diff options
author | Caveh Jalali <caveh@chromium.org> | 2018-10-11 20:07:41 -0700 |
---|---|---|
committer | chrome-bot <chrome-bot@chromium.org> | 2018-11-15 08:11:34 -0800 |
commit | 26e2bf4b2fe27d2cfcbb629c6a830dd0c979ad3b (patch) | |
tree | f7d6ed7e76c1bb515b03b9ba0ef11d49596cab75 | |
parent | b765350dd51299b6606a0c837ded1cd4700dd3fb (diff) | |
download | chrome-ec-26e2bf4b2fe27d2cfcbb629c6a830dd0c979ad3b.tar.gz |
atlas: clean up ROP PMIC registers
this replaces some ROP PMIC register magic numbers with their actual
names. corrected a few comments about the bits we're writing into
these registers along the way.
BUG=b:75070158
BRANCH=none
TEST=boots on atlas
Change-Id: If3be6b4c1d550d7e0770450e9f713282835656b5
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1278096
Commit-Ready: Caveh Jalali <caveh@google.com>
Tested-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
-rw-r--r-- | board/atlas/board.c | 45 | ||||
-rw-r--r-- | driver/pmic_bd99992gw.h | 6 |
2 files changed, 34 insertions, 17 deletions
diff --git a/board/atlas/board.c b/board/atlas/board.c index 242003e8ea..b0e945f3b8 100644 --- a/board/atlas/board.c +++ b/board/atlas/board.c @@ -270,8 +270,8 @@ static void board_report_pmic_fault(const char *str) uint32_t info; /* RESETIRQ1 -- Bit 4: VRFAULT */ - if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x8, &vrfault) - != EC_SUCCESS) + if (i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992, + BD99992GW_REG_RESETIRQ1, &vrfault) != EC_SUCCESS) return; if (!(vrfault & (1 << 4))) @@ -280,19 +280,24 @@ static void board_report_pmic_fault(const char *str) /* VRFAULT has occurred, print VRFAULT status bits. */ /* PWRSTAT1 */ - i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x16, &pwrstat1); + i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992, + BD99992GW_REG_PWRSTAT1, &pwrstat1); /* PWRSTAT2 */ - i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x17, &pwrstat2); + i2c_read8(I2C_PORT_PMIC, I2C_ADDR_BD99992, + BD99992GW_REG_PWRSTAT2, &pwrstat2); CPRINTS("PMIC VRFAULT: %s", str); CPRINTS("PMIC VRFAULT: PWRSTAT1=0x%02x PWRSTAT2=0x%02x", pwrstat1, pwrstat2); /* Clear all faults -- Write 1 to clear. */ - i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x8, (1 << 4)); - i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x16, pwrstat1); - i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x17, pwrstat2); + i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, + BD99992GW_REG_RESETIRQ1, (1 << 4)); + i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, + BD99992GW_REG_PWRSTAT1, pwrstat1); + i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, + BD99992GW_REG_PWRSTAT2, pwrstat2); /* * Status of the fault registers can be checked in the OS by looking at @@ -307,11 +312,12 @@ static void board_pmic_disable_slp_s0_vr_decay(void) /* * VCCIOCNT: * Bit 6 (0) - Disable decay of VCCIO on SLP_S0# assertion - * Bits 5:4 (00) - Nominal output voltage: 0.850V + * Bits 5:4 (11) - Nominal output voltage: 0.850V * Bits 3:2 (10) - VR set to AUTO on SLP_S0# de-assertion * Bits 1:0 (10) - VR set to AUTO operating mode */ - i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x30, 0x3a); + i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, + BD99992GW_REG_VCCIOCNT, 0x3a); /* * V18ACNT: @@ -320,16 +326,18 @@ static void board_pmic_disable_slp_s0_vr_decay(void) * Bits 3:2 (10) - VR set to AUTO on SLP_S0# de-assertion * Bits 1:0 (10) - VR set to AUTO operating mode */ - i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x34, 0x2a); + i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, + BD99992GW_REG_V18ACNT, 0x2a); /* * V085ACNT: * Bits 7:6 (00) - Disable low power mode on SLP_S0# assertion - * Bits 5:4 (11) - Nominal voltage 0.85V + * Bits 5:4 (10) - Nominal voltage 0.85V * Bits 3:2 (10) - VR set to AUTO on SLP_S0# de-assertion * Bits 1:0 (10) - VR set to AUTO operating mode */ - i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x38, 0x2a); + i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, + BD99992GW_REG_V085ACNT, 0x2a); } static void board_pmic_enable_slp_s0_vr_decay(void) @@ -337,11 +345,12 @@ static void board_pmic_enable_slp_s0_vr_decay(void) /* * VCCIOCNT: * Bit 6 (1) - Enable decay of VCCIO on SLP_S0# assertion - * Bits 5:4 (00) - Nominal output voltage: 0.850V + * Bits 5:4 (11) - Nominal output voltage: 0.850V * Bits 3:2 (10) - VR set to AUTO on SLP_S0# de-assertion * Bits 1:0 (10) - VR set to AUTO operating mode */ - i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x30, 0x7a); + i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, + BD99992GW_REG_VCCIOCNT, 0x7a); /* * V18ACNT: @@ -350,16 +359,18 @@ static void board_pmic_enable_slp_s0_vr_decay(void) * Bits 3:2 (10) - VR set to AUTO on SLP_S0# de-assertion * Bits 1:0 (10) - VR set to AUTO operating mode */ - i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x34, 0x6a); + i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, + BD99992GW_REG_V18ACNT, 0x6a); /* * V085ACNT: * Bits 7:6 (01) - Enable low power mode on SLP_S0# assertion - * Bits 5:4 (11) - Nominal voltage 0.85V + * Bits 5:4 (10) - Nominal voltage 0.85V * Bits 3:2 (10) - VR set to AUTO on SLP_S0# de-assertion * Bits 1:0 (10) - VR set to AUTO operating mode */ - i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x38, 0x6a); + i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, + BD99992GW_REG_V085ACNT, 0x6a); } void power_board_handle_host_sleep_event(enum host_sleep_event state) diff --git a/driver/pmic_bd99992gw.h b/driver/pmic_bd99992gw.h index 84fe4c2ab4..9275e3818f 100644 --- a/driver/pmic_bd99992gw.h +++ b/driver/pmic_bd99992gw.h @@ -11,7 +11,13 @@ #include "temp_sensor/bd99992gw.h" #define BD99992GW_REG_PWRSRCINT 0x04 +#define BD99992GW_REG_RESETIRQ1 0x08 #define BD99992GW_REG_PBCONFIG 0x14 +#define BD99992GW_REG_PWRSTAT1 0x16 +#define BD99992GW_REG_PWRSTAT2 0x17 +#define BD99992GW_REG_VCCIOCNT 0x30 +#define BD99992GW_REG_V18ACNT 0x34 +#define BD99992GW_REG_V100ACNT 0x37 #define BD99992GW_REG_V085ACNT 0x38 #define BD99992GW_REG_VRMODECTRL 0x3b #define BD99992GW_REG_DISCHGCNT2 0x3d |