diff options
| author | Hu, Hebo <hebo.hu@intel.com> | 2018-12-27 15:56:40 +0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2019-01-08 11:43:59 -0800 |
| commit | a3a17f0013e294b9b9496d78b9b2ab6cefa45270 (patch) | |
| tree | 9e0c2a02841c032bcfd224e0f402bf9ae701d4ef | |
| parent | 93cfa8be90891a8f264fdd559c1a38278a200554 (diff) | |
| download | chrome-ec-a3a17f0013e294b9b9496d78b9b2ab6cefa45270.tar.gz | |
ish/uart: fix wrong register address access in uart_tx_start()
void uart_tx_start(void)
{
...
if ( REG8(IER(id) & IER_TDRQ) )
return;
...
}
the expression 'REG8(IER(id) & IER_TDRQ)' is wrong,
'(IER(id) & IER_TDRQ)' is not a register address but a '0' value,
'0' address is a invalid address in ISH.
the correct expression of read IER register and check TDRQ bit
should be: 'REG8(IER(id)) & IER_TDRQ'.
BUG=b:122052562
BRANCH=none
TEST=tested on arcada
Change-Id: I811ce68ff17e197df83a8d44bffaa58799cbb3b6
Signed-off-by: Hu, Hebo <hebo.hu@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/1390942
Commit-Ready: Jett Rink <jettrink@chromium.org>
Tested-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
Reviewed-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
| -rw-r--r-- | chip/ish/uart.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/chip/ish/uart.c b/chip/ish/uart.c index 96a55f94c7..c1e974cb44 100644 --- a/chip/ish/uart.c +++ b/chip/ish/uart.c @@ -62,7 +62,7 @@ void uart_tx_start(void) enum UART_PORT id = ISH_DEBUG_UART; /* UART for ISH */ - if ( REG8(IER(id) & IER_TDRQ) ) + if (REG8(IER(id)) & IER_TDRQ) return; /* Do not allow deep sleep while transmit in progress */ |