npcx: lpc: don't set SHCFG[7:5] in the driver's initialization

In older Nuvoton EC chips (prior NPCX5), the Semaphore register is
mapped to offset 0 of the Shared RAM Window by default. We usually
disable it in the driver by setting SHCFG[7:6] both to 1 if we want to
disable the Semaphore mechanism. However, in NPCX5 and later chips,
this behavior is deprecated (the Semaphore register is not mapped to
offset 0 of the Shared RAM Window by default).
These bits (including bit 5) were removed. The driver should keep these
bits at their default state. Otherwise, the Semaphore mechanism may not
work as expected.

BRANCH=none
BUG=b:73018524
TEST=pass make buildall.
TEST=build and flash reef/grunt/yorp image, stress test the host command
and host event, no symptom occurs.

Change-Id: I63031f3957d0485f18fb8c4f1b13ad56c2dc5804
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/1383675
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>

1 files changed, 0 insertions, 2 deletions

diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c
index 2d4391583e..a86a5879ba 100644
--- a/chip/npcx/lpc.c
+++ b/chip/npcx/lpc.c
@@ -901,8 +901,6 @@ static void lpc_init(void)
 
 	/* Don't stall SHM transactions */
 	NPCX_SHM_CTL = NPCX_SHM_CTL & ~0x40;
-	/* Semaphore and Indirect access disable */
-	NPCX_SHCFG = 0xE0;
 	/* Disable Protect Win1&2*/
 	NPCX_WIN_WR_PROT(0) = 0;
 	NPCX_WIN_WR_PROT(1) = 0;