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authorMary Ruthven <mruthven@google.com>2019-02-07 17:02:54 -0800
committerMary Ruthven <mruthven@chromium.org>2019-02-11 23:33:58 +0000
commit52569e08985bb8406343835bb7134490f5b86b5c (patch)
tree2d04b2db85ba827af19e08d461e79620e1a5680f
parent2507a0c6b3ccbfd6c46abf128bbd099c73f50e87 (diff)
downloadchrome-ec-52569e08985bb8406343835bb7134490f5b86b5c.tar.gz
cr50: add mistral strap config
Mistral has a 1M PU on DIOA9 and a 5k PU on DIOA1. It needs to use PLT_RST_L and SPI. Add this to the board config table. BUG=b:124075760 BRANCH=cr50 TEST=Test on a mistral with the new straps. Make sure 0x41 is set in the board properties. Change-Id: Ie67610a39239fe2f86ead7e2643cb8bac16ef0d3 Signed-off-by: Mary Ruthven <mruthven@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/1461081 Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Namyoon Woo <namyoon@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Mary Ruthven <mruthven@chromium.org>
-rw-r--r--board/cr50/board.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/board/cr50/board.c b/board/cr50/board.c
index 36af6c0ffe..67908dc388 100644
--- a/board/cr50/board.c
+++ b/board/cr50/board.c
@@ -248,6 +248,12 @@ static struct board_cfg board_cfg_table[] = {
.board_properties = BOARD_SLAVE_CONFIG_SPI |
BOARD_USE_PLT_RESET,
},
+ /* Mistral: DI0A9 = 1M PU, DIOA1 = 5k PU */
+ {
+ .strap_cfg = 0x0B,
+ .board_properties = BOARD_SLAVE_CONFIG_SPI |
+ BOARD_USE_PLT_RESET,
+ },
/* I2C Variants: DIOA9 = 1M PD, DIOA1 = 1M PD */
/* Reef/Eve: DIOA12 = 5k PD, DIOA6 = 1M PU */
{