npcx7: introduce npcx7m7wc chip and refine memory layout of npcx7m7wb

This CL includes the following changes:
1. add CHIP_VARIANT_NPCX7M7WC in the npcx7 chip configuration files to
   define what (RAM, features...) is supported in npcx7m7wc.
2. add the chip id and chip revision id of npcx7m7wc.
3. re-organize the memory of npcx7m7wb from:
        current: 320 KB code RAM + 64 KB data RAM.
            to : 256 KB code RAM + 128 KB data RAM.
   The reason is that the extra 64 KB RAM is excepted to store the WoV
   voice data when it operates under RAM mode. Under the limitation of
   current memory layout, the 64 KB voice buffer is declared as const
   to force it allocated in the code section, which is strange.
   This can be fixed after changing the layout.

BRANCH=none
BUG=none
TEST=pass "make buildall"
TEST=with related CLs, change CHIP_VARIANT to npcx7m7wc in
board/npcx7_evb/build.mk; flash image in the internal testing board of
npcx7m7wc; make sure the EC can boot up; check the chip ID and chip
revision ID are correct by console command "version".
TEST=build npcx7m7wb image and test it on npcx7_evb, no symptom found.

Change-Id: I7533c1f5490e151571696ac615da2d0430827a78
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/1543062
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>

5 files changed, 27 insertions, 16 deletions

diff --git a/chip/npcx/config_chip-npcx7.h b/chip/npcx/config_chip-npcx7.h
index a932fa5836..fe88bc3016 100644
--- a/chip/npcx/config_chip-npcx7.h
+++ b/chip/npcx/config_chip-npcx7.h
@@ -20,14 +20,15 @@
 
 /* The optional hardware features depend on chip variant */
 #if defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) || \
-	defined(CHIP_VARIANT_NPCX7M6FC) || defined(CHIP_VARIANT_NPCX7M7WB)
+	defined(CHIP_VARIANT_NPCX7M6FC) || defined(CHIP_VARIANT_NPCX7M7WB) || \
+	defined(CHIP_VARIANT_NPCX7M7WC)
 #define NPCX_INT_FLASH_SUPPORT /* Internal flash support */
 #define NPCX_PSL_MODE_SUPPORT /* Power switch logic mode for ultra-low power */
 #define NPCX_EXT32K_OSC_SUPPORT /* External 32KHz crytal osc. input support */
 #endif
 
 #if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M6FC) || \
-	defined(CHIP_VARIANT_NPCX7M7WB)
+	defined(CHIP_VARIANT_NPCX7M7WB) || defined(CHIP_VARIANT_NPCX7M7WC)
 #define NPCX_UART_FIFO_SUPPORT
 /* Number of UART modules. */
 #define NPCX_SECOND_UART
@@ -36,7 +37,7 @@
 #define UART_MODULE_COUNT 1
 #endif
 
-#ifdef CHIP_VARIANT_NPCX7M7WB
+#if defined(CHIP_VARIANT_NPCX7M7WB) || defined(CHIP_VARIANT_NPCX7M7WC)
 #define NPCX_WOV_SUPPORT /* Audio front-end for Wake-on-Voice support */
 #endif
 
@@ -60,9 +61,17 @@
 /*****************************************************************************/
 /* Memory mapping */
 #define NPCX_BTRAM_SIZE    0x800 /* 2KB data ram used by booter. */
+
+#if defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) || \
+	defined(CHIP_VARIANT_NPCX7M6FC) || defined(CHIP_VARIANT_NPCX7M6G)
 #define CONFIG_RAM_BASE    0x200C0000 /* memory address of data ram */
 /* 62 KB data RAM + 2 KB BT RAM size */
 #define CONFIG_DATA_RAM_SIZE    0x00010000
+#elif defined(CHIP_VARIANT_NPCX7M7WB) || defined(CHIP_VARIANT_NPCX7M7WC)
+#define CONFIG_RAM_BASE    0x200B0000 /* memory address of data ram */
+/* 126 KB data RAM + 2 KB BT RAM size */
+#define CONFIG_DATA_RAM_SIZE    0x00020000
+#endif
 #define CONFIG_RAM_SIZE         (CONFIG_DATA_RAM_SIZE - NPCX_BTRAM_SIZE)
 /* no low power ram in npcx7 series */
 
@@ -73,10 +82,10 @@
 #define NPCX_PROGRAM_MEMORY_SIZE (192 * 1024)
 /* program memory base address for 192KB Code RAM (ie. 0x100C0000 - 192KB) */
 #define CONFIG_PROGRAM_MEMORY_BASE 0x10090000
-#elif defined(CHIP_VARIANT_NPCX7M7WB)
-/* 320 RAM for FW code */
-#define NPCX_PROGRAM_MEMORY_SIZE (320 * 1024)
-/* program memory base address for 320KB Code RAM (ie. 0x100C0000 - 320KB) */
+#elif defined(CHIP_VARIANT_NPCX7M7WB) || defined(CHIP_VARIANT_NPCX7M7WC)
+/* 256KB RAM for FW code */
+#define NPCX_PROGRAM_MEMORY_SIZE (256 * 1024)
+/* program memory base address for 256KB Code RAM (ie. 0x100B0000 - 256KB) */
 #define CONFIG_PROGRAM_MEMORY_BASE 0x10070000
 #else
 #error "Unsupported chip variant"
@@ -90,8 +99,8 @@
 #if (NPCX_RAM_SIZE != 0x40000)
 #error "Wrong memory mapping layout for NPCX7M6F"
 #endif
-#elif defined(CHIP_VARIANT_NPCX7M7WB)
-/* 384KB RAM in NPCX7M7WB */
+#elif defined(CHIP_VARIANT_NPCX7M7WB) || defined(CHIP_VARIANT_NPCX7M7WC)
+/* 384KB RAM in NPCX7M7WB/NPCX7M7WC */
 #if (NPCX_RAM_SIZE != 0x60000)
 #error "Wrong memory mapping layout for NPCX7M7W"
 #endif
diff --git a/chip/npcx/config_flash_layout.h b/chip/npcx/config_flash_layout.h
index 86891cd26d..3ed9af4bc3 100644
--- a/chip/npcx/config_flash_layout.h
+++ b/chip/npcx/config_flash_layout.h
@@ -31,7 +31,8 @@
 #define CONFIG_EC_WRITABLE_STORAGE_OFF   0x40000
 #define CONFIG_EC_WRITABLE_STORAGE_SIZE  0x40000
 #elif defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) || \
-	defined(CHIP_VARIANT_NPCX7M6FC) || defined(CHIP_VARIANT_NPCX7M6G)
+	defined(CHIP_VARIANT_NPCX7M6FC) || defined(CHIP_VARIANT_NPCX7M6G) || \
+	defined(CHIP_VARIANT_NPCX7M7WC)
 #define CONFIG_EC_PROTECTED_STORAGE_OFF  0
 #define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x40000
 #define CONFIG_EC_WRITABLE_STORAGE_OFF   0x40000
diff --git a/chip/npcx/registers.h b/chip/npcx/registers.h
index c13395eaa4..56b0bd3563 100644
--- a/chip/npcx/registers.h
+++ b/chip/npcx/registers.h
@@ -954,11 +954,11 @@ enum {
 #define NPCX_PWDWN_CTL7_SMB6_PD          1
 #define NPCX_PWDWN_CTL7_SMB7_PD          2
 #if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M6FC) || \
-	defined(CHIP_VARIANT_NPCX7M7WB)
+	defined(CHIP_VARIANT_NPCX7M7WB) || defined(CHIP_VARIANT_NPCX7M7WC)
 #define NPCX_PWDWN_CTL7_ITIM64_PD        5
 #define NPCX_PWDWN_CTL7_UART2_PD         6
 #endif
-#ifdef CHIP_VARIANT_NPCX7M7WB
+#if defined(CHIP_VARIANT_NPCX7M7WB) || defined(CHIP_VARIANT_NPCX7M7WC)
 #define NPCX_PWDWN_CTL7_WOV_PD           7
 #endif
 #endif
@@ -1238,7 +1238,7 @@ enum PM_CHANNEL_T {
 /* BBRAM register fields */
 #define NPCX_BKUP_STS_IBBR               7
 #if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M6FC) || \
-	defined(CHIP_VARIANT_NPCX7M7WB)
+	defined(CHIP_VARIANT_NPCX7M7WB) || defined(CHIP_VARIANT_NPCX7M7WC)
 #define NPCX_BKUP_STS_VSBY_STS           1
 #define NPCX_BKUP_STS_VCC1_STS           0
 #define NPCX_BKUP_STS_ALL_MASK \
diff --git a/chip/npcx/system.c b/chip/npcx/system.c
index 4b2f55ddb4..009dd49017 100644
--- a/chip/npcx/system.c
+++ b/chip/npcx/system.c
@@ -101,7 +101,7 @@ void system_check_bbram_on_reset(void)
 		/*
 		 * npcx5/npcx7m6g/npcx7m6f:
 		 *   Clear IBBR bit
-		 * npcx7m6fb/npcx7m6fc/npcx7m7wb:
+		 * npcx7m6fb/npcx7m6fc/npcx7m7wb/npcx7m7wc:
 		 *   Clear IBBR/VSBY_STS/VCC1_STS bit
 		 */
 		NPCX_BKUP_STS = NPCX_BKUP_STS_ALL_MASK;
@@ -702,7 +702,7 @@ void system_pre_init(void)
 
 #if defined(CHIP_FAMILY_NPCX7)
 #if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M6FC) || \
-	defined(CHIP_VARIANT_NPCX7M7WB)
+	defined(CHIP_VARIANT_NPCX7M7WB) || defined(CHIP_VARIANT_NPCX7M7WC)
 	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_7) = 0xE7;
 #else
 	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_7) = 0x07;
@@ -817,6 +817,7 @@ const char *system_get_chip_name(void)
 	case 0x29:
 		return "NPCX796F";
 	case 0x24:
+	case 0x2C:
 		return "NPCX797W";
 #endif
 	default:
diff --git a/chip/npcx/wov.c b/chip/npcx/wov.c
index 3bbeee90a0..15d442a142 100644
--- a/chip/npcx/wov.c
+++ b/chip/npcx/wov.c
@@ -171,7 +171,7 @@ struct wov_config wov_conf;
 static struct wov_cfifo_buf cfifo_buf;
 static wov_call_back_t callback_fun;
 
-const uint32_t voice_buffer[VOICE_BUF_SIZE] = {0};
+static uint32_t voice_buffer[VOICE_BUF_SIZE] = {0};
 
 #define WOV_RATE_ERROR_THRESH_MSEC 10
 #define WOV_RATE_ERROR_THRESH 5