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| author | Nicolas Norvez <norvez@chromium.org> | 2019-02-21 12:02:15 -0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2019-04-03 18:13:41 -0700 |
| commit | 204eb153327c59688fb430eb51471a76ecc61dee (patch) | |
| tree | e0d69f323cfb48a1ab5f700292c5e7f7c2e0f610 | |
| parent | 198e32b42853a507d1482766a6b8c96731038c59 (diff) | |
| download | chrome-ec-204eb153327c59688fb430eb51471a76ecc61dee.tar.gz | |
stm32f412: add TRNG support
No need to set up the TRNG's clock, on STM32F4 it always uses the PLL's
output that is set on boot.
BRANCH=None
BUG=b:124770147
TEST=hatch_fp builds. STM32F412's TRNG is not used on other projects.
Change-Id: Ie1f268137ee9a3a76cd0350e3ea5b2e85def1b76
Signed-off-by: Nicolas Norvez <norvez@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1481653
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
| -rw-r--r-- | chip/stm32/registers.h | 1 | ||||
| -rw-r--r-- | chip/stm32/trng.c | 7 |
2 files changed, 8 insertions, 0 deletions
diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h index e9067b5620..a6c9636098 100644 --- a/chip/stm32/registers.h +++ b/chip/stm32/registers.h @@ -1375,6 +1375,7 @@ typedef volatile struct timer_ctlr timer_ctlr_t; #define STM32_RCC_AHB1ENR_OTGHSULPIEN BIT(30) #define STM32_RCC_AHB2ENR REG32(STM32_RCC_BASE + 0x34) +#define STM32_RCC_AHB2ENR_RNGEN BIT(6) #define STM32_RCC_AHB2ENR_OTGFSEN BIT(7) #define STM32_RCC_AHB3ENR REG32(STM32_RCC_BASE + 0x38) diff --git a/chip/stm32/trng.c b/chip/stm32/trng.c index 7799c03f93..8ef7b891a7 100644 --- a/chip/stm32/trng.c +++ b/chip/stm32/trng.c @@ -68,6 +68,11 @@ void init_trng(void) STM32_RCC_D2CCIP2R = (STM32_RCC_D2CCIP2R & ~STM32_RCC_D2CCIP2_RNGSEL_MASK) | STM32_RCC_D2CCIP2_RNGSEL_HSI48; +#elif defined(CHIP_FAMILY_STM32F4) + /* + * The RNG clock is the same as the SDIO/USB OTG clock, already set at + * 48 MHz during clock initialisation. Nothing to do. + */ #else #error "Please add support for CONFIG_RNG on this chip family." #endif @@ -85,6 +90,8 @@ void exit_trng(void) STM32_RCC_CRRCR &= ~STM32_RCC_CRRCR_HSI48ON; #elif defined(CHIP_FAMILY_STM32H7) STM32_RCC_CR &= ~STM32_RCC_CR_HSI48ON; +#elif defined(CHIP_FAMILY_STM32F4) + /* Nothing to do */ #endif } |