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| author | Jett Rink <jettrink@chromium.org> | 2019-05-07 15:31:48 -0600 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2019-05-16 15:18:16 +0000 |
| commit | 38ef93d760f40c0b919ac2f861a51ba49e67c21f (patch) | |
| tree | 2334eb35915b02cf02dc654d422df4a8c6ab2624 | |
| parent | 89be8de4362b2615c385dd2bc21110749d17f841 (diff) | |
| download | chrome-ec-38ef93d760f40c0b919ac2f861a51ba49e67c21f.tar.gz | |
ish: fix lapic table read
When we switched to using REG32 macros for registers, we also changed
the math for the offset of the lapic. Fixing the pointer math.
The original CL that changed this was CL:1586458
BRANCH=ish
BUG=none
TEST=ISH runs normally
Change-Id: I1beea99ede496a2eee2adf96adeec21b3f1e1fd4
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1600158
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1615484
| -rw-r--r-- | chip/ish/registers.h | 2 | ||||
| -rw-r--r-- | core/minute-ia/interrupts.c | 12 |
2 files changed, 9 insertions, 5 deletions
diff --git a/chip/ish/registers.h b/chip/ish/registers.h index b1ead77818..15321c6d83 100644 --- a/chip/ish/registers.h +++ b/chip/ish/registers.h @@ -301,7 +301,7 @@ enum ish_i2c_port { #define IOAPIC_EOI_REG REG32(IOAPIC_EOI_REG_ADDR) #define IOAPIC_VERSION (0x1) -#define IOAPIC_IOREDTBL (0x10) +#define IOAPIC_IOREDTBL (0x10) #define IOAPIC_REDTBL_DELMOD_FIXED (0x00000000) #define IOAPIC_REDTBL_DESTMOD_PHYS (0x00000000) #define IOAPIC_REDTBL_INTPOL_HIGH (0x00000000) diff --git a/core/minute-ia/interrupts.c b/core/minute-ia/interrupts.c index 5e69b9c199..8fc5b2f9e9 100644 --- a/core/minute-ia/interrupts.c +++ b/core/minute-ia/interrupts.c @@ -26,19 +26,19 @@ extern struct idt_entry __idt[NUM_VECTORS]; /* To count the interrupt nesting depth. Usually it is not nested */ volatile uint32_t __in_isr; -void write_ioapic_reg(const uint8_t reg, const uint32_t val) +static void write_ioapic_reg(const uint32_t reg, const uint32_t val) { IOAPIC_IDX = reg; IOAPIC_WDW = val; } -uint32_t read_ioapic_reg(const uint8_t reg) +static uint32_t read_ioapic_reg(const uint32_t reg) { IOAPIC_IDX = reg; return IOAPIC_WDW; } -void set_ioapic_redtbl_raw(const uint32_t irq, const uint32_t val) +static void set_ioapic_redtbl_raw(const uint32_t irq, const uint32_t val) { const uint32_t redtbl_lo = IOAPIC_IOREDTBL + 2 * irq; const uint32_t redtbl_hi = redtbl_lo + 1; @@ -280,7 +280,11 @@ DECLARE_DEFERRED(print_lpaic_lvt_error); static inline unsigned int lapic_get_vector(volatile uint32_t *reg_base, uint32_t vector) { - uint32_t reg_pos = (vector >> 5) << 4; + /* + * Since we are using array indexing, we need to divide the vec_pos by + * sizeof(uint32_t), i.e. shift to the right 2. + */ + uint32_t reg_pos = (vector >> 5) << 2; uint32_t vec_pos = vector & (32 - 1); return reg_base[reg_pos] & BIT(vec_pos); |