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authorJett Rink <jettrink@chromium.org>2019-05-08 13:23:29 -0600
committerJett Rink <jettrink@chromium.org>2019-05-14 19:55:18 +0000
commit1fa9dc3e2e8a2771a854657e0441128a9a119dbc (patch)
treeb0d03d717416d30850a4db737971a3ea99042e7b
parent903a7b1f98b4e71c7f171c747df12d193d7cd86c (diff)
downloadchrome-ec-1fa9dc3e2e8a2771a854657e0441128a9a119dbc.tar.gz
ish: add more explanations comments for reset flow in aontask
BRANCH=none BUG=none TEST=ISH still reset properly on arcada Change-Id: I08a5935c5e8d1728e2984cbc70d75e380eb66f55 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1601349 Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
-rw-r--r--chip/ish/aontaskfw/ish_aontask.c32
1 files changed, 29 insertions, 3 deletions
diff --git a/chip/ish/aontaskfw/ish_aontask.c b/chip/ish/aontaskfw/ish_aontask.c
index 7c0809b4a2..fc584857b1 100644
--- a/chip/ish/aontaskfw/ish_aontask.c
+++ b/chip/ish/aontaskfw/ish_aontask.c
@@ -558,8 +558,33 @@ static void handle_reset(int pm_state)
sram_power(0);
while (1) {
-
- /* check if host ish driver already set the DMA enable flag */
+ /**
+ * check if host ish driver already set the DMA enable flag
+ *
+ * ISH FW and ISH ipc host driver using IPC_ISH_RMP2 register
+ * for synchronization during ISH boot.
+ * ISH ipc host driver will set DMA_ENABLED_MASK bit when it
+ * is loaded and starts, and clear this bit when it is removed.
+ *
+ * see: https://github.com/torvalds/linux/blob/master/drivers/
+ * hid/intel-ish-hid/ipc/ipc.c
+ *
+ * we have two kinds of reset situations need to handle here:
+ * 1: reset ISH via uart console cmd or ectool host cmd
+ * 2: S0 -> Sx (reset_prep interrupt)
+ *
+ * for #1, ISH ipc host driver no changed states,
+ * DMA_ENABLED_MASK bit always set, so, will reset ISH directly
+ *
+ * for #2, ISH ipc host driver changed states, and cleared
+ * DMA_ENABLED_MASK bit, then ISH FW received reset_prep
+ * interrupt, ISH will stay in this while loop (most time in
+ * halt state), waiting for DMA_ENABLED_MASK bit was set and
+ * reset ISH then. Since ISH ROM have no power managment, stay
+ * in aontask can save more power especially if system stay in
+ * Sx for long time.
+ *
+ */
if (IPC_ISH_RMP2 & DMA_ENABLED_MASK) {
/* clear ISH2HOST doorbell register */
@@ -570,12 +595,13 @@ static void handle_reset(int pm_state)
/* reset ISH minute-ia cpu core, will goto ISH ROM */
ish_mia_reset();
+
+ __builtin_unreachable();
}
ish_mia_halt();
}
- __builtin_unreachable();
}
static void handle_unknown_state(void)