diff options
| author | Nicolas Boichat <drinkcat@chromium.org> | 2019-06-21 19:41:58 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2019-06-24 06:45:19 +0000 |
| commit | b2c271b54eb87795d21b71c0c6784c89d9e26346 (patch) | |
| tree | 5b915999dcb627bb799837d67e1c5665839504d1 | |
| parent | ca5beb84948426fb8b84d2932a9ce272284c9359 (diff) | |
| download | chrome-ec-b2c271b54eb87795d21b71c0c6784c89d9e26346.tar.gz | |
chip/mt_scp/hrtimer: Switch hrtimer to use ULPOSC1/8
To be able to use the SCP in S3, we cannot rely on the 26Mhz clock,
as it's off in S3. Switch to using ULPOSC1 divided by 8 instead.
Also, make sure the frequency is a multiple of 8Mhz for the timer to
be accurate.
BRANCH=none
BUG=b:134035444
TEST=make BOARD=kukui_scp -j && \
bash board/kukui_scp/update_scp $IP
powerd_dbus_suspend
Change-Id: I048431cc062040caea70a5de3709ddd33550439c
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1672645
Reviewed-by: Yilun Lin <yllin@chromium.org>
| -rw-r--r-- | chip/mt_scp/clock_chip.h | 2 | ||||
| -rw-r--r-- | chip/mt_scp/hrtimer.c | 18 | ||||
| -rw-r--r-- | chip/mt_scp/registers.h | 6 |
3 files changed, 18 insertions, 8 deletions
diff --git a/chip/mt_scp/clock_chip.h b/chip/mt_scp/clock_chip.h index fe27d5914f..3eb02ed1ef 100644 --- a/chip/mt_scp/clock_chip.h +++ b/chip/mt_scp/clock_chip.h @@ -13,7 +13,7 @@ /* Default ULPOSC clock speed in MHz */ #ifndef ULPOSC1_CLOCK_MHZ -#define ULPOSC1_CLOCK_MHZ 250 +#define ULPOSC1_CLOCK_MHZ 248 #endif #ifndef ULPOSC2_CLOCK_MHZ #define ULPOSC2_CLOCK_MHZ 330 diff --git a/chip/mt_scp/hrtimer.c b/chip/mt_scp/hrtimer.c index 23d260faf4..f970af6eb5 100644 --- a/chip/mt_scp/hrtimer.c +++ b/chip/mt_scp/hrtimer.c @@ -7,11 +7,13 @@ * High-res hardware timer * * SCP hardware 32bit count down timer can be configured to source clock from - * 32KHz, 26MHz, BCLK or PCLK. This implementation selects 26MHz frequency - * countdown and converts to micro second value matching common timer. + * 32KHz, 26MHz, BCLK or PCLK. This implementation selects BCLK (ULPOSC1/8) as a + * source, countdown mode and converts to micro second value matching common + * timer. */ #include "clock.h" +#include "clock_chip.h" #include "common.h" #include "console.h" #include "hooks.h" @@ -27,7 +29,9 @@ #define TIMER_SYSTEM 5 #define TIMER_EVENT 3 -#define TIMER_CLOCK_MHZ 26 +/* ULPOSC1 should be a multiple of 8. */ +BUILD_ASSERT((ULPOSC1_CLOCK_MHZ % 8) == 0); +#define TIMER_CLOCK_MHZ (ULPOSC1_CLOCK_MHZ / 8) /* Common timer overflows at 0x100000000 micro seconds */ #define OVERFLOW_TICKS (TIMER_CLOCK_MHZ * 0x100000000 - 1) @@ -174,14 +178,16 @@ int __hw_clock_source_init(uint32_t start_t) /* Turn on OS TIMER, tick at 13MHz */ SCP_OSTIMER_CON |= 1; - /* System timestamp timer */ - timer_set_clock(TIMER_SYSTEM, TIMER_CLK_26M); + /* System timestamp timer from BCLK (sourced from ULPOSC) */ + SCP_CLK_BCLK = CLK_BCLK_SEL_ULPOSC1_DIV8; + + timer_set_clock(TIMER_SYSTEM, TIMER_CLK_BCLK); sys_high = TIMER_CLOCK_MHZ-1; timer_set_reset_value(TIMER_SYSTEM, 0xffffffff); __hw_timer_enable_clock(TIMER_SYSTEM, 1); task_enable_irq(IRQ_TIMER(TIMER_SYSTEM)); /* Event tick timer */ - timer_set_clock(TIMER_EVENT, TIMER_CLK_26M); + timer_set_clock(TIMER_EVENT, TIMER_CLK_BCLK); task_enable_irq(IRQ_TIMER(TIMER_EVENT)); return IRQ_TIMER(TIMER_SYSTEM); diff --git a/chip/mt_scp/registers.h b/chip/mt_scp/registers.h index 17b40baf77..a21385edf2 100644 --- a/chip/mt_scp/registers.h +++ b/chip/mt_scp/registers.h @@ -327,7 +327,11 @@ #define WAKE_CKSW_SEL_SLOW_MASK 0x30 #define WAKE_CKSW_SEL_SLOW_DEFAULT 0x10 #define SCP_CLK_UART REG32(SCP_CLK_BASE + 0x44) -#define SCP_CLK_BCK REG32(SCP_CLK_BASE + 0x48) +#define SCP_CLK_BCLK REG32(SCP_CLK_BASE + 0x48) +#define CLK_BCLK_SEL_MASK 0x3 +#define CLK_BCLK_SEL_SYS_DIV8 0x0 +#define CLK_BCLK_SEL_32K 0x1 +#define CLK_BCLK_SEL_ULPOSC1_DIV8 0x2 #define SCP_CLK_SPI_BCK REG32(SCP_CLK_BASE + 0x4C) #define SCP_CLK_DIV_CNT REG32(SCP_CLK_BASE + 0x50) #define SCP_CPU_VREQ REG32(SCP_CLK_BASE + 0x54) |