diff options
| author | Nicolas Boichat <drinkcat@chromium.org> | 2019-06-13 12:30:41 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2019-06-14 09:00:39 +0000 |
| commit | eb13a9379f7c44f2ef4a67a2e60cbe2610a06b6a (patch) | |
| tree | 49a44ec08e4bd8f3ca717164355a79415bdeeba9 | |
| parent | b5c6cf246deb0ade98bf3e84999984998b67267e (diff) | |
| download | chrome-ec-eb13a9379f7c44f2ef4a67a2e60cbe2610a06b6a.tar.gz | |
chip/mt_scp: Fix clock selection register values for ULPOSC_1/2
Values were incorrect, previously.
BRANCH=none
BUG=b:125616659
TEST=See bug. With CL:1475091, cycle count/time actually matches
the expected frequency.
Change-Id: Icdca1809dc202d527b708ce3df7ea19ac7f60532
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1657080
Reviewed-by: Yilun Lin <yllin@chromium.org>
| -rw-r--r-- | chip/mt_scp/registers.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/chip/mt_scp/registers.h b/chip/mt_scp/registers.h index e6bcbecac3..53a40ab7c8 100644 --- a/chip/mt_scp/registers.h +++ b/chip/mt_scp/registers.h @@ -244,8 +244,8 @@ #define SCP_CLK_SEL REG32(SCP_CLK_BASE) #define CLK_SEL_SYS_26M 0 #define CLK_SEL_32K 1 -#define CLK_SEL_ULPOSC_1 2 -#define CLK_SEL_ULPOSC_2 3 +#define CLK_SEL_ULPOSC_2 2 +#define CLK_SEL_ULPOSC_1 3 #define SCP_CLK_EN REG32(SCP_CLK_BASE + 0x04) #define EN_CLK_SYS BIT(0) /* System clock */ @@ -275,8 +275,8 @@ #define CKSW_SEL_SLOW_DIV_MASK 0x30 #define CKSW_SEL_SLOW_SYS_CLK 0 #define CKSW_SEL_SLOW_32K_CLK 1 -#define CKSW_SEL_SLOW_ULPOSC1_CLK 2 -#define CKSW_SEL_SLOW_ULPOSC2_CLK 3 +#define CKSW_SEL_SLOW_ULPOSC2_CLK 2 +#define CKSW_SEL_SLOW_ULPOSC1_CLK 3 /* * Sleep mode control. * VREQ_COUNT[7:1] Number of cycles to wait when requesting PMIC to raise the |