diff options
| author | Dino Li <Dino.Li@ite.com.tw> | 2019-07-02 16:04:18 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2019-07-03 03:44:29 +0000 |
| commit | fc9117badbc12cf2eda57287aff0315028cbf210 (patch) | |
| tree | ed72cf613ff33cb96b68881119ea051e5de0009f | |
| parent | d2bee5b58542c40abbd66fde8e551823ed8cc64e (diff) | |
| download | chrome-ec-fc9117badbc12cf2eda57287aff0315028cbf210.tar.gz | |
it83xx/register: rename the register of MCCR3 to RVILMCR0
This register is specific to the risc-v core.
We only apply the register to risc-v core.
BUG=none
BRANCH=none
TEST=console commands: flasherase and flashwrite
Change-Id: I241179170ca1394dca4f7631b266a57f959fe036
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1684955
Reviewed-by: Jett Rink <jettrink@chromium.org>
| -rw-r--r-- | chip/it83xx/flash.c | 8 | ||||
| -rw-r--r-- | chip/it83xx/registers.h | 2 |
2 files changed, 5 insertions, 5 deletions
diff --git a/chip/it83xx/flash.c b/chip/it83xx/flash.c index 658819a193..cae6eced7c 100644 --- a/chip/it83xx/flash.c +++ b/chip/it83xx/flash.c @@ -568,16 +568,16 @@ static void flash_code_static_dma(void) interrupt_disable(); /* invalid static DMA first */ - if (IS_ENABLED(CHIP_ILM_DLM_ORDER)) - IT83XX_GCTRL_MCCR3 &= ~ILMCR_ILM2_ENABLE; + if (IS_ENABLED(CHIP_CORE_RISCV)) + IT83XX_GCTRL_RVILMCR0 &= ~ILMCR_ILM2_ENABLE; IT83XX_SMFI_SCAR2H = 0x08; /* Copy to DLM */ IT83XX_GCTRL_MCCR2 |= 0x20; memcpy((void *)CHIP_RAMCODE_BASE, (const void *)FLASH_DMA_START, IT83XX_ILM_BLOCK_SIZE); - if (IS_ENABLED(CHIP_ILM_DLM_ORDER)) - IT83XX_GCTRL_MCCR3 |= ILMCR_ILM2_ENABLE; + if (IS_ENABLED(CHIP_CORE_RISCV)) + IT83XX_GCTRL_RVILMCR0 |= ILMCR_ILM2_ENABLE; IT83XX_GCTRL_MCCR2 &= ~0x20; /* diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h index 077bd794cf..52e6c3b43c 100644 --- a/chip/it83xx/registers.h +++ b/chip/it83xx/registers.h @@ -790,7 +790,7 @@ enum clock_gate_offsets { #define IT83XX_GCTRL_MCCR2 REG8(IT83XX_GCTRL_BASE+0x44) #define IT83XX_GCTRL_SSCR REG8(IT83XX_GCTRL_BASE+0x4A) #define IT83XX_GCTRL_ETWDUARTCR REG8(IT83XX_GCTRL_BASE+0x4B) -#define IT83XX_GCTRL_MCCR3 REG8(IT83XX_GCTRL_BASE+0x5D) +#define IT83XX_GCTRL_RVILMCR0 REG8(IT83XX_GCTRL_BASE+0x5D) #define ILMCR_ILM2_ENABLE BIT(2) #define IT83XX_GCTRL_EWPR0PFH(i) REG8(IT83XX_GCTRL_BASE+0x60+i) #define IT83XX_GCTRL_EWPR0PFD(i) REG8(IT83XX_GCTRL_BASE+0xA0+i) |