summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorNicolas Boichat <drinkcat@chromium.org>2019-06-21 19:48:34 +0800
committerCommit Bot <commit-bot@chromium.org>2019-06-25 14:56:07 +0000
commitf60a2d53226aeda2d8e3cabfa05457ee337ef15a (patch)
tree55673b91ecdcb14588a183b6496870cd29973e16
parenta6b5c0b7b986aa8221c501299d1b595fc7514d21 (diff)
downloadchrome-ec-f60a2d53226aeda2d8e3cabfa05457ee337ef15a.tar.gz
chip/mt_scp/uart: Switch to use ULPOSC1_DIV10 for UART
The 26Mhz clock is not available in S3, so use ULPOSC-sourced clock for the SCP in suspend. Also, change ULPOSC1 frequency to 240 Mhz, as this allows for a better division of the clock to get 115200 bps: - 240*1000*1000/10/(115200*16.0) => 13.02 <<< lowest error - 248*1000*1000/10/(115200*16.0) => 13.45 - 256*1000*1000/10/(115200*16.0) => 13.89 - 264*1000*1000/10/(115200*16.0) => 14.32 BRANCH=none BUG=b:134035444 TEST=make BOARD=kukui_scp -j && \ bash board/kukui_scp/update_scp $IP powerd_dbus_suspend TEST=Can interract with console SCP in suspend. TEST=Measure UART frequency with an oscilloscope: 115.7 kHz Change-Id: I3bce4e94abaa97e20bef70f4f3ef3ca4e01d57b5 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1672646 Reviewed-by: Yilun Lin <yllin@chromium.org>
-rw-r--r--chip/mt_scp/clock_chip.h2
-rw-r--r--chip/mt_scp/registers.h10
-rw-r--r--chip/mt_scp/uart.c11
3 files changed, 21 insertions, 2 deletions
diff --git a/chip/mt_scp/clock_chip.h b/chip/mt_scp/clock_chip.h
index 3eb02ed1ef..ab03d5c2f6 100644
--- a/chip/mt_scp/clock_chip.h
+++ b/chip/mt_scp/clock_chip.h
@@ -13,7 +13,7 @@
/* Default ULPOSC clock speed in MHz */
#ifndef ULPOSC1_CLOCK_MHZ
-#define ULPOSC1_CLOCK_MHZ 248
+#define ULPOSC1_CLOCK_MHZ 240
#endif
#ifndef ULPOSC2_CLOCK_MHZ
#define ULPOSC2_CLOCK_MHZ 330
diff --git a/chip/mt_scp/registers.h b/chip/mt_scp/registers.h
index a21385edf2..608efcc17b 100644
--- a/chip/mt_scp/registers.h
+++ b/chip/mt_scp/registers.h
@@ -327,6 +327,16 @@
#define WAKE_CKSW_SEL_SLOW_MASK 0x30
#define WAKE_CKSW_SEL_SLOW_DEFAULT 0x10
#define SCP_CLK_UART REG32(SCP_CLK_BASE + 0x44)
+#define CLK_UART_SEL_MASK 0x3
+#define CLK_UART_SEL_26M 0x0
+#define CLK_UART_SEL_32K 0x1
+/* This is named ulposc_div_to_26m in datasheet */
+#define CLK_UART_SEL_ULPOSC1_DIV10 0x2
+#define CLK_UART1_SEL_MASK (0x3 << 16)
+#define CLK_UART1_SEL_26M (0x0 << 16)
+#define CLK_UART1_SEL_32K (0x1 << 16)
+/* This is named ulposc_div_to_26m in datasheet */
+#define CLK_UART1_SEL_ULPOSC1_DIV10 (0x2 << 16)
#define SCP_CLK_BCLK REG32(SCP_CLK_BASE + 0x48)
#define CLK_BCLK_SEL_MASK 0x3
#define CLK_BCLK_SEL_SYS_DIV8 0x0
diff --git a/chip/mt_scp/uart.c b/chip/mt_scp/uart.c
index 8717d74704..78ea594c6b 100644
--- a/chip/mt_scp/uart.c
+++ b/chip/mt_scp/uart.c
@@ -5,6 +5,7 @@
/* SCP UART module */
+#include "clock_chip.h"
#include "console.h"
#include "registers.h"
#include "serial_reg.h"
@@ -134,13 +135,21 @@ void uart_task(void)
void uart_init(void)
{
const uint32_t baud_rate = CONFIG_UART_BAUD_RATE;
- const uint32_t uart_clock = 26000000;
+ /*
+ * UART clock source is set to ULPOSC1 / 10 below.
+ *
+ * TODO(b:134035444): We could get slightly more precise frequency by
+ * using the _measured_ ULPOSC1 frequency (instead of the target).
+ */
+ const uint32_t uart_clock = ULPOSC1_CLOCK_MHZ * 1000 / 10 * 1000;
const uint32_t div = DIV_ROUND_NEAREST(uart_clock, baud_rate * 16);
/* Init clock */
#if UARTN == 0
+ SCP_CLK_UART = CLK_UART_SEL_ULPOSC1_DIV10;
SCP_CLK_GATE |= CG_UART_M | CG_UART_B | CG_UART_RSTN;
#elif UARTN == 1
+ SCP_CLK_UART = CLK_UART1_SEL_ULPOSC1_DIV10;
SCP_CLK_GATE |= CG_UART1_M | CG_UART1_B | CG_UART1_RSTN;
#endif