power: add chipset_in_or_transitioning_to_state

We need a method that we can call from the chipset notify hooks that can
clearly distinguish which state you are about to be in. This is made
evident by the child CL for putting a MUX into low power mode in S5.
Without this method, we have to put chipset state into the PD task
variable and use that instead (since chipset_in_state won't work because
we are in the S3S5 state)

BRANCH=none
BUG=b:112136208,b:111196155,chromium:736508
TEST=On Phaser the 3300_pd_a drops from 92mW to 32 mW when the charger
is plugged into C1 and the SoC is in S5. The rail also says at 32mW
after
removing and plugging the power back in while the SoC is in S5. Also
ensured that power is low upon first insertion and AP does not come on
automatically.

Change-Id: I93cce2aa319c9689efce222919e5389471001a00
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1211368
Reviewed-by: Justin TerAvest <teravest@chromium.org>

2 files changed, 43 insertions, 0 deletions

diff --git a/include/chipset.h b/include/chipset.h
index 0e568dccd6..fae0d4e3da 100644
--- a/include/chipset.h
+++ b/include/chipset.h
@@ -112,6 +112,18 @@ enum chipset_shutdown_reason {
 int chipset_in_state(int state_mask);
 
 /**
+ * Check if chipset is in a given state or if the chipset task is currently
+ * transitioning to that state. For example, G3S5, S5, and S3S5 would all count
+ * as the S5 state.
+ *
+ * @param state_mask	Combination of one or more CHIPSET_STATE_* flags.
+ *
+ * @return non-zero if the chipset is in one of the states specified in the
+ * mask.
+ */
+int chipset_in_or_transitioning_to_state(int state_mask);
+
+/**
  * Ask the chipset to exit the hard off state.
  *
  * Does nothing if the chipset has already left the state, or was not in the
diff --git a/power/common.c b/power/common.c
index 718607f25c..ddbfaebded 100644
--- a/power/common.c
+++ b/power/common.c
@@ -405,6 +405,37 @@ int chipset_in_state(int state_mask)
 	return (state_mask & need_mask) == need_mask;
 }
 
+int chipset_in_or_transitioning_to_state(int state_mask)
+{
+	switch (state) {
+	case POWER_G3:
+	case POWER_S5G3:
+		return state_mask & CHIPSET_STATE_HARD_OFF;
+	case POWER_S5:
+	case POWER_G3S5:
+	case POWER_S3S5:
+		return state_mask & CHIPSET_STATE_SOFT_OFF;
+	case POWER_S3:
+	case POWER_S5S3:
+	case POWER_S0S3:
+		return state_mask & CHIPSET_STATE_SUSPEND;
+#ifdef CONFIG_POWER_S0IX
+	case POWER_S0ix:
+	case POWER_S0S0ix:
+		return state_mask & CHIPSET_STATE_STANDBY;
+#endif
+	case POWER_S0:
+	case POWER_S3S0:
+#ifdef CONFIG_POWER_S0IX
+	case POWER_S0ixS0:
+#endif
+		return state_mask & CHIPSET_STATE_ON;
+	}
+
+	/* Unknown power state; return false. */
+	return 0;
+}
+
 void chipset_exit_hard_off(void)
 {
 	/*