diff options
| author | Diana Z <dzigterman@chromium.org> | 2018-12-11 14:17:33 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-12-12 17:04:55 -0800 |
| commit | e95e95a0007fa8e69a002f551c31aee34ae94574 (patch) | |
| tree | 1d5cb381013c7bf2f0db4c189aa35ed1913b78e6 | |
| parent | c65597299e493ac5bbbc668c1fcb4d0530c0b070 (diff) | |
| download | chrome-ec-e95e95a0007fa8e69a002f551c31aee34ae94574.tar.gz | |
Octopus: add mux reset when applicable
The ITE based octopus boards have a PS8751 acting as a USB mux on at
least one port. Since these boards have GPIOs hooked up to the PS8751
reset pin(s), we should reset the chips on startup. This should help
in rare error cases, for example if the chip is hung up.
BUG=b:120087080
BRANCH=octopus
TEST=loaded onto apel board version 0, ran several EC reboots and
verified the DB USB-C and USB-A ports functioned well
Change-Id: I04279e5e12996deedf4d22b2be2aa2f9909f4852
Signed-off-by: Diana Z <dzigterman@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1372028
Reviewed-by: Jett Rink <jettrink@chromium.org>
| -rw-r--r-- | baseboard/octopus/variant_usbc_ec_tcpcs.c | 17 | ||||
| -rw-r--r-- | board/bip/gpio.inc | 2 |
2 files changed, 13 insertions, 6 deletions
diff --git a/baseboard/octopus/variant_usbc_ec_tcpcs.c b/baseboard/octopus/variant_usbc_ec_tcpcs.c index cb137ee06f..35365e232b 100644 --- a/baseboard/octopus/variant_usbc_ec_tcpcs.c +++ b/baseboard/octopus/variant_usbc_ec_tcpcs.c @@ -118,17 +118,24 @@ uint16_t tcpc_get_alert_status(void) } /** - * Reset all system PD/TCPC MCUs -- currently only called from - * handle_pending_reboot() in common/power.c just before hard - * resetting the system. This logic is likely not needed as the - * PP3300_A rail should be dropped on EC reset. + * Reset all system PD/TCPC MCUs -- currently called from both + * handle_pending_reboot() in common/system.c and baseboard_tcpc_init() in the + * octopus/baseboard.c */ void board_reset_pd_mcu(void) { /* * C0 & C1: The internal TCPC on ITE EC does not have a reset signal, - * but it will get reset when the EC gets reset. + * but it will get reset when the EC gets reset. We will, however, + * reset the USB muxes here. */ + gpio_set_level(GPIO_USB_C0_PD_RST_ODL, 0); + gpio_set_level(GPIO_USB_C1_PD_RST_ODL, 0); + + msleep(PS8XXX_RESET_DELAY_MS); + + gpio_set_level(GPIO_USB_C0_PD_RST_ODL, 1); + gpio_set_level(GPIO_USB_C1_PD_RST_ODL, 1); } void board_pd_vconn_ctrl(int port, int cc_pin, int enabled) diff --git a/board/bip/gpio.inc b/board/bip/gpio.inc index eca5c54bce..1e90024762 100644 --- a/board/bip/gpio.inc +++ b/board/bip/gpio.inc @@ -103,6 +103,7 @@ GPIO(USB_C0_BC12_CHG_DET_L, PIN(A, 0), GPIO_INPUT) /* C0 BC1.2 Detect */ GPIO(USB_C1_BC12_CHG_DET_L, PIN(A, 1), GPIO_INPUT) /* C1 BC1.2 Detect */ GPIO(USB_C0_BC12_VBUS_ON, PIN(J, 4), GPIO_OUT_LOW) /* C0 BC1.2 Power */ GPIO(USB_C1_BC12_VBUS_ON, PIN(J, 5), GPIO_OUT_LOW) /* C1 BC1.2 Power */ +GPIO(USB_C0_PD_RST_ODL, PIN(L, 6), GPIO_ODR_HIGH) /* NC, defined for shared reset code with ampton */ GPIO(USB_C1_PD_RST_ODL, PIN(L, 7), GPIO_ODR_HIGH) /* C1 PD Reset */ /* * Configure USB2_OTG_ID as ODR so that the EC never drives it high thus @@ -123,7 +124,6 @@ GPIO(GPIOG1_NC, PIN(G, 1), GPIO_INPUT | GPIO_PULL_DOWN) GPIO(GPIOH0_NC, PIN(H, 0), GPIO_INPUT | GPIO_PULL_DOWN) GPIO(GPIOL2_NC, PIN(L, 2), GPIO_INPUT | GPIO_PULL_DOWN) GPIO(GPIOL3_NC, PIN(L, 3), GPIO_INPUT | GPIO_PULL_DOWN) -GPIO(GPIOL6_NC, PIN(L, 6), GPIO_INPUT | GPIO_PULL_DOWN) GPIO(GPIOM6_NC, PIN(M, 6), GPIO_INPUT | GPIO_PULL_DOWN) /* Misc. */ |