max32660: add I2C master and slave

BRANCH=none
BUG=none
TEST=slave tested with EC CMDs sent from a custom written EC HOST using
      another MAX32660 device as an I2C Master

Change-Id: Icdd3ac4bacbc6536a4165f63d155760d4013a8cc
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1716928
Reviewed-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Harry Cutts <hcutts@chromium.org>
Tested-by: Harry Cutts <hcutts@chromium.org>
Commit-Queue: Harry Cutts <hcutts@chromium.org>

8 files changed, 2953 insertions, 69 deletions

diff --git a/board/max32660-eval/board.c b/board/max32660-eval/board.c
index 65e69c2453..15a856ab4e 100644
--- a/board/max32660-eval/board.c
+++ b/board/max32660-eval/board.c
@@ -17,3 +17,8 @@
 #include "gpio_list.h"
 
 #define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
+
+/* I2C ports */
+const struct i2c_port_t i2c_ports[] = {};
+
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
diff --git a/board/max32660-eval/board.h b/board/max32660-eval/board.h
index fba6c60cef..87a4b65fa1 100644
--- a/board/max32660-eval/board.h
+++ b/board/max32660-eval/board.h
@@ -10,6 +10,8 @@
 
 /* Optional features */
 #define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands */
+#define CONFIG_I2C
+#define CONFIG_I2C_MASTER
 
 #define CONFIG_FPU
 
@@ -17,9 +19,17 @@
 #undef CONFIG_LID_SWITCH
 #undef CONFIG_PECI
 #undef CONFIG_SWITCH
+#define CONFIG_CMD_HOSTCMD
 
-/* #define CONFIG_I2C_SLAVE */
-/* #define CONFIG_HOSTCMD_I2C_SLAVE_ADDR (0x51 << 1) */
+#undef CONFIG_HOSTCMD_EVENTS
+#define CONFIG_I2C
+
+#define CONFIG_I2C_SLAVE
+#define CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS (0x51) /* 7 bit right-aligned, bits 6 to 0 */
+
+/* Slave I2C port configuration */
+#define I2C_PORT_SLAVE 1
+#define I2C_PORT_EC I2C_PORT_SLAVE
 
 /* Write protect is active high */
 #define CONFIG_WP_ACTIVE_HIGH
diff --git a/board/max32660-eval/ec.tasklist b/board/max32660-eval/ec.tasklist
index 3f546f98ae..5e58b9dea8 100644
--- a/board/max32660-eval/ec.tasklist
+++ b/board/max32660-eval/ec.tasklist
@@ -19,4 +19,5 @@
  */
 #define CONFIG_TASK_LIST                                                       \
 	TASK_ALWAYS(HOOKS, hook_task, NULL, TASK_STACK_SIZE)                   \
+	TASK_NOTEST(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \
 	TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE)
diff --git a/board/max32660-eval/gpio.inc b/board/max32660-eval/gpio.inc
index db34c18bed..3ced37a77f 100644
--- a/board/max32660-eval/gpio.inc
+++ b/board/max32660-eval/gpio.inc
@@ -16,3 +16,4 @@ UNIMPLEMENTED(WP)	  /* Write protect input */
 UNIMPLEMENTED(ENTERING_RW) /* EC entering RW code */
 
 ALTERNATE(PIN_MASK(0, 0x0C00), 2, MODULE_UART, 0) /* Alt 2, P0.10 (UART1_TX), P0.11 (UART1_RX) */
+ALTERNATE(PIN_MASK(0, 0x000C), 1, MODULE_I2C, 0)  /* Alt 1, P0.2  (I2C1_SCL), P0.3  (I2C1_SDA) */
diff --git a/chip/max32660/build.mk b/chip/max32660/build.mk
index b47f91f7f9..e0f5636b2e 100644
--- a/chip/max32660/build.mk
+++ b/chip/max32660/build.mk
@@ -13,6 +13,7 @@ CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
 
 # Required chip modules
 chip-y=clock_chip.o gpio_chip.o system_chip.o hwtimer_chip.o uart_chip.o
+chip-$(CONFIG_I2C)+=i2c_chip.o
 
 # Optional chip modules
 chip-$(CONFIG_FLASH_PHYSICAL)+=flash_chip.o
diff --git a/chip/max32660/i2c_chip.c b/chip/max32660/i2c_chip.c
new file mode 100644
index 0000000000..4f8bc6f7ae
--- /dev/null
+++ b/chip/max32660/i2c_chip.c
@@ -0,0 +1,1235 @@
+/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* MAX32660 I2C port module for Chrome EC. */
+
+#include <stdint.h>
+#include <stddef.h>
+#include "common.h"
+#include "config_chip.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "system.h"
+#include "task.h"
+#include "registers.h"
+#include "i2c_regs.h"
+
+/**
+ * Byte to use if the EC HOST requested more data then the I2C Slave is able to
+ * send.
+ */
+#define EC_PADDING_BYTE 0xec
+
+/* **** Definitions **** */
+#define I2C_ERROR \
+	(MXC_F_I2C_INT_FL0_ARB_ER | MXC_F_I2C_INT_FL0_TO_ER | \
+	 MXC_F_I2C_INT_FL0_ADDR_NACK_ER | MXC_F_I2C_INT_FL0_DATA_ER | \
+	 MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER | MXC_F_I2C_INT_FL0_START_ER | \
+	 MXC_F_I2C_INT_FL0_STOP_ER)
+
+#define T_LOW_MIN (160) /* tLOW minimum in nanoseconds */
+#define T_HIGH_MIN (60) /* tHIGH minimum in nanoseconds */
+#define T_R_MAX_HS (40) /* tR maximum for high speed mode in nanoseconds */
+#define T_F_MAX_HS (40) /* tF maximum for high speed mode in nanoseconds */
+#define T_AF_MIN (10)	/* tAF minimun in nanoseconds */
+
+/**
+ * typedef i2c_speed_t - I2C speed modes.
+ * @I2C_STD_MODE: 100KHz bus speed
+ * @I2C_FAST_MODE: 400KHz Bus Speed
+ * @I2C_FASTPLUS_MODE: 1MHz Bus Speed
+ * @I2C_HS_MODE: 3.4MHz Bus Speed
+ */
+typedef enum {
+	I2C_STD_MODE = 100000,
+	I2C_FAST_MODE = 400000,
+	I2C_FASTPLUS_MODE = 1000000,
+	I2C_HS_MODE = 3400000
+} i2c_speed_t;
+
+/**
+ * typedef i2c_transfer_direction_t - I2C Transfer Direction.
+ */
+typedef enum {
+	I2C_TRANSFER_DIRECTION_MASTER_WRITE = 0,
+	I2C_TRANSFER_DIRECTION_MASTER_READ = 1,
+	I2C_TRANSFER_DIRECTION_NONE = 2
+} i2c_transfer_direction_t;
+
+/**
+ * typedef i2c_autoflush_disable_t - Enable/Disable TXFIFO Autoflush mode.
+ */
+typedef enum {
+	I2C_AUTOFLUSH_ENABLE = 0,
+	I2C_AUTOFLUSH_DISABLE = 1
+} i2c_autoflush_disable_t;
+
+/**
+ * typedef i2c_master_state_t - Available transaction states for I2C Master.
+ */
+typedef enum {
+	I2C_MASTER_IDLE = 1,
+	I2C_MASTER_START = 2,
+	I2C_MASTER_WRITE_COMPLETE = 3,
+	I2C_MASTER_READ_COMPLETE = 4
+} i2c_master_state_t;
+
+/**
+ * typedef i2c_slave_state_t - Available transaction states for I2C Slave.
+ */
+typedef enum {
+	I2C_SLAVE_ADDR_MATCH = 1,
+	I2C_SLAVE_WRITE_COMPLETE = 2,
+	I2C_SLAVE_READ_COMPLETE = 3
+} i2c_slave_state_t;
+
+/**
+ * typedef i2c_req_t - I2C Transaction request.
+ */
+typedef struct i2c_req i2c_req_t;
+
+/**
+ * typedef i2c_req_state_t - Saves the state of the non-blocking requests
+ * @req:
+ * @slave_state:
+ * @num_wr: Keep track of number of bytes loaded in the fifo during slave
+ * 			transmit.
+ */
+typedef struct {
+	i2c_req_t *req;
+	i2c_slave_state_t slave_state;
+	uint8_t num_wr;
+} i2c_req_state_t;
+
+/**
+ * struct i2c_req - I2C Transaction request.
+ * @addr: I2C 7-bit Address right aligned, bit 6 to bit 0.
+ * 	  Only supports 7-bit addressing. LSb of the given
+ * 	  address will be used as the read/write bit, the addr
+ * 	  will not be shifted. Used for both master and slave
+ * 	  transactions.
+ * @tx_data: Data for mater write/slave read.
+ * @rx_data: Data for master read/slave write.
+ * @tx_len:  Length of tx data.
+ * @rx_len:  Length of rx.
+ * @tx_num:  Number of tx bytes sent.
+ * @rx_num:  Number of rx bytes sent.
+ * @direction: For the master, sets direction bit in address.
+ *             For the slave, direction of request from master.
+ * @restart: Restart or stop bit indicator.
+ *           0 to send a stop bit at the end of the transaction
+ *           Non-zero to send a restart at end of the transaction
+ *           Only used for Master transactions.
+ * @sw_autoflush_disable: Enable/Disable autoflush.
+ * @driver_status: Driver status to send to the host
+ * @callback: Callback for asynchronous request.
+ *            First argument is to the transaction request.
+ *            Second argument is the error code.
+ */
+struct i2c_req {
+	uint8_t addr;
+	const uint8_t *tx_data;
+	uint8_t *rx_data;
+	unsigned tx_len;
+	unsigned rx_len;
+	unsigned tx_num;
+	unsigned rx_num;
+	i2c_transfer_direction_t direction;
+	int restart;
+	i2c_autoflush_disable_t sw_autoflush_disable;
+	enum ec_status driver_status;
+	void (*callback)(i2c_req_t *, int);
+};
+
+static i2c_req_state_t states[MXC_I2C_INSTANCES];
+static int slave_rx_remain = 0, slave_tx_remain = 0;
+
+/**
+ * struct i2c_port_data
+ * @out: Output data pointer.
+ * @out_size: Output data to transfer, in bytes.
+ * @in: Input data pointer.
+ * @in_size: Input data to transfer, in bytes.
+ * @flags: Flags (I2C_XFER_*).
+ * @idx: Index into input/output data.
+ * @err: Error code, if any.
+ * @timeout_us:	Transaction timeout, or 0 to use default.
+ * @task_waiting: Task waiting on port, or TASK_ID_INVALID if none.
+ */
+struct i2c_port_data {
+	const uint8_t *out;
+	int out_size;
+	uint8_t *in;
+	int in_size;
+	int flags;
+	int idx;
+	int err;
+	uint32_t timeout_us;
+	volatile int task_waiting;
+};
+static struct i2c_port_data pdata[I2C_PORT_COUNT];
+
+/* **** Function Prototypes **** */
+static void i2c_free_callback(int i2c_num, int error);
+static void init_i2cs(int port);
+static int i2c_init_peripheral(mxc_i2c_regs_t *i2c, i2c_speed_t i2cspeed);
+static int i2c_master_write(mxc_i2c_regs_t *i2c, uint8_t addr, int start,
+			    int stop, const uint8_t *data, int len,
+			    int restart);
+static int i2c_master_read(mxc_i2c_regs_t *i2c, uint8_t addr, int start,
+			   int stop, uint8_t *data, int len, int restart);
+static int i2c_slave_async(mxc_i2c_regs_t *i2c, i2c_req_t *req);
+static void i2c_handler(mxc_i2c_regs_t *i2c);
+
+/* Port address for each I2C */
+static mxc_i2c_regs_t *i2c_bus_ports[] = {MXC_I2C0, MXC_I2C1};
+
+#ifdef CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS
+/* IRQ for each I2C */
+static uint32_t i2c_bus_irqs[] = {EC_I2C0_IRQn, EC_I2C1_IRQn};
+#endif
+
+/**
+ * chip_i2c_xfer() - Low Level function for I2C Master Reads and Writes.
+ * @port: Port to access
+ * @slave_addr:	Slave device address
+ * @out: Data to send
+ * @out_size: Number of bytes to send
+ * @in: Destination buffer for received data
+ * @in_size: Number of bytes to receive
+ * @flags: Flags (see I2C_XFER_* above)
+ *
+ * Chip-level function to transmit one block of raw data, then receive one
+ * block of raw data.
+ *
+ * This is a low-level chip-dependent function and should only be called by
+ * i2c_xfer().\
+ *
+ * Return EC_SUCCESS, or non-zero if error.
+ */
+int chip_i2c_xfer(int port, const uint16_t slave_addr_flags, const uint8_t *out,
+		  int out_size, uint8_t *in, int in_size, int flags)
+{
+	int xfer_start;
+	int xfer_stop;
+	int status;
+
+	xfer_start = flags & I2C_XFER_START;
+	xfer_stop = flags & I2C_XFER_STOP;
+
+	if (out_size) {
+		status = i2c_master_write(i2c_bus_ports[port], slave_addr_flags,
+					  xfer_start, xfer_stop, out, out_size,
+					  1);
+		if (status != EC_SUCCESS) {
+			return status;
+		}
+	}
+	if (in_size) {
+		status = i2c_master_read(i2c_bus_ports[port], slave_addr_flags,
+					 xfer_start, xfer_stop, in, in_size, 0);
+		if (status != EC_SUCCESS) {
+			return status;
+		}
+	}
+	return EC_SUCCESS;
+}
+
+/**
+ * i2c_get_line_levels() - Read the current digital levels on the I2C pins.
+ * @port: Port number to use when reading line levels.
+ *
+ * Return a byte where bit 0 is the line level of SCL and
+ * bit 1 is the line level of SDA.
+ */
+int i2c_get_line_levels(int port)
+{
+	/* Retrieve the current levels of SCL and SDA from the control reg. */
+	return (i2c_bus_ports[port]->ctrl >> MXC_F_I2C_CTRL_SCL_POS) & 0x03;
+}
+
+/**
+ * i2c_set_timeout()
+ * @port: Port number to set timeout for.
+ * @timeout: Timeout duration in microseconds.
+ */
+void i2c_set_timeout(int port, uint32_t timeout)
+{
+	pdata[port].timeout_us = timeout ? timeout : I2C_TIMEOUT_DEFAULT_US;
+}
+
+/**
+ * i2c_init() - Initialize the I2C ports used on device.
+ */
+static void i2c_init(void)
+{
+	int i;
+	int port;
+
+	/* Configure GPIOs */
+	gpio_config_module(MODULE_I2C, 1);
+
+	/* Initialize all I2C ports used. */
+	for (i = 0; i < i2c_ports_used; i++) {
+		port = i2c_ports[i].port;
+		i2c_init_peripheral(i2c_bus_ports[port],
+				    i2c_ports[i].kbps * 1000);
+		i2c_set_timeout(i, 0);
+	}
+
+#ifdef CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS
+	/* Initialize the I2C Slave */
+	init_i2cs(I2C_PORT_EC);
+#endif
+}
+DECLARE_HOOK(HOOK_INIT, i2c_init, HOOK_PRIO_INIT_I2C);
+
+/**
+ *  I2C Slave Implentation
+ */
+#ifdef CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS
+
+/**
+ * Buffer for received host command packets (including prefix byte on request,
+ * and result/size on response).  After any protocol-specific headers, the
+ * buffers must be 32-bit aligned.
+ */
+static uint8_t host_buffer_padded[I2C_MAX_HOST_PACKET_SIZE + 4 +
+				  CONFIG_I2C_EXTRA_PACKET_SIZE] __aligned(4);
+static uint8_t *const host_buffer = host_buffer_padded + 2;
+static uint8_t params_copy[I2C_MAX_HOST_PACKET_SIZE] __aligned(4);
+static struct host_packet i2c_packet;
+
+static i2c_req_t req_slave;
+volatile int ec_pending_response = 0;
+
+void mockup_process_host_command(i2c_req_t *req);
+
+/**
+ * i2c_send_response_packet() - Send the responze packet to get processed.
+ * @pkt: Packet to send.
+ */
+static void i2c_send_response_packet(struct host_packet *pkt)
+{
+	int size = pkt->response_size;
+	uint8_t *out = host_buffer;
+
+	/* Ignore host command in-progress */
+	if (pkt->driver_result == EC_RES_IN_PROGRESS)
+		return;
+
+	/* Write result and size to first two bytes. */
+	*out++ = pkt->driver_result;
+	*out++ = size;
+
+	/* host_buffer data range */
+	req_slave.tx_len = size + 2;
+
+	/* Call the handler for transmition of response packet. */
+	i2c_handler(i2c_bus_ports[I2C_PORT_EC]);
+}
+
+/**
+ * i2c_process_command() - Process the command in the i2c host buffer
+ */
+static void i2c_process_command(void)
+{
+	char *buff = host_buffer;
+
+	i2c_packet.send_response = i2c_send_response_packet;
+	i2c_packet.request = (const void *)(&buff[1]);
+	i2c_packet.request_temp = params_copy;
+	i2c_packet.request_max = sizeof(params_copy);
+	/* Don't know the request size so pass in the entire buffer */
+	i2c_packet.request_size = I2C_MAX_HOST_PACKET_SIZE;
+
+	/*
+	 * Stuff response at buff[2] to leave the first two bytes of
+	 * buffer available for the result and size to send over i2c.  Note
+	 * that this 2-byte offset and the 2-byte offset from host_buffer
+	 * add up to make the response buffer 32-bit aligned.
+	 */
+	i2c_packet.response = (void *)(&buff[2]);
+	i2c_packet.response_max = I2C_MAX_HOST_PACKET_SIZE;
+	i2c_packet.response_size = 0;
+
+	if (*buff >= EC_COMMAND_PROTOCOL_3) {
+		i2c_packet.driver_result = EC_RES_SUCCESS;
+	} else {
+		/* Only host command protocol 3 is supported. */
+		i2c_packet.driver_result = EC_RES_INVALID_HEADER;
+	}
+
+	host_packet_receive(&i2c_packet);
+}
+
+/**
+ * i2c_chip_callback() - Async Callback from I2C Slave driver.
+ * @req:   Request currently being processed.
+ * @error: Error from async driver, EC_SUCCESS if no error.
+ */
+void i2c_chip_callback(i2c_req_t *req, int error)
+{
+	/* check if there was a host command (I2C master write) */
+	if (req->direction == I2C_TRANSFER_DIRECTION_MASTER_WRITE) {
+		req->tx_len = -1; /* nothing to send yet */
+
+		/* process incoming host command here */
+		req->rx_data = host_buffer;
+		req->tx_data = host_buffer;
+		i2c_process_command();
+
+		/* set the rx buffer for next host command */
+		req->rx_data = host_buffer;
+	}
+
+	req->addr = CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS;
+	req->rx_len = I2C_MAX_HOST_PACKET_SIZE;
+	req->callback = i2c_chip_callback;
+}
+
+/**
+ * I2C0_IRQHandler() - Async Handler for I2C Slave driver.
+ */
+void I2C0_IRQHandler(void)
+{
+	i2c_handler(i2c_bus_ports[0]);
+}
+
+/**
+ * I2C1_IRQHandler() - Async Handler for I2C Slave driver.
+ */
+void I2C1_IRQHandler(void)
+{
+	i2c_handler(i2c_bus_ports[1]);
+}
+
+DECLARE_IRQ(EC_I2C0_IRQn, I2C0_IRQHandler, 1);
+DECLARE_IRQ(EC_I2C1_IRQn, I2C1_IRQHandler, 1);
+
+/**
+ * init_i2cs() - Async Handler for I2C Slave driver.
+ * @port: I2C port number to initialize.
+ */
+void init_i2cs(int port)
+{
+	int error;
+
+	if ((error = i2c_init_peripheral(i2c_bus_ports[port], I2C_STD_MODE)) !=
+	    EC_SUCCESS) {
+		while (1)
+			;
+	}
+	/* Prepare SlaveAsync */
+	req_slave.addr = CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS;
+	req_slave.tx_data = host_buffer; /* transmitted to host */
+	req_slave.tx_len = -1;		 /* Nothing to send. */
+	req_slave.rx_data = host_buffer; /* received from host */
+	req_slave.rx_len = I2C_MAX_HOST_PACKET_SIZE;
+	req_slave.restart = 0;
+	req_slave.callback = i2c_chip_callback;
+
+	if ((error = i2c_slave_async(i2c_bus_ports[port], &req_slave)) !=
+	    EC_SUCCESS) {
+		while (1)
+			;
+	}
+
+	task_enable_irq(i2c_bus_irqs[port]);
+}
+
+#endif /* CONFIG_HOSTCMD_I2C_SLAVE_ADDR_FLAGS */
+
+/**
+ * i2c_set_speed() - Set the transfer speed of the selected I2C.
+ * @i2c: Pointer to I2C peripheral.
+ * @i2cspeed: Speed to set.
+ *
+ * Return EC_SUCCESS, or non-zero if error.
+ */
+static int i2c_set_speed(mxc_i2c_regs_t *i2c, i2c_speed_t i2cspeed)
+{
+	uint32_t ticks;
+	uint32_t ticks_lo;
+	uint32_t ticks_hi;
+	uint32_t time_pclk;
+	uint32_t target_bus_freq;
+	uint32_t time_scl_min;
+	uint32_t clock_low_min;
+	uint32_t clock_high_min;
+	uint32_t clock_min;
+
+	if (i2cspeed == I2C_HS_MODE) {
+		/* Compute dividers for high speed mode. */
+		time_pclk = 1000000 / (PeripheralClock / 1000);
+
+		target_bus_freq = i2cspeed;
+		if (target_bus_freq < 1000) {
+			return EC_ERROR_INVAL;
+		}
+
+		time_scl_min = 1000000 / (target_bus_freq / 1000);
+		clock_low_min =
+			((T_LOW_MIN + T_F_MAX_HS + (time_pclk - 1) - T_AF_MIN) /
+			 time_pclk) - 1;
+		clock_high_min = ((T_HIGH_MIN + T_R_MAX_HS + (time_pclk - 1) -
+				  T_AF_MIN) /
+				  time_pclk) - 1;
+		clock_min = ((time_scl_min + (time_pclk - 1)) / time_pclk) - 2;
+
+		ticks_lo = (clock_low_min > (clock_min - clock_high_min))
+				   ? (clock_low_min)
+				   : (clock_min - clock_high_min);
+		ticks_hi = clock_high_min;
+
+		if ((ticks_lo > (MXC_F_I2C_HS_CLK_HS_CLK_LO >>
+				 MXC_F_I2C_HS_CLK_HS_CLK_LO_POS)) ||
+		    (ticks_hi > (MXC_F_I2C_HS_CLK_HS_CLK_HI >>
+				 MXC_F_I2C_HS_CLK_HS_CLK_HI_POS))) {
+			return EC_ERROR_INVAL;
+		}
+
+		/* Write results to destination registers. */
+		i2c->hs_clk = (ticks_lo << MXC_F_I2C_HS_CLK_HS_CLK_LO_POS) |
+			      (ticks_hi << MXC_F_I2C_HS_CLK_HS_CLK_HI_POS);
+
+		/* Still need to load dividers for the preamble that each
+		 * high-speed transaction starts with. Switch setting to fast
+		 * mode and fall out of if statement.
+		 */
+		i2cspeed = I2C_FAST_MODE;
+	}
+
+	/* Get the number of periph clocks needed to achieve selected speed. */
+	ticks = PeripheralClock / i2cspeed;
+
+	/* For a 50% duty cycle, half the ticks will be spent high and half will
+	 * be low.
+	 */
+	ticks_hi = (ticks >> 1) - 1;
+	ticks_lo = (ticks >> 1) - 1;
+
+	/* Account for rounding error in odd tick counts. */
+	if (ticks & 1) {
+		ticks_hi++;
+	}
+
+	/* Will results fit into 9 bit registers?  (ticks_hi will always be >=
+	 * ticks_lo.  No need to check ticks_lo.)
+	 */
+	if (ticks_hi > 0x1FF) {
+		return EC_ERROR_INVAL;
+	}
+
+	/* 0 is an invalid value for the destination registers. (ticks_hi will
+	 * always be >= ticks_lo.  No need to check ticks_hi.)
+	 */
+	if (ticks_lo == 0) {
+		return EC_ERROR_INVAL;
+	}
+
+	/* Write results to destination registers. */
+	i2c->clk_lo = ticks_lo;
+	i2c->clk_hi = ticks_hi;
+
+	return EC_SUCCESS;
+}
+
+/**
+ * i2c_init_peripheral() - Initialize and enable I2C.
+ * @i2c:      Pointer to I2C peripheral registers.
+ * @i2cspeed: Desired speed (I2C mode).
+ * @sys_cfg:  System configuration object.
+ *
+ * Return EC_SUCCESS, or non-zero if error.
+ */
+static int i2c_init_peripheral(mxc_i2c_regs_t *i2c, i2c_speed_t i2cspeed)
+{
+	/**
+	 * Always disable the HW autoflush on data NACK and let the SW handle
+	 * the flushing.
+	 */
+	i2c->tx_ctrl0 |= 0x20;
+
+	states[MXC_I2C_GET_IDX(i2c)].num_wr = 0;
+
+	i2c->ctrl = 0; /* clear configuration bits */
+	i2c->ctrl = MXC_F_I2C_CTRL_I2C_EN; /* Enable I2C */
+	i2c->master_ctrl = 0; /* clear master configuration bits */
+	i2c->status = 0; /* clear status bits */
+
+	i2c->ctrl = 0; /* clear configuration bits */
+	i2c->ctrl = MXC_F_I2C_CTRL_I2C_EN; /* Enable I2C */
+	i2c->master_ctrl = 0; /* clear master configuration bits */
+	i2c->status = 0; /* clear status bits */
+
+	/* Check for HS mode */
+	if (i2cspeed == I2C_HS_MODE) {
+		i2c->ctrl |= MXC_F_I2C_CTRL_HS_MODE; /* Enable HS mode */
+	}
+
+	/* Disable and clear interrupts */
+	i2c->int_en0 = 0;
+	i2c->int_en1 = 0;
+	i2c->int_fl0 = i2c->int_fl0;
+	i2c->int_fl1 = i2c->int_fl1;
+
+	i2c->timeout = 0x0; /* set timeout */
+	i2c->rx_ctrl0 |= MXC_F_I2C_RX_CTRL0_RX_FLUSH; /* clear the RX FIFO */
+	i2c->tx_ctrl0 |= MXC_F_I2C_TX_CTRL0_TX_FLUSH; /* clear the TX FIFO */
+
+	return i2c_set_speed(i2c, i2cspeed);
+}
+
+/**
+ * i2c_master_write()
+ * @i2c:  Pointer to I2C regs.
+ * @addr: I2C 7-bit Address left aligned, bit 7 to bit 1.
+ *        Only supports 7-bit addressing. LSb of the given address
+ *        will be used as the read/write bit, the \p addr <b>will
+ *        not be shifted. Used for both master and
+ *        slave transactions.
+ * @data: Data to be written.
+ * @len:  Number of bytes to Write.
+ * @restart: 0 to send a stop bit at the end of the transaction,
+ *	     otherwise send a restart.
+ *
+ * Will block until transaction is complete.
+ *
+ * Return  EC_SUCCESS, or non-zero if error.
+ */
+static int i2c_master_write(mxc_i2c_regs_t *i2c, uint8_t addr, int start,
+			    int stop, const uint8_t *data, int len, int restart)
+{
+	if (len == 0) {
+		return EC_SUCCESS;
+	}
+
+	/* Clear the interrupt flag */
+	i2c->int_fl0 = i2c->int_fl0;
+
+	/* Make sure the I2C has been initialized */
+	if (!(i2c->ctrl & MXC_F_I2C_CTRL_I2C_EN)) {
+		return EC_ERROR_UNKNOWN;
+	}
+
+	/* Enable master mode */
+	i2c->ctrl |= MXC_F_I2C_CTRL_MST;
+
+	/* Load FIFO with slave address for WRITE and as much data as we can */
+	while (i2c->status & MXC_F_I2C_STATUS_TX_FULL) {
+	}
+
+	if (start) {
+		/**
+		 * The slave address is right-aligned, bits 6 to 0, shift
+		 * to the left and make room for the write bit.
+		 */
+		i2c->fifo = (addr << 1) & ~(0x1);
+	}
+
+	while ((len > 0) && !(i2c->status & MXC_F_I2C_STATUS_TX_FULL)) {
+		i2c->fifo = *data++;
+		len--;
+	}
+	/* Generate Start signal */
+	if (start) {
+		i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_START;
+	}
+
+	/* Write remaining data to FIFO */
+	while (len > 0) {
+		/* Check for errors */
+		if (i2c->int_fl0 & I2C_ERROR) {
+			/* Set the stop bit */
+			i2c->master_ctrl &= ~(MXC_F_I2C_MASTER_CTRL_RESTART);
+			i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
+			return EC_ERROR_UNKNOWN;
+		}
+
+		if (!(i2c->status & MXC_F_I2C_STATUS_TX_FULL)) {
+			i2c->fifo = *data++;
+			len--;
+		}
+	}
+	/* Check if Repeated Start requested */
+	if (restart) {
+		i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_RESTART;
+	} else {
+		if (stop) {
+			i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
+		}
+	}
+
+	if (stop) {
+		/* Wait for Done */
+		while (!(i2c->int_fl0 & MXC_F_I2C_INT_FL0_DONE)) {
+			/* Check for errors */
+			if (i2c->int_fl0 & I2C_ERROR) {
+				/* Set the stop bit */
+				i2c->master_ctrl &=
+					~(MXC_F_I2C_MASTER_CTRL_RESTART);
+				i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
+				return EC_ERROR_UNKNOWN;
+			}
+		}
+		/* Clear Done interrupt flag */
+		i2c->int_fl0 = MXC_F_I2C_INT_FL0_DONE;
+	}
+
+	/* Wait for Stop if requested and there is no restart. */
+	if (stop && !restart) {
+		while (!(i2c->int_fl0 & MXC_F_I2C_INT_FL0_STOP)) {
+			/* Check for errors */
+			if (i2c->int_fl0 & I2C_ERROR) {
+				/* Set the stop bit */
+				i2c->master_ctrl &=
+					~(MXC_F_I2C_MASTER_CTRL_RESTART);
+				i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
+				return EC_ERROR_UNKNOWN;
+			}
+		}
+		/* Clear stop interrupt flag */
+		i2c->int_fl0 = MXC_F_I2C_INT_FL0_STOP;
+	}
+
+	/* Check for errors */
+	if (i2c->int_fl0 & I2C_ERROR) {
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+/**
+ * i2c_master_read()
+ * @i2c:        Pointer to I2C regs.
+ * @addr:       I2C 7-bit Address right aligned, bit 6 to bit 0.
+ * @data:       Data to be written.
+ * @len:        Number of bytes to Write.
+ * @restart:    0 to send a stop bit at the end of the transaction,
+ * 	       otherwise send a restart.
+ *
+ * Will block until transaction is complete.
+ *
+ * Return:     EC_SUCCESS if successful, otherwise returns a common error code
+ */
+static int i2c_master_read(mxc_i2c_regs_t *i2c, uint8_t addr, int start,
+			   int stop, uint8_t *data, int len, int restart)
+{
+	volatile int length = len;
+	int interactive_receive_mode;
+
+	if (len == 0) {
+		return EC_SUCCESS;
+	}
+
+	if (len > 255) {
+		return EC_ERROR_INVAL;
+	}
+
+	/* Clear the interrupt flag */
+	i2c->int_fl0 = i2c->int_fl0;
+
+	/* Make sure the I2C has been initialized */
+	if (!(i2c->ctrl & MXC_F_I2C_CTRL_I2C_EN)) {
+		return EC_ERROR_UNKNOWN;
+	}
+
+	/* Enable master mode */
+	i2c->ctrl |= MXC_F_I2C_CTRL_MST;
+
+	if (stop) {
+		/* Set receive count */
+		i2c->ctrl &= ~MXC_F_I2C_CTRL_RX_MODE;
+		i2c->rx_ctrl1 = len;
+		interactive_receive_mode = 0;
+	} else {
+		i2c->ctrl |= MXC_F_I2C_CTRL_RX_MODE;
+		i2c->rx_ctrl1 = 1;
+		interactive_receive_mode = 1;
+	}
+
+	/* Load FIFO with slave address */
+	if (start) {
+		i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_START;
+		while (i2c->status & MXC_F_I2C_STATUS_TX_FULL) {
+		}
+		/**
+		 * The slave address is right-aligned, bits 6 to 0, shift
+		 * to the left and make room for the read bit.
+		 */
+		i2c->fifo = ((addr << 1) | 1);
+	}
+
+	/* Wait for all data to be received or error. */
+	while (length > 0) {
+		/* Check for errors */
+		if (i2c->int_fl0 & I2C_ERROR) {
+			/* Set the stop bit */
+			i2c->master_ctrl &= ~(MXC_F_I2C_MASTER_CTRL_RESTART);
+			i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
+			return EC_ERROR_UNKNOWN;
+		}
+
+		/* if in interactive receive mode then ack each received byte */
+		if (interactive_receive_mode) {
+			while (!(i2c->int_fl0 & MXC_F_I2C_INT_EN0_RX_MODE))
+				;
+			if (i2c->int_fl0 & MXC_F_I2C_INT_EN0_RX_MODE) {
+				/* read the data */
+				*data++ = i2c->fifo;
+				length--;
+				/* clear the bit */
+				if (length != 1) {
+					i2c->int_fl0 =
+						MXC_F_I2C_INT_EN0_RX_MODE;
+				}
+			}
+		} else {
+			if (!(i2c->status & MXC_F_I2C_STATUS_RX_EMPTY)) {
+				*data++ = i2c->fifo;
+				length--;
+			}
+		}
+	}
+
+	if (restart) {
+		i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_RESTART;
+	} else {
+		if (stop) {
+			i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
+		}
+	}
+
+	/* Wait for Done */
+	if (stop) {
+		while (!(i2c->int_fl0 & MXC_F_I2C_INT_FL0_DONE)) {
+			/* Check for errors */
+			if (i2c->int_fl0 & I2C_ERROR) {
+				/* Set the stop bit */
+				i2c->master_ctrl &=
+					~(MXC_F_I2C_MASTER_CTRL_RESTART);
+				i2c->master_ctrl |= MXC_F_I2C_MASTER_CTRL_STOP;
+				return EC_ERROR_UNKNOWN;
+			}
+		}
+		/* Clear Done interrupt flag */
+		i2c->int_fl0 = MXC_F_I2C_INT_FL0_DONE;
+	}
+
+	/* Wait for Stop */
+	if (!restart) {
+		if (stop) {
+			while (!(i2c->int_fl0 & MXC_F_I2C_INT_FL0_STOP)) {
+				/* Check for errors */
+				if (i2c->int_fl0 & I2C_ERROR) {
+					/* Set the stop bit */
+					i2c->master_ctrl &= ~(
+						MXC_F_I2C_MASTER_CTRL_RESTART);
+					i2c->master_ctrl |=
+						MXC_F_I2C_MASTER_CTRL_STOP;
+					return EC_ERROR_UNKNOWN;
+				}
+			}
+			/* Clear Stop interrupt flag */
+			i2c->int_fl0 = MXC_F_I2C_INT_FL0_STOP;
+		}
+	}
+
+	/* Check for errors */
+	if (i2c->int_fl0 & I2C_ERROR) {
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+/**
+ * i2c_slave_async() - Slave Read and Write Asynchronous.
+ * @i2c:   Pointer to I2C regs.
+ * @req:   Request for an I2C transaction.
+ *
+ * Return EC_SUCCESS if successful, otherwise returns a common error code.
+ */
+static int i2c_slave_async(mxc_i2c_regs_t *i2c, i2c_req_t *req)
+{
+	/* Make sure the I2C has been initialized. */
+	if (!(i2c->ctrl & MXC_F_I2C_CTRL_I2C_EN)) {
+		return EC_ERROR_UNKNOWN;
+	}
+
+	states[MXC_I2C_GET_IDX(i2c)].req = req;
+
+	/* Disable master mode */
+	i2c->ctrl &= ~(MXC_F_I2C_CTRL_MST);
+	/* Set the Slave Address in the I2C peripheral register. */
+	i2c->slave_addr = req->addr;
+
+	/* Clear the byte counters */
+	req->tx_num = 0;
+	req->rx_num = 0;
+
+	/* Disable and clear the interrupts. */
+	i2c->int_en0 = 0;
+	i2c->int_en1 = 0;
+	i2c->int_fl0 = i2c->int_fl0;
+	i2c->int_fl1 = i2c->int_fl1;
+	/* Only enable the I2C Address match interrupt. */
+	i2c->int_en0 = MXC_F_I2C_INT_EN0_ADDR_MATCH;
+
+	return EC_SUCCESS;
+}
+
+/**
+ * i2c_slave_read() - Handles async read request from the I2c master.
+ * @i2c: I2C peripheral pointer.
+ * @req: Pointer to the request info.
+ * @int_flags: Current state of the interrupt flags for this request.
+ *
+ * Return EC_SUCCESS if successful, otherwise returns a common error code.
+ */
+static int i2c_slave_read(mxc_i2c_regs_t *i2c, i2c_req_t *req,
+			  uint32_t int_flags)
+{
+	int i2c_num;
+
+	i2c_num = MXC_I2C_GET_IDX(i2c);
+	req->direction = I2C_TRANSFER_DIRECTION_MASTER_READ;
+	if (slave_tx_remain != 0) {
+		/* Fill the FIFO */
+		while ((slave_tx_remain > 0) &&
+		       !(i2c->status & MXC_F_I2C_STATUS_TX_FULL)) {
+			i2c->fifo = *(req->tx_data)++;
+			states[i2c_num].num_wr++;
+			slave_tx_remain--;
+		}
+		/* Set the TX threshold interrupt level. */
+		if (slave_tx_remain >= (MXC_I2C_FIFO_DEPTH - 1)) {
+			i2c->tx_ctrl0 =
+				((i2c->tx_ctrl0 &
+				  ~(MXC_F_I2C_TX_CTRL0_TX_THRESH)) |
+				 (MXC_I2C_FIFO_DEPTH - 1)
+					 << MXC_F_I2C_TX_CTRL0_TX_THRESH_POS);
+
+		} else {
+			i2c->tx_ctrl0 =
+				((i2c->tx_ctrl0 &
+				  ~(MXC_F_I2C_TX_CTRL0_TX_THRESH)) |
+				 (slave_tx_remain)
+					 << MXC_F_I2C_TX_CTRL0_TX_THRESH_POS);
+		}
+		/* Enable TXTH interrupt and Error interrupts. */
+		i2c->int_en0 |= (MXC_F_I2C_INT_EN0_TX_THRESH | I2C_ERROR);
+		if (int_flags & I2C_ERROR) {
+			i2c->int_en0 = 0;
+			/* Calculate the number of bytes sent by the slave. */
+			req->tx_num =
+				states[i2c_num].num_wr -
+				((i2c->tx_ctrl1 & MXC_F_I2C_TX_CTRL1_TX_FIFO) >>
+				 MXC_F_I2C_TX_CTRL1_TX_FIFO_POS);
+			if (!req->sw_autoflush_disable) {
+				/* Manually clear the TXFIFO. */
+				i2c->tx_ctrl0 |= MXC_F_I2C_TX_CTRL0_TX_FLUSH;
+			}
+			states[i2c_num].num_wr = 0;
+			if (req->callback != NULL) {
+				/* Disable and clear interrupts. */
+				i2c->int_en0 = 0;
+				i2c->int_en1 = 0;
+				i2c->int_fl0 = i2c->int_fl0;
+				i2c->int_fl1 = i2c->int_fl1;
+				/* Cycle the I2C peripheral enable on error. */
+				i2c->ctrl = 0;
+				i2c->ctrl = MXC_F_I2C_CTRL_I2C_EN;
+				i2c_free_callback(i2c_num, EC_ERROR_UNKNOWN);
+			}
+			return EC_ERROR_UNKNOWN;
+		}
+	} else {
+		/**
+		 * If there is nothing to transmit to the EC HOST, then default
+		 * to clock stretching.
+		 */
+		if (req->tx_len == -1)
+			return EC_SUCCESS;
+		/**
+		 * The EC HOST is requesting more that we are able to transmit.
+		 * Fulfill the EC HOST reading of extra bytes by sending the
+		 * EC_PADDING_BYTE.
+		 */
+		if (!(i2c->status & MXC_F_I2C_STATUS_TX_FULL)) {
+			i2c->fifo = EC_PADDING_BYTE;
+		}
+		/* set tx threshold to zero */
+		i2c->tx_ctrl0 =
+			((i2c->tx_ctrl0 & ~(MXC_F_I2C_TX_CTRL0_TX_THRESH)) |
+			 (0) << MXC_F_I2C_TX_CTRL0_TX_THRESH_POS);
+		/* Enable TXTH interrupt and Error interrupts */
+		i2c->int_en0 |= (MXC_F_I2C_INT_EN0_TX_THRESH | I2C_ERROR);
+	}
+	return EC_SUCCESS;
+}
+
+/**
+ * i2c_slave_write() - Handles async write request from the I2c master.
+ * @i2c: I2C peripheral pointer.
+ * @req: Pointer to the request info.
+ * @int_flags: Current state of the interrupt flags for this request.
+ *
+ * Return EC_SUCCESS if successful, otherwise returns a common error code.
+ */
+static int i2c_slave_write(mxc_i2c_regs_t *i2c, i2c_req_t *req,
+			   uint32_t int_flags)
+{
+	int i2c_num;
+
+	/**
+	 * Master Write has been called and if there is a
+	 * rx_data buffer
+	 */
+	i2c_num = MXC_I2C_GET_IDX(i2c);
+	req->direction = I2C_TRANSFER_DIRECTION_MASTER_WRITE;
+	if (slave_rx_remain != 0) {
+		/* Read out any data in the RX FIFO. */
+		while ((slave_rx_remain > 0) &&
+		       !(i2c->status & MXC_F_I2C_STATUS_RX_EMPTY)) {
+			*(req->rx_data)++ = i2c->fifo;
+			req->rx_num++;
+			slave_rx_remain--;
+		}
+		/* Set the RX threshold interrupt level. */
+		if (slave_rx_remain >= (MXC_I2C_FIFO_DEPTH - 1)) {
+			i2c->rx_ctrl0 =
+				((i2c->rx_ctrl0 &
+				  ~(MXC_F_I2C_RX_CTRL0_RX_THRESH)) |
+				 (MXC_I2C_FIFO_DEPTH - 1)
+					 << MXC_F_I2C_RX_CTRL0_RX_THRESH_POS);
+		} else {
+			i2c->rx_ctrl0 =
+				((i2c->rx_ctrl0 &
+				  ~(MXC_F_I2C_RX_CTRL0_RX_THRESH)) |
+				 (slave_rx_remain)
+					 << MXC_F_I2C_RX_CTRL0_RX_THRESH_POS);
+		}
+		/* Enable RXTH interrupt and Error interrupts. */
+		i2c->int_en0 |= (MXC_F_I2C_INT_EN0_RX_THRESH | I2C_ERROR);
+		if (int_flags & I2C_ERROR) {
+			i2c->int_en0 = 0;
+			/**
+			 * Calculate the number of bytes sent
+			 * by the slave.
+			 */
+			req->tx_num =
+				states[i2c_num].num_wr -
+				((i2c->tx_ctrl1 & MXC_F_I2C_TX_CTRL1_TX_FIFO) >>
+				 MXC_F_I2C_TX_CTRL1_TX_FIFO_POS);
+
+			if (!req->sw_autoflush_disable) {
+				/* Manually clear the TXFIFO. */
+				i2c->tx_ctrl0 |= MXC_F_I2C_TX_CTRL0_TX_FLUSH;
+			}
+			states[i2c_num].num_wr = 0;
+			if (req->callback != NULL) {
+				/* Disable and clear interrupts. */
+				i2c->int_en0 = 0;
+				i2c->int_en1 = 0;
+				i2c->int_fl0 = i2c->int_fl0;
+				i2c->int_fl1 = i2c->int_fl1;
+				/* Cycle the I2C peripheral enable on error. */
+				i2c->ctrl = 0;
+				i2c->ctrl = MXC_F_I2C_CTRL_I2C_EN;
+				i2c_free_callback(i2c_num, EC_ERROR_UNKNOWN);
+			}
+			return EC_ERROR_UNKNOWN;
+		}
+	} else {
+		/* Disable RXTH interrupt. */
+		i2c->int_en0 &= ~(MXC_F_I2C_INT_EN0_RX_THRESH);
+		/* Flush any extra bytes in the RXFIFO */
+		i2c->rx_ctrl0 |= MXC_F_I2C_RX_CTRL0_RX_FLUSH;
+		/* Store the current state of the slave */
+		states[i2c_num].slave_state = I2C_SLAVE_READ_COMPLETE;
+	}
+	return EC_SUCCESS;
+}
+
+static void i2c_slave_handler(mxc_i2c_regs_t *i2c)
+{
+	uint32_t int_flags;
+	int i2c_num;
+	i2c_req_t *req;
+	int status;
+
+	i2c_num = MXC_I2C_GET_IDX(i2c);
+	req = states[i2c_num].req;
+
+	/* Check for an Address match */
+	if (i2c->int_fl0 & MXC_F_I2C_INT_FL0_ADDR_MATCH) {
+		/* Clear AMI and TXLOI */
+		i2c->int_fl0 |= MXC_F_I2C_INT_FL0_DONE;
+		i2c->int_fl0 |= MXC_F_I2C_INT_FL0_ADDR_MATCH;
+		i2c->int_fl0 |= MXC_F_I2C_INT_FL0_TX_LOCK_OUT;
+		/* Store the current state of the Slave */
+		states[i2c_num].slave_state = I2C_SLAVE_ADDR_MATCH;
+		/* Set the Done, Stop interrupt */
+		i2c->int_en0 |= MXC_F_I2C_INT_EN0_DONE | MXC_F_I2C_INT_EN0_STOP;
+		/* Inhibit sleep mode when addressed until STOPF flag is set */
+		disable_sleep(SLEEP_MASK_I2C_SLAVE);
+	}
+
+	/* Check for errors */
+	int_flags = i2c->int_fl0;
+	/* Clear the interrupts */
+	i2c->int_fl0 = int_flags;
+
+	if (int_flags & I2C_ERROR) {
+		i2c->int_en0 = 0;
+		/* Calculate the number of bytes sent by the slave */
+		req->tx_num = states[i2c_num].num_wr -
+			      ((i2c->tx_ctrl1 & MXC_F_I2C_TX_CTRL1_TX_FIFO) >>
+			       MXC_F_I2C_TX_CTRL1_TX_FIFO_POS);
+
+		if (!req->sw_autoflush_disable) {
+			/* Manually clear the TXFIFO */
+			i2c->tx_ctrl0 |= MXC_F_I2C_TX_CTRL0_TX_FLUSH;
+		}
+		states[i2c_num].num_wr = 0;
+		if (req->callback != NULL) {
+			/* Disable and clear interrupts */
+			i2c->int_en0 = 0;
+			i2c->int_en1 = 0;
+			i2c->int_fl0 = i2c->int_fl0;
+			i2c->int_fl1 = i2c->int_fl1;
+			/* Cycle the I2C peripheral enable on error. */
+			i2c->ctrl = 0;
+			i2c->ctrl = MXC_F_I2C_CTRL_I2C_EN;
+			i2c_free_callback(i2c_num, EC_ERROR_UNKNOWN);
+		}
+		return;
+	}
+
+	slave_rx_remain = req->rx_len - req->rx_num;
+	/* determine if there is any data ready to transmit to the EC HOST */
+	if (req->tx_len != -1) {
+		slave_tx_remain = req->tx_len - states[i2c_num].num_wr;
+	} else {
+		slave_tx_remain = 0;
+	}
+
+	/* Check for Stop interrupt */
+	if (int_flags & MXC_F_I2C_INT_FL0_STOP) {
+		/* Disable all interrupts except address match. */
+		i2c->int_en1 = 0;
+		i2c->int_en0 = MXC_F_I2C_INT_EN0_ADDR_MATCH;
+		/* Clear all interrupts except a possible address match. */
+		i2c->int_fl0 = i2c->int_fl0 & ~MXC_F_I2C_INT_FL0_ADDR_MATCH;
+		i2c->int_fl1 = i2c->int_fl1;
+		if (req->direction == I2C_TRANSFER_DIRECTION_MASTER_WRITE) {
+			/* Read out any data in the RX FIFO */
+			while (!(i2c->status & MXC_F_I2C_STATUS_RX_EMPTY)) {
+				*(req->rx_data)++ = i2c->fifo;
+				req->rx_num++;
+			}
+		}
+
+		/* Calculate the number of bytes sent by the slave */
+		req->tx_num = states[i2c_num].num_wr -
+			      ((i2c->tx_ctrl1 & MXC_F_I2C_TX_CTRL1_TX_FIFO) >>
+			       MXC_F_I2C_TX_CTRL1_TX_FIFO_POS);
+		slave_rx_remain = 0;
+		slave_tx_remain = 0;
+		if (!req->sw_autoflush_disable) {
+			/* Manually clear the TXFIFO */
+			i2c->tx_ctrl0 |= MXC_F_I2C_TX_CTRL0_TX_FLUSH;
+		}
+		/* Callback to the EC request processor */
+		i2c_free_callback(i2c_num, EC_SUCCESS);
+		req->direction = I2C_TRANSFER_DIRECTION_NONE;
+		states[i2c_num].num_wr = 0;
+
+		/* Be ready to receive more data */
+		req->rx_len = 128;
+		/* Clear the byte counters */
+		req->tx_num = 0;
+		req->rx_num = 0;
+		req->tx_len = -1; /* Nothing to send. */
+
+		/* No longer inhibit deep sleep after stop condition */
+		enable_sleep(SLEEP_MASK_I2C_SLAVE);
+		return;
+	}
+
+	/* Check for DONE interrupt */
+	if (int_flags & MXC_F_I2C_INT_FL0_DONE) {
+		if (req->direction == I2C_TRANSFER_DIRECTION_MASTER_WRITE) {
+			/* Read out any data in the RX FIFO */
+			while (!(i2c->status & MXC_F_I2C_STATUS_RX_EMPTY)) {
+				*(req->rx_data)++ = i2c->fifo;
+				req->rx_num++;
+			}
+		}
+		/* Disable Done interrupt */
+		i2c->int_en0 &= ~(MXC_F_I2C_INT_EN0_DONE);
+		/* Calculate the number of bytes sent by the slave */
+		req->tx_num = states[i2c_num].num_wr -
+			      ((i2c->tx_ctrl1 & MXC_F_I2C_TX_CTRL1_TX_FIFO) >>
+			       MXC_F_I2C_TX_CTRL1_TX_FIFO_POS);
+		slave_rx_remain = 0;
+		slave_tx_remain = 0;
+		if (!req->sw_autoflush_disable) {
+			/* Manually clear the TXFIFO */
+			i2c->tx_ctrl0 |= MXC_F_I2C_TX_CTRL0_TX_FLUSH;
+		}
+		i2c_free_callback(i2c_num, EC_SUCCESS);
+		req->direction = I2C_TRANSFER_DIRECTION_NONE;
+		states[i2c_num].num_wr = 0;
+		return;
+	}
+
+	if (states[i2c_num].slave_state != I2C_SLAVE_ADDR_MATCH) {
+		return;
+	}
+	/**
+	 * Check if Master Read has been called and if there is a
+	 * tx_data buffer
+	 */
+	if (i2c->ctrl & MXC_F_I2C_CTRL_READ) {
+		status = i2c_slave_read(i2c, req, int_flags);
+		if (status != EC_SUCCESS) {
+			return;
+		}
+	} else {
+		status = i2c_slave_write(i2c, req, int_flags);
+		if (status != EC_SUCCESS) {
+			return;
+		}
+	}
+}
+
+/**
+ * i2c_handler() - I2C interrupt handler.
+ * @i2c: Base address of the I2C module.
+ *
+ * This function should be called by the application from the interrupt
+ * handler if I2C interrupts are enabled. Alternately, this function
+ * can be periodically called by the application if I2C interrupts are
+ * disabled.
+ */
+static void i2c_handler(mxc_i2c_regs_t *i2c)
+{
+	i2c_slave_handler(i2c);
+}
+
+static void i2c_free_callback(int i2c_num, int error)
+{
+	/* Save the request */
+	i2c_req_t *temp_req = states[i2c_num].req;
+
+	/* Callback if not NULL */
+	if (temp_req->callback != NULL) {
+		temp_req->callback(temp_req, error);
+	}
+}
diff --git a/chip/max32660/i2c_regs.h b/chip/max32660/i2c_regs.h
new file mode 100644
index 0000000000..e87de5d11d
--- /dev/null
+++ b/chip/max32660/i2c_regs.h
@@ -0,0 +1,1610 @@
+/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* MAX32660 Registers, Bit Masks and Bit Positions for the I2C Peripheral */
+
+#ifndef _I2C_REGS_H_
+#define _I2C_REGS_H_
+
+#include <stdint.h>
+
+/*
+    If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __R
+#define __R volatile const
+#endif
+
+/**
+ * Registers, Bit Masks and Bit Positions for the I2C Peripheral Module.
+ */
+
+/**
+ * typedef mxc_i2c_regs_t - Structure type to access the I2C Registers.
+ */
+typedef struct {
+	__IO uint32_t ctrl; /**< <tt>\b 0x00:</tt> I2C CTRL Register */
+	__IO uint32_t status; /**< <tt>\b 0x04:</tt> I2C STATUS Register */
+	__IO uint32_t int_fl0; /**< <tt>\b 0x08:</tt> I2C INT_FL0 Register */
+	__IO uint32_t int_en0; /**< <tt>\b 0x0C:</tt> I2C INT_EN0 Register */
+	__IO uint32_t int_fl1; /**< <tt>\b 0x10:</tt> I2C INT_FL1 Register */
+	__IO uint32_t int_en1; /**< <tt>\b 0x14:</tt> I2C INT_EN1 Register */
+	__IO uint32_t fifo_len; /**< <tt>\b 0x18:</tt> I2C FIFO_LEN Register */
+	__IO uint32_t rx_ctrl0; /**< <tt>\b 0x1C:</tt> I2C RX_CTRL0 Register */
+	__IO uint32_t rx_ctrl1; /**< <tt>\b 0x20:</tt> I2C RX_CTRL1 Register */
+	__IO uint32_t tx_ctrl0; /**< <tt>\b 0x24:</tt> I2C TX_CTRL0 Register */
+	__IO uint32_t tx_ctrl1; /**< <tt>\b 0x28:</tt> I2C TX_CTRL1 Register */
+	__IO uint32_t fifo; /**< <tt>\b 0x2C:</tt> I2C FIFO Register */
+	__IO uint32_t
+		master_ctrl; /**< <tt>\b 0x30:</tt> I2C MASTER_CTRL Register */
+	__IO uint32_t clk_lo; /**< <tt>\b 0x34:</tt> I2C CLK_LO Register */
+	__IO uint32_t clk_hi; /**< <tt>\b 0x38:</tt> I2C CLK_HI Register */
+	__IO uint32_t hs_clk; /**< <tt>\b 0x3C:</tt> I2C HS_CLK Register */
+	__IO uint32_t timeout; /**< <tt>\b 0x40:</tt> I2C TIMEOUT Register */
+	__IO uint32_t
+		slave_addr; /**< <tt>\b 0x44:</tt> I2C SLAVE_ADDR Register */
+	__IO uint32_t dma; /**< <tt>\b 0x48:</tt> I2C DMA Register */
+} mxc_i2c_regs_t;
+
+/* Register offsets for module I2C */
+/**
+ * I2C Peripheral Register Offsets from the I2C Base Peripheral Address.
+ */
+#define MXC_R_I2C_CTRL \
+	((uint32_t)0x00000000UL) /**< Offset from I2C Base Address: <tt>       \
+				    0x0000</tt> */
+#define MXC_R_I2C_STATUS \
+	((uint32_t)0x00000004UL) /**< Offset from I2C Base Address: <tt>       \
+				    0x0004</tt> */
+#define MXC_R_I2C_INT_FL0 \
+	((uint32_t)0x00000008UL) /**< Offset from I2C Base Address: <tt>       \
+				    0x0008</tt> */
+#define MXC_R_I2C_INT_EN0 \
+	((uint32_t)0x0000000CUL) /**< Offset from I2C Base Address: <tt>       \
+				    0x000C</tt> */
+#define MXC_R_I2C_INT_FL1 \
+	((uint32_t)0x00000010UL) /**< Offset from I2C Base Address: <tt>       \
+				    0x0010</tt> */
+#define MXC_R_I2C_INT_EN1 \
+	((uint32_t)0x00000014UL) /**< Offset from I2C Base Address: <tt>       \
+				    0x0014</tt> */
+#define MXC_R_I2C_FIFO_LEN \
+	((uint32_t)0x00000018UL) /**< Offset from I2C Base Address: <tt>       \
+				    0x0018</tt> */
+#define MXC_R_I2C_RX_CTRL0 \
+	((uint32_t)0x0000001CUL) /**< Offset from I2C Base Address: <tt>       \
+				    0x001C</tt> */
+#define MXC_R_I2C_RX_CTRL1 \
+	((uint32_t)0x00000020UL) /**< Offset from I2C Base Address: <tt>       \
+				    0x0020</tt> */
+#define MXC_R_I2C_TX_CTRL0 \
+	((uint32_t)0x00000024UL) /**< Offset from I2C Base Address: <tt>       \
+				    0x0024</tt> */
+#define MXC_R_I2C_TX_CTRL1 \
+	((uint32_t)0x00000028UL) /**< Offset from I2C Base Address: <tt>       \
+				    0x0028</tt> */
+#define MXC_R_I2C_FIFO \
+	((uint32_t)0x0000002CUL) /**< Offset from I2C Base Address: <tt>       \
+				    0x002C</tt> */
+#define MXC_R_I2C_MASTER_CTRL \
+	((uint32_t)0x00000030UL) /**< Offset from I2C Base Address: <tt>       \
+				    0x0030</tt> */
+#define MXC_R_I2C_CLK_LO \
+	((uint32_t)0x00000034UL) /**< Offset from I2C Base Address: <tt>       \
+				    0x0034</tt> */
+#define MXC_R_I2C_CLK_HI \
+	((uint32_t)0x00000038UL) /**< Offset from I2C Base Address: <tt>       \
+				    0x0038</tt> */
+#define MXC_R_I2C_HS_CLK \
+	((uint32_t)0x0000003CUL) /**< Offset from I2C Base Address: <tt>       \
+				    0x003C</tt> */
+#define MXC_R_I2C_TIMEOUT \
+	((uint32_t)0x00000040UL) /**< Offset from I2C Base Address: <tt>       \
+				    0x0040</tt> */
+#define MXC_R_I2C_SLAVE_ADDR \
+	((uint32_t)0x00000044UL) /**< Offset from I2C Base Address: <tt>       \
+				    0x0044</tt> */
+#define MXC_R_I2C_DMA \
+	((uint32_t)0x00000048UL) /**< Offset from I2C Base Address: <tt>       \
+				    0x0048</tt> */
+
+/**
+ * Control Register0.
+ */
+#define MXC_F_I2C_CTRL_I2C_EN_POS 0 /**< CTRL_I2C_EN Position */
+#define MXC_F_I2C_CTRL_I2C_EN \
+	((uint32_t)(0x1UL     \
+		    << MXC_F_I2C_CTRL_I2C_EN_POS)) /**< CTRL_I2C_EN Mask */
+#define MXC_V_I2C_CTRL_I2C_EN_DIS \
+	((uint32_t)0x0UL) /**< CTRL_I2C_EN_DIS Value */
+#define MXC_S_I2C_CTRL_I2C_EN_DIS  \
+	(MXC_V_I2C_CTRL_I2C_EN_DIS \
+	 << MXC_F_I2C_CTRL_I2C_EN_POS) /**< CTRL_I2C_EN_DIS Setting */
+#define MXC_V_I2C_CTRL_I2C_EN_EN \
+	((uint32_t)0x1UL) /**< CTRL_I2C_EN_EN Value                            \
+			   */
+#define MXC_S_I2C_CTRL_I2C_EN_EN  \
+	(MXC_V_I2C_CTRL_I2C_EN_EN \
+	 << MXC_F_I2C_CTRL_I2C_EN_POS) /**< CTRL_I2C_EN_EN Setting */
+
+#define MXC_F_I2C_CTRL_MST_POS 1 /**< CTRL_MST Position */
+#define MXC_F_I2C_CTRL_MST \
+	((uint32_t)(0x1UL << MXC_F_I2C_CTRL_MST_POS)) /**< CTRL_MST Mask */
+#define MXC_V_I2C_CTRL_MST_SLAVE_MODE \
+	((uint32_t)0x0UL) /**< CTRL_MST_SLAVE_MODE Value */
+#define MXC_S_I2C_CTRL_MST_SLAVE_MODE  \
+	(MXC_V_I2C_CTRL_MST_SLAVE_MODE \
+	 << MXC_F_I2C_CTRL_MST_POS) /**< CTRL_MST_SLAVE_MODE Setting */
+#define MXC_V_I2C_CTRL_MST_MASTER_MODE \
+	((uint32_t)0x1UL) /**< CTRL_MST_MASTER_MODE Value */
+#define MXC_S_I2C_CTRL_MST_MASTER_MODE  \
+	(MXC_V_I2C_CTRL_MST_MASTER_MODE \
+	 << MXC_F_I2C_CTRL_MST_POS) /**< CTRL_MST_MASTER_MODE Setting */
+
+#define MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS 2 /**< CTRL_GEN_CALL_ADDR Position */
+#define MXC_F_I2C_CTRL_GEN_CALL_ADDR \
+	((uint32_t)(                 \
+		0x1UL                \
+		<< MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS)) /**< CTRL_GEN_CALL_ADDR  \
+							 Mask */
+#define MXC_V_I2C_CTRL_GEN_CALL_ADDR_DIS \
+	((uint32_t)0x0UL) /**< CTRL_GEN_CALL_ADDR_DIS Value */
+#define MXC_S_I2C_CTRL_GEN_CALL_ADDR_DIS  \
+	(MXC_V_I2C_CTRL_GEN_CALL_ADDR_DIS \
+	 << MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS) /**< CTRL_GEN_CALL_ADDR_DIS      \
+						 Setting */
+#define MXC_V_I2C_CTRL_GEN_CALL_ADDR_EN \
+	((uint32_t)0x1UL) /**< CTRL_GEN_CALL_ADDR_EN Value */
+#define MXC_S_I2C_CTRL_GEN_CALL_ADDR_EN  \
+	(MXC_V_I2C_CTRL_GEN_CALL_ADDR_EN \
+	 << MXC_F_I2C_CTRL_GEN_CALL_ADDR_POS) /**< CTRL_GEN_CALL_ADDR_EN       \
+						 Setting */
+
+#define MXC_F_I2C_CTRL_RX_MODE_POS 3 /**< CTRL_RX_MODE Position */
+#define MXC_F_I2C_CTRL_RX_MODE \
+	((uint32_t)(0x1UL      \
+		    << MXC_F_I2C_CTRL_RX_MODE_POS)) /**< CTRL_RX_MODE Mask */
+#define MXC_V_I2C_CTRL_RX_MODE_DIS \
+	((uint32_t)0x0UL) /**< CTRL_RX_MODE_DIS Value */
+#define MXC_S_I2C_CTRL_RX_MODE_DIS  \
+	(MXC_V_I2C_CTRL_RX_MODE_DIS \
+	 << MXC_F_I2C_CTRL_RX_MODE_POS) /**< CTRL_RX_MODE_DIS Setting */
+#define MXC_V_I2C_CTRL_RX_MODE_EN \
+	((uint32_t)0x1UL) /**< CTRL_RX_MODE_EN Value */
+#define MXC_S_I2C_CTRL_RX_MODE_EN  \
+	(MXC_V_I2C_CTRL_RX_MODE_EN \
+	 << MXC_F_I2C_CTRL_RX_MODE_POS) /**< CTRL_RX_MODE_EN Setting */
+
+#define MXC_F_I2C_CTRL_RX_MODE_ACK_POS 4 /**< CTRL_RX_MODE_ACK Position */
+#define MXC_F_I2C_CTRL_RX_MODE_ACK \
+	((uint32_t)(               \
+		0x1UL              \
+		<< MXC_F_I2C_CTRL_RX_MODE_ACK_POS)) /**< CTRL_RX_MODE_ACK  \
+							   Mask */
+#define MXC_V_I2C_CTRL_RX_MODE_ACK_ACK \
+	((uint32_t)0x0UL) /**< CTRL_RX_MODE_ACK_ACK Value */
+#define MXC_S_I2C_CTRL_RX_MODE_ACK_ACK  \
+	(MXC_V_I2C_CTRL_RX_MODE_ACK_ACK \
+	 << MXC_F_I2C_CTRL_RX_MODE_ACK_POS) /**< CTRL_RX_MODE_ACK_ACK Setting  \
+					     */
+#define MXC_V_I2C_CTRL_RX_MODE_ACK_NACK \
+	((uint32_t)0x1UL) /**< CTRL_RX_MODE_ACK_NACK Value */
+#define MXC_S_I2C_CTRL_RX_MODE_ACK_NACK  \
+	(MXC_V_I2C_CTRL_RX_MODE_ACK_NACK \
+	 << MXC_F_I2C_CTRL_RX_MODE_ACK_POS) /**< CTRL_RX_MODE_ACK_NACK Setting \
+					     */
+
+#define MXC_F_I2C_CTRL_SCL_OUT_POS 6 /**< CTRL_SCL_OUT Position */
+#define MXC_F_I2C_CTRL_SCL_OUT \
+	((uint32_t)(0x1UL      \
+		    << MXC_F_I2C_CTRL_SCL_OUT_POS)) /**< CTRL_SCL_OUT Mask */
+#define MXC_V_I2C_CTRL_SCL_OUT_DRIVE_SCL_LOW \
+	((uint32_t)0x0UL) /**< CTRL_SCL_OUT_DRIVE_SCL_LOW Value */
+#define MXC_S_I2C_CTRL_SCL_OUT_DRIVE_SCL_LOW  \
+	(MXC_V_I2C_CTRL_SCL_OUT_DRIVE_SCL_LOW \
+	 << MXC_F_I2C_CTRL_SCL_OUT_POS) /**< CTRL_SCL_OUT_DRIVE_SCL_LOW        \
+					   Setting */
+#define MXC_V_I2C_CTRL_SCL_OUT_RELEASE_SCL \
+	((uint32_t)0x1UL) /**< CTRL_SCL_OUT_RELEASE_SCL Value */
+#define MXC_S_I2C_CTRL_SCL_OUT_RELEASE_SCL  \
+	(MXC_V_I2C_CTRL_SCL_OUT_RELEASE_SCL \
+	 << MXC_F_I2C_CTRL_SCL_OUT_POS) /**< CTRL_SCL_OUT_RELEASE_SCL Setting  \
+					 */
+
+#define MXC_F_I2C_CTRL_SDA_OUT_POS 7 /**< CTRL_SDA_OUT Position */
+#define MXC_F_I2C_CTRL_SDA_OUT \
+	((uint32_t)(0x1UL      \
+		    << MXC_F_I2C_CTRL_SDA_OUT_POS)) /**< CTRL_SDA_OUT Mask */
+#define MXC_V_I2C_CTRL_SDA_OUT_DRIVE_SDA_LOW \
+	((uint32_t)0x0UL) /**< CTRL_SDA_OUT_DRIVE_SDA_LOW Value */
+#define MXC_S_I2C_CTRL_SDA_OUT_DRIVE_SDA_LOW  \
+	(MXC_V_I2C_CTRL_SDA_OUT_DRIVE_SDA_LOW \
+	 << MXC_F_I2C_CTRL_SDA_OUT_POS) /**< CTRL_SDA_OUT_DRIVE_SDA_LOW        \
+					   Setting */
+#define MXC_V_I2C_CTRL_SDA_OUT_RELEASE_SDA \
+	((uint32_t)0x1UL) /**< CTRL_SDA_OUT_RELEASE_SDA Value */
+#define MXC_S_I2C_CTRL_SDA_OUT_RELEASE_SDA  \
+	(MXC_V_I2C_CTRL_SDA_OUT_RELEASE_SDA \
+	 << MXC_F_I2C_CTRL_SDA_OUT_POS) /**< CTRL_SDA_OUT_RELEASE_SDA Setting  \
+					 */
+
+#define MXC_F_I2C_CTRL_SCL_POS 8 /**< CTRL_SCL Position */
+#define MXC_F_I2C_CTRL_SCL \
+	((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_POS)) /**< CTRL_SCL Mask */
+
+#define MXC_F_I2C_CTRL_SDA_POS 9 /**< CTRL_SDA Position */
+#define MXC_F_I2C_CTRL_SDA \
+	((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_POS)) /**< CTRL_SDA Mask */
+
+#define MXC_F_I2C_CTRL_SW_OUT_EN_POS 10 /**< CTRL_SW_OUT_EN Position */
+#define MXC_F_I2C_CTRL_SW_OUT_EN \
+	((uint32_t)(             \
+		0x1UL            \
+		<< MXC_F_I2C_CTRL_SW_OUT_EN_POS)) /**< CTRL_SW_OUT_EN Mask */
+#define MXC_V_I2C_CTRL_SW_OUT_EN_OUTPUTS_DISABLE \
+	((uint32_t)0x0UL) /**< CTRL_SW_OUT_EN_OUTPUTS_DISABLE Value */
+#define MXC_S_I2C_CTRL_SW_OUT_EN_OUTPUTS_DISABLE  \
+	(MXC_V_I2C_CTRL_SW_OUT_EN_OUTPUTS_DISABLE \
+	 << MXC_F_I2C_CTRL_SW_OUT_EN_POS) /**< CTRL_SW_OUT_EN_OUTPUTS_DISABLE  \
+					     Setting */
+#define MXC_V_I2C_CTRL_SW_OUT_EN_OUTPUTS_ENABLE \
+	((uint32_t)0x1UL) /**< CTRL_SW_OUT_EN_OUTPUTS_ENABLE Value */
+#define MXC_S_I2C_CTRL_SW_OUT_EN_OUTPUTS_ENABLE  \
+	(MXC_V_I2C_CTRL_SW_OUT_EN_OUTPUTS_ENABLE \
+	 << MXC_F_I2C_CTRL_SW_OUT_EN_POS) /**< CTRL_SW_OUT_EN_OUTPUTS_ENABLE   \
+					     Setting */
+
+#define MXC_F_I2C_CTRL_READ_POS 11 /**< CTRL_READ Position */
+#define MXC_F_I2C_CTRL_READ \
+	((uint32_t)(0x1UL << MXC_F_I2C_CTRL_READ_POS)) /**< CTRL_READ Mask */
+#define MXC_V_I2C_CTRL_READ_WRITE \
+	((uint32_t)0x0UL) /**< CTRL_READ_WRITE Value */
+#define MXC_S_I2C_CTRL_READ_WRITE  \
+	(MXC_V_I2C_CTRL_READ_WRITE \
+	 << MXC_F_I2C_CTRL_READ_POS) /**< CTRL_READ_WRITE Setting */
+#define MXC_V_I2C_CTRL_READ_READ \
+	((uint32_t)0x1UL) /**< CTRL_READ_READ Value                            \
+			   */
+#define MXC_S_I2C_CTRL_READ_READ  \
+	(MXC_V_I2C_CTRL_READ_READ \
+	 << MXC_F_I2C_CTRL_READ_POS) /**< CTRL_READ_READ Setting */
+
+#define MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS \
+	12 /**< CTRL_SCL_CLK_STRECH_DIS Position */
+#define MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS \
+	((uint32_t)(                      \
+		0x1UL                     \
+		<< MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS)) /**<                       \
+							      CTRL_SCL_CLK_STRECH_DIS \
+							      Mask */
+#define MXC_V_I2C_CTRL_SCL_CLK_STRECH_DIS_EN \
+	((uint32_t)0x0UL) /**< CTRL_SCL_CLK_STRECH_DIS_EN Value */
+#define MXC_S_I2C_CTRL_SCL_CLK_STRECH_DIS_EN  \
+	(MXC_V_I2C_CTRL_SCL_CLK_STRECH_DIS_EN \
+	 << MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS) /**<                          \
+						      CTRL_SCL_CLK_STRECH_DIS_EN \
+						      Setting */
+#define MXC_V_I2C_CTRL_SCL_CLK_STRECH_DIS_DIS \
+	((uint32_t)0x1UL) /**< CTRL_SCL_CLK_STRECH_DIS_DIS Value */
+#define MXC_S_I2C_CTRL_SCL_CLK_STRECH_DIS_DIS  \
+	(MXC_V_I2C_CTRL_SCL_CLK_STRECH_DIS_DIS \
+	 << MXC_F_I2C_CTRL_SCL_CLK_STRECH_DIS_POS) /**<                           \
+						      CTRL_SCL_CLK_STRECH_DIS_DIS \
+						      Setting */
+
+#define MXC_F_I2C_CTRL_SCL_PP_MODE_POS 13 /**< CTRL_SCL_PP_MODE Position */
+#define MXC_F_I2C_CTRL_SCL_PP_MODE \
+	((uint32_t)(               \
+		0x1UL              \
+		<< MXC_F_I2C_CTRL_SCL_PP_MODE_POS)) /**< CTRL_SCL_PP_MODE  \
+							   Mask */
+#define MXC_V_I2C_CTRL_SCL_PP_MODE_DIS \
+	((uint32_t)0x0UL) /**< CTRL_SCL_PP_MODE_DIS Value */
+#define MXC_S_I2C_CTRL_SCL_PP_MODE_DIS  \
+	(MXC_V_I2C_CTRL_SCL_PP_MODE_DIS \
+	 << MXC_F_I2C_CTRL_SCL_PP_MODE_POS) /**< CTRL_SCL_PP_MODE_DIS Setting  \
+					     */
+#define MXC_V_I2C_CTRL_SCL_PP_MODE_EN \
+	((uint32_t)0x1UL) /**< CTRL_SCL_PP_MODE_EN Value */
+#define MXC_S_I2C_CTRL_SCL_PP_MODE_EN  \
+	(MXC_V_I2C_CTRL_SCL_PP_MODE_EN \
+	 << MXC_F_I2C_CTRL_SCL_PP_MODE_POS) /**< CTRL_SCL_PP_MODE_EN Setting   \
+					     */
+
+#define MXC_F_I2C_CTRL_HS_MODE_POS 15 /**< CTRL_HS_MODE Position */
+#define MXC_F_I2C_CTRL_HS_MODE \
+	((uint32_t)(0x1UL      \
+		    << MXC_F_I2C_CTRL_HS_MODE_POS)) /**< CTRL_HS_MODE Mask */
+#define MXC_V_I2C_CTRL_HS_MODE_DIS \
+	((uint32_t)0x0UL) /**< CTRL_HS_MODE_DIS Value */
+#define MXC_S_I2C_CTRL_HS_MODE_DIS  \
+	(MXC_V_I2C_CTRL_HS_MODE_DIS \
+	 << MXC_F_I2C_CTRL_HS_MODE_POS) /**< CTRL_HS_MODE_DIS Setting */
+#define MXC_V_I2C_CTRL_HS_MODE_EN \
+	((uint32_t)0x1UL) /**< CTRL_HS_MODE_EN Value */
+#define MXC_S_I2C_CTRL_HS_MODE_EN  \
+	(MXC_V_I2C_CTRL_HS_MODE_EN \
+	 << MXC_F_I2C_CTRL_HS_MODE_POS) /**< CTRL_HS_MODE_EN Setting */
+
+/**
+ * I2C_STATUS I2C_STATUS
+ */
+#define MXC_F_I2C_STATUS_BUS_POS 0 /**< STATUS_BUS Position */
+#define MXC_F_I2C_STATUS_BUS \
+	((uint32_t)(0x1UL    \
+		    << MXC_F_I2C_STATUS_BUS_POS)) /**< STATUS_BUS Mask   \
+							 */
+#define MXC_V_I2C_STATUS_BUS_IDLE \
+	((uint32_t)0x0UL) /**< STATUS_BUS_IDLE Value */
+#define MXC_S_I2C_STATUS_BUS_IDLE  \
+	(MXC_V_I2C_STATUS_BUS_IDLE \
+	 << MXC_F_I2C_STATUS_BUS_POS) /**< STATUS_BUS_IDLE Setting */
+#define MXC_V_I2C_STATUS_BUS_BUSY \
+	((uint32_t)0x1UL) /**< STATUS_BUS_BUSY Value */
+#define MXC_S_I2C_STATUS_BUS_BUSY  \
+	(MXC_V_I2C_STATUS_BUS_BUSY \
+	 << MXC_F_I2C_STATUS_BUS_POS) /**< STATUS_BUS_BUSY Setting */
+
+#define MXC_F_I2C_STATUS_RX_EMPTY_POS 1 /**< STATUS_RX_EMPTY Position */
+#define MXC_F_I2C_STATUS_RX_EMPTY \
+	((uint32_t)(0x1UL         \
+		    << MXC_F_I2C_STATUS_RX_EMPTY_POS)) /**< STATUS_RX_EMPTY  \
+							    Mask */
+#define MXC_V_I2C_STATUS_RX_EMPTY_NOT_EMPTY \
+	((uint32_t)0x0UL) /**< STATUS_RX_EMPTY_NOT_EMPTY Value */
+#define MXC_S_I2C_STATUS_RX_EMPTY_NOT_EMPTY  \
+	(MXC_V_I2C_STATUS_RX_EMPTY_NOT_EMPTY \
+	 << MXC_F_I2C_STATUS_RX_EMPTY_POS) /**< STATUS_RX_EMPTY_NOT_EMPTY      \
+					      Setting */
+#define MXC_V_I2C_STATUS_RX_EMPTY_EMPTY \
+	((uint32_t)0x1UL) /**< STATUS_RX_EMPTY_EMPTY Value */
+#define MXC_S_I2C_STATUS_RX_EMPTY_EMPTY  \
+	(MXC_V_I2C_STATUS_RX_EMPTY_EMPTY \
+	 << MXC_F_I2C_STATUS_RX_EMPTY_POS) /**< STATUS_RX_EMPTY_EMPTY Setting  \
+					    */
+
+#define MXC_F_I2C_STATUS_RX_FULL_POS 2 /**< STATUS_RX_FULL Position */
+#define MXC_F_I2C_STATUS_RX_FULL \
+	((uint32_t)(             \
+		0x1UL            \
+		<< MXC_F_I2C_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */
+#define MXC_V_I2C_STATUS_RX_FULL_NOT_FULL \
+	((uint32_t)0x0UL) /**< STATUS_RX_FULL_NOT_FULL Value */
+#define MXC_S_I2C_STATUS_RX_FULL_NOT_FULL  \
+	(MXC_V_I2C_STATUS_RX_FULL_NOT_FULL \
+	 << MXC_F_I2C_STATUS_RX_FULL_POS) /**< STATUS_RX_FULL_NOT_FULL Setting \
+					   */
+#define MXC_V_I2C_STATUS_RX_FULL_FULL \
+	((uint32_t)0x1UL) /**< STATUS_RX_FULL_FULL Value */
+#define MXC_S_I2C_STATUS_RX_FULL_FULL  \
+	(MXC_V_I2C_STATUS_RX_FULL_FULL \
+	 << MXC_F_I2C_STATUS_RX_FULL_POS) /**< STATUS_RX_FULL_FULL Setting */
+
+#define MXC_F_I2C_STATUS_TX_EMPTY_POS 3 /**< STATUS_TX_EMPTY Position */
+#define MXC_F_I2C_STATUS_TX_EMPTY \
+	((uint32_t)(0x1UL         \
+		    << MXC_F_I2C_STATUS_TX_EMPTY_POS)) /**< STATUS_TX_EMPTY  \
+							    Mask */
+#define MXC_V_I2C_STATUS_TX_EMPTY_NOT_EMPTY \
+	((uint32_t)0x0UL) /**< STATUS_TX_EMPTY_NOT_EMPTY Value */
+#define MXC_S_I2C_STATUS_TX_EMPTY_NOT_EMPTY  \
+	(MXC_V_I2C_STATUS_TX_EMPTY_NOT_EMPTY \
+	 << MXC_F_I2C_STATUS_TX_EMPTY_POS) /**< STATUS_TX_EMPTY_NOT_EMPTY      \
+					      Setting */
+#define MXC_V_I2C_STATUS_TX_EMPTY_EMPTY \
+	((uint32_t)0x1UL) /**< STATUS_TX_EMPTY_EMPTY Value */
+#define MXC_S_I2C_STATUS_TX_EMPTY_EMPTY  \
+	(MXC_V_I2C_STATUS_TX_EMPTY_EMPTY \
+	 << MXC_F_I2C_STATUS_TX_EMPTY_POS) /**< STATUS_TX_EMPTY_EMPTY Setting  \
+					    */
+
+#define MXC_F_I2C_STATUS_TX_FULL_POS 4 /**< STATUS_TX_FULL Position */
+#define MXC_F_I2C_STATUS_TX_FULL \
+	((uint32_t)(             \
+		0x1UL            \
+		<< MXC_F_I2C_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */
+#define MXC_V_I2C_STATUS_TX_FULL_NOT_EMPTY \
+	((uint32_t)0x0UL) /**< STATUS_TX_FULL_NOT_EMPTY Value */
+#define MXC_S_I2C_STATUS_TX_FULL_NOT_EMPTY  \
+	(MXC_V_I2C_STATUS_TX_FULL_NOT_EMPTY \
+	 << MXC_F_I2C_STATUS_TX_FULL_POS) /**< STATUS_TX_FULL_NOT_EMPTY        \
+					     Setting */
+#define MXC_V_I2C_STATUS_TX_FULL_EMPTY \
+	((uint32_t)0x1UL) /**< STATUS_TX_FULL_EMPTY Value */
+#define MXC_S_I2C_STATUS_TX_FULL_EMPTY  \
+	(MXC_V_I2C_STATUS_TX_FULL_EMPTY \
+	 << MXC_F_I2C_STATUS_TX_FULL_POS) /**< STATUS_TX_FULL_EMPTY Setting */
+
+#define MXC_F_I2C_STATUS_CLK_MODE_POS 5 /**< STATUS_CLK_MODE Position */
+#define MXC_F_I2C_STATUS_CLK_MODE \
+	((uint32_t)(0x1UL         \
+		    << MXC_F_I2C_STATUS_CLK_MODE_POS)) /**< STATUS_CLK_MODE  \
+							    Mask */
+#define MXC_V_I2C_STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK \
+	((uint32_t)0x0UL) /**< STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK  \
+			     Value */
+#define MXC_S_I2C_STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK  \
+	(MXC_V_I2C_STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK \
+	 << MXC_F_I2C_STATUS_CLK_MODE_POS) /**<                                              \
+					      STATUS_CLK_MODE_NOT_ACTIVELY_DRIVING_SCL_CLOCK \
+					      Setting */
+#define MXC_V_I2C_STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK \
+	((uint32_t)0x1UL) /**< STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK      \
+			     Value */
+#define MXC_S_I2C_STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK  \
+	(MXC_V_I2C_STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK \
+	 << MXC_F_I2C_STATUS_CLK_MODE_POS) /**<                                          \
+					      STATUS_CLK_MODE_ACTIVELY_DRIVING_SCL_CLOCK \
+					      Setting */
+
+#define MXC_F_I2C_STATUS_STATUS_POS 8 /**< STATUS_STATUS Position */
+#define MXC_F_I2C_STATUS_STATUS \
+	((uint32_t)(            \
+		0xFUL           \
+		<< MXC_F_I2C_STATUS_STATUS_POS)) /**< STATUS_STATUS Mask */
+#define MXC_V_I2C_STATUS_STATUS_IDLE \
+	((uint32_t)0x0UL) /**< STATUS_STATUS_IDLE Value */
+#define MXC_S_I2C_STATUS_STATUS_IDLE  \
+	(MXC_V_I2C_STATUS_STATUS_IDLE \
+	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_IDLE Setting */
+#define MXC_V_I2C_STATUS_STATUS_MTX_ADDR \
+	((uint32_t)0x1UL) /**< STATUS_STATUS_MTX_ADDR Value */
+#define MXC_S_I2C_STATUS_STATUS_MTX_ADDR  \
+	(MXC_V_I2C_STATUS_STATUS_MTX_ADDR \
+	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_MTX_ADDR Setting   \
+					  */
+#define MXC_V_I2C_STATUS_STATUS_MRX_ADDR_ACK \
+	((uint32_t)0x2UL) /**< STATUS_STATUS_MRX_ADDR_ACK Value */
+#define MXC_S_I2C_STATUS_STATUS_MRX_ADDR_ACK  \
+	(MXC_V_I2C_STATUS_STATUS_MRX_ADDR_ACK \
+	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_MRX_ADDR_ACK       \
+					    Setting */
+#define MXC_V_I2C_STATUS_STATUS_MTX_EX_ADDR \
+	((uint32_t)0x3UL) /**< STATUS_STATUS_MTX_EX_ADDR Value */
+#define MXC_S_I2C_STATUS_STATUS_MTX_EX_ADDR  \
+	(MXC_V_I2C_STATUS_STATUS_MTX_EX_ADDR \
+	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_MTX_EX_ADDR        \
+					    Setting */
+#define MXC_V_I2C_STATUS_STATUS_MRX_EX_ADDR \
+	((uint32_t)0x4UL) /**< STATUS_STATUS_MRX_EX_ADDR Value */
+#define MXC_S_I2C_STATUS_STATUS_MRX_EX_ADDR  \
+	(MXC_V_I2C_STATUS_STATUS_MRX_EX_ADDR \
+	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_MRX_EX_ADDR        \
+					    Setting */
+#define MXC_V_I2C_STATUS_STATUS_SRX_ADDR \
+	((uint32_t)0x5UL) /**< STATUS_STATUS_SRX_ADDR Value */
+#define MXC_S_I2C_STATUS_STATUS_SRX_ADDR  \
+	(MXC_V_I2C_STATUS_STATUS_SRX_ADDR \
+	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_SRX_ADDR Setting   \
+					  */
+#define MXC_V_I2C_STATUS_STATUS_STX_ADDR_ACK \
+	((uint32_t)0x6UL) /**< STATUS_STATUS_STX_ADDR_ACK Value */
+#define MXC_S_I2C_STATUS_STATUS_STX_ADDR_ACK  \
+	(MXC_V_I2C_STATUS_STATUS_STX_ADDR_ACK \
+	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_STX_ADDR_ACK       \
+					    Setting */
+#define MXC_V_I2C_STATUS_STATUS_SRX_EX_ADDR \
+	((uint32_t)0x7UL) /**< STATUS_STATUS_SRX_EX_ADDR Value */
+#define MXC_S_I2C_STATUS_STATUS_SRX_EX_ADDR  \
+	(MXC_V_I2C_STATUS_STATUS_SRX_EX_ADDR \
+	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_SRX_EX_ADDR        \
+					    Setting */
+#define MXC_V_I2C_STATUS_STATUS_STX_EX_ADDR_ACK \
+	((uint32_t)0x8UL) /**< STATUS_STATUS_STX_EX_ADDR_ACK Value */
+#define MXC_S_I2C_STATUS_STATUS_STX_EX_ADDR_ACK  \
+	(MXC_V_I2C_STATUS_STATUS_STX_EX_ADDR_ACK \
+	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_STX_EX_ADDR_ACK    \
+					    Setting */
+#define MXC_V_I2C_STATUS_STATUS_TX \
+	((uint32_t)0x9UL) /**< STATUS_STATUS_TX Value */
+#define MXC_S_I2C_STATUS_STATUS_TX  \
+	(MXC_V_I2C_STATUS_STATUS_TX \
+	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_TX Setting */
+#define MXC_V_I2C_STATUS_STATUS_RX_ACK \
+	((uint32_t)0xAUL) /**< STATUS_STATUS_RX_ACK Value */
+#define MXC_S_I2C_STATUS_STATUS_RX_ACK  \
+	(MXC_V_I2C_STATUS_STATUS_RX_ACK \
+	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_RX_ACK Setting */
+#define MXC_V_I2C_STATUS_STATUS_RX \
+	((uint32_t)0xBUL) /**< STATUS_STATUS_RX Value */
+#define MXC_S_I2C_STATUS_STATUS_RX  \
+	(MXC_V_I2C_STATUS_STATUS_RX \
+	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_RX Setting */
+#define MXC_V_I2C_STATUS_STATUS_TX_ACK \
+	((uint32_t)0xCUL) /**< STATUS_STATUS_TX_ACK Value */
+#define MXC_S_I2C_STATUS_STATUS_TX_ACK  \
+	(MXC_V_I2C_STATUS_STATUS_TX_ACK \
+	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_TX_ACK Setting */
+#define MXC_V_I2C_STATUS_STATUS_NACK \
+	((uint32_t)0xDUL) /**< STATUS_STATUS_NACK Value */
+#define MXC_S_I2C_STATUS_STATUS_NACK  \
+	(MXC_V_I2C_STATUS_STATUS_NACK \
+	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_NACK Setting */
+#define MXC_V_I2C_STATUS_STATUS_BY_ST \
+	((uint32_t)0xFUL) /**< STATUS_STATUS_BY_ST Value */
+#define MXC_S_I2C_STATUS_STATUS_BY_ST  \
+	(MXC_V_I2C_STATUS_STATUS_BY_ST \
+	 << MXC_F_I2C_STATUS_STATUS_POS) /**< STATUS_STATUS_BY_ST Setting */
+
+/**
+ * Interrupt Status Register.
+ */
+#define MXC_F_I2C_INT_FL0_DONE_POS 0 /**< INT_FL0_DONE Position */
+#define MXC_F_I2C_INT_FL0_DONE \
+	((uint32_t)(0x1UL      \
+		    << MXC_F_I2C_INT_FL0_DONE_POS)) /**< INT_FL0_DONE Mask */
+#define MXC_V_I2C_INT_FL0_DONE_INACTIVE \
+	((uint32_t)0x0UL) /**< INT_FL0_DONE_INACTIVE Value */
+#define MXC_S_I2C_INT_FL0_DONE_INACTIVE  \
+	(MXC_V_I2C_INT_FL0_DONE_INACTIVE \
+	 << MXC_F_I2C_INT_FL0_DONE_POS) /**< INT_FL0_DONE_INACTIVE Setting */
+#define MXC_V_I2C_INT_FL0_DONE_PENDING \
+	((uint32_t)0x1UL) /**< INT_FL0_DONE_PENDING Value */
+#define MXC_S_I2C_INT_FL0_DONE_PENDING  \
+	(MXC_V_I2C_INT_FL0_DONE_PENDING \
+	 << MXC_F_I2C_INT_FL0_DONE_POS) /**< INT_FL0_DONE_PENDING Setting */
+
+#define MXC_F_I2C_INT_FL0_RX_MODE_POS 1 /**< INT_FL0_RX_MODE Position */
+#define MXC_F_I2C_INT_FL0_RX_MODE \
+	((uint32_t)(0x1UL         \
+		    << MXC_F_I2C_INT_FL0_RX_MODE_POS)) /**< INT_FL0_RX_MODE  \
+							    Mask */
+#define MXC_V_I2C_INT_FL0_RX_MODE_INACTIVE \
+	((uint32_t)0x0UL) /**< INT_FL0_RX_MODE_INACTIVE Value */
+#define MXC_S_I2C_INT_FL0_RX_MODE_INACTIVE  \
+	(MXC_V_I2C_INT_FL0_RX_MODE_INACTIVE \
+	 << MXC_F_I2C_INT_FL0_RX_MODE_POS) /**< INT_FL0_RX_MODE_INACTIVE       \
+					      Setting */
+#define MXC_V_I2C_INT_FL0_RX_MODE_PENDING \
+	((uint32_t)0x1UL) /**< INT_FL0_RX_MODE_PENDING Value */
+#define MXC_S_I2C_INT_FL0_RX_MODE_PENDING  \
+	(MXC_V_I2C_INT_FL0_RX_MODE_PENDING \
+	 << MXC_F_I2C_INT_FL0_RX_MODE_POS) /**< INT_FL0_RX_MODE_PENDING        \
+					      Setting */
+
+#define MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS \
+	2 /**< INT_FL0_GEN_CALL_ADDR Position */
+#define MXC_F_I2C_INT_FL0_GEN_CALL_ADDR \
+	((uint32_t)(                    \
+		0x1UL                   \
+		<< MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS)) /**<                     \
+							    INT_FL0_GEN_CALL_ADDR \
+							    Mask */
+#define MXC_V_I2C_INT_FL0_GEN_CALL_ADDR_INACTIVE \
+	((uint32_t)0x0UL) /**< INT_FL0_GEN_CALL_ADDR_INACTIVE Value */
+#define MXC_S_I2C_INT_FL0_GEN_CALL_ADDR_INACTIVE  \
+	(MXC_V_I2C_INT_FL0_GEN_CALL_ADDR_INACTIVE \
+	 << MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS) /**<                              \
+						    INT_FL0_GEN_CALL_ADDR_INACTIVE \
+						    Setting */
+#define MXC_V_I2C_INT_FL0_GEN_CALL_ADDR_PENDING \
+	((uint32_t)0x1UL) /**< INT_FL0_GEN_CALL_ADDR_PENDING Value */
+#define MXC_S_I2C_INT_FL0_GEN_CALL_ADDR_PENDING  \
+	(MXC_V_I2C_INT_FL0_GEN_CALL_ADDR_PENDING \
+	 << MXC_F_I2C_INT_FL0_GEN_CALL_ADDR_POS) /**<                             \
+						    INT_FL0_GEN_CALL_ADDR_PENDING \
+						    Setting */
+
+#define MXC_F_I2C_INT_FL0_ADDR_MATCH_POS 3 /**< INT_FL0_ADDR_MATCH Position */
+#define MXC_F_I2C_INT_FL0_ADDR_MATCH \
+	((uint32_t)(                 \
+		0x1UL                \
+		<< MXC_F_I2C_INT_FL0_ADDR_MATCH_POS)) /**< INT_FL0_ADDR_MATCH  \
+							 Mask */
+#define MXC_V_I2C_INT_FL0_ADDR_MATCH_INACTIVE \
+	((uint32_t)0x0UL) /**< INT_FL0_ADDR_MATCH_INACTIVE Value */
+#define MXC_S_I2C_INT_FL0_ADDR_MATCH_INACTIVE  \
+	(MXC_V_I2C_INT_FL0_ADDR_MATCH_INACTIVE \
+	 << MXC_F_I2C_INT_FL0_ADDR_MATCH_POS) /**< INT_FL0_ADDR_MATCH_INACTIVE \
+						 Setting */
+#define MXC_V_I2C_INT_FL0_ADDR_MATCH_PENDING \
+	((uint32_t)0x1UL) /**< INT_FL0_ADDR_MATCH_PENDING Value */
+#define MXC_S_I2C_INT_FL0_ADDR_MATCH_PENDING  \
+	(MXC_V_I2C_INT_FL0_ADDR_MATCH_PENDING \
+	 << MXC_F_I2C_INT_FL0_ADDR_MATCH_POS) /**< INT_FL0_ADDR_MATCH_PENDING  \
+						 Setting */
+
+#define MXC_F_I2C_INT_FL0_RX_THRESH_POS 4 /**< INT_FL0_RX_THRESH Position */
+#define MXC_F_I2C_INT_FL0_RX_THRESH \
+	((uint32_t)(                \
+		0x1UL               \
+		<< MXC_F_I2C_INT_FL0_RX_THRESH_POS)) /**< INT_FL0_RX_THRESH    \
+							Mask */
+#define MXC_V_I2C_INT_FL0_RX_THRESH_INACTIVE \
+	((uint32_t)0x0UL) /**< INT_FL0_RX_THRESH_INACTIVE Value */
+#define MXC_S_I2C_INT_FL0_RX_THRESH_INACTIVE  \
+	(MXC_V_I2C_INT_FL0_RX_THRESH_INACTIVE \
+	 << MXC_F_I2C_INT_FL0_RX_THRESH_POS) /**< INT_FL0_RX_THRESH_INACTIVE   \
+						Setting */
+#define MXC_V_I2C_INT_FL0_RX_THRESH_PENDING \
+	((uint32_t)0x1UL) /**< INT_FL0_RX_THRESH_PENDING Value */
+#define MXC_S_I2C_INT_FL0_RX_THRESH_PENDING  \
+	(MXC_V_I2C_INT_FL0_RX_THRESH_PENDING \
+	 << MXC_F_I2C_INT_FL0_RX_THRESH_POS) /**< INT_FL0_RX_THRESH_PENDING    \
+						Setting */
+
+#define MXC_F_I2C_INT_FL0_TX_THRESH_POS 5 /**< INT_FL0_TX_THRESH Position */
+#define MXC_F_I2C_INT_FL0_TX_THRESH \
+	((uint32_t)(                \
+		0x1UL               \
+		<< MXC_F_I2C_INT_FL0_TX_THRESH_POS)) /**< INT_FL0_TX_THRESH    \
+							Mask */
+#define MXC_V_I2C_INT_FL0_TX_THRESH_INACTIVE \
+	((uint32_t)0x0UL) /**< INT_FL0_TX_THRESH_INACTIVE Value */
+#define MXC_S_I2C_INT_FL0_TX_THRESH_INACTIVE  \
+	(MXC_V_I2C_INT_FL0_TX_THRESH_INACTIVE \
+	 << MXC_F_I2C_INT_FL0_TX_THRESH_POS) /**< INT_FL0_TX_THRESH_INACTIVE   \
+						Setting */
+#define MXC_V_I2C_INT_FL0_TX_THRESH_PENDING \
+	((uint32_t)0x1UL) /**< INT_FL0_TX_THRESH_PENDING Value */
+#define MXC_S_I2C_INT_FL0_TX_THRESH_PENDING  \
+	(MXC_V_I2C_INT_FL0_TX_THRESH_PENDING \
+	 << MXC_F_I2C_INT_FL0_TX_THRESH_POS) /**< INT_FL0_TX_THRESH_PENDING    \
+						Setting */
+
+#define MXC_F_I2C_INT_FL0_STOP_POS 6 /**< INT_FL0_STOP Position */
+#define MXC_F_I2C_INT_FL0_STOP \
+	((uint32_t)(0x1UL      \
+		    << MXC_F_I2C_INT_FL0_STOP_POS)) /**< INT_FL0_STOP Mask */
+#define MXC_V_I2C_INT_FL0_STOP_INACTIVE \
+	((uint32_t)0x0UL) /**< INT_FL0_STOP_INACTIVE Value */
+#define MXC_S_I2C_INT_FL0_STOP_INACTIVE  \
+	(MXC_V_I2C_INT_FL0_STOP_INACTIVE \
+	 << MXC_F_I2C_INT_FL0_STOP_POS) /**< INT_FL0_STOP_INACTIVE Setting */
+#define MXC_V_I2C_INT_FL0_STOP_PENDING \
+	((uint32_t)0x1UL) /**< INT_FL0_STOP_PENDING Value */
+#define MXC_S_I2C_INT_FL0_STOP_PENDING  \
+	(MXC_V_I2C_INT_FL0_STOP_PENDING \
+	 << MXC_F_I2C_INT_FL0_STOP_POS) /**< INT_FL0_STOP_PENDING Setting */
+
+#define MXC_F_I2C_INT_FL0_ADDR_ACK_POS 7 /**< INT_FL0_ADDR_ACK Position */
+#define MXC_F_I2C_INT_FL0_ADDR_ACK \
+	((uint32_t)(               \
+		0x1UL              \
+		<< MXC_F_I2C_INT_FL0_ADDR_ACK_POS)) /**< INT_FL0_ADDR_ACK  \
+							   Mask */
+#define MXC_V_I2C_INT_FL0_ADDR_ACK_INACTIVE \
+	((uint32_t)0x0UL) /**< INT_FL0_ADDR_ACK_INACTIVE Value */
+#define MXC_S_I2C_INT_FL0_ADDR_ACK_INACTIVE  \
+	(MXC_V_I2C_INT_FL0_ADDR_ACK_INACTIVE \
+	 << MXC_F_I2C_INT_FL0_ADDR_ACK_POS) /**< INT_FL0_ADDR_ACK_INACTIVE     \
+					       Setting */
+#define MXC_V_I2C_INT_FL0_ADDR_ACK_PENDING \
+	((uint32_t)0x1UL) /**< INT_FL0_ADDR_ACK_PENDING Value */
+#define MXC_S_I2C_INT_FL0_ADDR_ACK_PENDING  \
+	(MXC_V_I2C_INT_FL0_ADDR_ACK_PENDING \
+	 << MXC_F_I2C_INT_FL0_ADDR_ACK_POS) /**< INT_FL0_ADDR_ACK_PENDING      \
+					       Setting */
+
+#define MXC_F_I2C_INT_FL0_ARB_ER_POS 8 /**< INT_FL0_ARB_ER Position */
+#define MXC_F_I2C_INT_FL0_ARB_ER \
+	((uint32_t)(             \
+		0x1UL            \
+		<< MXC_F_I2C_INT_FL0_ARB_ER_POS)) /**< INT_FL0_ARB_ER Mask */
+#define MXC_V_I2C_INT_FL0_ARB_ER_INACTIVE \
+	((uint32_t)0x0UL) /**< INT_FL0_ARB_ER_INACTIVE Value */
+#define MXC_S_I2C_INT_FL0_ARB_ER_INACTIVE  \
+	(MXC_V_I2C_INT_FL0_ARB_ER_INACTIVE \
+	 << MXC_F_I2C_INT_FL0_ARB_ER_POS) /**< INT_FL0_ARB_ER_INACTIVE Setting \
+					   */
+#define MXC_V_I2C_INT_FL0_ARB_ER_PENDING \
+	((uint32_t)0x1UL) /**< INT_FL0_ARB_ER_PENDING Value */
+#define MXC_S_I2C_INT_FL0_ARB_ER_PENDING  \
+	(MXC_V_I2C_INT_FL0_ARB_ER_PENDING \
+	 << MXC_F_I2C_INT_FL0_ARB_ER_POS) /**< INT_FL0_ARB_ER_PENDING Setting  \
+					   */
+
+#define MXC_F_I2C_INT_FL0_TO_ER_POS 9 /**< INT_FL0_TO_ER Position */
+#define MXC_F_I2C_INT_FL0_TO_ER \
+	((uint32_t)(            \
+		0x1UL           \
+		<< MXC_F_I2C_INT_FL0_TO_ER_POS)) /**< INT_FL0_TO_ER Mask */
+#define MXC_V_I2C_INT_FL0_TO_ER_INACTIVE \
+	((uint32_t)0x0UL) /**< INT_FL0_TO_ER_INACTIVE Value */
+#define MXC_S_I2C_INT_FL0_TO_ER_INACTIVE  \
+	(MXC_V_I2C_INT_FL0_TO_ER_INACTIVE \
+	 << MXC_F_I2C_INT_FL0_TO_ER_POS) /**< INT_FL0_TO_ER_INACTIVE Setting   \
+					  */
+#define MXC_V_I2C_INT_FL0_TO_ER_PENDING \
+	((uint32_t)0x1UL) /**< INT_FL0_TO_ER_PENDING Value */
+#define MXC_S_I2C_INT_FL0_TO_ER_PENDING  \
+	(MXC_V_I2C_INT_FL0_TO_ER_PENDING \
+	 << MXC_F_I2C_INT_FL0_TO_ER_POS) /**< INT_FL0_TO_ER_PENDING Setting */
+
+#define MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS \
+	10 /**< INT_FL0_ADDR_NACK_ER Position */
+#define MXC_F_I2C_INT_FL0_ADDR_NACK_ER \
+	((uint32_t)(                   \
+		0x1UL                  \
+		<< MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS)) /**<                    \
+							   INT_FL0_ADDR_NACK_ER \
+							   Mask */
+#define MXC_V_I2C_INT_FL0_ADDR_NACK_ER_INACTIVE \
+	((uint32_t)0x0UL) /**< INT_FL0_ADDR_NACK_ER_INACTIVE Value */
+#define MXC_S_I2C_INT_FL0_ADDR_NACK_ER_INACTIVE  \
+	(MXC_V_I2C_INT_FL0_ADDR_NACK_ER_INACTIVE \
+	 << MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS) /**<                             \
+						   INT_FL0_ADDR_NACK_ER_INACTIVE \
+						   Setting */
+#define MXC_V_I2C_INT_FL0_ADDR_NACK_ER_PENDING \
+	((uint32_t)0x1UL) /**< INT_FL0_ADDR_NACK_ER_PENDING Value */
+#define MXC_S_I2C_INT_FL0_ADDR_NACK_ER_PENDING  \
+	(MXC_V_I2C_INT_FL0_ADDR_NACK_ER_PENDING \
+	 << MXC_F_I2C_INT_FL0_ADDR_NACK_ER_POS) /**<                            \
+						   INT_FL0_ADDR_NACK_ER_PENDING \
+						   Setting */
+
+#define MXC_F_I2C_INT_FL0_DATA_ER_POS 11 /**< INT_FL0_DATA_ER Position */
+#define MXC_F_I2C_INT_FL0_DATA_ER \
+	((uint32_t)(0x1UL         \
+		    << MXC_F_I2C_INT_FL0_DATA_ER_POS)) /**< INT_FL0_DATA_ER  \
+							    Mask */
+#define MXC_V_I2C_INT_FL0_DATA_ER_INACTIVE \
+	((uint32_t)0x0UL) /**< INT_FL0_DATA_ER_INACTIVE Value */
+#define MXC_S_I2C_INT_FL0_DATA_ER_INACTIVE  \
+	(MXC_V_I2C_INT_FL0_DATA_ER_INACTIVE \
+	 << MXC_F_I2C_INT_FL0_DATA_ER_POS) /**< INT_FL0_DATA_ER_INACTIVE       \
+					      Setting */
+#define MXC_V_I2C_INT_FL0_DATA_ER_PENDING \
+	((uint32_t)0x1UL) /**< INT_FL0_DATA_ER_PENDING Value */
+#define MXC_S_I2C_INT_FL0_DATA_ER_PENDING  \
+	(MXC_V_I2C_INT_FL0_DATA_ER_PENDING \
+	 << MXC_F_I2C_INT_FL0_DATA_ER_POS) /**< INT_FL0_DATA_ER_PENDING        \
+					      Setting */
+
+#define MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS \
+	12 /**< INT_FL0_DO_NOT_RESP_ER Position */
+#define MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER \
+	((uint32_t)(                     \
+		0x1UL                    \
+		<< MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS)) /**<                      \
+							     INT_FL0_DO_NOT_RESP_ER \
+							     Mask */
+#define MXC_V_I2C_INT_FL0_DO_NOT_RESP_ER_INACTIVE \
+	((uint32_t)0x0UL) /**< INT_FL0_DO_NOT_RESP_ER_INACTIVE Value */
+#define MXC_S_I2C_INT_FL0_DO_NOT_RESP_ER_INACTIVE  \
+	(MXC_V_I2C_INT_FL0_DO_NOT_RESP_ER_INACTIVE \
+	 << MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS) /**<                               \
+						     INT_FL0_DO_NOT_RESP_ER_INACTIVE \
+						     Setting */
+#define MXC_V_I2C_INT_FL0_DO_NOT_RESP_ER_PENDING \
+	((uint32_t)0x1UL) /**< INT_FL0_DO_NOT_RESP_ER_PENDING Value */
+#define MXC_S_I2C_INT_FL0_DO_NOT_RESP_ER_PENDING  \
+	(MXC_V_I2C_INT_FL0_DO_NOT_RESP_ER_PENDING \
+	 << MXC_F_I2C_INT_FL0_DO_NOT_RESP_ER_POS) /**<                              \
+						     INT_FL0_DO_NOT_RESP_ER_PENDING \
+						     Setting */
+
+#define MXC_F_I2C_INT_FL0_START_ER_POS 13 /**< INT_FL0_START_ER Position */
+#define MXC_F_I2C_INT_FL0_START_ER \
+	((uint32_t)(               \
+		0x1UL              \
+		<< MXC_F_I2C_INT_FL0_START_ER_POS)) /**< INT_FL0_START_ER  \
+							   Mask */
+#define MXC_V_I2C_INT_FL0_START_ER_INACTIVE \
+	((uint32_t)0x0UL) /**< INT_FL0_START_ER_INACTIVE Value */
+#define MXC_S_I2C_INT_FL0_START_ER_INACTIVE  \
+	(MXC_V_I2C_INT_FL0_START_ER_INACTIVE \
+	 << MXC_F_I2C_INT_FL0_START_ER_POS) /**< INT_FL0_START_ER_INACTIVE     \
+					       Setting */
+#define MXC_V_I2C_INT_FL0_START_ER_PENDING \
+	((uint32_t)0x1UL) /**< INT_FL0_START_ER_PENDING Value */
+#define MXC_S_I2C_INT_FL0_START_ER_PENDING  \
+	(MXC_V_I2C_INT_FL0_START_ER_PENDING \
+	 << MXC_F_I2C_INT_FL0_START_ER_POS) /**< INT_FL0_START_ER_PENDING      \
+					       Setting */
+
+#define MXC_F_I2C_INT_FL0_STOP_ER_POS 14 /**< INT_FL0_STOP_ER Position */
+#define MXC_F_I2C_INT_FL0_STOP_ER \
+	((uint32_t)(0x1UL         \
+		    << MXC_F_I2C_INT_FL0_STOP_ER_POS)) /**< INT_FL0_STOP_ER  \
+							    Mask */
+#define MXC_V_I2C_INT_FL0_STOP_ER_INACTIVE \
+	((uint32_t)0x0UL) /**< INT_FL0_STOP_ER_INACTIVE Value */
+#define MXC_S_I2C_INT_FL0_STOP_ER_INACTIVE  \
+	(MXC_V_I2C_INT_FL0_STOP_ER_INACTIVE \
+	 << MXC_F_I2C_INT_FL0_STOP_ER_POS) /**< INT_FL0_STOP_ER_INACTIVE       \
+					      Setting */
+#define MXC_V_I2C_INT_FL0_STOP_ER_PENDING \
+	((uint32_t)0x1UL) /**< INT_FL0_STOP_ER_PENDING Value */
+#define MXC_S_I2C_INT_FL0_STOP_ER_PENDING  \
+	(MXC_V_I2C_INT_FL0_STOP_ER_PENDING \
+	 << MXC_F_I2C_INT_FL0_STOP_ER_POS) /**< INT_FL0_STOP_ER_PENDING        \
+					      Setting */
+
+#define MXC_F_I2C_INT_FL0_TX_LOCK_OUT_POS \
+	15 /**< INT_FL0_TX_LOCK_OUT Position */
+#define MXC_F_I2C_INT_FL0_TX_LOCK_OUT \
+	((uint32_t)(                  \
+		0x1UL                 \
+		<< MXC_F_I2C_INT_FL0_TX_LOCK_OUT_POS)) /**<                    \
+							  INT_FL0_TX_LOCK_OUT  \
+							  Mask */
+
+/**
+ * Interrupt Enable Register.
+ */
+#define MXC_F_I2C_INT_EN0_DONE_POS 0 /**< INT_EN0_DONE Position */
+#define MXC_F_I2C_INT_EN0_DONE \
+	((uint32_t)(0x1UL      \
+		    << MXC_F_I2C_INT_EN0_DONE_POS)) /**< INT_EN0_DONE Mask */
+#define MXC_V_I2C_INT_EN0_DONE_DIS \
+	((uint32_t)0x0UL) /**< INT_EN0_DONE_DIS Value */
+#define MXC_S_I2C_INT_EN0_DONE_DIS  \
+	(MXC_V_I2C_INT_EN0_DONE_DIS \
+	 << MXC_F_I2C_INT_EN0_DONE_POS) /**< INT_EN0_DONE_DIS Setting */
+#define MXC_V_I2C_INT_EN0_DONE_EN \
+	((uint32_t)0x1UL) /**< INT_EN0_DONE_EN Value */
+#define MXC_S_I2C_INT_EN0_DONE_EN  \
+	(MXC_V_I2C_INT_EN0_DONE_EN \
+	 << MXC_F_I2C_INT_EN0_DONE_POS) /**< INT_EN0_DONE_EN Setting */
+
+#define MXC_F_I2C_INT_EN0_RX_MODE_POS 1 /**< INT_EN0_RX_MODE Position */
+#define MXC_F_I2C_INT_EN0_RX_MODE \
+	((uint32_t)(0x1UL         \
+		    << MXC_F_I2C_INT_EN0_RX_MODE_POS)) /**< INT_EN0_RX_MODE  \
+							    Mask */
+#define MXC_V_I2C_INT_EN0_RX_MODE_DIS \
+	((uint32_t)0x0UL) /**< INT_EN0_RX_MODE_DIS Value */
+#define MXC_S_I2C_INT_EN0_RX_MODE_DIS  \
+	(MXC_V_I2C_INT_EN0_RX_MODE_DIS \
+	 << MXC_F_I2C_INT_EN0_RX_MODE_POS) /**< INT_EN0_RX_MODE_DIS Setting */
+#define MXC_V_I2C_INT_EN0_RX_MODE_EN \
+	((uint32_t)0x1UL) /**< INT_EN0_RX_MODE_EN Value */
+#define MXC_S_I2C_INT_EN0_RX_MODE_EN  \
+	(MXC_V_I2C_INT_EN0_RX_MODE_EN \
+	 << MXC_F_I2C_INT_EN0_RX_MODE_POS) /**< INT_EN0_RX_MODE_EN Setting */
+
+#define MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS \
+	2 /**< INT_EN0_GEN_CTRL_ADDR Position */
+#define MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR \
+	((uint32_t)(                    \
+		0x1UL                   \
+		<< MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS)) /**<                     \
+							    INT_EN0_GEN_CTRL_ADDR \
+							    Mask */
+#define MXC_V_I2C_INT_EN0_GEN_CTRL_ADDR_DIS \
+	((uint32_t)0x0UL) /**< INT_EN0_GEN_CTRL_ADDR_DIS Value */
+#define MXC_S_I2C_INT_EN0_GEN_CTRL_ADDR_DIS  \
+	(MXC_V_I2C_INT_EN0_GEN_CTRL_ADDR_DIS \
+	 << MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS) /**<                          \
+						    INT_EN0_GEN_CTRL_ADDR_DIS  \
+						    Setting */
+#define MXC_V_I2C_INT_EN0_GEN_CTRL_ADDR_EN \
+	((uint32_t)0x1UL) /**< INT_EN0_GEN_CTRL_ADDR_EN Value */
+#define MXC_S_I2C_INT_EN0_GEN_CTRL_ADDR_EN  \
+	(MXC_V_I2C_INT_EN0_GEN_CTRL_ADDR_EN \
+	 << MXC_F_I2C_INT_EN0_GEN_CTRL_ADDR_POS) /**< INT_EN0_GEN_CTRL_ADDR_EN \
+						    Setting */
+
+#define MXC_F_I2C_INT_EN0_ADDR_MATCH_POS 3 /**< INT_EN0_ADDR_MATCH Position */
+#define MXC_F_I2C_INT_EN0_ADDR_MATCH \
+	((uint32_t)(                 \
+		0x1UL                \
+		<< MXC_F_I2C_INT_EN0_ADDR_MATCH_POS)) /**< INT_EN0_ADDR_MATCH  \
+							 Mask */
+#define MXC_V_I2C_INT_EN0_ADDR_MATCH_DIS \
+	((uint32_t)0x0UL) /**< INT_EN0_ADDR_MATCH_DIS Value */
+#define MXC_S_I2C_INT_EN0_ADDR_MATCH_DIS  \
+	(MXC_V_I2C_INT_EN0_ADDR_MATCH_DIS \
+	 << MXC_F_I2C_INT_EN0_ADDR_MATCH_POS) /**< INT_EN0_ADDR_MATCH_DIS      \
+						 Setting */
+#define MXC_V_I2C_INT_EN0_ADDR_MATCH_EN \
+	((uint32_t)0x1UL) /**< INT_EN0_ADDR_MATCH_EN Value */
+#define MXC_S_I2C_INT_EN0_ADDR_MATCH_EN  \
+	(MXC_V_I2C_INT_EN0_ADDR_MATCH_EN \
+	 << MXC_F_I2C_INT_EN0_ADDR_MATCH_POS) /**< INT_EN0_ADDR_MATCH_EN       \
+						 Setting */
+
+#define MXC_F_I2C_INT_EN0_RX_THRESH_POS 4 /**< INT_EN0_RX_THRESH Position */
+#define MXC_F_I2C_INT_EN0_RX_THRESH \
+	((uint32_t)(                \
+		0x1UL               \
+		<< MXC_F_I2C_INT_EN0_RX_THRESH_POS)) /**< INT_EN0_RX_THRESH    \
+							Mask */
+#define MXC_V_I2C_INT_EN0_RX_THRESH_DIS \
+	((uint32_t)0x0UL) /**< INT_EN0_RX_THRESH_DIS Value */
+#define MXC_S_I2C_INT_EN0_RX_THRESH_DIS  \
+	(MXC_V_I2C_INT_EN0_RX_THRESH_DIS \
+	 << MXC_F_I2C_INT_EN0_RX_THRESH_POS) /**< INT_EN0_RX_THRESH_DIS        \
+						Setting */
+#define MXC_V_I2C_INT_EN0_RX_THRESH_EN \
+	((uint32_t)0x1UL) /**< INT_EN0_RX_THRESH_EN Value */
+#define MXC_S_I2C_INT_EN0_RX_THRESH_EN  \
+	(MXC_V_I2C_INT_EN0_RX_THRESH_EN \
+	 << MXC_F_I2C_INT_EN0_RX_THRESH_POS) /**< INT_EN0_RX_THRESH_EN Setting \
+					      */
+
+#define MXC_F_I2C_INT_EN0_TX_THRESH_POS 5 /**< INT_EN0_TX_THRESH Position */
+#define MXC_F_I2C_INT_EN0_TX_THRESH \
+	((uint32_t)(                \
+		0x1UL               \
+		<< MXC_F_I2C_INT_EN0_TX_THRESH_POS)) /**< INT_EN0_TX_THRESH    \
+							Mask */
+#define MXC_V_I2C_INT_EN0_TX_THRESH_DIS \
+	((uint32_t)0x0UL) /**< INT_EN0_TX_THRESH_DIS Value */
+#define MXC_S_I2C_INT_EN0_TX_THRESH_DIS  \
+	(MXC_V_I2C_INT_EN0_TX_THRESH_DIS \
+	 << MXC_F_I2C_INT_EN0_TX_THRESH_POS) /**< INT_EN0_TX_THRESH_DIS        \
+						Setting */
+#define MXC_V_I2C_INT_EN0_TX_THRESH_EN \
+	((uint32_t)0x1UL) /**< INT_EN0_TX_THRESH_EN Value */
+#define MXC_S_I2C_INT_EN0_TX_THRESH_EN  \
+	(MXC_V_I2C_INT_EN0_TX_THRESH_EN \
+	 << MXC_F_I2C_INT_EN0_TX_THRESH_POS) /**< INT_EN0_TX_THRESH_EN Setting \
+					      */
+
+#define MXC_F_I2C_INT_EN0_STOP_POS 6 /**< INT_EN0_STOP Position */
+#define MXC_F_I2C_INT_EN0_STOP \
+	((uint32_t)(0x1UL      \
+		    << MXC_F_I2C_INT_EN0_STOP_POS)) /**< INT_EN0_STOP Mask */
+#define MXC_V_I2C_INT_EN0_STOP_DIS \
+	((uint32_t)0x0UL) /**< INT_EN0_STOP_DIS Value */
+#define MXC_S_I2C_INT_EN0_STOP_DIS  \
+	(MXC_V_I2C_INT_EN0_STOP_DIS \
+	 << MXC_F_I2C_INT_EN0_STOP_POS) /**< INT_EN0_STOP_DIS Setting */
+#define MXC_V_I2C_INT_EN0_STOP_EN \
+	((uint32_t)0x1UL) /**< INT_EN0_STOP_EN Value */
+#define MXC_S_I2C_INT_EN0_STOP_EN  \
+	(MXC_V_I2C_INT_EN0_STOP_EN \
+	 << MXC_F_I2C_INT_EN0_STOP_POS) /**< INT_EN0_STOP_EN Setting */
+
+#define MXC_F_I2C_INT_EN0_ADDR_ACK_POS 7 /**< INT_EN0_ADDR_ACK Position */
+#define MXC_F_I2C_INT_EN0_ADDR_ACK \
+	((uint32_t)(               \
+		0x1UL              \
+		<< MXC_F_I2C_INT_EN0_ADDR_ACK_POS)) /**< INT_EN0_ADDR_ACK  \
+							   Mask */
+#define MXC_V_I2C_INT_EN0_ADDR_ACK_DIS \
+	((uint32_t)0x0UL) /**< INT_EN0_ADDR_ACK_DIS Value */
+#define MXC_S_I2C_INT_EN0_ADDR_ACK_DIS  \
+	(MXC_V_I2C_INT_EN0_ADDR_ACK_DIS \
+	 << MXC_F_I2C_INT_EN0_ADDR_ACK_POS) /**< INT_EN0_ADDR_ACK_DIS Setting  \
+					     */
+#define MXC_V_I2C_INT_EN0_ADDR_ACK_EN \
+	((uint32_t)0x1UL) /**< INT_EN0_ADDR_ACK_EN Value */
+#define MXC_S_I2C_INT_EN0_ADDR_ACK_EN  \
+	(MXC_V_I2C_INT_EN0_ADDR_ACK_EN \
+	 << MXC_F_I2C_INT_EN0_ADDR_ACK_POS) /**< INT_EN0_ADDR_ACK_EN Setting   \
+					     */
+
+#define MXC_F_I2C_INT_EN0_ARB_ER_POS 8 /**< INT_EN0_ARB_ER Position */
+#define MXC_F_I2C_INT_EN0_ARB_ER \
+	((uint32_t)(             \
+		0x1UL            \
+		<< MXC_F_I2C_INT_EN0_ARB_ER_POS)) /**< INT_EN0_ARB_ER Mask */
+#define MXC_V_I2C_INT_EN0_ARB_ER_DIS \
+	((uint32_t)0x0UL) /**< INT_EN0_ARB_ER_DIS Value */
+#define MXC_S_I2C_INT_EN0_ARB_ER_DIS  \
+	(MXC_V_I2C_INT_EN0_ARB_ER_DIS \
+	 << MXC_F_I2C_INT_EN0_ARB_ER_POS) /**< INT_EN0_ARB_ER_DIS Setting */
+#define MXC_V_I2C_INT_EN0_ARB_ER_EN \
+	((uint32_t)0x1UL) /**< INT_EN0_ARB_ER_EN Value */
+#define MXC_S_I2C_INT_EN0_ARB_ER_EN  \
+	(MXC_V_I2C_INT_EN0_ARB_ER_EN \
+	 << MXC_F_I2C_INT_EN0_ARB_ER_POS) /**< INT_EN0_ARB_ER_EN Setting */
+
+#define MXC_F_I2C_INT_EN0_TO_ER_POS 9 /**< INT_EN0_TO_ER Position */
+#define MXC_F_I2C_INT_EN0_TO_ER \
+	((uint32_t)(            \
+		0x1UL           \
+		<< MXC_F_I2C_INT_EN0_TO_ER_POS)) /**< INT_EN0_TO_ER Mask */
+#define MXC_V_I2C_INT_EN0_TO_ER_DIS \
+	((uint32_t)0x0UL) /**< INT_EN0_TO_ER_DIS Value */
+#define MXC_S_I2C_INT_EN0_TO_ER_DIS  \
+	(MXC_V_I2C_INT_EN0_TO_ER_DIS \
+	 << MXC_F_I2C_INT_EN0_TO_ER_POS) /**< INT_EN0_TO_ER_DIS Setting */
+#define MXC_V_I2C_INT_EN0_TO_ER_EN \
+	((uint32_t)0x1UL) /**< INT_EN0_TO_ER_EN Value */
+#define MXC_S_I2C_INT_EN0_TO_ER_EN  \
+	(MXC_V_I2C_INT_EN0_TO_ER_EN \
+	 << MXC_F_I2C_INT_EN0_TO_ER_POS) /**< INT_EN0_TO_ER_EN Setting */
+
+#define MXC_F_I2C_INT_EN0_ADDR_ER_POS 10 /**< INT_EN0_ADDR_ER Position */
+#define MXC_F_I2C_INT_EN0_ADDR_ER \
+	((uint32_t)(0x1UL         \
+		    << MXC_F_I2C_INT_EN0_ADDR_ER_POS)) /**< INT_EN0_ADDR_ER  \
+							    Mask */
+#define MXC_V_I2C_INT_EN0_ADDR_ER_DIS \
+	((uint32_t)0x0UL) /**< INT_EN0_ADDR_ER_DIS Value */
+#define MXC_S_I2C_INT_EN0_ADDR_ER_DIS  \
+	(MXC_V_I2C_INT_EN0_ADDR_ER_DIS \
+	 << MXC_F_I2C_INT_EN0_ADDR_ER_POS) /**< INT_EN0_ADDR_ER_DIS Setting */
+#define MXC_V_I2C_INT_EN0_ADDR_ER_EN \
+	((uint32_t)0x1UL) /**< INT_EN0_ADDR_ER_EN Value */
+#define MXC_S_I2C_INT_EN0_ADDR_ER_EN  \
+	(MXC_V_I2C_INT_EN0_ADDR_ER_EN \
+	 << MXC_F_I2C_INT_EN0_ADDR_ER_POS) /**< INT_EN0_ADDR_ER_EN Setting */
+
+#define MXC_F_I2C_INT_EN0_DATA_ER_POS 11 /**< INT_EN0_DATA_ER Position */
+#define MXC_F_I2C_INT_EN0_DATA_ER \
+	((uint32_t)(0x1UL         \
+		    << MXC_F_I2C_INT_EN0_DATA_ER_POS)) /**< INT_EN0_DATA_ER  \
+							    Mask */
+#define MXC_V_I2C_INT_EN0_DATA_ER_DIS \
+	((uint32_t)0x0UL) /**< INT_EN0_DATA_ER_DIS Value */
+#define MXC_S_I2C_INT_EN0_DATA_ER_DIS  \
+	(MXC_V_I2C_INT_EN0_DATA_ER_DIS \
+	 << MXC_F_I2C_INT_EN0_DATA_ER_POS) /**< INT_EN0_DATA_ER_DIS Setting */
+#define MXC_V_I2C_INT_EN0_DATA_ER_EN \
+	((uint32_t)0x1UL) /**< INT_EN0_DATA_ER_EN Value */
+#define MXC_S_I2C_INT_EN0_DATA_ER_EN  \
+	(MXC_V_I2C_INT_EN0_DATA_ER_EN \
+	 << MXC_F_I2C_INT_EN0_DATA_ER_POS) /**< INT_EN0_DATA_ER_EN Setting */
+
+#define MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS \
+	12 /**< INT_EN0_DO_NOT_RESP_ER Position */
+#define MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER \
+	((uint32_t)(                     \
+		0x1UL                    \
+		<< MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS)) /**<                      \
+							     INT_EN0_DO_NOT_RESP_ER \
+							     Mask */
+#define MXC_V_I2C_INT_EN0_DO_NOT_RESP_ER_DIS \
+	((uint32_t)0x0UL) /**< INT_EN0_DO_NOT_RESP_ER_DIS Value */
+#define MXC_S_I2C_INT_EN0_DO_NOT_RESP_ER_DIS  \
+	(MXC_V_I2C_INT_EN0_DO_NOT_RESP_ER_DIS \
+	 << MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS) /**<                          \
+						     INT_EN0_DO_NOT_RESP_ER_DIS \
+						     Setting */
+#define MXC_V_I2C_INT_EN0_DO_NOT_RESP_ER_EN \
+	((uint32_t)0x1UL) /**< INT_EN0_DO_NOT_RESP_ER_EN Value */
+#define MXC_S_I2C_INT_EN0_DO_NOT_RESP_ER_EN  \
+	(MXC_V_I2C_INT_EN0_DO_NOT_RESP_ER_EN \
+	 << MXC_F_I2C_INT_EN0_DO_NOT_RESP_ER_POS) /**<                         \
+						     INT_EN0_DO_NOT_RESP_ER_EN \
+						     Setting */
+
+#define MXC_F_I2C_INT_EN0_START_ER_POS 13 /**< INT_EN0_START_ER Position */
+#define MXC_F_I2C_INT_EN0_START_ER \
+	((uint32_t)(               \
+		0x1UL              \
+		<< MXC_F_I2C_INT_EN0_START_ER_POS)) /**< INT_EN0_START_ER  \
+							   Mask */
+#define MXC_V_I2C_INT_EN0_START_ER_DIS \
+	((uint32_t)0x0UL) /**< INT_EN0_START_ER_DIS Value */
+#define MXC_S_I2C_INT_EN0_START_ER_DIS  \
+	(MXC_V_I2C_INT_EN0_START_ER_DIS \
+	 << MXC_F_I2C_INT_EN0_START_ER_POS) /**< INT_EN0_START_ER_DIS Setting  \
+					     */
+#define MXC_V_I2C_INT_EN0_START_ER_EN \
+	((uint32_t)0x1UL) /**< INT_EN0_START_ER_EN Value */
+#define MXC_S_I2C_INT_EN0_START_ER_EN  \
+	(MXC_V_I2C_INT_EN0_START_ER_EN \
+	 << MXC_F_I2C_INT_EN0_START_ER_POS) /**< INT_EN0_START_ER_EN Setting   \
+					     */
+
+#define MXC_F_I2C_INT_EN0_STOP_ER_POS 14 /**< INT_EN0_STOP_ER Position */
+#define MXC_F_I2C_INT_EN0_STOP_ER \
+	((uint32_t)(0x1UL         \
+		    << MXC_F_I2C_INT_EN0_STOP_ER_POS)) /**< INT_EN0_STOP_ER  \
+							    Mask */
+#define MXC_V_I2C_INT_EN0_STOP_ER_DIS \
+	((uint32_t)0x0UL) /**< INT_EN0_STOP_ER_DIS Value */
+#define MXC_S_I2C_INT_EN0_STOP_ER_DIS  \
+	(MXC_V_I2C_INT_EN0_STOP_ER_DIS \
+	 << MXC_F_I2C_INT_EN0_STOP_ER_POS) /**< INT_EN0_STOP_ER_DIS Setting */
+#define MXC_V_I2C_INT_EN0_STOP_ER_EN \
+	((uint32_t)0x1UL) /**< INT_EN0_STOP_ER_EN Value */
+#define MXC_S_I2C_INT_EN0_STOP_ER_EN  \
+	(MXC_V_I2C_INT_EN0_STOP_ER_EN \
+	 << MXC_F_I2C_INT_EN0_STOP_ER_POS) /**< INT_EN0_STOP_ER_EN Setting */
+
+#define MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS \
+	15 /**< INT_EN0_TX_LOCK_OUT Position */
+#define MXC_F_I2C_INT_EN0_TX_LOCK_OUT \
+	((uint32_t)(                  \
+		0x1UL                 \
+		<< MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS)) /**<                    \
+							  INT_EN0_TX_LOCK_OUT  \
+							  Mask */
+#define MXC_V_I2C_INT_EN0_TX_LOCK_OUT_DIS \
+	((uint32_t)0x0UL) /**< INT_EN0_TX_LOCK_OUT_DIS Value */
+#define MXC_S_I2C_INT_EN0_TX_LOCK_OUT_DIS  \
+	(MXC_V_I2C_INT_EN0_TX_LOCK_OUT_DIS \
+	 << MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS) /**< INT_EN0_TX_LOCK_OUT_DIS    \
+						  Setting */
+#define MXC_V_I2C_INT_EN0_TX_LOCK_OUT_EN \
+	((uint32_t)0x1UL) /**< INT_EN0_TX_LOCK_OUT_EN Value */
+#define MXC_S_I2C_INT_EN0_TX_LOCK_OUT_EN  \
+	(MXC_V_I2C_INT_EN0_TX_LOCK_OUT_EN \
+	 << MXC_F_I2C_INT_EN0_TX_LOCK_OUT_POS) /**< INT_EN0_TX_LOCK_OUT_EN     \
+						  Setting */
+
+/**
+ * Interrupt Status Register 1.
+ */
+#define MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS \
+	0 /**< INT_FL1_RX_OVERFLOW Position                                    \
+	   */
+#define MXC_F_I2C_INT_FL1_RX_OVERFLOW \
+	((uint32_t)(                  \
+		0x1UL                 \
+		<< MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS)) /**<                    \
+							  INT_FL1_RX_OVERFLOW  \
+							  Mask */
+#define MXC_V_I2C_INT_FL1_RX_OVERFLOW_INACTIVE \
+	((uint32_t)0x0UL) /**< INT_FL1_RX_OVERFLOW_INACTIVE Value */
+#define MXC_S_I2C_INT_FL1_RX_OVERFLOW_INACTIVE  \
+	(MXC_V_I2C_INT_FL1_RX_OVERFLOW_INACTIVE \
+	 << MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS) /**<                            \
+						  INT_FL1_RX_OVERFLOW_INACTIVE \
+						  Setting */
+#define MXC_V_I2C_INT_FL1_RX_OVERFLOW_PENDING \
+	((uint32_t)0x1UL) /**< INT_FL1_RX_OVERFLOW_PENDING Value */
+#define MXC_S_I2C_INT_FL1_RX_OVERFLOW_PENDING  \
+	(MXC_V_I2C_INT_FL1_RX_OVERFLOW_PENDING \
+	 << MXC_F_I2C_INT_FL1_RX_OVERFLOW_POS) /**<                            \
+						  INT_FL1_RX_OVERFLOW_PENDING  \
+						  Setting */
+
+#define MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS \
+	1 /**< INT_FL1_TX_UNDERFLOW Position */
+#define MXC_F_I2C_INT_FL1_TX_UNDERFLOW \
+	((uint32_t)(                   \
+		0x1UL                  \
+		<< MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS)) /**<                    \
+							   INT_FL1_TX_UNDERFLOW \
+							   Mask */
+#define MXC_V_I2C_INT_FL1_TX_UNDERFLOW_INACTIVE \
+	((uint32_t)0x0UL) /**< INT_FL1_TX_UNDERFLOW_INACTIVE Value */
+#define MXC_S_I2C_INT_FL1_TX_UNDERFLOW_INACTIVE  \
+	(MXC_V_I2C_INT_FL1_TX_UNDERFLOW_INACTIVE \
+	 << MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS) /**<                             \
+						   INT_FL1_TX_UNDERFLOW_INACTIVE \
+						   Setting */
+#define MXC_V_I2C_INT_FL1_TX_UNDERFLOW_PENDING \
+	((uint32_t)0x1UL) /**< INT_FL1_TX_UNDERFLOW_PENDING Value */
+#define MXC_S_I2C_INT_FL1_TX_UNDERFLOW_PENDING  \
+	(MXC_V_I2C_INT_FL1_TX_UNDERFLOW_PENDING \
+	 << MXC_F_I2C_INT_FL1_TX_UNDERFLOW_POS) /**<                            \
+						   INT_FL1_TX_UNDERFLOW_PENDING \
+						   Setting */
+
+/**
+ * Interrupt Staus Register 1.
+ */
+#define MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS \
+	0 /**< INT_EN1_RX_OVERFLOW Position                                    \
+	   */
+#define MXC_F_I2C_INT_EN1_RX_OVERFLOW \
+	((uint32_t)(                  \
+		0x1UL                 \
+		<< MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS)) /**<                    \
+							  INT_EN1_RX_OVERFLOW  \
+							  Mask */
+#define MXC_V_I2C_INT_EN1_RX_OVERFLOW_DIS \
+	((uint32_t)0x0UL) /**< INT_EN1_RX_OVERFLOW_DIS Value */
+#define MXC_S_I2C_INT_EN1_RX_OVERFLOW_DIS  \
+	(MXC_V_I2C_INT_EN1_RX_OVERFLOW_DIS \
+	 << MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS) /**< INT_EN1_RX_OVERFLOW_DIS    \
+						  Setting */
+#define MXC_V_I2C_INT_EN1_RX_OVERFLOW_EN \
+	((uint32_t)0x1UL) /**< INT_EN1_RX_OVERFLOW_EN Value */
+#define MXC_S_I2C_INT_EN1_RX_OVERFLOW_EN  \
+	(MXC_V_I2C_INT_EN1_RX_OVERFLOW_EN \
+	 << MXC_F_I2C_INT_EN1_RX_OVERFLOW_POS) /**< INT_EN1_RX_OVERFLOW_EN     \
+						  Setting */
+
+#define MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS \
+	1 /**< INT_EN1_TX_UNDERFLOW Position */
+#define MXC_F_I2C_INT_EN1_TX_UNDERFLOW \
+	((uint32_t)(                   \
+		0x1UL                  \
+		<< MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS)) /**<                    \
+							   INT_EN1_TX_UNDERFLOW \
+							   Mask */
+#define MXC_V_I2C_INT_EN1_TX_UNDERFLOW_DIS \
+	((uint32_t)0x0UL) /**< INT_EN1_TX_UNDERFLOW_DIS Value */
+#define MXC_S_I2C_INT_EN1_TX_UNDERFLOW_DIS  \
+	(MXC_V_I2C_INT_EN1_TX_UNDERFLOW_DIS \
+	 << MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS) /**< INT_EN1_TX_UNDERFLOW_DIS  \
+						   Setting */
+#define MXC_V_I2C_INT_EN1_TX_UNDERFLOW_EN \
+	((uint32_t)0x1UL) /**< INT_EN1_TX_UNDERFLOW_EN Value */
+#define MXC_S_I2C_INT_EN1_TX_UNDERFLOW_EN  \
+	(MXC_V_I2C_INT_EN1_TX_UNDERFLOW_EN \
+	 << MXC_F_I2C_INT_EN1_TX_UNDERFLOW_POS) /**< INT_EN1_TX_UNDERFLOW_EN   \
+						   Setting */
+
+/**
+ * FIFO Configuration Register.
+ */
+#define MXC_F_I2C_FIFO_LEN_RX_LEN_POS 0 /**< FIFO_LEN_RX_LEN Position */
+#define MXC_F_I2C_FIFO_LEN_RX_LEN \
+	((uint32_t)(0xFFUL        \
+		    << MXC_F_I2C_FIFO_LEN_RX_LEN_POS)) /**< FIFO_LEN_RX_LEN \
+							     Mask */
+
+#define MXC_F_I2C_FIFO_LEN_TX_LEN_POS 8 /**< FIFO_LEN_TX_LEN Position */
+#define MXC_F_I2C_FIFO_LEN_TX_LEN \
+	((uint32_t)(0xFFUL        \
+		    << MXC_F_I2C_FIFO_LEN_TX_LEN_POS)) /**< FIFO_LEN_TX_LEN \
+							     Mask */
+
+/**
+ * Receive Control Register 0.
+ */
+#define MXC_F_I2C_RX_CTRL0_DNR_POS 0 /**< RX_CTRL0_DNR Position */
+#define MXC_F_I2C_RX_CTRL0_DNR \
+	((uint32_t)(0x1UL      \
+		    << MXC_F_I2C_RX_CTRL0_DNR_POS)) /**< RX_CTRL0_DNR Mask */
+#define MXC_V_I2C_RX_CTRL0_DNR_RESPOND \
+	((uint32_t)0x0UL) /**< RX_CTRL0_DNR_RESPOND Value */
+#define MXC_S_I2C_RX_CTRL0_DNR_RESPOND  \
+	(MXC_V_I2C_RX_CTRL0_DNR_RESPOND \
+	 << MXC_F_I2C_RX_CTRL0_DNR_POS) /**< RX_CTRL0_DNR_RESPOND Setting */
+#define MXC_V_I2C_RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY \
+	((uint32_t)0x1UL) /**< RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY Value */
+#define MXC_S_I2C_RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY  \
+	(MXC_V_I2C_RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY \
+	 << MXC_F_I2C_RX_CTRL0_DNR_POS) /**<                                      \
+					   RX_CTRL0_DNR_NOT_RESPOND_RX_FIFO_EMPTY \
+					   Setting */
+
+#define MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS 7 /**< RX_CTRL0_RX_FLUSH Position */
+#define MXC_F_I2C_RX_CTRL0_RX_FLUSH \
+	((uint32_t)(                \
+		0x1UL               \
+		<< MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS)) /**< RX_CTRL0_RX_FLUSH    \
+							Mask */
+#define MXC_V_I2C_RX_CTRL0_RX_FLUSH_NOT_FLUSHED \
+	((uint32_t)0x0UL) /**< RX_CTRL0_RX_FLUSH_NOT_FLUSHED Value */
+#define MXC_S_I2C_RX_CTRL0_RX_FLUSH_NOT_FLUSHED  \
+	(MXC_V_I2C_RX_CTRL0_RX_FLUSH_NOT_FLUSHED \
+	 << MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS) /**<                              \
+						RX_CTRL0_RX_FLUSH_NOT_FLUSHED  \
+						Setting */
+#define MXC_V_I2C_RX_CTRL0_RX_FLUSH_FLUSH \
+	((uint32_t)0x1UL) /**< RX_CTRL0_RX_FLUSH_FLUSH Value */
+#define MXC_S_I2C_RX_CTRL0_RX_FLUSH_FLUSH  \
+	(MXC_V_I2C_RX_CTRL0_RX_FLUSH_FLUSH \
+	 << MXC_F_I2C_RX_CTRL0_RX_FLUSH_POS) /**< RX_CTRL0_RX_FLUSH_FLUSH      \
+						Setting */
+
+#define MXC_F_I2C_RX_CTRL0_RX_THRESH_POS 8 /**< RX_CTRL0_RX_THRESH Position */
+#define MXC_F_I2C_RX_CTRL0_RX_THRESH \
+	((uint32_t)(                 \
+		0xFUL                \
+		<< MXC_F_I2C_RX_CTRL0_RX_THRESH_POS)) /**< RX_CTRL0_RX_THRESH  \
+							 Mask */
+
+/**
+ * Receive Control Register 1.
+ */
+#define MXC_F_I2C_RX_CTRL1_RX_CNT_POS 0 /**< RX_CTRL1_RX_CNT Position */
+#define MXC_F_I2C_RX_CTRL1_RX_CNT \
+	((uint32_t)(0xFFUL        \
+		    << MXC_F_I2C_RX_CTRL1_RX_CNT_POS)) /**< RX_CTRL1_RX_CNT \
+							     Mask */
+
+#define MXC_F_I2C_RX_CTRL1_RX_FIFO_POS 8 /**< RX_CTRL1_RX_FIFO Position */
+#define MXC_F_I2C_RX_CTRL1_RX_FIFO \
+	((uint32_t)(               \
+		0xFUL              \
+		<< MXC_F_I2C_RX_CTRL1_RX_FIFO_POS)) /**< RX_CTRL1_RX_FIFO  \
+							   Mask */
+
+/**
+ * Transmit Control Register 0.
+ */
+#define MXC_F_I2C_TX_CTRL0_TX_PRELOAD_POS \
+	0 /**< TX_CTRL0_TX_PRELOAD Position                                    \
+	   */
+#define MXC_F_I2C_TX_CTRL0_TX_PRELOAD \
+	((uint32_t)(                  \
+		0x1UL                 \
+		<< MXC_F_I2C_TX_CTRL0_TX_PRELOAD_POS)) /**<                    \
+							  TX_CTRL0_TX_PRELOAD  \
+							  Mask */
+
+#define MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS \
+	1 /**< TX_CTRL0_TX_READY_MODE Position */
+#define MXC_F_I2C_TX_CTRL0_TX_READY_MODE \
+	((uint32_t)(                     \
+		0x1UL                    \
+		<< MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS)) /**<                      \
+							     TX_CTRL0_TX_READY_MODE \
+							     Mask */
+#define MXC_V_I2C_TX_CTRL0_TX_READY_MODE_EN \
+	((uint32_t)0x0UL) /**< TX_CTRL0_TX_READY_MODE_EN Value */
+#define MXC_S_I2C_TX_CTRL0_TX_READY_MODE_EN  \
+	(MXC_V_I2C_TX_CTRL0_TX_READY_MODE_EN \
+	 << MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS) /**<                         \
+						     TX_CTRL0_TX_READY_MODE_EN \
+						     Setting */
+#define MXC_V_I2C_TX_CTRL0_TX_READY_MODE_DIS \
+	((uint32_t)0x1UL) /**< TX_CTRL0_TX_READY_MODE_DIS Value */
+#define MXC_S_I2C_TX_CTRL0_TX_READY_MODE_DIS  \
+	(MXC_V_I2C_TX_CTRL0_TX_READY_MODE_DIS \
+	 << MXC_F_I2C_TX_CTRL0_TX_READY_MODE_POS) /**<                          \
+						     TX_CTRL0_TX_READY_MODE_DIS \
+						     Setting */
+
+#define MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS 7 /**< TX_CTRL0_TX_FLUSH Position */
+#define MXC_F_I2C_TX_CTRL0_TX_FLUSH \
+	((uint32_t)(                \
+		0x1UL               \
+		<< MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS)) /**< TX_CTRL0_TX_FLUSH    \
+							Mask */
+#define MXC_V_I2C_TX_CTRL0_TX_FLUSH_NOT_FLUSHED \
+	((uint32_t)0x0UL) /**< TX_CTRL0_TX_FLUSH_NOT_FLUSHED Value */
+#define MXC_S_I2C_TX_CTRL0_TX_FLUSH_NOT_FLUSHED  \
+	(MXC_V_I2C_TX_CTRL0_TX_FLUSH_NOT_FLUSHED \
+	 << MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS) /**<                              \
+						TX_CTRL0_TX_FLUSH_NOT_FLUSHED  \
+						Setting */
+#define MXC_V_I2C_TX_CTRL0_TX_FLUSH_FLUSH \
+	((uint32_t)0x1UL) /**< TX_CTRL0_TX_FLUSH_FLUSH Value */
+#define MXC_S_I2C_TX_CTRL0_TX_FLUSH_FLUSH  \
+	(MXC_V_I2C_TX_CTRL0_TX_FLUSH_FLUSH \
+	 << MXC_F_I2C_TX_CTRL0_TX_FLUSH_POS) /**< TX_CTRL0_TX_FLUSH_FLUSH      \
+						Setting */
+
+#define MXC_F_I2C_TX_CTRL0_TX_THRESH_POS 8 /**< TX_CTRL0_TX_THRESH Position */
+#define MXC_F_I2C_TX_CTRL0_TX_THRESH \
+	((uint32_t)(                 \
+		0xFUL                \
+		<< MXC_F_I2C_TX_CTRL0_TX_THRESH_POS)) /**< TX_CTRL0_TX_THRESH  \
+							 Mask */
+
+/**
+ * Transmit Control Register 1.
+ */
+#define MXC_F_I2C_TX_CTRL1_TX_READY_POS 0 /**< TX_CTRL1_TX_READY Position */
+#define MXC_F_I2C_TX_CTRL1_TX_READY \
+	((uint32_t)(                \
+		0x1UL               \
+		<< MXC_F_I2C_TX_CTRL1_TX_READY_POS)) /**< TX_CTRL1_TX_READY    \
+							Mask */
+
+#define MXC_F_I2C_TX_CTRL1_TX_LAST_POS 1 /**< TX_CTRL1_TX_LAST Position */
+#define MXC_F_I2C_TX_CTRL1_TX_LAST \
+	((uint32_t)(               \
+		0x1UL              \
+		<< MXC_F_I2C_TX_CTRL1_TX_LAST_POS)) /**< TX_CTRL1_TX_LAST  \
+							   Mask */
+#define MXC_V_I2C_TX_CTRL1_TX_LAST_HOLD_SCL_LOW \
+	((uint32_t)0x0UL) /**< TX_CTRL1_TX_LAST_HOLD_SCL_LOW Value */
+#define MXC_S_I2C_TX_CTRL1_TX_LAST_HOLD_SCL_LOW  \
+	(MXC_V_I2C_TX_CTRL1_TX_LAST_HOLD_SCL_LOW \
+	 << MXC_F_I2C_TX_CTRL1_TX_LAST_POS) /**< TX_CTRL1_TX_LAST_HOLD_SCL_LOW \
+					       Setting */
+#define MXC_V_I2C_TX_CTRL1_TX_LAST_END_TRANSACTION \
+	((uint32_t)0x1UL) /**< TX_CTRL1_TX_LAST_END_TRANSACTION Value */
+#define MXC_S_I2C_TX_CTRL1_TX_LAST_END_TRANSACTION  \
+	(MXC_V_I2C_TX_CTRL1_TX_LAST_END_TRANSACTION \
+	 << MXC_F_I2C_TX_CTRL1_TX_LAST_POS) /**<                                \
+					       TX_CTRL1_TX_LAST_END_TRANSACTION \
+					       Setting */
+
+#define MXC_F_I2C_TX_CTRL1_TX_FIFO_POS 8 /**< TX_CTRL1_TX_FIFO Position */
+#define MXC_F_I2C_TX_CTRL1_TX_FIFO \
+	((uint32_t)(               \
+		0xFUL              \
+		<< MXC_F_I2C_TX_CTRL1_TX_FIFO_POS)) /**< TX_CTRL1_TX_FIFO  \
+							   Mask */
+
+/**
+ * Data Register.
+ */
+#define MXC_F_I2C_FIFO_DATA_POS 0 /**< FIFO_DATA Position */
+#define MXC_F_I2C_FIFO_DATA \
+	((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_DATA_POS)) /**< FIFO_DATA Mask */
+
+/**
+ * Master Control Register.
+ */
+#define MXC_F_I2C_MASTER_CTRL_START_POS 0 /**< MASTER_CTRL_START Position */
+#define MXC_F_I2C_MASTER_CTRL_START \
+	((uint32_t)(                \
+		0x1UL               \
+		<< MXC_F_I2C_MASTER_CTRL_START_POS)) /**< MASTER_CTRL_START    \
+							Mask */
+
+#define MXC_F_I2C_MASTER_CTRL_RESTART_POS \
+	1 /**< MASTER_CTRL_RESTART Position                                    \
+	   */
+#define MXC_F_I2C_MASTER_CTRL_RESTART \
+	((uint32_t)(                  \
+		0x1UL                 \
+		<< MXC_F_I2C_MASTER_CTRL_RESTART_POS)) /**<                    \
+							  MASTER_CTRL_RESTART  \
+							  Mask */
+
+#define MXC_F_I2C_MASTER_CTRL_STOP_POS 2 /**< MASTER_CTRL_STOP Position */
+#define MXC_F_I2C_MASTER_CTRL_STOP \
+	((uint32_t)(               \
+		0x1UL              \
+		<< MXC_F_I2C_MASTER_CTRL_STOP_POS)) /**< MASTER_CTRL_STOP  \
+							   Mask */
+
+#define MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS \
+	7 /**< MASTER_CTRL_SL_EX_ADDR Position */
+#define MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR \
+	((uint32_t)(                     \
+		0x1UL                    \
+		<< MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS)) /**<                      \
+							     MASTER_CTRL_SL_EX_ADDR \
+							     Mask */
+#define MXC_V_I2C_MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS \
+	((uint32_t)0x0UL) /**< MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS Value */
+#define MXC_S_I2C_MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS  \
+	(MXC_V_I2C_MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS \
+	 << MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS) /**<                                     \
+						     MASTER_CTRL_SL_EX_ADDR_7_BITS_ADDRESS \
+						     Setting */
+#define MXC_V_I2C_MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS \
+	((uint32_t)0x1UL) /**< MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS Value */
+#define MXC_S_I2C_MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS  \
+	(MXC_V_I2C_MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS \
+	 << MXC_F_I2C_MASTER_CTRL_SL_EX_ADDR_POS) /**<                                      \
+						     MASTER_CTRL_SL_EX_ADDR_10_BITS_ADDRESS \
+						     Setting */
+
+#define MXC_F_I2C_MASTER_CTRL_MASTER_CODE_POS \
+	8 /**< MASTER_CTRL_MASTER_CODE Position */
+#define MXC_F_I2C_MASTER_CTRL_MASTER_CODE \
+	((uint32_t)(                      \
+		0x7UL                     \
+		<< MXC_F_I2C_MASTER_CTRL_MASTER_CODE_POS)) /**<                       \
+							      MASTER_CTRL_MASTER_CODE \
+							      Mask */
+
+#define MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS \
+	11 /**< MASTER_CTRL_SCL_SPEED_UP Position */
+#define MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP \
+	((uint32_t)(                       \
+		0x1UL                      \
+		<< MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS)) /**<                        \
+							       MASTER_CTRL_SCL_SPEED_UP \
+							       Mask */
+#define MXC_V_I2C_MASTER_CTRL_SCL_SPEED_UP_EN \
+	((uint32_t)0x0UL) /**< MASTER_CTRL_SCL_SPEED_UP_EN Value */
+#define MXC_S_I2C_MASTER_CTRL_SCL_SPEED_UP_EN  \
+	(MXC_V_I2C_MASTER_CTRL_SCL_SPEED_UP_EN \
+	 << MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS) /**<                           \
+						       MASTER_CTRL_SCL_SPEED_UP_EN \
+						       Setting */
+#define MXC_V_I2C_MASTER_CTRL_SCL_SPEED_UP_DIS \
+	((uint32_t)0x1UL) /**< MASTER_CTRL_SCL_SPEED_UP_DIS Value */
+#define MXC_S_I2C_MASTER_CTRL_SCL_SPEED_UP_DIS  \
+	(MXC_V_I2C_MASTER_CTRL_SCL_SPEED_UP_DIS \
+	 << MXC_F_I2C_MASTER_CTRL_SCL_SPEED_UP_POS) /**<                            \
+						       MASTER_CTRL_SCL_SPEED_UP_DIS \
+						       Setting */
+
+/**
+ * Clock Low Register.
+ */
+#define MXC_F_I2C_CLK_LO_CLK_LO_POS 0 /**< CLK_LO_CLK_LO Position */
+#define MXC_F_I2C_CLK_LO_CLK_LO \
+	((uint32_t)(            \
+		0x1FFUL         \
+		<< MXC_F_I2C_CLK_LO_CLK_LO_POS)) /**< CLK_LO_CLK_LO Mask */
+
+/**
+ * Clock high Register.
+ */
+#define MXC_F_I2C_CLK_HI_CKH_POS 0 /**< CLK_HI_CKH Position */
+#define MXC_F_I2C_CLK_HI_CKH \
+	((uint32_t)(0x1FFUL  \
+		    << MXC_F_I2C_CLK_HI_CKH_POS)) /**< CLK_HI_CKH Mask */
+
+/**
+ * HS-Mode Clock Control Register
+ */
+#define MXC_F_I2C_HS_CLK_HS_CLK_LO_POS 0 /**< HS_CLK_HS_CLK_LO Position */
+#define MXC_F_I2C_HS_CLK_HS_CLK_LO \
+	((uint32_t)(               \
+		0xFFUL             \
+		<< MXC_F_I2C_HS_CLK_HS_CLK_LO_POS)) /**< HS_CLK_HS_CLK_LO  \
+							   Mask */
+
+#define MXC_F_I2C_HS_CLK_HS_CLK_HI_POS 8 /**< HS_CLK_HS_CLK_HI Position */
+#define MXC_F_I2C_HS_CLK_HS_CLK_HI \
+	((uint32_t)(               \
+		0xFFUL             \
+		<< MXC_F_I2C_HS_CLK_HS_CLK_HI_POS)) /**< HS_CLK_HS_CLK_HI  \
+							   Mask */
+
+/**
+ * Timeout Register
+ */
+#define MXC_F_I2C_TIMEOUT_TO_POS 0 /**< TIMEOUT_TO Position */
+#define MXC_F_I2C_TIMEOUT_TO \
+	((uint32_t)(0xFFFFUL \
+		    << MXC_F_I2C_TIMEOUT_TO_POS)) /**< TIMEOUT_TO Mask */
+
+/**
+ * Slave Address Register.
+ */
+#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_POS \
+	0 /**< SLAVE_ADDR_SLAVE_ADDR Position */
+#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR \
+	((uint32_t)(                    \
+		0x3FFUL                 \
+		<< MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_POS)) /**<                     \
+							    SLAVE_ADDR_SLAVE_ADDR \
+							    Mask */
+
+#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS_POS \
+	10 /**< SLAVE_ADDR_SLAVE_ADDR_DIS Position */
+#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS \
+	((uint32_t)(                        \
+		0x1UL                       \
+		<< MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_DIS_POS)) /**<                         \
+								SLAVE_ADDR_SLAVE_ADDR_DIS \
+								Mask */
+
+#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX_POS \
+	11 /**< SLAVE_ADDR_SLAVE_ADDR_IDX Position */
+#define MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX \
+	((uint32_t)(                        \
+		0xFUL                       \
+		<< MXC_F_I2C_SLAVE_ADDR_SLAVE_ADDR_IDX_POS)) /**<                         \
+								SLAVE_ADDR_SLAVE_ADDR_IDX \
+								Mask */
+
+#define MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS \
+	15 /**< SLAVE_ADDR_EX_ADDR Position                                    \
+	    */
+#define MXC_F_I2C_SLAVE_ADDR_EX_ADDR \
+	((uint32_t)(                 \
+		0x1UL                \
+		<< MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS)) /**< SLAVE_ADDR_EX_ADDR  \
+							 Mask */
+#define MXC_V_I2C_SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS \
+	((uint32_t)0x0UL) /**< SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS Value */
+#define MXC_S_I2C_SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS  \
+	(MXC_V_I2C_SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS \
+	 << MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS) /**<                                 \
+						 SLAVE_ADDR_EX_ADDR_7_BITS_ADDRESS \
+						 Setting */
+#define MXC_V_I2C_SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS \
+	((uint32_t)0x1UL) /**< SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS Value */
+#define MXC_S_I2C_SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS  \
+	(MXC_V_I2C_SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS \
+	 << MXC_F_I2C_SLAVE_ADDR_EX_ADDR_POS) /**<                                  \
+						 SLAVE_ADDR_EX_ADDR_10_BITS_ADDRESS \
+						 Setting */
+
+/**
+ * DMA Register.
+ */
+#define MXC_F_I2C_DMA_TX_EN_POS 0 /**< DMA_TX_EN Position */
+#define MXC_F_I2C_DMA_TX_EN \
+	((uint32_t)(0x1UL << MXC_F_I2C_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */
+#define MXC_V_I2C_DMA_TX_EN_DIS ((uint32_t)0x0UL) /**< DMA_TX_EN_DIS Value */
+#define MXC_S_I2C_DMA_TX_EN_DIS  \
+	(MXC_V_I2C_DMA_TX_EN_DIS \
+	 << MXC_F_I2C_DMA_TX_EN_POS) /**< DMA_TX_EN_DIS Setting */
+#define MXC_V_I2C_DMA_TX_EN_EN ((uint32_t)0x1UL) /**< DMA_TX_EN_EN Value */
+#define MXC_S_I2C_DMA_TX_EN_EN  \
+	(MXC_V_I2C_DMA_TX_EN_EN \
+	 << MXC_F_I2C_DMA_TX_EN_POS) /**< DMA_TX_EN_EN Setting */
+
+#define MXC_F_I2C_DMA_RX_EN_POS 1 /**< DMA_RX_EN Position */
+#define MXC_F_I2C_DMA_RX_EN \
+	((uint32_t)(0x1UL << MXC_F_I2C_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */
+#define MXC_V_I2C_DMA_RX_EN_DIS ((uint32_t)0x0UL) /**< DMA_RX_EN_DIS Value */
+#define MXC_S_I2C_DMA_RX_EN_DIS  \
+	(MXC_V_I2C_DMA_RX_EN_DIS \
+	 << MXC_F_I2C_DMA_RX_EN_POS) /**< DMA_RX_EN_DIS Setting */
+#define MXC_V_I2C_DMA_RX_EN_EN ((uint32_t)0x1UL) /**< DMA_RX_EN_EN Value */
+#define MXC_S_I2C_DMA_RX_EN_EN  \
+	(MXC_V_I2C_DMA_RX_EN_EN \
+	 << MXC_F_I2C_DMA_RX_EN_POS) /**< DMA_RX_EN_EN Setting */
+
+#endif /* _I2C_REGS_H_ */
diff --git a/chip/max32660/registers.h b/chip/max32660/registers.h
index 997b49976d..8a2a072898 100644
--- a/chip/max32660/registers.h
+++ b/chip/max32660/registers.h
@@ -10,60 +10,60 @@
 
 #include <stdint.h>
 
-#define EC_PF_IRQn 0	/* 0x10  0x0040  16: Power Fail */
-#define EC_WDT0_IRQn 1      /* 0x11  0x0044  17: Watchdog 0 */
-#define EC_RSV00_IRQn 2     /* 0x12  0x0048  18: RSV00 */
-#define EC_RTC_IRQn 3       /* 0x13  0x004C  19: RTC */
-#define EC_RSV1_IRQn 4      /* 0x14  0x0050  20: RSV1 */
-#define EC_TMR0_IRQn 5      /* 0x15  0x0054  21: Timer 0 */
-#define EC_TMR1_IRQn 6      /* 0x16  0x0058  22: Timer 1 */
-#define EC_TMR2_IRQn 7      /* 0x17  0x005C  23: Timer 2 */
-#define EC_RSV02_IRQn 8     /* 0x18  0x0060  24: RSV02 */
-#define EC_RSV03_IRQn 9     /* 0x19  0x0064  25: RSV03 */
-#define EC_RSV04_IRQn 10    /* 0x1A  0x0068  26: RSV04 */
-#define EC_RSV05_IRQn 11    /* 0x1B  0x006C  27: RSV05 */
-#define EC_RSV06_IRQn 12    /* 0x1C  0x0070  28: RSV06 */
-#define EC_I2C0_IRQn 13     /* 0x1D  0x0074  29: I2C0 */
-#define EC_UART0_IRQn 14    /* 0x1E  0x0078  30: UART 0 */
-#define EC_UART1_IRQn 15    /* 0x1F  0x007C  31: UART 1 */
-#define EC_SPI17Y_IRQn 16   /* 0x20  0x0080  32: SPI17Y */
-#define EC_SPIMSS_IRQn 17   /* 0x21  0x0084  33: SPIMSS */
-#define EC_RSV07_IRQn 18    /* 0x22  0x0088  34: RSV07 */
-#define EC_RSV08_IRQn 19    /* 0x23  0x008C  35: RSV08 */
-#define EC_RSV09_IRQn 20    /* 0x24  0x0090  36: RSV09 */
-#define EC_RSV10_IRQn 21    /* 0x25  0x0094  37: RSV10 */
-#define EC_RSV11_IRQn 22    /* 0x26  0x0098  38: RSV11 */
-#define EC_FLC_IRQn 23      /* 0x27  0x009C  39: FLC */
-#define EC_GPIO0_IRQn 24    /* 0x28  0x00A0  40: GPIO0 */
-#define EC_RSV12_IRQn 25    /* 0x29  0x00A4  41: RSV12 */
-#define EC_RSV13_IRQn 26    /* 0x2A  0x00A8  42: RSV13 */
-#define EC_RSV14_IRQn 27    /* 0x2B  0x00AC  43: RSV14 */
-#define EC_DMA0_IRQn 28     /* 0x2C  0x00B0  44: DMA0 */
-#define EC_DMA1_IRQn 29     /* 0x2D  0x00B4  45: DMA1 */
-#define EC_DMA2_IRQn 30     /* 0x2E  0x00B8  46: DMA2 */
-#define EC_DMA3_IRQn 31     /* 0x2F  0x00BC  47: DMA3 */
-#define EC_RSV15_IRQn 32    /* 0x30  0x00C0  48: RSV15 */
-#define EC_RSV16_IRQn 33    /* 0x31  0x00C4  49: RSV16 */
-#define EC_RSV17_IRQn 34    /* 0x32  0x00C8  50: RSV17 */
-#define EC_RSV18_IRQn 35    /* 0x33  0x00CC  51: RSV18 */
-#define EC_I2C1_IRQn 36     /* 0x34  0x00D0  52: I2C1 */
-#define EC_RSV19_IRQn 37    /* 0x35  0x00D4  53: RSV19 */
-#define EC_RSV20_IRQn 38    /* 0x36  0x00D8  54: RSV20 */
-#define EC_RSV21_IRQn 39    /* 0x37  0x00DC  55: RSV21 */
-#define EC_RSV22_IRQn 40    /* 0x38  0x00E0  56: RSV22 */
-#define EC_RSV23_IRQn 41    /* 0x39  0x00E4  57: RSV23 */
-#define EC_RSV24_IRQn 42    /* 0x3A  0x00E8  58: RSV24 */
-#define EC_RSV25_IRQn 43    /* 0x3B  0x00EC  59: RSV25 */
-#define EC_RSV26_IRQn 44    /* 0x3C  0x00F0  60: RSV26 */
-#define EC_RSV27_IRQn 45    /* 0x3D  0x00F4  61: RSV27 */
-#define EC_RSV28_IRQn 46    /* 0x3E  0x00F8  62: RSV28 */
-#define EC_RSV29_IRQn 47    /* 0x3F  0x00FC  63: RSV29 */
-#define EC_RSV30_IRQn 48    /* 0x40  0x0100  64: RSV30 */
-#define EC_RSV31_IRQn 49    /* 0x41  0x0104  65: RSV31 */
-#define EC_RSV32_IRQn 50    /* 0x42  0x0108  66: RSV32 */
-#define EC_RSV33_IRQn 51    /* 0x43  0x010C  67: RSV33 */
-#define EC_RSV34_IRQn 52    /* 0x44  0x0110  68: RSV34 */
-#define EC_RSV35_IRQn 53    /* 0x45  0x0114  69: RSV35 */
+#define EC_PF_IRQn 0 /* 0x10  0x0040  16: Power Fail */
+#define EC_WDT0_IRQn 1 /* 0x11  0x0044  17: Watchdog 0 */
+#define EC_RSV00_IRQn 2 /* 0x12  0x0048  18: RSV00 */
+#define EC_RTC_IRQn 3 /* 0x13  0x004C  19: RTC */
+#define EC_RSV1_IRQn 4 /* 0x14  0x0050  20: RSV1 */
+#define EC_TMR0_IRQn 5 /* 0x15  0x0054  21: Timer 0 */
+#define EC_TMR1_IRQn 6 /* 0x16  0x0058  22: Timer 1 */
+#define EC_TMR2_IRQn 7 /* 0x17  0x005C  23: Timer 2 */
+#define EC_RSV02_IRQn 8 /* 0x18  0x0060  24: RSV02 */
+#define EC_RSV03_IRQn 9 /* 0x19  0x0064  25: RSV03 */
+#define EC_RSV04_IRQn 10 /* 0x1A  0x0068  26: RSV04 */
+#define EC_RSV05_IRQn 11 /* 0x1B  0x006C  27: RSV05 */
+#define EC_RSV06_IRQn 12 /* 0x1C  0x0070  28: RSV06 */
+#define EC_I2C0_IRQn 13 /* 0x1D  0x0074  29: I2C0 */
+#define EC_UART0_IRQn 14 /* 0x1E  0x0078  30: UART 0 */
+#define EC_UART1_IRQn 15 /* 0x1F  0x007C  31: UART 1 */
+#define EC_SPI17Y_IRQn 16 /* 0x20  0x0080  32: SPI17Y */
+#define EC_SPIMSS_IRQn 17 /* 0x21  0x0084  33: SPIMSS */
+#define EC_RSV07_IRQn 18 /* 0x22  0x0088  34: RSV07 */
+#define EC_RSV08_IRQn 19 /* 0x23  0x008C  35: RSV08 */
+#define EC_RSV09_IRQn 20 /* 0x24  0x0090  36: RSV09 */
+#define EC_RSV10_IRQn 21 /* 0x25  0x0094  37: RSV10 */
+#define EC_RSV11_IRQn 22 /* 0x26  0x0098  38: RSV11 */
+#define EC_FLC_IRQn 23 /* 0x27  0x009C  39: FLC */
+#define EC_GPIO0_IRQn 24 /* 0x28  0x00A0  40: GPIO0 */
+#define EC_RSV12_IRQn 25 /* 0x29  0x00A4  41: RSV12 */
+#define EC_RSV13_IRQn 26 /* 0x2A  0x00A8  42: RSV13 */
+#define EC_RSV14_IRQn 27 /* 0x2B  0x00AC  43: RSV14 */
+#define EC_DMA0_IRQn 28 /* 0x2C  0x00B0  44: DMA0 */
+#define EC_DMA1_IRQn 29 /* 0x2D  0x00B4  45: DMA1 */
+#define EC_DMA2_IRQn 30 /* 0x2E  0x00B8  46: DMA2 */
+#define EC_DMA3_IRQn 31 /* 0x2F  0x00BC  47: DMA3 */
+#define EC_RSV15_IRQn 32 /* 0x30  0x00C0  48: RSV15 */
+#define EC_RSV16_IRQn 33 /* 0x31  0x00C4  49: RSV16 */
+#define EC_RSV17_IRQn 34 /* 0x32  0x00C8  50: RSV17 */
+#define EC_RSV18_IRQn 35 /* 0x33  0x00CC  51: RSV18 */
+#define EC_I2C1_IRQn 36 /* 0x34  0x00D0  52: I2C1 */
+#define EC_RSV19_IRQn 37 /* 0x35  0x00D4  53: RSV19 */
+#define EC_RSV20_IRQn 38 /* 0x36  0x00D8  54: RSV20 */
+#define EC_RSV21_IRQn 39 /* 0x37  0x00DC  55: RSV21 */
+#define EC_RSV22_IRQn 40 /* 0x38  0x00E0  56: RSV22 */
+#define EC_RSV23_IRQn 41 /* 0x39  0x00E4  57: RSV23 */
+#define EC_RSV24_IRQn 42 /* 0x3A  0x00E8  58: RSV24 */
+#define EC_RSV25_IRQn 43 /* 0x3B  0x00EC  59: RSV25 */
+#define EC_RSV26_IRQn 44 /* 0x3C  0x00F0  60: RSV26 */
+#define EC_RSV27_IRQn 45 /* 0x3D  0x00F4  61: RSV27 */
+#define EC_RSV28_IRQn 46 /* 0x3E  0x00F8  62: RSV28 */
+#define EC_RSV29_IRQn 47 /* 0x3F  0x00FC  63: RSV29 */
+#define EC_RSV30_IRQn 48 /* 0x40  0x0100  64: RSV30 */
+#define EC_RSV31_IRQn 49 /* 0x41  0x0104  65: RSV31 */
+#define EC_RSV32_IRQn 50 /* 0x42  0x0108  66: RSV32 */
+#define EC_RSV33_IRQn 51 /* 0x43  0x010C  67: RSV33 */
+#define EC_RSV34_IRQn 52 /* 0x44  0x0110  68: RSV34 */
+#define EC_RSV35_IRQn 53 /* 0x45  0x0114  69: RSV35 */
 #define EC_GPIOWAKE_IRQn 54 /* 0x46  0x0118  70: GPIO Wakeup */
 
 #ifndef HIRC96_FREQ
@@ -72,8 +72,9 @@
 
 extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)  */
 #ifndef PeripheralClock
-#define PeripheralClock                                                        \
-	(SystemCoreClock / 2) /*!< Peripheral Clock Frequency                  \
+#define PeripheralClock    \
+	(SystemCoreClock / \
+	 2) /*!< Peripheral Clock Frequency                  \
 			       */
 #endif
 
@@ -143,6 +144,26 @@ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)  */
 
 #define DUMMY_GPIO_BANK GPIO_0
 
+/******************************************************************************/
+/*                                                                        I2C */
+#define MXC_I2C_INSTANCES (2)
+#define MXC_I2C_FIFO_DEPTH (8)
+
+#define MXC_BASE_I2C0 ((uint32_t)0x4001D000UL)
+#define MXC_I2C0 ((mxc_i2c_regs_t *)MXC_BASE_I2C0)
+#define MXC_BASE_I2C1 ((uint32_t)0x4001E000UL)
+#define MXC_I2C1 ((mxc_i2c_regs_t *)MXC_BASE_I2C1)
+
+#define MXC_I2C_GET_IRQ(i) \
+	(IRQn_Type)((i) == 0 ? I2C0_IRQn : (i) == 1 ? I2C1_IRQn : 0)
+
+#define MXC_I2C_GET_BASE(i) \
+	((i) == 0 ? MXC_BASE_I2C0 : (i) == 1 ? MXC_BASE_I2C1 : 0)
+
+#define MXC_I2C_GET_I2C(i) ((i) == 0 ? MXC_I2C0 : (i) == 1 ? MXC_I2C1 : 0)
+
+#define MXC_I2C_GET_IDX(p) ((p) == MXC_I2C0 ? 0 : (p) == MXC_I2C1 ? 1 : -1)
+
 #define MXC_CFG_TMR_INSTANCES (3)
 
 #define MXC_BASE_TMR0 ((uint32_t)0x40010000UL)
@@ -152,19 +173,19 @@ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)  */
 #define MXC_BASE_TMR2 ((uint32_t)0x40012000UL)
 #define MXC_TMR2 ((mxc_tmr_regs_t *)MXC_BASE_TMR2)
 
-#define MXC_TMR_GET_IRQ(i)                                                     \
-	(IRQn_Type)((i) == 0                                                   \
-			    ? TMR0_IRQn                                        \
-			    : (i) == 1 ? TMR1_IRQn : (i) == 2 ? TMR2_IRQn : 0)
+#define MXC_TMR_GET_IRQ(i)              \
+	(IRQn_Type)((i) == 0 ?          \
+			    TMR0_IRQn : \
+			    (i) == 1 ? TMR1_IRQn : (i) == 2 ? TMR2_IRQn : 0)
 
-#define MXC_TMR_GET_BASE(i)                                                    \
-	((i) == 0 ? MXC_BASE_TMR0                                              \
-		  : (i) == 1 ? MXC_BASE_TMR1 : (i) == 2 ? MXC_BASE_TMR2 : 0)
+#define MXC_TMR_GET_BASE(i)         \
+	((i) == 0 ? MXC_BASE_TMR0 : \
+		    (i) == 1 ? MXC_BASE_TMR1 : (i) == 2 ? MXC_BASE_TMR2 : 0)
 
-#define MXC_TMR_GET_TMR(i)                                                     \
+#define MXC_TMR_GET_TMR(i) \
 	((i) == 0 ? MXC_TMR0 : (i) == 1 ? MXC_TMR1 : (i) == 2 ? MXC_TMR2 : 0)
 
-#define MXC_TMR_GET_IDX(p)                                                     \
+#define MXC_TMR_GET_IDX(p) \
 	((p) == MXC_TMR0 ? 0 : (p) == MXC_TMR1 ? 1 : (p) == MXC_TMR2 ? 2 : -1)
 
 /******************************************************************************/
@@ -188,10 +209,10 @@ extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock)  */
 #define MXC_BASE_UART1 ((uint32_t)0x40043000UL)
 #define MXC_UART1 ((mxc_uart_regs_t *)MXC_BASE_UART1)
 
-#define MXC_UART_GET_IRQ(i)                                                    \
+#define MXC_UART_GET_IRQ(i) \
 	(IRQn_Type)((i) == 0 ? UART0_IRQn : (i) == 1 ? UART1_IRQn : 0)
 
-#define MXC_UART_GET_BASE(i)                                                   \
+#define MXC_UART_GET_BASE(i) \
 	((i) == 0 ? MXC_BASE_UART0 : (i) == 1 ? MXC_BASE_UART1 : 0)
 
 #define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : (i) == 1 ? MXC_UART1 : 0)