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| author | Vadim Bendebury <vbendeb@chromium.org> | 2019-08-14 18:45:02 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2019-10-01 06:15:48 +0000 |
| commit | 4805196e894a73a2a1285f1cd622d160ad248f77 (patch) | |
| tree | 11f055890aad15fb87f079023132147678b91ed7 | |
| parent | 24996f6911bd12eacc927f991ea169bad4c7c1f9 (diff) | |
| download | chrome-ec-4805196e894a73a2a1285f1cd622d160ad248f77.tar.gz | |
cr50: debounce successive TPM reset pulses
Some platforms generate more than one pulse when resetting, many Intel
SOCs generate two pulses, some other chips could go even higher.
TPM reset on Cr50 is processed asynchronously, repetitive pulses
result in multiple reset processing cycles.In case pulses are coming
too soon one after another this could cause some race conditions.
Let's ignore repetitive reset pulses unless there has been an attempt
by the host to read a register (which is usually the very first action
of the AP when booting up).
BRANCH=cr50, cr50-mp
BUG=none
TEST=observed that only one reset is happening on an Octopus device,
while there are two pulses present on the PLT_RST_L line.
Verified proper reboot multiple times in a row.
Change-Id: Ie1b124d41be0388bd8e12d0084827782de62cfa0
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1755059
Reviewed-by: Mary Ruthven <mruthven@chromium.org>
| -rw-r--r-- | common/tpm_registers.c | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/common/tpm_registers.c b/common/tpm_registers.c index f228503e7a..6a57fa814f 100644 --- a/common/tpm_registers.c +++ b/common/tpm_registers.c @@ -424,9 +424,6 @@ void tpm_register_put(uint32_t regaddr, const uint8_t *data, uint32_t data_size) { uint32_t i; - if (reset_in_progress) - return; - CPRINTF("%s(0x%03x, %d,", __func__, regaddr, data_size); for (i = 0; i < data_size && i < 4; i++) CPRINTF(" %02x", data[i]); @@ -498,6 +495,8 @@ void tpm_register_get(uint32_t regaddr, uint8_t *dest, uint32_t data_size) { int i; + reset_in_progress = 0; + CPRINTF("%s(0x%06x, %d)", __func__, regaddr, data_size); switch (regaddr) { case TPM_DID_VID: @@ -890,8 +889,6 @@ static void tpm_reset_now(int wipe_first) */ hook_call_deferred(&reinstate_nvmem_commits_data, 3 * SECOND); - reset_in_progress = 0; - /* * In chip factory mode SPI idle byte sent on MISO is used for * progress reporting. TPM flow control messes it up, do not start TPM |