diff options
| author | Mary Ruthven <mruthven@chromium.org> | 2019-10-07 15:43:46 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2019-10-08 19:58:41 +0000 |
| commit | a8237a64b798dbf52419303d4e5c623b82870d98 (patch) | |
| tree | 861668c46ce0e053c2980637f95b6a91227a5217 | |
| parent | a575b3abb12d4f05482781f9cff028cfa4fc9917 (diff) | |
| download | chrome-ec-a8237a64b798dbf52419303d4e5c623b82870d98.tar.gz | |
docs: ccd gsc: add description of G3 WP issue
Cr50 may not be able to disable write protect in G3. Add a description
and workaround for this issue to the ccd gsc docs.
BUG=b:140551928
BRANCH=none
TEST=none
Change-Id: I752a1d4fd5a148af44b595924e57aaa7ec64e7a4
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1845780
Reviewed-by: Wai-Hong Tam <waihong@google.com>
| -rw-r--r-- | docs/case_closed_debugging_cr50.md | 27 | ||||
| -rw-r--r-- | docs/ccd_howtos.md | 6 |
2 files changed, 30 insertions, 3 deletions
diff --git a/docs/case_closed_debugging_cr50.md b/docs/case_closed_debugging_cr50.md index 8a76cf6419..0d777c3038 100644 --- a/docs/case_closed_debugging_cr50.md +++ b/docs/case_closed_debugging_cr50.md @@ -563,15 +563,15 @@ wp setting is reset to `follow_batt_pres` cr50 > wp follow_batt_pres atboot -#### HW WP quirks +### HW WP Issues -##### Chromeboxes +#### Chromeboxes Chromeboxes do not have batteries, so cr50 can't use battery presence for write protect. They use a write protect screw. You need to remove the write protect screw to disable write protect if cr50 is set to `follow_batt_pres`. -##### Bob +#### Bob Bob's have a write protect screw in addition to battery presence. The write protect screw will force enable write protect until it's removed. If cr50 is set @@ -579,6 +579,27 @@ to `follow_batt_pres`, you need to remove the write protect screw and disconnect the battery to disable write protect. If you run `wp disable`, you will also need to remove the screw. +#### AP Off + +Cr50 puts the device in reset to flash the AP. Due to hardware limitiations Cr50 +may not be able to disable write protect while the device is in reset. If you +want to reflash RO firmware using CCD and your board has issues disabling HW WP, +you may need to disable SW write protect. + +Check if your board has this issue + +1. Disable write protect using the cr50 console command + +2. Check it's still disabled when the AP is off. This command should show write + protect is disabled. If it shows it's enabled, then cr50 can't disable WP + when the AP is off. You should disable SW WP to flash RO firmware using ccd. + + chroot > sudo flashrom -p raiden_debug_spi:target=AP --wp-status + +Disable SW WP if the ccd flashrom command doesn't show write protect disabled. + + from AP > flashrom -p host --wp-disable + # CCD as a Servo replacement Once cr50 is open and all capabilities have been set to Always, cr50 should be diff --git a/docs/ccd_howtos.md b/docs/ccd_howtos.md index 874db1d415..8024d0cde7 100644 --- a/docs/ccd_howtos.md +++ b/docs/ccd_howtos.md @@ -199,7 +199,13 @@ It goes into a lot more detail. Cr50 > ccd set OpenNoDevMode Always Cr50 > ccd set OpenFromUSB Always +6. **(recommended) [Disable SW WP]** to flash RO firmware if your board has + issues disabling HW WP with the AP off. + + AP > flashrom -p host --wp-disable + [Setup CCD]: ./case_closed_debugging_cr50.md#CCD-Setup [sparkfun]: https://www.sparkfun.com/products/14746 [SuzyQ]: https://chromium.googlesource.com/chromiumos/third_party/hdctools/+/refs/heads/master/docs/ccd.md#suzyq-suzyqable [wp console command]: ./case_closed_debugging_cr50.md#WP-control +[Disable SW WP]: ./case_closed_debugging_cr50.md#AP-Off |