diff options
| author | Josh Tsai <josh_tsai@compal.corp-partner.google.com> | 2019-12-04 13:14:41 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2019-12-05 05:14:45 +0000 |
| commit | fee6e280e6729276e061fad8594cb2d29472411d (patch) | |
| tree | b82c676b717cb8b3f9a36023b164e16930d6bb64 | |
| parent | d112a590dd8cdebca2aaff6435345f0cd31903d8 (diff) | |
| download | chrome-ec-fee6e280e6729276e061fad8594cb2d29472411d.tar.gz | |
stryke: Assign SYS_RST_ODL to GPIOC5 and make sure EC_RST_ODL is LOCKED
There is an error where SYS_RST_ODL is assigned to GPIO02 where it is
actually assigned to GPIOC5 in the schematics.
BUG=b:145369657
BRANCH=none
TEST=make buildall
Change-Id: I26a4b37baf160714bc07d8f9eb5df7234e76d96e
Signed-off-by: Josh Tsai <josh_tsai@compal.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1948701
Reviewed-by: Ruby Lee <ruby_lee@compal.corp-partner.google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
| -rw-r--r-- | board/stryke/gpio.inc | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/board/stryke/gpio.inc b/board/stryke/gpio.inc index cd241f15f5..8c7977f585 100644 --- a/board/stryke/gpio.inc +++ b/board/stryke/gpio.inc @@ -44,8 +44,8 @@ GPIO_INT(HDMI_CONN_HPD, PIN(7, 2), GPIO_INT_BOTH, hdmi_hpd_interrupt) GPIO_INT(EC_VOLDN_BTN_ODL, PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt) GPIO_INT(EC_VOLUP_BTN_ODL, PIN(7, 5), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt) -/* SYS_RESET_L should be set to GPIOC5 per schematics, but was never built, so leaving as GPIO02 */ -GPIO(SYS_RESET_L, PIN(0, 2), GPIO_ODR_HIGH) /* SYS_RST_ODL */ + +GPIO(SYS_RESET_L, PIN(C, 5), GPIO_ODR_HIGH) /* SYS_RST_ODL */ GPIO(ENTERING_RW, PIN(E, 3), GPIO_OUT_LOW) /* EC_ENTERING_RW */ GPIO(PCH_WAKE_L, PIN(7, 4), GPIO_ODR_HIGH) /* EC_PCH_WAKE_ODL */ GPIO(PCH_PWRBTN_L, PIN(C, 1), GPIO_ODR_HIGH) /* EC_PCH_PWR_BTN_ODL */ @@ -63,6 +63,17 @@ GPIO(CPU_C10_GATE_L, PIN(6, 7), GPIO_INPUT) /* MKBP event synchronization */ GPIO(EC_INT_L, PIN(7, 0), GPIO_ODR_HIGH) +/* + * GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an + * interrupt handler because it is automatically handled by the PSL. + * + * We need to lock the setting so this gpio can't be reconfigured to overdrive + * the real reset signal. (This is the PSL input pin not the real reset pin). + */ +GPIO(EC_RST_ODL, PIN(0, 2), GPIO_INT_BOTH | + GPIO_HIB_WAKE_HIGH | + GPIO_LOCKED) + /* USB and USBC Signals */ GPIO(USB_C_OC_ODL, PIN(B, 1), GPIO_ODR_HIGH) GPIO(USB_C0_TCPC_RST, PIN(9, 7), GPIO_OUT_LOW) |