Morphius: create new board

BUG=b:144029292
BRANCH=none
TEST=build

Change-Id: Id362ac64a43082e0ae2cb59c0259f040c693dd1f
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1954308
Reviewed-by: Denis Brockus <dbrockus@chromium.org>

8 files changed, 424 insertions, 0 deletions

diff --git a/board/morphius/analyzestack.yaml b/board/morphius/analyzestack.yaml
new file mode 100644
index 0000000000..7ff5f39644
--- /dev/null
+++ b/board/morphius/analyzestack.yaml
@@ -0,0 +1,2 @@
+remove:
+- panic_assert_fail
diff --git a/board/morphius/battery.c b/board/morphius/battery.c
new file mode 100644
index 0000000000..33e4e9ce5d
--- /dev/null
+++ b/board/morphius/battery.c
@@ -0,0 +1,65 @@
+/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * Battery pack vendor provided charging profile
+ */
+
+#include "battery_fuel_gauge.h"
+#include "common.h"
+#include "util.h"
+
+/*
+ * Battery info for all Zork battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	/* AP18F4M */
+	[BATTERY_AP18F4M] = {
+		.fuel_gauge = {
+			.manuf_name = "Murata KT00404001",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.reg_addr = 0x0,
+				.reg_mask = 0x2000,
+				.disconnect_val = 0x2000,
+			}
+		},
+		.batt_info = {
+			.voltage_max          = 8700,
+			.voltage_normal       = 7600,
+			.voltage_min          = 5500,
+			.precharge_current    = 256,
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 50,
+			.charging_min_c       = 0,
+			.charging_max_c       = 60,
+			.discharging_min_c    = -20,
+			.discharging_max_c    = 75,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_AP18F4M;
diff --git a/board/morphius/board.c b/board/morphius/board.c
new file mode 100644
index 0000000000..ad4ea69091
--- /dev/null
+++ b/board/morphius/board.c
@@ -0,0 +1,43 @@
+/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Morphius board configuration */
+
+#include "button.h"
+#include "driver/accelgyro_bmi160.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "switch.h"
+#include "system.h"
+#include "usb_charge.h"
+
+#include "gpio_list.h"
+
+/* These GPIOs moved. Temporarily detect and support the V0 HW. */
+enum gpio_signal GPIO_PCH_PWRBTN_L = GPIO_EC_FCH_PWR_BTN_L;
+enum gpio_signal GPIO_PCH_SYS_PWROK = GPIO_EC_FCH_PWROK;
+
+void board_update_sensor_config_from_sku(void)
+{
+	int data;
+
+	/*
+	 * If the CBI EEPROM is found on the battery I2C port then we are
+	 * running on V0 HW so re-map the GPIOs that moved.
+	 */
+	if ((system_get_sku_id() == 0)
+	    && (i2c_read8(I2C_PORT_BATTERY, I2C_ADDR_EEPROM_FLAGS, 0, &data)
+		== EC_SUCCESS)) {
+		ccprints("V0 HW detected");
+		GPIO_PCH_PWRBTN_L = GPIO_EC_FCH_PWR_BTN_L_V0;
+		GPIO_PCH_SYS_PWROK = GPIO_EC_FCH_PWROK_V0;
+	}
+
+	/* Enable Gyro interrupts */
+	gpio_enable_interrupt(GPIO_6AXIS_INT_L);
+}
diff --git a/board/morphius/board.h b/board/morphius/board.h
new file mode 100644
index 0000000000..c9f8e6487a
--- /dev/null
+++ b/board/morphius/board.h
@@ -0,0 +1,71 @@
+/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Morphius board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#include "baseboard.h"
+
+/*
+ * Allow dangerous commands.
+ * TODO: Remove this config before production.
+ */
+#define CONFIG_SYSTEM_UNLOCKED
+#define CONFIG_BRINGUP
+#define CONFIG_I2C_DEBUG
+
+#define CONFIG_MKBP_USE_GPIO
+
+/* Motion sensing drivers */
+#define CONFIG_ACCELGYRO_BMI160
+#define CONFIG_ACCELGYRO_BMI160_INT_EVENT \
+	TASK_EVENT_MOTION_SENSOR_INTERRUPT(BASE_ACCEL)
+#define CONFIG_ACCEL_INTERRUPTS
+#define CONFIG_ACCEL_KX022
+#define CONFIG_CMD_ACCELS
+#define CONFIG_CMD_ACCEL_INFO
+#define CONFIG_TABLET_MODE
+#define CONFIG_LID_ANGLE
+#define CONFIG_LID_ANGLE_UPDATE
+#define CONFIG_LID_ANGLE_SENSOR_BASE BASE_ACCEL
+#define CONFIG_LID_ANGLE_SENSOR_LID LID_ACCEL
+
+/* GPIO mapping from board specific name to EC common name. */
+#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_EC_BATT_PRES_ODL
+#define GPIO_AC_PRESENT			GPIO_ACOK_OD
+#define GPIO_CPU_PROCHOT		GPIO_PROCHOT_ODL
+#define GPIO_EC_INT_L			GPIO_EC_AP_INT_ODL
+#define GPIO_ENABLE_BACKLIGHT_L		GPIO_EC_EDP_BL_DISABLE
+#define GPIO_ENTERING_RW		GPIO_EC_ENTERING_RW
+#define GPIO_KBD_KSO2			GPIO_EC_KSO_02_INV
+#define GPIO_PCH_RSMRST_L		GPIO_EC_FCH_RSMRST_L
+#define GPIO_PCH_SLP_S3_L		GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S5_L		GPIO_SLP_S5_L
+#define GPIO_PCH_WAKE_L			GPIO_EC_FCH_WAKE_L
+#define GPIO_POWER_BUTTON_L		GPIO_EC_PWR_BTN_ODL
+#define GPIO_S0_PGOOD			GPIO_S0_PWROK_OD
+#define GPIO_S5_PGOOD			GPIO_EC_PWROK_OD
+#define GPIO_SYS_RESET_L		GPIO_EC_SYS_RST_L
+#define GPIO_VOLUME_DOWN_L		GPIO_VOLDN_BTN_ODL
+#define GPIO_VOLUME_UP_L		GPIO_VOLUP_BTN_ODL
+#define GPIO_WP_L			GPIO_EC_WP_L
+
+#ifndef __ASSEMBLER__
+
+/* These GPIOs moved. Temporarily detect and support the V0 HW. */
+extern enum gpio_signal GPIO_PCH_PWRBTN_L;
+extern enum gpio_signal GPIO_PCH_SYS_PWROK;
+
+enum battery_type {
+	BATTERY_AP18F4M,
+	BATTERY_TYPE_COUNT,
+};
+
+#endif /* !__ASSEMBLER__ */
+
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/morphius/build.mk b/board/morphius/build.mk
new file mode 100644
index 0000000000..4ca0cbd96f
--- /dev/null
+++ b/board/morphius/build.mk
@@ -0,0 +1,15 @@
+# -*- makefile -*-
+# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx7
+CHIP_VARIANT:=npcx7m7wc
+BASEBOARD:=zork
+
+board-y=board.o led.o
+board-$(CONFIG_BATTERY_SMART)+=battery.o
diff --git a/board/morphius/ec.tasklist b/board/morphius/ec.tasklist
new file mode 100644
index 0000000000..4c4a4898b1
--- /dev/null
+++ b/board/morphius/ec.tasklist
@@ -0,0 +1,26 @@
+/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(MOTIONSENSE, motion_sense_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
+	TASK_NOTEST(PDCMD, pd_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/board/morphius/gpio.inc b/board/morphius/gpio.inc
new file mode 100644
index 0000000000..85de6ca3eb
--- /dev/null
+++ b/board/morphius/gpio.inc
@@ -0,0 +1,132 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first. */
+
+GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(3, 4), GPIO_INT_FALLING,			tcpc_alert_event)
+GPIO_INT(USB_C1_TCPC_INT_ODL,	PIN(F, 1), GPIO_INT_FALLING,			tcpc_alert_event)
+GPIO_INT(USB_C0_PPC_FAULT_ODL,	PIN(6, 3), GPIO_INT_FALLING,			ppc_interrupt)
+GPIO_INT(USB_C1_PPC_INT_ODL,	PIN(D, 4), GPIO_INT_FALLING,			ppc_interrupt)
+GPIO_INT(USB_C0_BC12_INT_ODL,	PIN(9, 3), GPIO_INT_FALLING | GPIO_PULL_UP,	bc12_interrupt)
+GPIO_INT(USB_C1_BC12_INT_ODL, 	PIN(A, 4), GPIO_INT_FALLING | GPIO_PULL_UP,	bc12_interrupt)
+GPIO_INT(SLP_S3_L,		PIN(7, 4), GPIO_INT_BOTH,			power_signal_interrupt)
+GPIO_INT(SLP_S5_L,		PIN(E, 0), GPIO_INT_BOTH,			power_signal_interrupt)
+GPIO_INT(S0_PWROK_OD,		PIN(5, 6), GPIO_INT_BOTH,			power_signal_interrupt)
+GPIO_INT(EC_PWROK_OD,		PIN(3, 7), GPIO_INT_BOTH,			power_signal_interrupt)
+GPIO_INT(EC_PWR_BTN_ODL,	PIN(0, 1), GPIO_INT_BOTH,			power_button_interrupt)
+GPIO_INT(LID_OPEN,		PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	lid_interrupt)
+GPIO_INT(ACOK_OD,		PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	extpower_interrupt)
+GPIO_INT(EC_WP_L,		PIN(5, 0), GPIO_INT_BOTH,			switch_interrupt)
+GPIO_INT(VOLDN_BTN_ODL,		PIN(A, 6), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
+GPIO_INT(VOLUP_BTN_ODL,		PIN(9, 5), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
+GPIO_INT(6AXIS_INT_L,		PIN(A, 0), GPIO_INT_FALLING | GPIO_PULL_UP,	bmi160_interrupt)
+
+/* GPIO_INT_BOTH is required for PSL wake from hibernate, but we don't need an interrupt handler. */
+GPIO(EC_RST_ODL,		PIN(0, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH)
+
+GPIO(3AXIS_INT_L,		PIN(9, 6), GPIO_INPUT | GPIO_PULL_UP)		/* 3 Axis Accel */
+GPIO(CCD_MODE_ODL,		PIN(C, 6), GPIO_INPUT)				/* Case Closed Debug Mode */
+GPIO(PROCHOT_ODL,		PIN(D, 5), GPIO_ODR_HIGH)			/* PROCHOT to SOC */
+GPIO(EC_BATT_PRES_ODL,		PIN(4, 1), GPIO_INPUT)				/* Battery Present */
+GPIO(EC_AP_INT_ODL,		PIN(A, 3), GPIO_ODR_HIGH)			/* Sensor MKBP event to SOC */
+GPIO(EN_PWR_A,			PIN(B, 7), GPIO_OUT_LOW)			/* Enable Power */
+GPIO(EC_EDP_BL_DISABLE,		PIN(A, 2), GPIO_OUT_HIGH)			/* Enable Backlight */
+GPIO(EC_ENTERING_RW,		PIN(E, 5), GPIO_OUT_LOW)			/* EC Entering RW */
+GPIO(EC_FCH_PWR_BTN_L,		PIN(6, 2), GPIO_OUT_HIGH)			/* Power Button to SOC */
+GPIO(EC_FCH_PWR_BTN_L_V0,	PIN(8, 6), GPIO_OUT_HIGH)			/* Power Button to SOC */
+GPIO(EC_FCH_RSMRST_L,		PIN(A, 1), GPIO_OUT_LOW)			/* RSMRST# to SOC */
+GPIO(EC_FCH_PWROK,		PIN(D, 3), GPIO_OUT_LOW)			/* Power OK to SOC */
+GPIO(EC_FCH_PWROK_V0,		PIN(7, 5), GPIO_OUT_LOW)			/* Power OK to SOC */
+GPIO(EC_FCH_WAKE_L,		PIN(0, 3), GPIO_OUT_HIGH)			/* Wake SOC */
+GPIO(EC_SYS_RST_L,		PIN(C, 7), GPIO_ODR_HIGH)			/* Cold Reset to SOC */
+GPIO(USB_C0_TCPC_RST_L,		PIN(E, 1), GPIO_OUT_HIGH)			/* C0 TCPC Reset */
+GPIO(USB_C1_TCPC_RST_L,		PIN(F, 0), GPIO_OUT_HIGH)			/* C1 TCPC Reset */
+GPIO(USB_C0_HPD,		PIN(F, 5), GPIO_OUT_LOW)			/* C0 DP Hotplug Detect */
+GPIO(USB_C0_IN_HPD,		PIN(7, 3), GPIO_OUT_LOW)			/* C0 IN Hotplug Detect */
+GPIO(DP2_HPD,			PIN(C, 1), GPIO_OUT_LOW)			/* C1 DP Hotplug Detect */
+
+GPIO(LED_FULL_L,		PIN(6, 0), GPIO_OUT_HIGH)
+GPIO(LED_CHRG_L,		PIN(C, 0), GPIO_OUT_HIGH)
+
+IOEX(USB_A0_RETIMER_EN,		EXPIN(USBC_PORT_C0, 0, 0), GPIO_OUT_HIGH)	/* A0 Retimer Enable */
+IOEX(USB_A0_RETIMER_RST,	EXPIN(USBC_PORT_C0, 0, 1), GPIO_OUT_LOW)	/* A0 Retimer Reset */
+IOEX(USB_C0_FAULT_ODL,		EXPIN(USBC_PORT_C0, 0, 3), GPIO_ODR_HIGH)	/* C0 Fault to SOC */
+IOEX(USB_C0_TCPC_FASTSW_CTL_EN,	EXPIN(USBC_PORT_C0, 0, 4), GPIO_OUT_LOW)	/* C0 FastSwitch Control */
+IOEX(USB_C1_FAULT_ODL,		EXPIN(USBC_PORT_C0, 1, 0), GPIO_ODR_HIGH)	/* C1 Fault to SOC */
+IOEX(USB_C0_PPC_ILIM_3A_EN,	EXPIN(USBC_PORT_C0, 1, 1), GPIO_OUT_LOW)	/* C0 3A Current Limit Enable */
+IOEX(USB_C0_SBU_FAULT_ODL,	EXPIN(USBC_PORT_C0, 1, 2), GPIO_INPUT)		/* C0 SBU Fault */
+IOEX(KB_BL_EN,			EXPIN(USBC_PORT_C0, 1, 3), GPIO_OUT_LOW)	/* KB Backlight Enable */
+IOEX(USB_C0_DATA_EN,		EXPIN(USBC_PORT_C0, 1, 4), GPIO_OUT_LOW)	/* C0 Data Enable */
+IOEX(EN_USB_A0_5V,		EXPIN(USBC_PORT_C0, 1, 5), GPIO_OUT_LOW)	/* A0 5V Source Enable */
+IOEX(USB_A0_CHARGE_EN_L,	EXPIN(USBC_PORT_C0, 1, 6), GPIO_OUT_HIGH)	/* A0 5V High Current Enable */
+
+IOEX(USB_A1_RETIMER_EN,		EXPIN(USBC_PORT_C1, 0, 0), GPIO_OUT_HIGH)	/* A1 Retimer Enable */
+IOEX(USB_A1_RETIMER_RST_DB,	EXPIN(USBC_PORT_C1, 0, 1), GPIO_OUT_LOW)	/* A1 Retimer Reset */
+IOEX(USB_C1_HPD_IN_DB,		EXPIN(USBC_PORT_C1, 0, 2), GPIO_OUT_LOW)	/* C1 HPD */
+IOEX(MST_HPD_OUT,		EXPIN(USBC_PORT_C1, 0, 3), GPIO_INPUT)		/* HPD from MST Hub */
+IOEX(USB_C1_TCPC_FASTSW_CTL_EN,	EXPIN(USBC_PORT_C1, 0, 4), GPIO_OUT_LOW)	/* C1 FastSwitch Control */
+IOEX(HDMI_CONN_HPD_3V3_DB,	EXPIN(USBC_PORT_C1, 1, 0), GPIO_INPUT)		/* HDMI HPD */
+IOEX(USB_C1_MUX_RST_DB,		EXPIN(USBC_PORT_C1, 1, 1), GPIO_OUT_LOW)	/* C1 Mux Reset */
+IOEX(USB_C1_SBU_FAULT_DB_ODL,	EXPIN(USBC_PORT_C1, 1, 2), GPIO_INPUT)		/* C1 SBU Fault */
+IOEX(USB_C1_PPC_EN_L,		EXPIN(USBC_PORT_C1, 1, 3), GPIO_OUT_LOW)	/* C1 PPC Enable */
+IOEX(HDMI_DATA_EN_DB,		EXPIN(USBC_PORT_C1, 1, 4), GPIO_OUT_HIGH)	/* HDMI Retimer Enable */
+IOEX(USB_C1_DATA_EN,		EXPIN(USBC_PORT_C1, 1, 5), GPIO_OUT_HIGH)	/* C1 Retimer Enable */
+IOEX(EN_USB_A1_5V_DB,		EXPIN(USBC_PORT_C1, 1, 6), GPIO_OUT_LOW)	/* A1 5V Source Enable */
+IOEX(USB_A1_CHARGE_EN_DB_L,	EXPIN(USBC_PORT_C1, 1, 7), GPIO_OUT_HIGH)	/* A1 5V High Current Enable */
+
+/*
+ * The NPCX LPC driver configures and controls SCI, so PCH_SCI_ODL [PIN(7, 6)]
+ * is not defined here as GPIO.
+ */
+
+/* I2C pins - these will be reconfigured for alternate function below */
+GPIO(EC_I2C_USB_A0_C0_SCL,	PIN(B, 5), GPIO_INPUT)
+GPIO(EC_I2C_USB_A0_C0_SDA,	PIN(B, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_A1_C1_SCL,	PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_A1_C1_SDA,	PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C_POWER_SCL,		PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C_POWER_SDA,		PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C_USBC_AP_MUX_SCL,	PIN(D, 1), GPIO_INPUT)
+GPIO(EC_I2C_USBC_AP_MUX_SDA,	PIN(D, 0), GPIO_INPUT)
+GPIO(FCH_SIC,			PIN(F, 3), GPIO_INPUT)
+GPIO(FCH_SID,			PIN(F, 2), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_CBI_SCL,	PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_CBI_SDA,	PIN(3, 6), GPIO_INPUT)
+GPIO(FCH_I2C_AUDIO_SCL,		PIN(E, 4), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(FCH_I2C_AUDIO_SDA,		PIN(E, 3), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(FCH_I2C_HDMI_HUB_3V3_SCL,	PIN(B, 3), GPIO_INPUT)
+GPIO(FCH_I2C_HDMI_HUB_3V3_SDA,	PIN(B, 2), GPIO_INPUT)
+
+ALTERNATE(PIN_MASK(6, BIT(4) | BIT(5)), 0, MODULE_UART, 0) /* Cr50 requires no pullups. */
+
+ALTERNATE(PIN_MASK(B, BIT(4) | BIT(5)), 0, MODULE_I2C, 0)			/* I2C0 */
+ALTERNATE(PIN_MASK(9, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_I2C, 0)		/* I2C1 SCL / I2C2 */
+ALTERNATE(PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)				/* I2C1 SDA */
+ALTERNATE(PIN_MASK(D, BIT(0) | BIT(1)), 0, MODULE_I2C, 0)			/* I2C3 */
+ALTERNATE(PIN_MASK(F, BIT(2) | BIT(3)), 0, MODULE_I2C, 0)			/* I2C4 */
+ALTERNATE(PIN_MASK(3, BIT(3) | BIT(6)), 0, MODULE_I2C, 0)			/* I2C5 */
+ALTERNATE(PIN_MASK(E, BIT(3) | BIT(4)), 0, MODULE_I2C, 0)			/* I2C6 */
+ALTERNATE(PIN_MASK(B, BIT(2) | BIT(3)), 0, MODULE_I2C, 0)			/* I2C7 */
+
+ALTERNATE(PIN_MASK(4, BIT(2) | BIT(3)), 0, MODULE_ADC, 0)			/* ADC2, ADC3 Temp Sensors */
+
+ALTERNATE(PIN_MASK(C, BIT(3)), 0, MODULE_PWM, 0)				/* PWM0 LED */
+ALTERNATE(PIN_MASK(C, BIT(4)), 0, MODULE_PWM, 0)				/* PWM2 - EC_FAN_PWM */
+ALTERNATE(PIN_MASK(8, BIT(0)), 0, MODULE_PWM, 0)				/* PWM3 KB Backlight */
+ALTERNATE(PIN_MASK(4, BIT(0)), 0, MODULE_PWM, 0)				/* TA1 - EC_FAN_SPEED */
+
+ALTERNATE(PIN_MASK(3, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)		/* KSI_00-01 */
+ALTERNATE(PIN_MASK(2, 0xFC), 0, MODULE_KEYBOARD_SCAN, GPIO_INPUT)		/* KSI_02-07 */
+ALTERNATE(PIN_MASK(2, 0x03), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_00-01 */
+GPIO(EC_KSO_02_INV, PIN(1, 7), GPIO_OUT_LOW)					/* KSO_02 inverted */
+ALTERNATE(PIN_MASK(1, 0x7F), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_03-09 */
+ALTERNATE(PIN_MASK(0, 0xE0), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)		/* KSO_10-12 */
+
+/* Power Switch Logic (PSL) inputs */
+ALTERNATE(PIN_MASK(0, BIT(0) | BIT(1) | BIT(2)), 0, MODULE_PMU, 0)		/* AC_PRESENT, POWER_BUTTON_L, EC_RST_ODL */
+ALTERNATE(PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0)				/* LID_OPEN */
diff --git a/board/morphius/led.c b/board/morphius/led.c
new file mode 100644
index 0000000000..9f3f7492c0
--- /dev/null
+++ b/board/morphius/led.c
@@ -0,0 +1,70 @@
+/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "ec_commands.h"
+#include "gpio.h"
+#include "led_common.h"
+#include "led_onoff_states.h"
+
+#define LED_OFF_LVL	1
+#define LED_ON_LVL	0
+
+const int led_charge_lvl_1;
+const int led_charge_lvl_2 = 100;
+
+struct led_descriptor led_bat_state_table[LED_NUM_STATES][LED_NUM_PHASES] = {
+	[STATE_CHARGING_LVL_1]       = {{EC_LED_COLOR_GREEN,  2 * LED_ONE_SEC},
+					{EC_LED_COLOR_RED, 2 * LED_ONE_SEC} },
+	[STATE_CHARGING_LVL_2]	     = {{EC_LED_COLOR_RED, LED_INDEFINITE} },
+	[STATE_CHARGING_FULL_CHARGE] = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
+	[STATE_DISCHARGE_S0]	     = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
+	[STATE_DISCHARGE_S3]	     = {{EC_LED_COLOR_RED, 1 * LED_ONE_SEC},
+					{LED_OFF,            3 * LED_ONE_SEC} },
+	[STATE_DISCHARGE_S5]         = {{LED_OFF,            LED_INDEFINITE} },
+	[STATE_BATTERY_ERROR]        = {{EC_LED_COLOR_GREEN,  2 * LED_ONE_SEC},
+					{EC_LED_COLOR_RED, 2 * LED_ONE_SEC} },
+	[STATE_FACTORY_TEST]         = {{EC_LED_COLOR_GREEN,  LED_INDEFINITE} },
+};
+BUILD_ASSERT(ARRAY_SIZE(led_bat_state_table) == LED_NUM_STATES);
+
+const enum ec_led_id supported_led_ids[] = { EC_LED_ID_BATTERY_LED };
+
+const int supported_led_ids_count = ARRAY_SIZE(supported_led_ids);
+
+void led_set_color_battery(enum ec_led_colors color)
+{
+	switch (color) {
+	case EC_LED_COLOR_GREEN:
+		gpio_set_level(GPIO_LED_FULL_L, LED_ON_LVL);
+		gpio_set_level(GPIO_LED_CHRG_L, LED_OFF_LVL);
+		break;
+	case EC_LED_COLOR_RED:
+		gpio_set_level(GPIO_LED_FULL_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_LED_CHRG_L, LED_ON_LVL);
+		break;
+	default: /* LED_OFF and other unsupported colors */
+		gpio_set_level(GPIO_LED_FULL_L, LED_OFF_LVL);
+		gpio_set_level(GPIO_LED_CHRG_L, LED_OFF_LVL);
+		break;
+	}
+}
+
+void led_get_brightness_range(enum ec_led_id led_id, uint8_t *brightness_range)
+{
+	brightness_range[EC_LED_COLOR_GREEN] = 1;
+	brightness_range[EC_LED_COLOR_RED] = 1;
+}
+
+int led_set_brightness(enum ec_led_id led_id, const uint8_t *brightness)
+{
+	if (brightness[EC_LED_COLOR_GREEN] != 0)
+		led_set_color_battery(EC_LED_COLOR_GREEN);
+	else if (brightness[EC_LED_COLOR_RED] != 0)
+		led_set_color_battery(EC_LED_COLOR_RED);
+	else
+		led_set_color_battery(LED_OFF);
+
+	return EC_SUCCESS;
+}