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| author | Vijay Hiremath <vijay.p.hiremath@intel.com> | 2020-01-15 16:36:50 -0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-01-22 00:04:22 +0000 |
| commit | 02262da3d35be2a0b73361923b8d3e841564beaf (patch) | |
| tree | ea2481c44f893b2f26c5f31dcf623dc60ac0211f | |
| parent | 7616354e44fb36d2721bc6bdb6bd8d18697fd60b (diff) | |
| download | chrome-ec-02262da3d35be2a0b73361923b8d3e841564beaf.tar.gz | |
TBT: Allow entering TBT mode for passive cables without SVID
Passive cables without Intel SVID can nack to the Discover SVID SOP'.
For these cables, limit the speed of TBT device to cables speed or TBT
Passive Gen2 cable speed whichever is lowest.
Ref: USB Type-C Cable and Connector Specification 2.0
Figure F-1 TBT3 Discovery Flow
BUG=b:147732811
BRANCH=none
TEST=Manually tested on Volteer.
Using Rev2 Gen1 cable device can enter into TBT mode
Change-Id: I654056f434501898e60152c52f6d85f81ae35a78
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2003506
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
| -rw-r--r-- | common/usb_pd_policy.c | 42 |
1 files changed, 32 insertions, 10 deletions
diff --git a/common/usb_pd_policy.c b/common/usb_pd_policy.c index 6df5e940b1..685bf061a2 100644 --- a/common/usb_pd_policy.c +++ b/common/usb_pd_policy.c @@ -874,6 +874,8 @@ static int process_tbt_compat_discover_modes(int port, uint32_t *payload) if (is_transmit_msg_sop_prime(port)) { /* Store Discover Mode SOP' response */ cable[port].cable_mode_resp.raw_value = payload[1]; + + /* Cable does not have Intel SVID for Discover SVID */ if (is_limit_tbt_cable_speed(port)) cable[port].cable_mode_resp.tbt_cable_speed = TBT_SS_U32_GEN1_GEN2; @@ -897,10 +899,27 @@ static int process_tbt_compat_discover_modes(int port, uint32_t *payload) /* Store Discover Mode SOP response */ cable[port].dev_mode_resp.raw_value = payload[1]; - /* Discover modes for SOP' */ - pe[port].svid_idx--; - rsize = dfp_discover_modes(port, payload); - enable_transmit_sop_prime(port); + if (is_limit_tbt_cable_speed(port)) { + /* + * Passive cable has Nacked for Discover SVID. + * No need to do Discover modes of cable. Assign the + * cable discovery attributes and enter into device + * Thunderbolt-compatible mode. + */ + cable[port].cable_mode_resp.tbt_cable_speed = + (cable[port].rev == PD_REV30 && + cable[port].attr.p_rev30.ss > + USB_R30_SS_U32_U40_GEN2) ? + TBT_SS_U32_GEN1_GEN2 : + cable[port].attr.p_rev30.ss; + + rsize = enter_tbt_compat_mode(port, payload); + } else { + /* Discover modes for SOP' */ + pe[port].svid_idx--; + rsize = dfp_discover_modes(port, payload); + enable_transmit_sop_prime(port); + } } return rsize; @@ -1157,12 +1176,15 @@ int pd_svdm(int port, int cnt, uint32_t *payload, uint32_t **rpayload, rsize = 0; } } else if (cmd_type == CMDT_RSP_NAK) { - rsize = 0; - /* Send SOP' Discover Ident message, if not already received. */ - if (IS_ENABLED(CONFIG_USB_PD_DECODE_SOP) && - !cable[port].is_identified && (cmd == CMD_DISCOVER_IDENT)) { - rsize = dfp_discover_ident(payload); - enable_transmit_sop_prime(port); + /* Passive cable Nacked for Discover SVID */ + if (cmd == CMD_DISCOVER_SVID && is_tbt_compat_enabled(port) && + is_transmit_msg_sop_prime(port) && + get_usb_pd_mux_cable_type(port) == IDH_PTYPE_PCABLE) { + limit_tbt_cable_speed(port); + rsize = dfp_discover_modes(port, payload); + disable_transmit_sop_prime(port); + } else { + rsize = 0; } #endif /* CONFIG_USB_PD_ALT_MODE_DFP */ } else { |