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| author | Ruibin Chang <ruibin.chang@ite.com.tw> | 2020-01-20 18:03:54 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-01-22 07:42:00 +0000 |
| commit | 491ee94be1f74876a37f396fffb4457692b5fdab (patch) | |
| tree | c36bfbdc19c914c8b029eef1f0520a73121af8a0 | |
| parent | adf6054e8eef567a6beb1d6894133446966c9e0a (diff) | |
| download | chrome-ec-491ee94be1f74876a37f396fffb4457692b5fdab.tar.gz | |
it83xx/adc: adc control pin order changes for it83202Bx
Add configuration for changing adc control pin order
on chip it83202Bx.
BUG=none
BRANCH=none
TEST=ADC16 of PD port2 can read correct Vbus value.
Change-Id: I9a7f81bf3cb1ac74a5f07ce817d03f5ab0569d17
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2009539
Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
| -rw-r--r-- | chip/it83xx/adc.c | 11 | ||||
| -rw-r--r-- | chip/it83xx/config_chip_it8xxx2.h | 8 |
2 files changed, 19 insertions, 0 deletions
diff --git a/chip/it83xx/adc.c b/chip/it83xx/adc.c index 287a3bd5ba..b6d5a7dbc1 100644 --- a/chip/it83xx/adc.c +++ b/chip/it83xx/adc.c @@ -40,6 +40,16 @@ const struct adc_ctrl_t adc_ctrl_regs[] = { &IT83XX_GPIO_GPCRI6}, {&IT83XX_ADC_VCH7CTL, &IT83XX_ADC_VCH7DATM, &IT83XX_ADC_VCH7DATL, &IT83XX_GPIO_GPCRI7}, +#ifdef IT83XX_CHIP_ADC_PIN_ORDER_CHANGE + {&IT83XX_ADC_VCH13CTL, &IT83XX_ADC_VCH13DATM, &IT83XX_ADC_VCH13DATL, + &IT83XX_GPIO_GPCRL1}, + {&IT83XX_ADC_VCH14CTL, &IT83XX_ADC_VCH14DATM, &IT83XX_ADC_VCH14DATL, + &IT83XX_GPIO_GPCRL2}, + {&IT83XX_ADC_VCH15CTL, &IT83XX_ADC_VCH15DATM, &IT83XX_ADC_VCH15DATL, + &IT83XX_GPIO_GPCRL3}, + {&IT83XX_ADC_VCH16CTL, &IT83XX_ADC_VCH16DATM, &IT83XX_ADC_VCH16DATL, + &IT83XX_GPIO_GPCRL0}, +#else {&IT83XX_ADC_VCH13CTL, &IT83XX_ADC_VCH13DATM, &IT83XX_ADC_VCH13DATL, &IT83XX_GPIO_GPCRL0}, {&IT83XX_ADC_VCH14CTL, &IT83XX_ADC_VCH14DATM, &IT83XX_ADC_VCH14DATL, @@ -48,6 +58,7 @@ const struct adc_ctrl_t adc_ctrl_regs[] = { &IT83XX_GPIO_GPCRL2}, {&IT83XX_ADC_VCH16CTL, &IT83XX_ADC_VCH16DATM, &IT83XX_ADC_VCH16DATL, &IT83XX_GPIO_GPCRL3}, +#endif }; BUILD_ASSERT(ARRAY_SIZE(adc_ctrl_regs) == CHIP_ADC_COUNT); diff --git a/chip/it83xx/config_chip_it8xxx2.h b/chip/it83xx/config_chip_it8xxx2.h index 22c62f4c01..01e4b6eda2 100644 --- a/chip/it83xx/config_chip_it8xxx2.h +++ b/chip/it83xx/config_chip_it8xxx2.h @@ -33,6 +33,14 @@ #if defined(CHIP_VARIANT_IT83202BX) /* TODO(b/133460224): enable properly chip config option. */ #define CONFIG_FLASH_SIZE 0x00080000 +/* + * ADC control pin order change: + * ADC13 control pin GPL0 GPL1 + * ADC14 control pin GPL1 change to GPL2 + * ADC15 control pin GPL2 ---------> GPL3 + * ADC16 control pin GPL3 GPL0 + */ +#define IT83XX_CHIP_ADC_PIN_ORDER_CHANGE /* Embedded flash is KGD */ #define IT83XX_CHIP_FLASH_IS_KGD /* Don't let internal flash go into deep power down mode. */ |