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authorNamyoon Woo <namyoon@chromium.org>2020-02-07 15:30:14 -0800
committerCommit Bot <commit-bot@chromium.org>2020-02-13 23:06:10 +0000
commit4b22d02961ad266d588d31c2324a19f8ef650558 (patch)
tree6340c2e593cc0009eec6ac8d231e4cb2f15fbc7c
parent085ab4d4603f7c1fd402adae6a8f10e8b569df81 (diff)
downloadchrome-ec-4b22d02961ad266d588d31c2324a19f8ef650558.tar.gz
use gpio_set_wakepin() to enable or disable wake pins
This uses gpio_set_wakepin() to setup the wake pins instead of writing to the PINMUX EXITEN registers directly. This patch reduces the flash usage by 248 bytes. BUG=b:35587259 BRANCH=cr50 TEST=checked pinmux configuration hasn't changed on coral. Checked firmware_Cr50DeviceState running good on coral. Change-Id: Ic4ef1751e34b85ea2719f257ebd9b7ad52355eec Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2047923 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
-rw-r--r--board/cr50/board.c91
-rw-r--r--chip/g/sps.c6
2 files changed, 31 insertions, 66 deletions
diff --git a/board/cr50/board.c b/board/cr50/board.c
index c837e11630..e1ecfff772 100644
--- a/board/cr50/board.c
+++ b/board/cr50/board.c
@@ -569,9 +569,10 @@ void board_configure_deep_sleep_wakepins(void)
* not being used and reenable them in their init functions on
* resume.
*/
- GWRITE_FIELD(PINMUX, EXITEN0, DIOA12, 0); /* SPS_CS_L */
- GWRITE_FIELD(PINMUX, EXITEN0, DIOA1, 0); /* I2CS_SDA */
- GWRITE_FIELD(PINMUX, EXITEN0, DIOA9, 0); /* I2CS_SCL */
+ gpio_set_wakepin(GPIO_STRAP_B1, 0); /* SPS_CS_L */
+ gpio_set_wakepin(GPIO_STRAP_A0, 0); /* I2CS_SDA */
+ gpio_set_wakepin(GPIO_STRAP_A1, 0); /* I2CS_SCL */
+
/* Remove the pulldown on EC uart tx and disable the input */
GWRITE_FIELD(PINMUX, DIOB5_CTL, PD, 0);
@@ -587,34 +588,16 @@ void board_configure_deep_sleep_wakepins(void)
* resuming from deep sleep the TPM will be reset. Cr50 doesn't need to
* read the low value and then reset.
*/
- if (board_use_plt_rst()) {
- /* Configure plt_rst_l to wake on high */
- /* Disable plt_rst_l as a wake pin */
- GWRITE_FIELD(PINMUX, EXITEN0, DIOM3, 0);
- /* Reconfigure the pin */
- GWRITE_FIELD(PINMUX, EXITEDGE0, DIOM3, 0); /* level sensitive */
- GWRITE_FIELD(PINMUX, EXITINV0, DIOM3, 0); /* wake on high */
- /* enable powerdown exit */
- GWRITE_FIELD(PINMUX, EXITEN0, DIOM3, 1);
- } else {
- /* Configure plt_rst_l to wake on high */
- /* Disable sys_rst_l as a wake pin */
- GWRITE_FIELD(PINMUX, EXITEN0, DIOM0, 0);
- /* Reconfigure the pin */
- GWRITE_FIELD(PINMUX, EXITEDGE0, DIOM0, 0); /* level sensitive */
- GWRITE_FIELD(PINMUX, EXITINV0, DIOM0, 0); /* wake on high */
- /* enable powerdown exit */
- GWRITE_FIELD(PINMUX, EXITEN0, DIOM0, 1);
- }
- if (board_has_ec_cr50_comm_support()) {
- /* disable powerdown exit */
- GWRITE_FIELD(PINMUX, EXITEN0, DIOB3, 0);
- GWRITE_FIELD(PINMUX, EXITEDGE0, DIOB3, 0); /* level sensitive */
- GWRITE_FIELD(PINMUX, EXITINV0, DIOB3, 0); /* wake on high */
- /* enable powerdown exit */
- GWRITE_FIELD(PINMUX, EXITEN0, DIOB3, 1);
- }
+ /*
+ * Configure plt_rst_l (DIOM3) or sys_rst_(DIOM0) to wake on high.
+ * Note: the pinmux with GPIO_TPM_RST_L is configured in
+ * configure_board_specific_gpios().
+ */
+ gpio_set_wakepin(GPIO_TPM_RST_L, GPIO_HIB_WAKE_HIGH);
+
+ if (board_has_ec_cr50_comm_support())
+ gpio_set_wakepin(GPIO_EC_PACKET_MODE_EN, GPIO_HIB_WAKE_HIGH);
}
static void deferred_tpm_rst_isr(void);
@@ -646,22 +629,6 @@ static void configure_board_specific_gpios(void)
/* Enable the input */
GWRITE_FIELD(PINMUX, DIOM3_CTL, IE, 1);
-
- /*
- * Make plt_rst_l routed to DIOM3 a low level sensitive wake
- * source. This way when a plt_rst_l pulse comes along while
- * H1 is in sleep, the H1 wakes from sleep first, enabling all
- * necessary clocks, and becomes ready to generate an
- * interrupt on the rising edge of plt_rst_l.
- *
- * It takes at most 150 us to wake up, and the pulse is at
- * least 1ms long.
- */
- GWRITE_FIELD(PINMUX, EXITEDGE0, DIOM3, 0);
- GWRITE_FIELD(PINMUX, EXITINV0, DIOM3, 1);
-
- /* Enable powerdown exit on DIOM3 */
- GWRITE_FIELD(PINMUX, EXITEN0, DIOM3, 1);
} else {
/* Use sys_rst_l as the tpm reset signal. */
/* Select for TPM_RST_L */
@@ -670,14 +637,19 @@ static void configure_board_specific_gpios(void)
GWRITE(PINMUX, GPIO1_GPIO4_SEL, GC_PINMUX_DIOM0_SEL);
/* Enable the input */
GWRITE_FIELD(PINMUX, DIOM0_CTL, IE, 1);
-
- /* Set to be level sensitive */
- GWRITE_FIELD(PINMUX, EXITEDGE0, DIOM0, 0);
- /* wake on low */
- GWRITE_FIELD(PINMUX, EXITINV0, DIOM0, 1);
- /* Enable powerdown exit on DIOM0 */
- GWRITE_FIELD(PINMUX, EXITEN0, DIOM0, 1);
}
+ /*
+ * Now that TPM_RST_L has been connected to the right signal, enable it
+ * as wake_low. This way when a tpm_rst_l pulse comes along while H1 is
+ * in sleep, the H1 wakes from sleep first, enabling all necessary
+ * clocks, and becomes ready to generate an interrupt on the rising edge
+ * of tpm_rst_l.
+ *
+ * It takes at most 150 us to wake up, and the pulse is at
+ * least 1ms long.
+ */
+ gpio_set_wakepin(GPIO_TPM_RST_L, GPIO_HIB_WAKE_LOW);
+
/* Connect the correct pin to the lid open/recovery switch gpio. */
switch (board_get_ccd_rec_lid_pin()) {
case BOARD_CCD_REC_LID_PIN_DIOA1:
@@ -1535,15 +1507,10 @@ void i2cs_set_pinmux(void)
*/
GWRITE(PINMUX, GPIO0_GPIO14_SEL, GC_PINMUX_DIOA1_SEL);
- /* Allow I2CS_SCL to wake from sleep */
- GWRITE_FIELD(PINMUX, EXITEDGE0, DIOA9, 1); /* edge sensitive */
- GWRITE_FIELD(PINMUX, EXITINV0, DIOA9, 1); /* wake on low */
- GWRITE_FIELD(PINMUX, EXITEN0, DIOA9, 1); /* enable powerdown exit */
-
- /* Allow I2CS_SDA to wake from sleep */
- GWRITE_FIELD(PINMUX, EXITEDGE0, DIOA1, 1); /* edge sensitive */
- GWRITE_FIELD(PINMUX, EXITINV0, DIOA1, 1); /* wake on low */
- GWRITE_FIELD(PINMUX, EXITEN0, DIOA1, 1); /* enable powerdown exit */
+ /* Configure the I2CS_SDA signal, DIOA1, as wake falling */
+ gpio_set_wakepin(GPIO_STRAP_A0, GPIO_HIB_WAKE_FALLING);
+ /* Configure the I2CS_SCL signal, DIOA9, as wake falling */
+ gpio_set_wakepin(GPIO_STRAP_A1, GPIO_HIB_WAKE_FALLING);
}
static int command_sysinfo(int argc, char **argv)
diff --git a/chip/g/sps.c b/chip/g/sps.c
index 7f8b81de9b..b64e1d1a7b 100644
--- a/chip/g/sps.c
+++ b/chip/g/sps.c
@@ -255,10 +255,8 @@ static void sps_init(void)
GWRITE_FIELD(PINMUX, DIOA10_CTL, IE, 0); /* SPS_MISO */
GWRITE_FIELD(PINMUX, DIOA12_CTL, IE, 1); /* SPS_CS_L */
- /* Allow SPS_CS_L to wake from sleep */
- GWRITE_FIELD(PINMUX, EXITEN0, DIOA12, 1); /* enable powerdown exit */
- GWRITE_FIELD(PINMUX, EXITEDGE0, DIOA12, 1); /* edge sensitive */
- GWRITE_FIELD(PINMUX, EXITINV0, DIOA12, 1); /* wake on low */
+ /* Configure the SPS_CS_L signal, DIOA12, as wake falling */
+ gpio_set_wakepin(GPIO_STRAP_B1, GPIO_HIB_WAKE_FALLING);
}
DECLARE_HOOK(HOOK_INIT, sps_init, HOOK_PRIO_DEFAULT);