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| author | Raul E Rangel <rrangel@chromium.org> | 2020-02-25 16:27:22 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-02-27 19:42:26 +0000 |
| commit | 0dff5a752b3796c73bf29919d7d13f03204bc0f3 (patch) | |
| tree | 2c0bdd9e3bf757e87684caab84d71bde257bfeb3 | |
| parent | c70d0a3e25db1a687c09a392b5e43b7a95cf94a8 (diff) | |
| download | chrome-ec-0dff5a752b3796c73bf29919d7d13f03204bc0f3.tar.gz | |
chip/npcx/lpc: Set bit 5 when sending AUX responses.
The linux kernel expects bit 5 to be set in the status register when the
output buffer contains and AUX packet.
BUG=b:145575366
BRANCH=none
TEST=Verified bit 5 is set when sending aux packets
Change-Id: I0d3944ea6fd04224d9f9bcf0e1b0b3c8633ad786
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2073281
Reviewed-by: Edward Hill <ecgh@chromium.org>
| -rw-r--r-- | chip/npcx/lpc.c | 5 | ||||
| -rw-r--r-- | include/i8042_protocol.h | 3 |
2 files changed, 8 insertions, 0 deletions
diff --git a/chip/npcx/lpc.c b/chip/npcx/lpc.c index 5162ff158d..672e1154a5 100644 --- a/chip/npcx/lpc.c +++ b/chip/npcx/lpc.c @@ -13,6 +13,7 @@ #include "gpio.h" #include "hooks.h" #include "host_command.h" +#include "i8042_protocol.h" #include "keyboard_protocol.h" #include "lpc.h" #include "lpc_chip.h" @@ -316,6 +317,7 @@ void lpc_keyboard_put_char(uint8_t chr, int send_irq) /* Put a char to host buffer by HIMDO */ void lpc_mouse_put_char(uint8_t chr) { + NPCX_HIKMST |= I8042_AUX_DATA; NPCX_HIMDO = chr; CPRINTS("Mouse put %02x", chr); @@ -532,6 +534,9 @@ void lpc_kbc_obe_interrupt(void) task_disable_irq(NPCX_IRQ_KBC_OBE); CPRINTS("obe isr %02x", NPCX_HIKMST); + + NPCX_HIKMST &= ~I8042_AUX_DATA; + task_wake(TASK_ID_KEYPROTO); } DECLARE_IRQ(NPCX_IRQ_KBC_OBE, lpc_kbc_obe_interrupt, 4); diff --git a/include/i8042_protocol.h b/include/i8042_protocol.h index 0bb668a136..7e554fc03e 100644 --- a/include/i8042_protocol.h +++ b/include/i8042_protocol.h @@ -86,4 +86,7 @@ #define I8042_ENIRQ12 BIT(1) #define I8042_ENIRQ1 BIT(0) +/* Status Flags */ +#define I8042_AUX_DATA BIT(5) + #endif /* __CROS_EC_I8042_PROTOCOL_H */ |