remove board/cr50 and chip/g

This patch removes cr50 related files from platform/ec.

BUG=b:149350081
BRANCH=none
TEST=$ make buildall -j

$ cros_workon --host list
chromeos-base/chromeos-cr50-dev
chromeos-base/chromeos-ec
chromeos-base/chromeos-ec-headers
chromeos-base/ec-devutils
chromeos-base/ec-utils
chromeos-base/ec-utils-test
dev-util/hdctools

$ sudo emerge chromeos-cr50-dev -j
$ sudo emerge chromeos-ec -j
$ sudo emerge chromeos-ec-headers -j
$ sudo emerge ec-devutils -j
$ sudo emerge ec-utils -j
$ sudo emerge ec-utils-test -j
$ sudo emerge hdctools -j

$ cros_workon-octopus list
chromeos-base/chromeos-ec
chromeos-base/chromeos-ec-headers
chromeos-base/ec-devutils
chromeos-base/ec-utils
chromeos-base/ec-utils-test
dev-util/hdctools

$ sudo emerge-octopus chromeos-ec -j
$ sudo emerge-octopus chromeos-ec-headers -j
$ sudo emerge-octopus ec-devutils -j
$ sudo emerge-octopus ec-utils -j
$ sudo emerge-octopus ec-utils-test -j
$ sudo emerge-octopus hdctools -j

Signed-off-by: Namyoon Woo <namyoon@chromium.org>
Change-Id: Ifa3a037fff17177204ce1a9b88474490fb9be3ed
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2083659
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Denis Brockus <dbrockus@chromium.org>

196 files changed, 0 insertions, 70631 deletions

diff --git a/board/cr50/OWNERS b/board/cr50/OWNERS
deleted file mode 100644
index b234ea8308..0000000000
--- a/board/cr50/OWNERS
+++ /dev/null
@@ -1,9 +0,0 @@
-# Cr50 board owners
-apronin@chromium.org
-mruthven@chromium.org
-namyoon@chromium.org
-sukhomlinov@chromium.org
-vbendeb@chromium.org
-
-# Don't inherit owners from elsewhere in the manifest
-set noparent
diff --git a/board/cr50/ap_state.c b/board/cr50/ap_state.c
deleted file mode 100644
index 1224818f5b..0000000000
--- a/board/cr50/ap_state.c
+++ /dev/null
@@ -1,205 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * AP state machine
- */
-#include "ec_commands.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "system.h"
-#include "tpm_registers.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-
-static enum device_state state = DEVICE_STATE_INIT;
-
-void print_ap_state(void)
-{
-	ccprintf("AP:      %s\n", device_state_name(state));
-}
-
-int ap_is_on(void)
-{
-	return state == DEVICE_STATE_ON;
-}
-
-/**
- * Set the AP state.
- *
- * Done as a function to make it easier to debug state transitions.  Note that
- * this ONLY sets the state (and possibly prints debug info), and doesn't do
- * all the additional transition work that set_ap_on(), etc. do.
- *
- * @param new_state	State to set.
- */
-static void set_state(enum device_state new_state)
-{
-#ifdef CR50_DEBUG_AP_STATE
-	/* Print all state transitions.  May spam the console. */
-	if (state != new_state)
-		CPRINTS("AP %s -> %s",
-			device_state_name(state), device_state_name(new_state));
-#endif
-	state = new_state;
-}
-
-/**
- * Set AP to the off state. Disable functionality that should only be available
- * when the AP is on.
- */
-static void deferred_set_ap_off(void)
-{
-	CPRINTS("AP off");
-	set_state(DEVICE_STATE_OFF);
-
-	/*
-	 * If TPM is configured then the INT_AP_L signal is used as a low pulse
-	 * trigger to sync transactions with the host. By default Cr50 is
-	 * driving this line high, but when the AP powers off, the 1.8V rail
-	 * that it's pulled up to will be off and cause excessive power to be
-	 * consumed by the Cr50. Set INT_AP_L as an input while the AP is
-	 * powered off.
-	 */
-	gpio_set_flags(GPIO_INT_AP_L, GPIO_INPUT);
-
-	ccd_update_state();
-
-	/*
-	 * We don't enable deep sleep on ARM devices yet, as its processing
-	 * there will require more support on the AP side than is available
-	 * now.
-	 *
-	 * Note: Presence of platform reset is a poor indicator of deep sleep
-	 * support.  It happens to be correlated with ARM vs x86 at present.
-	 */
-	if (board_deep_sleep_allowed())
-		enable_deep_sleep();
-}
-DECLARE_DEFERRED(deferred_set_ap_off);
-
-/**
- * Move the AP to the ON state
- */
-void set_ap_on(void)
-{
-	hook_call_deferred(&deferred_set_ap_off_data, -1);
-	CPRINTS("AP on");
-	set_state(DEVICE_STATE_ON);
-
-	/*
-	 * AP is powering up, set the host sync signal to output and set it
-	 * high which is the default level.
-	 */
-	gpio_set_flags(GPIO_INT_AP_L, GPIO_OUT_HIGH);
-	gpio_set_level(GPIO_INT_AP_L, 1);
-
-	ccd_update_state();
-
-	if (board_deep_sleep_allowed())
-		disable_deep_sleep();
-}
-
-static uint8_t waiting_for_ap_reset;
-/*
- * If TPM_RST_L is asserted, the AP is in reset. Disable all AP functionality
- * in 1 second if it remains asserted.
- */
-void tpm_rst_asserted(enum gpio_signal unused)
-{
-	CPRINTS("%s", __func__);
-
-	/*
-	 * It's possible the signal is being pulsed. Wait 1 second to disable
-	 * functionality, so it's more likely the AP is fully off and not being
-	 * reset.
-	 */
-	hook_call_deferred(&deferred_set_ap_off_data, SECOND);
-
-	set_state(DEVICE_STATE_DEBOUNCING);
-
-	if (waiting_for_ap_reset) {
-		CPRINTS("CL: done");
-		waiting_for_ap_reset = 0;
-		deassert_ec_rst();
-		enable_sleep(SLEEP_MASK_AP_RUN);
-	}
-}
-
-void board_closed_loop_reset(void)
-{
-	CPRINTS("CL: start");
-	/* Disable sleep while waiting for the reset */
-	disable_sleep(SLEEP_MASK_AP_RUN);
-
-	/* Until the AP resets, we can't trust it's state */
-	set_state(DEVICE_STATE_UNKNOWN);
-
-	waiting_for_ap_reset = 1;
-
-	/* Disable AP communications with the TPM until cr50 sees the reset */
-	tpm_stop();
-
-	/* Use EC_RST_L to reset the system */
-	assert_ec_rst();
-
-	/*
-	 * DETECT_TPM_RST_L_ASSERTED is edge triggered. If TPM_RST_L is already
-	 * low, tpm_rst_asserted wont get called. Alert tpm_rst_asserted
-	 * manually if the signal is already low.
-	 */
-	if (!gpio_get_level(GPIO_DETECT_TPM_RST_L_ASSERTED))
-		tpm_rst_asserted(GPIO_TPM_RST_L);
-}
-
-/**
- * Check the initial AP state.
- */
-static void init_ap_detect(void)
-{
-	/* Enable interrupts for AP state detection */
-	gpio_enable_interrupt(GPIO_TPM_RST_L);
-	gpio_enable_interrupt(GPIO_DETECT_TPM_RST_L_ASSERTED);
-	/*
-	 * After resuming from any reset other than deep sleep, cr50 needs to
-	 * make sure the rest of the system has reset. If cr50 needs a closed
-	 * loop reset to reset the system, it can't rely on the short EC_RST
-	 * pulse from RO. Use the closed loop reset to ensure the system has
-	 * actually been reset.
-	 *
-	 * During this reset, the ap state will not be set to 'on' until the AP
-	 * enters and then leaves reset. The tpm waits until the ap is on before
-	 * allowing any tpm activity, so it wont do anything until the reset is
-	 * complete.
-	 */
-	if (board_uses_closed_loop_reset() &&
-	    !(system_get_reset_flags() & EC_RESET_FLAG_HIBERNATE)) {
-		board_closed_loop_reset();
-	} else {
-		/*
-		 * If the TPM_RST_L signal is already high when cr50 wakes up or
-		 * transitions to high before we are able to configure the gpio
-		 * then we will have missed the edge and the tpm reset isr will
-		 * not get called. Check that we haven't already missed the
-		 * rising edge. If we have alert tpm_rst_isr.
-		 *
-		 * DONT alert tpm_rst_isr if the board is waiting for the closed
-		 * loop reset to finish. The isr is edge triggered, so
-		 * tpm_rst_deasserted wont be called until the AP enters and
-		 * exits reset. That is what we want. The TPM and other
-		 * peripherals check ap_is_on before enabling interactions with
-		 * the AP, and we want these to be disabled until the closed
-		 * loop reset is complete.
-		 */
-		if (gpio_get_level(GPIO_TPM_RST_L))
-			tpm_rst_deasserted(GPIO_TPM_RST_L);
-		else
-			tpm_rst_asserted(GPIO_TPM_RST_L);
-	}
-}
-/*
- * TPM_RST_L isn't setup until board_init. Make sure init_ap_detect happens
- * after that.
- */
-DECLARE_HOOK(HOOK_INIT, init_ap_detect, HOOK_PRIO_DEFAULT + 1);
diff --git a/board/cr50/ap_uart_state.c b/board/cr50/ap_uart_state.c
deleted file mode 100644
index 191ecee95b..0000000000
--- a/board/cr50/ap_uart_state.c
+++ /dev/null
@@ -1,133 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * AP UART state machine
- */
-#include "ccd_config.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "uart_bitbang.h"
-#include "uartn.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-
-static enum device_state state = DEVICE_STATE_INIT;
-
-void print_ap_uart_state(void)
-{
-	ccprintf("AP UART: %s\n", device_state_name(state));
-}
-
-int ap_uart_is_on(void)
-{
-	/* Debouncing and on are both still on */
-	return (state == DEVICE_STATE_DEBOUNCING || state == DEVICE_STATE_ON);
-}
-
-/**
- * Set the AP UART state.
- *
- * Done as a function to make it easier to debug state transitions.  Note that
- * this ONLY sets the state (and possibly prints debug info), and doesn't do
- * all the additional transition work that set_ap_uart_on(), etc. do.
- *
- * @param new_state	State to set.
- */
-static void set_state(enum device_state new_state)
-{
-#ifdef CR50_DEBUG_AP_UART_STATE
-	/* Print all state transitions.  May spam the console. */
-	if (state != new_state)
-		CPRINTS("AP UART %s -> %s",
-			device_state_name(state), device_state_name(new_state));
-#endif
-	state = new_state;
-}
-
-/* Move the AP UART to the OFF state. */
-static void set_ap_uart_off(void)
-{
-	CPRINTS("AP UART off");
-	set_state(DEVICE_STATE_OFF);
-
-	ccd_update_state();
-}
-
-/**
- * Move the AP UART to the ON state.
- *
- * This can be deferred from the interrupt handler, or called from the state
- * machine which also runs in HOOK task, so it needs to check the current state
- * to determine whether we're already on.
- */
-static void set_ap_uart_on_deferred(void)
-{
-	/* If we were debouncing ON->OFF, cancel it because we're still on */
-	if (state == DEVICE_STATE_DEBOUNCING)
-		set_state(DEVICE_STATE_ON);
-
-	/* If we're already on, done */
-	if (state == DEVICE_STATE_ON)
-		return;
-
-	/* We were previously off */
-	CPRINTS("AP UART on");
-	set_state(DEVICE_STATE_ON);
-
-	ccd_update_state();
-}
-DECLARE_DEFERRED(set_ap_uart_on_deferred);
-
-/**
- * Interrupt handler for AP detect asserted
- */
-void ap_detect_asserted(enum gpio_signal signal)
-{
-	gpio_disable_interrupt(GPIO_DETECT_AP_UART);
-	hook_call_deferred(&set_ap_uart_on_deferred_data, 0);
-}
-
-/**
- * Detect state machine
- */
-static void ap_uart_detect(void)
-{
-	/* Disable interrupts if we had them on for debouncing */
-	gpio_disable_interrupt(GPIO_DETECT_AP_UART);
-
-	/* If the AP UART signal is high, make sure it's on */
-	if (gpio_get_level(GPIO_DETECT_AP_UART)) {
-		hook_call_deferred(&set_ap_uart_on_deferred_data, 0);
-		return;
-	}
-
-	/*
-	 * Make sure the interrupt is enabled. We will need to detect the on
-	 * transition if we enter the off or debouncing state
-	 */
-	gpio_enable_interrupt(GPIO_DETECT_AP_UART);
-
-	/* AP UART wasn't detected.  If we're already off, done. */
-	if (state == DEVICE_STATE_OFF)
-		return;
-
-	/* If we were debouncing, we're now sure we're off */
-	if (state == DEVICE_STATE_DEBOUNCING ||
-	    state == DEVICE_STATE_INIT_DEBOUNCING) {
-		set_ap_uart_off();
-		return;
-	}
-
-	/*
-	 * Otherwise, we were on or initializing, and we're not sure if the AP
-	 * UART is actually off or just sending a 0-bit.  So start debouncing.
-	 */
-	if (state == DEVICE_STATE_INIT)
-		set_state(DEVICE_STATE_INIT_DEBOUNCING);
-	else
-		set_state(DEVICE_STATE_DEBOUNCING);
-}
-DECLARE_HOOK(HOOK_SECOND, ap_uart_detect, HOOK_PRIO_DEFAULT);
diff --git a/board/cr50/board.c b/board/cr50/board.c
deleted file mode 100644
index 41163edf2a..0000000000
--- a/board/cr50/board.c
+++ /dev/null
@@ -1,1720 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#include "board_id.h"
-#include "ccd_config.h"
-#include "clock.h"
-#include "closed_source_set1.h"
-#include "common.h"
-#include "console.h"
-#include "dcrypto/dcrypto.h"
-#include "ec_version.h"
-#include "endian.h"
-#include "extension.h"
-#include "flash.h"
-#include "flash_config.h"
-#include "gpio.h"
-#include "ite_sync.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "i2cs.h"
-#include "init_chip.h"
-#include "nvmem.h"
-#include "nvmem_vars.h"
-#include "rbox.h"
-#include "rdd.h"
-#include "recovery_button.h"
-#include "registers.h"
-#include "scratch_reg1.h"
-#include "signed_header.h"
-#include "spi.h"
-#include "system.h"
-#include "system_chip.h"
-#include "task.h"
-#include "tpm_registers.h"
-#include "trng.h"
-#include "uart_bitbang.h"
-#include "uartn.h"
-#include "usart.h"
-#include "usb_descriptor.h"
-#include "usb_hid.h"
-#include "usb_i2c.h"
-#include "usb_spi.h"
-#include "util.h"
-#include "wp.h"
-
-/* Define interrupt and gpio structs */
-#include "gpio_list.h"
-
-#include "cryptoc/sha.h"
-
-/*
- * Need to include Implementation.h here to make sure that NVRAM size
- * definitions match across different git repos.
- *
- * MAX() definition from include/utils.h does not work in Implementation.h, as
- * it is used in a preprocessor expression there;
- *
- * SHA_DIGEST_SIZE is defined to be the same in both git repos, but using
- * different expressions.
- *
- * To untangle compiler errors let's just undefine MAX() and SHA_DIGEST_SIZE
- * here, as nether is necessary in this case: all we want from
- * Implementation.h at this point is the definition for NV_MEMORY_SIZE.
- */
-#undef MAX
-#undef SHA_DIGEST_SIZE
-#include "Implementation.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-
-#define NVMEM_TPM_SIZE ((sizeof((struct nvmem_partition *)0)->buffer) \
-			- NVMEM_CR50_SIZE)
-
-/*
- * Make sure NV memory size definition in Implementation.h matches reality. It
- * should be set to
- *
- * NVMEM_PARTITION_SIZE - NVMEM_CR50_SIZE - 8
- *
- * Both of these macros are defined in board.h.
- */
-BUILD_ASSERT(NVMEM_TPM_SIZE == NV_MEMORY_SIZE);
-
-/* NvMem user buffer lengths table */
-uint32_t nvmem_user_sizes[NVMEM_NUM_USERS] = {
-	NVMEM_TPM_SIZE,
-	NVMEM_CR50_SIZE
-};
-
-/*  Board specific configuration settings */
-static uint32_t board_properties; /* Mainly used as a cache for strap config. */
-static uint8_t reboot_request_posted;
-static uint8_t in_prod_mode;
-
-/* Which UARTs we'd like to be able to bitbang. */
-struct uart_bitbang_properties bitbang_config = {
-	.uart = UART_EC,
-	.tx_gpio = GPIO_DETECT_SERVO, /* This is TX to EC console. */
-	.rx_gpio = GPIO_EC_TX_CR50_RX,
-	.rx_irq = GC_IRQNUM_GPIO1_GPIO11INT, /* Must match gpoi.inc */
-	/*
-	 * The rx/tx_pinmux_regval values MUST agree with the pin config for
-	 * both the TX and RX GPIOs in gpio.inc.  Don't change one without
-	 * changing the other.
-	 */
-	.tx_pinmux_reg = GBASE(PINMUX) + GOFFSET(PINMUX, DIOB5_SEL),
-	.tx_pinmux_regval = GC_PINMUX_GPIO1_GPIO3_SEL,
-	.rx_pinmux_reg = GBASE(PINMUX) + GOFFSET(PINMUX, DIOB6_SEL),
-	.rx_pinmux_regval = GC_PINMUX_GPIO1_GPIO11_SEL,
-};
-
-DECLARE_IRQ(GC_IRQNUM_GPIO1_GPIO11INT, uart_bitbang_irq, 0);
-
-const char *device_state_names[] = {
-	"init",
-	"init_debouncing",
-	"init_rx_only",
-	"disconnected",
-	"off",
-	"undetectable",
-	"connected",
-	"on",
-	"debouncing",
-	"unknown",
-	"ignored"
-};
-BUILD_ASSERT(ARRAY_SIZE(device_state_names) == DEVICE_STATE_COUNT);
-
-const char *device_state_name(enum device_state state)
-{
-	if (state >= 0 && state < DEVICE_STATE_COUNT)
-		return device_state_names[state];
-	else
-		return "?";
-}
-
-int board_use_plt_rst(void)
-{
-	return !!(board_properties & BOARD_USE_PLT_RESET);
-}
-
-/* Allow enabling deep sleep if the board supports it. */
-int board_deep_sleep_allowed(void)
-{
-	return !(board_properties & BOARD_DEEP_SLEEP_DISABLED);
-}
-
-int board_rst_pullup_needed(void)
-{
-	return !!(board_properties & BOARD_NEEDS_SYS_RST_PULL_UP);
-}
-
-int board_tpm_uses_i2c(void)
-{
-	return !!(board_properties & BOARD_SLAVE_CONFIG_I2C);
-}
-
-int board_tpm_uses_spi(void)
-{
-	return !!(board_properties & BOARD_SLAVE_CONFIG_SPI);
-}
-
-int board_uses_closed_source_set1(void)
-{
-	return !!(board_properties & BOARD_CLOSED_SOURCE_SET1);
-}
-
-int board_uses_closed_loop_reset(void)
-{
-	return !!(board_properties & BOARD_CLOSED_LOOP_RESET);
-}
-
-int board_has_ina_support(void)
-{
-	return !(board_properties & BOARD_NO_INA_SUPPORT);
-}
-
-int board_tpm_mode_change_allowed(void)
-{
-	return !!(board_properties & BOARD_ALLOW_CHANGE_TPM_MODE);
-}
-
-/* Get header address of the backup RW copy. */
-const struct SignedHeader *get_other_rw_addr(void)
-{
-	if (system_get_image_copy() == EC_IMAGE_RW)
-		return (const struct SignedHeader *)
-			get_program_memory_addr(EC_IMAGE_RW_B);
-
-	return (const struct SignedHeader *)
-		get_program_memory_addr(EC_IMAGE_RW);
-}
-
-/* Return true if the other RW is not ready to run. */
-static int other_rw_is_inactive(void)
-{
-	const struct SignedHeader *header = get_other_rw_addr();
-
-	return !!(header->image_size & TOP_IMAGE_SIZE_BIT);
-}
-
-/* I2C Port definition */
-const struct i2c_port_t i2c_ports[]  = {
-	{"master", I2C_PORT_MASTER, 100,
-	 GPIO_I2C_SCL_INA, GPIO_I2C_SDA_INA},
-};
-const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
-
-/* Strapping pin info structure */
-#define STRAP_PIN_DELAY_USEC  100
-enum strap_list {
-	a0,
-	a1,
-	b0,
-	b1,
-};
-
-struct strap_desc {
-	/* GPIO enum from gpio.inc for the strap pin */
-	uint8_t gpio_signal;
-	/* Offset into pinmux register section for pad SEL register */
-	uint8_t sel_offset;
-	/* Entry in the pinmux peripheral selector table for pad */
-	uint8_t pad_select;
-	const char *pad_name;
-};
-
-struct board_cfg {
-	/* Value the strap pins should read for a given board */
-	uint8_t strap_cfg;
-	/* Properties required for a given board */
-	uint32_t board_properties;
-};
-
-/*
- * This table contains both the GPIO and pad specific information required to
- * configure each strapping pin to be either a GPIO input or output.
- */
-const struct strap_desc strap_regs[] = {
-	{GPIO_STRAP_A0, GOFFSET(PINMUX, DIOA1_SEL), GC_PINMUX_DIOA1_SEL, "a1"},
-	{GPIO_STRAP_A1, GOFFSET(PINMUX, DIOA9_SEL), GC_PINMUX_DIOA9_SEL, "a9"},
-	{GPIO_STRAP_B0, GOFFSET(PINMUX, DIOA6_SEL), GC_PINMUX_DIOA6_SEL, "a6"},
-	{GPIO_STRAP_B1, GOFFSET(PINMUX, DIOA12_SEL), GC_PINMUX_DIOA12_SEL,
-	 "a12"},
-};
-
-#define BOARD_PROPERTIES_DEFAULT (BOARD_SLAVE_CONFIG_I2C | BOARD_USE_PLT_RESET)
-static struct board_cfg board_cfg_table[] = {
-	/* SPI Variants: DIOA12 = 1M PD, DIOA6 = 1M PD */
-	/* Kevin/Gru: DI0A9 = 5k PD, DIOA1 = 1M PU */
-	{
-		.strap_cfg = 0x02,
-		.board_properties = BOARD_SLAVE_CONFIG_SPI |
-			BOARD_NEEDS_SYS_RST_PULL_UP,
-	},
-	/* Poppy: DI0A9 = 1M PU, DIOA1 = 1M PU */
-	{
-		.strap_cfg = 0x0A,
-		.board_properties = BOARD_SLAVE_CONFIG_SPI |
-			BOARD_USE_PLT_RESET,
-	},
-	/* Mistral: DI0A9 = 1M PU, DIOA1 = 5k PU */
-	{
-		.strap_cfg = 0x0B,
-		.board_properties = BOARD_SLAVE_CONFIG_SPI |
-			BOARD_USE_PLT_RESET | BOARD_NO_INA_SUPPORT |
-			BOARD_CLOSED_LOOP_RESET,
-	},
-	/* Kukui: DI0A9 = 5k PU, DIOA1 = 5k PU */
-	{
-		.strap_cfg = 0x0F,
-		.board_properties = BOARD_SLAVE_CONFIG_SPI |
-			BOARD_USE_PLT_RESET,
-	},
-	/* I2C Variants: DIOA9 = 1M PD, DIOA1 = 1M PD */
-	/* Reef/Eve: DIOA12 = 5k PD, DIOA6 = 1M PU */
-	{
-		.strap_cfg = 0x20,
-		.board_properties = BOARD_SLAVE_CONFIG_I2C |
-			BOARD_USE_PLT_RESET,
-	},
-	/* Rowan: DIOA12 = 5k PD, DIOA6 = 5k PU */
-	{
-		.strap_cfg = 0x30,
-		.board_properties = BOARD_SLAVE_CONFIG_I2C |
-			BOARD_DEEP_SLEEP_DISABLED | BOARD_DETECT_AP_WITH_UART,
-	},
-	/* Sarien/Arcada: DIOA12 = 1M PD, DIOA6 = 5k PU */
-	{
-		.strap_cfg = 0x70,
-		.board_properties = BOARD_SLAVE_CONFIG_I2C |
-			BOARD_USE_PLT_RESET | BOARD_WP_DISABLE_DELAY |
-			BOARD_CLOSED_SOURCE_SET1 | BOARD_NO_INA_SUPPORT |
-			BOARD_ALLOW_CHANGE_TPM_MODE,
-	},
-
-};
-
-void post_reboot_request(void)
-{
-	/* Reboot the device next time TPM reset is requested. */
-	reboot_request_posted = 1;
-}
-
-/*****************************************************************************/
-/*                                                                           */
-
-/*
- * Battery cutoff monitor is needed on the devices where hardware alone does
- * not provide proper battery cutoff functionality.
- *
- * The sequence is as follows: set up an interrupt to react to the charger
- * disconnect event. When the interrupt happens observe status of the buttons
- * connected to PWRB_IN and KEY0_IN.
- *
- * If both are pressed, start the 5 second timeout, while keeping monitoring
- * the charger connection state. If it remains disconnected for the entire
- * duration - generate 5 second pulses on EC_RST_L and BAT_EN outputs.
- *
- * In reality the BAT_EN output pulse will cause the complete power cut off,
- * so strictly speaking the code does not need to do anything once BAT_EN
- * output is deasserted.
- */
-
-/* Time to wait before initiating battery cutoff procedure. */
-#define CUTOFF_TIMEOUT_US (5 * SECOND)
-
-/* A timeout hook to run in the end of the 5 s interval. */
-static void ac_stayed_disconnected(void)
-{
-	uint32_t saved_override_state;
-
-	CPRINTS("%s", __func__);
-
-	/* assert EC_RST_L and deassert BAT_EN */
-	GREG32(RBOX, ASSERT_EC_RST) = 1;
-
-	/*
-	 * BAT_EN needs to use the RBOX override ability, bit 1 is battery
-	 * disable bit.
-	 */
-	saved_override_state = GREG32(RBOX, OVERRIDE_OUTPUT);
-	GWRITE_FIELD(RBOX, OVERRIDE_OUTPUT, VAL, 0); /* Setting it to zero. */
-	GWRITE_FIELD(RBOX, OVERRIDE_OUTPUT, OEN, 1);
-	GWRITE_FIELD(RBOX, OVERRIDE_OUTPUT, EN, 1);
-
-
-	msleep(5000);
-
-	/*
-	 * The system was supposed to be shut down the moment battery
-	 * disconnect was asserted, but if we made it here we might as well
-	 * restore the original state.
-	 */
-	GREG32(RBOX, OVERRIDE_OUTPUT) = saved_override_state;
-	GREG32(RBOX, ASSERT_EC_RST) = 0;
-}
-DECLARE_DEFERRED(ac_stayed_disconnected);
-
-/*
- * Just a shortcut to make use of these AC power interrupt states better
- * readable. RED means rising edge and FED means falling edge.
- */
-enum {
-	ac_pres_red = GC_RBOX_INT_STATE_INTR_AC_PRESENT_RED_MASK,
-	ac_pres_fed = GC_RBOX_INT_STATE_INTR_AC_PRESENT_FED_MASK,
-	buttons_not_pressed = GC_RBOX_CHECK_INPUT_KEY0_IN_MASK |
-		GC_RBOX_CHECK_INPUT_PWRB_IN_MASK
-};
-
-/*
- * ISR reacting to both falling and raising edges of the AC_PRESENT signal.
- * Falling edge indicates AC no longer present (removal of the charger cable)
- * and rising edge indicates AP present (insertion of charger cable).
- */
-static void ac_power_state_changed(void)
-{
-	uint32_t req;
-	/* Get current status and clear it. */
-	req = GREG32(RBOX, INT_STATE) & (ac_pres_red | ac_pres_fed);
-	GREG32(RBOX, INT_STATE) = req;
-
-	CPRINTS("AC: %c%c",
-		req & ac_pres_red ? 'R' : '-',
-		req & ac_pres_fed ? 'F' : '-');
-
-	/* Delay sleep so RDD state machines can stabilize */
-	delay_sleep_by(5 * SECOND);
-
-	/* The remaining code is only used for battery cutoff */
-	if (!system_battery_cutoff_support_required())
-		return;
-
-	/* Raising edge gets priority, stop timeout timer and go. */
-	if (req & ac_pres_red) {
-		hook_call_deferred(&ac_stayed_disconnected_data, -1);
-		return;
-	}
-
-	/*
-	 * If this is not a falling edge, or either of the buttons is not
-	 * pressed - bail out.
-	 */
-	if (!(req & ac_pres_fed) ||
-	    (GREG32(RBOX, CHECK_INPUT) & buttons_not_pressed))
-		return;
-
-	/*
-	 * Charger cable was yanked while the power and key0 buttons were kept
-	 * pressed - user wants a battery cut off.
-	 */
-	hook_call_deferred(&ac_stayed_disconnected_data, CUTOFF_TIMEOUT_US);
-}
-DECLARE_IRQ(GC_IRQNUM_RBOX0_INTR_AC_PRESENT_RED_INT, ac_power_state_changed, 1);
-DECLARE_IRQ(GC_IRQNUM_RBOX0_INTR_AC_PRESENT_FED_INT, ac_power_state_changed, 1);
-
-/* Enable interrupts on plugging in and yanking out of the charger cable. */
-static void init_ac_detect(void)
-{
-	/* It is set in idle.c also. */
-	GWRITE_FIELD(RBOX, WAKEUP, ENABLE, 1);
-
-	GWRITE_FIELD(RBOX, INT_ENABLE, INTR_AC_PRESENT_RED, 1);
-	GWRITE_FIELD(RBOX, INT_ENABLE, INTR_AC_PRESENT_FED, 1);
-
-	task_enable_irq(GC_IRQNUM_RBOX0_INTR_AC_PRESENT_RED_INT);
-	task_enable_irq(GC_IRQNUM_RBOX0_INTR_AC_PRESENT_FED_INT);
-}
-/*                                                                           */
-/*****************************************************************************/
-
-/*
- * There's no way to trigger on both rising and falling edges, so force a
- * compiler error if we try. The workaround is to use the pinmux to connect
- * two GPIOs to the same input and configure each one for a separate edge.
- */
-#define GPIO_INT(name, pin, flags, signal)	\
-	BUILD_ASSERT(((flags) & GPIO_INT_BOTH) != GPIO_INT_BOTH);
-#include "gpio.wrap"
-
-/**
- * Reset wake logic
- *
- * If any wake pins are edge triggered, the pad logic latches the wakeup. Clear
- * and restore EXITEN0 to reset the wakeup logic.
- */
-static void reset_wake_logic(void)
-{
-	uint32_t exiten = GREG32(PINMUX, EXITEN0);
-
-	GREG32(PINMUX, EXITEN0) = 0;
-	GREG32(PINMUX, EXITEN0) = exiten;
-}
-
-static void init_pmu(void)
-{
-	clock_enable_module(MODULE_PMU, 1);
-
-	/* This boot sequence may be a result of previous soft reset,
-	 * in which case the PMU low power sequence register needs to
-	 * be reset. */
-	GREG32(PMU, LOW_POWER_DIS) = 0;
-
-	/* Enable wakeup interrupt */
-	task_enable_irq(GC_IRQNUM_PMU_INTR_WAKEUP_INT);
-	GWRITE_FIELD(PMU, INT_ENABLE, INTR_WAKEUP, 1);
-}
-
-void pmu_wakeup_interrupt(void)
-{
-	int wakeup_src;
-	static uint8_t count;
-	static uint8_t ws;
-	static uint8_t line_length;
-	static const char wheel[] = { '|', '/', '-', '\\' };
-
-	delay_sleep_by(1 * MSEC);
-
-	wakeup_src = GR_PMU_EXITPD_SRC;
-
-	/* Clear interrupt state */
-	GWRITE_FIELD(PMU, INT_STATE, INTR_WAKEUP, 1);
-
-	/* Clear pmu reset */
-	GWRITE(PMU, CLRRST, 1);
-
-	/*
-	 * This will print the next state of the "rotating wheel" every time
-	 * cr50 resumes from regular sleep (8 is the ASCII code for
-	 * 'backspace'). Each time wake source changes, its hex value is
-	 * printed out preceded by a space.
-	 *
-	 * In steady state when there is no other activity Cr50 wakes up every
-	 * half second for HOOK_TICK, so that is the rate the wheel will be
-	 * spinning at when device is idle.
-	 */
-	if (ws == wakeup_src) {
-		ccprintf("%c%c%c%2x%c", 8, 8, 8, ws,
-			 wheel[count++ % sizeof(wheel)]);
-	} else {
-		ws = wakeup_src;
-		line_length += 3;
-		if (line_length > 50) {
-			ccprintf("\n");
-			line_length = 0;
-		}
-		ccprintf(" %2x ", wakeup_src);
-	}
-
-	if (wakeup_src & GC_PMU_EXITPD_SRC_RBOX_WAKEUP_MASK)
-		rbox_clear_wakeup();
-
-	/* Disable rbox wakeup. It will be reenabled before entering sleep. */
-	GREG32(RBOX, WAKEUP) = 0;
-
-	if (wakeup_src & GC_PMU_EXITPD_SRC_PIN_PD_EXIT_MASK) {
-		reset_wake_logic();
-
-		/*
-		 * Delay sleep long enough for a SPI slave transaction to start
-		 * or for the system to be reset.
-		 */
-		delay_sleep_by(5 * SECOND);
-	}
-
-	/* Trigger timer0 interrupt */
-	if (wakeup_src & GC_PMU_EXITPD_SRC_TIMELS0_PD_EXIT_TIMER0_MASK)
-		task_trigger_irq(GC_IRQNUM_TIMELS0_TIMINT0);
-
-	/* Trigger timer1 interrupt */
-	if (wakeup_src & GC_PMU_EXITPD_SRC_TIMELS0_PD_EXIT_TIMER1_MASK)
-		task_trigger_irq(GC_IRQNUM_TIMELS0_TIMINT1);
-}
-DECLARE_IRQ(GC_IRQNUM_PMU_INTR_WAKEUP_INT, pmu_wakeup_interrupt, 1);
-
-void board_configure_deep_sleep_wakepins(void)
-{
-	/*
-	 * Disable the i2c and spi slave wake sources since the TPM is
-	 * not being used and reenable them in their init functions on
-	 * resume.
-	 */
-	GWRITE_FIELD(PINMUX, EXITEN0, DIOA12, 0); /* SPS_CS_L */
-	GWRITE_FIELD(PINMUX, EXITEN0, DIOA1, 0);  /* I2CS_SDA */
-	GWRITE_FIELD(PINMUX, EXITEN0, DIOA9, 0);  /* I2CS_SCL */
-
-	/* Remove the pulldown on EC uart tx and disable the input */
-	GWRITE_FIELD(PINMUX, DIOB5_CTL, PD, 0);
-	GWRITE_FIELD(PINMUX, DIOB5_CTL, IE, 0);
-
-	/*
-	 * Configure the TPM_RST_L signal as wake on high. There is a
-	 * requirement the tpm reset has to remain asserted when cr50 should
-	 * be in deep sleep, so cr50 should not wake up until it goes high.
-	 *
-	 * Whether it is a short pulse or long one waking on the high level is
-	 * fine, because the goal of TPM_RST_L is to reset the TPM and after
-	 * resuming from deep sleep the TPM will be reset. Cr50 doesn't need to
-	 * read the low value and then reset.
-	 */
-	if (board_use_plt_rst()) {
-		/* Configure plt_rst_l to wake on high */
-		/* Disable plt_rst_l as a wake pin */
-		GWRITE_FIELD(PINMUX, EXITEN0, DIOM3, 0);
-		/* Reconfigure the pin */
-		GWRITE_FIELD(PINMUX, EXITEDGE0, DIOM3, 0); /* level sensitive */
-		GWRITE_FIELD(PINMUX, EXITINV0, DIOM3, 0);  /* wake on high */
-		/* enable powerdown exit */
-		GWRITE_FIELD(PINMUX, EXITEN0, DIOM3, 1);
-	} else {
-		/* Configure plt_rst_l to wake on high */
-		/* Disable sys_rst_l as a wake pin */
-		GWRITE_FIELD(PINMUX, EXITEN0, DIOM0, 0);
-		/* Reconfigure the pin */
-		GWRITE_FIELD(PINMUX, EXITEDGE0, DIOM0, 0); /* level sensitive */
-		GWRITE_FIELD(PINMUX, EXITINV0, DIOM0, 0);  /* wake on high */
-		/* enable powerdown exit */
-		GWRITE_FIELD(PINMUX, EXITEN0, DIOM0, 1);
-	}
-}
-
-static void deferred_tpm_rst_isr(void);
-DECLARE_DEFERRED(deferred_tpm_rst_isr);
-
-static void configure_board_specific_gpios(void)
-{
-	/* Add a pullup to sys_rst_l */
-	if (board_rst_pullup_needed())
-		GWRITE_FIELD(PINMUX, DIOM0_CTL, PU, 1);
-
-	/*
-	 * Connect either plt_rst_l or sys_rst_l to GPIO_TPM_RST_L based on the
-	 * board type. This signal is used to monitor AP resets and reset the
-	 * TPM.
-	 *
-	 * Also configure these pins to be wake triggers on the rising edge,
-	 * this will apply to regular sleep only, entering deep sleep would
-	 * reconfigure this.
-	 *
-	 * plt_rst_l is on diom3, and sys_rst_l is on diom0.
-	 */
-	if (board_use_plt_rst()) {
-		/* Use plt_rst_l as the tpm reset signal. */
-		/* Select for TPM_RST_L */
-		GWRITE(PINMUX, GPIO1_GPIO0_SEL, GC_PINMUX_DIOM3_SEL);
-		/* Select for DETECT_TPM_RST_L_ASSERTED */
-		GWRITE(PINMUX, GPIO1_GPIO4_SEL, GC_PINMUX_DIOM3_SEL);
-
-		/* Enable the input */
-		GWRITE_FIELD(PINMUX, DIOM3_CTL, IE, 1);
-
-		/*
-		 * Make plt_rst_l routed to DIOM3 a low level sensitive wake
-		 * source. This way when a plt_rst_l pulse comes along while
-		 * H1 is in sleep, the H1 wakes from sleep first, enabling all
-		 * necessary clocks, and becomes ready to generate an
-		 * interrupt on the rising edge of plt_rst_l.
-		 *
-		 * It takes at most 150 us to wake up, and the pulse is at
-		 * least 1ms long.
-		 */
-		GWRITE_FIELD(PINMUX, EXITEDGE0, DIOM3, 0);
-		GWRITE_FIELD(PINMUX, EXITINV0, DIOM3, 1);
-
-		/* Enable powerdown exit on DIOM3 */
-		GWRITE_FIELD(PINMUX, EXITEN0, DIOM3, 1);
-	} else {
-		/* Use sys_rst_l as the tpm reset signal. */
-		/* Select for TPM_RST_L */
-		GWRITE(PINMUX, GPIO1_GPIO0_SEL, GC_PINMUX_DIOM0_SEL);
-		/* Select for DETECT_TPM_RST_L_ASSERTED */
-		GWRITE(PINMUX, GPIO1_GPIO4_SEL, GC_PINMUX_DIOM0_SEL);
-		/* Enable the input */
-		GWRITE_FIELD(PINMUX, DIOM0_CTL, IE, 1);
-
-		/* Set to be level sensitive */
-		GWRITE_FIELD(PINMUX, EXITEDGE0, DIOM0, 0);
-		/* wake on low */
-		GWRITE_FIELD(PINMUX, EXITINV0, DIOM0, 1);
-		/* Enable powerdown exit on DIOM0 */
-		GWRITE_FIELD(PINMUX, EXITEN0, DIOM0, 1);
-	}
-
-	if (board_uses_closed_source_set1())
-		closed_source_set1_configure_gpios();
-}
-
-static uint8_t mismatched_board_id;
-
-int board_id_is_mismatched(void)
-{
-	return !!mismatched_board_id;
-}
-
-static void  check_board_id_mismatch(void)
-{
-	if (!board_id_mismatch(NULL))
-		return;
-
-	if (system_rollback_detected()) {
-		/*
-		 * We are in a rollback, the other image must be no good.
-		 * Let's keep going with the TPM disabled, only updates will
-		 * be allowed.
-		 */
-		mismatched_board_id = 1;
-		ccprintf("Board ID mismatched, but can not reboot.\n");
-
-		/* Force CCD disabled */
-		ccd_disable();
-
-		return;
-	}
-
-	system_ensure_rollback();
-	ccprintf("Rebooting due to board ID mismatch\n");
-	cflush();
-	system_reset(0);
-}
-
-/*
- * Check if ITE SYNC sequence generation was requested before the reset, if so
- * - clear the request and call the function to generate the sequence.
- */
-static void maybe_trigger_ite_sync(void)
-{
-	uint32_t lls1;
-
-	lls1 = GREG32(PMU, LONG_LIFE_SCRATCH1);
-
-	if (!(lls1 & BOARD_ITE_EC_SYNC_NEEDED))
-		return;
-
-	/* Clear the sync required bit, this should work only once. */
-	GWRITE_FIELD(PMU, LONG_LIFE_SCRATCH_WR_EN, REG1, 1);
-	GREG32(PMU, LONG_LIFE_SCRATCH1) = lls1 & ~BOARD_ITE_EC_SYNC_NEEDED;
-	GWRITE_FIELD(PMU, LONG_LIFE_SCRATCH_WR_EN, REG1, 0);
-
-	generate_ite_sync();
-}
-
-/* Initialize board. */
-static void board_init(void)
-{
-#ifdef CR50_DEV
-	static enum ccd_state ccd_init_state = CCD_STATE_OPENED;
-#else
-	static enum ccd_state ccd_init_state = CCD_STATE_LOCKED;
-#endif
-
-	/*
-	 * Deep sleep resets should be considered valid and should not impact
-	 * the rolling reboot count.
-	 */
-	if (system_get_reset_flags() & EC_RESET_FLAG_HIBERNATE)
-		system_decrement_retry_counter();
-	configure_board_specific_gpios();
-	init_pmu();
-	reset_wake_logic();
-	init_trng();
-	maybe_trigger_ite_sync();
-	init_jittery_clock(1);
-
-	/*
-	 * Need to cache this, because key manager registers are not available
-	 * after run level is lowered.
-	 */
-	in_prod_mode = (GREG32(KEYMGR, HKEY_FWR7) == 0) &&
-		(GREG32(KEYMGR, HKEY_RWR7) == 0xaa66150f);
-
-	init_runlevel(PERMISSION_MEDIUM);
-	/* Initialize NvMem partitions */
-	nvmem_init();
-
-	/*
-	 * If this was a low power wake and not a rollback, restore the ccd
-	 * state from the long-life register.
-	 */
-	if ((system_get_reset_flags() & EC_RESET_FLAG_HIBERNATE) &&
-	    !system_rollback_detected()) {
-		ccd_init_state = (GREG32(PMU, LONG_LIFE_SCRATCH1) &
-				  BOARD_CCD_STATE) >> BOARD_CCD_SHIFT;
-	}
-
-	/* Load case-closed debugging config.  Must be after initvars(). */
-	ccd_config_init(ccd_init_state);
-
-	system_update_rollback_mask_with_both_imgs();
-
-	/* Indication that firmware is running, for debug purposes. */
-	GREG32(PMU, PWRDN_SCRATCH16) = 0xCAFECAFE;
-
-	/*
-	 * Call the function twice to make it harder to glitch execution into
-	 * passing the check when not supposed to.
-	 */
-	check_board_id_mismatch();
-	check_board_id_mismatch();
-
-	/*
-	 * Start monitoring AC detect to wake Cr50 from deep sleep.  This is
-	 * needed to detect RDD cable changes in deep sleep.  AC detect is also
-	 * used for battery cutoff software support on detachable devices.
-	 */
-	init_ac_detect();
-	init_rdd_state();
-
-	/* Initialize write protect.  Must be after CCD config init. */
-	init_wp_state();
-
-	/*
-	 * Need to do this at run time as compile time constant initialization
-	 * to a variable value (even to a const known at compile time) is not
-	 * supported.
-	 */
-	bitbang_config.uart_in = ec_uart.producer.queue;
-
-	/*
-	 * Enable interrupt handler for RBOX key combo so it can be used to
-	 * store the recovery request.
-	 */
-	if (board_uses_closed_source_set1()) {
-		/* Enable interrupt handler for reset button combo */
-		task_enable_irq(GC_IRQNUM_RBOX0_INTR_BUTTON_COMBO0_RDY_INT);
-		GWRITE_FIELD(RBOX, INT_ENABLE, INTR_BUTTON_COMBO0_RDY, 1);
-	}
-
-	/*
-	 * Note that the AP, EC, and servo state machines do not have explicit
-	 * init_xxx_state() functions, because they don't need to configure
-	 * registers prior to starting their state machines.  Their state
-	 * machines run in HOOK_SECOND, which first triggers right after
-	 * HOOK_INIT, not at +1.0 seconds.
-	 */
-}
-DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
-
-/**
- * Hook for CCD config loaded/changed.
- */
-static void board_ccd_config_changed(void)
-{
-	/* Store the current CCD state so we can restore it after deep sleep */
-	GWRITE_FIELD(PMU, LONG_LIFE_SCRATCH_WR_EN, REG1, 1);
-	GREG32(PMU, LONG_LIFE_SCRATCH1) &= ~BOARD_CCD_STATE;
-	GREG32(PMU, LONG_LIFE_SCRATCH1) |= (ccd_get_state() << BOARD_CCD_SHIFT)
-			& BOARD_CCD_STATE;
-	GWRITE_FIELD(PMU, LONG_LIFE_SCRATCH_WR_EN, REG1, 0);
-
-	if (board_uses_closed_source_set1())
-		closed_source_set1_update_factory_mode();
-
-	/* Update CCD state */
-	ccd_update_state();
-}
-DECLARE_HOOK(HOOK_CCD_CHANGE, board_ccd_config_changed, HOOK_PRIO_DEFAULT);
-
-#if defined(CONFIG_USB)
-const void * const usb_strings[] = {
-	[USB_STR_DESC] = usb_string_desc,
-	[USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."),
-	[USB_STR_PRODUCT] = USB_STRING_DESC("Cr50"),
-	[USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32),
-	[USB_STR_CONSOLE_NAME] = USB_STRING_DESC("Shell"),
-	[USB_STR_BLOB_NAME] = USB_STRING_DESC("Blob"),
-	[USB_STR_HID_KEYBOARD_NAME] = USB_STRING_DESC("PokeyPokey"),
-	[USB_STR_AP_NAME] = USB_STRING_DESC("AP"),
-	[USB_STR_EC_NAME] = USB_STRING_DESC("EC"),
-	[USB_STR_UPGRADE_NAME] = USB_STRING_DESC("Firmware upgrade"),
-	[USB_STR_SPI_NAME] = USB_STRING_DESC("AP EC upgrade"),
-	[USB_STR_SERIALNO] = USB_STRING_DESC(DEFAULT_SERIALNO),
-	[USB_STR_I2C_NAME] = USB_STRING_DESC("I2C"),
-};
-BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
-#endif
-
-/* SPI devices */
-const struct spi_device_t spi_devices[] = {
-	[CONFIG_SPI_FLASH_PORT] = {0, 2, GPIO_COUNT}
-};
-const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
-
-int flash_regions_to_enable(struct g_flash_region *regions,
-			    int max_regions)
-{
-	/*
-	 * This needs to account for two regions: the "other" RW partition and
-	 * the NVRAM in TOP_B.
-	 *
-	 * When running from RW_A the two regions are adjacent, but it is
-	 * simpler to keep function logic the same and always configure two
-	 * separate regions.
-	 */
-
-	if (max_regions < 3)
-		return 0;
-
-	/* Enable access to the other RW image... */
-	if (system_get_image_copy() == EC_IMAGE_RW)
-		/* Running RW_A, enable RW_B */
-		regions[0].reg_base = CONFIG_MAPPED_STORAGE_BASE +
-			CONFIG_RW_B_MEM_OFF;
-	else
-		/* Running RW_B, enable RW_A */
-		regions[0].reg_base = CONFIG_MAPPED_STORAGE_BASE +
-			CONFIG_RW_MEM_OFF;
-	/* Size is the same */
-	regions[0].reg_size = CONFIG_RW_SIZE;
-	regions[0].reg_perms = FLASH_REGION_EN_ALL;
-
-	/* Enable access to the NVRAM partition A region */
-	regions[1].reg_base = CONFIG_MAPPED_STORAGE_BASE +
-		CFG_TOP_A_OFF;
-	regions[1].reg_size = CFG_TOP_SIZE;
-	regions[1].reg_perms = FLASH_REGION_EN_ALL;
-
-	/* Enable access to the NVRAM partition B region */
-	regions[2].reg_base = CONFIG_MAPPED_STORAGE_BASE +
-		CFG_TOP_B_OFF;
-	regions[2].reg_size = CFG_TOP_SIZE;
-	regions[2].reg_perms = FLASH_REGION_EN_ALL;
-
-	return 3;
-}
-
-/**
- * Deferred TPM reset interrupt handling
- *
- * This is always called from the HOOK task.
- */
-static void deferred_tpm_rst_isr(void)
-{
-	CPRINTS("%s", __func__);
-
-	/*
-	 * TPM reset is used to detect the AP, connect AP. Let the AP state
-	 * machine know the AP is on.
-	 */
-	set_ap_on();
-
-	/*
-	 * If no reboot request is posted, OR if the other RW's header is not
-	 * ready to run - do not try rebooting the device, just reset the
-	 * TPM.
-	 *
-	 * The inactive header will have to be restored by the appropriate
-	 * vendor command, the device will be rebooted then.
-	 */
-	if (!reboot_request_posted || other_rw_is_inactive()) {
-		/* Reset TPM, no need to wait for completion. */
-		tpm_reset_request(0, 0);
-		return;
-	}
-
-	/*
-	 * Reset TPM and wait to completion to make sure nvmem is
-	 * committed before reboot.
-	 */
-	tpm_reset_request(1, 0);
-
-	/* This will never return. */
-	system_reset(SYSTEM_RESET_MANUALLY_TRIGGERED | SYSTEM_RESET_HARD);
-}
-
-/**
- * Handle TPM_RST_L deasserting
- *
- * This can also be called explicitly from AP detection, if it thinks the
- * interrupt handler missed the rising edge.
- */
-void tpm_rst_deasserted(enum gpio_signal signal)
-{
-	hook_call_deferred(&deferred_tpm_rst_isr_data, 0);
-}
-
-void assert_sys_rst(void)
-{
-	/* Assert it */
-	gpio_set_level(GPIO_SYS_RST_L_OUT, 0);
-}
-
-void deassert_sys_rst(void)
-{
-	/* Deassert it */
-	gpio_set_level(GPIO_SYS_RST_L_OUT, 1);
-}
-
-static int is_sys_rst_asserted(void)
-{
-	/*
-	 * SYS_RST_L is pseudo open drain. It is only an output when it's
-	 * asserted.
-	 */
-	return gpio_get_flags(GPIO_SYS_RST_L_OUT) & GPIO_OUTPUT;
-}
-
-/**
- * Reboot the AP
- */
-void board_reboot_ap(void)
-{
-	if (board_uses_closed_loop_reset()) {
-		board_closed_loop_reset();
-		return;
-	}
-	assert_sys_rst();
-	msleep(20);
-	deassert_sys_rst();
-}
-
-/**
- * Reboot the EC
- */
-void board_reboot_ec(void)
-{
-	if (board_uses_closed_loop_reset()) {
-		board_closed_loop_reset();
-		return;
-	}
-	assert_ec_rst();
-	deassert_ec_rst();
-}
-
-/*
- * This interrupt handler will be called if the RBOX key combo is detected.
- */
-static void key_combo0_irq(void)
-{
-	GWRITE_FIELD(RBOX, INT_STATE, INTR_BUTTON_COMBO0_RDY, 1);
-	recovery_button_record();
-	board_reboot_ec();
-	CPRINTS("Recovery Requested");
-}
-DECLARE_IRQ(GC_IRQNUM_RBOX0_INTR_BUTTON_COMBO0_RDY_INT, key_combo0_irq, 0);
-
-/**
- * Console command to toggle system (AP) reset
- */
-static int command_sys_rst(int argc, char **argv)
-{
-	int val;
-	char *e;
-	int ms = 20;
-
-	if (argc > 1) {
-		if (!ccd_is_cap_enabled(CCD_CAP_REBOOT_EC_AP))
-			return EC_ERROR_ACCESS_DENIED;
-
-		if (!strcasecmp("pulse", argv[1])) {
-			if (argc == 3) {
-				ms = strtoi(argv[2], &e, 0);
-				if (*e)
-					return EC_ERROR_PARAM2;
-			}
-			ccprintf("Pulsing AP reset for %dms\n", ms);
-			assert_sys_rst();
-			msleep(ms);
-			deassert_sys_rst();
-		} else if (parse_bool(argv[1], &val)) {
-			if (val)
-				assert_sys_rst();
-			else
-				deassert_sys_rst();
-		} else
-			return EC_ERROR_PARAM1;
-	}
-
-	ccprintf("SYS_RST_L is %s\n", is_sys_rst_asserted() ?
-		 "asserted" : "deasserted");
-
-	return EC_SUCCESS;
-
-}
-DECLARE_SAFE_CONSOLE_COMMAND(sysrst, command_sys_rst,
-	"[pulse [time] | <BOOLEAN>]",
-	"Assert/deassert SYS_RST_L to reset the AP");
-
-/*
- * Set RBOX register controlling EC reset and wait until RBOX updates the
- * output.
- *
- * Input parameter is treated as a Boolean, 1 means reset needs to be
- * asserted, 0 means reset needs to be deasserted.
- */
-static void wait_ec_rst(int level)
-{
-	int i;
-
-
-	/* Just in case. */
-	level = !!level;
-
-	GWRITE(RBOX, ASSERT_EC_RST, level);
-
-	/*
-	 * If ec_rst value is being explicitly set while power button is held
-	 * pressed after reset, do not let "power button release" ISR change
-	 * the ec_rst value.
-	 */
-	power_button_release_enable_interrupt(0);
-
-	/*
-	 * RBOX is running on its own clock, let's make sure we don't exit
-	 * this function until the ecr_rst output matches the desired setting.
-	 * 1000 cycles is way more than needed for RBOX to react.
-	 *
-	 * Note that the read back value is the inversion of the value written
-	 * into the register once it propagates through RBOX.
-	 */
-	for (i = 0; i < 1000; i++)
-		if (GREAD_FIELD(RBOX, CHECK_OUTPUT, EC_RST) != level)
-			break;
-}
-
-void assert_ec_rst(void)
-{
-	/* Prevent bit bang interrupt storm. */
-	if (uart_bitbang_is_enabled())
-		task_disable_irq(bitbang_config.rx_irq);
-
-	wait_ec_rst(1);
-
-	/*
-	 * On closed source set1, the EC requires a minimum 30 ms pulse to
-	 * properly reset. Ensure EC reset is always asserted for more than
-	 * this time.
-	 */
-	if (board_uses_closed_source_set1())
-		msleep(30);
-}
-
-void deassert_ec_rst(void)
-{
-	wait_ec_rst(0);
-
-	if (uart_bitbang_is_enabled())
-		task_enable_irq(bitbang_config.rx_irq);
-}
-
-int is_ec_rst_asserted(void)
-{
-	return GREAD(RBOX, ASSERT_EC_RST);
-}
-
-/**
- * Console command to toggle EC reset
- */
-static int command_ec_rst(int argc, char **argv)
-{
-	int val;
-
-	if (argc > 1) {
-		if (!ccd_is_cap_enabled(CCD_CAP_REBOOT_EC_AP))
-			return EC_ERROR_ACCESS_DENIED;
-
-		if (!strcasecmp("cl", argv[1])) {
-			/* Assert EC_RST_L until TPM_RST_L is asserted */
-			board_closed_loop_reset();
-		} else if (!strcasecmp("pulse", argv[1])) {
-			ccprintf("Pulsing EC reset\n");
-			board_reboot_ec();
-		} else if (parse_bool(argv[1], &val)) {
-			if (val)
-				assert_ec_rst();
-			else
-				deassert_ec_rst();
-		} else
-			return EC_ERROR_PARAM1;
-	}
-
-	ccprintf("EC_RST_L is %s\n", is_ec_rst_asserted() ?
-		 "asserted" : "deasserted");
-
-	return EC_SUCCESS;
-}
-DECLARE_SAFE_CONSOLE_COMMAND(ecrst, command_ec_rst,
-	"[cl | pulse | <BOOLEAN>]",
-	"Assert/deassert EC_RST_L to reset the EC (and AP)");
-
-/*
- * This function duplicates some of the functionality in chip/g/gpio.c in order
- * to configure a given strap pin to be either a low gpio output, a gpio input
- * with or without an internal pull resistor, or disconnect the gpio signal
- * from the pin pad.
- *
- * The desired gpio functionality is contained in the input parameter flags,
- * while the strap parameter is an index into the array strap_regs.
- */
-static void strap_config_pin(enum strap_list strap, int flags)
-{
-	const struct gpio_info *g = gpio_list + strap_regs[strap].gpio_signal;
-	int bitnum  = GPIO_MASK_TO_NUM(g->mask);
-	int mask = DIO_CTL_IE_MASK | DIO_CTL_PD_MASK | DIO_CTL_PU_MASK;
-	int val;
-
-	if (!flags) {
-		/* Reset strap pins, disconnect output and clear pull up/dn */
-		/* Disconnect gpio from pin mux */
-		DIO_SEL_REG(strap_regs[strap].sel_offset) = 0;
-		/* Clear input enable and pulldown/pullup in pinmux */
-		REG_WRITE_MLV(DIO_CTL_REG(strap_regs[strap].sel_offset),
-			      mask, 0, 0);
-		return;
-	}
-
-	if (flags & GPIO_OUT_LOW) {
-		/* Config gpio to output and drive low */
-		gpio_set_flags(strap_regs[strap].gpio_signal, GPIO_OUT_LOW);
-		/* connect pin mux to gpio */
-		DIO_SEL_REG(strap_regs[strap].sel_offset) =
-			GET_GPIO_FUNC(g->port, bitnum);
-		return;
-	}
-
-	if (flags & GPIO_INPUT) {
-		/* Configure gpio pin to be an input */
-		gpio_set_flags(strap_regs[strap].gpio_signal, GPIO_INPUT);
-		/* Connect pad to gpio */
-		GET_GPIO_SEL_REG(g->port, bitnum) =
-			strap_regs[strap].pad_select;
-
-		/*
-		 * Input enable is bit 2 of the CTL register. Pulldown enable is
-		 * bit 3, and pullup enable is bit 4. Always set input enable
-		 * and clear the pullup/pulldown bits unless the flags variable
-		 * specifies that pulldown or pullup should be enabled.
-		 */
-		val = DIO_CTL_IE_MASK;
-		if (flags & GPIO_PULL_DOWN)
-			val |= DIO_CTL_PD_MASK;
-		if (flags & GPIO_PULL_UP)
-			val |= DIO_CTL_PU_MASK;
-		/* Set input enable and pulldown/pullup in pinmux */
-		REG_WRITE_MLV(DIO_CTL_REG(strap_regs[strap].sel_offset),
-			      mask, 0, val);
-	}
-}
-
-static int get_strap_config(uint8_t *config)
-{
-	enum strap_list s0;
-	int lvl;
-	int flags;
-	uint8_t use_i2c;
-	uint8_t i2c_prop;
-	uint8_t use_spi;
-	uint8_t spi_prop;
-
-	/*
-	 * There are 4 pins that are used to determine Cr50 board strapping
-	 * options. These pins are:
-	 *   1. DIOA1  -> I2CS_SDA
-	 *   2. DI0A9  -> I2CS_SCL
-	 *   3. DIOA6  -> SPS_CLK
-	 *   4. DIOA12 -> SPS_CS_L
-	 * There are two main configuration options based on whether I2C or SPI
-	 * is used for TPM2 communication to/from the host AP. If SPI is the
-	 * TPM2 bus, then the pair of pins DIOA9|DIOA1 are used to designate
-	 * strapping options. If TPM uses I2C, then DIOA12|DIOA6 are the
-	 * strapping pins.
-	 *
-	 * Each strapping pin will have either an external pullup or pulldown
-	 * resistor. The external pull resistors have two levels, 5k for strong
-	 * and 1M for weak. Cr50 has internal pullup/pulldown 50k resistors that
-	 * can be configured via pinmux register settings. This combination of
-	 * external and internal pullup/pulldown resistors allows for 4 possible
-	 * states per strapping pin. The following table shows the different
-	 * combinations. Note that when a strong external pull down/up resistor
-	 * is used, the internal resistor is a don't care and those cases are
-	 * marked by n/a. The bits column represents the signal level read on
-	 * the gpio pin. Bit 1 of this field is the value read with the internal
-	 * pull down/up resistors disabled, and bit 0 is the gpio signal level
-	 * of the same pin when the internal pull resistor is selected as shown
-	 * in the 'internal' column.
-	 *   external    internal   bits
-	 *   --------    --------   ----
-	 *    5K PD       n/a        00
-	 *    1M PD       50k PU     01
-	 *    1M PU       50k PD     10
-	 *    5K PU       n/a        11
-	 *
-	 * To determine the bits associated with each strapping pin, the
-	 * following method is used.
-	 *   1. Set all 4 pins as inputs with internal pulls disabled.
-	 *   2. For each pin do the following to encode 2 bits b1:b0
-	 *      a. b1 = gpio_get_level(pin)
-	 *      b. If b1 == 1, then enable internal pulldown, else enable
-	 *         internal pullup resistor.
-	 *      c. b0 = gpio_get_level(pin)
-	 *
-	 * To be considered a valid strap configuraiton, the upper 4 bits must
-	 * have no pullups and at least one pullup in the lower 4 bits or vice
-	 * versa. So can use 0xA0 and 0x0A as masks to check for each
-	 * condition. Once this check is passed, the 4 bits which are used to
-	 * distinguish between SPI vs I2C are masked since reading them as weak
-	 * pulldowns is not being explicitly required due to concerns that the
-	 * AP could prevent accurate differentiation between strong and weak
-	 * pull down cases.
-	 */
-
-	/* Drive all 4 strap pins low to discharge caps. */
-	for (s0 = a0; s0 < ARRAY_SIZE(strap_regs); s0++)
-		strap_config_pin(s0, GPIO_OUT_LOW);
-	/* Delay long enough to discharge any caps. */
-	udelay(STRAP_PIN_DELAY_USEC);
-
-	/* Set all 4 strap pins as inputs with pull resistors disabled. */
-	for (s0 = a0; s0 < ARRAY_SIZE(strap_regs); s0++)
-		strap_config_pin(s0, GPIO_INPUT);
-	/* Delay so voltage levels can settle. */
-	udelay(STRAP_PIN_DELAY_USEC);
-
-	*config = 0;
-	/* Read 2 bit value of each strapping pin. */
-	ccprintf("strap pin readings:");
-	for (s0 = a0; s0 < ARRAY_SIZE(strap_regs); s0++) {
-		lvl = gpio_get_level(strap_regs[s0].gpio_signal);
-		flags = GPIO_INPUT;
-		if (lvl)
-			flags |= GPIO_PULL_DOWN;
-		else
-			flags |= GPIO_PULL_UP;
-		/* Enable internal pull down/up resistor. */
-		strap_config_pin(s0, flags);
-		udelay(STRAP_PIN_DELAY_USEC);
-		lvl = (lvl << 1) |
-			gpio_get_level(strap_regs[s0].gpio_signal);
-		ccprintf(" %s:%d", strap_regs[s0].pad_name, lvl);
-		*config |= lvl << s0 * 2;
-
-		/*
-		 * Finished with this pin. Disable internal pull up/dn resistor
-		 * and disconnect gpio from pin mux. The pins used for straps
-		 * are configured for their desired role when either the SPI or
-		 * I2C interfaces are initialized.
-		 */
-		strap_config_pin(s0, 0);
-	}
-	ccprintf("\n");
-
-	/*
-	 * The strap bits for DIOA12|DIOA6 are in the upper 4 bits of 'config'
-	 * while the strap bits for DIOA9|DIOA1 are in the lower 4 bits. Check
-	 * for SPI vs I2C config by checking for presence of external pullups in
-	 * one group of 4 bits and confirming no external pullups in the other
-	 * group. For SPI config the weak pulldowns may not be accurately read
-	 * on DIOA12|DIOA6 and similarly for I2C config on
-	 * DIOA9|DIOA1. Therefore, only requiring that there be no external
-	 * pullups on these pins and will mask the bits so they will match the
-	 * config table entries.
-	 */
-
-	use_i2c = *config & 0xa0;
-	use_spi = *config & 0x0a;
-	/*
-	 * The strap signals should have at least one pullup. Nothing can
-	 * interfere with these. If we did not read any pullups, these are
-	 * invalid straps. The config can't be salvaged.
-	 */
-	if (!use_i2c && !use_spi)
-		return EC_ERROR_INVAL;
-	/*
-	 * The unused strap signals are used for the bus to the AP. If the AP
-	 * has added pullups to the signals, it could interfere with the strap
-	 * readings. If pullups are found on both the SPI and I2C straps, use
-	 * the board properties to determine SPI vs I2C. We can use this to mask
-	 * unused config pins the AP is interfering with.
-	 */
-	if (use_i2c && use_spi) {
-		spi_prop = (GREG32(PMU, LONG_LIFE_SCRATCH1) &
-			    BOARD_SLAVE_CONFIG_SPI);
-		i2c_prop = (GREG32(PMU, LONG_LIFE_SCRATCH1) &
-			    BOARD_SLAVE_CONFIG_I2C);
-		/* Make sure exactly one interface is selected */
-		if ((i2c_prop && spi_prop) || (!spi_prop && !i2c_prop))
-			return EC_ERROR_INVAL;
-		use_spi = spi_prop;
-		CPRINTS("Ambiguous strap config. Use %s based on old "
-			"brdprop.", use_spi ? "spi" : "i2c");
-	}
-
-	/* Now that I2C vs SPI is known, mask the unused strap bits. */
-	*config &= use_spi ? 0xf : 0xf0;
-
-	return EC_SUCCESS;
-}
-
-static uint32_t get_properties(void)
-{
-	int i;
-	uint8_t config;
-	uint32_t properties;
-
-	if (chip_factory_mode()) {
-		CPRINTS("Chip factory mode, short circuit to SPI");
-		return BOARD_SLAVE_CONFIG_SPI;
-	}
-
-#ifdef H1_RED_BOARD
-	CPRINTS("Unconditionally enabling SPI and platform reset");
-	return (BOARD_SLAVE_CONFIG_SPI | BOARD_USE_PLT_RESET);
-#endif
-	if (get_strap_config(&config) != EC_SUCCESS) {
-		/*
-		 * No pullups were detected on any of the strap pins so there
-		 * is no point in checking for a matching config table entry.
-		 * For this case use default properties.
-		 */
-		CPRINTS("Invalid strap pins! Default properties = 0x%x",
-			BOARD_PROPERTIES_DEFAULT);
-		return BOARD_PROPERTIES_DEFAULT;
-	}
-
-	/* Search board config table to find a matching entry */
-	for (i = 0; i < ARRAY_SIZE(board_cfg_table); i++) {
-		if (board_cfg_table[i].strap_cfg == config) {
-			properties = board_cfg_table[i].board_properties;
-			CPRINTS("Valid strap: 0x%x properties: 0x%x",
-				config, properties);
-			/* Read board properties for this config */
-			return properties;
-		}
-	}
-
-	/*
-	 * Reached the end of the table and didn't find a matching config entry.
-	 * However, the SPI vs I2C determination can still be made as
-	 * get_strap_config() returned EC_SUCCESS.
-	 */
-	if (config & 0xa) {
-		properties = BOARD_SLAVE_CONFIG_SPI;
-		/*
-		 * Determine PLT_RST_L vs SYS_RST_L. Any board with a pullup on
-		 * DIOA9 uses PLT_RST_L.
-		 */
-		properties |= config & 0x8 ? BOARD_USE_PLT_RESET : 0;
-	} else {
-		/* All I2C boards use same default properties. */
-		properties = BOARD_PROPERTIES_DEFAULT;
-	}
-	CPRINTS("strap_cfg 0x%x has no table entry, prop = 0x%x",
-		config, properties);
-	return properties;
-}
-
-static void init_board_properties(void)
-{
-	uint32_t properties;
-
-	properties = GREG32(PMU, LONG_LIFE_SCRATCH1);
-
-	/*
-	 * This must be a power on reset or maybe restart due to a software
-	 * update from a version not setting the register.
-	 */
-	if (!(properties & BOARD_ALL_PROPERTIES) || (system_get_reset_flags() &
-						     EC_RESET_FLAG_HARD)) {
-		/*
-		 * Mask board properties because following hard reset, they
-		 * won't be cleared.
-		 */
-		properties &= ~BOARD_ALL_PROPERTIES;
-		properties |= get_properties();
-		/*
-		 * Now save the properties value for future use.
-		 *
-		 * Enable access to LONG_LIFE_SCRATCH1 reg.
-		 */
-		GWRITE_FIELD(PMU, LONG_LIFE_SCRATCH_WR_EN, REG1, 1);
-		/* Save properties in LONG_LIFE register */
-		GREG32(PMU, LONG_LIFE_SCRATCH1) = properties;
-		/* Disable access to LONG_LIFE_SCRATCH1 reg */
-		GWRITE_FIELD(PMU, LONG_LIFE_SCRATCH_WR_EN, REG1, 0);
-	}
-	/* Save this configuration setting */
-	board_properties = properties;
-}
-DECLARE_HOOK(HOOK_INIT, init_board_properties, HOOK_PRIO_FIRST);
-
-void i2cs_set_pinmux(void)
-{
-	/* Connect I2CS SDA/SCL output to A1/A9 pads */
-	GWRITE(PINMUX, DIOA1_SEL, GC_PINMUX_I2CS0_SDA_SEL);
-	GWRITE(PINMUX, DIOA9_SEL, GC_PINMUX_I2CS0_SCL_SEL);
-	/* Connect A1/A9 pads to I2CS input SDA/SCL */
-	GWRITE(PINMUX, I2CS0_SDA_SEL, GC_PINMUX_DIOA1_SEL);
-	GWRITE(PINMUX, I2CS0_SCL_SEL, GC_PINMUX_DIOA9_SEL);
-	/* Enable SDA/SCL inputs from A1/A9 pads */
-	GWRITE_FIELD(PINMUX, DIOA1_CTL, IE, 1);	 /* I2CS_SDA */
-	GWRITE_FIELD(PINMUX, DIOA9_CTL, IE, 1);	 /* I2CS_SCL */
-
-	/*
-	 * Provide access to the SDA line to be able to detect 'hosed i2c
-	 * slave' condition.
-	 */
-	GWRITE(PINMUX, GPIO0_GPIO14_SEL, GC_PINMUX_DIOA1_SEL);
-
-	/* Allow I2CS_SCL to wake from sleep */
-	GWRITE_FIELD(PINMUX, EXITEDGE0, DIOA9, 1); /* edge sensitive */
-	GWRITE_FIELD(PINMUX, EXITINV0, DIOA9, 1);  /* wake on low */
-	GWRITE_FIELD(PINMUX, EXITEN0, DIOA9, 1);   /* enable powerdown exit */
-
-	/* Allow I2CS_SDA to wake from sleep */
-	GWRITE_FIELD(PINMUX, EXITEDGE0, DIOA1, 1); /* edge sensitive */
-	GWRITE_FIELD(PINMUX, EXITINV0, DIOA1, 1);  /* wake on low */
-	GWRITE_FIELD(PINMUX, EXITEN0, DIOA1, 1);   /* enable powerdown exit */
-}
-
-static int command_sysinfo(int argc, char **argv)
-{
-	enum ec_image active;
-	uintptr_t vaddr;
-	const struct SignedHeader *h;
-	int reset_count = GREG32(PMU, LONG_LIFE_SCRATCH0);
-	char rollback_str[30];
-	uint8_t tpm_mode;
-
-	ccprintf("Reset flags: 0x%08x (", system_get_reset_flags());
-	system_print_reset_flags();
-	ccprintf(")\n");
-	if (system_rollback_detected())
-		ccprintf("Rollback detected\n");
-	ccprintf("Reset count: %d\n", reset_count);
-
-	ccprintf("Chip:        %s %s %s\n", system_get_chip_vendor(),
-		 system_get_chip_name(), system_get_chip_revision());
-
-	active = system_get_ro_image_copy();
-	vaddr = get_program_memory_addr(active);
-	h = (const struct SignedHeader *)vaddr;
-	ccprintf("RO keyid:    0x%08x\n", h->keyid);
-
-	active = system_get_image_copy();
-	vaddr = get_program_memory_addr(active);
-	h = (const struct SignedHeader *)vaddr;
-	ccprintf("RW keyid:    0x%08x\n", h->keyid);
-
-	ccprintf("DEV_ID:      0x%08x 0x%08x\n",
-		 GREG32(FUSE, DEV_ID0), GREG32(FUSE, DEV_ID1));
-
-	system_get_rollback_bits(rollback_str, sizeof(rollback_str));
-	ccprintf("Rollback:   %s\n", rollback_str);
-
-	tpm_mode = get_tpm_mode();
-	ccprintf("TPM MODE:    %s (%d)\n",
-		(tpm_mode == TPM_MODE_DISABLED) ? "disabled" : "enabled",
-		tpm_mode);
-	ccprintf("Key Ladder:  %s\n",
-		DCRYPTO_ladder_is_enabled() ?
-		 (board_in_prod_mode() ? "prod" : "dev") : "disabled");
-
-	return EC_SUCCESS;
-}
-DECLARE_SAFE_CONSOLE_COMMAND(sysinfo, command_sysinfo,
-			     NULL,
-			     "Print system info");
-
-/*
- * SysInfo command:
- * There are no input args.
- * Output is this struct, all fields in network order.
- */
-struct sysinfo_s {
-	uint32_t ro_keyid;
-	uint32_t rw_keyid;
-	uint32_t dev_id0;
-	uint32_t dev_id1;
-} __packed;
-
-static enum vendor_cmd_rc vc_sysinfo(enum vendor_cmd_cc code,
-				     void *buf,
-				     size_t input_size,
-				     size_t *response_size)
-{
-	enum ec_image active;
-	uintptr_t vaddr;
-	const struct SignedHeader *h;
-	struct sysinfo_s *sysinfo = buf;
-
-	active = system_get_ro_image_copy();
-	vaddr = get_program_memory_addr(active);
-	h = (const struct SignedHeader *)vaddr;
-	sysinfo->ro_keyid = htobe32(h->keyid);
-
-	active = system_get_image_copy();
-	vaddr = get_program_memory_addr(active);
-	h = (const struct SignedHeader *)vaddr;
-	sysinfo->rw_keyid = htobe32(h->keyid);
-
-	sysinfo->dev_id0 = htobe32(GREG32(FUSE, DEV_ID0));
-	sysinfo->dev_id1 = htobe32(GREG32(FUSE, DEV_ID1));
-
-	*response_size = sizeof(*sysinfo);
-	return VENDOR_RC_SUCCESS;
-}
-DECLARE_VENDOR_COMMAND(VENDOR_CC_SYSINFO, vc_sysinfo);
-
-static enum vendor_cmd_rc vc_invalidate_inactive_rw(enum vendor_cmd_cc code,
-						    void *buf,
-						    size_t input_size,
-						    size_t *response_size)
-{
-	const struct SignedHeader *header;
-	uint32_t ctrl;
-	uint32_t base_addr;
-	uint32_t size;
-	const char zero[4] = {}; /* value to write to magic. */
-
-	*response_size = 0;
-
-	/* Update INFO1 mask based on the currently active image. */
-	system_update_rollback_mask_with_active_img();
-
-	if (other_rw_is_inactive()) {
-		CPRINTS("%s: Inactive region is disabled", __func__);
-		return VENDOR_RC_SUCCESS;
-	}
-
-	/* save the original flash region6 register values */
-	ctrl = GREAD(GLOBALSEC, FLASH_REGION6_CTRL);
-	base_addr = GREG32(GLOBALSEC, FLASH_REGION6_BASE_ADDR);
-	size = GREG32(GLOBALSEC, FLASH_REGION6_SIZE);
-
-	header = get_other_rw_addr();
-
-	/* Enable RW access to the other header. */
-	GREG32(GLOBALSEC, FLASH_REGION6_BASE_ADDR) = (uint32_t) header;
-	GREG32(GLOBALSEC, FLASH_REGION6_SIZE) = 1023;
-	GWRITE_FIELD(GLOBALSEC, FLASH_REGION6_CTRL, EN, 1);
-	GWRITE_FIELD(GLOBALSEC, FLASH_REGION6_CTRL, RD_EN, 1);
-	GWRITE_FIELD(GLOBALSEC, FLASH_REGION6_CTRL, WR_EN, 1);
-
-	CPRINTS("%s: TPM verified corrupting inactive image, magic before %x",
-		__func__, header->magic);
-
-	flash_physical_write((intptr_t)&header->magic -
-			     CONFIG_PROGRAM_MEMORY_BASE,
-			     sizeof(zero), zero);
-
-	CPRINTS("%s: magic after: %x", __func__, header->magic);
-
-	/* Restore original values */
-	GREG32(GLOBALSEC, FLASH_REGION6_BASE_ADDR) = base_addr;
-	GREG32(GLOBALSEC, FLASH_REGION6_SIZE) = size;
-	GREG32(GLOBALSEC, FLASH_REGION6_CTRL) = ctrl;
-
-	return VENDOR_RC_SUCCESS;
-}
-DECLARE_VENDOR_COMMAND(VENDOR_CC_INVALIDATE_INACTIVE_RW,
-	vc_invalidate_inactive_rw);
-
-static enum vendor_cmd_rc vc_commit_nvmem(enum vendor_cmd_cc code,
-					  void *buf,
-					  size_t input_size,
-					  size_t *response_size)
-{
-	nvmem_enable_commits();
-	*response_size = 0;
-	return VENDOR_RC_SUCCESS;
-}
-DECLARE_VENDOR_COMMAND(VENDOR_CC_COMMIT_NVMEM, vc_commit_nvmem);
-
-static int command_board_properties(int argc, char **argv)
-{
-	/*
-	 * The board properties are stored in LONG_LIFE_SCRATCH1.  Note that we
-	 * don't just simply return board_properties here since that's just a
-	 * cached value from init time.
-	 */
-	ccprintf("properties = 0x%x\n", GREG32(PMU, LONG_LIFE_SCRATCH1));
-
-	return EC_SUCCESS;
-}
-DECLARE_SAFE_CONSOLE_COMMAND(brdprop, command_board_properties,
-			     NULL, "Display board properties");
-
-int chip_factory_mode(void)
-{
-	static uint8_t mode_set;
-
-	/*
-	 * Bit 0x2 used to indicate that mode has been set, bit 0x1 is the
-	 * actual indicator of the chip factory mode.
-	 */
-	if (!mode_set)
-		mode_set = 2 | !!gpio_get_level(GPIO_DIOB4);
-
-	return mode_set & 1;
-}
-
-#ifdef CR50_RELAXED
-static int command_rollback(int argc, char **argv)
-{
-	system_ensure_rollback();
-	ccprintf("Rebooting to alternate RW due to manual request\n");
-	cflush();
-	system_reset(0);
-
-	return EC_SUCCESS;
-}
-DECLARE_SAFE_CONSOLE_COMMAND(rollback, command_rollback,
-	"", "Force rollback to escape DEV image.");
-#endif
-
-/*
- * Set long life register bit requesting generating of the ITE SYNC sequence
- * and reboot.
- */
-static void deferred_ite_sync_reset(void)
-{
-	/* Enable writing to the long life register */
-	GWRITE_FIELD(PMU, LONG_LIFE_SCRATCH_WR_EN, REG1, 1);
-	GREG32(PMU, LONG_LIFE_SCRATCH1) |= BOARD_ITE_EC_SYNC_NEEDED;
-	/* Disable writing to the long life register */
-	GWRITE_FIELD(PMU, LONG_LIFE_SCRATCH_WR_EN, REG1, 0);
-
-	system_reset(SYSTEM_RESET_MANUALLY_TRIGGERED |
-		     SYSTEM_RESET_HARD);
-}
-DECLARE_DEFERRED(deferred_ite_sync_reset);
-
-void board_start_ite_sync(void)
-{
-	/* Let the usb reply to make it to the host. */
-	hook_call_deferred(&deferred_ite_sync_reset_data, 10 * MSEC);
-}
-
-void board_unwedge_i2cs(void)
-{
-	/*
-	 * Create connection between i2cs_scl and the 'unwedge_scl' GPIO, and
-	 * generate the i2c stop sequence which will reset the i2cs FSM.
-	 *
-	 * First, disconnect the external pin from the i2cs_scl input.
-	 */
-	GWRITE(PINMUX, DIOA9_SEL, 0);
-
-	/* Connect the 'unwedge' GPIO to the i2cs_scl input. */
-	GWRITE(PINMUX, GPIO1_GPIO5_SEL, GC_PINMUX_I2CS0_SCL_SEL);
-
-	/* Generate a 'stop' condition. */
-	gpio_set_level(GPIO_UNWEDGE_I2CS_SCL, 1);
-	usleep(2);
-	GWRITE_FIELD(I2CS, CTRL_SDA_VAL, READ0_S, 1);
-	usleep(2);
-	GWRITE_FIELD(I2CS, CTRL_SDA_VAL, READ0_S, 0);
-	usleep(2);
-
-	/* Disconnect the 'unwedge' mode SCL. */
-	GWRITE(PINMUX, GPIO1_GPIO5_SEL, 0);
-
-	/* Restore external pin connection to the i2cs_scl. */
-	GWRITE(PINMUX, DIOA9_SEL, GC_PINMUX_I2CS0_SCL_SEL);
-}
-
-int board_in_prod_mode(void)
-{
-	return in_prod_mode;
-}
diff --git a/board/cr50/board.h b/board/cr50/board.h
deleted file mode 100644
index f85d938b29..0000000000
--- a/board/cr50/board.h
+++ /dev/null
@@ -1,484 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_BOARD_H
-#define __CROS_EC_BOARD_H
-
-#define CONFIG_LTO
-
-/*
- * The default watchdog timeout is 1.6 seconds, but there are some legitimate
- * flash-intensive TPM operations that actually take close to that long to
- * complete. Make sure we don't trigger the watchdog accidentally if the timing
- * is just a little off.
- */
-#undef CONFIG_WATCHDOG_PERIOD_MS
-#define CONFIG_WATCHDOG_PERIOD_MS 5000
-
-/* Features that we don't want */
-#undef CONFIG_CMD_LID_ANGLE
-#undef CONFIG_CMD_POWERINDEBUG
-#undef CONFIG_DMA_DEFAULT_HANDLERS
-#undef CONFIG_FMAP
-#undef CONFIG_HIBERNATE
-#undef CONFIG_LID_SWITCH
-#undef CONFIG_CMD_SYSINFO
-#undef CONFIG_CMD_SYSJUMP
-#undef CONFIG_CMD_SYSLOCK
-
-#ifndef CR50_DEV
-/* Disable stuff that should only be in debug builds */
-#undef CONFIG_CMD_CRASH
-#undef CONFIG_CMD_MD
-#undef CONFIG_CMD_RW
-#undef CONFIG_CMD_SLEEPMASK_SET
-#undef CONFIG_CMD_WAITMS
-#undef CONFIG_FLASH
-#endif
-
-/* Enable getting gpio flags to tell if open drain pins are asserted */
-#define CONFIG_GPIO_GET_EXTENDED
-
-/* Flash configuration */
-#undef CONFIG_FLASH_PSTATE
-#define CONFIG_WP_ALWAYS
-#define CONFIG_CMD_FLASH
-
-#define CONFIG_CRC8
-
-/* We're using TOP_A for partition 0, TOP_B for partition 1 */
-#define CONFIG_FLASH_NVMEM
-/* Offset to start of NvMem area from base of flash */
-#define CONFIG_FLASH_NVMEM_OFFSET_A (CFG_TOP_A_OFF)
-#define CONFIG_FLASH_NVMEM_OFFSET_B (CFG_TOP_B_OFF)
-/* Address of start of Nvmem area */
-#define CONFIG_FLASH_NVMEM_BASE_A                                              \
-	(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_FLASH_NVMEM_OFFSET_A)
-#define CONFIG_FLASH_NVMEM_BASE_B                                              \
-	(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_FLASH_NVMEM_OFFSET_B)
-#define CONFIG_FLASH_NEW_NVMEM_BASE_A                                          \
-	(CONFIG_FLASH_NVMEM_BASE_A + CONFIG_FLASH_BANK_SIZE)
-#define CONFIG_FLASH_NEW_NVMEM_BASE_B                                          \
-	(CONFIG_FLASH_NVMEM_BASE_B + CONFIG_FLASH_BANK_SIZE)
-
-/* Size partition in NvMem */
-#define NVMEM_PARTITION_SIZE (CFG_TOP_SIZE)
-#define NEW_NVMEM_PARTITION_SIZE (NVMEM_PARTITION_SIZE - CONFIG_FLASH_BANK_SIZE)
-#define NEW_NVMEM_TOTAL_PAGES                                                  \
-	(2 * NEW_NVMEM_PARTITION_SIZE / CONFIG_FLASH_BANK_SIZE)
-/* Size in bytes of NvMem area */
-#define CONFIG_FLASH_LOG
-#define CONFIG_FLASH_NVMEM_SIZE (NVMEM_PARTITION_SIZE * NVMEM_NUM_PARTITIONS)
-/* Enable <key, value> variable support. */
-#define CONFIG_FLASH_NVMEM_VARS
-#define NVMEM_CR50_SIZE 272
-#define CONFIG_FLASH_NVMEM_VARS_USER_SIZE NVMEM_CR50_SIZE
-
-
-/* Go to sleep when nothing else is happening */
-#define CONFIG_LOW_POWER_IDLE
-
-/* Allow multiple concurrent memory allocations. */
-#define CONFIG_MALLOC
-
-/* Enable debug cable detection */
-#define CONFIG_RDD
-
-/* Also use the cr50 as a second factor authentication */
-#define CONFIG_U2F
-
-/* USB configuration */
-#define CONFIG_USB
-#define CONFIG_USB_CONSOLE_STREAM
-#undef CONFIG_USB_CONSOLE_TX_BUF_SIZE
-#define CONFIG_USB_CONSOLE_TX_BUF_SIZE		4096
-#define CONFIG_USB_I2C
-#define CONFIG_USB_INHIBIT_INIT
-#define CONFIG_USB_SPI
-#define CONFIG_USB_SERIALNO
-#define DEFAULT_SERIALNO "0"
-
-#define CONFIG_STREAM_USART
-#define CONFIG_STREAM_USB
-#define CONFIG_STREAM_USART1
-#define CONFIG_STREAM_USART2
-
-/* Enable Case Closed Debugging */
-#define CONFIG_CASE_CLOSED_DEBUG_V1
-#define CONFIG_PHYSICAL_PRESENCE
-/* Loosen CCD open requirements. Only allowed in prePVT images */
-#define CONFIG_CCD_OPEN_PREPVT
-
-#ifdef CR50_DEV
-/* Enable unsafe dev features for CCD in dev builds */
-#define CONFIG_CASE_CLOSED_DEBUG_V1_UNSAFE
-#define CONFIG_CMD_FLASH_LOG
-#define CONFIG_PHYSICAL_PRESENCE_DEBUG_UNSAFE
-#endif
-#if defined(CR50_DEV) || defined(CR50_SQA)
-#define CR50_RELAXED
-#endif
-
-#define CONFIG_USB_PID 0x5014
-#define CONFIG_USB_SELF_POWERED
-
-#undef CONFIG_USB_MAXPOWER_MA
-#define CONFIG_USB_MAXPOWER_MA 0
-
-/* Need to be able to bitbang the EC UART for updates through CCD. */
-#define CONFIG_UART_BITBANG
-
-/* Enable SPI Master (SPI) module */
-#define CONFIG_SPI_MASTER
-#define CONFIG_SPI_MASTER_NO_CS_GPIOS
-#define CONFIG_SPI_MASTER_CONFIGURE_GPIOS
-#define CONFIG_SPI_FLASH_PORT 0
-
-/* Enable SPI Slave (SPS) module */
-#define CONFIG_SPS
-#define CONFIG_TPM_SPS
-
-#define CONFIG_RBOX
-#define CONFIG_RBOX_WAKEUP
-
-/* We don't need to send events to the AP */
-#undef  CONFIG_HOSTCMD_EVENTS
-
-/* Make most commands restricted */
-#define CONFIG_CONSOLE_COMMAND_FLAGS
-#define CONFIG_RESTRICTED_CONSOLE_COMMANDS
-#define CONFIG_CONSOLE_COMMAND_FLAGS_DEFAULT CMD_FLAG_RESTRICTED
-
-/* Include crypto stuff, both software and hardware. Enable optimizations. */
-#define CONFIG_DCRYPTO
-#define CONFIG_UPTO_SHA512
-#define CONFIG_DCRYPTO_RSA_SPEEDUP
-
-/* Implement custom udelay, due to usec hwtimer imprecision. */
-#define CONFIG_HW_SPECIFIC_UDELAY
-
-#ifndef __ASSEMBLER__
-
-#include "gpio_signal.h"
-
-/* USB string indexes */
-enum usb_strings {
-	USB_STR_DESC = 0,
-	USB_STR_VENDOR,
-	USB_STR_PRODUCT,
-	USB_STR_VERSION,
-	USB_STR_CONSOLE_NAME,
-	USB_STR_BLOB_NAME,
-	USB_STR_HID_KEYBOARD_NAME,
-	USB_STR_AP_NAME,
-	USB_STR_EC_NAME,
-	USB_STR_UPGRADE_NAME,
-	USB_STR_SPI_NAME,
-	USB_STR_SERIALNO,
-	USB_STR_I2C_NAME,
-
-	USB_STR_COUNT
-};
-
-/*
- * Device states
- *
- * Note that not all states are used by all devices.
- */
-enum device_state {
-	/* Initial state at boot */
-	DEVICE_STATE_INIT = 0,
-
-	/*
-	 * Detect was not asserted at boot, but we're not willing to give up on
-	 * the device right away so we're debouncing to see if it shows up.
-	 */
-	DEVICE_STATE_INIT_DEBOUNCING,
-
-	/*
-	 * Device was detected at boot, but we can't enable transmit yet
-	 * because that would interfere with detection of another device.
-	 */
-	DEVICE_STATE_INIT_RX_ONLY,
-
-	/* Disconnected or off, because detect is deasserted */
-	DEVICE_STATE_DISCONNECTED,
-	DEVICE_STATE_OFF,
-
-	/* Device state is not knowable because we're driving detect */
-	DEVICE_STATE_UNDETECTABLE,
-
-	/* Connected or on, because detect is asserted */
-	DEVICE_STATE_CONNECTED,
-	DEVICE_STATE_ON,
-
-	/*
-	 * Device was connected, but we saw detect deasserted and are
-	 * debouncing to see if it stays deasserted - at which point we'll
-	 * decide that it's disconnected.
-	 */
-	DEVICE_STATE_DEBOUNCING,
-
-	/* Device state is unknown.  Used only by legacy device_state code. */
-	DEVICE_STATE_UNKNOWN,
-
-	/* The state is being ignored. */
-	DEVICE_STATE_IGNORED,
-
-	/* Number of device states */
-	DEVICE_STATE_COUNT
-};
-
-/**
- * Return the name of the device state as as string.
- *
- * @param state		State to look up
- * @return Name of the state, or "?" if no match.
- */
-const char *device_state_name(enum device_state state);
-
-/* NVMem variables. */
-enum nvmem_vars {
-	NVMEM_VAR_CONSOLE_LOCKED = 0,
-	NVMEM_VAR_TEST_VAR,
-	NVMEM_VAR_U2F_SALT,
-	NVMEM_VAR_CCD_CONFIG,
-	NVMEM_VAR_G2F_SALT,
-
-	NVMEM_VARS_COUNT
-};
-
-void board_configure_deep_sleep_wakepins(void);
-void ap_detect_asserted(enum gpio_signal signal);
-void ec_detect_asserted(enum gpio_signal signal);
-void servo_detect_asserted(enum gpio_signal signal);
-void tpm_rst_deasserted(enum gpio_signal signal);
-void tpm_rst_asserted(enum gpio_signal signal);
-
-void post_reboot_request(void);
-
-/* Special controls over EC and AP */
-void assert_sys_rst(void);
-void deassert_sys_rst(void);
-void assert_ec_rst(void);
-void deassert_ec_rst(void);
-int is_ec_rst_asserted(void);
-/* Ignore the servo state. */
-void servo_ignore(int enable);
-
-/**
- * Set up a deferred call to update CCD state.
- *
- * This will enable/disable UARTs, SPI, I2C, etc. as needed.
- */
-void ccd_update_state(void);
-
-/**
- * Return the state of the BOARD_USE_PLT_RST board strap option.
- *
- * @return 0 if option is not set, !=0 if option set.
- */
-int board_use_plt_rst(void);
-/**
- * Return the state of the BOARD_NEEDS_SYS_RST_PULL_UP board strap option.
- *
- * @return 0 if option is not set, !=0 if option set.
- */
-int board_rst_pullup_needed(void);
-/**
- * Return the state of the BOARD_SLAVE_CONFIG_I2C board strap option.
- *
- * @return 0 if option is not set, !=0 if option set.
- */
-int board_tpm_uses_i2c(void);
-/**
- * Return the state of the BOARD_SLAVE_CONFIG_SPI board strap option.
- *
- * @return 0 if option is not set, !=0 if option set.
- */
-int board_tpm_uses_spi(void);
-/**
- * Return the state of the BOARD_CLOSED_SOURCE_SET1 board strap option.
- *
- * @return 0 if option is not set, !=0 if option set.
- */
-int board_uses_closed_source_set1(void);
-/**
- * The board needs to wait until TPM_RST_L is asserted before deasserting
- * system reset signals.
- *
- * @return 0 if option is not set, !=0 if option set.
- */
-int board_uses_closed_loop_reset(void);
-/**
- * The board has all necessary I2C pins connected for INA support.
- *
- * @return 0 if option is not set, !=0 if option set.
- */
-int board_has_ina_support(void);
-/* The board allows vendor commands to enable/disable tpm. */
-int board_tpm_mode_change_allowed(void);
-int board_id_is_mismatched(void);
-/* Allow for deep sleep to be enabled on AP shutdown */
-int board_deep_sleep_allowed(void);
-
-void power_button_record(void);
-
-/**
- * Enable/disable power button release interrupt.
- *
- * @param enable	Enable (!=0) or disable (==0)
- */
-void power_button_release_enable_interrupt(int enable);
-
-/* Functions needed by CCD config */
-int board_battery_is_present(void);
-int board_fwmp_allows_unlock(void);
-int board_vboot_dev_mode_enabled(void);
-void board_reboot_ap(void);
-void board_reboot_ec(void);
-void board_closed_loop_reset(void);
-int board_wipe_tpm(int reset_required);
-int board_is_first_factory_boot(void);
-int board_fwmp_fips_mode_enabled(void);
-
-int usb_i2c_board_enable(void);
-void usb_i2c_board_disable(void);
-
-void print_ap_state(void);
-void print_ap_uart_state(void);
-void print_ec_state(void);
-void print_servo_state(void);
-
-int ap_is_on(void);
-int ap_uart_is_on(void);
-int ec_is_on(void);
-int ec_is_rx_allowed(void);
-int servo_is_connected(void);
-
-void set_ap_on(void);
-
-/* Returns True if chip is brought up in a factory test harness. */
-int chip_factory_mode(void);
-
-/*
- * Trigger generation of the ITE SYNC sequence on the way up after next
- * reboot.
- */
-void board_start_ite_sync(void);
-
-/*
- * Board specific function (needs information about pinmux settings) which
- * allows to take the i2cs controller out of the 'wedged' state where the
- * master stopped i2c access mid transaction and the slave is holding SDA low,
- */
-void board_unwedge_i2cs(void);
-
-int board_in_prod_mode(void);
-
-#endif /* !__ASSEMBLER__ */
-
-/* USB interface indexes (use define rather than enum to expand them) */
-#define USB_IFACE_CONSOLE 0
-#define USB_IFACE_AP      1
-#define USB_IFACE_EC      2
-#define USB_IFACE_UPGRADE 3
-#define USB_IFACE_SPI     4
-#define USB_IFACE_I2C     5
-#define USB_IFACE_COUNT   6
-
-/* USB endpoint indexes (use define rather than enum to expand them) */
-#define USB_EP_CONTROL   0
-#define USB_EP_CONSOLE   1
-#define USB_EP_AP        2
-#define USB_EP_EC        3
-#define USB_EP_UPGRADE   4
-#define USB_EP_SPI       5
-#define USB_EP_I2C       6
-#define USB_EP_COUNT     7
-
-/* UART indexes (use define rather than enum to expand them) */
-#define UART_CR50	0
-#define UART_AP		1
-#define UART_EC		2
-
-#define UARTN UART_CR50
-
-#define CC_DEFAULT     (CC_ALL & ~CC_MASK(CC_TPM))
-
-/* Nv Memory users */
-#ifndef __ASSEMBLER__
-enum nvmem_users {
-	NVMEM_TPM = 0,
-	NVMEM_CR50,
-	NVMEM_NUM_USERS
-};
-#endif
-
-#define CONFIG_FLASH_NVMEM_VARS_USER_NUM NVMEM_CR50
-#define CONFIG_RW_B
-
-/* Firmware upgrade options. */
-#define CONFIG_NON_HC_FW_UPDATE
-#define CONFIG_USB_FW_UPDATE
-
-#define CONFIG_I2C
-#define CONFIG_I2C_MASTER
-#define CONFIG_I2C_SLAVE
-#define CONFIG_TPM_I2CS
-
-#define CONFIG_BOARD_ID_SUPPORT
-#define CONFIG_SN_BITS_SUPPORT
-#define CONFIG_EXTENDED_VERSION_INFO
-
-#define I2C_PORT_MASTER 0
-
-#define CONFIG_BASE32
-#define CONFIG_RMA_AUTH
-#define CONFIG_FACTORY_MODE
-#define CONFIG_RNG
-
-#define CONFIG_ENABLE_H1_ALERTS
-
-/* Enable hardware backed brute force resistance feature */
-#define CONFIG_PINWEAVER
-
-/*
- * Disabling p256 will result in RMA Auth falling back to the x25519 curve
- * which in turn would require extra 5328 bytes of flash space.
- */
-#define CONFIG_RMA_AUTH_USE_P256
-#ifndef CONFIG_RMA_AUTH_USE_P256
-#define CONFIG_CURVE25519
-#endif
-
-#define CONFIG_CCD_ITE_PROGRAMMING
-
-/*
- * Increase sizes of USB over I2C read and write queues. Sizes are are such
- * that when appropriate overheads are included, total buffer sizes are powers
- * of 2 (2^9 in both cases below).
- */
-#undef CONFIG_USB_I2C_MAX_WRITE_COUNT
-#undef CONFIG_USB_I2C_MAX_READ_COUNT
-#define CONFIG_USB_I2C_MAX_WRITE_COUNT 508
-#define CONFIG_USB_I2C_MAX_READ_COUNT 506
-
-/* The below time constants are way longer than should be required in practice:
- *
- * Time it takes to finish processing TPM command
- */
-#define TPM_PROCESSING_TIME (1 * SECOND)
-
-/*
- * Time it takse TPM reset function to wipe out the NVMEM and reboot the
- * device.
- */
-#define TPM_RESET_TIME (10 * SECOND)
-
-/* Total time deep sleep should not be allowed while wiping the TPM. */
-#define DISABLE_SLEEP_TIME_TPM_WIPE (TPM_PROCESSING_TIME + TPM_RESET_TIME)
-
-#endif /* __CROS_EC_BOARD_H */
diff --git a/board/cr50/build.mk b/board/cr50/build.mk
deleted file mode 100644
index 5b0d788401..0000000000
--- a/board/cr50/build.mk
+++ /dev/null
@@ -1,122 +0,0 @@
-# -*- makefile -*-
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-# Board-specific build requirements
-
-# Define the SoC used by this board
-CHIP:=g
-CHIP_FAMILY:=cr50
-CHIP_VARIANT ?= cr50_fpga
-
-# This file is included twice by the Makefile, once to determine the CHIP info
-# and then again after defining all the CONFIG_ and HAS_TASK variables. We use
-# a guard so that recipe definitions and variable extensions only happen the
-# second time.
-ifeq ($(BOARD_MK_INCLUDED_ONCE),)
-
-# List of variables which can be defined in the environment or set in the make
-# command line.
-ENV_VARS := CR50_DEV CR50_SQA CRYPTO_TEST H1_RED_BOARD
-
-ifneq ($(CRYPTO_TEST),)
-CPPFLAGS += -DCRYPTO_TEST_SETUP
-endif
-
-
-BOARD_MK_INCLUDED_ONCE=1
-SIG_EXTRA = --cros
-else
-
-# Need to generate a .hex file
-all: hex
-
-# The simulator components have their own subdirectory
-CFLAGS += -I$(realpath chip/$(CHIP)/dcrypto)
-CFLAGS += -I$(realpath $(BDIR)/tpm2)
-dirs-y += chip/$(CHIP)/dcrypto
-dirs-y += $(BDIR)/tpm2
-
-# Objects that we need to build
-board-y =  board.o
-board-y += ap_state.o
-board-y += closed_source_set1.o
-board-y += ec_state.o
-board-y += power_button.o
-board-y += servo_state.o
-board-y += ap_uart_state.o
-board-y += factory_mode.o
-board-${CONFIG_RDD} += rdd.o
-board-${CONFIG_USB_SPI} += usb_spi.o
-board-${CONFIG_USB_I2C} += usb_i2c.o
-board-y += recovery_button.o
-board-y += tpm2/NVMem.o
-board-y += tpm2/aes.o
-board-y += tpm2/ecc.o
-board-y += tpm2/ecies.o
-board-y += tpm2/endorsement.o
-board-y += tpm2/hash.o
-board-y += tpm2/hash_data.o
-board-y += tpm2/hkdf.o
-board-y += tpm2/manufacture.o
-board-y += tpm2/nvmem_ops.o
-board-y += tpm2/platform.o
-board-y += tpm2/rsa.o
-board-y += tpm2/stubs.o
-board-y += tpm2/tpm_mode.o
-board-y += tpm2/tpm_state.o
-board-y += tpm2/trng.o
-board-y += tpm2/virtual_nvmem.o
-board-y += tpm_nvmem_ops.o
-board-y += wp.o
-board-$(CONFIG_U2F) += u2f.o
-
-ifneq ($(H1_RED_BOARD),)
-CPPFLAGS += -DH1_RED_BOARD=$(EMPTY)
-endif
-
-# Build and link with an external library
-EXTLIB := $(realpath ../../third_party/tpm2)
-CFLAGS += -I$(EXTLIB)
-
-# For the benefit of the tpm2 library.
-INCLUDE_ROOT := $(abspath ./include)
-CFLAGS += -I$(INCLUDE_ROOT)
-CPPFLAGS += -I$(abspath ./builtin)
-CPPFLAGS += -I$(abspath ./chip/$(CHIP))
-# For core includes
-CPPFLAGS += -I$(abspath .)
-CPPFLAGS += -I$(abspath $(BDIR))
-CPPFLAGS += -I$(abspath ./fuzz)
-CPPFLAGS += -I$(abspath ./test)
-ifeq ($(CONFIG_UPTO_SHA512),y)
-CPPFLAGS += -DSHA512_SUPPORT
-endif
-
-# Make sure the context of the software sha512 implementation fits. If it ever
-# increases, a compile time assert will fire in tpm2/hash.c.
-ifeq ($(CONFIG_UPTO_SHA512),y)
-CFLAGS += -DUSER_MIN_HASH_STATE_SIZE=208
-else
-CFLAGS += -DUSER_MIN_HASH_STATE_SIZE=112
-endif
-# Configure TPM2 headers accordingly.
-CFLAGS += -DEMBEDDED_MODE=1
-# Configure cryptoc headers to handle unaligned accesses.
-CFLAGS += -DSUPPORT_UNALIGNED=1
-
-TPM2_OBJS = $(shell find $(out)/tpm2 -name '*.cp.o')
-# Add dependencies on that library
-$(out)/RW/ec.RW.elf $(out)/RW/ec.RW_B.elf: LDFLAGS_EXTRA += $(TPM2_OBJS)
-$(out)/RW/ec.RW.elf $(out)/RW/ec.RW_B.elf: copied_objs
-
-# Force the external build each time, so it can look for changed sources.
-.PHONY: copied_objs
-copied_objs:
-	$(MAKE) obj=$(realpath $(out))/tpm2 EMBEDDED_MODE=1 \
-		-C $(EXTLIB) copied_objs
-
-endif   # BOARD_MK_INCLUDED_ONCE is nonempty
-
-board-$(CONFIG_PINWEAVER)+=pinweaver_tpm_imports.o
diff --git a/board/cr50/closed_source_set1.c b/board/cr50/closed_source_set1.c
deleted file mode 100644
index 058573fb46..0000000000
--- a/board/cr50/closed_source_set1.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Board specific routines used only when BOARD_CLOSED_SOURCE_SET1 is
- * enabled.
- */
-#include "ccd_config.h"
-#include "closed_source_set1.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-
-#define CPRINTF(format, args...) \
-	cprintf(CC_SYSTEM, "Closed Source Set1: " format, ## args)
-
-/*
- * Map common gpio.inc pin names to descriptive names specific to the
- * BOARD_CLOSED_SOURCE_SET1 option.
- */
-#define GPIO_FACTORY_MODE		GPIO_I2C_SCL_INA
-#define GPIO_CHROME_SEL			GPIO_EN_PP3300_INA_L
-#define GPIO_EXIT_FACTORY_MODE		GPIO_I2C_SDA_INA
-
-enum ec_trust_level {
-	EC_TL_FACTORY_MODE,
-	EC_TL_DIAGNOSTIC_MODE,
-	EC_TL_COREBOOT,
-};
-
-void closed_source_set1_configure_gpios(void)
-{
-	CPRINTF("configuring GPIOs\n");
-
-	/*
-	 * Connect GPIO outputs to pads:
-	 *     GPIO0_12 (FACTORY_MODE)      : B0
-	 *     GPIO0_13 (EXIT_FACTORY_MODE) : B1
-	 *     GPIO0_11 (CHROME_SEL)        : B7
-	 */
-	GWRITE(PINMUX, DIOB0_SEL, GC_PINMUX_GPIO0_GPIO12_SEL);
-	GWRITE(PINMUX, DIOB1_SEL, GC_PINMUX_GPIO0_GPIO13_SEL);
-	GWRITE(PINMUX, DIOB7_SEL, GC_PINMUX_GPIO0_GPIO11_SEL);
-
-	/*
-	 * The PINMUX entries in gpio.inc already write to the GPIOn_GPOIn_SEL
-	 * and DIOBn_CTL registers with values that work for GPIO output
-	 * operation. If gpio.inc makes changes to the GPIO_I2C_SCL_INA,
-	 * GPIO_I2C_SDA_INA, or GPIO_EN_PP3300_INA_L pinmux, then explicitly
-	 * configure the corresponding GPIOn_GPIOn_SEL and DIOBn_CTL registers
-	 * here.
-	 */
-
-	/*
-	 * TODO (keithshort): closed source EC documentation defines
-	 * EXIT_FACTORY_MODE as an output from the EC that is driven low
-	 * to indicate that factory mode must be terminated.  However, the
-	 * EC firmware has not yet (and may never) add this capability.
-	 */
-
-	closed_source_set1_update_factory_mode();
-}
-
-static void closed_source_set1_update_ec_trust_level(enum ec_trust_level tl)
-{
-	/*
-	 * The EC state is partially controlled by the FACTORY_MODE and
-	 * CHROME_SEL signals.
-	 *
-	 * State                          Description
-	 * CHROME_SEL=0,FACTORY_MODE=1    TL0: EC factory mode
-	 * CHROME_SEL=0,FACTORY_MODE=0    TL1: EC diagnostic mode
-	 * CHROME_SEL=1,FACTORY_MODE=0    TL2: EC coreboot mode
-	 * CHROME_SEL=1,FACTORY_MODE=1    Undefined
-	 */
-	switch (tl) {
-	case EC_TL_FACTORY_MODE:
-		CPRINTF("enable factory mode\n");
-		/*
-		 * Enable factory mode, CHROME_SEL must be set low first so
-		 * that CHROME_SEL and FACTORY_MODE are not high
-		 * simultaneously.
-		 */
-		gpio_set_flags(GPIO_CHROME_SEL, GPIO_OUT_LOW);
-		gpio_set_flags(GPIO_FACTORY_MODE, GPIO_OUT_HIGH);
-		break;
-
-	case EC_TL_DIAGNOSTIC_MODE:
-		CPRINTF("enable diagnostic mode\n");
-
-		gpio_set_flags(GPIO_CHROME_SEL, GPIO_OUT_LOW);
-		gpio_set_flags(GPIO_FACTORY_MODE, GPIO_OUT_LOW);
-		break;
-
-	case EC_TL_COREBOOT:
-		CPRINTF("disable factory mode\n");
-		/*
-		 * Disable factory mode, set FACTORY_MODE low first to avoid
-		 * undefined state.
-		 */
-		gpio_set_flags(GPIO_FACTORY_MODE, GPIO_OUT_LOW);
-		gpio_set_flags(GPIO_CHROME_SEL, GPIO_OUT_HIGH);
-		break;
-	default:
-		CPRINTF("unsupported EC trust level %d\n", tl);
-	}
-}
-
-void closed_source_set1_update_factory_mode(void)
-{
-	if (ccd_get_factory_mode())
-		closed_source_set1_update_ec_trust_level(EC_TL_FACTORY_MODE);
-	else
-		closed_source_set1_update_ec_trust_level(EC_TL_COREBOOT);
-}
-
-void close_source_set1_disable_tpm(void)
-{
-	/*
-	 * Once the TPM mode is disabled from the AP, set the EC trust level
-	 * to permit running diagnostics.  Diagnostic mode may be entered from
-	 * any of the EC trust level states, so no additional checks are needed.
-	 *
-	 * This state is only cleared by a reboot of the Cr50 and then the
-	 * trust level reverts back to either EC_TL_FACTORY_MODE or
-	 * EC_TL_COREBOOT.
-	 */
-	closed_source_set1_update_ec_trust_level(EC_TL_DIAGNOSTIC_MODE);
-}
-
-
-#ifdef CR50_DEV
-/* Debug command to manually set the EC trust level */
-static int ec_trust_level(int argc, char **argv)
-{
-	enum ec_trust_level tl;
-
-	if (argc > 1) {
-		tl = (enum ec_trust_level)atoi(argv[1]);
-
-		closed_source_set1_update_ec_trust_level(tl);
-	}
-
-	ccprintf("CCD factory mode  = %d\n", ccd_get_factory_mode());
-
-	ccprintf("FACTORY_MODE      = %d\n",
-		gpio_get_level(GPIO_FACTORY_MODE));
-	ccprintf("CHROME_SEL        = %d\n",
-		gpio_get_level(GPIO_CHROME_SEL));
-	ccprintf("EXIT_FACTORY_MODE = %d\n",
-		gpio_get_level(GPIO_EXIT_FACTORY_MODE));
-
-	return 0;
-}
-DECLARE_SAFE_CONSOLE_COMMAND(ectrust, ec_trust_level,
-	"[0|1|2]",
-	"Get/set the EC trust level");
-#endif
-
diff --git a/board/cr50/closed_source_set1.h b/board/cr50/closed_source_set1.h
deleted file mode 100644
index 0970726f45..0000000000
--- a/board/cr50/closed_source_set1.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __EC_BOARD_CR50_CLOSED_SOURCE_SET1_H
-#define __EC_BOARD_CR50_CLOSED_SOURCE_SET1_H
-
-
-/**
- * Configure the GPIOs specific to the BOARD_CLOSED_SOURCE_SET1 board strapping
- * option.  This includes the FACTORY_MODE, CHROME_SEL, and EXIT_FACTORY_MODE
- * signals.
- */
-void closed_source_set1_configure_gpios(void);
-
-/**
- * Drive the GPIOs specific to BOARD_CLOSED_SOURCE_SET1 to match the current
- * factory mode setting.
- */
-void closed_source_set1_update_factory_mode(void);
-
-/**
- * In response to a TPM_MODE disable, drive the GPIOs specific to
- * BOARD_CLOSED_SOURCE_SET1 to match the diagnostic state setting.
- */
-void close_source_set1_disable_tpm(void);
-
-
-#endif   /* ! __EC_BOARD_CR50_CLOSED_SOURCE_SET1_H */
diff --git a/board/cr50/ec.tasklist b/board/cr50/ec.tasklist
deleted file mode 100644
index 43641c6c38..0000000000
--- a/board/cr50/ec.tasklist
+++ /dev/null
@@ -1,12 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/**
- * See CONFIG_TASK_LIST in config.h for details.
- */
-#define CONFIG_TASK_LIST \
-	TASK_ALWAYS(HOOKS, hook_task, NULL, CONFIG_STACK_SIZE) \
-	TASK_NOTEST(TPM, tpm_task, NULL, 8192) \
-	TASK_ALWAYS(CONSOLE, console_task, NULL, CONFIG_STACK_SIZE)
diff --git a/board/cr50/ec_state.c b/board/cr50/ec_state.c
deleted file mode 100644
index c42518f709..0000000000
--- a/board/cr50/ec_state.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * EC state machine
- */
-#include "ccd_config.h"
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "uart_bitbang.h"
-#include "uartn.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-
-static enum device_state state = DEVICE_STATE_INIT;
-
-void print_ec_state(void)
-{
-	ccprintf("EC:      %s\n", device_state_name(state));
-}
-
-int ec_is_on(void)
-{
-	/* Debouncing and on are both still on */
-	return (state == DEVICE_STATE_DEBOUNCING || state == DEVICE_STATE_ON);
-}
-
-int ec_is_rx_allowed(void)
-{
-	return ec_is_on() || state == DEVICE_STATE_INIT_RX_ONLY;
-}
-
-/**
- * Set the EC state.
- *
- * Done as a function to make it easier to debug state transitions.  Note that
- * this ONLY sets the state (and possibly prints debug info), and doesn't do
- * all the additional transition work that set_ec_on(), etc. do.
- *
- * @param new_state	State to set.
- */
-static void set_state(enum device_state new_state)
-{
-#ifdef CR50_DEBUG_EC_STATE
-	/* Print all state transitions.  May spam the console. */
-	if (state != new_state)
-		CPRINTS("EC %s -> %s",
-			device_state_name(state), device_state_name(new_state));
-#endif
-	state = new_state;
-}
-
-/**
- * Move the EC to the ON state.
- *
- * This can be deferred from the interrupt handler, or called from the state
- * machine which also runs in HOOK task, so it needs to check the current state
- * to determine whether we're already on.
- */
-static void set_ec_on(void)
-{
-	/* If we're already on, done */
-	if (state == DEVICE_STATE_ON)
-		return;
-
-	/* If we were debouncing ON->OFF, cancel it because we're still on */
-	if (state == DEVICE_STATE_DEBOUNCING) {
-		set_state(DEVICE_STATE_ON);
-		return;
-	}
-
-	if (state == DEVICE_STATE_INIT ||
-	    state == DEVICE_STATE_INIT_DEBOUNCING) {
-		/*
-		 * Enable the UART peripheral so we start receiving on EC RX,
-		 * but do not call uartn_tx_connect() to connect EC TX yet.  We
-		 * need to be able to use EC TX to detect servo, so if we drive
-		 * it right away that blocks us from detecting servo.
-		 */
-		CPRINTS("EC RX only");
-		set_state(DEVICE_STATE_INIT_RX_ONLY);
-		ccd_update_state();
-		return;
-	}
-
-	/* We were previously off */
-	CPRINTS("EC on");
-	set_state(DEVICE_STATE_ON);
-	ccd_update_state();
-}
-DECLARE_DEFERRED(set_ec_on);
-
-/**
- * Interrupt handler for EC detect asserted.
- */
-void ec_detect_asserted(enum gpio_signal signal)
-{
-	gpio_disable_interrupt(GPIO_DETECT_EC_UART);
-	hook_call_deferred(&set_ec_on_data, 0);
-}
-
-/**
- * Detect state machine
- */
-static void ec_detect(void)
-{
-	/* Disable interrupts if we had them on for debouncing */
-	gpio_disable_interrupt(GPIO_DETECT_EC_UART);
-
-	if (uart_bitbang_is_enabled())
-		return;
-
-	/* If we detect the EC, make sure it's on */
-	if (gpio_get_level(GPIO_DETECT_EC_UART)) {
-		set_ec_on();
-		return;
-	}
-	/*
-	 * Make sure the interrupt is enabled. We will need to detect the on
-	 * transition if we enter the off or debouncing state
-	 */
-	gpio_enable_interrupt(GPIO_DETECT_EC_UART);
-
-	/* EC wasn't detected.  If we're already off, done. */
-	if (state == DEVICE_STATE_OFF)
-		return;
-
-	/* If we were debouncing, we're now sure we're off */
-	if (state == DEVICE_STATE_DEBOUNCING ||
-	    state == DEVICE_STATE_INIT_DEBOUNCING) {
-		CPRINTS("EC off");
-		set_state(DEVICE_STATE_OFF);
-		ccd_update_state();
-		return;
-	}
-
-	/*
-	 * Otherwise, we were on or initializing, and we're not sure if the EC
-	 * is actually off or just sending a 0-bit.  So start debouncing.
-	 */
-	if (state == DEVICE_STATE_INIT)
-		set_state(DEVICE_STATE_INIT_DEBOUNCING);
-	else
-		set_state(DEVICE_STATE_DEBOUNCING);
-}
-DECLARE_HOOK(HOOK_SECOND, ec_detect, HOOK_PRIO_DEFAULT);
diff --git a/board/cr50/factory_mode.c b/board/cr50/factory_mode.c
deleted file mode 100644
index 9597b1b440..0000000000
--- a/board/cr50/factory_mode.c
+++ /dev/null
@@ -1,119 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "board_id.h"
-#include "console.h"
-#include "ccd_config.h"
-#include "ec_commands.h"
-#include "extension.h"
-#include "system.h"
-
-#define CPRINTS(format, args...) cprints(CC_CCD, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_CCD, format, ## args)
-
-
-static int board_id_is_erased(void)
-{
-	struct board_id id;
-	/*
-	 * If we can't read the board id for some reason, return 0 just to be
-	 * safe
-	 */
-	if (read_board_id(&id) != EC_SUCCESS) {
-		CPRINTS("%s: BID read error", __func__);
-		return 0;
-	}
-
-	if (board_id_is_blank(&id)) {
-		CPRINTS("BID erased");
-		return 1;
-	}
-	return 0;
-}
-
-static int inactive_image_is_guc_image(void)
-{
-	enum ec_image inactive_copy;
-	const struct SignedHeader *other;
-
-	if (system_get_image_copy() == EC_IMAGE_RW)
-		inactive_copy = EC_IMAGE_RW_B;
-	else
-		inactive_copy = EC_IMAGE_RW;
-	other = (struct SignedHeader *) get_program_memory_addr(
-		inactive_copy);
-	/*
-	 * Chips from GUC are manufactured with 0.0.13 or 0.0.22. Compare the
-	 * versions to determine if the inactive image is a GUC image.
-	 */
-	if (other->epoch_ == 0 && other->major_ == 0 &&
-	    ((other->minor_ == 13) || (other->minor_ == 22))) {
-		CPRINTS("GUC in inactive RW");
-		return 1;
-	}
-	/*
-	 * TODO(mruthven): Return true if factory image field of header is
-	 * set
-	 */
-	return 0;
-}
-
-/**
- * Return non-zero if this is the first boot of a board in the factory.
- *
- * This is used to determine whether the default CCD configuration will be RMA
- * (things are unlocked for factory) or normal (things locked down because not
- * in factory).
- *
- * checks:
- * - If the system recovered from reboot not deep sleep resume.
- * - If the board ID exists, this is not the first boot
- * - If the inactive image is not a GUC image, then we've left the factory
- */
-int board_is_first_factory_boot(void)
-{
-	return (!(system_get_reset_flags() & EC_RESET_FLAG_HIBERNATE) &&
-		inactive_image_is_guc_image() && board_id_is_erased());
-}
-
-/*
- * Vendor command for ccd factory reset.
- *
- * This vendor command can be used to enable ccd and disable write protect with
- * a factory reset. A factory reset is automatically done during the first
- * factory boot, but this vendor command can be used to do a factory reset at
- * any time. Before calling factory reset, cr50 will make sure it is safe to do
- * so. Cr50 checks batt_is_present to make sure the user has physical access to
- * the device. Cr50 also checks ccd isn't disabled by the FWMP or ccd password.
- *
- * checks:
- * - batt_is_present - Factory reset can only be done if HW write protect is
- *              removed.
- * - FWMP disables ccd -  If FWMP has disabled ccd, then we can't bypass it with
- *              a factory reset.
- * - CCD password is set - If there is a password, someone will have to use that
- *              to open ccd and enable ccd manually. A factory reset cannot be
- *              used to get around the password.
- */
-static enum vendor_cmd_rc vc_factory_reset(enum vendor_cmd_cc code,
-					   void *buf,
-					   size_t input_size,
-					   size_t *response_size)
-{
-	*response_size = 0;
-
-	if (input_size)
-		return VENDOR_RC_BOGUS_ARGS;
-
-	if (board_battery_is_present() || !board_fwmp_allows_unlock() ||
-	    ccd_has_password())
-		return VENDOR_RC_NOT_ALLOWED;
-
-	CPRINTF("factory reset\n");
-	enable_ccd_factory_mode(1);
-
-	return VENDOR_RC_SUCCESS;
-}
-DECLARE_VENDOR_COMMAND(VENDOR_CC_RESET_FACTORY, vc_factory_reset);
diff --git a/board/cr50/gpio.inc b/board/cr50/gpio.inc
deleted file mode 100644
index 73a7360de1..0000000000
--- a/board/cr50/gpio.inc
+++ /dev/null
@@ -1,295 +0,0 @@
-/* -*- mode:c -*-
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * This file describes GPIO mapping for the cr50 code running on the H1 chip.
- *
- * For the purposes of this file H1 core has the following logical and
- * physical items and properties:
- *
- *   - 32 internal GPIOs, which are split into two ports of 16 bits each.
- *     Ports' architecture and programmig is described in "ARM Cortex-M System
- *     Design Kit TRM" DDIO47B.
- *
- *   - a set of peripherals - slave and master SPI and I2C controllers, UARTs,
- *     interrupt controller, etc.
- *
- *   - 28 pins on the package named DIOA0..14, DIOB0..7 and DIOM0..4
- *
- *   - a PINMUX - a unit which allows to interconnect objects from the three
- *     groups listed above. Note that some peripherals are attached to some
- *     pins directly, so in case those peripherals are used the pins should
- *     not be connected by PINMUX to any other outputs.
- *
- * The below macros are somewhat misleading (apparently for historical
- * reasons), as PIN(p, b) component in fact refers not to the external pin,
- * but to the GPIO (bit b on port p), where bit is in 0..15 range, and port is
- * in 0..1 range.
- *
- * To describe routing of an external signal two macro instantiations are
- * required:
- *
- * The GPIO_INT() or GPIO() macro assigns the signal a name and assigns it to
- * the internal GPIO port, (again, defining the port using the PIN(port, bit)
- * component of the macro invocation). GPIO_INT definitions assign their
- * respective signals to interrupts and ISRs.
- *
- * The PINMUX macro assigns the previously defined GPIO to another object,
- * most commonly to an external pin, but possibly to some internal component.
- */
-
-/* Declare symbolic names for all the GPIOs that we care about.
- * Note: Those with interrupt handlers must be declared first. */
-
-/*
- * A manually maintained tally of all GPIO ports configured in this file.
- *
- * GPIO0.0   int_ap_l
- * GPIO0.1   ec_flash_select
- * GPIO0.2   ap_flash_select
- * GPIO0.4   sys_rst_l_out
- * GPIO0.5   ccd_mode_l
- * GPIO0.6   batt_pres_l
- * GPIO0.7   spi_mosi
- * GPIO0.8   spi_clk
- * GPIO0.9   spi_cs_l
- * GPIO0.10  diob4
- * GPIO0.11  en_pp3300_ina
- * GPIO0.12  i2c_scl_ina
- * GPIO0.13  i2c_sda_ina
- * GPIO0.14  i2cs_sda poll
- * GPIO0.15  ec_tx_cr50_rx_out
- * GPIO1.0   tpm_rst_l
- * GPIO1.1   detect_ap_uart
- * GPIO1.2   detect_ec_uart
- * GPIO1.3   detect_servo
- * GPIO1.4   detect_tpm_rst_asserted
- * GPIO1.5   unwedge_i2cs_scl
- * GPIO1.6   monitor_i2cs_sda
- * GPIO1.11  ec_tx_cr50_rx_in
- * GPIO1.12  strap_a0
- * GPIO1.13  strap_a1
- * GPIO1.14  strap_b0
- * GPIO1.15  strap_b1
- */
-/*****************************************************************************/
-/* INTERRUPT GPIOs - interrupts processed in chip/g/gpio.c */
-/*
- * The system reset signal can be from two different pins depending on what the
- * board type is. One board uses plt_rst_l (diom3) and the other board type uses
- * sys_rst_l (diom0) to detect a warm reset. The pin is selected based on the
- * board properties in board.c
- *
- * On both boards sys_rst_l is used as an output to trigger warm resets. The ARM
- * core can't trigger an interrupt if it's driving it as an output so we attach
- * two internal GPIOs to the same pad if sys_rst_l is also being used to detect
- * system resets.
- */
-GPIO_INT(TPM_RST_L,       PIN(1, 0),  GPIO_INT_RISING, tpm_rst_deasserted)
-GPIO_INT(DETECT_AP_UART,  PIN(1, 1),  GPIO_INT_HIGH, ap_detect_asserted)
-GPIO_INT(DETECT_EC_UART,  PIN(1, 2),  GPIO_INT_HIGH, ec_detect_asserted)
-/*
- * DETECT_SERVO and EC_TX_CR50_RX pins must NOT be changed without also changing
- * the pinmux_regval fields in the bitbang_config in board.c.  The pinmux values
- * in the config assume the pin definitions here.
- */
-GPIO_INT(DETECT_SERVO,    PIN(1, 3),  GPIO_INT_HIGH | GPIO_PULL_DOWN,
-	 servo_detect_asserted)
-/*
- * Whan TPM_RST_L is asserted, the AP is in reset. Use this for detecting when
- * the AP is off.
- */
-GPIO_INT(DETECT_TPM_RST_L_ASSERTED, PIN(1, 4),  GPIO_INT_FALLING,
-         tpm_rst_asserted)
-
-/*****************************************************************************/
-/* NON STANDARD INTERRUPT GPIOs - handlers defined and configured in board.c */
-/*
- * This signal is used as an interrupt for uart bitbang. This is setup manually
- * in board.c instead of using chip/g/gpio.c, so the interrupts can be processed
- * more quickly. This increases the max bitbang programming speed.
- *
- * If this gpio is changed, you must update the information in board.c.
- */
-GPIO(EC_TX_CR50_RX,   PIN(1, 11),  GPIO_INPUT)
-
-/*****************************************************************************/
-/* GPIOs */
-/* Pull this low to interrupt the AP */
-GPIO(INT_AP_L,        PIN(0, 0), GPIO_OUT_HIGH)
-
-/* Use these to take over the AP & EC flash (only when AP & EC are off!) */
-GPIO(EC_FLASH_SELECT, PIN(0, 1), GPIO_OUT_LOW)
-GPIO(AP_FLASH_SELECT, PIN(0, 2), GPIO_OUT_LOW)
-
-/*
- * Pull this low to reset the AP. (We reset the EC with the RBOX.)
- * This is pseudo open drain.
- */
-GPIO(SYS_RST_L_OUT,   PIN(0, 4), GPIO_ODR_HIGH)
-
-/*
- * Indicate to EC when CCD is enabled. EC can pull this down too, to tell us if
- * it decided instead.
- * This is pseudo open drain.
- */
-GPIO(CCD_MODE_L,      PIN(0, 5), GPIO_ODR_HIGH | GPIO_PULL_UP)
-
-/* Battery present signal is active low */
-GPIO(BATT_PRES_L,     PIN(0, 6), GPIO_INPUT)
-
-/* GPIOs used to tristate the SPI bus */
-GPIO(SPI_MOSI,        PIN(0, 7), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(SPI_CLK,         PIN(0, 8), GPIO_INPUT | GPIO_PULL_DOWN)
-GPIO(SPI_CS_L,        PIN(0, 9), GPIO_INPUT)
-
-/* Used during *chip* factory process. */
-GPIO(DIOB4,           PIN(0, 10), GPIO_INPUT | GPIO_PULL_DOWN)
-
-/* GPIOs used for Cr50 strapping options */
-GPIO(STRAP_A0,        PIN(1, 12), GPIO_INPUT)
-GPIO(STRAP_A1,        PIN(1, 13), GPIO_INPUT)
-GPIO(STRAP_B0,        PIN(1, 14), GPIO_INPUT)
-GPIO(STRAP_B1,        PIN(1, 15), GPIO_INPUT)
-
-GPIO(UNWEDGE_I2CS_SCL, PIN(1, 5), GPIO_OUT_HIGH)
-
-/*
- * A GPIO to sample the current state of the I2CS SDA line, allowing to detect
- * the 'wedged I2C bus' condition.
- */
-GPIO(MONITOR_I2CS_SDA, PIN(1, 6), GPIO_INPUT)
-
-/*
- * If you change the names of EN_PP3300_INA_L, I2C_SCL_INA, or I2C_SDA_INA,
- * you also need to update the usage in closed_source_set1.c
- */
-/* Control the load switch powering the INA 3.3V rail */
-GPIO(EN_PP3300_INA_L, PIN(0, 11), GPIO_ODR_HIGH)
-/* GPIOs used for I2CM pins for INAs */
-GPIO(I2C_SCL_INA,     PIN(0, 12), GPIO_INPUT)
-GPIO(I2C_SDA_INA,     PIN(0, 13), GPIO_INPUT)
-
-/*
- * Use this to poll the state of the I2CS SDA line. Note that this is not
- * necessary if SPI interface is used to communicate with the AP, if needed,
- * this GPIO could be reclaimed in that case.
- *
- * Actual attachment of this GPIO to the SDA line happens in board.c only when
- * I2CS interface is required. Should this GPIO ever change, the code setting
- * up the pinmux in board.c will have to change as well.
- */
-GPIO(I2CS_SDA,        PIN(0, 14), GPIO_INPUT)
-/*
- * Fake open drain on EC_TX_CR50_RX_OUT. When asserted, the signal can be used
- * to enable UART programming mode on the EC. The signal needs to fake open
- * drain so it can still be used as the cr50 rx signal when it is deasserted.
- */
-GPIO(EC_TX_CR50_RX_OUT, PIN(0, 15), GPIO_ODR_HIGH)
-
-/*
- * ENTERING_RW is not a GPIO in H1, but an input pin to RBOX module.
- * However, we declare it as 'UNIMPLEMENTED' to avoid a compile error in
- * common/system.c.
- */
-UNIMPLEMENTED(ENTERING_RW)
-
-/*
- * If we are included by generic GPIO code that doesn't know about the PINMUX
- * macro we need to provide an empty definition so that the invocations don't
- * interfere with other GPIO processing.
- */
-#ifndef PINMUX
-#define PINMUX(...)
-#endif
-
-/* GPIOs - mark outputs as inputs too, to read back from the driven pad */
-PINMUX(GPIO(INT_AP_L),        A5, DIO_INPUT)	/* DIOB7 is p_digitial_od */
-                                                /* We can't pull it up */
-PINMUX(GPIO(EC_FLASH_SELECT), B2, DIO_INPUT)
-PINMUX(GPIO(AP_FLASH_SELECT), B3, DIO_INPUT)
-PINMUX(GPIO(MONITOR_I2CS_SDA), A1, GPIO_INPUT)
-
-/*
- * Update closed_source_set1.c if pinmux for EN_PP3300_INA_L is changed or
- * removed.
- */
-PINMUX(GPIO(EN_PP3300_INA_L), B7, DIO_INPUT)
-PINMUX(GPIO(SYS_RST_L_OUT),   M0, DIO_INPUT)
-PINMUX(GPIO(CCD_MODE_L),      M1, DIO_INPUT)
-PINMUX(GPIO(BATT_PRES_L),     M2, 0)
-/*
- * Update closed_source_set1.c if pinmux for I2C_SCL_INA or I2C_SDA_INA is
- * changed or removed.
- */
-PINMUX(GPIO(I2C_SCL_INA),     B0, DIO_INPUT)
-PINMUX(GPIO(I2C_SDA_INA),     B1, DIO_INPUT)
-/* UARTs */
-PINMUX(FUNC(UART0_TX),        A0, DIO_OUTPUT)	/* Cr50 console */
-PINMUX(FUNC(UART0_RX),        A13, DIO_INPUT | DIO_WAKE_LOW)
-/*
- * UART1_TX and UART2_TX are configured in usart.c. They are not set as outputs
- * here in order to avoid interfering with servo. They can be controlled using
- * the 'uart' console command.
- *   UART1_TX = DIOA7	AP console
- *   UART2_TX = DIOB5	EC console
- */
-PINMUX(FUNC(UART1_RX),        A3, DIO_INPUT)	/* AP console */
-PINMUX(FUNC(UART2_RX),        B6, DIO_INPUT)	/* EC console */
-/*
- * Monitor UART RX/TX signals to detect state changes on the EC, AP, and servo.
- *
- * The idle state of the RX signals when the AP or EC are powered on is high.
- * When they are not powered, the signals will remain low. When servo is
- * connected it drives the TX signals high. The servo TX signals are wired
- * to cr50's. Because the two device TX signals are directly wired together,
- * driving the cr50 uart TX at the same time as servo is driving those pins may
- * damage both servo and cr50.
- */
-PINMUX(GPIO(DETECT_AP_UART),    A3, DIO_INPUT)
-PINMUX(GPIO(DETECT_EC_UART),    B6, DIO_INPUT)
-PINMUX(GPIO(EC_TX_CR50_RX),     B6, DIO_INPUT)
-PINMUX(GPIO(EC_TX_CR50_RX_OUT), B6, DIO_INPUT)
-PINMUX(GPIO(DETECT_SERVO),      B5, DIO_INPUT)
-
-/*
- * I2CS pins are bi-directional and would be configured here as shown. However,
- * A1 is also used as a strapping option GPIO input which is configured
- * above. If a board is configured (via the strapping pins) to support the I2CS
- * interface, then the connection of A1 and A9 to/from the I2C0_SDA and I2C0_SCL
- * lines is done in the function i2cs_set_pinmux() which lives in board.c.
- *
- * PINMUX(FUNC(I2C0_SCL),        A9, DIO_INPUT)
- * PINMUX(FUNC(I2C0_SDA),        A1, DIO_INPUT)
-*/
-
-/*
- * Both SPI master and slave buses are wired directly to specific pads
- *
- * If CONFIG_SPS is defined, these pads are used:
- *   DIOA2  = SPS_MOSI  (input)
- *   DIOA6  = SPS_CLK   (input)
- *   DIOA10 = SPS_MISO  (output)
- *   DIOA12 = SPS_CS_L  (input)
- * The digital inputs are enabled in sps.c
- *
- * If CONFIG_SPI_MASTER is defined, these pads are used:
- *   DIOA4  = SPI_MOSI  (output)
- *   DIOA8  = SPI_CLK   (output)
- *   DIOA11 = SPI_MISO  (input)
- *   DIOA14 = SPI_CS_L  (output)
- * The pads are only connected to the peripheral outputs when SPI is enabled to
- * avoid interfering with other things on the board.
- * Note: Double-check to be sure these are configured in spi_master.c
- */
-PINMUX(GPIO(SPI_MOSI),           A4, DIO_OUTPUT)
-PINMUX(GPIO(SPI_CLK),            A8, DIO_OUTPUT)
-PINMUX(GPIO(SPI_CS_L),          A14, DIO_OUTPUT)
-
-PINMUX(GPIO(DIOB4),              B4, DIO_INPUT)
-
-
-#undef PINMUX
diff --git a/board/cr50/pinweaver_tpm_imports.c b/board/cr50/pinweaver_tpm_imports.c
deleted file mode 100644
index b7bef62aff..0000000000
--- a/board/cr50/pinweaver_tpm_imports.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <pinweaver_tpm_imports.h>
-
-#include <Global.h>
-#include <InternalRoutines.h>
-#include <dcrypto.h>
-#include <util.h>
-#include <console.h>
-
-void get_storage_seed(void *buf, size_t *len)
-{
-	*len = MIN(*len, sizeof(gp.SPSeed));
-	memcpy(buf, &gp.SPSeed, *len);
-}
-
-uint8_t get_current_pcr_digest(const uint8_t bitmask[2],
-			       uint8_t sha256_of_selected_pcr[32])
-{
-	TPM2B_DIGEST pcr_digest;
-	TPML_PCR_SELECTION selection;
-
-	selection.count = 1;
-	selection.pcrSelections[0].hash = TPM_ALG_SHA256;
-	selection.pcrSelections[0].sizeofSelect = PCR_SELECT_MIN;
-	memset(&selection.pcrSelections[0].pcrSelect, 0, PCR_SELECT_MIN);
-	memcpy(&selection.pcrSelections[0].pcrSelect, bitmask, 2);
-
-	PCRComputeCurrentDigest(TPM_ALG_SHA256, &selection, &pcr_digest);
-	if (memcmp(&selection.pcrSelections[0].pcrSelect, bitmask, 2) != 0)
-		return 1;
-
-	memcpy(sha256_of_selected_pcr, &pcr_digest.b.buffer, 32);
-	return 0;
-}
diff --git a/board/cr50/power_button.c b/board/cr50/power_button.c
deleted file mode 100644
index 5f46a4d0a6..0000000000
--- a/board/cr50/power_button.c
+++ /dev/null
@@ -1,163 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "console.h"
-#include "extension.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "physical_presence.h"
-#include "rbox.h"
-#include "registers.h"
-#include "system.h"
-#include "system_chip.h"
-#include "task.h"
-#include "timer.h"
-#include "u2f_impl.h"
-
-#define CPRINTS(format, args...) cprints(CC_RBOX, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_RBOX, format, ## args)
-
-DECLARE_DEFERRED(deassert_ec_rst);
-
-void power_button_release_enable_interrupt(int enable)
-{
-	/* Clear any leftover power button rising edge detection interrupts */
-	GWRITE_FIELD(RBOX, INT_STATE, INTR_PWRB_IN_RED, 1);
-
-	if (enable) {
-		/* Enable power button rising edge detection interrupt */
-		GWRITE_FIELD(RBOX, INT_ENABLE, INTR_PWRB_IN_RED, 1);
-		task_enable_irq(GC_IRQNUM_RBOX0_INTR_PWRB_IN_RED_INT);
-	} else {
-		GWRITE_FIELD(RBOX, INT_ENABLE, INTR_PWRB_IN_RED, 0);
-		task_disable_irq(GC_IRQNUM_RBOX0_INTR_PWRB_IN_RED_INT);
-	}
-}
-
-/**
- * Enable/disable power button interrupt.
- *
- * @param enable	Enable (!=0) or disable (==0)
- */
-static void power_button_press_enable_interrupt(int enable)
-{
-	if (enable) {
-		/* Clear any leftover power button interrupts */
-		GWRITE_FIELD(RBOX, INT_STATE, INTR_PWRB_IN_FED, 1);
-
-		/* Enable power button interrupt */
-		GWRITE_FIELD(RBOX, INT_ENABLE, INTR_PWRB_IN_FED, 1);
-		task_enable_irq(GC_IRQNUM_RBOX0_INTR_PWRB_IN_FED_INT);
-	} else {
-		GWRITE_FIELD(RBOX, INT_ENABLE, INTR_PWRB_IN_FED, 0);
-		task_disable_irq(GC_IRQNUM_RBOX0_INTR_PWRB_IN_FED_INT);
-	}
-}
-
-static void power_button_handler(void)
-{
-	CPRINTS("power button pressed");
-
-	if (physical_detect_press() != EC_SUCCESS) {
-		/* Not consumed by physical detect */
-#ifdef CONFIG_U2F
-		/* Track last power button press for U2F */
-		power_button_record();
-#endif
-	}
-
-	GWRITE_FIELD(RBOX, INT_STATE, INTR_PWRB_IN_FED, 1);
-}
-DECLARE_IRQ(GC_IRQNUM_RBOX0_INTR_PWRB_IN_FED_INT, power_button_handler, 1);
-
-static void power_button_release_handler(void)
-{
-#ifdef CR50_DEV
-	CPRINTS("power button released");
-#endif
-
-	/*
-	 * Let deassert_ec_rst be called deferred rather than
-	 * by interrupt handler.
-	 */
-	hook_call_deferred(&deassert_ec_rst_data, 0);
-
-	/* Note that this is for one-time use through the current power on. */
-	power_button_release_enable_interrupt(0);
-}
-DECLARE_IRQ(GC_IRQNUM_RBOX0_INTR_PWRB_IN_RED_INT, power_button_release_handler,
-	1);
-
-#ifdef CONFIG_U2F
-static void power_button_init(void)
-{
-	/*
-	 * Enable power button interrupts all the time for U2F.
-	 *
-	 * Ideally U2F should only enable physical presence after the start of
-	 * a U2F request (using atomic operations for the PP enable mask so it
-	 * plays nicely with CCD config), but that doesn't happen yet.
-	 */
-	power_button_press_enable_interrupt(1);
-}
-DECLARE_HOOK(HOOK_INIT, power_button_init, HOOK_PRIO_DEFAULT);
-#endif  /* CONFIG_U2F */
-
-void board_physical_presence_enable(int enable)
-{
-#ifndef CONFIG_U2F
-	/* Enable/disable power button interrupts */
-	power_button_press_enable_interrupt(enable);
-#endif
-
-	/* Stay awake while we're doing this, just in case. */
-	if (enable)
-		disable_sleep(SLEEP_MASK_PHYSICAL_PRESENCE);
-	else
-		enable_sleep(SLEEP_MASK_PHYSICAL_PRESENCE);
-}
-
-static int command_powerbtn(int argc, char **argv)
-{
-	ccprintf("powerbtn: %s\n",
-		 rbox_powerbtn_is_pressed() ? "pressed" : "released");
-
-#ifdef CR50_DEV
-	pop_check_presence(1);
-#endif
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(powerbtn, command_powerbtn, "",
-			"get the state of the power button");
-
-/*
- * Perform a user presence check using the power button.
- */
-static enum vendor_cmd_rc vc_get_pwr_btn(enum vendor_cmd_cc code,
-					 void *buf,
-					 size_t input_size,
-					 size_t *response_size)
-{
-	/*
-	 * The AP uses VENDOR_CC_GET_PWR_BTN to poll both for the press and
-	 * release of the power button.
-	 *
-	 * pop_check_presence(1) returns true if a new power button press was
-	 * recorded in the last 10 seconds.
-	 *
-	 * Indicate button release if no new presses have been recorded and the
-	 * current button state is not pressed.
-	 */
-	if (pop_check_presence(1) == POP_TOUCH_YES ||
-		rbox_powerbtn_is_pressed())
-		*(uint8_t *)buf = 1;
-	else
-		*(uint8_t *)buf = 0;
-	*response_size = 1;
-
-	return VENDOR_RC_SUCCESS;
-}
-DECLARE_VENDOR_COMMAND(VENDOR_CC_GET_PWR_BTN, vc_get_pwr_btn);
-
diff --git a/board/cr50/rdd.c b/board/cr50/rdd.c
deleted file mode 100644
index 9ce2970045..0000000000
--- a/board/cr50/rdd.c
+++ /dev/null
@@ -1,490 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "case_closed_debug.h"  /* For ccd_ext_is_enabled() */
-#include "ccd_config.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "rbox.h"
-#include "rdd.h"
-#include "registers.h"
-#include "system.h"
-#include "uart_bitbang.h"
-#include "uartn.h"
-#include "usb_api.h"
-#include "usb_console.h"
-#include "usb_i2c.h"
-#include "usb_spi.h"
-
-/* Include the dazzlingly complex macro to instantiate the USB SPI config */
-USB_SPI_CONFIG(ccd_usb_spi, USB_IFACE_SPI, USB_EP_SPI, 0);
-
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
-
-static enum device_state state = DEVICE_STATE_INIT;
-
-/* Flags for CCD blocking */
-enum ccd_block_flags {
-	/*
-	 * UARTs.  Disabling these can be helpful if the AP or EC is doing
-	 * something which creates an interrupt storm on these ports.
-	 */
-	CCD_BLOCK_AP_UART = BIT(0),
-	CCD_BLOCK_EC_UART = BIT(1),
-
-	/*
-	 * Any ports shared with servo.  Disabling these will stop CCD from
-	 * interfering with servo, in the case where both CCD and servo is
-	 * connected but servo isn't properly detected.
-	 */
-	CCD_BLOCK_SERVO_SHARED = BIT(2),
-
-	/*
-	 * In case of broken hardware use IGNORE_SERVO to bypass the "servo
-	 * connected check". If cr50 thinks servo is connected, it won't enable
-	 * the AP or EC uart. Using IGNORE_SERVO will force cr50 to enable uart
-	 * even if it thinks servo is connected.
-	 *
-	 * ONLY USE THIS IF SERVO IS DISCONNECTED. If you force enable AP and EC
-	 * uart while servo is connected, it could break the hardware and the
-	 * ccd uart could become permanently unusable.
-	 */
-	CCD_BLOCK_IGNORE_SERVO = BIT(3)
-};
-
-/* Which UARTs are blocked by console command */
-static uint8_t ccd_block;
-
-int ccd_ext_is_enabled(void)
-{
-	return state == DEVICE_STATE_CONNECTED;
-}
-
-/* If the UART TX is connected the pinmux select will have a non-zero value */
-int uart_tx_is_connected(int uart)
-{
-	if (uart == UART_AP)
-		return GREAD(PINMUX, DIOA7_SEL);
-
-	/*
-	 * Enabling bit bang programming mode disconnected the EC UART from
-	 * the external pin, but muxed DIOB5 to a different GPIO bit.
-	 */
-	return !uart_bitbang_is_enabled() && GREAD(PINMUX, DIOB5_SEL);
-}
-
-/**
- * Connect the UART pin to the given signal
- *
- * @param uart		the uart peripheral number
- * @param signal	the pinmux selector value for the gpio or peripheral
- *			function. 0 to disable the output.
- */
-static void uart_select_tx(int uart, int signal)
-{
-	if (uart == UART_AP) {
-		GWRITE(PINMUX, DIOA7_SEL, signal);
-	} else {
-		GWRITE(PINMUX, DIOB5_SEL, signal);
-
-		/* Remove the pulldown when we are driving the signal */
-		GWRITE_FIELD(PINMUX, DIOB5_CTL, PD, signal ? 0 : 1);
-	}
-}
-
-void uartn_tx_connect(int uart)
-{
-	/*
-	 * Don't drive TX unless the debug cable is connected (we have
-	 * something to transmit) and servo is disconnected (we won't be
-	 * drive-fighting with servo).
-	 */
-	if (servo_is_connected() || !ccd_ext_is_enabled())
-		return;
-
-	if (uart == UART_AP) {
-		if (!ccd_is_cap_enabled(CCD_CAP_GSC_TX_AP_RX))
-			return;
-
-		if (!ap_uart_is_on())
-			return;
-
-		uart_select_tx(UART_AP, GC_PINMUX_UART1_TX_SEL);
-	} else {
-		if (!ccd_is_cap_enabled(CCD_CAP_GSC_TX_EC_RX))
-			return;
-
-		if (!ec_is_on())
-			return;
-
-		uart_select_tx(UART_EC, GC_PINMUX_UART2_TX_SEL);
-	}
-}
-
-void uartn_tx_disconnect(int uart)
-{
-	/* Disconnect the TX pin from UART peripheral */
-	uart_select_tx(uart, 0);
-}
-
-/*
- * Flags for the current CCD device state.  This is used for determining what
- * hardware devices we've enabled now, and which we want enabled.
- */
-enum ccd_state_flag {
-	/* Flags for individual devices/ports */
-
-	/* AP UART is enabled.  RX-only, unless TX is also enabled. */
-	CCD_ENABLE_UART_AP		= BIT(0),
-
-	/* AP UART transmit is enabled.  Requires AP UART enabled. */
-	CCD_ENABLE_UART_AP_TX		= BIT(1),
-
-	/* EC UART is enabled.  RX-only, unless TX is also enabled. */
-	CCD_ENABLE_UART_EC		= BIT(2),
-
-	/* EC UART transmit is enabled.  Requires EC UART enabled. */
-	CCD_ENABLE_UART_EC_TX		= BIT(3),
-
-	/*
-	 * EC UART bit-banging is enabled.  Requires EC UART enabled, and
-	 * blocks EC UART transmit.
-	 */
-	CCD_ENABLE_UART_EC_BITBANG	= BIT(4),
-
-	/* I2C port is enabled */
-	CCD_ENABLE_I2C			= BIT(5),
-
-	/* SPI port is enabled for AP and/or EC flash */
-	CCD_ENABLE_SPI			= BIT(6),
-};
-
-int console_is_restricted(void)
-{
-	return !ccd_is_cap_enabled(CCD_CAP_GSC_RESTRICTED_CONSOLE);
-}
-
-/**
- * Return the currently enabled state flags (see enum ccd_state_flag).
- */
-static uint32_t get_state_flags(void)
-{
-	uint32_t flags_now = 0;
-
-	if (uartn_is_enabled(UART_AP))
-		flags_now |= CCD_ENABLE_UART_AP;
-	if (uart_tx_is_connected(UART_AP))
-		flags_now |= CCD_ENABLE_UART_AP_TX;
-	if (uartn_is_enabled(UART_EC))
-		flags_now |= CCD_ENABLE_UART_EC;
-	if (uart_tx_is_connected(UART_EC))
-		flags_now |= CCD_ENABLE_UART_EC_TX;
-
-#ifdef CONFIG_UART_BITBANG
-	if (uart_bitbang_is_enabled())
-		flags_now |= CCD_ENABLE_UART_EC_BITBANG;
-#endif
-
-	if (usb_i2c_board_is_enabled())
-		flags_now |= CCD_ENABLE_I2C;
-
-	if (ccd_usb_spi.state->enabled_device)
-		flags_now |= CCD_ENABLE_SPI;
-
-	return flags_now;
-}
-
-/**
- * Print the state flags to the specified output channel
- *
- * @param channel	Console channel
- * @param flags		Flags to print
- */
-static void print_state_flags(enum console_channel channel, uint32_t flags)
-{
-	if (flags & CCD_ENABLE_UART_AP)
-		cprintf(channel, " UARTAP");
-	if (flags & CCD_ENABLE_UART_AP_TX)
-		cprintf(channel, "+TX");
-	if (flags & CCD_ENABLE_UART_EC)
-		cprintf(channel, " UARTEC");
-	if (flags & CCD_ENABLE_UART_EC_TX)
-		cprintf(channel, "+TX");
-	if (flags & CCD_ENABLE_UART_EC_BITBANG)
-		cprintf(channel, "+BB");
-	if (flags & CCD_ENABLE_I2C)
-		cprintf(channel, " I2C");
-	if (flags & CCD_ENABLE_SPI)
-		cprintf(channel, " SPI");
-}
-
-static void ccd_state_change_hook(void)
-{
-	uint32_t flags_now;
-	uint32_t flags_want = 0;
-	uint32_t delta;
-
-	/* Check what's enabled now */
-	flags_now = get_state_flags();
-
-	/* Start out by figuring what flags we might want enabled */
-
-	/* Enable EC/AP UART RX if that device is on */
-	if (ap_uart_is_on())
-		flags_want |= CCD_ENABLE_UART_AP;
-	if (ec_is_rx_allowed())
-		flags_want |= CCD_ENABLE_UART_EC;
-
-#ifdef CONFIG_UART_BITBANG
-	if (uart_bitbang_is_wanted())
-		flags_want |= CCD_ENABLE_UART_EC_BITBANG;
-#endif
-
-	/*
-	 * External CCD will try to enable all the ports. If it's disabled,
-	 * disable all ports.
-	 */
-	if (ccd_ext_is_enabled())
-		flags_want |= (CCD_ENABLE_UART_AP_TX | CCD_ENABLE_UART_EC_TX |
-			       CCD_ENABLE_I2C | CCD_ENABLE_SPI);
-	else
-		flags_want = 0;
-
-	/* Then disable flags we can't have */
-
-	/* Servo takes over UART TX, I2C, and SPI. */
-	if (servo_is_connected() || (ccd_block & CCD_BLOCK_SERVO_SHARED))
-		flags_want &= ~(CCD_ENABLE_UART_AP_TX | CCD_ENABLE_UART_EC_TX |
-				CCD_ENABLE_UART_EC_BITBANG | CCD_ENABLE_I2C |
-				CCD_ENABLE_SPI);
-
-	/* Disable based on capabilities */
-	if (!ccd_is_cap_enabled(CCD_CAP_GSC_RX_AP_TX))
-		flags_want &= ~CCD_ENABLE_UART_AP;
-	if (!ccd_is_cap_enabled(CCD_CAP_GSC_TX_AP_RX))
-		flags_want &= ~CCD_ENABLE_UART_AP_TX;
-	if (!ccd_is_cap_enabled(CCD_CAP_GSC_RX_EC_TX))
-		flags_want &= ~CCD_ENABLE_UART_EC;
-	if (!ccd_is_cap_enabled(CCD_CAP_GSC_TX_EC_RX))
-		flags_want &= ~(CCD_ENABLE_UART_EC_TX |
-				CCD_ENABLE_UART_EC_BITBANG);
-	if (!ccd_is_cap_enabled(CCD_CAP_I2C))
-		flags_want &= ~CCD_ENABLE_I2C;
-
-	/*
-	 * EC and AP flash block on a per-packet basis, but if we don't have
-	 * access to either one, turn off SPI.
-	 */
-	if (!ccd_is_cap_enabled(CCD_CAP_AP_FLASH) &&
-	    !ccd_is_cap_enabled(CCD_CAP_EC_FLASH))
-		flags_want &= ~CCD_ENABLE_SPI;
-
-	/* EC UART TX blocked by bit-banging */
-	if (flags_want & CCD_ENABLE_UART_EC_BITBANG)
-		flags_want &= ~CCD_ENABLE_UART_EC_TX;
-
-	/* UARTs can be specifically blocked by console command */
-	if (ccd_block & CCD_BLOCK_AP_UART)
-		flags_want &= ~CCD_ENABLE_UART_AP;
-	if (ccd_block & CCD_BLOCK_EC_UART)
-		flags_want &= ~CCD_ENABLE_UART_EC;
-
-	/* UARTs are either RX-only or RX+TX, so no RX implies no TX */
-	if (!(flags_want & CCD_ENABLE_UART_AP))
-		flags_want &= ~CCD_ENABLE_UART_AP_TX;
-	if (!(flags_want & CCD_ENABLE_UART_EC))
-		flags_want &= ~CCD_ENABLE_UART_EC_TX;
-
-	/* If no change, we're done */
-	if (flags_now == flags_want)
-		return;
-
-	CPRINTF("[%pT CCD state:", PRINTF_TIMESTAMP_NOW);
-	print_state_flags(CC_USB, flags_want);
-	CPRINTF("]\n");
-
-	/* Handle turning things off */
-	delta = flags_now & ~flags_want;
-	if (delta & CCD_ENABLE_UART_AP)
-		uartn_disable(UART_AP);
-	if (delta & CCD_ENABLE_UART_AP_TX)
-		uartn_tx_disconnect(UART_AP);
-	if (delta & CCD_ENABLE_UART_EC)
-		uartn_disable(UART_EC);
-	if (delta & CCD_ENABLE_UART_EC_TX)
-		uartn_tx_disconnect(UART_EC);
-#ifdef CONFIG_UART_BITBANG
-	if (delta & CCD_ENABLE_UART_EC_BITBANG)
-		uart_bitbang_disable();
-#endif
-	if (delta & CCD_ENABLE_I2C)
-		usb_i2c_board_disable();
-	if (delta & CCD_ENABLE_SPI)
-		usb_spi_enable(&ccd_usb_spi, 0);
-
-	/* Handle turning things on */
-	delta = flags_want & ~flags_now;
-	if (delta & CCD_ENABLE_UART_AP)
-		uartn_enable(UART_AP);
-	if (delta & CCD_ENABLE_UART_AP_TX)
-		uartn_tx_connect(UART_AP);
-	if (delta & CCD_ENABLE_UART_EC)
-		uartn_enable(UART_EC);
-	if (delta & CCD_ENABLE_UART_EC_TX)
-		uartn_tx_connect(UART_EC);
-#ifdef CONFIG_UART_BITBANG
-	if (delta & CCD_ENABLE_UART_EC_BITBANG) {
-		/*
-		 * Servo detect interrupt will be re-enabled by the
-		 * servo_detect() poll once bit bang mode is disabled.
-		 */
-		gpio_disable_interrupt(GPIO_DETECT_SERVO);
-		uart_bitbang_enable();
-	}
-#endif
-	if (delta & CCD_ENABLE_I2C)
-		usb_i2c_board_enable();
-	if (delta & CCD_ENABLE_SPI)
-		usb_spi_enable(&ccd_usb_spi, 1);
-}
-DECLARE_DEFERRED(ccd_state_change_hook);
-
-void ccd_update_state(void)
-{
-	/*
-	 * Use a deferred call to serialize changes from CCD config, RDD
-	 * attach/detach, EC/AP startup or shutdown, etc.
-	 */
-	hook_call_deferred(&ccd_state_change_hook_data, 0);
-}
-
-/*****************************************************************************/
-
-static void ccd_ext_detect(void)
-{
-	/* The CCD mode pin is active low. */
-	int enable = !gpio_get_level(GPIO_CCD_MODE_L);
-
-	if (enable == ccd_ext_is_enabled())
-		return;
-
-	if (enable) {
-		/*
-		 * If we're not disconnected, release USB to ensure it's in a
-		 * good state before we usb_init().  This matches what
-		 * common/case_closed_debug.c does.
-		 *
-		 * Not sure exactly why this is necessary.  It could be because
-		 * that also has CCD_MODE_PARTIAL, and the only way to go
-		 * cleanly between ENABLED and PARTIAL is to disable things and
-		 * then re-enable only what's needed?
-		 *
-		 * TODO(rspangler): Figure out whether we can delete this.
-		 */
-		if (state != DEVICE_STATE_DISCONNECTED)
-			usb_release();
-
-		CPRINTS("CCD EXT enable");
-		state = DEVICE_STATE_CONNECTED;
-
-		usb_init();
-		usb_console_enable(1, 0);
-	} else {
-		CPRINTS("CCD EXT disable");
-		state = DEVICE_STATE_DISCONNECTED;
-
-		usb_release();
-		usb_console_enable(0, 0);
-	}
-
-	ccd_update_state();
-}
-DECLARE_HOOK(HOOK_SECOND, ccd_ext_detect, HOOK_PRIO_DEFAULT);
-
-static void print_ccd_ports_blocked(void)
-{
-	/* Regardless, print current state */
-	ccputs("CCD ports blocked:");
-	if (ccd_block & CCD_BLOCK_AP_UART)
-		ccputs(" AP");
-	if (ccd_block & CCD_BLOCK_EC_UART)
-		ccputs(" EC");
-	if (ccd_block & CCD_BLOCK_SERVO_SHARED)
-		ccputs(" SERVO");
-	if (ccd_block & CCD_BLOCK_IGNORE_SERVO) {
-		ccputs(" IGNORE_SERVO");
-		ccputs("\nWARNING: enabling UART while servo is connected may "
-		       "damage hardware");
-	}
-	if (!ccd_block)
-		ccputs(" (none)");
-	ccputs("\n");
-}
-
-static int command_ccd_state(int argc, char **argv)
-{
-	print_ap_state();
-	print_ap_uart_state();
-	print_ec_state();
-	print_rdd_state();
-	print_servo_state();
-
-	ccprintf("CCD EXT: %s\n",
-		 ccd_ext_is_enabled() ? "enabled" : "disabled");
-
-	ccprintf("State flags:");
-	print_state_flags(CC_COMMAND, get_state_flags());
-	ccprintf("\n");
-
-	print_ccd_ports_blocked();
-
-	return EC_SUCCESS;
-}
-DECLARE_SAFE_CONSOLE_COMMAND(ccdstate, command_ccd_state,
-			     "",
-			     "Print the case closed debug device state");
-
-static int command_ccd_block(int argc, char **argv)
-{
-	uint8_t block_flag = 0;
-	int new_state;
-
-	if (argc == 3) {
-		if (!strcasecmp(argv[1], "AP"))
-			block_flag = CCD_BLOCK_AP_UART;
-		else if (!strcasecmp(argv[1], "EC"))
-			block_flag = CCD_BLOCK_EC_UART;
-		else if (!strcasecmp(argv[1], "SERVO"))
-			block_flag = CCD_BLOCK_SERVO_SHARED;
-		else if (!strcasecmp(argv[1], "IGNORE_SERVO"))
-			block_flag = CCD_BLOCK_IGNORE_SERVO;
-		else
-			return EC_ERROR_PARAM1;
-
-		if (!parse_bool(argv[2], &new_state))
-			return EC_ERROR_PARAM2;
-
-		if (new_state)
-			ccd_block |= block_flag;
-		else
-			ccd_block &= ~block_flag;
-
-		if (block_flag == CCD_BLOCK_IGNORE_SERVO)
-			servo_ignore(new_state);
-
-		/* Update blocked state in deferred function */
-		ccd_update_state();
-	}
-
-	print_ccd_ports_blocked();
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(ccdblock, command_ccd_block,
-			"[<AP | EC | SERVO | IGNORE_SERVO> [BOOLEAN]]",
-			"Force CCD ports disabled");
diff --git a/board/cr50/recovery_button.c b/board/cr50/recovery_button.c
deleted file mode 100644
index 0a5702981f..0000000000
--- a/board/cr50/recovery_button.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Recovery button override module. */
-
-#include "common.h"
-#include "console.h"
-#include "extension.h"
-#include "registers.h"
-#include "system.h"
-#include "timer.h"
-#include "u2f_impl.h"
-#include "util.h"
-
-/*
- * The recovery button, on some systems only, is wired to KEY0 in rbox.  For
- * testing, we need to be able override the value.  We'll have a vendor command
- * such that the AP can query the state of the recovery button.  However, the
- * reported state can only be overridden with a console command given sufficient
- * privileges.
- */
-static uint8_t rec_btn_force_pressed;
-
-/*
- * Timestamp of the most recent recovery button press
- */
-static timestamp_t last_press;
-
-/* How long do we latch the last recovery button press */
-#define RECOVERY_BUTTON_TIMEOUT (10 * SECOND)
-
-void recovery_button_record(void)
-{
-	last_press = get_time();
-
-	/*
-	 * Pressing the power button causes the AP to shutdown, and typically
-	 * the Cr50 will enter deep sleep very quickly.  Delay deep sleep
-	 * so the recovery button state is saved long enough for the AP to
-	 * power on and read the recovery button state.
-	 */
-	delay_sleep_by(RECOVERY_BUTTON_TIMEOUT);
-}
-
-/*
- * Read the recovery button latched state and unconditionally clear the state.
- *
- * Returns 1 iff the recovery button key combination was recorded within the
- * last RECOVERY_BUTTON_TIMEOUT microseconds.  Note that deep sleep also
- * clears the recovery button state.
- */
-static int pop_recovery_button_state(void)
-{
-	int latched_state = 0;
-
-	if (last_press.val &&
-		((get_time().val - last_press.val) < RECOVERY_BUTTON_TIMEOUT))
-		latched_state = 1;
-
-	last_press.val = 0;
-
-	/* Latched recovery button state */
-	return latched_state;
-}
-
-static uint8_t is_rec_btn_pressed(void)
-{
-	if (rec_btn_force_pressed)
-		return 1;
-
-	/*
-	 * Platform has a defined recovery button combination and it
-	 * the combination was pressed within a timeout
-	 */
-	if (board_uses_closed_source_set1() && pop_recovery_button_state())
-		return 1;
-
-	/*
-	 * If not force pressed, check the actual state of button.  Note,
-	 * the value is inverted because the button is active low.
-	 */
-	return !GREAD_FIELD(RBOX, CHECK_INPUT, KEY0_IN);
-}
-
-static int command_recbtnforce(int argc, char **argv)
-{
-	int val;
-
-	if (argc > 2)
-		return EC_ERROR_PARAM_COUNT;
-
-	if (argc == 2) {
-		/* Make sure we're allowed to override the recovery button. */
-		if (console_is_restricted())
-			return EC_ERROR_ACCESS_DENIED;
-
-		if (!parse_bool(argv[1], &val))
-			return EC_ERROR_PARAM1;
-
-		rec_btn_force_pressed = val;
-	}
-
-	ccprintf("RecBtn: %s pressed\n",
-		 rec_btn_force_pressed ? "forced" :
-		 is_rec_btn_pressed() ? "" : "not");
-
-	return EC_SUCCESS;
-}
-DECLARE_SAFE_CONSOLE_COMMAND(recbtnforce, command_recbtnforce,
-			     "[enable | disable]",
-			     "Force enable the reported recbtn state.");
-
-static enum vendor_cmd_rc vc_get_rec_btn(enum vendor_cmd_cc code,
-					 void *buf,
-					 size_t input_size,
-					 size_t *response_size)
-{
-	*(uint8_t *)buf = is_rec_btn_pressed();
-	*response_size = 1;
-
-	ccprints("%s: state=%d", __func__, *(uint8_t *)buf);
-
-	return VENDOR_RC_SUCCESS;
-}
-DECLARE_VENDOR_COMMAND(VENDOR_CC_GET_REC_BTN, vc_get_rec_btn);
diff --git a/board/cr50/recovery_button.h b/board/cr50/recovery_button.h
deleted file mode 100644
index 4a237a776a..0000000000
--- a/board/cr50/recovery_button.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright 2019 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __EC_BOARD_CR50_RECOVERY_BUTTON_H
-#define __EC_BOARD_CR50_RECOVERY_BUTTON_H
-
-/**
- * Latch a recovery button sequence.  This state is latched for
- * RECOVERY_BUTTON_TIMEOUT or until the AP requests the recovery button
- * state.
- */
-void recovery_button_record(void);
-
-#endif  /* ! __EC_BOARD_CR50_RECOVERY_BUTTON_H */
diff --git a/board/cr50/rma_key_blob.README.md b/board/cr50/rma_key_blob.README.md
deleted file mode 100644
index 66fa0c04da..0000000000
--- a/board/cr50/rma_key_blob.README.md
+++ /dev/null
@@ -1,7 +0,0 @@
-The rma_key_blob.{p256,x25519}.{prod,test} files in this directory are binary
-blobs concatenating the respective public key used by prod or test RMA server
-and single byte of the key ID. The key size for p256 is 65 bytes, for x25519 -
-32 bytes.
-
-The util/bin2h.sh script is used to convert these binary blobs into .h
-file containing a #define statement which is suitable for use in C.
diff --git a/board/cr50/rma_key_blob.p256.prod b/board/cr50/rma_key_blob.p256.prod
deleted file mode 100644
index 519a98506a..0000000000
--- a/board/cr50/rma_key_blob.p256.prod
+++ /dev/null
@@ -1 +0,0 @@
-V¡ÏCdôÄä­S]²SŸïÈò]#ÔìßRr†EFóèe,ý5�éî�¢¥Ñ5l„̼v­(N�’ûD

\ No newline at end of file
diff --git a/board/cr50/rma_key_blob.p256.test b/board/cr50/rma_key_blob.p256.test
deleted file mode 100644
index 0e5cba1a6c..0000000000
--- a/board/cr50/rma_key_blob.p256.test
+++ /dev/null
diff --git a/board/cr50/rma_key_blob.x25519.prod b/board/cr50/rma_key_blob.x25519.prod
deleted file mode 100644
index 54e8fd5a1d..0000000000
--- a/board/cr50/rma_key_blob.x25519.prod
+++ /dev/null
diff --git a/board/cr50/rma_key_blob.x25519.test b/board/cr50/rma_key_blob.x25519.test
deleted file mode 100644
index c8b0062e64..0000000000
--- a/board/cr50/rma_key_blob.x25519.test
+++ /dev/null
@@ -1 +0,0 @@
-®-,#às
Ó·’¬TÅý~œð¨ë~*µÛôy_Š(?
\ No newline at end of file
diff --git a/board/cr50/scratch_reg1.h b/board/cr50/scratch_reg1.h
deleted file mode 100644
index 79eb4b4382..0000000000
--- a/board/cr50/scratch_reg1.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __EC_BOARD_CR50_SCRATCH_REG1_H
-#define __EC_BOARD_CR50_SCRATCH_REG1_H
-
-/*
- * Bit assignments of the LONG_LIFE_SCRATCH1 register. This register survives
- * all kinds of resets, it is cleared only on the Power ON event.
- */
-#define BOARD_SLAVE_CONFIG_SPI       BIT(0)   /* TPM uses SPI interface */
-#define BOARD_SLAVE_CONFIG_I2C       BIT(1)   /* TPM uses I2C interface */
-
-/*
- * The gaps are left to ensure backwards compatibility with the earliest cr50
- * code releases. It will be possible to safely reuse these gaps if and when the
- * rest of the bits are taken.
- */
-
-/* TODO(crosbug.com/p/56945): Remove when sys_rst_l has an external pullup */
-#define BOARD_NEEDS_SYS_RST_PULL_UP  BIT(5)   /* Add a pullup to sys_rst_l */
-#define BOARD_USE_PLT_RESET          BIT(6)   /* Use plt_rst_l instead of */
-						/* sys_rst_l to monitor the */
-						/* system resets */
-
-/* Bits to store write protect bit state across deep sleep and resets. */
-#define BOARD_WP_ASSERTED            BIT(8)
-#define BOARD_FORCING_WP             BIT(9)
-
-/*
- * Bit to signal to compatible RO to suppress its uart output.
- * Helps to reduce time to resume from deep sleep.
- */
-#define BOARD_NO_RO_UART             BIT(10)
-
-/*
- * Bits to store current case-closed debug state across deep sleep.
- *
- * DO NOT examine these bits to determine the current CCD state.  Call methods
- * from case_closed_debug.h instead.
- */
-#define BOARD_CCD_SHIFT              11
-#define BOARD_CCD_STATE              (3 << BOARD_CCD_SHIFT)
-
-/* Prevent Cr50 from entering deep sleep when the AP is off */
-#define BOARD_DEEP_SLEEP_DISABLED    BIT(13)
-/* Use Cr50_RX_AP_TX to determine if the AP is off or on */
-#define BOARD_DETECT_AP_WITH_UART    BIT(14)
-
-/* ITE EC sync sequence generation after reset is required. */
-#define BOARD_ITE_EC_SYNC_NEEDED     BIT(15)
-
-/*
- * Enable delayed write protect disable for systems that can be opened
- * in less than 2 minutes
- */
-#define BOARD_WP_DISABLE_DELAY       BIT(16)
-/*
- * Enable custom options required for the closed source EC on the
- * Sarien/Arcada boards.  Includes the following behavior
- *    Enable factory mode to closed-source EC via GPIO
- *    Support customer diagnostic mode
- *    UEFI factory mode
- *    EC extended reset
- *    Power+Refresh recovery mode (instead of Power+Refresh+Esc)
- */
-#define BOARD_CLOSED_SOURCE_SET1     BIT(17)
-
-/*
- * Wait until PLT_RST_L is asserted before deasserting reset.
- */
-#define BOARD_CLOSED_LOOP_RESET      BIT(18)
-
-/*
- * The board uses INA pins as GPIOs, so it can't support reading inas using usb
- * i2c.
- */
-#define BOARD_NO_INA_SUPPORT             BIT(19)
-
-/*
- * The board allows commands to stop TPM (Wilco, Campfire, etc.)
- */
-#define BOARD_ALLOW_CHANGE_TPM_MODE       BIT(20)
-
-/*
- * Macro to capture all properties related to board strapping pins. This must be
- * updated if additional strap related properties are added.
- */
-#define BOARD_ALL_PROPERTIES ( \
-	BOARD_ALLOW_CHANGE_TPM_MODE | \
-	BOARD_CLOSED_LOOP_RESET | \
-	BOARD_CLOSED_SOURCE_SET1 | \
-	BOARD_DEEP_SLEEP_DISABLED | \
-	BOARD_DETECT_AP_WITH_UART | \
-	BOARD_NEEDS_SYS_RST_PULL_UP | \
-	BOARD_NO_INA_SUPPORT | \
-	BOARD_SLAVE_CONFIG_I2C | \
-	BOARD_SLAVE_CONFIG_SPI | \
-	BOARD_USE_PLT_RESET | \
-	BOARD_WP_DISABLE_DELAY)
-
-#endif  /* ! __EC_BOARD_CR50_SCRATCH_REG1_H */
diff --git a/board/cr50/servo_state.c b/board/cr50/servo_state.c
deleted file mode 100644
index f6ded01dd0..0000000000
--- a/board/cr50/servo_state.c
+++ /dev/null
@@ -1,233 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Servo state machine.
- */
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "uart_bitbang.h"
-#include "uartn.h"
-#include "usb_i2c.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-
-static enum device_state state = DEVICE_STATE_INIT;
-
-void print_servo_state(void)
-{
-	ccprintf("Servo:   %s\n", device_state_name(state));
-}
-
-int servo_is_connected(void)
-{
-	/*
-	 * If we're connected, we definitely know we are.  If we're debouncing,
-	 * then we were connected and might still be.  If we haven't
-	 * initialized yet, we'd bettter assume we're connected until we prove
-	 * otherwise.  In any of these cases, it's not safe to allow ports to
-	 * be connected because that would block detecting servo.
-	 */
-	return (state == DEVICE_STATE_CONNECTED ||
-		state == DEVICE_STATE_DEBOUNCING ||
-		state == DEVICE_STATE_INIT ||
-		state == DEVICE_STATE_INIT_DEBOUNCING);
-}
-
-/**
- * Set the servo state.
- *
- * Done as a function to make it easier to debug state transitions.  Note that
- * this ONLY sets the state (and possibly prints debug info), and doesn't do
- * all the additional transition work that servo_disconnect(), etc. do.
- *
- * @param new_state	State to set.
- */
-static void set_state(enum device_state new_state)
-{
-#ifdef CR50_DEBUG_SERVO_STATE
-	/* Print all state transitions.  May spam the console. */
-	if (state != new_state)
-		CPRINTS("Servo %s -> %s",
-			device_state_name(state), device_state_name(new_state));
-#endif
-	state = new_state;
-}
-
-/**
- * Check if we can tell servo is connected.
- *
- * @return 1 if we can tell if servo is connected, 0 if we can't tell.
- */
-static int servo_detectable(void)
-{
-	/*
-	 * If we are driving the UART transmit line to the EC, then we can't
-	 * check to see if servo is also doing so.
-	 *
-	 * We also need to check if we're bit-banging the EC UART, because in
-	 * that case, the UART transmit line is directly controlled as a GPIO
-	 * and can be high even if UART TX is disconnected.
-	 */
-	return !(uart_tx_is_connected(UART_EC) || uart_bitbang_is_enabled());
-}
-
-/**
- * Handle servo being disconnected
- */
-static void servo_disconnect(void)
-{
-	if (!servo_is_connected())
-		return;
-
-	CPRINTS("Servo disconnect");
-	set_state(DEVICE_STATE_DISCONNECTED);
-	ccd_update_state();
-}
-
-/**
- * Handle servo being connected.
- *
- * This can be called directly by servo_detect(), or as a deferred function.
- * Both are in the HOOK task, so can't preempt each other.
- */
-static void servo_connect(void)
-{
-	/*
-	 * If we were debouncing disconnect, go back to connected.  We never
-	 * finished disconnecting, so nothing else is necessary.
-	 */
-	if (state == DEVICE_STATE_DEBOUNCING)
-		set_state(DEVICE_STATE_CONNECTED);
-
-	/* If we're already connected, nothing else needs to be done */
-	if (state == DEVICE_STATE_CONNECTED)
-		return;
-
-	/*
-	 * If we're still here, this is a real transition from a disconnected
-	 * state, so we need to configure ports.
-	 */
-	CPRINTS("Servo connect");
-	set_state(DEVICE_STATE_CONNECTED);
-	ccd_update_state();
-}
-DECLARE_DEFERRED(servo_connect);
-
-void servo_ignore(int enable)
-{
-	if (enable) {
-		/*
-		 * Set servo state to IGNORE, so servo presence wont prevent
-		 * cr50 from enabling EC and AP uart.
-		 */
-		set_state(DEVICE_STATE_IGNORED);
-		ccd_update_state();
-	} else {
-		/*
-		 * To be on the safe side 'connect' servo when we stop ignoring
-		 * the servo state. If servo is disconnected, then cr50 will
-		 * notice within 1 second and reenable ccd.
-		 */
-		servo_connect();
-	}
-}
-
-/**
- * Servo state machine
- */
-static void servo_detect(void)
-{
-	/* Disable interrupts if we had them on for debouncing */
-	gpio_disable_interrupt(GPIO_DETECT_SERVO);
-
-	if (state == DEVICE_STATE_IGNORED)
-		return;
-
-	/* If we're driving EC UART TX, we can't detect servo */
-	if (!servo_detectable()) {
-		/* We're driving one port; might as well drive them all */
-		servo_disconnect();
-
-		set_state(DEVICE_STATE_UNDETECTABLE);
-		return;
-	}
-
-	/* Handle detecting servo */
-	if (gpio_get_level(GPIO_DETECT_SERVO)) {
-		servo_connect();
-		return;
-	}
-	/*
-	 * If servo has become detectable but wasn't detected above, assume
-	 * it's disconnected.
-	 *
-	 * We know we were driving EC UART TX, so we want to give priority to
-	 * our ability to drive it again.  If we went to the debouncing state
-	 * here, then we'd need to wait a second before we could drive it.
-	 *
-	 * This is similar to how if servo was driving EC UART TX, we go to the
-	 * debouncing state below, because we want to give priority to servo
-	 * being able to drive it again.
-	 */
-	if (state == DEVICE_STATE_UNDETECTABLE) {
-		set_state(DEVICE_STATE_DISCONNECTED);
-		return;
-	}
-	/*
-	 * Make sure the interrupt is enabled. We will need to detect the on
-	 * transition if we enter the off or debouncing state
-	 */
-	gpio_enable_interrupt(GPIO_DETECT_SERVO);
-
-	/* Servo wasn't detected.  If we're already disconnected, done. */
-	if (state == DEVICE_STATE_DISCONNECTED)
-		return;
-
-	/* If we were debouncing, we're now sure we're disconnected */
-	if (state == DEVICE_STATE_DEBOUNCING ||
-	    state == DEVICE_STATE_INIT_DEBOUNCING) {
-		servo_disconnect();
-		return;
-	}
-
-	/*
-	 * Otherwise, we were connected or initializing, and we're not sure if
-	 * we're now disconnected or just sending a 0-bit.  So start
-	 * debouncing.
-	 *
-	 * During debouncing, servo_is_connected() will still return true, so
-	 * that if both CCD and servo cables are connected, we won't start
-	 * driving EC UART TX and become unable to determine the servo connect
-	 * state.
-	 */
-	if (state == DEVICE_STATE_INIT)
-		set_state(DEVICE_STATE_INIT_DEBOUNCING);
-	else
-		set_state(DEVICE_STATE_DEBOUNCING);
-}
-/*
- * Do this at slightly elevated priority so it runs before rdd_check_pin() and
- * ec_detect().  This increases the odds that we'll detect servo before
- * detecting the EC.  If ec_detect() ran first, it could turn on TX to the EC
- * UART before we had a chance to detect servo.  This is still a little bit of
- * a race condition.
- */
-DECLARE_HOOK(HOOK_SECOND, servo_detect, HOOK_PRIO_DEFAULT - 1);
-
-/**
- * Interrupt handler for servo detect asserted
- */
-void servo_detect_asserted(enum gpio_signal signal)
-{
-	gpio_disable_interrupt(GPIO_DETECT_SERVO);
-
-	/*
-	 * If this interrupt is because servo is actually detectable (vs. we're
-	 * driving the detect pin now), queue a transition back to connected.
-	 */
-	if (servo_detectable())
-		hook_call_deferred(&servo_connect_data, 0);
-}
diff --git a/board/cr50/tpm2/NVMem.c b/board/cr50/tpm2/NVMem.c
deleted file mode 100644
index e1a14b4536..0000000000
--- a/board/cr50/tpm2/NVMem.c
+++ /dev/null
@@ -1,190 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * The function prototypes were extracted from the TCG Published
- * Trusted Platform Module Library
- * Part 4: Supporting Routines
- * Family "2.0"
- * Level 00 Revision 01.16
- * October 30, 2014
- */
-
-#include <string.h>
-
-#include "Platform.h"
-#include "PlatformData.h"
-#include "TpmError.h"
-#include "assert.h"
-#include "nvmem.h"
-
-/* Local state */
-static struct {
-	BOOL s_NvIsAvailable;
-	BOOL s_NV_unrecoverable;
-	BOOL s_NV_recoverable;
-} local_state  __attribute__((section(".bss.Tpm2_common")));
-/*
- * This function is used by the simulator to set the error flags in the NV
- * subsystem to simulate an error in the NV loading process.
- */
-void _plat__NvErrors(BOOL recoverable, BOOL unrecoverable)
-{
-	local_state.s_NV_unrecoverable = unrecoverable;
-	local_state.s_NV_recoverable = recoverable;
-}
-
-/*
- * This function should retrieve and verify the integrity of the saved context.
- * On success, the NV content has been copied into local RAM for fast access.
- *
- * The recovery from an integrity failure depends on where the error occurred.
- * It it was in the state that is discarded by TPM Reset, then the error is
- * recoverable if the TPM is reset. Otherwise, the TPM must go into failure
- * mode.
- *
- *     Return Value                      Meaning
- *
- *     0                                 if success
- *     >0                                if receive recoverable error
- *     <0                                if unrecoverable error
- */
-int _plat__NVEnable(void *platParameter)
-{
-	local_state.s_NV_unrecoverable = FALSE;
-	local_state.s_NV_recoverable = FALSE;
-
-	/* TODO: Need to define what is recoverable and unrecoverable
-	 * conditions with regards to NvMem module. For now, the only
-	 * requirement is that at Cr50 board initialization time, the
-	 * nvmem_init() function either detects a valid partition, or
-	 * determines that NvMem is fully erased and configures  a valid
-	 * partition. Setting both variables TRUE if NvMem is not available
-	 */
-	local_state.s_NV_recoverable = nvmem_get_error_state() != 0;
-	local_state.s_NV_unrecoverable = local_state.s_NV_recoverable;
-
-	if (local_state.s_NV_unrecoverable)
-		return -1;
-	return local_state.s_NV_recoverable;
-}
-
-void _plat__NVDisable(void)
-{
-	/* nothing yet */
-}
-
-/*
- * Check if NV is available
- *
- *      Return Value                      Meaning
- *
- *      0                                 NV is available
- *      1                                 NV not available due to write failure
- *      2                                 NV not available due to rate limit
- */
-int _plat__IsNvAvailable(void)
-{
-
-	int rv;
-
-	/*
-	 * sNv_IsAvailable is a state variable that can be accesed by the
-	 * simmulator to control access to NvMemory. This variable and
-	 * the on chip NvMem area must be in the correct state for NvMem
-	 * to be in 'NV is available' state.
-	 */
-	rv = !local_state.s_NvIsAvailable || nvmem_get_error_state();
-	return rv;
-}
-
-/*
- * Read a chunk of NV memory
- */
-void _plat__NvMemoryRead(unsigned int startOffset,
-				    unsigned int size,
-				    void *data)
-{
-	if (_plat__NvOffsetIsVirtual(startOffset)) {
-		_plat__NvVirtualMemoryRead(startOffset, size, data);
-		return;
-	}
-
-	assert(startOffset + size <= NV_MEMORY_SIZE);
-	/* Copy the data from the NV image */
-	nvmem_read(startOffset, size, data, NVMEM_TPM);
-	return;
-}
-
-/*
- * This function tests to see if the NV is different from the test value.
- * Returns true if different, false if not.
- */
-BOOL
-_plat__NvIsDifferent(unsigned int startOffset,
-		     unsigned int size,
-		     void *data)
-{
-	return (nvmem_is_different(startOffset, size, data, NVMEM_TPM) != 0);
-}
-
-/*
- * This function is used to update NV memory. The write is to a memory copy of
- * NV. At the end of the current command, any changes are written to the actual
- * NV memory.
- */
-void _plat__NvMemoryWrite(unsigned int startOffset,
-			  unsigned int size,
-			  void *data)
-{
-	assert(startOffset + size <= NV_MEMORY_SIZE);
-	/* Copy the data to the NV image */
-	nvmem_write(startOffset, size, data, NVMEM_TPM);
-}
-
-/*
- *      Function: Move a chunk of NV memory from source to destination,
- *      handling overlap correctly.
- */
-void _plat__NvMemoryMove(unsigned int sourceOffset,
-				    unsigned int destOffset,
-				    unsigned int size)
-{
-	assert(sourceOffset + size <= NV_MEMORY_SIZE);
-	assert(destOffset + size <= NV_MEMORY_SIZE);
-	nvmem_move(sourceOffset, destOffset, size, NVMEM_TPM);
-	return;
-}
-
-/*
- * Commit the local RAM copy to NV storage.
- *
- *      Return Value                      Meaning
- *
- *      0                                 NV write success
- *      non-0                             NV write fail
- */
-int _plat__NvCommit(void)
-{
-	return nvmem_commit();
-}
-
-/*
- * Set the current NV state to available. This function is for testing purpose
- * only. It is not part of the platform NV logic
- */
-void _plat__SetNvAvail(void)
-{
-	local_state.s_NvIsAvailable = TRUE;
-	return;
-}
-
-/*
- * Set the current NV state to unavailable. This function is for testing
- * purpose only. It is not part of the platform NV logic
- */
-void _plat__ClearNvAvail(void)
-{
-	local_state.s_NvIsAvailable = FALSE;
-	return;
-}
diff --git a/board/cr50/tpm2/aes.c b/board/cr50/tpm2/aes.c
deleted file mode 100644
index 5fe431222a..0000000000
--- a/board/cr50/tpm2/aes.c
+++ /dev/null
@@ -1,540 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "CryptoEngine.h"
-#include "dcrypto.h"
-
-#include <assert.h>
-
-static CRYPT_RESULT _cpri__AESBlock(
-	uint8_t *out, uint32_t len, uint8_t *in);
-
-
-CRYPT_RESULT _cpri__AESDecryptCBC(
-	uint8_t *out, uint32_t num_bits, uint8_t *key, uint8_t *iv,
-	uint32_t len, uint8_t *in)
-{
-	CRYPT_RESULT result;
-
-	if (len == 0)
-		return CRYPT_SUCCESS;
-	assert(key != NULL && iv != NULL && in != NULL && out != NULL);
-	assert(len <= INT32_MAX);
-	if (!DCRYPTO_aes_init(key, num_bits, iv, CIPHER_MODE_CBC, DECRYPT_MODE))
-		return CRYPT_PARAMETER;
-
-	result = _cpri__AESBlock(out, len, in);
-	if (result != CRYPT_SUCCESS)
-		return result;
-
-	DCRYPTO_aes_read_iv(iv);
-	return CRYPT_SUCCESS;
-}
-
-CRYPT_RESULT _cpri__AESDecryptCFB(uint8_t *out, uint32_t num_bits,
-				uint8_t *key, uint8_t *iv, uint32_t len,
-				uint8_t *in)
-{
-	if (len == 0)
-		return CRYPT_SUCCESS;
-	assert(key != NULL && iv != NULL && out != NULL && in != NULL);
-
-	/* Initialize AES hardware. */
-	if (!DCRYPTO_aes_init(key, num_bits, NULL,
-				CIPHER_MODE_ECB, ENCRYPT_MODE))
-		return CRYPT_PARAMETER;
-
-	while (len > 0) {
-		int i;
-		size_t chunk_len;
-		uint8_t mask[16];
-
-		chunk_len = MIN(len, 16);
-
-		DCRYPTO_aes_block(iv, mask);
-
-		memcpy(iv, in, chunk_len);
-		if (chunk_len != 16)
-			memset(iv + chunk_len, 0, 16 - chunk_len);
-
-		for (i = 0; i < chunk_len; i++)
-			*out++ = *in++ ^ mask[i];
-		len -= chunk_len;
-	}
-
-	return CRYPT_SUCCESS;
-}
-
-CRYPT_RESULT _cpri__AESDecryptECB(
-	uint8_t *out, uint32_t num_bits, uint8_t *key, uint32_t len,
-	uint8_t *in)
-{
-	assert(key != NULL);
-	/* Initialize AES hardware. */
-	if (!DCRYPTO_aes_init(key, num_bits, NULL,
-				CIPHER_MODE_ECB, DECRYPT_MODE))
-		return CRYPT_PARAMETER;
-	return _cpri__AESBlock(out, len, in);
-}
-
-static CRYPT_RESULT _cpri__AESBlock(
-	uint8_t *out, uint32_t len, uint8_t *in)
-{
-	int32_t slen;
-
-	assert(out != NULL && in != NULL && len > 0 && len <= INT32_MAX);
-	slen = (int32_t) len;
-	if ((slen % 16) != 0)
-		return CRYPT_PARAMETER;
-
-	for (; slen > 0; slen -= 16) {
-		DCRYPTO_aes_block(in, out);
-		in = &in[16];
-		out = &out[16];
-	}
-	return CRYPT_SUCCESS;
-}
-
-CRYPT_RESULT _cpri__AESEncryptCBC(
-	uint8_t *out, uint32_t num_bits, uint8_t *key, uint8_t *iv,
-	uint32_t len, uint8_t *in)
-{
-	CRYPT_RESULT result;
-
-	assert(key != NULL && iv != NULL);
-	if (!DCRYPTO_aes_init(key, num_bits, iv, CIPHER_MODE_CBC, ENCRYPT_MODE))
-		return CRYPT_PARAMETER;
-
-	result = _cpri__AESBlock(out, len, in);
-	if (result != CRYPT_SUCCESS)
-		return result;
-
-	DCRYPTO_aes_read_iv(iv);
-	return CRYPT_SUCCESS;
-}
-
-CRYPT_RESULT _cpri__AESEncryptCFB(
-	uint8_t *out, uint32_t num_bits, uint8_t *key, uint8_t *iv,
-	uint32_t len, uint8_t *in)
-{
-	if (len == 0)
-		return CRYPT_SUCCESS;
-
-	assert(out != NULL && key != NULL && iv != NULL && in != NULL);
-	assert(len <= INT32_MAX);
-	if (!DCRYPTO_aes_init(key, num_bits, iv, CIPHER_MODE_CTR, ENCRYPT_MODE))
-		return CRYPT_PARAMETER;
-
-	for (; len >= 16; len -= 16, in += 16, out += 16) {
-		DCRYPTO_aes_block(in, out);
-		DCRYPTO_aes_write_iv(out);
-	}
-	if (len > 0) {
-		uint8_t buf[16];
-
-		memcpy(buf, in, len);
-		memset(buf+len, 0, 16-len);
-		DCRYPTO_aes_block(buf, buf);
-		memcpy(out, buf, len);
-		memcpy(iv, buf, len);
-		memset(iv+len, 0, 16-len);
-	} else {
-		memcpy(iv, out-16, 16);
-	}
-	return CRYPT_SUCCESS;
-}
-
-CRYPT_RESULT _cpri__AESEncryptCTR(
-	uint8_t *out, uint32_t num_bits, uint8_t *key, uint8_t *iv,
-	uint32_t len, uint8_t *in)
-{
-	if (len == 0)
-		return CRYPT_SUCCESS;
-
-	assert(out != NULL && key != NULL && iv != NULL && in != NULL);
-	assert(len <= INT32_MAX);
-
-	if (!DCRYPTO_aes_ctr(out, key, num_bits, iv, in, len))
-		return CRYPT_PARAMETER;
-	else
-		return CRYPT_SUCCESS;
-}
-
-CRYPT_RESULT _cpri__AESEncryptECB(
-	uint8_t *out, uint32_t num_bits, uint8_t *key, uint32_t len,
-	uint8_t *in)
-{
-	assert(key != NULL);
-	/* Initialize AES hardware. */
-	if (!DCRYPTO_aes_init(key, num_bits, NULL,
-			      CIPHER_MODE_ECB, ENCRYPT_MODE))
-		return CRYPT_PARAMETER;
-	return _cpri__AESBlock(out, len, in);
-}
-
-CRYPT_RESULT _cpri__AESEncryptOFB(
-	uint8_t *out, uint32_t num_bits, uint8_t *key, uint8_t *iv,
-	uint32_t len, uint8_t *in)
-{
-	uint8_t *ivp;
-	int32_t slen;
-	int i;
-
-	if (len == 0)
-		return CRYPT_SUCCESS;
-
-	assert(out != NULL && key != NULL && iv != NULL && in != NULL);
-	assert(len <= INT32_MAX);
-	slen = (int32_t) len;
-	/* Initialize AES hardware. */
-	if (!DCRYPTO_aes_init(key, num_bits, NULL,
-				CIPHER_MODE_ECB, ENCRYPT_MODE))
-		return CRYPT_PARAMETER;
-
-	for (; slen > 0; slen -= 16) {
-		DCRYPTO_aes_block(iv, iv);
-		ivp = iv;
-		for (i = (slen < 16) ? slen : 16; i > 0; i--)
-			*out++ = (*ivp++ ^ *in++);
-	}
-	return CRYPT_SUCCESS;
-}
-
-#ifdef CRYPTO_TEST_SETUP
-
-#include "console.h"
-#include "extension.h"
-#include "hooks.h"
-#include "uart.h"
-
-enum aes_test_cipher_mode {
-	TEST_MODE_ECB = 0,
-	TEST_MODE_CTR = 1,
-	TEST_MODE_CBC = 2,
-	TEST_MODE_GCM = 3,
-	TEST_MODE_OFB = 4,
-	TEST_MODE_CFB = 5,
-};
-
-#define CPRINTF(format, args...) cprintf(CC_EXTENSION, format, ## args)
-
-static void aes_command_handler(void *cmd_body,
-				size_t cmd_size,
-				size_t *response_size)
-{
-	uint8_t *key;
-	uint16_t key_len;
-	uint8_t iv_len;
-	uint8_t *iv;
-	uint8_t aad_len;
-	const uint8_t *aad;
-	enum aes_test_cipher_mode c_mode;
-	enum encrypt_mode e_mode;
-	uint8_t *cmd = (uint8_t *)cmd_body;
-	int16_t data_len;
-	unsigned max_data_len = *response_size;
-	unsigned actual_cmd_size;
-
-	/* Copy inputs into a local unaligned buffer, so as to ensure
-	 * that api's are memory-alignment agnostic.
-	 */
-	struct unaligned_buf {
-		uint8_t unused;
-		uint8_t b[255];
-	} __packed;
-
-	struct unaligned_buf out_local;
-	struct unaligned_buf iv_local;
-	struct unaligned_buf key_local;
-	struct unaligned_buf data_local;
-
-	*response_size = 0;
-
-	/*
-	 * Command structure, shared out of band with the test driver running
-	 * on the host:
-	 *
-	 * field       |    size  |              note
-	 * ================================================================
-	 * mode        |    1     | 0 - decrypt, 1 - encrypt
-	 * cipher_mode |    1     | as per aes_test_cipher_mode
-	 * key_len     |    1     | key size in bytes (16, 24 or 32)
-	 * key         | key len  | key to use
-	 * iv_len      |    1     | either 0 or 16
-	 * iv          | 0 or 16  | as defined by iv_len
-	 * aad_len     |  <= 127  | additional authentication data length
-	 * aad         |  aad_len | additional authentication data
-	 * text_len    |    2     | size of the text to process, big endian
-	 * text        | text_len | text to encrypt/decrypt
-	 */
-	e_mode = *cmd++;
-	c_mode = *cmd++;
-	key_len = *cmd++;
-
-	if ((key_len != 16) && (key_len != 24) && (key_len != 32)) {
-		CPRINTF("Invalid key len %d\n", key_len * 8);
-		return;
-	}
-	key = cmd;
-	cmd += key_len;
-	key_len *= 8;
-	iv_len = *cmd++;
-	if ((c_mode == TEST_MODE_GCM && iv_len == 0) ||
-		(c_mode != TEST_MODE_GCM && iv_len && iv_len != 16)) {
-		CPRINTF("Invalid vector len %d\n", iv_len);
-		return;
-	}
-	iv = cmd;
-	cmd += iv_len;
-	aad_len = *cmd++;
-	aad = cmd;
-	cmd += aad_len;
-	data_len = *cmd++;
-	data_len = data_len * 256 + *cmd++;
-
-	/*
-	 * We know that the receive buffer is at least this big, i.e. all the
-	 * preceding fields are guaranteed to fit.
-	 *
-	 * Now is a good time to verify overall sanity of the received
-	 * payload: does the actual size match the added up sizes of the
-	 * pieces.
-	 */
-	actual_cmd_size = cmd - (const uint8_t *)cmd_body + data_len;
-	if (actual_cmd_size != cmd_size) {
-		CPRINTF("Command size mismatch: %d != %d (data len %d)\n",
-			actual_cmd_size, cmd_size, data_len);
-		return;
-	}
-
-	if (((data_len + 15) & ~15) > max_data_len) {
-		CPRINTF("Response buffer too small\n");
-		return;
-	}
-
-	if (data_len > sizeof(out_local.b)) {
-		CPRINTF("Response buffer too small\n");
-		return;
-	}
-
-	memset(out_local.b, 'A', sizeof(out_local.b));
-	memcpy(iv_local.b, iv, iv_len);
-	memcpy(key_local.b, key, key_len / 8);
-	memcpy(data_local.b, cmd, data_len);
-
-	switch (c_mode) {
-	case TEST_MODE_ECB:
-		if (e_mode == 0) {
-			if (_cpri__AESDecryptECB(
-					out_local.b, key_len, key_local.b,
-					data_len, data_local.b) ==
-			    CRYPT_SUCCESS) {
-				*response_size = data_len;
-			}
-			CPRINTF("%s:%d response size %d\n",
-				__func__, __LINE__, *response_size);
-		} else if (e_mode == 1) {
-			/* pad input data to integer block size. */
-			while (data_len & 15)
-				data_local.b[data_len++] = 0;
-			if (_cpri__AESEncryptECB(
-					out_local.b, key_len, key_local.b,
-					data_len, data_local.b) ==
-			    CRYPT_SUCCESS) {
-				*response_size = data_len;
-			}
-			CPRINTF("%s:%d response size %d\n",
-				__func__, __LINE__, *response_size);
-		}
-		break;
-	case TEST_MODE_CTR:
-		if (e_mode == 0) {
-			if (_cpri__AESDecryptCTR(
-					out_local.b, key_len, key_local.b,
-					iv_local.b, data_len, data_local.b) ==
-			    CRYPT_SUCCESS) {
-				*response_size = data_len;
-			}
-			CPRINTF("%s:%d response size %d\n",
-				__func__, __LINE__, *response_size);
-		} else if (e_mode == 1) {
-			/* pad input data to integer block size. */
-			while (data_len & 15)
-				data_local.b[data_len++] = 0;
-			if (_cpri__AESEncryptCTR(
-					out_local.b, key_len, key_local.b,
-					iv_local.b, data_len, data_local.b) ==
-			    CRYPT_SUCCESS) {
-				*response_size = data_len;
-			}
-			CPRINTF("%s:%d response size %d\n",
-				__func__, __LINE__, *response_size);
-		}
-		break;
-	case TEST_MODE_CBC:
-	{
-		if (e_mode == 0) {
-			if (_cpri__AESDecryptCBC(
-					out_local.b, key_len, key_local.b,
-					iv_local.b, data_len, data_local.b) ==
-				CRYPT_SUCCESS) {
-				*response_size = data_len;
-			}
-			CPRINTF("%s:%d response size %d\n",
-				__func__, __LINE__, *response_size);
-		} else if (e_mode == 1) {
-			if (_cpri__AESEncryptCBC(
-					out_local.b, key_len, key_local.b,
-					iv_local.b, data_len, data_local.b) ==
-			    CRYPT_SUCCESS) {
-				*response_size = data_len;
-			}
-			CPRINTF("%s:%d response size %d\n",
-				__func__, __LINE__, *response_size);
-		}
-		break;
-	}
-	case TEST_MODE_GCM:
-	{
-		if (e_mode == 0) {
-			size_t total;
-			size_t count;
-			struct GCM_CTX ctx;
-
-			DCRYPTO_gcm_init(&ctx, key_len, key_local.b,
-				iv_local.b, iv_len);
-			DCRYPTO_gcm_aad(&ctx, aad, aad_len);
-			count = DCRYPTO_gcm_decrypt(
-				&ctx, out_local.b, sizeof(out_local.b),
-				data_local.b, data_len);
-			if (count < 0) {
-				CPRINTF(
-					"%s: gcm decrypt failed\n", __func__);
-				break;
-			}
-			total = count;
-			count = DCRYPTO_gcm_decrypt_final(
-				&ctx, out_local.b + total,
-				sizeof(out_local.b) - total);
-			if (count < 0) {
-				CPRINTF(
-					"%s: gcm decrypt_final failed\n",
-					__func__);
-				break;
-			}
-			total += count;
-			count = DCRYPTO_gcm_tag(&ctx, out_local.b + total,
-						sizeof(out_local.b) - total);
-			if (count == 0) {
-				CPRINTF("%s: gcm tag failed\n", __func__);
-				break;
-			}
-			total += count;
-			*response_size = total;
-		} else if (e_mode == 1) {
-			size_t total;
-			size_t count;
-			struct GCM_CTX ctx;
-
-			DCRYPTO_gcm_init(&ctx, key_len, key_local.b,
-				iv_local.b, iv_len);
-			DCRYPTO_gcm_aad(&ctx, aad, aad_len);
-			count = DCRYPTO_gcm_encrypt(
-				&ctx, out_local.b, sizeof(out_local.b),
-				data_local.b, data_len);
-			if (count < 0) {
-				CPRINTF("%s: gcm encrypt failed\n", __func__);
-				break;
-			}
-			total = count;
-			count = DCRYPTO_gcm_encrypt_final(
-				&ctx, out_local.b + total,
-				sizeof(out_local.b) - total);
-			if (count < 0) {
-				CPRINTF(
-					"%s: gcm encrypt_final failed\n",
-					__func__);
-				break;
-			}
-			total += count;
-			count = DCRYPTO_gcm_tag(
-				&ctx, out_local.b + total,
-				sizeof(out_local.b) - total);
-			if (count == 0) {
-				CPRINTF("%s: gcm tag failed\n", __func__);
-				break;
-			}
-			total += count;
-			*response_size = total;
-		}
-		break;
-	}
-	case TEST_MODE_OFB:
-		if (e_mode == 0) {
-			if (_cpri__AESDecryptOFB(
-					out_local.b, key_len, key_local.b,
-					iv_local.b, data_len, data_local.b) ==
-			    CRYPT_SUCCESS) {
-				*response_size = data_len;
-			}
-			CPRINTF("%s:%d response size %d\n",
-				__func__, __LINE__, *response_size);
-		} else if (e_mode == 1) {
-			if (_cpri__AESEncryptOFB(
-					out_local.b, key_len, key_local.b,
-					iv_local.b, data_len, data_local.b) ==
-			    CRYPT_SUCCESS) {
-				*response_size = data_len;
-			}
-			CPRINTF("%s:%d response size %d\n",
-				__func__, __LINE__, *response_size);
-		}
-		break;
-	case TEST_MODE_CFB:
-	{
-		if (e_mode == 0) {
-			if (_cpri__AESDecryptCFB(
-					out_local.b, key_len, key_local.b,
-					iv_local.b, data_len, data_local.b) ==
-			    CRYPT_SUCCESS) {
-				*response_size = data_len;
-			}
-			CPRINTF("%s:%d response size %d\n",
-				__func__, __LINE__, *response_size);
-		} else if (e_mode == 1) {
-			if (_cpri__AESEncryptCFB(
-					out_local.b, key_len, key_local.b,
-					iv_local.b, data_len, data_local.b) ==
-			    CRYPT_SUCCESS) {
-				*response_size = data_len;
-			}
-			CPRINTF("%s:%d response size %d\n",
-				__func__, __LINE__, *response_size);
-		}
-		break;
-	}
-	default:
-		break;
-	}
-
-	if (*response_size > 0) {
-		int i;
-
-		for (i = *response_size; i < sizeof(out_local.b); i++) {
-			if (out_local.b[i] != 'A') {
-				CPRINTF(
-					"%s:%d output overwrite at offset %d\n",
-					__func__, __LINE__, i);
-				*response_size = 0;
-			}
-		}
-
-		memcpy(cmd_body, out_local.b, *response_size);
-	}
-}
-
-DECLARE_EXTENSION_COMMAND(EXTENSION_AES, aes_command_handler);
-
-#endif   /* CRYPTO_TEST_SETUP */
diff --git a/board/cr50/tpm2/ecc.c b/board/cr50/tpm2/ecc.c
deleted file mode 100644
index 3aea411487..0000000000
--- a/board/cr50/tpm2/ecc.c
+++ /dev/null
@@ -1,618 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/*
- * TODO(ngm): only the NIST-P256 curve is currently supported.
- */
-
-#include "CryptoEngine.h"
-#include "TPMB.h"
-
-#include "trng.h"
-#include "util.h"
-#include "dcrypto.h"
-
-#include "cryptoc/p256.h"
-#include "cryptoc/p256_ecdsa.h"
-#include "cryptoc/util.h"
-
-static void reverse_tpm2b(TPM2B *b)
-{
-	reverse(b->buffer, b->size);
-}
-
-TPM2B_BYTE_VALUE(4);
-TPM2B_BYTE_VALUE(32);
-
-static int check_p256_param(const TPM2B_ECC_PARAMETER *a)
-{
-	return a->b.size == sizeof(p256_int);
-}
-
-static int check_p256_point(const TPMS_ECC_POINT *a)
-{
-	return check_p256_param(&a->x) &&
-		check_p256_param(&a->y);
-}
-
-BOOL _cpri__EccIsPointOnCurve(TPM_ECC_CURVE curve_id, TPMS_ECC_POINT *q)
-{
-	int result;
-
-	switch (curve_id) {
-	case TPM_ECC_NIST_P256:
-		if (!check_p256_point(q))
-			return FALSE;
-
-		reverse_tpm2b(&q->x.b);
-		reverse_tpm2b(&q->y.b);
-
-		result = dcrypto_p256_is_valid_point((p256_int *) q->x.b.buffer,
-					(p256_int *) q->y.b.buffer);
-
-		reverse_tpm2b(&q->x.b);
-		reverse_tpm2b(&q->y.b);
-
-		if (result)
-			return TRUE;
-		else
-			return FALSE;
-	default:
-		return FALSE;
-	}
-}
-
-/* out = n1*G, or out = n2*in */
-CRYPT_RESULT _cpri__EccPointMultiply(
-	TPMS_ECC_POINT *out, TPM_ECC_CURVE curve_id,
-	TPM2B_ECC_PARAMETER *n1, TPMS_ECC_POINT *in, TPM2B_ECC_PARAMETER *n2)
-{
-	int result;
-
-	switch (curve_id) {
-	case TPM_ECC_NIST_P256:
-		if ((n1 != NULL && n2 != NULL) ||
-			(n1 == NULL && n2 == NULL))
-			/* Only one of n1 or n2 must be specified. */
-			return CRYPT_PARAMETER;
-		if ((n2 != NULL && in == NULL) ||
-			(n2 == NULL && in != NULL))
-			return CRYPT_PARAMETER;
-		if (n1 != NULL && !check_p256_param(n1))
-			return CRYPT_PARAMETER;
-		if (in != NULL &&
-			(!check_p256_point(in) ||
-				!_cpri__EccIsPointOnCurve(curve_id, in)))
-			return CRYPT_POINT;
-		if (n2 != NULL && !check_p256_param(n2))
-			return CRYPT_PARAMETER;
-
-		if (n1 != NULL) {
-			reverse_tpm2b(&n1->b);
-
-			result = DCRYPTO_p256_base_point_mul(
-				(p256_int *) out->x.b.buffer,
-				(p256_int *) out->y.b.buffer,
-				(p256_int *) n1->b.buffer);
-
-			reverse_tpm2b(&n1->b);
-		} else {
-			reverse_tpm2b(&n2->b);
-			reverse_tpm2b(&in->x.b);
-			reverse_tpm2b(&in->y.b);
-
-			result = DCRYPTO_p256_point_mul(
-				(p256_int *) out->x.b.buffer,
-				(p256_int *) out->y.b.buffer,
-				(p256_int *) n2->b.buffer,
-				(p256_int *) in->x.b.buffer,
-				(p256_int *) in->y.b.buffer);
-
-			reverse_tpm2b(&n2->b);
-			reverse_tpm2b(&in->x.b);
-			reverse_tpm2b(&in->y.b);
-		}
-
-		if (result) {
-			out->x.b.size = sizeof(p256_int);
-			out->y.b.size = sizeof(p256_int);
-			reverse_tpm2b(&out->x.b);
-			reverse_tpm2b(&out->y.b);
-
-			return CRYPT_SUCCESS;
-		} else {
-			return CRYPT_NO_RESULT;
-		}
-	default:
-		return CRYPT_PARAMETER;
-	}
-}
-
-/* The name field of TPM2B_NAME is a TPMT_HA */
-static const uint8_t TPM2_ECC_EK_NAME_TEMPLATE[] = {
-	/* TPM_ALG_SHA256 in big endian. */
-	0x00, 0x0b,
-	/* SHA256 digest of the default template TPMT_PUBLIC. */
-	0x0f, 0x12, 0x77, 0xa2, 0xf3, 0xf3, 0x82, 0xe7,
-	0xf7, 0x5d, 0xb4, 0x66, 0xfa, 0xc2, 0x34, 0x18,
-	0x2a, 0x8d, 0x62, 0xf9, 0x7d, 0xfb, 0xaa, 0xe7,
-	0xb0, 0x6f, 0xdf, 0x52, 0xbd, 0xa5, 0x14, 0x67
-};
-BUILD_ASSERT(sizeof(TPM2_ECC_EK_NAME_TEMPLATE) == 2 + SHA256_DIGEST_SIZE);
-
-/* The first 4 bytes of the wrong template used in factory
- * c2e0319340fb48f102539ea98363f81e2d306e918dd778abf05473a2a60dae09
- */
-static const TPM2B_4_BYTE_VALUE TPM2_ECC_EK_NAME_CR50 = {
-	.t = {
-		.size = 4,
-		.buffer = {
-			0xc2, 0xe0, 0x31, 0x93
-		},
-	}
-};
-
-/* Key generation based on FIPS-186.4 section B.1.2 (Key Generation by
- * Testing Candidates) */
-CRYPT_RESULT _cpri__GenerateKeyEcc(
-	TPMS_ECC_POINT *q, TPM2B_ECC_PARAMETER *d,
-	TPM_ECC_CURVE curve_id,	TPM_ALG_ID hash_alg,
-	TPM2B *seed, const char *label,	TPM2B *extra, UINT32 *counter)
-{
-	TPM2B_4_BYTE_VALUE marshaled_counter = { .t = {4} };
-	TPM2B_32_BYTE_VALUE local_seed = { .t = {32} };
-	TPM2B *local_extra;
-	uint32_t count = 0;
-	uint8_t key_bytes[P256_NBYTES];
-	LITE_HMAC_CTX hmac;
-
-	if (curve_id != TPM_ECC_NIST_P256)
-		return CRYPT_PARAMETER;
-
-	/* extra may be empty, but seed must be specified. */
-	if (seed == NULL || seed->size < PRIMARY_SEED_SIZE)
-		return CRYPT_PARAMETER;
-
-	if (counter != NULL)
-		count = *counter;
-	if (count == 0)
-		count++;
-
-	/* Hash down the primary seed for ECC key generation, so that
-	 * the derivation tree is distinct from RSA key derivation. */
-	DCRYPTO_HMAC_SHA256_init(&hmac, seed->buffer, seed->size);
-	HASH_update(&hmac.hash, "ECC", 4);
-	memcpy(local_seed.t.buffer, DCRYPTO_HMAC_final(&hmac),
-	       local_seed.t.size);
-	always_memset(&hmac, 0, sizeof(hmac));
-	/* b/35576109: the personalize code uses only the first 4 bytes
-	 * of extra.
-	 */
-	if (extra && extra->size == sizeof(TPM2_ECC_EK_NAME_TEMPLATE) &&
-		memcmp(extra->buffer,
-		       TPM2_ECC_EK_NAME_TEMPLATE,
-		       sizeof(TPM2_ECC_EK_NAME_TEMPLATE)) == 0) {
-		local_extra = (TPM2B *) &TPM2_ECC_EK_NAME_CR50.b;
-	} else {
-		local_extra = extra;
-	}
-
-	for (; count != 0; count++) {
-		memcpy(marshaled_counter.t.buffer, &count, sizeof(count));
-		_cpri__KDFa(hash_alg, &local_seed.b, label, local_extra,
-			&marshaled_counter.b, sizeof(key_bytes) * 8, key_bytes,
-			NULL, FALSE);
-		if (DCRYPTO_p256_key_from_bytes(
-				(p256_int *) q->x.b.buffer,
-				(p256_int *) q->y.b.buffer,
-				(p256_int *) d->b.buffer, key_bytes)) {
-			q->x.b.size = sizeof(p256_int);
-			q->y.b.size = sizeof(p256_int);
-			reverse_tpm2b(&q->x.b);
-			reverse_tpm2b(&q->y.b);
-
-			d->b.size = sizeof(p256_int);
-			reverse_tpm2b(&d->b);
-
-			break;
-		}
-	}
-
-	always_memset(local_seed.t.buffer, 0, local_seed.t.size);
-	always_memset(key_bytes, 0, sizeof(key_bytes));
-
-	if (count == 0)
-		FAIL(FATAL_ERROR_INTERNAL);
-	if (counter != NULL)
-		*counter = count;
-
-	return CRYPT_SUCCESS;
-}
-
-CRYPT_RESULT _cpri__SignEcc(
-	TPM2B_ECC_PARAMETER *r, TPM2B_ECC_PARAMETER *s,
-	TPM_ALG_ID scheme, TPM_ALG_ID hash_alg, TPM_ECC_CURVE curve_id,
-	TPM2B_ECC_PARAMETER *d, TPM2B *digest, TPM2B_ECC_PARAMETER *k)
-{
-	uint8_t digest_local[sizeof(p256_int)];
-	const size_t digest_len = MIN(digest->size, sizeof(digest_local));
-	p256_int p256_digest;
-	int result;
-	struct drbg_ctx drbg;
-
-	if (curve_id != TPM_ECC_NIST_P256)
-		return CRYPT_PARAMETER;
-
-	switch (scheme) {
-	case TPM_ALG_ECDSA:
-		if (!check_p256_param(d))
-			return CRYPT_PARAMETER;
-		/* Trucate / zero-pad the digest as appropriate. */
-		memset(digest_local, 0, sizeof(digest_local));
-		memcpy(digest_local + sizeof(digest_local) - digest_len,
-			digest->buffer, digest_len);
-		p256_from_bin(digest_local, &p256_digest);
-
-		reverse_tpm2b(&d->b);
-
-		hmac_drbg_init_rand(&drbg, 512);
-		result = dcrypto_p256_ecdsa_sign(&drbg,
-				(p256_int *) d->b.buffer,
-				&p256_digest,
-				(p256_int *) r->b.buffer,
-				(p256_int *) s->b.buffer);
-		reverse_tpm2b(&d->b);
-
-		r->b.size = sizeof(p256_int);
-		s->b.size = sizeof(p256_int);
-		reverse_tpm2b(&r->b);
-		reverse_tpm2b(&s->b);
-
-		if (result)
-			return CRYPT_SUCCESS;
-		else
-			return CRYPT_FAIL;
-	default:
-		return CRYPT_PARAMETER;
-	}
-}
-
-CRYPT_RESULT _cpri__ValidateSignatureEcc(
-	TPM2B_ECC_PARAMETER *r,	TPM2B_ECC_PARAMETER *s,
-	TPM_ALG_ID scheme, TPM_ALG_ID hash_alg,
-	TPM_ECC_CURVE curve_id,	TPMS_ECC_POINT *q, TPM2B *digest)
-{
-	uint8_t digest_local[sizeof(p256_int)];
-	const size_t digest_len = MIN(digest->size, sizeof(digest_local));
-	p256_int p256_digest;
-	int result;
-
-	if (curve_id != TPM_ECC_NIST_P256)
-		return CRYPT_PARAMETER;
-
-	switch (scheme) {
-	case TPM_ALG_ECDSA:
-		/* Trucate / zero-pad the digest as appropriate. */
-		memset(digest_local, 0, sizeof(digest_local));
-		memcpy(digest_local + sizeof(digest_local) - digest_len,
-			digest->buffer, digest_len);
-		p256_from_bin(digest_local, &p256_digest);
-
-		reverse_tpm2b(&q->x.b);
-		reverse_tpm2b(&q->y.b);
-
-		reverse_tpm2b(&r->b);
-		reverse_tpm2b(&s->b);
-
-		result = dcrypto_p256_ecdsa_verify(
-			(p256_int *) q->x.b.buffer,
-			(p256_int *) q->y.b.buffer,
-			&p256_digest,
-			(p256_int *) r->b.buffer,
-			(p256_int *) s->b.buffer);
-
-		reverse_tpm2b(&q->x.b);
-		reverse_tpm2b(&q->y.b);
-
-		reverse_tpm2b(&r->b);
-		reverse_tpm2b(&s->b);
-
-		if (result)
-			return CRYPT_SUCCESS;
-		else
-			return CRYPT_FAIL;
-	default:
-		return CRYPT_PARAMETER;
-	}
-}
-
-CRYPT_RESULT _cpri__GetEphemeralEcc(TPMS_ECC_POINT *q, TPM2B_ECC_PARAMETER *d,
-				TPM_ECC_CURVE curve_id)
-{
-	int result;
-	uint8_t key_bytes[P256_NBYTES] __aligned(4);
-
-	if (curve_id != TPM_ECC_NIST_P256)
-		return CRYPT_PARAMETER;
-
-	rand_bytes(key_bytes, sizeof(key_bytes));
-
-	result = DCRYPTO_p256_key_from_bytes((p256_int *) q->x.b.buffer,
-					(p256_int *) q->y.b.buffer,
-					(p256_int *) d->b.buffer,
-					key_bytes);
-	always_memset(key_bytes, 0, sizeof(key_bytes));
-
-	if (result) {
-		q->x.b.size = sizeof(p256_int);
-		q->y.b.size = sizeof(p256_int);
-		reverse_tpm2b(&q->x.b);
-		reverse_tpm2b(&q->y.b);
-
-		d->b.size = sizeof(p256_int);
-		reverse_tpm2b(&d->b);
-
-		return CRYPT_SUCCESS;
-	} else {
-		return CRYPT_FAIL;
-	}
-}
-
-#ifdef CRYPTO_TEST_SETUP
-
-#include "extension.h"
-
-enum {
-	TEST_SIGN = 0,
-	TEST_VERIFY = 1,
-	TEST_KEYGEN = 2,
-	TEST_KEYDERIVE = 3
-};
-
-struct TPM2B_ECC_PARAMETER_aligned {
-	uint16_t pad;
-	TPM2B_ECC_PARAMETER d;
-} __packed __aligned(4);
-
-struct TPM2B_MAX_BUFFER_aligned {
-	uint16_t pad;
-	TPM2B_MAX_BUFFER d;
-} __packed __aligned(4);
-
-static const struct TPM2B_ECC_PARAMETER_aligned NIST_P256_d = {
-	.d = {
-		.t = {32, {
-				0xfc, 0x44, 0x1e, 0x07, 0x74, 0x4e, 0x48, 0xf1,
-				0x09, 0xb7, 0xe6, 0x6b, 0x29, 0x48, 0x2f, 0x7b,
-				0x7e, 0x3e, 0xc9, 0x1f, 0xa2, 0x7f, 0xd4, 0x87,
-				0x09, 0x91, 0xb2, 0x89, 0xfe, 0xa0, 0xd2, 0x0a
-			}
-		}
-	}
-};
-
-static const struct TPM2B_ECC_PARAMETER_aligned NIST_P256_qx = {
-	.d = {
-		.t = {32, {
-				0x12, 0xc3, 0xd6, 0xa2, 0x67, 0x9c, 0xa8, 0xee,
-				0x3c, 0x4d, 0x92, 0x7f, 0x20, 0x4e, 0xd5, 0xbc,
-				0xb4, 0x57, 0x7a, 0x04, 0xb0, 0xac, 0x02, 0xb2,
-				0xa3, 0x6a, 0xb3, 0xe9, 0xe1, 0x07, 0x81, 0xde
-			}
-		}
-	}
-};
-
-static const struct TPM2B_ECC_PARAMETER_aligned NIST_P256_qy = {
-	.d = {
-		.t = {32, {
-				0x5c, 0x85, 0xad, 0x74, 0x13, 0x97, 0x11, 0x72,
-				0xfc, 0xa5, 0x73, 0x8f, 0xee, 0x9d, 0x0e, 0x7b,
-				0xc5, 0x9f, 0xfd, 0x8a, 0x62, 0x6d, 0x68, 0x9b,
-				0xc6, 0xcc, 0xa4, 0xb5, 0x86, 0x65, 0x52, 0x1d
-			}
-		}
-	}
-};
-
-#define MAX_MSG_BYTES MAX_DIGEST_BUFFER
-
-static int point_equals(const TPMS_ECC_POINT *a, const TPMS_ECC_POINT *b)
-{
-	int diff = 0;
-
-	diff = a->x.b.size != b->x.b.size;
-	diff |= a->y.b.size != b->y.b.size;
-	if (!diff) {
-		diff |= !DCRYPTO_equals(
-			a->x.b.buffer, b->x.b.buffer, a->x.b.size);
-		diff |= !DCRYPTO_equals(
-			a->y.b.buffer, b->y.b.buffer, a->y.b.size);
-	}
-
-	return !diff;
-}
-
-static void ecc_command_handler(void *cmd_body, size_t cmd_size,
-			size_t *response_size_out)
-{
-	uint8_t *cmd;
-	uint8_t op;
-	uint8_t curve_id;
-	uint8_t sign_mode;
-	uint8_t hashing;
-	uint16_t in_len;
-	uint8_t in[MAX_MSG_BYTES];
-	uint16_t digest_len;
-	struct TPM2B_MAX_BUFFER_aligned digest;
-	uint8_t *out = (uint8_t *) cmd_body;
-	uint32_t *response_size = (uint32_t *) response_size_out;
-
-	TPMS_ECC_POINT q;
-	TPM2B_ECC_PARAMETER d;
-	struct TPM2B_ECC_PARAMETER_aligned r;
-	struct TPM2B_ECC_PARAMETER_aligned s;
-
-	/* Command format.
-	 *
-	 *   OFFSET       FIELD
-	 *   0            OP
-	 *   1            CURVE_ID
-	 *   2            SIGN_MODE
-	 *   3            HASHING
-	 *   4            MSB IN LEN
-	 *   5            LSB IN LEN
-	 *   6            IN
-	 *   6 + IN_LEN   MSB DIGEST LEN
-	 *   7 + IN_LEN   LSB DIGEST LEN
-	 *   8 + IN_LEN   DIGEST
-	 */
-
-	cmd = (uint8_t *) cmd_body;
-	op = *cmd++;
-	curve_id = *cmd++;
-	sign_mode = *cmd++;
-	hashing = *cmd++;
-	in_len = ((uint16_t) (cmd[0] << 8)) | cmd[1];
-	cmd += 2;
-	if (in_len > sizeof(in)) {
-		*response_size = 0;
-		return;
-	}
-	memcpy(in, cmd, in_len);
-	cmd += in_len;
-
-	digest_len = ((uint16_t) (cmd[0] << 8)) | cmd[1];
-	cmd += 2;
-	if (digest_len > sizeof(digest.d.t.buffer)) {
-		*response_size = 0;
-		return;
-	}
-	digest.d.t.size = digest_len;
-	memcpy(digest.d.t.buffer, cmd, digest_len);
-	cmd += digest_len;
-
-	/* Make copies of d, and q, as const data is immutable. */
-	switch (curve_id) {
-	case TPM_ECC_NIST_P256:
-		d = NIST_P256_d.d;
-		q.x = NIST_P256_qx.d;
-		q.y = NIST_P256_qy.d;
-		break;
-	default:
-		*response_size = 0;
-		return;
-	}
-
-	switch (op) {
-	case TEST_SIGN:
-		if (_cpri__SignEcc(&r.d, &s.d, sign_mode, hashing,
-					curve_id, &d, &digest.d.b, NULL)
-			!= CRYPT_SUCCESS) {
-			*response_size = 0;
-			return;
-		}
-		memcpy(out, r.d.b.buffer, r.d.b.size);
-		out += r.d.b.size;
-		memcpy(out, s.d.b.buffer, s.d.b.size);
-		*response_size = r.d.b.size + s.d.b.size;
-		break;
-	case TEST_VERIFY:
-		r.d.b.size = in_len / 2;
-		memcpy(r.d.b.buffer, in, r.d.b.size);
-		s.d.b.size = in_len / 2;
-		memcpy(s.d.b.buffer, in + r.d.b.size, s.d.b.size);
-		if (_cpri__ValidateSignatureEcc(
-				&r.d, &s.d, sign_mode, hashing, curve_id,
-				&q, &digest.d.b) != CRYPT_SUCCESS) {
-			*response_size = 0;
-		} else {
-			*out = 1;
-			*response_size = 1;
-		}
-		return;
-	case TEST_KEYGEN:
-	{
-		struct TPM2B_ECC_PARAMETER_aligned d_local;
-		TPMS_ECC_POINT q_local;
-
-		if (_cpri__GetEphemeralEcc(&q, &d_local.d, curve_id)
-			!= CRYPT_SUCCESS) {
-			*response_size = 0;
-			return;
-		}
-
-		if (_cpri__EccIsPointOnCurve(curve_id, &q) != TRUE) {
-			*response_size = 0;
-			return;
-		}
-
-		/* Verify correspondence of secret with the public point. */
-		if (_cpri__EccPointMultiply(
-				&q_local, curve_id, &d_local.d,
-				NULL, NULL) != CRYPT_SUCCESS) {
-			*response_size = 0;
-			return;
-		}
-		if (!point_equals(&q, &q_local)) {
-			*response_size = 0;
-			return;
-		}
-		*out = 1;
-		*response_size = 1;
-		return;
-	}
-	case TEST_KEYDERIVE:
-	{
-		/* Random seed. */
-		TPM2B_SEED seed;
-		struct TPM2B_ECC_PARAMETER_aligned d_local;
-		TPMS_ECC_POINT q_local;
-		const char *label = "ecc_test";
-
-
-		if (in_len > PRIMARY_SEED_SIZE) {
-			*response_size = 0;
-			return;
-		}
-		seed.t.size = in_len;
-		memcpy(seed.t.buffer, in, in_len);
-
-		if (_cpri__GenerateKeyEcc(
-				&q, &d_local.d, curve_id, hashing,
-				&seed.b, label, NULL, NULL) != CRYPT_SUCCESS) {
-			*response_size = 0;
-			return;
-		}
-
-		if (_cpri__EccIsPointOnCurve(curve_id, &q) != TRUE) {
-			*response_size = 0;
-			return;
-		}
-
-		/* Verify correspondence of secret with the public point. */
-		if (_cpri__EccPointMultiply(
-				&q_local, curve_id, &d_local.d,
-				NULL, NULL) != CRYPT_SUCCESS) {
-			*response_size = 0;
-			return;
-		}
-		if (!point_equals(&q, &q_local)) {
-			*response_size = 0;
-			return;
-		}
-
-		*out = 1;
-		*response_size = 1;
-		return;
-	}
-	default:
-		*response_size = 0;
-		return;
-	}
-}
-
-DECLARE_EXTENSION_COMMAND(EXTENSION_ECC, ecc_command_handler);
-
-#endif   /* CRYPTO_TEST_SETUP */
diff --git a/board/cr50/tpm2/ecies.c b/board/cr50/tpm2/ecies.c
deleted file mode 100644
index 6f89d79396..0000000000
--- a/board/cr50/tpm2/ecies.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "dcrypto.h"
-
-#ifdef CRYPTO_TEST_SETUP
-
-#include "extension.h"
-
-enum {
-	TEST_ENCRYPT = 0,
-	TEST_DECRYPT = 1,
-};
-
-#define MAX_OUT_BYTES 256
-
-#define AES_BLOCK_BYTES 16
-
-static void ecies_command_handler(void *cmd_body, size_t cmd_size,
-			size_t *response_size)
-{
-	uint8_t *cmd = cmd_body;
-	uint8_t *out = cmd_body;
-
-	uint8_t op;
-	uint8_t *in;
-	size_t in_len;
-	size_t auth_data_len;
-	const uint8_t *iv;
-	size_t iv_len = AES_BLOCK_BYTES;
-	p256_int pub_x;
-	size_t pub_x_len;
-	p256_int pub_y;
-	size_t pub_y_len;
-	p256_int *d = &pub_x;
-	const uint8_t *salt;
-	size_t salt_len;
-	const uint8_t *info;
-	size_t info_len;
-
-	/* Command format.
-	 *
-	 *   WIDTH	   FIELD
-	 *   1		   OP
-	 *   1             MSB IN LEN
-	 *   1             LSB IN LEN
-	 *   IN_LEN        IN
-	 *   1             MSB AUTH_DATA LEN
-	 *   1             LSB AUTH_DATA LEN
-	 *   16            IV
-	 *   1             MSB PUB_X LEN
-	 *   1             LSB PUB_X LEN
-	 *   PUB_X_LEN     PUB_X
-	 *   1             MSB PUB_Y LEN
-	 *   1             LSB PUB_Y LEN
-	 *   PUB_Y_LEN     PUB_Y
-	 *   1             MSB SALT LEN
-	 *   1             LSB SALT LEN
-	 *   SALT_LEN      SALT
-	 *   1             MSB INFO LEN
-	 *   1             LSB INFO LEN
-	 *   INFO_LEN      INFO
-	 */
-
-	op = *cmd++;
-	in_len = ((size_t) cmd[0]) << 8 | cmd[1];
-	cmd += 2;
-	in = cmd;
-	cmd += in_len;
-
-	auth_data_len = ((size_t) cmd[0]) << 8 | cmd[1];
-	cmd += 2;
-
-	iv = cmd;
-	cmd += iv_len;
-
-	pub_x_len = ((size_t) cmd[0]) << 8 | cmd[1];
-	cmd += 2;
-	p256_from_bin(cmd, &pub_x);
-	cmd += pub_x_len;
-
-	pub_y_len = ((size_t) cmd[0]) << 8 | cmd[1];
-	cmd += 2;
-	if (pub_y_len)
-		p256_from_bin(cmd, &pub_y);
-	cmd += pub_y_len;
-
-	salt_len = ((size_t) cmd[0]) << 8 | cmd[1];
-	cmd += 2;
-	salt = cmd;
-	cmd += salt_len;
-
-	info_len = ((size_t) cmd[0]) << 8 | cmd[1];
-	cmd += 2;
-	info = cmd;
-	cmd += info_len;
-
-	switch (op) {
-	case TEST_ENCRYPT:
-		*response_size = DCRYPTO_ecies_encrypt(
-			in, MAX_OUT_BYTES, in, in_len,
-			auth_data_len, iv,
-			&pub_x, &pub_y, salt, salt_len,
-			info, info_len);
-		break;
-	case TEST_DECRYPT:
-		*response_size = DCRYPTO_ecies_decrypt(
-			in, MAX_OUT_BYTES, in, in_len,
-			auth_data_len, iv,
-			d, salt, salt_len,
-			info, info_len);
-		break;
-	default:
-		*response_size = 0;
-	}
-
-	if (*response_size > 0)
-		memmove(out, in, *response_size);
-}
-
-DECLARE_EXTENSION_COMMAND(EXTENSION_ECIES, ecies_command_handler);
-
-#endif   /* CRYPTO_TEST_SETUP */
-
diff --git a/board/cr50/tpm2/endian.h b/board/cr50/tpm2/endian.h
deleted file mode 100644
index b5b64d3bea..0000000000
--- a/board/cr50/tpm2/endian.h
+++ /dev/null
@@ -1,11 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __EC_BOARD_CR50_TPM2_ENDIAN_H
-#define __EC_BOARD_CR50_TPM2_ENDIAN_H
-
-#include "byteorder.h"
-
-#endif /* __EC_BOARD_CR50_TPM2_ENDIAN_H */
diff --git a/board/cr50/tpm2/endorsement.c b/board/cr50/tpm2/endorsement.c
deleted file mode 100644
index e85d3dfd0e..0000000000
--- a/board/cr50/tpm2/endorsement.c
+++ /dev/null
@@ -1,684 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "TPM_Types.h"
-#include "TpmBuildSwitches.h"
-#include "CryptoEngine.h"
-#include "CpriECC_fp.h"
-#include "CpriRSA_fp.h"
-#include "tpm_types.h"
-
-#include "Global.h"
-#include "Hierarchy_fp.h"
-#include "InternalRoutines.h"
-#include "Manufacture_fp.h"
-#include "NV_Write_fp.h"
-#include "NV_DefineSpace_fp.h"
-
-#include "console.h"
-#include "extension.h"
-#include "flash.h"
-#include "flash_config.h"
-#include "flash_info.h"
-#include "printf.h"
-#include "registers.h"
-#include "system.h"
-#include "tpm_manufacture.h"
-#include "tpm_registers.h"
-
-#include "dcrypto.h"
-
-#include <cryptoc/sha256.h>
-#include <cryptoc/util.h>
-
-#include <endian.h>
-#include <string.h>
-
-#define CPRINTF(format, args...) cprintf(CC_EXTENSION, format, ## args)
-
-#define EK_CERT_NV_START_INDEX             0x01C00000
-#define INFO1_EPS_SIZE                     PRIMARY_SEED_SIZE
-#define INFO1_EPS_OFFSET                   FLASH_INFO_MANUFACTURE_STATE_OFFSET
-
-#define RO_CERTS_START_ADDR                 0x43800
-#define RO_CERTS_REGION_SIZE                0x0800
-
-enum cros_perso_component_type {
-	CROS_PERSO_COMPONENT_TYPE_EPS       = 128,
-	CROS_PERSO_COMPONENT_TYPE_RSA_CERT  = 129,
-	CROS_PERSO_COMPONENT_TYPE_P256_CERT = 130
-};
-
-struct cros_perso_response_component_info_v0 {
-	uint16_t component_size;
-	uint8_t  component_type;
-	uint8_t  reserved[5];
-} __packed;                                             /* Size: 8B */
-
-/* key_id: key for which this is the certificate */
-/* cert_len: length of the following certificate */
-/* cert: the certificate bytes */
-struct cros_perso_certificate_response_v0 {
-	uint8_t key_id[4];
-	uint32_t cert_len;
-	uint8_t cert[0];
-} __packed;                                             /* Size: 8B */
-
-/* Personalization response. */
-BUILD_ASSERT(sizeof(struct cros_perso_response_component_info_v0) == 8);
-BUILD_ASSERT(sizeof(struct cros_perso_certificate_response_v0) == 8);
-
-
-/*
- * Uncomment the #define below to enable fallback certificate installatin
- * capability.
- *
-#define CR50_INCLUDE_FALLBACK_CERT
- */
-
-#ifdef CR50_INCLUDE_FALLBACK_CERT
-
-/* This is a fixed seed (and corresponding certificates) for use in a
- * developer environment.  Use of this fixed seed will be triggered if
- * the HMAC on the certificate region (i.e. read-only certificates
- * written at manufacture) fails to verify.
- *
- * The HMAC verification failure itself only occurs in the event that
- * RO & RW are signed in a mode that does correspond to the
- * manufacture process, i.e. a PRODUCTION mode chip installed with DEV
- * signed RO/RW (or vice-versa) or a PRODUCTION signed RO and DEV
- * signed RW (or vice-versa).
- *
- * The fixed seed and its corresponding certificates are not trusted
- * by production infrastructure, and are hence useful for development
- * and testing.
- */
-const uint8_t FIXED_ENDORSEMENT_SEED[PRIMARY_SEED_SIZE] = {
-	0x1c, 0xb0, 0xde, 0x0e, 0x96, 0xe5, 0x58, 0xb0,
-	0xad, 0x1d, 0x3a, 0x08, 0x22, 0x41, 0x7f, 0x45,
-	0x37, 0xe7, 0x17, 0x42, 0x5d, 0x87, 0xc4, 0x77,
-	0xf2, 0x97, 0xf8, 0xdd, 0xb9, 0xa0, 0xe5, 0x3a
-};
-
-const uint8_t FIXED_RSA_ENDORSEMENT_CERT[1007] = {
-	0x30, 0x82, 0x03, 0xeb, 0x30, 0x82, 0x02, 0xd3, 0xa0, 0x03, 0x02, 0x01,
-	0x02, 0x02, 0x10, 0x57, 0xd7, 0x5a, 0xbc, 0x74, 0xa8, 0x2e, 0x11, 0x9c,
-	0x73, 0x70, 0x2d, 0x3e, 0x15, 0xdf, 0x4e, 0x30, 0x0d, 0x06, 0x09, 0x2a,
-	0x86, 0x48, 0x86, 0xf7, 0x0d, 0x01, 0x01, 0x0b, 0x05, 0x00, 0x30, 0x81,
-	0x80, 0x31, 0x0b, 0x30, 0x09, 0x06, 0x03, 0x55, 0x04, 0x06, 0x13, 0x02,
-	0x55, 0x53, 0x31, 0x13, 0x30, 0x11, 0x06, 0x03, 0x55, 0x04, 0x08, 0x0c,
-	0x0a, 0x43, 0x61, 0x6c, 0x69, 0x66, 0x6f, 0x72, 0x6e, 0x69, 0x61, 0x31,
-	0x14, 0x30, 0x12, 0x06, 0x03, 0x55, 0x04, 0x0a, 0x0c, 0x0b, 0x47, 0x6f,
-	0x6f, 0x67, 0x6c, 0x65, 0x20, 0x49, 0x6e, 0x63, 0x2e, 0x31, 0x24, 0x30,
-	0x22, 0x06, 0x03, 0x55, 0x04, 0x0b, 0x0c, 0x1b, 0x45, 0x6e, 0x67, 0x69,
-	0x6e, 0x65, 0x65, 0x72, 0x69, 0x6e, 0x67, 0x20, 0x61, 0x6e, 0x64, 0x20,
-	0x44, 0x65, 0x76, 0x65, 0x6c, 0x6f, 0x70, 0x6d, 0x65, 0x6e, 0x74, 0x31,
-	0x20, 0x30, 0x1e, 0x06, 0x03, 0x55, 0x04, 0x03, 0x0c, 0x17, 0x43, 0x52,
-	0x4f, 0x53, 0x20, 0x54, 0x50, 0x4d, 0x20, 0x44, 0x45, 0x56, 0x20, 0x45,
-	0x4b, 0x20, 0x52, 0x4f, 0x4f, 0x54, 0x20, 0x43, 0x41, 0x30, 0x1e, 0x17,
-	0x0d, 0x31, 0x36, 0x31, 0x30, 0x32, 0x30, 0x30, 0x30, 0x34, 0x39, 0x33,
-	0x36, 0x5a, 0x17, 0x0d, 0x32, 0x36, 0x31, 0x30, 0x31, 0x38, 0x30, 0x30,
-	0x34, 0x39, 0x33, 0x36, 0x5a, 0x30, 0x00, 0x30, 0x82, 0x01, 0x22, 0x30,
-	0x0d, 0x06, 0x09, 0x2a, 0x86, 0x48, 0x86, 0xf7, 0x0d, 0x01, 0x01, 0x01,
-	0x05, 0x00, 0x03, 0x82, 0x01, 0x0f, 0x00, 0x30, 0x82, 0x01, 0x0a, 0x02,
-	0x82, 0x01, 0x01, 0x00, 0xae, 0x3f, 0x7e, 0x66, 0x78, 0x26, 0x7a, 0x38,
-	0x93, 0xaf, 0x9c, 0xe4, 0x2c, 0x3c, 0x9e, 0x11, 0xb7, 0xae, 0x2f, 0x71,
-	0x8d, 0x4f, 0x2e, 0x3f, 0xd2, 0x35, 0x18, 0xb0, 0x27, 0x04, 0x4e, 0x04,
-	0x66, 0xb2, 0x16, 0xd4, 0xa8, 0xfc, 0x51, 0x60, 0x1b, 0x05, 0x1c, 0x02,
-	0xb5, 0x77, 0x1b, 0xf6, 0x40, 0xc4, 0x0e, 0x01, 0xbf, 0x70, 0xc1, 0x68,
-	0x53, 0x8b, 0x20, 0x4c, 0xa3, 0x39, 0x09, 0xd4, 0x4e, 0x28, 0x7c, 0x1d,
-	0xda, 0x57, 0x5c, 0x41, 0xae, 0x9b, 0xf3, 0xd5, 0xd3, 0x46, 0x12, 0x3d,
-	0x43, 0xcc, 0x39, 0x29, 0x79, 0x9d, 0xe5, 0x87, 0x84, 0x22, 0x85, 0x4b,
-	0x49, 0x35, 0x16, 0x4f, 0x3b, 0xdd, 0xd8, 0xaf, 0xe3, 0x99, 0xfa, 0x37,
-	0xaf, 0xbd, 0xa9, 0x38, 0xb4, 0x47, 0x58, 0x1e, 0x71, 0xb2, 0x46, 0xf2,
-	0x14, 0x85, 0x43, 0x12, 0x55, 0x8b, 0xc3, 0x5b, 0x78, 0x86, 0xd0, 0x0b,
-	0x08, 0x87, 0x1d, 0xf7, 0x4c, 0x69, 0x47, 0x91, 0xd1, 0x16, 0x5c, 0x0e,
-	0xf7, 0x0d, 0xad, 0x4a, 0x2d, 0xd8, 0x74, 0xe2, 0x89, 0xe1, 0xaf, 0xd7,
-	0x54, 0xb6, 0xe0, 0x36, 0x76, 0x7b, 0xd4, 0x6d, 0x50, 0x64, 0x13, 0x5b,
-	0x86, 0xa8, 0xa7, 0xee, 0xed, 0xf9, 0x50, 0x4d, 0xac, 0x1d, 0x1f, 0x9c,
-	0x1b, 0x58, 0x19, 0xa5, 0x20, 0x19, 0x75, 0xb7, 0xcf, 0xf6, 0x37, 0x59,
-	0x2a, 0xc7, 0x5b, 0x14, 0x51, 0xe6, 0x64, 0x70, 0xcc, 0x0e, 0x90, 0x9f,
-	0xe8, 0xf3, 0xc5, 0x95, 0x41, 0x74, 0x24, 0xb4, 0x6d, 0x37, 0x4a, 0x90,
-	0x17, 0x0e, 0x11, 0xea, 0xde, 0x74, 0x0e, 0x05, 0x4d, 0x1f, 0x9c, 0x11,
-	0xea, 0x06, 0xbd, 0x90, 0x9a, 0x9f, 0x44, 0x55, 0x0f, 0x93, 0x82, 0x96,
-	0xfc, 0x29, 0xb7, 0x26, 0x5e, 0x01, 0x25, 0x55, 0x4b, 0x80, 0xda, 0xd6,
-	0x2d, 0xe0, 0xd9, 0x65, 0xcf, 0xcb, 0x7a, 0x2b, 0x02, 0x03, 0x01, 0x00,
-	0x01, 0xa3, 0x81, 0xdf, 0x30, 0x81, 0xdc, 0x30, 0x0e, 0x06, 0x03, 0x55,
-	0x1d, 0x0f, 0x01, 0x01, 0xff, 0x04, 0x04, 0x03, 0x02, 0x00, 0x20, 0x30,
-	0x51, 0x06, 0x03, 0x55, 0x1d, 0x11, 0x01, 0x01, 0xff, 0x04, 0x47, 0x30,
-	0x45, 0xa4, 0x43, 0x30, 0x41, 0x31, 0x16, 0x30, 0x14, 0x06, 0x05, 0x67,
-	0x81, 0x05, 0x02, 0x01, 0x0c, 0x0b, 0x69, 0x64, 0x3a, 0x34, 0x37, 0x34,
-	0x46, 0x34, 0x46, 0x34, 0x37, 0x31, 0x0f, 0x30, 0x0d, 0x06, 0x05, 0x67,
-	0x81, 0x05, 0x02, 0x02, 0x0c, 0x04, 0x48, 0x31, 0x42, 0x32, 0x31, 0x16,
-	0x30, 0x14, 0x06, 0x05, 0x67, 0x81, 0x05, 0x02, 0x03, 0x0c, 0x0b, 0x69,
-	0x64, 0x3a, 0x30, 0x30, 0x31, 0x33, 0x30, 0x30, 0x33, 0x37, 0x30, 0x0c,
-	0x06, 0x03, 0x55, 0x1d, 0x13, 0x01, 0x01, 0xff, 0x04, 0x02, 0x30, 0x00,
-	0x30, 0x13, 0x06, 0x03, 0x55, 0x1d, 0x20, 0x04, 0x0c, 0x30, 0x0a, 0x30,
-	0x08, 0x06, 0x06, 0x67, 0x81, 0x0c, 0x01, 0x02, 0x02, 0x30, 0x1f, 0x06,
-	0x03, 0x55, 0x1d, 0x23, 0x04, 0x18, 0x30, 0x16, 0x80, 0x14, 0xd5, 0xfd,
-	0x4b, 0xf1, 0xbe, 0x05, 0xfb, 0x13, 0x28, 0xe2, 0x5f, 0x39, 0xd3, 0x9d,
-	0x70, 0x4a, 0x48, 0x91, 0x6b, 0xb0, 0x30, 0x10, 0x06, 0x03, 0x55, 0x1d,
-	0x25, 0x04, 0x09, 0x30, 0x07, 0x06, 0x05, 0x67, 0x81, 0x05, 0x08, 0x01,
-	0x30, 0x21, 0x06, 0x03, 0x55, 0x1d, 0x09, 0x04, 0x1a, 0x30, 0x18, 0x30,
-	0x16, 0x06, 0x05, 0x67, 0x81, 0x05, 0x02, 0x10, 0x31, 0x0d, 0x30, 0x0b,
-	0x0c, 0x03, 0x32, 0x2e, 0x30, 0x02, 0x01, 0x00, 0x02, 0x01, 0x10, 0x30,
-	0x0d, 0x06, 0x09, 0x2a, 0x86, 0x48, 0x86, 0xf7, 0x0d, 0x01, 0x01, 0x0b,
-	0x05, 0x00, 0x03, 0x82, 0x01, 0x01, 0x00, 0x4c, 0x65, 0x3f, 0x58, 0x73,
-	0xb6, 0x21, 0x72, 0xb3, 0x2c, 0xc3, 0x94, 0xf4, 0xb3, 0xe0, 0x74, 0xa3,
-	0x2e, 0x47, 0xa7, 0x63, 0x12, 0xa3, 0x0f, 0xc5, 0x18, 0x45, 0x06, 0xab,
-	0xa9, 0xba, 0x64, 0xf0, 0xeb, 0x18, 0x7c, 0xba, 0x57, 0x09, 0xd0, 0x11,
-	0x60, 0x6f, 0xbd, 0x52, 0x73, 0xab, 0x39, 0x81, 0x29, 0xab, 0x78, 0x84,
-	0xec, 0x00, 0xe3, 0x87, 0xec, 0xf1, 0x7d, 0x2e, 0x15, 0x3f, 0xad, 0x1b,
-	0x3a, 0x3f, 0x03, 0x53, 0x91, 0xee, 0x72, 0x7a, 0x87, 0x74, 0xa8, 0x09,
-	0x7d, 0x83, 0x37, 0x0d, 0x46, 0x22, 0x12, 0xf3, 0x79, 0x61, 0xaf, 0x80,
-	0xf3, 0xf4, 0x76, 0x7d, 0xbd, 0xb3, 0x1f, 0x87, 0xb8, 0x66, 0xc9, 0x24,
-	0x15, 0xe9, 0xc7, 0x5b, 0x19, 0xdf, 0x04, 0x0a, 0x47, 0xec, 0x88, 0x46,
-	0x7f, 0x20, 0x6c, 0x4b, 0x23, 0xdb, 0x65, 0x67, 0x54, 0xde, 0x3a, 0xc3,
-	0x64, 0xbb, 0x77, 0x4d, 0x6d, 0x4b, 0x1e, 0x43, 0x9a, 0x35, 0x20, 0x7e,
-	0x28, 0xce, 0x4e, 0xe5, 0xb7, 0x0b, 0xae, 0xd0, 0x26, 0xc0, 0xac, 0x2f,
-	0x79, 0x35, 0x71, 0xbd, 0x74, 0x68, 0x8d, 0x51, 0x6f, 0x84, 0x4d, 0xaa,
-	0xca, 0x0d, 0xf0, 0xa8, 0x41, 0x5c, 0xa9, 0x6e, 0x3b, 0x70, 0x15, 0x73,
-	0x8d, 0xf0, 0x70, 0xd3, 0xb3, 0x0e, 0xa7, 0x3a, 0x34, 0x12, 0xd2, 0x1e,
-	0xa4, 0x18, 0x4c, 0x31, 0xee, 0x26, 0x44, 0x24, 0xe0, 0xa5, 0xca, 0x56,
-	0x5d, 0x76, 0x9e, 0xf4, 0x9a, 0x6e, 0x2b, 0xd6, 0x4a, 0xe9, 0x47, 0xd9,
-	0x29, 0x94, 0x2d, 0x23, 0xf7, 0xbb, 0x13, 0x0c, 0x48, 0x73, 0x93, 0xe3,
-	0x49, 0xc7, 0xd8, 0xca, 0x5d, 0x63, 0xf5, 0x68, 0xb2, 0xe9, 0x1a, 0xe6,
-	0x87, 0x39, 0xf8, 0x12, 0xa7, 0x5c, 0xb2, 0x6e, 0x04, 0xd0, 0x73, 0x3a,
-	0x05, 0x77, 0xc0, 0x9f, 0x23, 0xa7, 0x1a, 0x71, 0x38, 0x55, 0x70
-};
-
-const uint8_t FIXED_ECC_ENDORSEMENT_CERT[804] = {
-	0x30, 0x82, 0x03, 0x20, 0x30, 0x82, 0x02, 0x08, 0xa0, 0x03, 0x02, 0x01,
-	0x02, 0x02, 0x10, 0x67, 0x02, 0x3f, 0x35, 0xc3, 0x17, 0xad, 0xcf, 0x0a,
-	0x76, 0xed, 0x50, 0x17, 0xd8, 0x4e, 0x50, 0x30, 0x0d, 0x06, 0x09, 0x2a,
-	0x86, 0x48, 0x86, 0xf7, 0x0d, 0x01, 0x01, 0x0b, 0x05, 0x00, 0x30, 0x81,
-	0x80, 0x31, 0x0b, 0x30, 0x09, 0x06, 0x03, 0x55, 0x04, 0x06, 0x13, 0x02,
-	0x55, 0x53, 0x31, 0x13, 0x30, 0x11, 0x06, 0x03, 0x55, 0x04, 0x08, 0x0c,
-	0x0a, 0x43, 0x61, 0x6c, 0x69, 0x66, 0x6f, 0x72, 0x6e, 0x69, 0x61, 0x31,
-	0x14, 0x30, 0x12, 0x06, 0x03, 0x55, 0x04, 0x0a, 0x0c, 0x0b, 0x47, 0x6f,
-	0x6f, 0x67, 0x6c, 0x65, 0x20, 0x49, 0x6e, 0x63, 0x2e, 0x31, 0x24, 0x30,
-	0x22, 0x06, 0x03, 0x55, 0x04, 0x0b, 0x0c, 0x1b, 0x45, 0x6e, 0x67, 0x69,
-	0x6e, 0x65, 0x65, 0x72, 0x69, 0x6e, 0x67, 0x20, 0x61, 0x6e, 0x64, 0x20,
-	0x44, 0x65, 0x76, 0x65, 0x6c, 0x6f, 0x70, 0x6d, 0x65, 0x6e, 0x74, 0x31,
-	0x20, 0x30, 0x1e, 0x06, 0x03, 0x55, 0x04, 0x03, 0x0c, 0x17, 0x43, 0x52,
-	0x4f, 0x53, 0x20, 0x54, 0x50, 0x4d, 0x20, 0x44, 0x45, 0x56, 0x20, 0x45,
-	0x4b, 0x20, 0x52, 0x4f, 0x4f, 0x54, 0x20, 0x43, 0x41, 0x30, 0x1e, 0x17,
-	0x0d, 0x31, 0x36, 0x31, 0x30, 0x32, 0x30, 0x30, 0x30, 0x34, 0x39, 0x33,
-	0x36, 0x5a, 0x17, 0x0d, 0x32, 0x36, 0x31, 0x30, 0x31, 0x38, 0x30, 0x30,
-	0x34, 0x39, 0x33, 0x36, 0x5a, 0x30, 0x00, 0x30, 0x59, 0x30, 0x13, 0x06,
-	0x07, 0x2a, 0x86, 0x48, 0xce, 0x3d, 0x02, 0x01, 0x06, 0x08, 0x2a, 0x86,
-	0x48, 0xce, 0x3d, 0x03, 0x01, 0x07, 0x03, 0x42, 0x00, 0x04, 0x6e, 0xcc,
-	0xf0, 0x96, 0x69, 0x9b, 0x3f, 0xea, 0x95, 0xb7, 0xd5, 0x00, 0x27, 0x20,
-	0x81, 0x8e, 0x57, 0x00, 0x6f, 0x67, 0x98, 0xce, 0x8e, 0xdf, 0xc7, 0xda,
-	0xae, 0xa8, 0xa3, 0xed, 0x3e, 0x7a, 0xb3, 0x27, 0xbf, 0x92, 0xee, 0xb2,
-	0xa2, 0x76, 0x81, 0xc1, 0x71, 0x4d, 0x8c, 0xa8, 0x9d, 0xfd, 0x8e, 0xd0,
-	0x29, 0xb5, 0x01, 0x20, 0xec, 0x78, 0xc0, 0x17, 0x8f, 0xf6, 0xf8, 0x67,
-	0x5f, 0xe8, 0xa3, 0x81, 0xdf, 0x30, 0x81, 0xdc, 0x30, 0x0e, 0x06, 0x03,
-	0x55, 0x1d, 0x0f, 0x01, 0x01, 0xff, 0x04, 0x04, 0x03, 0x02, 0x00, 0x20,
-	0x30, 0x51, 0x06, 0x03, 0x55, 0x1d, 0x11, 0x01, 0x01, 0xff, 0x04, 0x47,
-	0x30, 0x45, 0xa4, 0x43, 0x30, 0x41, 0x31, 0x16, 0x30, 0x14, 0x06, 0x05,
-	0x67, 0x81, 0x05, 0x02, 0x01, 0x0c, 0x0b, 0x69, 0x64, 0x3a, 0x34, 0x37,
-	0x34, 0x46, 0x34, 0x46, 0x34, 0x37, 0x31, 0x0f, 0x30, 0x0d, 0x06, 0x05,
-	0x67, 0x81, 0x05, 0x02, 0x02, 0x0c, 0x04, 0x48, 0x31, 0x42, 0x32, 0x31,
-	0x16, 0x30, 0x14, 0x06, 0x05, 0x67, 0x81, 0x05, 0x02, 0x03, 0x0c, 0x0b,
-	0x69, 0x64, 0x3a, 0x30, 0x30, 0x31, 0x33, 0x30, 0x30, 0x33, 0x37, 0x30,
-	0x0c, 0x06, 0x03, 0x55, 0x1d, 0x13, 0x01, 0x01, 0xff, 0x04, 0x02, 0x30,
-	0x00, 0x30, 0x13, 0x06, 0x03, 0x55, 0x1d, 0x20, 0x04, 0x0c, 0x30, 0x0a,
-	0x30, 0x08, 0x06, 0x06, 0x67, 0x81, 0x0c, 0x01, 0x02, 0x02, 0x30, 0x1f,
-	0x06, 0x03, 0x55, 0x1d, 0x23, 0x04, 0x18, 0x30, 0x16, 0x80, 0x14, 0xd5,
-	0xfd, 0x4b, 0xf1, 0xbe, 0x05, 0xfb, 0x13, 0x28, 0xe2, 0x5f, 0x39, 0xd3,
-	0x9d, 0x70, 0x4a, 0x48, 0x91, 0x6b, 0xb0, 0x30, 0x10, 0x06, 0x03, 0x55,
-	0x1d, 0x25, 0x04, 0x09, 0x30, 0x07, 0x06, 0x05, 0x67, 0x81, 0x05, 0x08,
-	0x01, 0x30, 0x21, 0x06, 0x03, 0x55, 0x1d, 0x09, 0x04, 0x1a, 0x30, 0x18,
-	0x30, 0x16, 0x06, 0x05, 0x67, 0x81, 0x05, 0x02, 0x10, 0x31, 0x0d, 0x30,
-	0x0b, 0x0c, 0x03, 0x32, 0x2e, 0x30, 0x02, 0x01, 0x00, 0x02, 0x01, 0x10,
-	0x30, 0x0d, 0x06, 0x09, 0x2a, 0x86, 0x48, 0x86, 0xf7, 0x0d, 0x01, 0x01,
-	0x0b, 0x05, 0x00, 0x03, 0x82, 0x01, 0x01, 0x00, 0x21, 0xab, 0x9e, 0x92,
-	0x4d, 0xb0, 0x50, 0x04, 0xeb, 0x2b, 0xb6, 0xcc, 0x87, 0x8c, 0xa8, 0x27,
-	0xe3, 0x5a, 0xbf, 0x03, 0x5d, 0xb1, 0x4d, 0x24, 0xda, 0xdf, 0x44, 0xdb,
-	0x4a, 0x37, 0x5c, 0x3e, 0x70, 0xf3, 0x35, 0x5d, 0x26, 0x2e, 0xaa, 0x85,
-	0xc6, 0xbe, 0x1c, 0x9d, 0x1e, 0x5f, 0xf6, 0x6c, 0xb8, 0x94, 0x41, 0x25,
-	0x20, 0x55, 0x28, 0x53, 0x55, 0x67, 0x9a, 0xb5, 0xfb, 0x6b, 0x57, 0x09,
-	0xf0, 0x5b, 0xe2, 0x66, 0xc5, 0xe8, 0xd1, 0x9e, 0xb8, 0xb7, 0xed, 0xd8,
-	0x41, 0xb5, 0xbd, 0x44, 0xd9, 0x53, 0xab, 0x2d, 0x17, 0x4c, 0x73, 0x05,
-	0x19, 0x2c, 0x9d, 0x18, 0x98, 0xd8, 0x55, 0xbe, 0xbd, 0xb6, 0xa5, 0xf6,
-	0x5f, 0x3d, 0x70, 0x98, 0xd6, 0xd0, 0xcf, 0x1c, 0x0d, 0xc6, 0x78, 0x6d,
-	0x2e, 0x9c, 0x44, 0xf6, 0x9e, 0x0a, 0x80, 0x12, 0xcd, 0x9b, 0x4b, 0x1f,
-	0xbc, 0xfe, 0xe7, 0x3f, 0x45, 0x81, 0x78, 0x43, 0x40, 0xf2, 0xb0, 0x6b,
-	0x2c, 0x23, 0xc8, 0xc8, 0x57, 0xc6, 0x33, 0x08, 0x3e, 0x17, 0x43, 0x16,
-	0xf0, 0x3f, 0xbf, 0x24, 0x54, 0xba, 0xe6, 0x85, 0x4c, 0xc8, 0x2e, 0x7f,
-	0x88, 0x41, 0x6c, 0x4e, 0x03, 0xa6, 0x35, 0x00, 0x4d, 0xdb, 0x65, 0x68,
-	0x78, 0x01, 0x40, 0xc6, 0xa0, 0x95, 0xd9, 0xe9, 0x27, 0xe1, 0x90, 0x20,
-	0xc8, 0xe6, 0xa7, 0x7c, 0x4d, 0x9c, 0x1c, 0x44, 0x47, 0xfe, 0x9e, 0xc9,
-	0x25, 0x7a, 0x07, 0xa9, 0x86, 0x60, 0x58, 0x18, 0x1c, 0x16, 0x18, 0x7e,
-	0x04, 0xd6, 0x5a, 0xb6, 0xcb, 0xb6, 0xa6, 0x0f, 0xd9, 0x42, 0xf3, 0x19,
-	0x8c, 0xbe, 0x26, 0x98, 0xdd, 0x07, 0x05, 0x76, 0xc0, 0xf9, 0xa4, 0xeb,
-	0x53, 0xff, 0x13, 0x27, 0x61, 0x87, 0x66, 0x99, 0x76, 0x9c, 0x5f, 0x03,
-	0x52, 0x95, 0x13, 0x6e, 0xb7, 0x33, 0x1f, 0x8d, 0xc6, 0x22, 0xd8, 0xe4
-};
-
-static int store_eps(const uint8_t eps[PRIMARY_SEED_SIZE]);
-static int store_cert(enum cros_perso_component_type component_type,
-		      const uint8_t *cert, size_t cert_len);
-
-static int install_fixed_certs(void)
-{
-	if (!store_eps(FIXED_ENDORSEMENT_SEED))
-		return 0;
-
-	if (!store_cert(CROS_PERSO_COMPONENT_TYPE_RSA_CERT,
-				FIXED_RSA_ENDORSEMENT_CERT,
-				sizeof(FIXED_RSA_ENDORSEMENT_CERT)))
-		return 0;
-
-	if (!store_cert(CROS_PERSO_COMPONENT_TYPE_P256_CERT,
-				FIXED_ECC_ENDORSEMENT_CERT,
-				sizeof(FIXED_ECC_ENDORSEMENT_CERT)))
-		return 0;
-
-	return 1;
-}
-
-#endif
-
-/* Test endorsement CA root. */
-static const uint32_t TEST_ENDORSEMENT_CA_RSA_N[64] = {
-	0xfa3b34ed, 0x3c59ad05, 0x912d6623, 0x83302402,
-	0xd43b6755, 0x5777021a, 0xaf37e9a1, 0x45c0e8ad,
-	0x9728f946, 0x4391523d, 0xdf7a9164, 0x88f1a9ae,
-	0x036c557e, 0x5d9df43e, 0x3e65de68, 0xe172008a,
-	0x709dc81f, 0x27a75fe0, 0x3e77f89e, 0x4f400ecc,
-	0x51a17dae, 0x2ff9c652, 0xd1d83cdb, 0x20d26349,
-	0xbbad71dd, 0x30051b2b, 0x276b2459, 0x809bb8e1,
-	0xb8737049, 0xdbe94466, 0x8287072b, 0x070ef311,
-	0x6e2a26de, 0x29d69f11, 0x96463d95, 0xb4dc6950,
-	0x097d4dfe, 0x1b4a88cc, 0xbd6b50c8, 0x9f7a5b34,
-	0xda22c199, 0x9d1ac04b, 0x136af5e5, 0xb1a0e824,
-	0x4a065b34, 0x1f67fb46, 0xa1f91ab1, 0x27bb769f,
-	0xb704c992, 0xb669cbf4, 0x9299bb6c, 0xcb1b2208,
-	0x2dc0d9db, 0xe1513e13, 0xc7f24923, 0xa74c6bcc,
-	0xca1a9a69, 0x1b994244, 0x4f64b0d9, 0x78607fd6,
-	0x486fb315, 0xa1098c31, 0x5dc50dd6, 0xcdc10874
-};
-
-/* Production endorsement CA root. */
-static const uint32_t PROD_ENDORSEMENT_CA_RSA_N[64] = {
-	0xeb6a07bf, 0x6cf8eca6, 0x4756e85e, 0x2fc3874c,
-	0xa4c23e87, 0xc364dffe, 0x2a2ddb95, 0x2f7f0e1e,
-	0xdb485bd8, 0xce8aa808, 0xe062001b, 0x187811c3,
-	0x0e400462, 0xb7097a01, 0xb988152b, 0xba9d058a,
-	0x814b6691, 0xc70a694f, 0x8108c7f0, 0x4c7a1f33,
-	0x5cfda48e, 0xef303dbc, 0x84f5a3ea, 0x14607435,
-	0xc72f1e60, 0x345d0b38, 0x0ac16927, 0xbdf903c7,
-	0x11b660ed, 0x21ebfe0e, 0x8c8b303c, 0xd6eff6cb,
-	0x76156bf7, 0x57735ce4, 0x8b7a87ed, 0x7a757188,
-	0xd4fb3eb0, 0xc67fa05d, 0x163f0cf5, 0x69d8abf3,
-	0xec105749, 0x1de78f37, 0xb885a62f, 0x81344a82,
-	0x390df2b7, 0x58a7c56a, 0xa938f471, 0x506ee7d4,
-	0x2ca0f2a3, 0x2aa5392c, 0x39052797, 0x199e837c,
-	0x0d367b81, 0xb7bbff6f, 0x0ea99f5f, 0xfbac0d2a,
-	0x7bbe018d, 0x265fc995, 0x34f73008, 0x5e2cd747,
-	0x42096e33, 0x0c15f816, 0xffa7f7d2, 0xbd6f0198
-};
-
-static const struct RSA TEST_ENDORSEMENT_CA_RSA_PUB = {
-	.e = RSA_F4,
-	.N = {
-		.dmax = sizeof(TEST_ENDORSEMENT_CA_RSA_N) / sizeof(uint32_t),
-		.d = (struct access_helper *) TEST_ENDORSEMENT_CA_RSA_N,
-	},
-	.d = {
-		.dmax = 0,
-		.d = NULL,
-	},
-};
-
-static const struct RSA PROD_ENDORSEMENT_CA_RSA_PUB = {
-	.e = RSA_F4,
-	.N = {
-		.dmax = sizeof(PROD_ENDORSEMENT_CA_RSA_N) / sizeof(uint32_t),
-		.d = (struct access_helper *) PROD_ENDORSEMENT_CA_RSA_N,
-	},
-	.d = {
-		.dmax = 0,
-		.d = NULL,
-	},
-};
-
-static int validate_cert(
-	const struct cros_perso_response_component_info_v0 *cert_info,
-	const struct cros_perso_certificate_response_v0 *cert,
-	const uint8_t eps[PRIMARY_SEED_SIZE])
-{
-	if (cert_info->component_type != CROS_PERSO_COMPONENT_TYPE_RSA_CERT &&
-	    cert_info->component_type !=
-	    CROS_PERSO_COMPONENT_TYPE_P256_CERT)
-		return 0;  /* Invalid component type. */
-
-	/* TODO(ngm): verify key_id against HIK/FRK0. */
-	if (cert->cert_len > MAX_NV_BUFFER_SIZE)
-		return 0;
-
-	/* Verify certificate signature; accept either root CA.
-	 * Getting here implies that the previous mac check on the
-	 * endorsement seed passed, and that one of these two CA
-	 * certificates serve as roots for the installed endorsement
-	 * certificate.
-	 */
-	return DCRYPTO_x509_verify(cert->cert, cert->cert_len,
-				&PROD_ENDORSEMENT_CA_RSA_PUB) ||
-		DCRYPTO_x509_verify(cert->cert, cert->cert_len,
-				&TEST_ENDORSEMENT_CA_RSA_PUB);
-}
-
-static int store_cert(enum cros_perso_component_type component_type,
-		const uint8_t *cert, size_t cert_len)
-{
-	const uint32_t rsa_ek_nv_index = EK_CERT_NV_START_INDEX;
-	const uint32_t ecc_ek_nv_index = EK_CERT_NV_START_INDEX + 1;
-	uint32_t nv_index;
-	NV_DefineSpace_In define_space;
-	TPMA_NV space_attributes;
-	NV_Write_In in;
-
-	/* Clear up structures potentially uszed only partially. */
-	memset(&define_space, 0, sizeof(define_space));
-	memset(&space_attributes, 0, sizeof(space_attributes));
-	memset(&in, 0, sizeof(in));
-
-	/* Indicate that a system reset has occurred, and currently
-	 * running with Platform auth.
-	 */
-	HierarchyStartup(SU_RESET);
-
-	if (component_type == CROS_PERSO_COMPONENT_TYPE_RSA_CERT)
-		nv_index = rsa_ek_nv_index;
-	else   /* P256 certificate. */
-		nv_index = ecc_ek_nv_index;
-
-	/* EK Credential attributes specified in the "TCG PC Client
-	 * Platform, TPM Profile (PTP) Specification" document.
-	 */
-	/* REQUIRED: Writeable under platform auth. */
-	space_attributes.TPMA_NV_PPWRITE = 1;
-	/* OPTIONAL: Write-once; space must be deleted to be re-written. */
-	space_attributes.TPMA_NV_WRITEDEFINE = 1;
-	/* REQUIRED: Space created with platform auth. */
-	space_attributes.TPMA_NV_PLATFORMCREATE = 1;
-	/* REQUIRED: Readable under empty password? */
-	space_attributes.TPMA_NV_AUTHREAD = 1;
-	/* REQUIRED: Disable dictionary attack protection. */
-	space_attributes.TPMA_NV_NO_DA = 1;
-
-	define_space.authHandle = TPM_RH_PLATFORM;
-	define_space.auth.t.size = 0;
-	define_space.publicInfo.t.size = sizeof(
-		define_space.publicInfo.t.nvPublic);
-	define_space.publicInfo.t.nvPublic.nvIndex = nv_index;
-	define_space.publicInfo.t.nvPublic.nameAlg = TPM_ALG_SHA256;
-	define_space.publicInfo.t.nvPublic.attributes = space_attributes;
-	define_space.publicInfo.t.nvPublic.authPolicy.t.size = 0;
-	define_space.publicInfo.t.nvPublic.dataSize = cert_len;
-
-	/* Define the required space first. */
-	if (TPM2_NV_DefineSpace(&define_space) != TPM_RC_SUCCESS)
-		return 0;
-
-	/* TODO(ngm): call TPM2_NV_WriteLock(nvIndex) on tpm_init();
-	 * this prevents delete?
-	 */
-
-	in.nvIndex = nv_index;
-	in.authHandle = TPM_RH_PLATFORM;
-	in.data.t.size = cert_len;
-	memcpy(in.data.t.buffer, cert, cert_len);
-	in.offset = 0;
-
-	if (TPM2_NV_Write(&in) != TPM_RC_SUCCESS)
-		return 0;
-	if (NvCommit())
-		return 1;
-	return 0;
-}
-
-static void flash_cert_region_enable(void)
-{
-	/* Enable R access to CERT block. */
-	GREG32(GLOBALSEC, FLASH_REGION6_BASE_ADDR) = RO_CERTS_START_ADDR;
-	GREG32(GLOBALSEC, FLASH_REGION6_SIZE) =
-		RO_CERTS_REGION_SIZE - 1;
-	GREG32(GLOBALSEC, FLASH_REGION6_CTRL) =
-		GC_GLOBALSEC_FLASH_REGION6_CTRL_EN_MASK |
-		GC_GLOBALSEC_FLASH_REGION6_CTRL_RD_EN_MASK;
-}
-
-#define K_CROS_FW_MAJOR_VERSION 0
-
-/* EPS is stored XOR'd with FRK2, so make sure that the sizes match. */
-BUILD_ASSERT(AES256_BLOCK_CIPHER_KEY_SIZE == PRIMARY_SEED_SIZE);
-static int get_decrypted_eps(uint8_t eps[PRIMARY_SEED_SIZE])
-{
-	int i;
-	uint8_t frk2[AES256_BLOCK_CIPHER_KEY_SIZE];
-
-	CPRINTF("%s: getting eps\n", __func__);
-	if (!DCRYPTO_ladder_compute_frk2(K_CROS_FW_MAJOR_VERSION, frk2))
-		return 0;
-
-	for (i = 0; i < INFO1_EPS_SIZE; i += sizeof(uint32_t)) {
-		uint32_t word;
-
-		if (flash_physical_info_read_word(
-				INFO1_EPS_OFFSET + i, &word) != EC_SUCCESS) {
-			always_memset(frk2, 0, sizeof(frk2));
-			return 0;     /* Flash read INFO1 failed. */
-		}
-		memcpy(eps + i, &word, sizeof(word));
-	}
-
-	/* One-time-pad decrypt EPS. */
-	for (i = 0; i < PRIMARY_SEED_SIZE; i++)
-		eps[i] ^= frk2[i];
-
-	always_memset(frk2, 0, sizeof(frk2));
-	return 1;
-}
-
-static int store_eps(const uint8_t eps[PRIMARY_SEED_SIZE])
-{
-	/* gp is a TPM global state structure, declared in Global.h. */
-	memcpy(gp.EPSeed.t.buffer, eps, PRIMARY_SEED_SIZE);
-
-	/* Persist the seed to flash. */
-	NvWriteReserved(NV_EP_SEED, &gp.EPSeed);
-	return NvCommit();
-}
-
-static void endorsement_complete(void)
-{
-	CPRINTF("%s(): SUCCESS\n", __func__);
-}
-
-static int handle_cert(
-	const struct cros_perso_response_component_info_v0 *cert_info,
-	const struct cros_perso_certificate_response_v0 *cert,
-	const uint8_t *eps)
-{
-
-	/* Write RSA / P256 endorsement certificate. */
-	if (!validate_cert(cert_info, cert, eps))
-		return 0;
-
-	/* TODO(ngm): verify that storage succeeded. */
-	if (!store_cert(cert_info->component_type, cert->cert,
-				cert->cert_len)) {
-		CPRINTF("%s(): cert storage failed, type: %d\n", __func__,
-			cert_info->component_type);
-		return 0;  /* Internal failure. */
-	}
-
-	return 1;
-}
-
-enum manufacturing_status tpm_endorse(void)
-{
-	struct ro_cert_response {
-		uint8_t key_id[4];
-		uint32_t cert_len;
-		uint8_t cert[0];
-	} __packed;
-
-	struct ro_cert {
-		const struct cros_perso_response_component_info_v0 cert_info;
-		const struct ro_cert_response cert_response;
-	} __packed;
-
-	/* 2-kB RO cert region is setup like so:
-	 *
-	 *   | struct ro_cert | rsa_cert | struct ro_cert | ecc_cert |
-	 *
-	 *   last 32 bytes is hmac over (2048 - 32) preceding bytes.
-	 *   using hmac(eps, "RSA", 4) as key
-	 */
-	const uint8_t *p = (const uint8_t *) RO_CERTS_START_ADDR;
-	const uint32_t *c = (const uint32_t *) RO_CERTS_START_ADDR;
-	const struct ro_cert *rsa_cert;
-	const struct ro_cert *ecc_cert;
-	enum manufacturing_status result;
-	uint8_t eps[PRIMARY_SEED_SIZE];
-
-	LITE_HMAC_CTX hmac;
-
-	flash_cert_region_enable();
-
-	/* First boot, certs not yet installed. */
-	if (*c == 0xFFFFFFFF)
-		return mnf_no_certs;
-
-	if (!get_decrypted_eps(eps)) {
-		CPRINTF("%s(): failed to read eps\n", __func__);
-		return mnf_eps_decr;
-	}
-
-	/* Unpack rsa cert struct. */
-	rsa_cert = (const struct ro_cert *) p;
-	/* Sanity check cert region contents. */
-	if ((2 * sizeof(struct ro_cert)) +
-		rsa_cert->cert_response.cert_len > RO_CERTS_REGION_SIZE)
-		return mnf_bad_rsa_size;
-
-	/* Unpack ecc cert struct. */
-	ecc_cert = (const struct ro_cert *) (p + sizeof(struct ro_cert) +
-					rsa_cert->cert_response.cert_len);
-	/* Sanity check cert region contents. */
-	if ((2 * sizeof(struct ro_cert)) +
-		rsa_cert->cert_response.cert_len +
-		ecc_cert->cert_response.cert_len > RO_CERTS_REGION_SIZE)
-		return mnf_bad_total_size;
-
-	/* Verify expected component types. */
-	if (rsa_cert->cert_info.component_type !=
-		CROS_PERSO_COMPONENT_TYPE_RSA_CERT) {
-		return mnf_bad_rsa_type;
-	}
-	if (ecc_cert->cert_info.component_type !=
-		CROS_PERSO_COMPONENT_TYPE_P256_CERT) {
-		return mnf_bad_ecc_type;
-	}
-
-	do {
-		/* Check cert region hmac.
-		 *
-		 * This will fail if we are not running w/ expected keyladder.
-		 */
-		DCRYPTO_HMAC_SHA256_init(&hmac, eps, sizeof(eps));
-		HASH_update(&hmac.hash, "RSA", 4);
-		DCRYPTO_HMAC_SHA256_init(&hmac, DCRYPTO_HMAC_final(&hmac), 32);
-		HASH_update(&hmac.hash, p, RO_CERTS_REGION_SIZE - 32);
-		if (!DCRYPTO_equals(p + RO_CERTS_REGION_SIZE - 32,
-				   DCRYPTO_HMAC_final(&hmac), 32)) {
-
-			CPRINTF("%s: bad cert region hmac;", __func__);
-#ifdef CR50_INCLUDE_FALLBACK_CERT
-			/* HMAC verification failure indicates either
-			 * a manufacture fault, or mis-match in
-			 * production mode and currently running
-			 * firmware (e.g. PRODUCTION mode chip, now
-			 * flashed with DEV mode firmware.
-			 *
-			 * In either case, fall back to a fixed
-			 * endorsement seed, which will not be trusted
-			 * by production infrastructure.
-			 */
-			if (!install_fixed_certs()) {
-				CPRINTF(" failed to install fixed "
-					"endorsement certs;");
-				result = mnf_hmac_mismatch;
-				break;
-			}
-#else
-			if (board_in_prod_mode()) {
-
-				/* TODO(ngm): is this state considered
-				 * endorsement failure?
-				 */
-				CPRINTF("NO certs installed\n");
-				result = mnf_hmac_mismatch;
-				break;
-			}
-
-			/*
-			 * This will install bogus certificate, will happen
-			 * only when Cr50 image is signed with dev key.
-			 *
-			 * Installing bogus certificate helps with simple TPM
-			 * operations, as it allows to prevent TPM going
-			 * through manufacturing process after every reset,
-			 * but the generated RSA endorsement will not
-			 * correspond to the certificate, which will cause
-			 * problems when TPM identity is required.
-			 */
-			result = mnf_unverified_cert;
-			CPRINTF("instaling UNVERIFIED certs\n");
-#endif
-		}
-
-		if (!handle_cert(
-				&rsa_cert->cert_info,
-				(struct cros_perso_certificate_response_v0 *)
-				&rsa_cert->cert_response, eps)) {
-			CPRINTF("%s: Failed to process RSA cert\n", __func__);
-			result = mnf_rsa_proc;
-			break;
-		}
-		CPRINTF("%s: RSA cert install success\n", __func__);
-
-		if (!handle_cert(
-				&ecc_cert->cert_info,
-				(struct cros_perso_certificate_response_v0 *)
-				&ecc_cert->cert_response, eps)) {
-			CPRINTF("%s: Failed to process ECC cert\n", __func__);
-			result = mnf_ecc_proc;
-			break;
-		}
-		CPRINTF("%s: ECC cert install success\n", __func__);
-
-		/* Copy EPS from INFO1 to flash data region. */
-		if (!store_eps(eps)) {
-			CPRINTF("%s(): eps storage failed\n", __func__);
-			result = mnf_store;
-			break;
-		}
-
-		/* Mark as endorsed. */
-		endorsement_complete();
-
-		/* Chip has been marked as manufactured. */
-		result = mnf_success;
-	} while (0);
-
-	always_memset(eps, 0, sizeof(eps));
-	return result;
-}
diff --git a/board/cr50/tpm2/hash.c b/board/cr50/tpm2/hash.c
deleted file mode 100644
index 7774a6f819..0000000000
--- a/board/cr50/tpm2/hash.c
+++ /dev/null
@@ -1,460 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "CryptoEngine.h"
-
-#include "util.h"
-#include "dcrypto.h"
-
-static const HASH_INFO *lookup_hash_info(TPM_ALG_ID alg)
-{
-	int i;
-	const int num_algs = ARRAY_SIZE(g_hashData);
-
-	for (i = 0; i < num_algs - 1; i++) {
-		if (g_hashData[i].alg == alg)
-			return &g_hashData[i];
-	}
-	return &g_hashData[num_algs - 1];
-}
-
-TPM_ALG_ID _cpri__GetContextAlg(CPRI_HASH_STATE *hash_state)
-{
-	return hash_state->hashAlg;
-}
-
-TPM_ALG_ID _cpri__GetHashAlgByIndex(uint32_t index)
-{
-	if (index >= HASH_COUNT)
-		return TPM_ALG_NULL;
-	return g_hashData[index].alg;
-}
-
-uint16_t _cpri__GetDigestSize(TPM_ALG_ID alg)
-{
-	return lookup_hash_info(alg)->digestSize;
-}
-
-uint16_t _cpri__GetHashBlockSize(TPM_ALG_ID alg)
-{
-	return lookup_hash_info(alg)->blockSize;
-}
-
-BUILD_ASSERT(sizeof(LITE_SHA256_CTX) == USER_MIN_HASH_STATE_SIZE);
-BUILD_ASSERT(sizeof(CPRI_HASH_STATE) == sizeof(EXPORT_HASH_STATE));
-void _cpri__ImportExportHashState(CPRI_HASH_STATE *osslFmt,
-				EXPORT_HASH_STATE *externalFmt,
-				IMPORT_EXPORT direction)
-{
-	if (direction == IMPORT_STATE)
-		memcpy(osslFmt, externalFmt, sizeof(CPRI_HASH_STATE));
-	else
-		memcpy(externalFmt, osslFmt, sizeof(CPRI_HASH_STATE));
-}
-
-uint16_t _cpri__HashBlock(TPM_ALG_ID alg, uint32_t in_len, uint8_t *in,
-			uint32_t out_len, uint8_t *out)
-{
-	uint8_t digest[SHA_DIGEST_MAX_BYTES];
-	const uint16_t digest_len = _cpri__GetDigestSize(alg);
-
-	if (digest_len == 0)
-		return 0;
-
-	switch (alg) {
-	case TPM_ALG_SHA1:
-		DCRYPTO_SHA1_hash(in, in_len, digest);
-		break;
-
-	case TPM_ALG_SHA256:
-		DCRYPTO_SHA256_hash(in, in_len, digest);
-		break;
-	case TPM_ALG_SHA384:
-		DCRYPTO_SHA384_hash(in, in_len, digest);
-		break;
-	case TPM_ALG_SHA512:
-		DCRYPTO_SHA512_hash(in, in_len, digest);
-		break;
-	default:
-		FAIL(FATAL_ERROR_INTERNAL);
-		break;
-	}
-
-	out_len = MIN(out_len, digest_len);
-	memcpy(out, digest, out_len);
-	return out_len;
-}
-
-BUILD_ASSERT(sizeof(struct HASH_CTX) <=
-	     sizeof(((CPRI_HASH_STATE *)0)->state));
-uint16_t _cpri__StartHash(TPM_ALG_ID alg, BOOL sequence,
-			  CPRI_HASH_STATE *state)
-{
-	struct HASH_CTX *ctx = (struct HASH_CTX *) state->state;
-	uint16_t result;
-
-	/* NOTE: as per bug http://crosbug.com/p/55331#26 (NVMEM
-	 * encryption), always use the software hash implementation
-	 * for TPM related calculations, since we have no guarantee
-	 * that the key-ladder will not be used between SHA_init() and
-	 * final().
-	 */
-	switch (alg) {
-	case TPM_ALG_SHA1:
-		DCRYPTO_SHA1_init(ctx, 1);
-		result = HASH_size(ctx);
-		break;
-	case TPM_ALG_SHA256:
-		DCRYPTO_SHA256_init(ctx, 1);
-		result = HASH_size(ctx);
-		break;
-
-	case TPM_ALG_SHA384:
-		DCRYPTO_SHA384_init(ctx);
-		result = HASH_size(ctx);
-		break;
-	case TPM_ALG_SHA512:
-		DCRYPTO_SHA512_init(ctx);
-		result = HASH_size(ctx);
-		break;
-	default:
-		result = 0;
-		break;
-	}
-
-	if (result > 0)
-		state->hashAlg = alg;
-
-	return result;
-}
-
-void _cpri__UpdateHash(CPRI_HASH_STATE *state, uint32_t in_len,
-		BYTE *in)
-{
-	struct HASH_CTX *ctx = (struct HASH_CTX *) state->state;
-
-	HASH_update(ctx, in, in_len);
-}
-
-uint16_t _cpri__CompleteHash(CPRI_HASH_STATE *state,
-			uint32_t out_len, uint8_t *out)
-{
-	struct HASH_CTX *ctx = (struct HASH_CTX *) state->state;
-
-	out_len = MIN(HASH_size(ctx), out_len);
-	memcpy(out, HASH_final(ctx), out_len);
-	return out_len;
-}
-
-#ifdef CRYPTO_TEST_SETUP
-
-#include "console.h"
-#include "extension.h"
-#include "shared_mem.h"
-
-#define CPRINTF(format, args...) cprintf(CC_EXTENSION, format, ## args)
-
-struct test_context {
-	int context_handle;
-	CPRI_HASH_STATE hstate;
-};
-
-static struct {
-	int current_context_count;
-	int max_contexts;
-	struct test_context *contexts;
-} hash_test_db;
-
-struct test_context *find_context(int handle)
-{
-	int i;
-
-	for (i = 0; i < hash_test_db.current_context_count; i++)
-		if (hash_test_db.contexts[i].context_handle == handle)
-			return hash_test_db.contexts + i;
-	return NULL;
-}
-
-static void process_start(TPM_ALG_ID alg, int handle, void *response_body,
-			  size_t *response_size)
-{
-	uint8_t *response = response_body;
-	struct test_context *new_context;
-
-	if (find_context(handle)) {
-		*response = EXC_HASH_DUPLICATED_HANDLE;
-		*response_size = 1;
-		return;
-	}
-
-	if (!hash_test_db.max_contexts) {
-		size_t buffer_size;
-
-		/* Check how many contexts could possible fit. */
-		hash_test_db.max_contexts = shared_mem_size() /
-			sizeof(struct test_context);
-
-		buffer_size = sizeof(struct test_context) *
-			hash_test_db.max_contexts;
-
-		if (shared_mem_acquire(buffer_size,
-				       (char **)&hash_test_db.contexts) !=
-		    EC_SUCCESS) {
-			/* Must be out of memory. */
-			hash_test_db.max_contexts = 0;
-			*response = EXC_HASH_TOO_MANY_HANDLES;
-			*response_size = 1;
-			return;
-		}
-		memset(hash_test_db.contexts, 0, buffer_size);
-	}
-
-	if (hash_test_db.current_context_count == hash_test_db.max_contexts) {
-		*response = EXC_HASH_TOO_MANY_HANDLES;
-		*response_size = 1;
-		return;
-	}
-
-	new_context = hash_test_db.contexts +
-		hash_test_db.current_context_count++;
-	new_context->context_handle = handle;
-	_cpri__StartHash(alg, 0, &new_context->hstate);
-}
-
-static void process_continue(int handle, void *cmd_body, uint16_t text_len,
-			     void *response_body, size_t *response_size)
-{
-	struct test_context *context = find_context(handle);
-
-	if (!context) {
-		*((uint8_t *)response_body) = EXC_HASH_UNKNOWN_CONTEXT;
-		*response_size = 1;
-		return;
-	}
-
-	_cpri__UpdateHash(&context->hstate, text_len, cmd_body);
-}
-
-static void process_finish(int handle, void *response_body,
-			   size_t *response_size)
-{
-	struct test_context *context = find_context(handle);
-
-	if (!context) {
-		*((uint8_t *)response_body) = EXC_HASH_UNKNOWN_CONTEXT;
-		*response_size = 1;
-		return;
-	}
-
-	/* There for sure is enough room in the TPM buffer. */
-	*response_size = _cpri__CompleteHash(&context->hstate,
-					     SHA_DIGEST_MAX_BYTES,
-					     response_body);
-
-	/* drop this context from the database. */
-	hash_test_db.current_context_count--;
-	if (!hash_test_db.current_context_count) {
-		shared_mem_release(hash_test_db.contexts);
-		hash_test_db.max_contexts = 0;
-		return;
-	}
-
-	/* Nothing to do, if the deleted context is the last one in memory. */
-	if (context == (hash_test_db.contexts +
-			hash_test_db.current_context_count))
-		return;
-
-	memcpy(context,
-	       hash_test_db.contexts + hash_test_db.current_context_count,
-	       sizeof(*context));
-}
-
-static uint16_t do_software_hmac(TPM_ALG_ID alg, uint32_t in_len, uint8_t *in,
-				 uint32_t out_len, uint8_t *out)
-{
-	CPRI_HASH_STATE hstate;
-	TPM2B_MAX_HASH_BLOCK hmacKey;
-	uint8_t *key;
-	uint32_t key_len;
-	const uint16_t digest_len = _cpri__GetDigestSize(alg);
-
-	if (digest_len == 0)
-		return 0;
-	key = in + in_len;
-	key_len = *key++;
-	key_len = key_len * 256 + *key++;
-	_cpri__StartHMAC(alg, 0, &hstate, key_len, key, &hmacKey.b);
-	_cpri__UpdateHash(&hstate, in_len, in);
-	out_len = _cpri__CompleteHMAC(&hstate, &hmacKey.b, out_len, out);
-	return out_len;
-}
-
-static uint16_t do_dcrypto_hmac(TPM_ALG_ID alg, uint32_t in_len,
-				uint8_t *in, int32_t out_len, uint8_t *out)
-{
-	LITE_HMAC_CTX ctx;
-	uint8_t *key;
-	uint32_t key_len;
-
-	/* Dcrypto only support SHA-256 */
-	if (alg != TPM_ALG_SHA256)
-		return 0;
-	key = in + in_len;
-	key_len = *key++;
-	key_len = key_len * 256 + *key++;
-	DCRYPTO_HMAC_SHA256_init(&ctx, key, key_len);
-	HASH_update(&ctx.hash, in, in_len);
-	out_len = MIN(out_len, SHA256_DIGEST_SIZE);
-	memcpy(out, DCRYPTO_HMAC_final(&ctx), out_len);
-	return out_len;
-}
-
-enum hash_cmd {
-	CMD_HASH_START = 0,
-	CMD_HASH_CONTINUE = 1,
-	CMD_HASH_FINISH = 2,
-	CMD_HASH = 3,
-	CMD_SW_HMAC = 4,
-	CMD_HW_HMAC = 5
-};
-
-enum hash_alg {
-	HASH_ALG_SHA1 = 0,
-	HASH_ALG_SHA256 = 1,
-	HASH_ALG_SHA384 = 2,
-	HASH_ALG_SHA512 = 3
-};
-
-static void hash_command_handler(void *cmd_body,
-				size_t cmd_size,
-				size_t *response_size)
-{
-	enum hash_cmd hash_cmd;
-	enum hash_alg hash_alg;
-	int handle;
-	uint16_t text_len;
-	uint8_t *cmd;
-	size_t response_room = *response_size;
-	TPM_ALG_ID alg;
-
-	cmd = cmd_body;
-
-	/*
-	 * Empty response is sent as a success indication when the digest is
-	 * not yet expected (i.e. in response to 'start' and 'cont' commands,
-	 * as defined below).
-	 *
-	 * Single byte responses indicate errors, test successes are
-	 * communicated as responses of the size of the appropriate digests.
-	 */
-	*response_size = 0;
-
-	/*
-	 * Command structure, shared out of band with the test driver running
-	 * on the host:
-	 *
-	 * field     |    size  |                  note
-	 * ===================================================================
-	 * hash_cmd  |    1     | 0 - start, 1 - cont., 2 - finish, 3 - single
-	 *           |          | 4 - SW HMAC single shot (TPM code)
-	 *           |          | 5 - HW HMAC SHA256 single shot (dcrypto code)
-	 * hash_alg  |    1     | 0 - sha1, 1 - sha256, 2 - sha384, 3 - sha512
-	 * handle    |    1     | session handle, ignored in 'single' mode
-	 * text_len  |    2     | size of the text to process, big endian
-	 * text      | text_len | text to hash
-	 * for HMAC single shot only:
-	 * key_len   |    2     | size of the key for HMAC, big endian
-	 * key       | key_len  | key for HMAC single shot
-	 */
-
-	hash_cmd = *cmd++;
-	hash_alg = *cmd++;
-	handle = *cmd++;
-	text_len = *cmd++;
-	text_len = text_len * 256 + *cmd++;
-
-	switch (hash_alg) {
-	case HASH_ALG_SHA1:
-		alg = TPM_ALG_SHA1;
-		break;
-	case HASH_ALG_SHA256:
-		alg = TPM_ALG_SHA256;
-		break;
-#ifdef SHA512_SUPPORT
-	case HASH_ALG_SHA384:
-		alg = TPM_ALG_SHA384;
-		break;
-	case HASH_ALG_SHA512:
-		alg = TPM_ALG_SHA512;
-		break;
-#endif
-	default:
-		return;
-	}
-
-	switch (hash_cmd) {
-	case CMD_HASH_START: /* Start a new hash context. */
-		process_start(alg, handle, cmd_body, response_size);
-		if (*response_size)
-			break; /* Something went wrong. */
-		process_continue(handle, cmd, text_len,
-				 cmd_body, response_size);
-		break;
-
-	case CMD_HASH_CONTINUE:
-		process_continue(handle, cmd, text_len,
-				 cmd_body, response_size);
-		break;
-
-	case CMD_HASH_FINISH:
-		process_continue(handle, cmd, text_len,
-				 cmd_body, response_size);
-		if (*response_size)
-			break;  /* Something went wrong. */
-
-		process_finish(handle, cmd_body, response_size);
-		CPRINTF("%s:%d response size %d\n", __func__, __LINE__,
-			*response_size);
-		break;
-
-	case CMD_HASH: /* Process a buffer in a single shot. */
-		/*
-		 * Error responses are just 1 byte in size, valid responses
-		 * are of various hash sizes.
-		 */
-		*response_size = _cpri__HashBlock(alg, text_len,
-						  cmd, response_room, cmd_body);
-		CPRINTF("%s:%d response size %d\n", __func__,
-			__LINE__, *response_size);
-		break;
-	case CMD_SW_HMAC: /* SW HMAC SHA-256 (key, value) in a single shot. */
-		/*
-		 * Error responses are just 1 byte in size, valid responses
-		 * are of various hash sizes.
-		 */
-		*response_size = do_software_hmac(alg, text_len, cmd,
-						  response_room, cmd_body);
-		CPRINTF("%s:%d hmac response size %d\n", __func__, __LINE__,
-			*response_size);
-		break;
-	case CMD_HW_HMAC: /* HW HMAC SHA-256 (key, value) in a single shot */
-		/*
-		 * Error responses are just 1 byte in size, valid responses
-		 * are of various hash sizes.
-		 */
-		*response_size = do_dcrypto_hmac(alg, text_len, cmd,
-						 response_room, cmd_body);
-		CPRINTF("%s:%d hmac response size %d\n", __func__, __LINE__,
-			*response_size);
-		break;
-
-	default:
-		break;
-	}
-}
-
-DECLARE_EXTENSION_COMMAND(EXTENSION_HASH, hash_command_handler);
-
-#endif   /* CRYPTO_TEST_SETUP */
diff --git a/board/cr50/tpm2/hash_data.c b/board/cr50/tpm2/hash_data.c
deleted file mode 100644
index 6e6ad8aa4d..0000000000
--- a/board/cr50/tpm2/hash_data.c
+++ /dev/null
@@ -1,11 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#include "CryptoEngine.h"
-
-/*
- * This is unfortunate, but this is the only way to bring in necessary data
- * from the TPM2 library, as this file is not compiled in embedded mode.
- */
-#include "CpriHashData.c"
diff --git a/board/cr50/tpm2/hkdf.c b/board/cr50/tpm2/hkdf.c
deleted file mode 100644
index dcc494af16..0000000000
--- a/board/cr50/tpm2/hkdf.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "dcrypto.h"
-
-#ifdef CRYPTO_TEST_SETUP
-
-#include "extension.h"
-
-enum {
-	TEST_RFC = 0,
-};
-
-#define MAX_OKM_BYTES 1024
-
-static void hkdf_command_handler(void *cmd_body,
-				size_t cmd_size,
-				size_t *response_size)
-{
-	uint8_t *cmd;
-	uint8_t *out;
-	uint8_t op;
-	size_t salt_len;
-	const uint8_t *salt;
-	size_t IKM_len;
-	const uint8_t *IKM;
-	size_t info_len;
-	const uint8_t *info;
-	size_t OKM_len;
-	uint8_t OKM[MAX_OKM_BYTES];
-
-	/* Command format.
-	 *
-	 *   WIDTH	   FIELD
-	 *   1		   OP
-	 *   1             MSB SALT LEN
-	 *   1             LSB SALT LEN
-	 *   SALT_LEN      SALT
-	 *   1             MSB IKM LEN
-	 *   1             LSB IKM LEN
-	 *   IKM_LEN       IKM
-	 *   1             MSB INFO LEN
-	 *   1             LSB INFO LEN
-	 *   INFO_LEN      INFO
-	 *   1             MSB OKM LEN
-	 *   1             LSB OKM LEN
-	 */
-	cmd = (uint8_t *) cmd_body;
-	out = (uint8_t *) cmd_body;
-	op = *cmd++;
-
-	salt_len = ((uint16_t) (cmd[0] << 8)) | cmd[1];
-	cmd += 2;
-	salt = cmd;
-	cmd += salt_len;
-
-	IKM_len = ((uint16_t) (cmd[0] << 8)) | cmd[1];
-	cmd += 2;
-	IKM = cmd;
-	cmd += IKM_len;
-
-	info_len = ((uint16_t) (cmd[0] << 8)) | cmd[1];
-	cmd += 2;
-	info = cmd;
-	cmd += info_len;
-
-	OKM_len = ((uint16_t) (cmd[0] << 8)) | cmd[1];
-
-	if (OKM_len > MAX_OKM_BYTES) {
-		*response_size = 0;
-		return;
-	}
-
-	switch (op) {
-	case TEST_RFC:
-		if (DCRYPTO_hkdf(OKM, OKM_len, salt, salt_len,
-					IKM, IKM_len, info, info_len)) {
-			memcpy(out, OKM, OKM_len);
-			*response_size = OKM_len;
-		} else {
-			*response_size = 0;
-		}
-		break;
-	default:
-		*response_size = 0;
-	}
-}
-
-DECLARE_EXTENSION_COMMAND(EXTENSION_HKDF, hkdf_command_handler);
-
-#endif   /* CRYPTO_TEST_SETUP */
diff --git a/board/cr50/tpm2/manufacture.c b/board/cr50/tpm2/manufacture.c
deleted file mode 100644
index b2c214c38e..0000000000
--- a/board/cr50/tpm2/manufacture.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "console.h"
-#include "tpm_manufacture.h"
-
-#include "Global.h"
-#include "NV_fp.h"
-#include "Platform.h"
-#include "TPM_Types.h"
-#include "TpmBuildSwitches.h"
-#include "tpm_types.h"
-
-#define CPRINTF(format, args...) cprintf(CC_EXTENSION, format, ## args)
-
-#define EK_CERT_NV_START_INDEX  0x01C00000
-
-int tpm_manufactured(void)
-{
-	uint32_t nv_ram_index;
-	const uint32_t rsa_ek_nv_index = EK_CERT_NV_START_INDEX;
-	const uint32_t ecc_ek_nv_index = EK_CERT_NV_START_INDEX + 1;
-
-	/*
-	 * If nvram_index (value written at NV RAM offset of zero) is all
-	 * ones, or either endorsement certificate is not installed, consider
-	 * the chip un-manufactured.
-	 *
-	 * Thus, wiping flash NV ram allows to re-manufacture the chip.
-	 */
-	_plat__NvMemoryRead(0, sizeof(nv_ram_index), &nv_ram_index);
-	if ((nv_ram_index == ~0) ||
-	    (NvIsUndefinedIndex(rsa_ek_nv_index) == TPM_RC_SUCCESS) ||
-	    (NvIsUndefinedIndex(ecc_ek_nv_index) == TPM_RC_SUCCESS)) {
-		CPRINTF("%s: NOT manufactured\n", __func__);
-		return 0;
-	}
-
-	CPRINTF("%s: manufactured\n", __func__);
-	return 1;
-}
diff --git a/board/cr50/tpm2/mfg_nvmem_allocations.txt b/board/cr50/tpm2/mfg_nvmem_allocations.txt
deleted file mode 100644
index a17a71b7f1..0000000000
--- a/board/cr50/tpm2/mfg_nvmem_allocations.txt
+++ /dev/null
@@ -1,24 +0,0 @@
-A range of NV indices are reserved for use by the TPM manufacturer,
-and can be allocated arbitrarily, without the need to consult the TCG,
-or any expectation that these be consistent across different models
-of TPM. See 'Registery of reserved TPM 2.0 handles and localities' for
-more details.
-
-The range allocated to TPM manufacturers is 0x01000000 - 0x013fffff
-
-This file documents indices that have been allocated as part of the TPM
-implementation in cr50.
-
-Index	       Description		Definition
-
-0x01001007     FIRMWARE_NV_INDEX	src/platform/vboot_reference/firmware/lib/include/rollback_index.h
-0x01001008     KERNEL_NV_INDEX		src/platform/vboot_reference/firmware/lib/include/rollback_index.h
-0x01001009     BACKUP_NV_INDEX		src/platform/vboot_reference/firmware/lib/include/rollback_index.h
-0x0100100a     FWMP_NV_INDEX		src/platform/vboot_reference/firmware/lib/include/rollback_index.h
-0x0100100b     REC_HASH_NV_INDEX	src/platform/vboot_reference/firmware/lib/include/rollback_index.h
-
-	       Virtual NV indices	src/platform/ec/board/cr50/tpm2/virtual_nvmem.c
-0x013fff00     BOARD_ID
-0x013fff01     SN_BITS
-- to -         Reserved
-0x013fffff
diff --git a/board/cr50/tpm2/nvmem_ops.c b/board/cr50/tpm2/nvmem_ops.c
deleted file mode 100644
index 4281d5f944..0000000000
--- a/board/cr50/tpm2/nvmem_ops.c
+++ /dev/null
@@ -1,32 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "Global.h"
-#include "NV_fp.h"
-#include "util.h"
-
-void nvmem_wipe_cache(void)
-{
-	/*
-	 * Inclusive list of NV indices not to be wiped out when invalidating
-	 * the cache.
-	 */
-	const uint16_t whitelist_range[] = { 0x1007, 0x100b };
-
-	NvSelectivelyInvalidateCache(whitelist_range);
-
-	/*
-	 * Wipe some confidential persistent data
-	 */
-	memset(&gp.ownerAuth, 0, sizeof(gp.ownerAuth));
-	memset(&gp.endorsementAuth, 0, sizeof(gp.endorsementAuth));
-	memset(&gp.lockoutAuth, 0, sizeof(gp.lockoutAuth));
-	memset(&gp.EPSeed, 0, sizeof(gp.EPSeed));
-	memset(&gp.SPSeed, 0, sizeof(gp.SPSeed));
-	memset(&gp.PPSeed, 0, sizeof(gp.PPSeed));
-	memset(&gp.phProof, 0, sizeof(gp.phProof));
-	memset(&gp.shProof, 0, sizeof(gp.shProof));
-	memset(&gp.ehProof, 0, sizeof(gp.ehProof));
-}
diff --git a/board/cr50/tpm2/platform.c b/board/cr50/tpm2/platform.c
deleted file mode 100644
index 07851b9a23..0000000000
--- a/board/cr50/tpm2/platform.c
+++ /dev/null
@@ -1,98 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "Platform.h"
-#include "TPM_Types.h"
-
-#include "ccd_config.h"
-#include "pinweaver.h"
-#include "tpm_nvmem.h"
-#include "trng.h"
-#include "u2f_impl.h"
-#include "util.h"
-#include "version.h"
-
-uint16_t _cpri__GenerateRandom(size_t random_size,
-			uint8_t *buffer)
-{
-	rand_bytes(buffer, random_size);
-	return random_size;
-}
-
-/*
- * Return the pointer to the character immediately after the first dash
- * encountered in the passed in string, or NULL if there is no dashes in the
- * string.
- */
-static const char *char_after_dash(const char *str)
-{
-	char c;
-
-	do {
-		c = *str++;
-
-		if (c == '-')
-			return str;
-	} while (c);
-
-	return NULL;
-}
-
-/*
- * The properly formatted build_info string has the ec code SHA1 after the
- * first dash, and tpm2 code sha1 after the second dash.
- */
-
-void   _plat__GetFwVersion(uint32_t *firmwareV1, uint32_t *firmwareV2)
-{
-	const char *ver_str = char_after_dash(build_info);
-
-	/* Just in case the build_info string is misformatted. */
-	*firmwareV1 = 0;
-	*firmwareV2 = 0;
-
-	if (!ver_str)
-		return;
-
-	*firmwareV1 = strtoi(ver_str, NULL, 16);
-
-	ver_str = char_after_dash(ver_str);
-	if (!ver_str)
-		return;
-
-	*firmwareV2 = strtoi(ver_str, NULL, 16);
-}
-
-void _plat__StartupCallback(void)
-{
-	pinweaver_init();
-
-	/*
-	 * Eventually, we'll want to allow CCD unlock with no password, so
-	 * enterprise policy can set a password to block CCD instead of locking
-	 * it out via the FWMP.
-	 *
-	 * When we do that, we'll allow unlock without password between a real
-	 * TPM startup (not just a resume) - which is this callback - and
-	 * explicit disabling of that feature via a to-be-created vendor
-	 * command.  That vendor command will be called after enterprize policy
-	 * is updated, or the device is determined not to be enrolled.
-	 *
-	 * But for now, we'll just block unlock entirely if no password is set,
-	 * so we don't yet need to tell CCD that a real TPM startup has
-	 * occurred.
-	 */
-}
-
-BOOL _plat__ShallSurviveOwnerClear(uint32_t  index)
-{
-	return index == HR_NV_INDEX + FWMP_NV_INDEX;
-}
-
-void _plat__OwnerClearCallback(void)
-{
-	/* Invalidate existing u2f registrations. */
-	u2f_gen_kek_seed(0 /* commit */);
-}
diff --git a/board/cr50/tpm2/rsa.c b/board/cr50/tpm2/rsa.c
deleted file mode 100644
index 70e14fba97..0000000000
--- a/board/cr50/tpm2/rsa.c
+++ /dev/null
@@ -1,1174 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "CryptoEngine.h"
-#include "Global.h"
-#include "Hierarchy_fp.h"
-
-#include "dcrypto.h"
-#include "trng.h"
-
-#include "cryptoc/util.h"
-
-#include <assert.h>
-
-TPM2B_BYTE_VALUE(4);
-TPM2B_BYTE_VALUE(32);
-
-static void reverse_tpm2b(TPM2B *b)
-{
-	reverse(b->buffer, b->size);
-}
-
-static int check_key(const RSA_KEY *key)
-{
-	if (key->publicKey->size & 0x3)
-		/* Only word-multiple sizes supported. */
-		return 0;
-	return 1;
-}
-
-static int check_encrypt_params(TPM_ALG_ID padding_alg, TPM_ALG_ID hash_alg,
-				enum padding_mode *padding,
-				enum hashing_mode *hashing)
-{
-	/* Initialize hashing for all padding types */
-	*hashing = HASH_SHA1;
-
-	if (padding_alg == TPM_ALG_RSAES) {
-		*padding = PADDING_MODE_PKCS1;
-	} else if (padding_alg == TPM_ALG_OAEP) {
-		/* Only SHA1 and SHA256 supported with OAEP. */
-		if (hash_alg == TPM_ALG_SHA256)
-			*hashing = HASH_SHA256;
-		else if (hash_alg != TPM_ALG_SHA1)
-			/* Unsupported hash algorithm. */
-			return 0;
-		*padding = PADDING_MODE_OAEP;
-	} else if (padding_alg == TPM_ALG_NULL) {
-		*padding = PADDING_MODE_NULL;
-	} else {
-		return 0;  /* Unsupported padding mode. */
-	}
-	return 1;
-}
-
-static int check_sign_params(TPM_ALG_ID padding_alg, TPM_ALG_ID hash_alg,
-			enum padding_mode *padding,
-			enum hashing_mode *hashing)
-{
-	if (padding_alg == TPM_ALG_RSASSA ||
-		padding_alg == TPM_ALG_RSAPSS) {
-		if (hash_alg == TPM_ALG_SHA1)
-			*hashing = HASH_SHA1;
-		else if (hash_alg == TPM_ALG_SHA256)
-			*hashing = HASH_SHA256;
-		else if (hash_alg == ALG_SHA384_VALUE &&
-			 padding_alg == TPM_ALG_RSASSA)
-			*hashing = HASH_SHA384;
-		else if (hash_alg == ALG_SHA512_VALUE &&
-			 padding_alg == TPM_ALG_RSASSA)
-			*hashing = HASH_SHA512;
-#if defined(SUPPORT_PADDING_ONLY_RSASSA) && SUPPORT_PADDING_ONLY_RSASSA == YES
-		else if (hash_alg == TPM_ALG_NULL &&
-			 padding_alg == TPM_ALG_RSASSA)
-			*hashing = HASH_NULL;
-#endif
-		else
-			return 0;
-		if (padding_alg == TPM_ALG_RSASSA)
-			*padding = PADDING_MODE_PKCS1;
-		else
-			*padding = PADDING_MODE_PSS;
-	} else {
-		return 0;
-	}
-	return 1;
-}
-
-CRYPT_RESULT _cpri__EncryptRSA(uint32_t *out_len, uint8_t *out,
-			RSA_KEY *key, TPM_ALG_ID padding_alg,
-			uint32_t in_len, uint8_t *in,
-			TPM_ALG_ID hash_alg, const char *label)
-{
-	struct RSA rsa;
-	enum padding_mode padding;
-	enum hashing_mode hashing;
-	int result;
-
-	if (!check_key(key))
-		return CRYPT_FAIL;
-	if (!check_encrypt_params(padding_alg, hash_alg, &padding, &hashing))
-		return CRYPT_FAIL;
-
-	reverse_tpm2b(key->publicKey);
-	rsa.e = key->exponent;
-	rsa.N.dmax = key->publicKey->size / sizeof(uint32_t);
-	rsa.N.d = (struct access_helper *) &key->publicKey->buffer;
-	rsa.d.dmax = 0;
-	rsa.d.d = NULL;
-
-	result = DCRYPTO_rsa_encrypt(&rsa, out, out_len, in, in_len, padding,
-				hashing, label);
-
-	reverse_tpm2b(key->publicKey);
-
-	if (result)
-		return CRYPT_SUCCESS;
-	else
-		return CRYPT_FAIL;
-}
-
-CRYPT_RESULT _cpri__DecryptRSA(uint32_t *out_len, uint8_t *out,
-			RSA_KEY *key, TPM_ALG_ID padding_alg,
-			uint32_t in_len, uint8_t *in,
-			TPM_ALG_ID hash_alg, const char *label)
-{
-	struct RSA rsa;
-	enum padding_mode padding;
-	enum hashing_mode hashing;
-	int result;
-
-	if (!check_key(key))
-		return CRYPT_FAIL;
-	if (!check_encrypt_params(padding_alg, hash_alg, &padding, &hashing))
-		return CRYPT_FAIL;
-
-	reverse_tpm2b(key->publicKey);
-	reverse_tpm2b(key->privateKey);
-
-	rsa.e = key->exponent;
-	rsa.N.dmax = key->publicKey->size / sizeof(uint32_t);
-	rsa.N.d = (struct access_helper *) &key->publicKey->buffer;
-	rsa.d.dmax = key->privateKey->size / sizeof(uint32_t);
-	rsa.d.d = (struct access_helper *) &key->privateKey->buffer;
-
-	result = DCRYPTO_rsa_decrypt(&rsa, out, out_len, in, in_len, padding,
-				hashing, label);
-
-	reverse_tpm2b(key->publicKey);
-	reverse_tpm2b(key->privateKey);
-
-	if (result)
-		return CRYPT_SUCCESS;
-	else
-		return CRYPT_FAIL;
-}
-
-CRYPT_RESULT _cpri__SignRSA(uint32_t *out_len, uint8_t *out,
-			RSA_KEY *key, TPM_ALG_ID padding_alg,
-			TPM_ALG_ID hash_alg, uint32_t in_len, uint8_t *in)
-{
-	struct RSA rsa;
-	enum padding_mode padding;
-	enum hashing_mode hashing;
-	int result;
-
-	if (!check_key(key))
-		return CRYPT_FAIL;
-	if (!check_sign_params(padding_alg, hash_alg, &padding, &hashing))
-		return CRYPT_FAIL;
-
-	reverse_tpm2b(key->publicKey);
-	reverse_tpm2b(key->privateKey);
-
-	rsa.e = key->exponent;
-	rsa.N.dmax = key->publicKey->size / sizeof(uint32_t);
-	rsa.N.d = (struct access_helper *) &key->publicKey->buffer;
-	rsa.d.dmax = key->privateKey->size / sizeof(uint32_t);
-	rsa.d.d = (struct access_helper *) &key->privateKey->buffer;
-
-	/* TPM2 wrapper function fails to initialize out_len! */
-	*out_len = key->publicKey->size;
-	result = DCRYPTO_rsa_sign(&rsa, out, out_len, in, in_len,
-				padding, hashing);
-
-	reverse_tpm2b(key->publicKey);
-	reverse_tpm2b(key->privateKey);
-
-	if (result)
-		return CRYPT_SUCCESS;
-	else
-		return CRYPT_FAIL;
-}
-
-CRYPT_RESULT _cpri__ValidateSignatureRSA(
-	RSA_KEY *key, TPM_ALG_ID padding_alg, TPM_ALG_ID hash_alg,
-	uint32_t digest_len, uint8_t *digest, uint32_t sig_len,
-	uint8_t *sig, uint16_t salt_len)
-{
-	struct RSA rsa;
-	enum padding_mode padding;
-	enum hashing_mode hashing;
-	int result;
-
-	if (!check_key(key))
-		return CRYPT_FAIL;
-	if (!check_sign_params(padding_alg, hash_alg, &padding, &hashing))
-		return CRYPT_FAIL;
-
-	reverse_tpm2b(key->publicKey);
-
-	rsa.e = key->exponent;
-	rsa.N.dmax = key->publicKey->size / sizeof(uint32_t);
-	rsa.N.d = (struct access_helper *) &key->publicKey->buffer;
-	rsa.d.dmax = 0;
-	rsa.d.d = NULL;
-
-	result = DCRYPTO_rsa_verify(&rsa, digest, digest_len, sig, sig_len,
-				padding, hashing);
-
-	reverse_tpm2b(key->publicKey);
-
-	if (result)
-		return CRYPT_SUCCESS;
-	else
-		return CRYPT_FAIL;
-}
-
-CRYPT_RESULT _cpri__TestKeyRSA(TPM2B *d_buf, uint32_t e,
-			TPM2B *N_buf, TPM2B *p_buf, TPM2B *q_buf)
-{
-	struct LITE_BIGNUM N;
-	struct LITE_BIGNUM p;
-	struct LITE_BIGNUM q;
-	struct LITE_BIGNUM d;
-	int result;
-
-	if (!p_buf)
-		return CRYPT_PARAMETER;
-	if (q_buf && p_buf->size != q_buf->size)
-		return CRYPT_PARAMETER;
-	if (N_buf->size != p_buf->size * 2)
-		return CRYPT_PARAMETER;  /* Insufficient output buffer space. */
-	if (N_buf->size > RSA_MAX_BYTES)
-		return CRYPT_PARAMETER;  /* Unsupported key size. */
-
-	DCRYPTO_bn_wrap(&N, N_buf->buffer, N_buf->size);
-	DCRYPTO_bn_wrap(&p, p_buf->buffer, p_buf->size);
-	reverse_tpm2b(N_buf);
-	reverse_tpm2b(p_buf);
-	if (q_buf) {
-		DCRYPTO_bn_wrap(&q, q_buf->buffer, q_buf->size);
-		reverse_tpm2b(q_buf);
-	}
-	/* d_buf->size may be uninitialized. */
-	DCRYPTO_bn_wrap(&d, d_buf->buffer, N_buf->size);
-
-	result = DCRYPTO_rsa_key_compute(&N, &d, &p, q_buf ? &q : NULL, e);
-
-	reverse_tpm2b(N_buf);
-	reverse_tpm2b(p_buf);
-	if (q_buf)
-		reverse_tpm2b(q_buf);
-
-	if (result) {
-		d_buf->size = N_buf->size;
-		reverse_tpm2b(d_buf);
-		return CRYPT_SUCCESS;
-	} else {
-		return CRYPT_FAIL;
-	}
-}
-
-/* Each 1024-bit prime generation attempt fails with probability
- * ~0.5%.  Setting an upper limit on the attempts allows for an
- * application to display a message and then reattempt.
- * TODO(ngm): tweak this value along with performance improvements. */
-#define MAX_GENERATE_ATTEMPTS 3
-
-static int generate_prime(struct LITE_BIGNUM *b, TPM_ALG_ID hashing,
-			TPM2B *seed, const char *label, TPM2B *extra,
-			uint32_t *counter)
-{
-	TPM2B_4_BYTE_VALUE marshaled_counter = { .t = {4} };
-	uint32_t i;
-
-	for (i = 0; i < MAX_GENERATE_ATTEMPTS; i++) {
-		UINT32_TO_BYTE_ARRAY(*counter, marshaled_counter.t.buffer);
-		_cpri__KDFa(hashing, seed, label, extra, &marshaled_counter.b,
-			bn_bits(b), (uint8_t *) b->d, NULL, FALSE);
-
-		(*counter)++;           /* Mark as used. */
-		if (DCRYPTO_bn_generate_prime(b))
-			return 1;
-	}
-
-	return 0;
-}
-
-#ifdef CRYPTO_TEST_SETUP
-static const uint8_t VERIFY_SEED[32] = {
-	0x54, 0xef, 0xe3, 0xe9, 0x1e, 0xfa, 0xad, 0x9b,
-	0x18, 0x3f, 0x27, 0x12, 0xfd, 0xe7, 0xfb, 0xc6,
-	0x60, 0xcc, 0x34, 0x05, 0x00, 0x7d, 0x21, 0x6e,
-	0xc2, 0x1e, 0x78, 0xbe, 0x61, 0xc8, 0x41, 0x99
-};
-#endif
-
-/* The array below represents the output of ObjectComputeName() when
- * applied to the TPMT_PUBLIC RSA template described in the TPM 2.0
- * EK Credential Profile specification: https://goo.gl/rbE6q7
- */
-static const uint8_t TPM2_RSA_EK_NAME_TEMPLATE[] = {
-	/* TPM_ALG_SHA256 in big endian. */
-	0x00, 0x0b,
-	/* SHA256 digest of the default template TPMT_PUBLIC. */
-	0x32, 0x50, 0x39, 0x29, 0xa1, 0x28, 0x7e, 0xed,
-	0xaa, 0x3e, 0x89, 0xd9, 0x32, 0xf9, 0xb5, 0x1a,
-	0x6f, 0x92, 0xab, 0xd0, 0xfa, 0x57, 0x72, 0x1f,
-	0xfa, 0x6f, 0xc0, 0x41, 0xe0, 0x4f, 0x74, 0x98
-};
-BUILD_ASSERT(sizeof(TPM2_RSA_EK_NAME_TEMPLATE) == 2 + SHA256_DIGEST_SIZE);
-
-/* The array below represents the 'name' (corresponding to the
- * parameter extra) used by the CR50 certificate authority when
- * generating the endorsement certificate.
- */
-static const uint8_t TPM2_RSA_EK_NAME_CR50[] = {
-	0x68, 0xd1, 0xa2, 0x41, 0xfb, 0x27, 0x2f, 0x03,
-	0x90, 0xbf, 0xd0, 0x42, 0x8d, 0xad, 0xee, 0xb0,
-	0x2b, 0xf4, 0xa1, 0xcd, 0x46, 0xab, 0x6c, 0x39,
-	0x1b, 0xa3, 0x1f, 0x51, 0x87, 0x06, 0x8e, 0x6a
-};
-BUILD_ASSERT(sizeof(TPM2_RSA_EK_NAME_CR50) == SHA256_DIGEST_SIZE);
-
-CRYPT_RESULT _cpri__GenerateKeyRSA(
-	TPM2B *N_buf, TPM2B *p_buf, uint16_t num_bits,
-	uint32_t e_buf, TPM_ALG_ID hashing, TPM2B *seed,
-	const char *label, TPM2B *extra, uint32_t *counter_in)
-{
-	const char *label_p = "RSA p!";
-	const char *label_q = "RSA q!";
-	/* Numbers from NIST SP800-57.
-	 * Fallback conservatively for keys larger than 2048 bits. */
-	const uint32_t security_strength =
-		num_bits <= 1024 ? 80 :
-		num_bits <= 2048 ? 112 :
-		256;
-
-	const uint16_t num_bytes = num_bits / 8;
-	uint8_t q_buf[RSA_MAX_BYTES / 2];
-
-	struct LITE_BIGNUM e;
-	struct LITE_BIGNUM p;
-	struct LITE_BIGNUM q;
-	struct LITE_BIGNUM N;
-
-	uint32_t counter = 0;
-	TPM2B_32_BYTE_VALUE local_seed = { .t = {32} };
-	TPM2B_32_BYTE_VALUE local_extra = { .t = {32} };
-
-	const TPM2B_SEED *endorsement_seed = HierarchyGetPrimarySeed(
-		TPM_RH_ENDORSEMENT);
-
-	if (num_bits & 0xF)
-		return CRYPT_FAIL;
-	if (num_bytes > RSA_MAX_BYTES)
-		return CRYPT_FAIL;
-	/* Seed size must be at least 2*security_strength per TPM 2.0 spec. */
-	if (seed == NULL || seed->size * 8 < 2 * security_strength)
-		return CRYPT_FAIL;
-
-	/* When generating the endorsement primary key (based on the
-	 * TPM 2.0 standard template, swap in the vendor specific
-	 * template instead.
-	 */
-	if (extra->size == sizeof(TPM2_RSA_EK_NAME_TEMPLATE) &&
-		DCRYPTO_equals(extra->buffer, TPM2_RSA_EK_NAME_TEMPLATE,
-			       sizeof(TPM2_RSA_EK_NAME_TEMPLATE)) &&
-		seed == &endorsement_seed->b) {
-		memcpy(local_extra.b.buffer, TPM2_RSA_EK_NAME_CR50,
-			sizeof(TPM2_RSA_EK_NAME_CR50));
-		extra = &local_extra.b;
-	}
-
-	/* Hash down the primary seed for RSA key generation, so that
-	 * the derivation tree is distinct from ECC key derivation.
-	 */
-#ifdef CRYPTO_TEST_SETUP
-	if (seed->size == sizeof(VERIFY_SEED) &&
-		DCRYPTO_equals(seed->buffer, VERIFY_SEED, seed->size)) {
-		/* Test seed has already been hashed down. */
-		memcpy(local_seed.t.buffer, seed->buffer, seed->size);
-	} else
-#endif
-	{
-		LITE_HMAC_CTX hmac;
-
-		DCRYPTO_HMAC_SHA256_init(&hmac, seed->buffer, seed->size);
-		HASH_update(&hmac.hash, "RSA", 4);
-		memcpy(local_seed.t.buffer, DCRYPTO_HMAC_final(&hmac),
-			local_seed.t.size);
-	}
-
-	if (e_buf == 0)
-		e_buf = RSA_F4;
-
-	DCRYPTO_bn_wrap(&e, &e_buf, sizeof(e_buf));
-	DCRYPTO_bn_wrap(&p, p_buf->buffer, num_bytes / 2);
-	DCRYPTO_bn_wrap(&q, q_buf, num_bytes / 2);
-
-	if (label == NULL)
-		label = label_p;
-
-	/* The manufacture process uses a counter of 1, whereas the
-	 * TPM2.0 library (CryptGenerateKeyRSA) passes in a counter
-	 * value of 0.  Having that the counter always start at least
-	 * at 1 ensures that endorsement keys are correctly generated.
-	 * For non-endorsement keys, the counter value used is
-	 * immaterial, as the generation process remains deterministic.
-	 */
-	if (counter_in != NULL)
-		counter = *counter_in;
-	counter++;
-
-	if (!generate_prime(&p, hashing, &local_seed.b, label, extra,
-			    &counter)) {
-		if (counter_in != NULL)
-			*counter_in = counter;
-		always_memset(local_seed.t.buffer, 0, local_seed.t.size);
-		return CRYPT_FAIL;
-	}
-
-	if (label == label_p)
-		label = label_q;
-	if (!generate_prime(&q, hashing, &local_seed.b, label, extra,
-			    &counter)) {
-		if (counter_in != NULL)
-			*counter_in = counter;
-		always_memset(local_seed.t.buffer, 0, local_seed.t.size);
-		return CRYPT_FAIL;
-	}
-
-	if (counter_in != NULL)
-		*counter_in = counter;
-	N_buf->size = num_bytes;
-	p_buf->size = num_bytes / 2;
-	DCRYPTO_bn_wrap(&N, N_buf->buffer, num_bytes);
-	DCRYPTO_bn_mul(&N, &p, &q);
-	reverse_tpm2b(N_buf);
-	reverse_tpm2b(p_buf);
-	always_memset(q_buf, 0, sizeof(q_buf));
-	always_memset(local_seed.t.buffer, 0, local_seed.t.size);
-	return CRYPT_SUCCESS;
-}
-
-#ifdef CRYPTO_TEST_SETUP
-
-#include "extension.h"
-
-enum {
-	TEST_RSA_ENCRYPT = 0,
-	TEST_RSA_DECRYPT = 1,
-	TEST_RSA_SIGN = 2,
-	TEST_RSA_VERIFY = 3,
-	TEST_RSA_KEYGEN = 4,
-	TEST_RSA_KEYTEST = 5,
-	TEST_BN_PRIMEGEN = 6,
-	TEST_X509_VERIFY = 7,
-};
-
-/* Test support for RSA 2k (signing / encryption) and RSA 4k
- * (verification) without changing the default value for
- * MAX_RSA_KEY_BYTES (which corresponds to RSA 2k) in
- * tpm2/tpm_types.h.
- */
-TPM2B_BYTE_VALUE(512);
-
-static const TPM2B_512_BYTE_VALUE RSA_768_N = {
-	.t = {96, {
-			0xb0, 0xdb, 0xed, 0x46, 0xd9, 0x32, 0xf0, 0x7c,
-			0xd4, 0x20, 0x23, 0xd2, 0x35, 0x5a, 0x86, 0x17,
-			0xdb, 0x24, 0x72, 0x36, 0x33, 0x3b, 0xc2, 0x64,
-			0x8b, 0xa4, 0x49, 0x6e, 0x74, 0xfe, 0xfa, 0xd2,
-			0x82, 0x0c, 0xc4, 0x12, 0x3a, 0x48, 0x67, 0xe1,
-			0x15, 0xcc, 0x94, 0xdf, 0x44, 0x1b, 0x4e, 0xc0,
-			0x18, 0xba, 0x46, 0x1b, 0x51, 0x2c, 0xe2, 0x0f,
-			0xc0, 0x32, 0x77, 0xed, 0x5f, 0x8b, 0xe5, 0xa3,
-			0x00, 0xe6, 0x3c, 0x2d, 0xa7, 0x10, 0x89, 0x53,
-			0xa8, 0x2b, 0x33, 0x74, 0x38, 0xf7, 0x36, 0x00,
-			0xfd, 0xdd, 0x5b, 0xbd, 0x7b, 0xc1, 0x7c, 0xe1,
-			0x75, 0x90, 0x2b, 0x78, 0x2d, 0x39, 0x85, 0x69
-		}
-	}
-};
-
-static const TPM2B_512_BYTE_VALUE RSA_768_D = {
-	.t = {96, {
-			0xae, 0xad, 0xb9, 0x50, 0x25, 0x8c, 0x1b, 0x5c,
-			0x9f, 0x42, 0xd3, 0x3e, 0x76, 0x75, 0xdf, 0x45,
-			0x46, 0xab, 0x5b, 0xa6, 0xce, 0xb9, 0x72, 0x49,
-			0x4e, 0x66, 0xc8, 0x24, 0x31, 0xa7, 0xf9, 0x61,
-			0xdb, 0x12, 0xf2, 0xc1, 0x32, 0x11, 0x7b, 0x90,
-			0x23, 0xb0, 0xb9, 0x45, 0x3f, 0x06, 0x5d, 0xa2,
-			0xd7, 0x35, 0x0f, 0xdd, 0xfc, 0x03, 0xdf, 0x8d,
-			0x91, 0x6b, 0x83, 0xf9, 0x59, 0xee, 0x67, 0x1e,
-			0x1a, 0x20, 0x9e, 0x8b, 0xf8, 0xf6, 0xe2, 0xb2,
-			0xf5, 0x29, 0x71, 0x4c, 0x22, 0x54, 0xcf, 0x7e,
-			0x97, 0xbc, 0x70, 0x24, 0xdd, 0x6d, 0x52, 0xfe,
-			0x17, 0xd9, 0xd6, 0x41, 0x7b, 0x76, 0x40, 0x01
-		}
-	}
-};
-
-static const TPM2B_512_BYTE_VALUE RSA_768_P = {
-	.t = {48, {
-			0xd6, 0x09, 0x64, 0xc8, 0xf3, 0x5c, 0x02, 0xc7,
-			0xc6, 0x47, 0x4e, 0x7f, 0x43, 0x9d, 0x31, 0x46,
-			0x7a, 0x33, 0x85, 0xa0, 0xa4, 0x16, 0xea, 0x22,
-			0x7b, 0xcd, 0x64, 0x9b, 0x50, 0xec, 0xa7, 0x2f,
-			0x7e, 0xcf, 0xeb, 0x69, 0x29, 0x34, 0x8e, 0xb7,
-			0xb5, 0xb3, 0xba, 0x7f, 0x9b, 0x01, 0x7d, 0x69
-		}
-	}
-};
-
-static const TPM2B_512_BYTE_VALUE RSA_768_Q = {
-	.t = {48, {
-			0xd3, 0x88, 0x92, 0x2d, 0xd5, 0xc6, 0x29, 0xf4,
-			0xf0, 0x2e, 0x61, 0xf0, 0x60, 0xad, 0xa9, 0x46,
-			0x11, 0xa9, 0x0c, 0x69, 0x14, 0x31, 0x09, 0x36,
-			0x8b, 0x70, 0x1b, 0x11, 0x9b, 0x26, 0x39, 0x34,
-			0x34, 0xfd, 0xf1, 0x9a, 0x89, 0x51, 0x63, 0x0a,
-			0xc6, 0x60, 0x0b, 0xba, 0x18, 0x8e, 0xc8, 0x01
-		}
-	}
-};
-
-static const TPM2B_512_BYTE_VALUE RSA_1024_N = {
-	.t = {128, {
-			0xdf, 0x4e, 0xaf, 0x73, 0x45, 0x94, 0x98, 0x34,
-			0x30, 0x7e, 0x26, 0xad, 0x40, 0x83, 0xf9, 0x17,
-			0x21, 0xb0, 0x4e, 0x1b, 0x0d, 0x6a, 0x44, 0xce,
-			0x4e, 0x3e, 0x2e, 0x72, 0x4c, 0x97, 0xdf, 0x89,
-			0x8a, 0x39, 0x10, 0x25, 0xae, 0x20, 0x4c, 0xf2,
-			0x3b, 0x20, 0xb2, 0xa5, 0x10, 0xdd, 0xb2, 0x6b,
-			0x62, 0x4e, 0xa6, 0x9f, 0x92, 0x4a, 0xd9, 0x86,
-			0x97, 0xcc, 0x70, 0x20, 0x3b, 0x6a, 0x32, 0x63,
-			0xca, 0x7f, 0x59, 0xfb, 0x57, 0xb6, 0xa9, 0x99,
-			0xe9, 0xd0, 0x2e, 0x0f, 0x1c, 0xd4, 0x7d, 0x8b,
-			0xa0, 0xbd, 0x0f, 0xd2, 0xd5, 0x3b, 0x1f, 0x11,
-			0xb4, 0x6a, 0x94, 0xcf, 0x4f, 0x0a, 0x2b, 0x44,
-			0xe7, 0xfa, 0x6b, 0x24, 0x91, 0xb4, 0x82, 0x1f,
-			0xf6, 0x75, 0xb6, 0x91, 0xc5, 0xa0, 0xf6, 0x2f,
-			0xd5, 0xff, 0x10, 0x73, 0x9b, 0x34, 0xf6, 0x7a,
-			0x88, 0x23, 0xa9, 0x42, 0x3c, 0xa8, 0x24, 0x91
-		}
-	}
-};
-
-static const TPM2B_512_BYTE_VALUE RSA_1024_D = {
-	.t = {128, {
-			0x9a, 0x6d, 0x85, 0xf4, 0x07, 0xa8, 0x6d, 0x61,
-			0x9a, 0x2f, 0x83, 0x7b, 0xc8, 0xe3, 0xfb, 0x7c,
-			0xbd, 0xb5, 0x79, 0x2e, 0x48, 0x26, 0xb7, 0x92,
-			0x9c, 0x95, 0x6f, 0xf5, 0x67, 0x76, 0x98, 0x06,
-			0x3b, 0xea, 0x9e, 0x7a, 0x10, 0x63, 0x12, 0x13,
-			0x6a, 0x44, 0x80, 0x86, 0x9a, 0x95, 0x56, 0x6f,
-			0xe0, 0xba, 0x57, 0x8c, 0x7e, 0xd4, 0xf8, 0x7d,
-			0x95, 0xb8, 0xb1, 0xc9, 0xf8, 0x8c, 0xc6, 0x6e,
-			0xe5, 0x7b, 0xa0, 0xaf, 0xa0, 0x4e, 0x4e, 0x84,
-			0xd7, 0x97, 0xb9, 0x5a, 0xdd, 0x32, 0xe5, 0x2b,
-			0xe5, 0x80, 0xb3, 0xb2, 0xbf, 0x56, 0xff, 0x01,
-			0xdc, 0xe6, 0xa6, 0x6c, 0x4a, 0x81, 0x1d, 0x8f,
-			0xea, 0x4b, 0xed, 0x24, 0x08, 0xf4, 0x67, 0xaf,
-			0x0d, 0xf2, 0xfd, 0x37, 0x3f, 0x31, 0x25, 0xfa,
-			0xee, 0x35, 0xb0, 0xdb, 0x66, 0x11, 0xff, 0x49,
-			0xe1, 0xe5, 0xff, 0x1b, 0xcc, 0xc3, 0x0e, 0x09
-		}
-	}
-};
-
-static const TPM2B_512_BYTE_VALUE RSA_1024_P = {
-	.t = {64, {
-			0xf9, 0x5e, 0x79, 0x65, 0x43, 0x70, 0x40, 0x83,
-			0x50, 0x0a, 0xbb, 0x61, 0xb3, 0x87, 0x7b, 0x24,
-			0x8f, 0x2a, 0x03, 0x5b, 0xb5, 0x4b, 0x94, 0x94,
-			0x67, 0xaa, 0x98, 0xd6, 0x14, 0x40, 0x90, 0x3c,
-			0xa4, 0x0d, 0x6d, 0x58, 0x31, 0xc5, 0x42, 0xf1,
-			0x2d, 0x15, 0x0e, 0xe7, 0xcd, 0xe6, 0x3e, 0xca,
-			0xd8, 0x94, 0x37, 0xaa, 0x4c, 0xd6, 0xf3, 0x21,
-			0x2e, 0xa4, 0xfe, 0x1d, 0x79, 0x44, 0xd7, 0xb3
-		}
-	}
-};
-
-static const TPM2B_512_BYTE_VALUE RSA_1024_Q = {
-	.t = {64, {
-			0xe5, 0x3e, 0xcd, 0x4b, 0x97, 0xc5, 0x96, 0x39,
-			0x70, 0x97, 0x3a, 0x10, 0xa9, 0xc3, 0x35, 0x0a,
-			0xd6, 0x2b, 0xf5, 0x12, 0x8d, 0xb2, 0xc0, 0x0b,
-			0x1c, 0x5f, 0xa0, 0x0b, 0x86, 0x83, 0xa7, 0x90,
-			0xe9, 0xf8, 0x16, 0x92, 0x9f, 0xce, 0x13, 0x4c,
-			0x14, 0xe8, 0x9e, 0x4c, 0x24, 0xef, 0xff, 0x58,
-			0x22, 0x06, 0xf9, 0xcf, 0xfd, 0x19, 0xb7, 0x23,
-			0xf9, 0xe3, 0xb3, 0xe3, 0x7a, 0x9b, 0xb0, 0xab
-		}
-	}
-};
-
-static const TPM2B_512_BYTE_VALUE RSA_2048_N = {
-	.t = {256, {
-			0x9c, 0xd7, 0x61, 0x2e, 0x43, 0x8e, 0x15, 0xbe,
-			0xcd, 0x73, 0x9f, 0xb7, 0xf5, 0x86, 0x4b, 0xe3,
-			0x95, 0x90, 0x5c, 0x85, 0x19, 0x4c, 0x1d, 0x2e,
-			0x2c, 0xef, 0x6e, 0x1f, 0xed, 0x75, 0x32, 0x0f,
-			0x0a, 0xc1, 0x72, 0x9f, 0x0c, 0x78, 0x50, 0xa2,
-			0x99, 0x82, 0x53, 0x90, 0xbe, 0x64, 0x23, 0x49,
-			0x75, 0x7b, 0x0c, 0xeb, 0x2d, 0x68, 0x97, 0xd6,
-			0xaf, 0xb1, 0xaa, 0x2a, 0xde, 0x5e, 0x9b, 0xe3,
-			0x06, 0x0d, 0xf2, 0xac, 0xd9, 0xd7, 0x1f, 0x50,
-			0x6e, 0xc9, 0x5d, 0xeb, 0xb4, 0xf0, 0xc0, 0x98,
-			0x23, 0x04, 0x30, 0x46, 0x10, 0xdc, 0xd4, 0x6b,
-			0x57, 0xc7, 0x30, 0xc3, 0x06, 0xdd, 0xaf, 0x51,
-			0x6e, 0x40, 0x41, 0xf8, 0x10, 0xde, 0x49, 0x18,
-			0x52, 0xb3, 0x18, 0xca, 0x49, 0x50, 0xa8, 0x3a,
-			0xcd, 0xb6, 0x94, 0x7b, 0xdb, 0xf1, 0x2d, 0x05,
-			0xce, 0x57, 0x0b, 0xbe, 0x38, 0x48, 0xbb, 0xc9,
-			0xb1, 0x76, 0x36, 0xb8, 0xa8, 0xcc, 0xe2, 0x07,
-			0x5c, 0xc8, 0x7b, 0xcf, 0xcf, 0xf0, 0xfa, 0xa3,
-			0xc5, 0xd7, 0x3a, 0x5e, 0xb2, 0xf4, 0xbf, 0xea,
-			0xc2, 0xed, 0x51, 0x16, 0xa2, 0x92, 0x9c, 0x36,
-			0xa6, 0x86, 0x0e, 0x24, 0xa5, 0x66, 0x15, 0xe7,
-			0x97, 0x22, 0x50, 0x04, 0xff, 0xc9, 0x4d, 0xb0,
-			0xbc, 0x27, 0x05, 0x5e, 0x2c, 0xf7, 0xef, 0xdc,
-			0x5d, 0x58, 0xa1, 0x3b, 0x60, 0x83, 0xb7, 0x8c,
-			0xb7, 0xd0, 0x36, 0x6d, 0x55, 0x2e, 0x05, 0x23,
-			0x63, 0x74, 0x4a, 0x97, 0x37, 0xa7, 0x78, 0x40,
-			0xef, 0x3e, 0x66, 0xfd, 0xba, 0x6e, 0xb3, 0x72,
-			0x4a, 0x21, 0x82, 0x1f, 0x33, 0xad, 0x62, 0x0c,
-			0xf2, 0x1a, 0xd2, 0x6a, 0xb5, 0xa7, 0xf2, 0x51,
-			0x69, 0x1f, 0x38, 0xa5, 0x57, 0x9a, 0xc5, 0x88,
-			0x67, 0xe3, 0x11, 0xa6, 0x53, 0x4f, 0xb1, 0xe9,
-			0x07, 0x41, 0xde, 0xe8, 0xdf, 0x93, 0xa9, 0x99
-		}
-	}
-};
-
-static const uint8_t RSA_2048_CERT[] = {
-	0x30, 0x82, 0x03, 0x5D, 0x30, 0x82, 0x02, 0x45,
-	0xA0, 0x03, 0x02, 0x01, 0x02, 0x02, 0x09, 0x00,
-	0xCB, 0x9D, 0x38, 0x47, 0x3F, 0x4F, 0x3B, 0xC6,
-	0x30, 0x0D, 0x06, 0x09, 0x2A, 0x86, 0x48, 0x86,
-	0xF7, 0x0D, 0x01, 0x01, 0x0B, 0x05, 0x00, 0x30,
-	0x45, 0x31, 0x0B, 0x30, 0x09, 0x06, 0x03, 0x55,
-	0x04, 0x06, 0x13, 0x02, 0x41, 0x55, 0x31, 0x13,
-	0x30, 0x11, 0x06, 0x03, 0x55, 0x04, 0x08, 0x0C,
-	0x0A, 0x53, 0x6F, 0x6D, 0x65, 0x2D, 0x53, 0x74,
-	0x61, 0x74, 0x65, 0x31, 0x21, 0x30, 0x1F, 0x06,
-	0x03, 0x55, 0x04, 0x0A, 0x0C, 0x18, 0x49, 0x6E,
-	0x74, 0x65, 0x72, 0x6E, 0x65, 0x74, 0x20, 0x57,
-	0x69, 0x64, 0x67, 0x69, 0x74, 0x73, 0x20, 0x50,
-	0x74, 0x79, 0x20, 0x4C, 0x74, 0x64, 0x30, 0x1E,
-	0x17, 0x0D, 0x31, 0x36, 0x30, 0x36, 0x30, 0x38,
-	0x32, 0x33, 0x34, 0x35, 0x32, 0x33, 0x5A, 0x17,
-	0x0D, 0x31, 0x36, 0x30, 0x37, 0x30, 0x38, 0x32,
-	0x33, 0x34, 0x35, 0x32, 0x33, 0x5A, 0x30, 0x45,
-	0x31, 0x0B, 0x30, 0x09, 0x06, 0x03, 0x55, 0x04,
-	0x06, 0x13, 0x02, 0x41, 0x55, 0x31, 0x13, 0x30,
-	0x11, 0x06, 0x03, 0x55, 0x04, 0x08, 0x0C, 0x0A,
-	0x53, 0x6F, 0x6D, 0x65, 0x2D, 0x53, 0x74, 0x61,
-	0x74, 0x65, 0x31, 0x21, 0x30, 0x1F, 0x06, 0x03,
-	0x55, 0x04, 0x0A, 0x0C, 0x18, 0x49, 0x6E, 0x74,
-	0x65, 0x72, 0x6E, 0x65, 0x74, 0x20, 0x57, 0x69,
-	0x64, 0x67, 0x69, 0x74, 0x73, 0x20, 0x50, 0x74,
-	0x79, 0x20, 0x4C, 0x74, 0x64, 0x30, 0x82, 0x01,
-	0x22, 0x30, 0x0D, 0x06, 0x09, 0x2A, 0x86, 0x48,
-	0x86, 0xF7, 0x0D, 0x01, 0x01, 0x01, 0x05, 0x00,
-	0x03, 0x82, 0x01, 0x0F, 0x00, 0x30, 0x82, 0x01,
-	0x0A, 0x02, 0x82, 0x01, 0x01, 0x00, 0x9C, 0xD7,
-	0x61, 0x2E, 0x43, 0x8E, 0x15, 0xBE, 0xCD, 0x73,
-	0x9F, 0xB7, 0xF5, 0x86, 0x4B, 0xE3, 0x95, 0x90,
-	0x5C, 0x85, 0x19, 0x4C, 0x1D, 0x2E, 0x2C, 0xEF,
-	0x6E, 0x1F, 0xED, 0x75, 0x32, 0x0F, 0x0A, 0xC1,
-	0x72, 0x9F, 0x0C, 0x78, 0x50, 0xA2, 0x99, 0x82,
-	0x53, 0x90, 0xBE, 0x64, 0x23, 0x49, 0x75, 0x7B,
-	0x0C, 0xEB, 0x2D, 0x68, 0x97, 0xD6, 0xAF, 0xB1,
-	0xAA, 0x2A, 0xDE, 0x5E, 0x9B, 0xE3, 0x06, 0x0D,
-	0xF2, 0xAC, 0xD9, 0xD7, 0x1F, 0x50, 0x6E, 0xC9,
-	0x5D, 0xEB, 0xB4, 0xF0, 0xC0, 0x98, 0x23, 0x04,
-	0x30, 0x46, 0x10, 0xDC, 0xD4, 0x6B, 0x57, 0xC7,
-	0x30, 0xC3, 0x06, 0xDD, 0xAF, 0x51, 0x6E, 0x40,
-	0x41, 0xF8, 0x10, 0xDE, 0x49, 0x18, 0x52, 0xB3,
-	0x18, 0xCA, 0x49, 0x50, 0xA8, 0x3A, 0xCD, 0xB6,
-	0x94, 0x7B, 0xDB, 0xF1, 0x2D, 0x05, 0xCE, 0x57,
-	0x0B, 0xBE, 0x38, 0x48, 0xBB, 0xC9, 0xB1, 0x76,
-	0x36, 0xB8, 0xA8, 0xCC, 0xE2, 0x07, 0x5C, 0xC8,
-	0x7B, 0xCF, 0xCF, 0xF0, 0xFA, 0xA3, 0xC5, 0xD7,
-	0x3A, 0x5E, 0xB2, 0xF4, 0xBF, 0xEA, 0xC2, 0xED,
-	0x51, 0x16, 0xA2, 0x92, 0x9C, 0x36, 0xA6, 0x86,
-	0x0E, 0x24, 0xA5, 0x66, 0x15, 0xE7, 0x97, 0x22,
-	0x50, 0x04, 0xFF, 0xC9, 0x4D, 0xB0, 0xBC, 0x27,
-	0x05, 0x5E, 0x2C, 0xF7, 0xEF, 0xDC, 0x5D, 0x58,
-	0xA1, 0x3B, 0x60, 0x83, 0xB7, 0x8C, 0xB7, 0xD0,
-	0x36, 0x6D, 0x55, 0x2E, 0x05, 0x23, 0x63, 0x74,
-	0x4A, 0x97, 0x37, 0xA7, 0x78, 0x40, 0xEF, 0x3E,
-	0x66, 0xFD, 0xBA, 0x6E, 0xB3, 0x72, 0x4A, 0x21,
-	0x82, 0x1F, 0x33, 0xAD, 0x62, 0x0C, 0xF2, 0x1A,
-	0xD2, 0x6A, 0xB5, 0xA7, 0xF2, 0x51, 0x69, 0x1F,
-	0x38, 0xA5, 0x57, 0x9A, 0xC5, 0x88, 0x67, 0xE3,
-	0x11, 0xA6, 0x53, 0x4F, 0xB1, 0xE9, 0x07, 0x41,
-	0xDE, 0xE8, 0xDF, 0x93, 0xA9, 0x99, 0x02, 0x03,
-	0x01, 0x00, 0x01, 0xA3, 0x50, 0x30, 0x4E, 0x30,
-	0x1D, 0x06, 0x03, 0x55, 0x1D, 0x0E, 0x04, 0x16,
-	0x04, 0x14, 0xDF, 0xA0, 0x28, 0xD1, 0xAF, 0xB0,
-	0x55, 0xE3, 0xC1, 0xF1, 0x33, 0x28, 0xED, 0x5C,
-	0xDD, 0xC2, 0xBB, 0xBF, 0x22, 0x6E, 0x30, 0x1F,
-	0x06, 0x03, 0x55, 0x1D, 0x23, 0x04, 0x18, 0x30,
-	0x16, 0x80, 0x14, 0xDF, 0xA0, 0x28, 0xD1, 0xAF,
-	0xB0, 0x55, 0xE3, 0xC1, 0xF1, 0x33, 0x28, 0xED,
-	0x5C, 0xDD, 0xC2, 0xBB, 0xBF, 0x22, 0x6E, 0x30,
-	0x0C, 0x06, 0x03, 0x55, 0x1D, 0x13, 0x04, 0x05,
-	0x30, 0x03, 0x01, 0x01, 0xFF, 0x30, 0x0D, 0x06,
-	0x09, 0x2A, 0x86, 0x48, 0x86, 0xF7, 0x0D, 0x01,
-	0x01, 0x0B, 0x05, 0x00, 0x03, 0x82, 0x01, 0x01,
-	0x00, 0x42, 0x3D, 0x98, 0x0C, 0x98, 0x54, 0xD0,
-	0xD7, 0x7B, 0x04, 0x18, 0x5C, 0x8F, 0xD2, 0xC1,
-	0xE9, 0xB4, 0xDA, 0x13, 0x76, 0x25, 0xD8, 0x9E,
-	0x8D, 0x00, 0x4A, 0x03, 0x89, 0xF3, 0x15, 0xB0,
-	0x0A, 0x80, 0x78, 0x5A, 0xB2, 0xAA, 0xBC, 0xE5,
-	0x37, 0xF1, 0x4C, 0xAE, 0x34, 0x3B, 0xB1, 0x6B,
-	0xD9, 0xF5, 0x8E, 0xA1, 0xFE, 0xC5, 0xED, 0x2E,
-	0xA5, 0xD6, 0xA1, 0xDC, 0x13, 0xB7, 0x36, 0xEC,
-	0xC5, 0x98, 0x9F, 0xE8, 0xA3, 0x22, 0x66, 0x88,
-	0xF2, 0x94, 0x5D, 0x9C, 0x8C, 0x6F, 0xAB, 0x81,
-	0x05, 0x3D, 0xE0, 0x9E, 0x5B, 0x03, 0xA9, 0xCA,
-	0x54, 0x8F, 0xDC, 0xE2, 0xD6, 0x0E, 0xDA, 0x15,
-	0x96, 0xAF, 0x47, 0xA1, 0x99, 0xA8, 0x37, 0xD6,
-	0xED, 0xBE, 0x3F, 0x4A, 0x4A, 0x9A, 0xC0, 0x05,
-	0x77, 0x6F, 0x1E, 0x62, 0xCB, 0x11, 0x74, 0xDF,
-	0x6D, 0xB7, 0xFF, 0x42, 0x77, 0xB3, 0x29, 0x6C,
-	0x38, 0x6F, 0xBA, 0xE5, 0x5F, 0xB7, 0x23, 0x2F,
-	0x53, 0x19, 0xC0, 0x49, 0x09, 0x18, 0x50, 0x9D,
-	0x0F, 0xFE, 0x6C, 0xA4, 0xBD, 0x35, 0x2A, 0xDD,
-	0xCF, 0xF8, 0xB6, 0x42, 0x06, 0xE1, 0x53, 0xCA,
-	0xC3, 0xF6, 0xA6, 0x70, 0x82, 0x3C, 0x3B, 0x1F,
-	0x19, 0x93, 0xBE, 0xC5, 0xB8, 0x11, 0x28, 0xEC,
-	0x66, 0xB6, 0xA5, 0x3A, 0x35, 0x82, 0x17, 0x1A,
-	0x3C, 0x4E, 0x3E, 0x25, 0xFE, 0x4C, 0xA3, 0x1F,
-	0xCA, 0xFB, 0xE6, 0xF8, 0x3B, 0x61, 0xE2, 0x33,
-	0x5C, 0x89, 0x66, 0x0F, 0xFB, 0x99, 0xFE, 0xFD,
-	0xDB, 0xC2, 0xB7, 0xA8, 0xCF, 0x45, 0xC9, 0xF1,
-	0x67, 0xB8, 0xA8, 0x97, 0xF4, 0xA5, 0x90, 0xA1,
-	0x99, 0xAA, 0xA6, 0xFF, 0x47, 0x38, 0x13, 0x82,
-	0xE4, 0x81, 0x84, 0x36, 0xC3, 0x8C, 0xE5, 0xDD,
-	0x7A, 0x70, 0xF8, 0x70, 0x27, 0xFB, 0xCD, 0xC2,
-	0xA0, 0xA9, 0xC5, 0x61, 0xA4, 0x3C, 0x9D, 0x1B,
-	0x57
-};
-
-static const TPM2B_512_BYTE_VALUE RSA_2048_D = {
-	.t  = {256, {
-			0x4e, 0x9d, 0x02, 0x1f, 0xdf, 0x4a, 0x8b, 0x89,
-			0xbc, 0x8f, 0x14, 0xe2, 0x6f, 0x15, 0x66, 0x5a,
-			0x67, 0x70, 0x19, 0x7f, 0xb9, 0x43, 0x56, 0x68,
-			0xfb, 0xaa, 0xf3, 0x26, 0xdb, 0xad, 0xdf, 0x6e,
-			0x7c, 0xb4, 0xa3, 0xd0, 0x26, 0xbe, 0xf3, 0xa3,
-			0xdc, 0x8f, 0xdf, 0x74, 0xf0, 0x89, 0x5e, 0xca,
-			0x86, 0x31, 0x2c, 0x33, 0x80, 0xea, 0x29, 0x19,
-			0x39, 0xad, 0x32, 0x9f, 0x14, 0x20, 0x95, 0xc0,
-			0x40, 0x1b, 0xa3, 0xa4, 0x91, 0xf7, 0xea, 0xc1,
-			0x35, 0x16, 0x87, 0x96, 0x0a, 0x76, 0x96, 0x02,
-			0x6b, 0xa2, 0xc0, 0xd3, 0x8d, 0xc6, 0x32, 0x4e,
-			0xaf, 0x8b, 0xae, 0xdc, 0x42, 0x47, 0xc1, 0x85,
-			0x6e, 0x5e, 0x94, 0xf2, 0x52, 0xfa, 0x27, 0xe7,
-			0x22, 0x24, 0x94, 0xeb, 0x67, 0xbe, 0x1e, 0xe4,
-			0x82, 0x91, 0xde, 0x71, 0x0a, 0xb8, 0x23, 0x1a,
-			0x02, 0xe7, 0xcc, 0x82, 0x06, 0xd2, 0x26, 0x15,
-			0x54, 0x97, 0x52, 0xcd, 0xf5, 0x3f, 0x6d, 0xc6,
-			0xb9, 0x70, 0x30, 0xbe, 0xc5, 0x88, 0xa6, 0xb0,
-			0x65, 0x16, 0x9c, 0x4c, 0x84, 0xe2, 0x7a, 0x6e,
-			0xe9, 0xc7, 0xbd, 0xcf, 0x45, 0x27, 0xfc, 0x19,
-			0xc6, 0x23, 0x1d, 0x2b, 0x88, 0xa2, 0x67, 0x1f,
-			0xc2, 0xd6, 0xd3, 0xa0, 0x79, 0xfb, 0xbf, 0xea,
-			0x38, 0xa8, 0xdf, 0x4f, 0xbc, 0x9b, 0x8e, 0xee,
-			0x04, 0xb7, 0x7c, 0x00, 0xd7, 0x95, 0x1a, 0x03,
-			0x82, 0x7a, 0xe8, 0x41, 0xb8, 0xb1, 0xaf, 0x7f,
-			0xf1, 0x30, 0x89, 0x56, 0x6d, 0x07, 0x11, 0x55,
-			0x79, 0xdd, 0x68, 0x0f, 0x82, 0x08, 0x5c, 0xcc,
-			0x24, 0x47, 0x54, 0x68, 0x86, 0xf1, 0xf0, 0x3f,
-			0x52, 0x10, 0xad, 0xe4, 0x16, 0x33, 0x16, 0x02,
-			0x21, 0x62, 0xe3, 0x2f, 0x5d, 0xeb, 0x22, 0x5b,
-			0x64, 0xb4, 0x29, 0x22, 0x74, 0x24, 0x29, 0xa9,
-			0x4c, 0x66, 0x84, 0x31, 0xca, 0x99, 0x95, 0xf5
-		}
-	}
-};
-
-static const TPM2B_512_BYTE_VALUE RSA_2048_P = {
-	.t  = {128, {
-			0xc8, 0x80, 0x6f, 0xf6, 0x2f, 0xfb, 0x49, 0x8b,
-			0x77, 0x39, 0xe2, 0x3d, 0x3d, 0x1f, 0x4d, 0xf9,
-			0xbb, 0x54, 0x06, 0x0d, 0x71, 0xbf, 0x54, 0xb1,
-			0x1e, 0xa2, 0x20, 0x7e, 0xdd, 0xcf, 0x21, 0x16,
-			0xe9, 0xc0, 0xba, 0x94, 0x02, 0xd2, 0xa4, 0x2e,
-			0x78, 0x3c, 0xfb, 0x64, 0xa0, 0xe7, 0xe9, 0x27,
-			0x64, 0x29, 0x19, 0x74, 0xc5, 0x77, 0xbb, 0xe1,
-			0x6d, 0xb4, 0x83, 0x1d, 0x43, 0x5a, 0x80, 0x72,
-			0xec, 0x3c, 0x32, 0xc3, 0x20, 0x2c, 0xce, 0xf7,
-			0xba, 0xf6, 0xc6, 0x0c, 0xf4, 0x56, 0xfd, 0xdf,
-			0x21, 0x55, 0xf3, 0xe2, 0x56, 0x25, 0xa6, 0xb3,
-			0x96, 0xa4, 0x9c, 0xb8, 0xfd, 0x9c, 0xec, 0x87,
-			0xfa, 0xda, 0x2e, 0xa4, 0xf6, 0x0f, 0x14, 0xe6,
-			0x81, 0x22, 0x84, 0xe7, 0xc0, 0x1d, 0xd1, 0x3f,
-			0xed, 0xb0, 0xba, 0xd8, 0xe4, 0xe9, 0xd4, 0x18,
-			0x33, 0xae, 0x29, 0x51, 0x79, 0x79, 0xd1, 0x0f
-		}
-	}
-};
-
-static const TPM2B_512_BYTE_VALUE RSA_2048_Q = {
-	.t  = {128, {
-			0xc8, 0x41, 0x2a, 0x42, 0xf1, 0x6a, 0x81, 0xac,
-			0x06, 0xab, 0xd0, 0xb7, 0xc0, 0xbb, 0xc6, 0x13,
-			0xdd, 0xfd, 0x5e, 0x3c, 0x77, 0xfe, 0xc1, 0x2e,
-			0x76, 0xf0, 0x94, 0xc0, 0x5d, 0x24, 0x8b, 0x30,
-			0x0d, 0xf8, 0x2a, 0xc7, 0x26, 0x78, 0x1b, 0x81,
-			0x5a, 0x42, 0x96, 0xad, 0xf7, 0x0e, 0xa4, 0x1b,
-			0x2c, 0x8f, 0x38, 0x06, 0x05, 0x8d, 0x98, 0x6e,
-			0x37, 0x65, 0xb4, 0x2c, 0x80, 0xe2, 0x38, 0xd5,
-			0x79, 0xd2, 0xea, 0x62, 0xf2, 0x32, 0xac, 0x7b,
-			0x88, 0x90, 0xc3, 0x4e, 0x9e, 0x53, 0xe5, 0x7e,
-			0xef, 0x13, 0xb1, 0xe3, 0xd5, 0x41, 0xd1, 0xa9,
-			0x15, 0x04, 0x3c, 0x61, 0x74, 0x5e, 0x1a, 0x00,
-			0x5c, 0x8a, 0x8b, 0x17, 0xd5, 0x78, 0xad, 0x5e,
-			0xe0, 0xcf, 0x35, 0x63, 0x0a, 0x95, 0x1e, 0x70,
-			0xbe, 0x97, 0xf2, 0xd3, 0x78, 0x06, 0x8a, 0x88,
-			0x9b, 0x27, 0xc8, 0xb2, 0xb1, 0x3d, 0x8a, 0xd7
-		}
-	}
-};
-
-static const TPM2B_512_BYTE_VALUE RSA_4096_N = {
-	.t  = {512, {
-			0xB4, 0xD2, 0xAB, 0x9C, 0xFA, 0x42, 0x9A, 0x37,
-			0x70, 0x2A, 0xE4, 0x2D, 0x87, 0x67, 0x7F, 0x15,
-			0xB6, 0x31, 0x06, 0x06, 0xD5, 0x5A, 0xE9, 0x8E,
-			0xA9, 0xD4, 0x6D, 0x6B, 0x92, 0xB9, 0x63, 0x37,
-			0x7D, 0x9C, 0xF0, 0xCA, 0x0A, 0x44, 0x19, 0xF0,
-			0x71, 0xA7, 0x4C, 0xE0, 0x90, 0x9C, 0xBE, 0x69,
-			0x4A, 0x9C, 0x55, 0x18, 0xB3, 0x42, 0x43, 0xD9,
-			0x6C, 0x65, 0xFD, 0xD1, 0xCF, 0x20, 0x0C, 0x92,
-			0x34, 0x27, 0x46, 0x48, 0x58, 0x0B, 0x13, 0xCD,
-			0xF1, 0x67, 0x70, 0x02, 0x7E, 0xE7, 0x4C, 0xA9,
-			0xD8, 0xFD, 0x48, 0x17, 0x80, 0xF6, 0x01, 0x0E,
-			0x61, 0xB0, 0xBE, 0xEF, 0x87, 0x2B, 0x71, 0x0E,
-			0x65, 0x81, 0xC1, 0x50, 0xCE, 0xB8, 0x65, 0xD2,
-			0xD7, 0xFA, 0x76, 0xC4, 0xB7, 0x13, 0xD9, 0xED,
-			0xDA, 0xD6, 0x9F, 0x9E, 0x10, 0xB2, 0x50, 0xF4,
-			0xFD, 0xF4, 0xF9, 0xEC, 0xD8, 0x33, 0x56, 0xEF,
-			0xF4, 0x22, 0xD3, 0xC2, 0xBA, 0x49, 0xD5, 0xA9,
-			0x0B, 0xB0, 0x18, 0xA3, 0xD9, 0x26, 0xCD, 0x27,
-			0x76, 0x6A, 0x72, 0x1B, 0x31, 0xAC, 0x3D, 0x42,
-			0xE8, 0xD9, 0x26, 0xD3, 0x90, 0xBB, 0x39, 0x64,
-			0xBB, 0xEA, 0x89, 0x0B, 0x7A, 0xB4, 0x88, 0x39,
-			0xEA, 0xE9, 0xCA, 0x19, 0x8C, 0x42, 0xFB, 0x69,
-			0x22, 0xCA, 0x8E, 0xBD, 0x6C, 0x73, 0xB7, 0x88,
-			0xA0, 0xA1, 0x19, 0xA8, 0xFA, 0x94, 0x55, 0x20,
-			0x6F, 0x80, 0xBA, 0xD7, 0x69, 0x12, 0x1F, 0x74,
-			0x82, 0xEC, 0xAF, 0xEE, 0x28, 0xAF, 0xCD, 0xDA,
-			0xAD, 0x1B, 0x5B, 0x54, 0xE4, 0x2B, 0xEF, 0x0C,
-			0x4D, 0xD1, 0xAB, 0xD7, 0x03, 0xC4, 0xA4, 0x99,
-			0xA0, 0xBC, 0x7E, 0x9D, 0x3C, 0x2F, 0x34, 0x3B,
-			0xD5, 0xDD, 0x6A, 0xED, 0xA6, 0x19, 0x93, 0x83,
-			0xBE, 0xE2, 0xD4, 0x6F, 0x92, 0xFF, 0x55, 0xA7,
-			0xF7, 0x67, 0xEB, 0xE3, 0x46, 0xD3, 0xE7, 0x6D,
-			0xC0, 0x29, 0x95, 0x2B, 0xBF, 0xDD, 0xB4, 0x93,
-			0xBB, 0x45, 0x01, 0xFC, 0x53, 0x21, 0xCE, 0x9F,
-			0x8B, 0x90, 0x80, 0x09, 0xBA, 0x1A, 0x6E, 0x08,
-			0x87, 0x15, 0xB4, 0x74, 0xA3, 0xDC, 0xBB, 0xDB,
-			0x45, 0xF2, 0x38, 0x20, 0x85, 0xC3, 0x9E, 0x4A,
-			0x45, 0x1E, 0x75, 0x18, 0x05, 0x42, 0x86, 0xAD,
-			0x47, 0xE6, 0xAA, 0xED, 0x88, 0x9A, 0x9F, 0x37,
-			0xA3, 0xB8, 0xC7, 0x99, 0x35, 0xE2, 0xA8, 0x8E,
-			0x9D, 0x2E, 0xBC, 0xF2, 0x64, 0x48, 0xC3, 0x63,
-			0x4F, 0x1C, 0xD0, 0x45, 0xC3, 0x41, 0xA1, 0xBE,
-			0xE5, 0xC2, 0xA4, 0x5D, 0x45, 0xF0, 0x03, 0x83,
-			0xC9, 0x80, 0x4C, 0x68, 0xF0, 0xD1, 0xDA, 0xF1,
-			0x51, 0x81, 0xD5, 0xFE, 0xC4, 0xE8, 0x8A, 0xD6,
-			0x32, 0x95, 0x38, 0xD8, 0x3B, 0xDA, 0xF7, 0x8C,
-			0x5C, 0x6B, 0x01, 0xF4, 0x6E, 0x12, 0xB5, 0xB6,
-			0x36, 0xE3, 0xD1, 0xAA, 0x49, 0x44, 0x6A, 0xF3,
-			0xE6, 0x7B, 0x19, 0x7D, 0xF8, 0x35, 0xCB, 0x2D,
-			0xB8, 0x62, 0x54, 0xCF, 0x2D, 0x66, 0xB3, 0x7F,
-			0xE0, 0x37, 0x65, 0x19, 0x82, 0xD6, 0x88, 0x24,
-			0xC2, 0x31, 0x7E, 0x1F, 0x6E, 0xDA, 0x4B, 0x28,
-			0xAF, 0x5E, 0x2B, 0xE8, 0x34, 0xB2, 0xDC, 0xC7,
-			0xD1, 0x95, 0x0C, 0x94, 0xE7, 0x09, 0xA0, 0xED,
-			0xAA, 0x91, 0x2F, 0x91, 0x6F, 0xF0, 0x00, 0xDF,
-			0x0D, 0x46, 0xEF, 0xD2, 0x59, 0x7B, 0x65, 0xCE,
-			0xA2, 0xED, 0x8A, 0xE2, 0x1E, 0xD0, 0xE1, 0x93,
-			0x72, 0x7F, 0x18, 0x79, 0x18, 0x35, 0xF3, 0xCA,
-			0xDB, 0x01, 0x5F, 0x09, 0x48, 0x21, 0x45, 0xFE,
-			0x89, 0x44, 0xED, 0x07, 0x79, 0x68, 0x32, 0xD8,
-			0xD6, 0x8B, 0xA0, 0xC6, 0xDC, 0xF9, 0x56, 0x89,
-			0x5B, 0xCE, 0x35, 0x05, 0xE9, 0xC1, 0x4A, 0x1E,
-			0x24, 0x0B, 0xC8, 0x73, 0x18, 0x19, 0x6B, 0xED,
-			0xF9, 0x3E, 0x92, 0x92, 0xF2, 0x0B, 0x75, 0x25,
-		}
-	}
-};
-
-#define MAX_MSG_BYTES 512
-#define MAX_LABEL_LEN 32
-
-/* 128-byte buffer to hold entropy for generating a
- * 2048-bit RSA key (assuming ~112 bits of security strength,
- * the TPM spec requires a seed of minimum size 28-bytes). */
-TPM2B_BYTE_VALUE(128);
-
-static void rsa_command_handler(void *cmd_body,
-				size_t cmd_size,
-				size_t *response_size_out)
-{
-	uint8_t *cmd;
-	uint8_t op;
-	uint8_t padding_alg;
-	uint8_t hashing_alg;
-	uint16_t key_len;
-	uint16_t in_len;
-	uint8_t in[MAX_MSG_BYTES];
-	uint16_t digest_len;
-	uint8_t digest[SHA_DIGEST_MAX_BYTES];
-	uint8_t *out = (uint8_t *) cmd_body;
-	TPM2B_512_BYTE_VALUE N;
-	TPM2B_512_BYTE_VALUE d;
-	TPM2B_512_BYTE_VALUE p;
-	TPM2B_512_BYTE_VALUE q;
-	RSA_KEY key;
-	uint32_t *response_size = (uint32_t *) response_size_out;
-	TPM2B_PUBLIC_KEY_RSA rsa_d;
-	TPM2B_PUBLIC_KEY_RSA rsa_n;
-
-	TPM2B_128_BYTE_VALUE seed;
-	uint8_t bn_buf[RSA_MAX_BYTES];
-	struct LITE_BIGNUM bn;
-	char label[MAX_LABEL_LEN];
-
-	/* This is the SHA-256 hash of the RSA template from the TCG
-	 * EK Credential Profile spec.
-	 */
-	TPM2B_32_BYTE_VALUE RSA_TEMPLATE_EK_EXTRA = {
-		.t = {32, {
-				0x68, 0xd1, 0xa2, 0x41, 0xfb, 0x27, 0x2f, 0x03,
-				0x90, 0xbf, 0xd0, 0x42, 0x8d, 0xad, 0xee, 0xb0,
-				0x2b, 0xf4, 0xa1, 0xcd, 0x46, 0xab, 0x6c, 0x39,
-				0x1b, 0xa3, 0x1f, 0x51, 0x87, 0x06, 0x8e, 0x6a
-			}
-		}
-	};
-
-	assert(sizeof(size_t) == sizeof(uint32_t));
-
-	/* Command format.
-	 *
-	 *   OFFSET       FIELD
-	 *   0            OP
-	 *   1            PADDING
-	 *   2            HASHING
-	 *   3            MSB KEY LEN
-	 *   4            LSB KEY LEN
-	 *   5            MSB IN LEN
-	 *   6            LSB IN LEN
-	 *   7            IN
-	 *   7 + IN_LEN   MSB DIGEST LEN
-	 *   8 + IN_LEN   LSB DIGEST LEN
-	 *   9 + IN_LEN   DIGEST
-	 */
-	cmd = (uint8_t *) cmd_body;
-	op = *cmd++;
-	padding_alg = *cmd++;
-	hashing_alg = *cmd++;
-	key_len = ((uint16_t) (cmd[0] << 8)) | cmd[1];
-	cmd += 2;
-	in_len = ((uint16_t) (cmd[0] << 8)) | cmd[1];
-	cmd += 2;
-	if (in_len > sizeof(in)) {
-		*response_size = 0;
-		return;
-	}
-	memcpy(in, cmd, in_len);
-
-	/* Make copies of N, and d, as const data is immutable. */
-	switch (key_len) {
-	case 768:
-		N = RSA_768_N;
-		d = RSA_768_D;
-		p = RSA_768_P;
-		q = RSA_768_Q;
-		rsa_n.b.size = RSA_768_N.b.size;
-		rsa_d.b.size = RSA_768_D.b.size;
-		break;
-	case 1024:
-		N = RSA_1024_N;
-		d = RSA_1024_D;
-		p = RSA_1024_P;
-		q = RSA_1024_Q;
-		rsa_n.b.size = RSA_1024_N.b.size;
-		rsa_d.b.size = RSA_1024_D.b.size;
-		break;
-	case 2048:
-		N = RSA_2048_N;
-		d = RSA_2048_D;
-		p = RSA_2048_P;
-		q = RSA_2048_Q;
-		rsa_n.b.size = RSA_2048_N.b.size;
-		rsa_d.b.size = RSA_2048_D.b.size;
-		break;
-	case 4096:
-		N = RSA_4096_N;
-		rsa_n.b.size = RSA_4096_N.b.size;
-		break;
-	default:
-		*response_size = 0;
-		return;
-	}
-	key.exponent = 65537;
-	key.publicKey = &N.b;
-	key.privateKey = &d.b;
-
-	switch (op) {
-	case TEST_RSA_ENCRYPT:
-		if (_cpri__EncryptRSA(
-				response_size, out, &key,
-				padding_alg, in_len, in, hashing_alg, "")
-			!= CRYPT_SUCCESS)
-			*response_size = 0;
-		return;
-	case TEST_RSA_DECRYPT:
-		if (_cpri__DecryptRSA(
-				response_size, out, &key,
-				padding_alg, in_len, in, hashing_alg, "")
-			!= CRYPT_SUCCESS)
-			*response_size = 0;
-		return;
-	case TEST_RSA_SIGN:
-		if (_cpri__SignRSA(
-				response_size, out, &key,
-				padding_alg, hashing_alg, in_len, in)
-			!= CRYPT_SUCCESS)
-			*response_size = 0;
-		return;
-	case TEST_RSA_VERIFY:
-		cmd += in_len;
-		digest_len = ((uint16_t) (cmd[0] << 8)) | cmd[1];
-		cmd += 2;
-		if (digest_len > sizeof(digest)) {
-			*response_size = 0;
-			return;
-		}
-		memcpy(digest, cmd, digest_len);
-
-		if (_cpri__ValidateSignatureRSA(
-				&key, padding_alg, hashing_alg, digest_len,
-				digest, in_len, in, 0)
-			!= CRYPT_SUCCESS) {
-			*response_size = 0;
-		} else {
-			*out = 1;
-			*response_size = 1;
-		}
-		return;
-	case TEST_RSA_KEYTEST:
-		if (_cpri__TestKeyRSA(&rsa_d.b, 65537, &rsa_n.b, &p.b, &q.b)
-			!= CRYPT_SUCCESS) {
-			*response_size = 0;
-			return;
-		}
-		if (memcmp(rsa_n.b.buffer, key.publicKey->buffer,
-				rsa_n.b.size) != 0 ||
-			memcmp(rsa_d.b.buffer, key.privateKey->buffer,
-					rsa_d.b.size) != 0) {
-				*response_size = 0;
-				return;
-		}
-
-		if (_cpri__TestKeyRSA(&rsa_d.b, 65537, key.publicKey,
-					&p.b, NULL) != CRYPT_SUCCESS) {
-			*response_size = 0;
-			return;
-		}
-		if (memcmp(rsa_d.b.buffer, key.privateKey->buffer,
-				rsa_d.b.size) != 0) {
-			*response_size = 0;
-			return;
-		}
-		*out = 1;
-		*response_size = 1;
-		return;
-	case TEST_RSA_KEYGEN:
-		if (in_len > MAX_LABEL_LEN - 1) {
-			*response_size = 0;
-			return;
-		}
-		N.b.size = sizeof(N.t.buffer);
-		p.b.size = sizeof(p.t.buffer);
-		seed.b.size = sizeof(VERIFY_SEED);
-		memcpy(seed.b.buffer, VERIFY_SEED, sizeof(VERIFY_SEED));
-		if (in_len > 0) {
-			memcpy(label, in, in_len);
-			label[in_len] = '\0';
-		}
-		if (_cpri__GenerateKeyRSA(
-				&N.b, &p.b, key_len, RSA_F4, TPM_ALG_SHA256,
-				&seed.b, in_len ? label : NULL,
-				&RSA_TEMPLATE_EK_EXTRA.b, NULL)
-			!= CRYPT_SUCCESS) {
-			*response_size = 0;
-		} else {
-			memcpy(out, N.b.buffer, N.b.size);
-			memcpy(out + N.b.size, p.b.buffer, p.b.size);
-			*response_size = N.b.size + p.b.size;
-		}
-		return;
-	case TEST_BN_PRIMEGEN:
-		if (in_len > sizeof(bn_buf)) {
-			*response_size = 0;
-			return;
-		}
-		DCRYPTO_bn_wrap(&bn, bn_buf, in_len);
-		memcpy(bn_buf, in, in_len);
-		if (DCRYPTO_bn_generate_prime(&bn)) {
-			memcpy(out, bn.d, bn_size(&bn));
-			*response_size = bn_size(&bn);
-		} else {
-			*response_size = 0;
-		}
-		return;
-	case TEST_X509_VERIFY:
-	{
-		int result;
-		struct RSA rsa;
-
-		if (key.publicKey != &N.b) {
-			*response_size = 0;
-			return;
-		}
-
-		reverse_tpm2b(key.publicKey);
-		rsa.e = key.exponent;
-		rsa.N.dmax = key.publicKey->size / sizeof(uint32_t);
-		rsa.N.d = (struct access_helper *) &key.publicKey->buffer;
-		rsa.d.dmax = 0;
-		rsa.d.d = NULL;
-
-		result = DCRYPTO_x509_verify(RSA_2048_CERT,
-					sizeof(RSA_2048_CERT), &rsa);
-		reverse_tpm2b(key.publicKey);
-
-		if (!result) {
-			*response_size = 0;
-			return;
-		}
-		*out = 0x01;
-		*response_size = 1;
-	}
-	}
-}
-
-DECLARE_EXTENSION_COMMAND(EXTENSION_RSA, rsa_command_handler);
-
-#endif   /* CRYPTO_TEST_SETUP */
diff --git a/board/cr50/tpm2/stubs.c b/board/cr50/tpm2/stubs.c
deleted file mode 100644
index 2d38b2c904..0000000000
--- a/board/cr50/tpm2/stubs.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#define        TPM_FAIL_C
-#include "Global.h"
-#include "CryptoEngine.h"
-
-CRYPT_RESULT _cpri__C_2_2_KeyExchange(
-  TPMS_ECC_POINT * outZ1,       //   OUT: a computed point
-  TPMS_ECC_POINT * outZ2,       //   OUT: and optional second point
-  TPM_ECC_CURVE curveId,        //   IN: the curve for the computations
-  TPM_ALG_ID scheme,            //   IN: the key exchange scheme
-  TPM2B_ECC_PARAMETER * dsA,    //   IN: static private TPM key
-  TPM2B_ECC_PARAMETER * deA,    //   IN: ephemeral private TPM key
-  TPMS_ECC_POINT * QsB,         //   IN: static public party B key
-  TPMS_ECC_POINT * QeB          //   IN: ephemeral public party B key
-  )
-{
-  ecprintf("%s called\n", __func__);
-  return CRYPT_FAIL;
-}
-
-CRYPT_RESULT _cpri__DrbgGetPutState(
-  GET_PUT direction,
-  int bufferSize,
-  BYTE * buffer)
-{
-  /* This unction is not implemented in the TPM2 library either. */
-  return CRYPT_SUCCESS;
-}
-
-CRYPT_RESULT _cpri__EccCommitCompute(
-  TPMS_ECC_POINT * K,           //   OUT: [d]B or [r]Q
-  TPMS_ECC_POINT * L,           //   OUT: [r]B
-  TPMS_ECC_POINT * E,           //   OUT: [r]M
-  TPM_ECC_CURVE curveId,        //   IN: the curve for the computations
-  TPMS_ECC_POINT * M,           //   IN: M (optional)
-  TPMS_ECC_POINT * B,           //   IN: B (optional)
-  TPM2B_ECC_PARAMETER * d,      //   IN: d (required)
-  TPM2B_ECC_PARAMETER * r       //   IN: the computed r value (required)
-  )
-{
-  ecprintf("%s called\n", __func__);
-  return CRYPT_FAIL;
-}
-
-BOOL _cpri__Startup(
-  void)
-{
-  /*
-   * Below is the list of functions called by the TPM2 library from
-   * _cpri__Startup().
-   *
-   *  _cpri__HashStartup() - not doing anything for now, maybe hw
-   *               reinitialization is required?
-   * _cpri__RsaStartup() - not sure what needs to be done in HW
-   * _cpri__EccStartup() - not sure what needs to be done in HW
-   * _cpri__SymStartup() - this function is emtpy in the TPM2 library
-   *                implementation.
-   */
-  return 1;
-}
-
-CRYPT_RESULT _math__Div(
-  const TPM2B * n,              //   IN: numerator
-  const TPM2B * d,              //   IN: denominator
-  TPM2B * q,                    //   OUT: quotient
-  TPM2B * r                     //   OUT: remainder
-  )
-{
-  ecprintf("%s called\n", __func__);
-  return CRYPT_FAIL;
-}
-
-void __assert_func(
-  const char *file,
-  int line,
-  const char *func,
-  const char *condition
-)
-{
-  /*
-   * TPM2 library invokes assert from a common wrapper, which first sets
-   * global variables describing the failure point and then invokes the
-   * assert() macro which ends up calling this function as defined by the gcc
-   * toolchain.
-   *
-   * For some weird reason (or maybe this is a bug), s_FailFunction is defined
-   * in the tpm2 library as a 32 bit int, but on a failure the name of the
-   * failing function (its first four bytes) are copiied into this variable.
-   *
-   * TODO(vbendeb): investigate and fix TPM2 library assert handling.
-   */
-  ecprintf("Failure in %s, func %s, line %d:\n%s\n",
-           file,
-	   s_failFunction ? (const char *)&s_failFunction : func,
-	   s_failLine ? s_failLine : line,
-	   condition);
-  while (1)
-    ;                           /* Let the watchdog doo the rest. */
-}
-
-CRYPT_RESULT _cpri__InitCryptoUnits(
-  FAIL_FUNCTION failFunction)
-{
-  return CRYPT_SUCCESS;
-}
diff --git a/board/cr50/tpm2/tpm_mode.c b/board/cr50/tpm2/tpm_mode.c
deleted file mode 100644
index 8282236caa..0000000000
--- a/board/cr50/tpm2/tpm_mode.c
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "config.h"
-#include "Global.h"
-#include "board.h"
-#include "closed_source_set1.h"
-#include "console.h"
-#include "dcrypto.h"
-#include "extension.h"
-#include "hooks.h"
-#include "nvmem.h"
-#include "system.h"
-#include "timer.h"
-#include "tpm_registers.h"
-#include "tpm_vendor_cmds.h"
-
-#define CPRINTS(format, args...) cprints(CC_EXTENSION, format, ## args)
-
-static void disable_tpm(void)
-{
-	nvmem_enable_commits();
-	tpm_stop();
-	DCRYPTO_ladder_revoke();
-	nvmem_clear_cache();
-
-	if (board_uses_closed_source_set1())
-		close_source_set1_disable_tpm();
-}
-DECLARE_DEFERRED(disable_tpm);
-
-/*
- * On TPM reset event, tpm_reset_now() in tpm_registers.c clears TPM2 BSS memory
- * area. By placing s_tpm_mode in TPM2 BSS area, TPM mode value shall be
- * "TPM_MODE_ENABLED_TENTATIVE" on every TPM reset events.
- */
-static enum tpm_modes s_tpm_mode __attribute__((section(".bss.Tpm2_common")));
-
-static enum vendor_cmd_rc process_tpm_mode(struct vendor_cmd_params *p)
-{
-	uint8_t mode_val;
-	uint8_t *buffer;
-
-	p->out_size = 0;
-
-	if (p->in_size > sizeof(uint8_t))
-		return VENDOR_RC_NOT_ALLOWED;
-
-	buffer = (uint8_t *)p->buffer;
-	if (p->in_size == sizeof(uint8_t)) {
-
-		if (!board_tpm_mode_change_allowed() ||
-		    (s_tpm_mode != TPM_MODE_ENABLED_TENTATIVE))
-			return VENDOR_RC_NOT_ALLOWED;
-
-		mode_val = buffer[0];
-
-		switch (mode_val) {
-		case TPM_MODE_ENABLED:
-			/*
-			 * If Key ladder is disabled, then fail this request.
-			 */
-			if (!DCRYPTO_ladder_is_enabled())
-				return VENDOR_RC_INTERNAL_ERROR;
-			break;
-		case TPM_MODE_DISABLED:
-			/*
-			 * If it is to be disabled, call disable_tpm() deferred
-			 * so that this vendor command can be responded to
-			 * before TPM stops.
-			 */
-			hook_call_deferred(&disable_tpm_data, 10 * MSEC);
-			break;
-		default:
-			return VENDOR_RC_NO_SUCH_SUBCOMMAND;
-		}
-		s_tpm_mode = mode_val;
-	} else {
-		if (s_tpm_mode < TPM_MODE_DISABLED &&
-		    !DCRYPTO_ladder_is_enabled())
-			return VENDOR_RC_INTERNAL_ERROR;
-	}
-
-	p->out_size = sizeof(uint8_t);
-	buffer[0] = (uint8_t) s_tpm_mode;
-
-	return VENDOR_RC_SUCCESS;
-}
-DECLARE_VENDOR_COMMAND_P(VENDOR_CC_TPM_MODE, process_tpm_mode);
-
-enum tpm_modes get_tpm_mode(void)
-{
-	return s_tpm_mode;
-}
diff --git a/board/cr50/tpm2/tpm_state.c b/board/cr50/tpm2/tpm_state.c
deleted file mode 100644
index 43b28ea7b2..0000000000
--- a/board/cr50/tpm2/tpm_state.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "config.h"
-
-#include "Global.h"
-#include "board.h"
-#include "console.h"
-#include "endian.h"
-#include "extension.h"
-#include "system.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-
-/*
- * The below structure represents the body of the response to the 'report tpm
- * state' vendor command.
- *
- * It will be transferred over the wire, so it needs to be
- * serialized/deserialized, and it is likely to change, so its contents must
- * be versioned.
- */
-#define TPM_STATE_VERSION	1
-struct tpm_state {
-	uint32_t version;
-	uint32_t fail_line;	/* s_failLIne */
-	uint32_t fail_code;	/* s_failCode */
-	char func_name[4];	/* s_failFunction, limited to 4 chars */
-	uint32_t failed_tries;	/* gp.failedTries */
-	uint32_t max_tries;	/* gp.maxTries */
-	/* The below fields are present in version 2 and above. */
-} __packed;
-
-static void serialize_u32(void *buf, uint32_t value)
-{
-	value = htobe32(value);
-	memcpy(buf, &value, sizeof(value));
-}
-
-static enum vendor_cmd_rc report_tpm_state(enum vendor_cmd_cc code,
-					   void *buf,
-					   size_t input_size,
-					   size_t *response_size)
-{
-	struct tpm_state *state = buf;
-
-	CPRINTS("%s", __func__);
-
-	memset(state, 0, sizeof(*state));
-
-	if (board_id_is_mismatched()) {
-		s_failCode = 0xbadc0de;
-		s_failLine = __LINE__;
-		memcpy(&s_failFunction, __func__, sizeof(s_failFunction));
-	}
-
-	serialize_u32(&state->version, TPM_STATE_VERSION);
-	serialize_u32(&state->fail_code, s_failCode);
-	serialize_u32(&state->fail_line, s_failLine);
-	serialize_u32(&state->failed_tries, gp.failedTries);
-	serialize_u32(&state->max_tries, gp.maxTries);
-	if (s_failFunction)
-		memcpy(state->func_name, (void *)&s_failFunction,
-		       sizeof(state->func_name));
-
-	*response_size = sizeof(*state);
-
-	return VENDOR_RC_SUCCESS;
-}
-DECLARE_VENDOR_COMMAND(VENDOR_CC_REPORT_TPM_STATE, report_tpm_state);
diff --git a/board/cr50/tpm2/trng.c b/board/cr50/tpm2/trng.c
deleted file mode 100644
index 7cce13ff1c..0000000000
--- a/board/cr50/tpm2/trng.c
+++ /dev/null
@@ -1,11 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "CryptoEngine.h"
-
-CRYPT_RESULT _cpri__StirRandom(int32_t num, uint8_t *entropy)
-{
-	return CRYPT_SUCCESS;     /* NO-OP on CR50. */
-}
diff --git a/board/cr50/tpm2/virtual_nvmem.c b/board/cr50/tpm2/virtual_nvmem.c
deleted file mode 100644
index ef2bf62300..0000000000
--- a/board/cr50/tpm2/virtual_nvmem.c
+++ /dev/null
@@ -1,362 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <string.h>
-
-#include "Global.h"
-
-#include "board_id.h"
-#include "console.h"
-#include "cryptoc/sha256.h"
-#include "link_defs.h"
-#include "rma_auth.h"
-#include "sn_bits.h"
-#include "u2f_impl.h"
-#include "virtual_nvmem.h"
-
-/*
- * Functions to allow access to non-NVRam data through NVRam Indexes.
- *
- * These functions map virtual NV indexes to virtual offsets, and allow
- * reads from those virtual offsets. The functions are contrained based on the
- * implementation of the calling TPM functions; these constraints and other
- * assumptions are described below.
- *
- * The TPM NVRam functions make use of the available NVRam space to store NVRam
- * Indexes in a linked list with the following structure:
- *
- * struct nvram_list_node {
- *   UINT32 next_node_offset;
- *   TPM_HANDLE this_node_handle;
- *   NV_INDEX index;
- *   BYTE data[];
- * };
- *
- * The TPM functions for operating on NVRam begin by iterating through the list
- * to find the offset for the relevant Index.
- *
- * See NvFindHandle() in //third_party/tpm2/NV.c for more details.
- *
- * Once the offset has been found, read operations on the NV Index will
- * call _plat__NvMemoryRead() twice, first to read the NV_INDEX data, and
- * second to read the actual NV data.
- *
- * The offset x returned by NvFindHandle() is to the this_node_handle element of
- * the linked list node; the subsequent reads are therefore to
- * x+sizeof(TPM_HANDLE) and x+sizeof(TPM_HANDLE)+sizeof(NV_INDEX).
- *
- * The first read, to retrieve NV_INDEX data, is always a fixed size
- * (sizeof(NV_INDEX)). The size of the second read is user defined, but will
- * not exceed the size of the data.
- */
-
-/*  Size constraints for virtual NV indexes. */
-#define VIRTUAL_NV_INDEX_HEADER_SIZE       sizeof(NV_INDEX)
-#define MAX_VIRTUAL_NV_INDEX_DATA_SIZE     0x200
-#define MAX_VIRTUAL_NV_INDEX_SLOT_SIZE     (sizeof(TPM_HANDLE) +	   \
-					    VIRTUAL_NV_INDEX_HEADER_SIZE + \
-					    MAX_VIRTUAL_NV_INDEX_DATA_SIZE)
-
-/*
- * Prefix for virtual NV offsets. Chosen such that all virtual NV offsets are
- * not valid memory addresses, to ensure it is impossible to accidentally read
- * (incorrect) virtual NV data from anywhere other than these functions.
- */
-#define VIRTUAL_NV_OFFSET_START            0xfff00000
-#define VIRTUAL_NV_OFFSET_END		   0xffffffff
-/* Used to check if offsets are virtual. */
-#define VIRTUAL_NV_OFFSET_MASK		   (~(VIRTUAL_NV_OFFSET_END -     \
-					      VIRTUAL_NV_OFFSET_START))
-
-/*
- * These offsets are the two offsets queried by the TPM code, as a result of the
- * design of that code, and the linked list structure described above.
- */
-#define NV_INDEX_READ_OFFSET               0x00000004 /* sizeof(uint32_t) */
-#define NV_DATA_READ_OFFSET                0x00000098 /* NV_INDEX_READ_OFFSET
-						       *   + sizeof(NV_INDEX)
-						       */
-
-/* Template for the NV_INDEX data. */
-#define NV_INDEX_TEMPLATE {						  \
-	.publicArea = {							  \
-		.nameAlg = TPM_ALG_SHA256,				  \
-		.attributes = {						  \
-			/* Allow index to be read using its authValue. */ \
-			.TPMA_NV_AUTHREAD = 1,				  \
-			/*						  \
-			 * The spec requires at least one write		  \
-			 * authentication method to be specified. We	  \
-			 * intentionally don't include one, so that	  \
-			 * this index cannot be spoofed by an		  \
-			 * attacker running a version of cr50 that	  \
-			 * pre-dates the implementation of virtual	  \
-			 * NV indices.					  \
-			 * .TPMA_NV_AUTHWRITE = 1,			  \
-			 * Only allow deletion if the authPolicy is	  \
-			 * satisied. The authPolicy is empty, and so	  \
-			 * cannot be satisfied, so this effectively	  \
-			 * disables deletion.				  \
-			 */						  \
-			.TPMA_NV_POLICY_DELETE = 1,			  \
-			/* Prevent writes. */				  \
-			.TPMA_NV_WRITELOCKED = 1,			  \
-			/* Write-lock will not be cleared on startup. */  \
-			.TPMA_NV_WRITEDEFINE = 1,			  \
-			/* Index has been written, can be read. */	  \
-			.TPMA_NV_WRITTEN = 1,				  \
-		},							  \
-		.authPolicy = { },					  \
-	},								  \
-	.authValue = { },						  \
-};
-
-/* Configuration data for virtual NV indexes. */
-struct virtual_nv_index_cfg {
-	uint16_t size;
-
-	void (*get_data_fn)(BYTE *to, size_t offset, size_t size);
-} __packed;
-
-#define REGISTER_CONFIG(r_index, r_size, r_get_data_fn) \
-	[r_index - VIRTUAL_NV_INDEX_START] = { \
-		.size = r_size, \
-		.get_data_fn = r_get_data_fn \
-	},
-
-#define REGISTER_DEPRECATED_CONFIG(r_index) \
-	REGISTER_CONFIG(r_index, 0, 0)
-
-
-/*
- * The salt to be mixed in with RMA device ID to produce RSU device ID.
- */
-#define RSU_SALT_SIZE 32
-const char kRsuSalt[] = "Wu8oGt0uu0H8uSGxfo75uSDrGcRk2BXh";
-BUILD_ASSERT(ARRAY_SIZE(kRsuSalt) == RSU_SALT_SIZE+1);
-
-/*
- * Helpers for dealing with NV indexes, associated configs and offsets.
- */
-
-/*
- * Looks up the config for the specified virtual NV index, and sets a default
- * 'empty' config if the index is not defined.
- */
-static inline void GetNvIndexConfig(
-	enum virtual_nv_index index, struct virtual_nv_index_cfg *cfg);
-
-/* Converts a virtual NV index to the corresponding virtual offset. */
-static inline BOOL NvIndexToNvOffset(uint32_t index)
-{
-	return VIRTUAL_NV_OFFSET_START +
-		((index - VIRTUAL_NV_INDEX_START) *
-		 MAX_VIRTUAL_NV_INDEX_SLOT_SIZE);
-}
-
-/* Converts an virtual offset to the corresponding NV Index. */
-static inline BOOL NvOffsetToNvIndex(uint32_t offset)
-{
-	return VIRTUAL_NV_INDEX_START +
-		((offset - VIRTUAL_NV_OFFSET_START) /
-		 MAX_VIRTUAL_NV_INDEX_SLOT_SIZE);
-}
-
-/*
- * Copies the template NV_INDEX data to the specified destination, and updates
- * it with the specified NV index and size values.
- */
-static inline void CopyNvIndex(void *dest, size_t start, size_t count,
-			       uint32_t nvIndex, uint32_t size)
-{
-	NV_INDEX nv_index_template = NV_INDEX_TEMPLATE;
-
-	nv_index_template.publicArea.nvIndex = nvIndex;
-	nv_index_template.publicArea.dataSize = size;
-	memcpy(dest, ((BYTE *) &nv_index_template) + start, count);
-}
-
-/*
- * Functions exposed to the TPM2 code.
- */
-
-uint32_t _plat__NvGetHandleVirtualOffset(uint32_t handle)
-{
-	if (handle >= VIRTUAL_NV_INDEX_START && handle <= VIRTUAL_NV_INDEX_MAX)
-		return NvIndexToNvOffset(handle);
-	else
-		return 0;
-}
-
-BOOL _plat__NvOffsetIsVirtual(unsigned int startOffset)
-{
-	return (startOffset & VIRTUAL_NV_OFFSET_MASK) ==
-			VIRTUAL_NV_OFFSET_START;
-}
-
-void _plat__NvVirtualMemoryRead(unsigned int startOffset, unsigned int size,
-				void *data)
-{
-	uint32_t nvIndex;
-	struct virtual_nv_index_cfg nvIndexConfig;
-	unsigned int offset;
-
-	nvIndex = NvOffsetToNvIndex(startOffset);
-	GetNvIndexConfig(nvIndex, &nvIndexConfig);
-
-	/* Calculate offset within this section. */
-	startOffset = startOffset - NvIndexToNvOffset(nvIndex);
-
-	offset = startOffset;
-	while (size > 0) {
-		int section_offset;
-		int copied;
-
-		if (offset < NV_INDEX_READ_OFFSET) {
-			/*
-			 * The first 4 bytes are supposed to represent a pointer
-			 * to the next element in the NV index list; we don't
-			 * have a next item, so return 0.
-			 */
-			copied = MIN(sizeof(TPM_HANDLE) - offset, size);
-
-			memset((BYTE *) data, 0, copied);
-		} else if (offset < NV_DATA_READ_OFFSET) {
-			/*
-			 * The NV_INDEX section is the second section, which
-			 * immediately folows the 'next' pointer above.
-			 */
-			section_offset = offset - NV_INDEX_READ_OFFSET;
-			copied = MIN(VIRTUAL_NV_INDEX_HEADER_SIZE -
-				     section_offset, size);
-
-			CopyNvIndex((BYTE *)data + offset - startOffset,
-				    section_offset,
-				    copied,
-				    nvIndex, nvIndexConfig.size);
-		} else if (offset < NV_DATA_READ_OFFSET + nvIndexConfig.size) {
-			/*
-			 * The actual NV data is the final section, which
-			 * immediately follos the NV_INDEX.
-			 */
-			section_offset = offset - NV_DATA_READ_OFFSET;
-			copied = MIN(nvIndexConfig.size - section_offset, size);
-
-			nvIndexConfig.get_data_fn((BYTE *)data + offset -
-						  startOffset,
-						  section_offset,
-						  copied);
-		} else {
-			/* More data was requested than is available. */
-#ifdef CR50_DEV
-			cprints(CC_TPM,
-				"Invalid vNVRAM read, offset: %x, size: %x",
-				offset, size);
-#endif
-			memset((BYTE *)data + offset - startOffset, 0,
-			       size);
-			break;
-		}
-
-		offset += copied;
-		size -= copied;
-	}
-}
-
-/*
- *  Helpers to fetch actual virtual NV data.
- */
-
-static void GetBoardId(BYTE *to, size_t offset, size_t size)
-{
-	struct board_id board_id_tmp;
-
-	read_board_id(&board_id_tmp);
-	memcpy(to, ((BYTE *) &board_id_tmp) + offset, size);
-}
-BUILD_ASSERT(VIRTUAL_NV_INDEX_BOARD_ID_SIZE == sizeof(struct board_id));
-
-static void GetSnData(BYTE *to, size_t offset, size_t size)
-{
-	struct sn_data sn_data_tmp;
-
-	read_sn_data(&sn_data_tmp);
-	memcpy(to, ((BYTE *) &sn_data_tmp) + offset, size);
-}
-BUILD_ASSERT(VIRTUAL_NV_INDEX_SN_DATA_SIZE == sizeof(struct sn_data));
-
-static void GetG2fCert(BYTE *to, size_t offset, size_t size)
-{
-	uint8_t cert[G2F_ATTESTATION_CERT_MAX_LEN] = { 0 };
-
-	if (!g2f_attestation_cert(cert))
-		memset(cert, 0, G2F_ATTESTATION_CERT_MAX_LEN);
-
-	memcpy(to, ((BYTE *) cert) + offset, size);
-}
-BUILD_ASSERT(VIRTUAL_NV_INDEX_G2F_CERT_SIZE == G2F_ATTESTATION_CERT_MAX_LEN);
-
-static void GetRSUDevID(BYTE *to, size_t offset, size_t size)
-{
-	LITE_SHA256_CTX ctx;
-	uint8_t rma_device_id[RMA_DEVICE_ID_SIZE];
-	const uint8_t *rsu_device_id;
-
-	get_rma_device_id(rma_device_id);
-
-	SHA256_init(&ctx);
-	HASH_update(&ctx, rma_device_id, sizeof(rma_device_id));
-	HASH_update(&ctx, kRsuSalt, RSU_SALT_SIZE);
-	rsu_device_id = HASH_final(&ctx);
-
-	memcpy(to, rsu_device_id + offset, size);
-}
-BUILD_ASSERT(VIRTUAL_NV_INDEX_RSU_DEV_ID_SIZE == SHA256_DIGEST_SIZE);
-
-/*
- * Registration of current virtual indexes.
- *
- * Indexes are declared in the virtual_nv_index enum in the header.
- *
- * Active entries of this enum must have a size and data function registered
- * with a REGISTER_CONFIG statement below.
- *
- * Deprecated indices should use the REGISTER_DEPRECATED_CONFIG variant.
- */
-
-static const struct virtual_nv_index_cfg index_config[] = {
-	REGISTER_CONFIG(VIRTUAL_NV_INDEX_BOARD_ID,
-			VIRTUAL_NV_INDEX_BOARD_ID_SIZE,
-			GetBoardId)
-	REGISTER_CONFIG(VIRTUAL_NV_INDEX_SN_DATA,
-			VIRTUAL_NV_INDEX_SN_DATA_SIZE,
-			GetSnData)
-	REGISTER_CONFIG(VIRTUAL_NV_INDEX_G2F_CERT,
-			VIRTUAL_NV_INDEX_G2F_CERT_SIZE,
-			GetG2fCert)
-	REGISTER_CONFIG(VIRTUAL_NV_INDEX_RSU_DEV_ID,
-			VIRTUAL_NV_INDEX_RSU_DEV_ID_SIZE,
-			GetRSUDevID)
-};
-
-/* Check sanity of above config. */
-BUILD_ASSERT(VIRTUAL_NV_INDEX_END <= (VIRTUAL_NV_INDEX_MAX + 1));
-BUILD_ASSERT((VIRTUAL_NV_INDEX_END - VIRTUAL_NV_INDEX_START) ==
-	     ARRAY_SIZE(index_config));
-/* Check we will never overrun the virtual address space. */
-BUILD_ASSERT((VIRTUAL_NV_INDEX_MAX - VIRTUAL_NV_INDEX_START + 1) *
-	     MAX_VIRTUAL_NV_INDEX_SLOT_SIZE <
-	     (VIRTUAL_NV_OFFSET_END - VIRTUAL_NV_OFFSET_START));
-
-static inline void GetNvIndexConfig(
-	enum virtual_nv_index index, struct virtual_nv_index_cfg *cfg)
-{
-	if (index >= VIRTUAL_NV_INDEX_START && index < VIRTUAL_NV_INDEX_END) {
-		*cfg = index_config[index - VIRTUAL_NV_INDEX_START];
-	} else {
-		cfg->size = 0;
-		cfg->get_data_fn = 0;
-	}
-}
diff --git a/board/cr50/tpm2/virtual_nvmem.h b/board/cr50/tpm2/virtual_nvmem.h
deleted file mode 100644
index 8321daa88c..0000000000
--- a/board/cr50/tpm2/virtual_nvmem.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __EC_BOARD_CR50_TPM2_VIRTUAL_NVMEM_H
-#define __EC_BOARD_CR50_TPM2_VIRTUAL_NVMEM_H
-
-/*
- * Currently supported virtual NV indexes.
- *
- * The range for virtual NV indexes is chosen such that all indexes
- * fall within a range designated by the TCG for use by TPM manufacturers,
- * without expectation of consultation with the TCG, or consistent behavior
- * across TPM models. See Table 3 in the 'Registry of reserved TPM 2.0
- * handles and localities' for more details.
- *
- * To return data, entries in this enum must be registered in virtual_nvmem.c.
- *
- * Values in this enum must be consecutive.
- */
-enum virtual_nv_index {
-	VIRTUAL_NV_INDEX_START = 0x013fff00,
-	VIRTUAL_NV_INDEX_BOARD_ID = VIRTUAL_NV_INDEX_START,
-	VIRTUAL_NV_INDEX_SN_DATA,
-	VIRTUAL_NV_INDEX_G2F_CERT,
-	VIRTUAL_NV_INDEX_RSU_DEV_ID,
-	VIRTUAL_NV_INDEX_END,
-};
-/* Reserved space for future virtual indexes; this is the last valid index. */
-#define VIRTUAL_NV_INDEX_MAX 0x013fffff
-
-/*
- * Data sizes (in bytes) of currently defined indexes.
- */
-#define VIRTUAL_NV_INDEX_BOARD_ID_SIZE	12
-#define VIRTUAL_NV_INDEX_SN_DATA_SIZE	16
-#define VIRTUAL_NV_INDEX_G2F_CERT_SIZE	315
-#define VIRTUAL_NV_INDEX_RSU_DEV_ID_SIZE 32
-
-#endif /* __EC_BOARD_CR50_TPM2_VIRTUAL_NVMEM_H */
diff --git a/board/cr50/tpm_nvmem_ops.c b/board/cr50/tpm_nvmem_ops.c
deleted file mode 100644
index 90bddfb313..0000000000
--- a/board/cr50/tpm_nvmem_ops.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "tpm_nvmem_ops.h"
-
-/* These come from the tpm2 tree. */
-#include "Global.h"
-#include "Implementation.h"
-#include "NV_fp.h"
-#include "tpm_types.h"
-
-#define CPRINTF(format, args...) cprintf(CC_TASK, format, ## args)
-
-enum tpm_read_rv read_tpm_nvmem(uint16_t obj_index,
-				uint16_t obj_size, void *obj_value)
-{
-	TPM_HANDLE       object_handle;
-	NV_INDEX         nvIndex;
-
-	object_handle = HR_NV_INDEX + obj_index;
-
-	if (!NvEarlyStageFindHandle(object_handle)) {
-		CPRINTF("%s: object at 0x%x not found\n", __func__, obj_index);
-		return tpm_read_not_found;
-	}
-
-	/* Get properties of this index as stored in nvmem. */
-	NvGetIndexInfo(object_handle, &nvIndex);
-
-	/*
-	 * We presume it is readable and are not checking the access
-	 * limitations.
-	 */
-
-	/*
-	 * Does the caller ask for too much? Note that we always read from the
-	 * beginning of the space, unlike the actual TPM2_NV_Read command
-	 * which can start at an offset.
-	 */
-	if (obj_size > nvIndex.publicArea.dataSize) {
-		CPRINTF("%s: object at 0x%x is smaller than %d\n",
-			__func__, obj_index, obj_size);
-		return tpm_read_too_small;
-	}
-
-	/* Perform the read. */
-	NvGetIndexData(object_handle, &nvIndex, 0, obj_size, obj_value);
-
-	return tpm_read_success;
-}
-
-enum tpm_read_rv read_tpm_nvmem_hidden(uint16_t object_index,
-				       uint16_t object_size,
-				       void *obj_value)
-{
-	if (NvGetHiddenObject(HR_HIDDEN | object_index,
-			      object_size,
-			      obj_value) == TPM_RC_SUCCESS) {
-		return tpm_read_success;
-	} else {
-		return tpm_read_not_found;
-	}
-}
-
-enum tpm_write_rv write_tpm_nvmem_hidden(uint16_t object_index,
-					 uint16_t object_size,
-					 void *obj_value,
-					 int commit)
-{
-	enum tpm_write_rv ret = tpm_write_fail;
-
-	uint32_t handle = object_index | HR_HIDDEN;
-
-	if (!NvIsDefinedHiddenObject(handle) &&
-	    NvAddHiddenObject(handle,
-			      object_size,
-			      obj_value) == TPM_RC_SUCCESS) {
-		ret = tpm_write_created;
-	} else if (NvWriteHiddenObject(handle,
-				       object_size,
-				       obj_value) == TPM_RC_SUCCESS) {
-		ret = tpm_write_updated;
-	}
-
-	if (commit && !NvCommit())
-		ret = tpm_write_fail;
-
-	return ret;
-}
diff --git a/board/cr50/tpm_nvmem_ops.h b/board/cr50/tpm_nvmem_ops.h
deleted file mode 100644
index d12eb1bb5f..0000000000
--- a/board/cr50/tpm_nvmem_ops.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __EC_BOARD_CR50_TPM_NVMEM_OPS_H
-#define __EC_BOARD_CR50_TPM_NVMEM_OPS_H
-
-enum tpm_read_rv {
-	tpm_read_success,
-	tpm_read_not_found,
-	tpm_read_too_small
-};
-
-enum tpm_write_rv {
-	tpm_write_created,
-	tpm_write_updated,
-	tpm_write_fail
-};
-
-enum tpm_nv_hidden_object {
-	TPM_HIDDEN_U2F_KEK,
-	TPM_HIDDEN_U2F_KH_SALT,
-};
-
-enum tpm_read_rv read_tpm_nvmem(uint16_t object_index,
-				uint16_t object_size,
-				void *obj_value);
-
-/*
- * The following functions must only be called from the TPM task,
- * and only after TPM initialization is complete (specifically,
- * after NvInitStatic).
- */
-
-enum tpm_read_rv read_tpm_nvmem_hidden(uint16_t object_index,
-				       uint16_t object_size,
-				       void *obj_value);
-
-enum tpm_write_rv write_tpm_nvmem_hidden(uint16_t object_index,
-					 uint16_t object_size,
-					 void *obj_value,
-					 int commit);
-
-#endif  /* ! __EC_BOARD_CR50_TPM_NVMEM_OPS_H */
diff --git a/board/cr50/u2f.c b/board/cr50/u2f.c
deleted file mode 100644
index b99722e48f..0000000000
--- a/board/cr50/u2f.c
+++ /dev/null
@@ -1,348 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Helpers to emulate a U2F HID dongle over the TPM transport */
-
-#include "console.h"
-#include "dcrypto.h"
-#include "extension.h"
-#include "nvmem_vars.h"
-#include "rbox.h"
-#include "registers.h"
-#include "signed_header.h"
-#include "system.h"
-#include "tpm_nvmem_ops.h"
-#include "tpm_vendor_cmds.h"
-#include "u2f.h"
-#include "u2f_impl.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_EXTENSION, format, ## args)
-
-/* ---- physical presence (using the laptop power button) ---- */
-
-static timestamp_t last_press;
-
-/* how long do we keep the last button press as valid presence */
-#define PRESENCE_TIMEOUT (10 * SECOND)
-
-void power_button_record(void)
-{
-	if (ap_is_on() && rbox_powerbtn_is_pressed()) {
-		last_press = get_time();
-#ifdef CR50_DEV
-		CPRINTS("record pp");
-#endif
-	}
-}
-
-enum touch_state pop_check_presence(int consume)
-{
-	int recent = ((last_press.val  > 0) &&
-		((get_time().val - last_press.val) < PRESENCE_TIMEOUT));
-
-#ifdef CR50_DEV
-	if (recent)
-		CPRINTS("User presence: consumed %d", consume);
-#endif
-	if (consume)
-		last_press.val = 0;
-
-	/* user physical presence on the power button */
-	return recent ? POP_TOUCH_YES : POP_TOUCH_NO;
-}
-
-/* ---- non-volatile U2F state ---- */
-
-struct u2f_state {
-	uint32_t salt[8];
-	uint32_t salt_kek[8];
-	uint32_t salt_kh[8];
-};
-
-static const uint8_t k_salt = NVMEM_VAR_G2F_SALT;
-static const uint8_t k_salt_deprecated = NVMEM_VAR_U2F_SALT;
-
-static int load_state(struct u2f_state *state)
-{
-	const struct tuple *t_salt = getvar(&k_salt, sizeof(k_salt));
-
-	if (!t_salt) {
-		/* Delete the old salt if present, no-op if not. */
-		if (setvar(&k_salt_deprecated, sizeof(k_salt_deprecated),
-			   NULL, 0))
-			return 0;
-
-		/* create random salt */
-		if (!DCRYPTO_ladder_random(state->salt))
-			return 0;
-		if (setvar(&k_salt, sizeof(k_salt),
-			   (const uint8_t *)state->salt, sizeof(state->salt)))
-			return 0;
-	} else {
-		memcpy(state->salt, tuple_val(t_salt), sizeof(state->salt));
-		freevar(t_salt);
-	}
-
-	if (read_tpm_nvmem_hidden(TPM_HIDDEN_U2F_KEK, sizeof(state->salt_kek),
-				  state->salt_kek) == tpm_read_not_found) {
-		/*
-		 * Not found means that we have not used u2f before,
-		 * or not used it with updated fw that resets kek seed
-		 * on TPM clear.
-		 */
-		if (t_salt) { /* Note that memory has been freed already!. */
-			/*
-			 * We have previously used u2f, and may have
-			 * existing registrations; we don't want to
-			 * invalidate these, so preserve the existing
-			 * seed as a one-off. It will be changed on
-			 * next TPM clear.
-			 */
-			memcpy(state->salt_kek, state->salt,
-			       sizeof(state->salt_kek));
-		} else {
-			/*
-			 * We have never used u2f before - generate
-			 * new seed.
-			 */
-			if (!DCRYPTO_ladder_random(state->salt_kek))
-				return 0;
-		}
-		if (write_tpm_nvmem_hidden(TPM_HIDDEN_U2F_KEK,
-					   sizeof(state->salt_kek),
-					   state->salt_kek,
-					   1 /* commit */) != tpm_write_created)
-			return 0;
-	}
-
-	if (read_tpm_nvmem_hidden(TPM_HIDDEN_U2F_KH_SALT,
-				  sizeof(state->salt_kh),
-				  state->salt_kh) == tpm_read_not_found) {
-		/*
-		 * We have never used u2f before - generate
-		 * new seed.
-		 */
-		if (!DCRYPTO_ladder_random(state->salt_kh))
-			return 0;
-
-		if (write_tpm_nvmem_hidden(TPM_HIDDEN_U2F_KH_SALT,
-					   sizeof(state->salt_kh),
-					   state->salt_kh,
-					   1 /* commit */) != tpm_write_created)
-			return 0;
-	}
-
-	return 1;
-}
-
-static struct u2f_state *get_state(void)
-{
-	static int state_loaded;
-	static struct u2f_state state;
-
-	if (!state_loaded)
-		state_loaded = load_state(&state);
-
-	return state_loaded ? &state : NULL;
-}
-
-/* ---- chip-specific U2F crypto ---- */
-
-static int _derive_key(enum dcrypto_appid appid, const uint32_t input[8],
-		       uint32_t output[8])
-{
-	struct APPKEY_CTX ctx;
-	int result;
-
-	/* Setup USR-based application key. */
-	if (!DCRYPTO_appkey_init(appid, &ctx))
-		return 0;
-	result = DCRYPTO_appkey_derive(appid, input, output);
-
-	DCRYPTO_appkey_finish(&ctx);
-	return result;
-}
-
-int u2f_origin_key(const uint8_t *seed, p256_int *d)
-{
-	uint32_t tmp[P256_NDIGITS];
-
-	memcpy(tmp, seed, sizeof(tmp));
-	if (!_derive_key(U2F_ORIGIN, tmp, tmp))
-		return EC_ERROR_UNKNOWN;
-	return DCRYPTO_p256_key_from_bytes(NULL, NULL, d,
-					   (const uint8_t *)tmp) == 0;
-}
-
-int u2f_origin_user_keyhandle(const uint8_t *origin,
-			      const uint8_t *user,
-			      const uint8_t *origin_seed,
-			      uint8_t *key_handle)
-{
-	LITE_HMAC_CTX ctx;
-	struct u2f_state *state = get_state();
-
-	if (!state)
-		return EC_ERROR_UNKNOWN;
-
-	memcpy(key_handle, origin_seed, P256_NBYTES);
-
-	DCRYPTO_HMAC_SHA256_init(&ctx, state->salt_kek, SHA256_DIGEST_SIZE);
-	HASH_update(&ctx.hash, origin, P256_NBYTES);
-	HASH_update(&ctx.hash, user, P256_NBYTES);
-	HASH_update(&ctx.hash, origin_seed, P256_NBYTES);
-
-	memcpy(key_handle + P256_NBYTES,
-	       DCRYPTO_HMAC_final(&ctx), SHA256_DIGEST_SIZE);
-
-	return EC_SUCCESS;
-}
-
-int u2f_origin_user_keypair(const uint8_t *key_handle,
-			    p256_int *d,
-			    p256_int *pk_x,
-			    p256_int *pk_y)
-{
-	uint32_t dev_salt[P256_NDIGITS];
-	uint8_t key_seed[P256_NBYTES];
-
-	struct drbg_ctx drbg;
-	struct u2f_state *state = get_state();
-
-	if (!state)
-		return EC_ERROR_UNKNOWN;
-
-	if (!_derive_key(U2F_ORIGIN, state->salt_kek, dev_salt))
-		return EC_ERROR_UNKNOWN;
-
-	hmac_drbg_init(&drbg, state->salt_kh, P256_NBYTES, dev_salt,
-		       P256_NBYTES, NULL, 0);
-
-	hmac_drbg_generate(&drbg,
-			   key_seed, sizeof(key_seed),
-			   key_handle, P256_NBYTES * 2);
-
-	if (!DCRYPTO_p256_key_from_bytes(pk_x, pk_y, d, key_seed))
-		return EC_ERROR_TRY_AGAIN;
-
-	return EC_SUCCESS;
-}
-
-int u2f_gen_kek(const uint8_t *origin, uint8_t *kek, size_t key_len)
-{
-	uint32_t buf[P256_NDIGITS];
-
-	struct u2f_state *state = get_state();
-
-	if (!state)
-		return EC_ERROR_UNKNOWN;
-
-	if (key_len != sizeof(buf))
-		return EC_ERROR_UNKNOWN;
-	if (!_derive_key(U2F_WRAP, state->salt_kek, buf))
-		return EC_ERROR_UNKNOWN;
-	memcpy(kek, buf, key_len);
-
-	return EC_SUCCESS;
-}
-
-int g2f_individual_keypair(p256_int *d, p256_int *pk_x, p256_int *pk_y)
-{
-	uint8_t buf[SHA256_DIGEST_SIZE];
-
-	struct u2f_state *state = get_state();
-
-	if (!state)
-		return EC_ERROR_UNKNOWN;
-
-	/* Incorporate HIK & diversification constant */
-	if (!_derive_key(U2F_ATTEST, state->salt, (uint32_t *)buf))
-		return EC_ERROR_UNKNOWN;
-
-	/* Generate unbiased private key */
-	while (!DCRYPTO_p256_key_from_bytes(pk_x, pk_y, d, buf)) {
-		HASH_CTX sha;
-
-		DCRYPTO_SHA256_init(&sha, 0);
-		HASH_update(&sha, buf, sizeof(buf));
-		memcpy(buf, HASH_final(&sha), sizeof(buf));
-	}
-
-	return EC_SUCCESS;
-}
-
-int u2f_gen_kek_seed(int commit)
-{
-	struct u2f_state *state = get_state();
-
-	if (!state)
-		return EC_ERROR_UNKNOWN;
-
-	if (!DCRYPTO_ladder_random(state->salt_kek))
-		return EC_ERROR_HW_INTERNAL;
-
-	if (write_tpm_nvmem_hidden(TPM_HIDDEN_U2F_KEK, sizeof(state->salt_kek),
-				   state->salt_kek, commit) == tpm_write_fail)
-		return EC_ERROR_UNKNOWN;
-
-	return EC_SUCCESS;
-}
-
-/*
- * We need to keep a dummy version of this function around, as u2fd on M77 will
- * call it and not start up or send commands unless it receives a success
- * response. cr50 has been updated to no longer require the commands being sent,
- * so we don't need to do anything other than return a valid success response.
- */
-static enum vendor_cmd_rc vc_u2f_apdu_dummy(enum vendor_cmd_cc code, void *body,
-					    size_t cmd_size,
-					    size_t *response_size)
-{
-	uint8_t *cmd = body;
-
-	if (cmd_size < 3)
-		return VENDOR_RC_BOGUS_ARGS;
-
-	/*
-	 * The incoming APDUs are in the following format:
-	 *
-	 *   CLA INS   P1  P2  Le
-	 *   00  <ins> ??  ??  ??
-	 */
-
-	if (cmd[1] == 0xbf /* U2F_VENDOR_MODE */) {
-		/*
-		 * The u2fd code that call this command expects confirmation
-		 * that the mode was correctly set in the return message.
-		 *
-		 * The incoming APDU is in the following format:
-		 *
-		 *   CLA INS P1  P2      Le
-		 *   00  bf  01  <mode>  00
-		 */
-		cmd[0] = cmd[3];
-	} else if (cmd[1] == 0x03 /* U2F_VERSION */) {
-		/*
-		 * The returned value for U2F_VERSION is not checked; return
-		 * a known string just to be safe.
-		 */
-		cmd[0] = '2';
-	} else {
-		/* We're not expecting any other commands. */
-		*response_size = 0;
-		return VENDOR_RC_NO_SUCH_SUBCOMMAND;
-	}
-
-	/*
-	 * Return U2F_SW_NO_ERROR status.
-	 */
-	cmd[1] = 0x90;
-	cmd[2] = 0x00;
-	*response_size = 3;
-
-	return VENDOR_RC_SUCCESS;
-}
-DECLARE_VENDOR_COMMAND(VENDOR_CC_U2F_APDU, vc_u2f_apdu_dummy);
diff --git a/board/cr50/usb_i2c.c b/board/cr50/usb_i2c.c
deleted file mode 100644
index 0bc7408329..0000000000
--- a/board/cr50/usb_i2c.c
+++ /dev/null
@@ -1,106 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "case_closed_debug.h"
-#include "ccd_config.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "rdd.h"
-#include "registers.h"
-#include "system.h"
-#include "timer.h"
-#include "usb_i2c.h"
-
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
-
-int usb_i2c_board_is_enabled(void)
-{
-	/* board options use the INA pins as GPIOs */
-	if (!board_has_ina_support())
-		return 0;
-
-	/*
-	 * Note that this signal requires an external pullup, because this is
-	 * one of the real open drain pins; we cannot pull it up or drive it
-	 * high.  On test boards without the pullup, this will mis-detect as
-	 * enabled.
-	 */
-	return !gpio_get_level(GPIO_EN_PP3300_INA_L);
-}
-
-static void ina_disconnect(void)
-{
-	CPRINTS("I2C disconnect");
-
-	/* Disonnect I2C0 SDA/SCL output to B1/B0 pads */
-	GWRITE(PINMUX, DIOB1_SEL, 0);
-	GWRITE(PINMUX, DIOB0_SEL, 0);
-	/* Disconnect B1/B0 pads to I2C0 input SDA/SCL */
-	GWRITE(PINMUX, I2C0_SDA_SEL, 0);
-	GWRITE(PINMUX, I2C0_SCL_SEL, 0);
-
-	/* Disable power to INA chips */
-	gpio_set_level(GPIO_EN_PP3300_INA_L, 1);
-}
-
-static void ina_connect(void)
-{
-	CPRINTS("I2C connect");
-
-	/* Apply power to INA chips */
-	gpio_set_level(GPIO_EN_PP3300_INA_L, 0);
-
-	/*
-	 * Connect B0/B1 pads to I2C0 input SDA/SCL. Note, that the inputs
-	 * for these pads are already enabled for the gpio signals I2C_SCL_INA
-	 * and I2C_SDA_INA in gpio.inc.
-	 */
-	GWRITE(PINMUX, I2C0_SDA_SEL, GC_PINMUX_DIOB1_SEL);
-	GWRITE(PINMUX, I2C0_SCL_SEL, GC_PINMUX_DIOB0_SEL);
-
-	/* Connect I2CS SDA/SCL output to B1/B0 pads */
-	GWRITE(PINMUX, DIOB1_SEL, GC_PINMUX_I2C0_SDA_SEL);
-	GWRITE(PINMUX, DIOB0_SEL, GC_PINMUX_I2C0_SCL_SEL);
-
-	/*
-	 * Initialize the i2cm module after the INAs are powered and the signal
-	 * lines are connected.
-	 */
-	i2cm_init();
-}
-
-void usb_i2c_board_disable(void)
-{
-	if (!usb_i2c_board_is_enabled())
-		return;
-
-	ina_disconnect();
-}
-
-int usb_i2c_board_enable(void)
-{
-	/* board options use the INA pins as GPIOs */
-	if (!board_has_ina_support())
-		return EC_SUCCESS;
-
-	if (servo_is_connected()) {
-		CPRINTS("Servo attached; cannot enable I2C");
-		usb_i2c_board_disable();
-		return EC_ERROR_BUSY;
-	}
-
-	if (!ccd_ext_is_enabled())
-		return EC_ERROR_BUSY;
-
-	if (!ccd_is_cap_enabled(CCD_CAP_I2C))
-		return EC_ERROR_ACCESS_DENIED;
-
-	if (!usb_i2c_board_is_enabled())
-		ina_connect();
-
-	return EC_SUCCESS;
-}
diff --git a/board/cr50/usb_spi.c b/board/cr50/usb_spi.c
deleted file mode 100644
index 66083de4b1..0000000000
--- a/board/cr50/usb_spi.c
+++ /dev/null
@@ -1,766 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "byteorder.h"
-#include "ccd_config.h"
-#include "cryptoc/sha256.h"
-#include "console.h"
-#include "dcrypto.h"
-#include "extension.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "physical_presence.h"
-#include "registers.h"
-#include "spi.h"
-#include "spi_flash.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "tpm_registers.h"
-#include "tpm_vendor_cmds.h"
-#include "usb_spi.h"
-
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
-
-/* Don't hash more than this at once */
-#define MAX_SPI_HASH_SIZE (4 * 1024 * 1024)
-
-/*
- * Buffer size to use for reading and hashing.  This must be a multiple of the
- * SHA256 block size (64 bytes) and at least 4 less than the maximum SPI
- * transaction size for H1 (0x80 bytes).  So, 64.
- */
-#define SPI_HASH_CHUNK_SIZE 64
-
-/* Timeout for auto-disabling SPI hash device, in microseconds */
-#define SPI_HASH_TIMEOUT_US (60 * SECOND)
-
-/* Current device for SPI hashing */
-static uint8_t spi_hash_device = USB_SPI_DISABLE;
-
-/*
- * Do we need to use NPCX7 gang programming mode?
- *
- * If 0, then we hold the EC in reset the whole time we've acquired the SPI
- * bus, to keep the EC from accessing it.
- *
- * If 1, then:
- *
- *	When we acquire the EC SPI bus, we need to reset the EC, assert the
- *	gang programmer enable, then take the EC out of reset so its boot ROM
- *	can map the EC's internal SPI bus to the EC gang programmer pins.
- *
- *	When we relinquish the EC SPI bus, we need to reset the EC again while
- *	keeping gang programmer deasserted, then take the EC out of reset.  The
- *	EC will then boot normally.
- */
-static uint8_t use_npcx_gang_mode;
-
-/*
- * Device and gang mode selected by last spihash command, for use by
- * spi_hash_pp_done().
- */
-static uint8_t new_device;
-static uint8_t new_gang_mode;
-
-static void spi_hash_inactive_timeout(void);
-DECLARE_DEFERRED(spi_hash_inactive_timeout);
-
-/*****************************************************************************/
-/*
- * Mutex and variable for tracking whether the SPI bus is used by the USB
- * connection or hashing commands.
- *
- * Access these ONLY through set_spi_bus_user() and get_spi_bus_user(), to
- * ensure thread-safe access to the SPI bus.
- */
-static struct mutex spi_bus_user_mutex;
-static enum spi_bus_user_t {
-	SPI_BUS_USER_NONE = 0,
-	SPI_BUS_USER_USB,
-	SPI_BUS_USER_HASH
-} spi_bus_user = SPI_BUS_USER_NONE;
-
-/**
- * Set who's using the SPI bus.
- *
- * This is thread-safe and will not block if someone owns the bus.  You can't
- * take the bus if someone else has it, and you can only free it if you hold
- * it.  It has no extra effect if you already own the bus.
- *
- * @param user		What bus user is asking?
- * @param want_bus	Do we want the bus (!=0) or no longer want it (==0)?
- *
- * @return EC_SUCCESS, or non-zero error code.
- */
-static int set_spi_bus_user(enum spi_bus_user_t user, int want_bus)
-{
-	int rv = EC_SUCCESS;
-
-	/*
-	 * Serialize access to bus user variable, but don't mutex lock the
-	 * entire bus because that would freeze USB or the console instead of
-	 * just failing.
-	 */
-	mutex_lock(&spi_bus_user_mutex);
-
-	if (want_bus) {
-		/* Can only take the bus if it's free or we already own it */
-		if (spi_bus_user == SPI_BUS_USER_NONE)
-			spi_bus_user = user;
-		else if (spi_bus_user != user)
-			rv = EC_ERROR_BUSY;
-	} else {
-		/* Can only free the bus if it was ours */
-		if (spi_bus_user == user)
-			spi_bus_user = SPI_BUS_USER_NONE;
-		else
-			rv = EC_ERROR_BUSY;
-	}
-
-	mutex_unlock(&spi_bus_user_mutex);
-
-	return rv;
-}
-
-/**
- * Get the current SPI bus user.
- */
-static enum spi_bus_user_t get_spi_bus_user(void)
-{
-	return spi_bus_user;
-}
-
-/*****************************************************************************/
-/* Methods to enable / disable the SPI bus and pin mux */
-
-static void disable_ec_ap_spi(void)
-{
-	int was_ap_spi_en = gpio_get_level(GPIO_AP_FLASH_SELECT);
-
-	/* Disable EC SPI access. */
-	gpio_set_level(GPIO_EC_FLASH_SELECT, 0);
-
-	/* Disable AP SPI access. */
-	if (was_ap_spi_en) {
-		/*
-		 * The fact that AP SPI access was enabled means that the EC was
-		 * held in reset.  Therefore, it needs to be released here.
-		 */
-		gpio_set_level(GPIO_AP_FLASH_SELECT, 0);
-		deassert_ec_rst();
-		deassert_sys_rst();
-	}
-}
-
-static void enable_ec_spi(void)
-{
-	/* Select EC flash */
-	gpio_set_level(GPIO_AP_FLASH_SELECT, 0);
-	gpio_set_level(GPIO_EC_FLASH_SELECT, 1);
-
-	/*
-	 * Note that we don't hold the EC in reset here.  This is because some
-	 * ECs with internal SPI flash cannot be held in reset in order to
-	 * access the flash.
-	 */
-}
-
-static void enable_ap_spi(void)
-{
-	/* Select AP flash */
-	gpio_set_level(GPIO_AP_FLASH_SELECT, 1);
-	gpio_set_level(GPIO_EC_FLASH_SELECT, 0);
-
-	/*
-	 * On some systems SYS_RST_L is not level sensitive, so the only way to
-	 * be sure we're holding the AP in reset is to hold the EC in reset.
-	 */
-	assert_ec_rst();
-}
-
-/**
- * Enable the pin mux to the SPI master port.
- */
-static void enable_spi_pinmux(void)
-{
-	GWRITE_FIELD(PINMUX, DIOA4_CTL, PD, 0);    /* SPI_MOSI */
-	GWRITE_FIELD(PINMUX, DIOA8_CTL, PD, 0);    /* SPI_CLK */
-
-	/* Connect DIO A4, A8, and A14 to the SPI peripheral */
-	GWRITE(PINMUX, DIOA4_SEL, 0); /* SPI_MOSI */
-	GWRITE(PINMUX, DIOA8_SEL, 0); /* SPI_CS_L */
-	GWRITE(PINMUX, DIOA14_SEL, 0); /* SPI_CLK */
-	/* Set SPI_CS to be an internal pull up */
-	GWRITE_FIELD(PINMUX, DIOA14_CTL, PU, 1);
-
-	CPRINTS("%s: %s", __func__,
-		gpio_get_level(GPIO_AP_FLASH_SELECT) ? "AP" : "EC");
-
-	spi_enable(CONFIG_SPI_FLASH_PORT, 1);
-}
-
-/**
- * Disable the pin mux to the SPI master port.
- */
-static void disable_spi_pinmux(void)
-{
-	spi_enable(CONFIG_SPI_FLASH_PORT, 0);
-
-	/* Disconnect SPI peripheral to tri-state pads */
-	/* Disable internal pull up */
-	GWRITE_FIELD(PINMUX, DIOA14_CTL, PU, 0);
-	/* TODO: Implement way to get the gpio */
-	ASSERT(GREAD(PINMUX, GPIO0_GPIO7_SEL) == GC_PINMUX_DIOA4_SEL);
-	ASSERT(GREAD(PINMUX, GPIO0_GPIO8_SEL) == GC_PINMUX_DIOA8_SEL);
-	ASSERT(GREAD(PINMUX, GPIO0_GPIO9_SEL) == GC_PINMUX_DIOA14_SEL);
-
-	GWRITE_FIELD(PINMUX, DIOA4_CTL, PD, 1);    /* SPI_MOSI */
-	GWRITE_FIELD(PINMUX, DIOA8_CTL, PD, 1);    /* SPI_CLK */
-
-	/* Set SPI MOSI, CLK, and CS_L as inputs */
-	GWRITE(PINMUX, DIOA4_SEL, GC_PINMUX_GPIO0_GPIO7_SEL);
-	GWRITE(PINMUX, DIOA8_SEL, GC_PINMUX_GPIO0_GPIO8_SEL);
-	GWRITE(PINMUX, DIOA14_SEL, GC_PINMUX_GPIO0_GPIO9_SEL);
-}
-
-/*****************************************************************************/
-/* USB SPI methods */
-
-int usb_spi_board_enable(struct usb_spi_config const *config)
-{
-	int host = config->state->enabled_host;
-
-	/* Make sure we're allowed to enable the requested device */
-	if (host == USB_SPI_EC) {
-		if (!ccd_is_cap_enabled(CCD_CAP_EC_FLASH)) {
-			CPRINTS("%s: EC access denied", __func__);
-			return EC_ERROR_ACCESS_DENIED;
-		}
-	} else if (host == USB_SPI_AP) {
-		if (!ccd_is_cap_enabled(CCD_CAP_AP_FLASH)) {
-			CPRINTS("%s: AP access denied", __func__);
-			return EC_ERROR_ACCESS_DENIED;
-		}
-	} else {
-		CPRINTS("%s: device %d not supported", __func__, host);
-		return EC_ERROR_INVAL;
-	}
-
-	if (set_spi_bus_user(SPI_BUS_USER_USB, 1) != EC_SUCCESS) {
-		CPRINTS("%s: bus in use", __func__);
-		return EC_ERROR_BUSY;
-	}
-
-	disable_ec_ap_spi();
-
-	/*
-	 * Only need to check EC vs. AP, because other hosts were ruled out
-	 * above.
-	 */
-	if (host == USB_SPI_EC)
-		enable_ec_spi();
-	else
-		enable_ap_spi();
-
-	enable_spi_pinmux();
-	return EC_SUCCESS;
-}
-
-void usb_spi_board_disable(struct usb_spi_config const *config)
-{
-	CPRINTS("%s", __func__);
-
-	/* Only disable the SPI bus if we own it */
-	if (get_spi_bus_user() != SPI_BUS_USER_USB)
-		return;
-
-	disable_spi_pinmux();
-	disable_ec_ap_spi();
-	set_spi_bus_user(SPI_BUS_USER_USB, 0);
-}
-
-int usb_spi_interface(struct usb_spi_config const *config,
-		      struct usb_setup_packet *req)
-{
-	if (req->bmRequestType != (USB_DIR_OUT |
-				    USB_TYPE_VENDOR |
-				    USB_RECIP_INTERFACE))
-		return 1;
-
-	if (req->wValue  != 0 ||
-	    req->wIndex  != config->interface ||
-	    req->wLength != 0)
-		return 1;
-
-	if (!config->state->enabled_device)
-		return 1;
-
-	switch (req->bRequest) {
-	case USB_SPI_REQ_ENABLE_AP:
-		config->state->enabled_host = USB_SPI_AP;
-		break;
-	case USB_SPI_REQ_ENABLE_EC:
-		config->state->enabled_host = USB_SPI_EC;
-		break;
-	case USB_SPI_REQ_ENABLE:
-		CPRINTS("%s: Must specify target", __func__);
-		/* Fall through... */
-	case USB_SPI_REQ_DISABLE:
-		config->state->enabled_host = USB_SPI_DISABLE;
-		break;
-
-	default:
-		return 1;
-	}
-
-	/*
-	 * Our state has changed, call the deferred function to handle the
-	 * state change.
-	 */
-	hook_call_deferred(config->deferred, 0);
-	return 0;
-}
-
-/*****************************************************************************/
-/* Hashing support */
-
-/**
- * Returns the content of SPI flash
- *
- * @param buf_usr Buffer to write flash contents
- * @param offset Flash offset to start reading from
- * @param bytes Number of bytes to read.
- *
- * @return EC_SUCCESS, or non-zero if any error.
- */
-int spi_read_chunk(uint8_t *buf_usr, unsigned int offset, unsigned int bytes)
-{
-	uint8_t cmd[4];
-
-	if (bytes > SPI_HASH_CHUNK_SIZE)
-		return EC_ERROR_INVAL;
-
-	cmd[0] = SPI_FLASH_READ;
-	cmd[1] = (offset >> 16) & 0xFF;
-	cmd[2] = (offset >> 8) & 0xFF;
-	cmd[3] = offset & 0xFF;
-
-	return spi_transaction(SPI_FLASH_DEVICE, cmd, 4, buf_usr, bytes);
-}
-
-/**
- * Reset EC out of gang programming mode if needed.
- */
-static void spi_hash_stop_ec_device(void)
-{
-	/* If device is not currently EC, nothing to do */
-	if (spi_hash_device != USB_SPI_EC)
-		return;
-
-	if (use_npcx_gang_mode) {
-		/*
-		 * EC was in gang mode.  Pulse reset without asserting gang
-		 * programmer enable, so that when we take the EC out of reset
-		 * it will boot normally.
-		 */
-		assert_ec_rst();
-		usleep(200);
-		use_npcx_gang_mode = 0;
-	}
-
-	/*
-	 * Release EC from reset (either from above, or because gang progamming
-	 * mode was disabled so the EC was held in reset during SPI access).
-	 */
-	deassert_ec_rst();
-}
-
-/**
- * Disable SPI hashing mode.
- *
- * @return Vendor command return code.
- */
-static enum vendor_cmd_rc spi_hash_disable(void)
-{
-	if (spi_hash_device == USB_SPI_DISABLE)
-		return VENDOR_RC_SUCCESS;
-
-	/* Can't disable SPI if we don't own it */
-	if (get_spi_bus_user() != SPI_BUS_USER_HASH)
-		return VENDOR_RC_NOT_ALLOWED;
-
-	/* Disable the SPI bus and chip select */
-	disable_spi_pinmux();
-	disable_ec_ap_spi();
-
-	/* Stop the EC device, if it was active */
-	spi_hash_stop_ec_device();
-
-	/* Release the bus */
-	spi_hash_device = USB_SPI_DISABLE;
-	new_device = USB_SPI_DISABLE;
-	new_gang_mode = 0;
-	set_spi_bus_user(SPI_BUS_USER_HASH, 0);
-
-	/* Disable inactivity timer to turn hashing mode off */
-	hook_call_deferred(&spi_hash_inactive_timeout_data, -1);
-
-	CPRINTS("%s", __func__);
-	return VENDOR_RC_SUCCESS;
-}
-
-/**
- * Deferred function to disable SPI hash mode on inactivity.
- */
-static void spi_hash_inactive_timeout(void)
-{
-	spi_hash_disable();
-}
-
-/**
- * Callback to set up the new SPI device after physical presence check.
- */
-static void spi_hash_pp_done(void)
-{
-	/* Acquire the bus */
-	if (set_spi_bus_user(SPI_BUS_USER_HASH, 1)) {
-		CPRINTS("%s: bus busy", __func__);
-		return;
-	}
-
-	/* Clear previous enable if needed */
-	if (spi_hash_device != USB_SPI_DISABLE)
-		disable_ec_ap_spi();
-
-	/* Set up new device */
-	if (new_device == USB_SPI_AP) {
-		/* Stop the EC device, if it was previously active */
-		spi_hash_stop_ec_device();
-
-		enable_ap_spi();
-	} else {
-		/* Force the EC into reset and enable EC SPI bus */
-		assert_ec_rst();
-		enable_ec_spi();
-
-		/*
-		 * If EC is headed into gang programmer mode, need to release
-		 * EC from reset after acquiring the bus.  EC_FLASH_SELECT runs
-		 * to the EC's GP_SEL_ODL signal, which is what enables gang
-		 * programmer mode.
-		 */
-		if (new_gang_mode) {
-			usleep(200);
-			deassert_ec_rst();
-			use_npcx_gang_mode = 1;
-		}
-	}
-
-	enable_spi_pinmux();
-	spi_hash_device = new_device;
-
-	/* Start inactivity timer to turn hashing mode off */
-	hook_call_deferred(&spi_hash_inactive_timeout_data,
-			   SPI_HASH_TIMEOUT_US);
-
-	CPRINTS("%s: %s", __func__,
-		(spi_hash_device == USB_SPI_AP ? "AP" : "EC"));
-}
-
-/* Process vendor subcommand dealing with Physical presence polling. */
-static enum vendor_cmd_rc spihash_pp_poll(void *buf,
-					  size_t input_size,
-					  size_t *response_size)
-{
-	char *buffer = buf;
-
-	if (spi_hash_device != USB_SPI_DISABLE) {
-		buffer[0] = CCD_PP_DONE;
-	} else {
-		switch (physical_presense_fsm_state()) {
-		case PP_AWAITING_PRESS:
-			buffer[0] = CCD_PP_AWAITING_PRESS;
-			break;
-		case PP_BETWEEN_PRESSES:
-			buffer[0] = CCD_PP_BETWEEN_PRESSES;
-			break;
-		default:
-			buffer[0] = CCD_PP_CLOSED;
-			break;
-		}
-	}
-	*response_size = 1;
-	return VENDOR_RC_SUCCESS;
-}
-
-/**
- * Set the SPI hashing device.
- *
- * @param dev		Device (enum usb_spi)
- * @param gang_mode	If non-zero, EC uses gang mode
- *
- * @return Vendor command return code
- */
-static enum vendor_cmd_rc spi_hash_set_device(int dev, int gang_mode,
-					      uint8_t *response_buf,
-					      size_t *response_size)
-{
-	*response_size = 0;
-
-	if (dev == spi_hash_device)
-		return VENDOR_RC_SUCCESS;
-
-	/* Enabling requires permission */
-	if (!(ccd_is_cap_enabled(CCD_CAP_FLASH_READ)))
-		return VENDOR_RC_NOT_ALLOWED;
-
-	new_device = dev;
-	new_gang_mode = gang_mode;
-
-	/* Handle enabling */
-	if (spi_hash_device == USB_SPI_DISABLE &&
-	    !(ccd_is_cap_enabled(CCD_CAP_AP_FLASH) &&
-	      ccd_is_cap_enabled(CCD_CAP_EC_FLASH))) {
-		/*
-		 * We were disabled, and CCD does not grant permission
-		 * to both flash chips.  So we need physical presence
-		 * to take the SPI bus.  That prevents a malicious
-		 * peripheral from using this to reset the device.
-		 *
-		 * Technically, we could track the chips separately,
-		 * and only require physical presence the first time we
-		 * check a chip which CCD doesn't grant access to.  But
-		 * that's more bookkeeping, so for now the only way to
-		 * skip physical presence is to have access to both.
-		 */
-		int rv = physical_detect_start(0, spi_hash_pp_done);
-
-		if (rv == EC_SUCCESS)
-			return VENDOR_RC_IN_PROGRESS;
-
-		*response_size = 1;
-		response_buf[0] = rv;
-
-		return VENDOR_RC_INTERNAL_ERROR;
-	}
-
-	/*
-	 * If we're still here, we already own the SPI bus, and are
-	 * changing which chip we're looking at.  Update hash device
-	 * directly; no new physical presence required.
-	 */
-	spi_hash_pp_done();
-	return VENDOR_RC_SUCCESS;
-}
-
-static enum vendor_cmd_rc spi_hash_dump(uint8_t *dest, uint32_t offset,
-					uint32_t size)
-{
-	/* Fail if we don't own the bus */
-	if (get_spi_bus_user() != SPI_BUS_USER_HASH) {
-		CPRINTS("%s: not enabled", __func__);
-		return VENDOR_RC_NOT_ALLOWED;
-	}
-
-	/* Bump inactivity timer to turn hashing mode off */
-	hook_call_deferred(&spi_hash_inactive_timeout_data,
-			   SPI_HASH_TIMEOUT_US);
-
-	if (size > SPI_HASH_MAX_RESPONSE_BYTES)
-		return VENDOR_RC_BOGUS_ARGS;
-
-	if (spi_read_chunk(dest, offset, size) != EC_SUCCESS) {
-		CPRINTS("%s: read error at 0x%x", __func__, offset);
-		return VENDOR_RC_READ_FLASH_FAIL;
-	}
-
-	return VENDOR_RC_SUCCESS;
-}
-
-static enum vendor_cmd_rc spi_hash_sha256(uint8_t *dest, uint32_t offset,
-					  uint32_t size)
-{
-	HASH_CTX sha;
-	uint8_t data[SPI_HASH_CHUNK_SIZE];
-	int chunk_size = SPI_HASH_CHUNK_SIZE;
-	int chunks = 0;
-
-	/* Fail if we don't own the bus */
-	if (get_spi_bus_user() != SPI_BUS_USER_HASH) {
-		CPRINTS("%s: not enabled", __func__);
-		return VENDOR_RC_NOT_ALLOWED;
-	}
-
-	/* Bump inactivity timer to turn hashing mode off */
-	hook_call_deferred(&spi_hash_inactive_timeout_data,
-			   SPI_HASH_TIMEOUT_US);
-
-	if (size > MAX_SPI_HASH_SIZE)
-		return VENDOR_RC_BOGUS_ARGS;
-
-	CPRINTS("%s: 0x%x 0x%x", __func__, offset, size);
-
-	DCRYPTO_SHA256_init(&sha, 0);
-
-	for (chunks = 0; size > 0; chunks++) {
-		int this_chunk = MIN(size, chunk_size);
-		/* Read the data */
-		if (spi_read_chunk(data, offset, this_chunk) != EC_SUCCESS) {
-			CPRINTS("%s: read error at 0x%x", __func__, offset);
-			return VENDOR_RC_READ_FLASH_FAIL;
-		}
-
-		/* Update hash */
-		HASH_update(&sha, data, this_chunk);
-
-		/* Give other things a chance to happen */
-		if (!(chunks % 128))
-			msleep(1);
-
-		size -= this_chunk;
-		offset += this_chunk;
-	}
-
-	memcpy(dest, HASH_final(&sha), SHA256_DIGEST_SIZE);
-
-	CPRINTS("%s: done", __func__);
-	return VENDOR_RC_SUCCESS;
-}
-
-/*
- * TPM Vendor command handler for SPI hash commands which need to be available
- * both through CLI and over /dev/tpm0.
- */
-static enum vendor_cmd_rc spi_hash_vendor(enum vendor_cmd_cc code,
-					  void *buf,
-					  size_t input_size,
-					  size_t *response_size)
-{
-	const struct vendor_cc_spi_hash_request *req = buf;
-	enum vendor_cmd_rc rc;
-
-	/* Default to no response data */
-	*response_size = 0;
-
-	/* Pick what to do based on subcommand. */
-	switch (req->subcmd) {
-	case SPI_HASH_SUBCMD_DISABLE:
-		/* Handle disabling */
-		return spi_hash_disable();
-	case SPI_HASH_SUBCMD_AP:
-		return spi_hash_set_device(USB_SPI_AP, 0, buf, response_size);
-	case SPI_HASH_SUBCMD_EC:
-		return spi_hash_set_device(USB_SPI_EC,
-					   !!(req->flags &
-					      SPI_HASH_FLAG_EC_GANG),
-					   buf, response_size);
-	case SPI_HASH_SUBCMD_SHA256:
-		*response_size = SHA256_DIGEST_SIZE;
-		rc = spi_hash_sha256(buf, req->offset, req->size);
-		if (rc != VENDOR_RC_SUCCESS)
-			*response_size = 0;
-		return rc;
-	case SPI_HASH_SUBCMD_DUMP:
-		/* Save size before we overwrite it with data */
-		*response_size = req->size;
-		rc = spi_hash_dump(buf, req->offset, req->size);
-		if (rc != VENDOR_RC_SUCCESS)
-			*response_size = 0;
-		return rc;
-	case SPI_HASH_PP_POLL:
-		return spihash_pp_poll(buf, input_size, response_size);
-
-	default:
-		CPRINTS("%s:%d - unknown subcommand %d",
-			__func__, __LINE__, req->subcmd);
-		*response_size = 0;
-		return VENDOR_RC_NO_SUCH_SUBCOMMAND;
-	}
-}
-DECLARE_VENDOR_COMMAND(VENDOR_CC_SPI_HASH, spi_hash_vendor);
-
-/**
- * Wrapper for hash commands which are passed through the TPM task context.
- */
-static int hash_command_wrapper(int argc, char *argv[])
-{
-	int rv;
-	struct vendor_cc_spi_hash_request req;
-	struct tpm_cmd_header *tpm_header;
-	const size_t command_size = sizeof(*tpm_header) +
-			MAX(sizeof(req), SPI_HASH_MAX_RESPONSE_BYTES);
-	uint8_t buf[command_size];
-	uint8_t *p;
-	uint32_t return_code;
-
-	/* If no args, just return */
-	if (argc < 2) {
-		ccprintf("SPI hash device: %s\n",
-			 (spi_hash_device ?
-			  (spi_hash_device == USB_SPI_AP ? "AP" : "EC") :
-			  "disable"));
-		return EC_SUCCESS;
-	}
-
-	/* Parse args into stack-based struct */
-	memset(&req, 0, sizeof(req));
-	if (!strcasecmp(argv[1], "AP")) {
-		req.subcmd = SPI_HASH_SUBCMD_AP;
-	} else if (!strcasecmp(argv[1], "EC")) {
-		req.subcmd = SPI_HASH_SUBCMD_EC;
-		if (argc > 2 && !strcasecmp(argv[2], "gang"))
-			req.flags |= SPI_HASH_FLAG_EC_GANG;
-	} else if (!strcasecmp(argv[1], "disable")) {
-		req.subcmd = SPI_HASH_SUBCMD_DISABLE;
-	} else if (argc == 3) {
-		req.subcmd = SPI_HASH_SUBCMD_SHA256;
-		rv = parse_offset_size(argc, argv, 1, &req.offset, &req.size);
-		if (rv)
-			return rv;
-	} else if (argc == 4 && !strcasecmp(argv[1], "dump")) {
-		req.subcmd = SPI_HASH_SUBCMD_DUMP;
-		rv = parse_offset_size(argc, argv, 2, &req.offset, &req.size);
-		if (rv)
-			return rv;
-	} else {
-		return EC_ERROR_PARAM1;
-	}
-
-	/* Build the extension command */
-	tpm_header = (struct tpm_cmd_header *)buf;
-	tpm_header->tag = htobe16(0x8001); /* TPM_ST_NO_SESSIONS */
-	tpm_header->size = htobe32(command_size);
-	tpm_header->command_code = htobe32(TPM_CC_VENDOR_BIT_MASK);
-	tpm_header->subcommand_code = htobe16(VENDOR_CC_SPI_HASH);
-	/* Copy request data */
-	p = (uint8_t *)(tpm_header + 1);
-	memcpy(p, &req, sizeof(req));
-
-	tpm_alt_extension(tpm_header, command_size);
-
-	/*
-	 * Return status in the command code field now, in case of error,
-	 * error code is the first byte after the header.
-	 */
-	return_code = be32toh(tpm_header->command_code);
-
-	if ((return_code != EC_SUCCESS) &&
-	    ((return_code - VENDOR_RC_ERR) != VENDOR_RC_IN_PROGRESS)) {
-		rv = p[0];
-	} else {
-		rv = EC_SUCCESS;
-
-		if (req.subcmd == SPI_HASH_SUBCMD_DUMP)
-			ccprintf("data: %ph\n", HEX_BUF(p, req.size));
-		else if (req.subcmd == SPI_HASH_SUBCMD_SHA256)
-			ccprintf("hash: %ph\n", HEX_BUF(p, 32));
-	}
-
-	return rv;
-}
-DECLARE_SAFE_CONSOLE_COMMAND(spihash, hash_command_wrapper,
-		     "ap | ec [gang] | disable | [dump] <offset> <size>",
-		     "Hash SPI flash via TPM vendor command");
diff --git a/board/cr50/wp.c b/board/cr50/wp.c
deleted file mode 100644
index 8e9be0edeb..0000000000
--- a/board/cr50/wp.c
+++ /dev/null
@@ -1,530 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "ccd_config.h"
-#include "console.h"
-#include "crc8.h"
-#include "ec_commands.h"
-#include "extension.h"
-#include "flash_log.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "scratch_reg1.h"
-#include "system.h"
-#include "system_chip.h"
-#include "tpm_nvmem.h"
-#include "tpm_nvmem_ops.h"
-#include "tpm_registers.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_RBOX, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_RBOX, format, ## args)
-
-uint8_t bp_connect;
-uint8_t bp_forced;
-/**
- * Return non-zero if battery is present
- */
-int board_battery_is_present(void)
-{
-	/* Invert because battery-present signal is active low */
-	return bp_forced ? bp_connect : !gpio_get_level(GPIO_BATT_PRES_L);
-}
-
-/**
- * Return non-zero if the wp state is being overridden.
- */
-static int board_forcing_wp(void)
-{
-	return GREG32(PMU, LONG_LIFE_SCRATCH1) & BOARD_FORCING_WP;
-}
-
-/**
- * Set the current write protect state in RBOX and long life scratch register.
- *
- * @param asserted: 0 to disable write protect, otherwise enable write protect.
- */
-static void set_wp_state(int asserted)
-{
-	/* Enable writing to the long life register */
-	GWRITE_FIELD(PMU, LONG_LIFE_SCRATCH_WR_EN, REG1, 1);
-
-	if (asserted) {
-		GREG32(PMU, LONG_LIFE_SCRATCH1) |= BOARD_WP_ASSERTED;
-		GREG32(RBOX, EC_WP_L) = 0;
-	} else {
-		GREG32(PMU, LONG_LIFE_SCRATCH1) &= ~BOARD_WP_ASSERTED;
-		GREG32(RBOX, EC_WP_L) = 1;
-	}
-
-	/* Disable writing to the long life register */
-	GWRITE_FIELD(PMU, LONG_LIFE_SCRATCH_WR_EN, REG1, 0);
-}
-
-/**
- * Return the current WP state
- *
- * @return 0 if WP deasserted, 1 if WP asserted
- */
-int wp_is_asserted(void)
-{
-	/* Signal is active low, so invert */
-	return !GREG32(RBOX, EC_WP_L);
-}
-
-static void check_wp_battery_presence(void)
-{
-	int bp = board_battery_is_present();
-
-	/* If we're forcing WP, ignore battery detect */
-	if (board_forcing_wp())
-		return;
-
-	/* Otherwise, mirror battery */
-	if (bp != wp_is_asserted()) {
-		CPRINTS("WP %d", bp);
-		set_wp_state(bp);
-	}
-}
-DECLARE_HOOK(HOOK_SECOND, check_wp_battery_presence, HOOK_PRIO_DEFAULT);
-
-/**
- * Force write protect state or follow battery presence.
- *
- * @param force: Force write protect to wp_en if non-zero, otherwise use battery
- *               presence as the source.
- * @param wp_en: 0: Deassert WP. 1: Assert WP.
- */
-static void force_write_protect(int force, int wp_en)
-{
-	/* Enable writing to the long life register */
-	GWRITE_FIELD(PMU, LONG_LIFE_SCRATCH_WR_EN, REG1, 1);
-
-	if (force) {
-		/* Force WP regardless of battery presence. */
-		GREG32(PMU, LONG_LIFE_SCRATCH1) |= BOARD_FORCING_WP;
-	} else {
-		/* Stop forcing write protect. */
-		GREG32(PMU, LONG_LIFE_SCRATCH1) &= ~BOARD_FORCING_WP;
-		/* Use battery presence as the value for write protect. */
-		wp_en = board_battery_is_present();
-	}
-
-	/* Disable writing to the long life register */
-	GWRITE_FIELD(PMU, LONG_LIFE_SCRATCH_WR_EN, REG1, 0);
-
-	/* Update the WP state. */
-	set_wp_state(wp_en);
-}
-
-static enum vendor_cmd_rc vc_set_wp(enum vendor_cmd_cc code,
-				    void *buf,
-				    size_t input_size,
-				    size_t *response_size)
-{
-	uint8_t response = 0;
-
-	*response_size = 0;
-	/* There shouldn't be any args */
-	if (input_size)
-		return VENDOR_RC_BOGUS_ARGS;
-
-	/* Get current wp settings */
-	if (board_forcing_wp())
-		response |= WPV_FORCE;
-	if (wp_is_asserted())
-		response |= WPV_ENABLE;
-	/* Get atboot wp settings */
-	if (ccd_get_flag(CCD_FLAG_OVERRIDE_WP_AT_BOOT)) {
-		response |= WPV_ATBOOT_SET;
-		if (ccd_get_flag(CCD_FLAG_OVERRIDE_WP_STATE_ENABLED))
-			response |= WPV_ATBOOT_ENABLE;
-	}
-	((uint8_t *)buf)[0] = response;
-	*response_size = sizeof(response);
-	return VENDOR_RC_SUCCESS;
-}
-DECLARE_VENDOR_COMMAND(VENDOR_CC_WP, vc_set_wp);
-
-static int command_bpforce(int argc, char **argv)
-{
-	int val = 1;
-	int forced = 1;
-
-	if (argc > 1) {
-		/* Make sure we're allowed to override battery presence */
-		if (!ccd_is_cap_enabled(CCD_CAP_OVERRIDE_BATT_STATE))
-			return EC_ERROR_ACCESS_DENIED;
-
-		/* Update BP */
-		if (!strncasecmp(argv[1], "follow", 6))
-			forced = 0;
-		else if (!strncasecmp(argv[1], "dis", 3))
-			val = 0;
-		else if (strncasecmp(argv[1], "con", 3))
-			return EC_ERROR_PARAM2;
-
-		bp_forced = forced;
-		bp_connect = val;
-
-		if (argc > 2 && !strcasecmp(argv[2], "atboot")) {
-			/* Change override at boot to match */
-			ccd_set_flag(CCD_FLAG_OVERRIDE_BATT_AT_BOOT, bp_forced);
-			ccd_set_flag(CCD_FLAG_OVERRIDE_BATT_STATE_CONNECT,
-				     bp_connect);
-		}
-		/* Update the WP state based on new battery presence setting */
-		check_wp_battery_presence();
-	}
-
-	ccprintf("batt pres: %s%sconnect\n", bp_forced ? "forced " : "",
-		 board_battery_is_present() ? "" : "dis");
-	ccprintf("  at boot: ");
-	if (ccd_get_flag(CCD_FLAG_OVERRIDE_BATT_AT_BOOT))
-		ccprintf("forced %sconnect\n",
-			 ccd_get_flag(CCD_FLAG_OVERRIDE_BATT_STATE_CONNECT) ? ""
-			 : "dis");
-	else
-		ccprintf("follow_batt_pres\n");
-	return EC_SUCCESS;
-}
-DECLARE_SAFE_CONSOLE_COMMAND(bpforce, command_bpforce,
-			     "[connect|disconnect|follow_batt_pres [atboot]]",
-			     "Get/set BATT_PRES_L signal override");
-
-static int command_wp(int argc, char **argv)
-{
-	int val;
-	int forced;
-
-	if (argc > 1) {
-		/* Make sure we're allowed to override WP settings */
-		if (!ccd_is_cap_enabled(CCD_CAP_OVERRIDE_WP))
-			return EC_ERROR_ACCESS_DENIED;
-
-		/* Update WP */
-		if (!strncasecmp(argv[1], "follow", 6))
-			forced = 0;
-		else if (parse_bool(argv[1], &val))
-			forced = 1;
-		else
-			return EC_ERROR_PARAM1;
-
-		force_write_protect(forced, val);
-
-		if (argc > 2 && !strcasecmp(argv[2], "atboot")) {
-			/* Change override at boot to match */
-			ccd_set_flag(CCD_FLAG_OVERRIDE_WP_AT_BOOT, forced);
-			ccd_set_flag(CCD_FLAG_OVERRIDE_WP_STATE_ENABLED, val);
-		}
-	}
-
-	ccprintf("Flash WP: %s%sabled\n", board_forcing_wp() ? "forced " : "",
-		 wp_is_asserted() ? "en" : "dis");
-	ccprintf(" at boot: ");
-	if (ccd_get_flag(CCD_FLAG_OVERRIDE_WP_AT_BOOT))
-		ccprintf("forced %sabled\n",
-			 ccd_get_flag(CCD_FLAG_OVERRIDE_WP_STATE_ENABLED)
-			 ? "en" : "dis");
-	else
-		ccprintf("follow_batt_pres\n");
-
-	return EC_SUCCESS;
-}
-DECLARE_SAFE_CONSOLE_COMMAND(wp, command_wp,
-			     "[<BOOLEAN>/follow_batt_pres [atboot]]",
-			     "Get/set the flash HW write-protect signal");
-
-void set_bp_follow_ccd_config(void)
-{
-	if (ccd_get_flag(CCD_FLAG_OVERRIDE_BATT_AT_BOOT)) {
-		/* Reset to at-boot state specified by CCD */
-		bp_forced = 1;
-		bp_connect = ccd_get_flag(CCD_FLAG_OVERRIDE_BATT_STATE_CONNECT);
-	} else {
-		bp_forced = 0;
-	}
-}
-
-static void set_wp_follow_ccd_config(void)
-{
-	if (ccd_get_flag(CCD_FLAG_OVERRIDE_WP_AT_BOOT)) {
-		/* Reset to at-boot state specified by CCD */
-		force_write_protect(1, ccd_get_flag
-				    (CCD_FLAG_OVERRIDE_WP_STATE_ENABLED));
-	} else {
-		/* Reset to WP based on battery-present (val is ignored) */
-		force_write_protect(0, 1);
-	}
-}
-
-void board_wp_follow_ccd_config(void)
-{
-	/*
-	 * Battery presence can be overidden using CCD. Get that setting before
-	 * configuring write protect.
-	 */
-	set_bp_follow_ccd_config();
-
-	/* Update write protect setting based on ccd config */
-	set_wp_follow_ccd_config();
-}
-
-void init_wp_state(void)
-{
-	/*
-	 * Battery presence can be overidden using CCD. Get that setting before
-	 * configuring write protect.
-	 */
-	set_bp_follow_ccd_config();
-
-	/* Check system reset flags after CCD config is initially loaded */
-	if ((system_get_reset_flags() & EC_RESET_FLAG_HIBERNATE) &&
-	    !system_rollback_detected()) {
-		/*
-		 * Deep sleep resume without rollback, so reload the WP state
-		 * that was saved to the long-life registers before the deep
-		 * sleep instead of going back to the at-boot default.
-		 */
-		if (board_forcing_wp()) {
-			/* Temporarily forcing WP */
-			set_wp_state(GREG32(PMU, LONG_LIFE_SCRATCH1) &
-				     BOARD_WP_ASSERTED);
-		} else {
-			/* Write protected if battery is present */
-			set_wp_state(board_battery_is_present());
-		}
-	} else {
-		set_wp_follow_ccd_config();
-	}
-}
-
-/**
- * Wipe the TPM
- *
- * @param reset_required: reset the system after wiping the TPM.
- *
- * @return EC_SUCCESS, or non-zero if error.
- */
-int board_wipe_tpm(int reset_required)
-{
-	int rc;
-
-	/* Wipe the TPM's memory and reset the TPM task. */
-	rc = tpm_reset_request(1, 1);
-	if (rc != EC_SUCCESS) {
-		flash_log_add_event(FE_LOG_TPM_WIPE_ERROR, 0, NULL);
-		/*
-		 * If anything goes wrong (which is unlikely), we REALLY don't
-		 * want to unlock the console. It's possible to fail without
-		 * the TPM task ever running, so rebooting is probably our best
-		 * bet for fixing the problem.
-		 */
-		CPRINTS("%s: Couldn't wipe nvmem! (rc %d)", __func__, rc);
-		cflush();
-		system_reset(SYSTEM_RESET_MANUALLY_TRIGGERED |
-			     SYSTEM_RESET_HARD);
-
-		/*
-		 * That should never return, but if it did, reset the EC and
-		 * through the error we got.
-		 */
-		board_reboot_ec();
-		return rc;
-	}
-
-	/*
-	 * TPM was wiped out successfully, let's prevent further communications
-	 * from the AP until next reboot. The reboot will be triggered below if
-	 * a reset is requested. If we aren't resetting the system now, the TPM
-	 * will stay disabled until the user resets the system.
-	 * This should be done as soon as possible after tpm_reset_request
-	 * completes.
-	 */
-	tpm_stop();
-
-	CPRINTS("TPM is erased");
-
-	/* Tell the TPM task to re-enable NvMem commits. */
-	tpm_reinstate_nvmem_commits();
-
-	/*
-	 * Use board_reboot_ec to ensure the system resets instead of
-	 * deassert_ec_reset. Some boards don't reset immediately when EC_RST_L
-	 * is asserted. board_reboot_ec will ensure the system has actually
-	 * reset before releasing it. If the system has a normal reset scheme,
-	 * EC reset will be released immediately.
-	 */
-	if (reset_required) {
-		CPRINTS("%s: reset EC", __func__);
-		board_reboot_ec();
-	}
-	return EC_SUCCESS;
-}
-
-/****************************************************************************/
-/* Verified boot TPM NVRAM space support */
-
-/*
- * These definitions and the structure layout were manually copied from
- * src/platform/vboot_reference/firmware/2lib/include/2secdata.h. at
- * git sha 38d7d1c.
- */
-#define FWMP_HASH_SIZE		    32
-#define FWMP_DEV_DISABLE_CCD_UNLOCK BIT(6)
-#define FWMP_DEV_FIPS_MODE	    BIT(7)
-#define FIRMWARE_FLAG_DEV_MODE      0x02
-
-struct RollbackSpaceFirmware {
-	/* Struct version, for backwards compatibility */
-	uint8_t struct_version;
-	/* Flags (see FIRMWARE_FLAG_* above) */
-	uint8_t flags;
-	/* Firmware versions */
-	uint32_t fw_versions;
-	/* Reserved for future expansion */
-	uint8_t reserved[3];
-	/* Checksum (v2 and later only) */
-	uint8_t crc8;
-} __packed;
-
-/* Firmware management parameters */
-struct RollbackSpaceFwmp {
-	/* CRC-8 of fields following struct_size */
-	uint8_t crc;
-	/* Structure size in bytes */
-	uint8_t struct_size;
-	/* Structure version */
-	uint8_t struct_version;
-	/* Reserved; ignored by current reader */
-	uint8_t reserved0;
-	/* Flags; see enum fwmp_flags */
-	uint32_t flags;
-	/* Hash of developer kernel key */
-	uint8_t dev_key_hash[FWMP_HASH_SIZE];
-} __packed;
-
-#ifndef CR50_DEV
-static int lock_enforced(const struct RollbackSpaceFwmp *fwmp)
-{
-	uint8_t crc;
-
-	/* Let's verify that the FWMP structure makes sense. */
-	if (fwmp->struct_size != sizeof(*fwmp)) {
-		CPRINTS("%s: fwmp size mismatch (%d)", __func__,
-			fwmp->struct_size);
-		return 1;
-	}
-
-	crc = crc8(&fwmp->struct_version, sizeof(struct RollbackSpaceFwmp) -
-		   offsetof(struct RollbackSpaceFwmp, struct_version));
-	if (fwmp->crc != crc) {
-		CPRINTS("%s: fwmp crc mismatch", __func__);
-		return 1;
-	}
-
-	return !!(fwmp->flags & FWMP_DEV_DISABLE_CCD_UNLOCK);
-}
-#endif
-
-int board_fwmp_allows_unlock(void)
-{
-#ifdef CR50_DEV
-	return 1;
-#else
-	/* Let's see if FWMP disables console activation. */
-	struct RollbackSpaceFwmp fwmp;
-	int allows_unlock;
-
-	switch (read_tpm_nvmem(FWMP_NV_INDEX,
-			       sizeof(struct RollbackSpaceFwmp), &fwmp)) {
-	default:
-		/* Something is messed up, let's not allow console unlock. */
-		allows_unlock = 0;
-		break;
-
-	case tpm_read_not_found:
-		allows_unlock = 1;
-		break;
-
-	case tpm_read_success:
-		allows_unlock = !lock_enforced(&fwmp);
-		break;
-	}
-
-	CPRINTS("Console unlock %sallowed", allows_unlock ? "" : "not ");
-
-	return allows_unlock;
-#endif
-}
-
-int board_fwmp_fips_mode_enabled(void)
-{
-	struct RollbackSpaceFirmware fw;
-
-	if (tpm_read_success ==
-	    read_tpm_nvmem(FIRMWARE_NV_INDEX, sizeof(fw), &fw)) {
-		return !!(fw.flags & FWMP_DEV_FIPS_MODE);
-	}
-
-	/* If not found or other error, assume fips mode is disabled */
-	return 0;
-}
-
-int board_vboot_dev_mode_enabled(void)
-{
-	struct RollbackSpaceFirmware fw;
-
-	if (tpm_read_success ==
-	    read_tpm_nvmem(FIRMWARE_NV_INDEX, sizeof(fw), &fw)) {
-		return !!(fw.flags & FIRMWARE_FLAG_DEV_MODE);
-	}
-
-	/* If not found or other error, assume dev mode is disabled */
-	return 0;
-}
-
-/****************************************************************************/
-/* TPM vendor-specific commands */
-
-static enum vendor_cmd_rc vc_lock(enum vendor_cmd_cc code,
-				  void *buf,
-				  size_t input_size,
-				  size_t *response_size)
-{
-	uint8_t *buffer = buf;
-
-	if (code == VENDOR_CC_GET_LOCK) {
-		/*
-		 * Get the state of the console lock.
-		 *
-		 *   Args: none
-		 *   Returns: one byte; true (locked) or false (unlocked)
-		 */
-		if (input_size != 0) {
-			*response_size = 0;
-			return VENDOR_RC_BOGUS_ARGS;
-		}
-
-		buffer[0] = console_is_restricted() ? 0x01 : 0x00;
-		*response_size = 1;
-		return VENDOR_RC_SUCCESS;
-	}
-
-	/* I have no idea what you're talking about */
-	*response_size = 0;
-	return VENDOR_RC_NO_SUCH_COMMAND;
-}
-DECLARE_VENDOR_COMMAND(VENDOR_CC_GET_LOCK, vc_lock);
-
-/*
- * TODO(rspangler): The old concept of 'lock the console' really meant
- * something closer to 'reset CCD config', not the CCD V1 meaning of 'ccdlock'.
- * This command is no longer supported, so will fail.  It was defined this
- * way:
- *
- * DECLARE_VENDOR_COMMAND(VENDOR_CC_SET_LOCK, vc_lock);
- */
diff --git a/board/cr50/wp.h b/board/cr50/wp.h
deleted file mode 100644
index d5cbade855..0000000000
--- a/board/cr50/wp.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __EC_BOARD_CR50_WP_H
-#define __EC_BOARD_CR50_WP_H
-
-#include "common.h"
-
-/**
- * Initialize write protect state.
- *
- * Must be called after case-closed debugging is initialized.
- */
-void init_wp_state(void);
-
-/**
- * Get the current write protect state.
- *
- * @return 0 if WP deasserted, 1 if WP asserted
- */
-int wp_is_asserted(void);
-
-/**
- * Read the FWMP value from TPM NVMEM and set the console restriction
- * appropriately.
- */
-void read_fwmp(void);
-
-/**
- * Set WP and battery presence as dicated by CCD configuration.
- */
-void board_wp_follow_ccd_config(void);
-
-#endif  /* ! __EC_BOARD_CR50_WP_H */
diff --git a/chip/g/OWNERS b/chip/g/OWNERS
deleted file mode 100644
index 0ae3592067..0000000000
--- a/chip/g/OWNERS
+++ /dev/null
@@ -1 +0,0 @@
-include ../../board/cr50/OWNERS
\ No newline at end of file
diff --git a/chip/g/alerts.c b/chip/g/alerts.c
deleted file mode 100644
index b53045ccaf..0000000000
--- a/chip/g/alerts.c
+++ /dev/null
@@ -1,364 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "board_id.h"
-#include "common.h"
-#include "console.h"
-#include "endian.h"
-#include "extension.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "signed_header.h"
-#include "task.h"
-#include "tpm_vendor_cmds.h"
-
-#define BROM_FWBIT_APPLYSEC_SC300       0
-#define BROM_FWBIT_APPLYSEC_CAMO        1
-#define BROM_FWBIT_APPLYSEC_BUSERR      2
-#define BROM_FWBIT_APPLYSEC_BUSOBF      3
-#define BROM_FWBIT_APPLYSEC_HEARTBEAT   4
-#define BROM_FWBIT_APPLYSEC_BATMON      5
-#define BROM_FWBIT_APPLYSEC_RTCCHECK    6
-#define BROM_FWBIT_APPLYSEC_JITTERY     7
-#define BROM_FWBIT_APPLYSEC_TRNG        8
-#define BROM_FWBIT_APPLYSEC_VOLT        9
-#define BROM_FWBIT_APPLYSEC_NOB5        10
-#define BROM_FWBIT_APPLYSEC_UNKNOWN     11
-
-struct alert_desc {
-	const char *name;
-	const uint8_t fuse; // BROM_FWBIT_APPLYSEC_* fuse that gates the alert
-};
-
-// These numbers correspond to index at 'alert_counters/alert_descs' arrays
-#define ALERT_NUM_CAMO0_BREACH 0
-#define ALERT_NUM_CRYPTO0_DMEM_PARITY 1
-#define ALERT_NUM_CRYPTO0_DRF_PARITY 2
-#define ALERT_NUM_CRYPTO0_IMEM_PARITY 3
-#define ALERT_NUM_CRYPTO0_PGM_FAULT 4
-#define ALERT_NUM_DBCTRL_CPU0_D_IF_BUS_ERR 5
-#define ALERT_NUM_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG 6
-#define ALERT_NUM_DBCTRL_CPU0_I_IF_BUS_ERR 7
-#define ALERT_NUM_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG 8
-#define ALERT_NUM_DBCTRL_CPU0_S_IF_BUS_ERR 9
-#define ALERT_NUM_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG 10
-#define ALERT_NUM_DBCTRL_DDMA0_IF_BUS_ERR 11
-#define ALERT_NUM_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG 12
-#define ALERT_NUM_DBCTRL_DSPS0_IF_BUS_ERR 13
-#define ALERT_NUM_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG 14
-#define ALERT_NUM_DBCTRL_DUSB0_IF_BUS_ERR 15
-#define ALERT_NUM_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG 16
-#define ALERT_NUM_FUSE0_FUSE_DEFAULTS 17
-#define ALERT_NUM_GLOBALSEC_DIFF_FAIL 18
-#define ALERT_NUM_GLOBALSEC_FW0 19
-#define ALERT_NUM_GLOBALSEC_FW1 20
-#define ALERT_NUM_GLOBALSEC_FW2 21
-#define ALERT_NUM_GLOBALSEC_FW3 22
-#define ALERT_NUM_GLOBALSEC_HEARTBEAT_FAIL 23
-#define ALERT_NUM_GLOBALSEC_PROC_OPCODE_HASH 24
-#define ALERT_NUM_GLOBALSEC_SRAM_PARITY_SCRUB 25
-#define ALERT_NUM_KEYMGR0_AES_EXEC_CTR_MAX 26
-#define ALERT_NUM_KEYMGR0_AES_HKEY 27
-#define ALERT_NUM_KEYMGR0_CERT_LOOKUP 28
-#define ALERT_NUM_KEYMGR0_FLASH_ENTRY 29
-#define ALERT_NUM_KEYMGR0_PW 30
-#define ALERT_NUM_KEYMGR0_SHA_EXEC_CTR_MAX 31
-#define ALERT_NUM_KEYMGR0_SHA_FAULT 32
-#define ALERT_NUM_KEYMGR0_SHA_HKEY 33
-#define ALERT_NUM_PMU_BATTERY_MON 34
-#define ALERT_NUM_PMU_PMU_WDOG 35
-#define ALERT_NUM_RTC0_RTC_DEAD 36
-#define ALERT_NUM_TEMP0_MAX_TEMP 37
-#define ALERT_NUM_TEMP0_MAX_TEMP_DIFF 38
-#define ALERT_NUM_TEMP0_MIN_TEMP 39
-#define ALERT_NUM_TRNG0_OUT_OF_SPEC 40
-#define ALERT_NUM_TRNG0_TIMEOUT 41
-#define ALERT_NUM_VOLT0_VOLT_ERR 42
-#define ALERT_NUM_XO0_JITTERY_TRIM_DIS 43
-
-#define ALERTS_NUM 44
-
-uint16_t alert_counters[ALERTS_NUM];
-
-static void alerts_init(void)
-{
-	int irq;
-
-	// enable every single IRQ for globalsec alerts
-	for (irq = GC_IRQNUM_GLOBALSEC_CAMO0_BREACH_ALERT_INT;
-		irq <= GC_IRQNUM_GLOBALSEC_XO0_JITTERY_TRIM_DIS_ALERT_INT;
-		irq++) {
-		task_enable_irq(irq);
-	}
-}
-DECLARE_HOOK(HOOK_INIT, alerts_init, HOOK_PRIO_DEFAULT);
-
-volatile uint32_t *INTR_STATUS_ADDR[] = {
-	GREG32_ADDR(GLOBALSEC, ALERT_INTR_STS0),
-	GREG32_ADDR(GLOBALSEC, ALERT_INTR_STS1),
-};
-BUILD_ASSERT(ARRAY_SIZE(INTR_STATUS_ADDR) * 32 >= ALERTS_NUM);
-
-static void alert_intr_clear(int alert)
-{
-	int reg = alert / 32;
-	int offset = alert % 32;
-
-	*INTR_STATUS_ADDR[reg] = 1 << offset;
-}
-
-static void alert_interrupt_process(int alert)
-{
-	alert_counters[alert]++;
-	alert_intr_clear(alert);
-}
-
-#define GLOBALSEC_ALERT_COUNTER(name) \
-	DECLARE_IRQ(GC_IRQNUM_GLOBALSEC_##name##_ALERT_INT, handler_##name, 1); \
-	void handler_##name(void) \
-	{ \
-		alert_interrupt_process(ALERT_NUM_##name); \
-	}
-
-GLOBALSEC_ALERT_COUNTER(CAMO0_BREACH);
-GLOBALSEC_ALERT_COUNTER(CRYPTO0_DMEM_PARITY);
-GLOBALSEC_ALERT_COUNTER(CRYPTO0_DRF_PARITY);
-GLOBALSEC_ALERT_COUNTER(CRYPTO0_IMEM_PARITY);
-GLOBALSEC_ALERT_COUNTER(CRYPTO0_PGM_FAULT);
-GLOBALSEC_ALERT_COUNTER(DBCTRL_CPU0_D_IF_BUS_ERR);
-GLOBALSEC_ALERT_COUNTER(DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG);
-GLOBALSEC_ALERT_COUNTER(DBCTRL_CPU0_I_IF_BUS_ERR);
-GLOBALSEC_ALERT_COUNTER(DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG);
-GLOBALSEC_ALERT_COUNTER(DBCTRL_CPU0_S_IF_BUS_ERR);
-GLOBALSEC_ALERT_COUNTER(DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG);
-GLOBALSEC_ALERT_COUNTER(DBCTRL_DDMA0_IF_BUS_ERR);
-GLOBALSEC_ALERT_COUNTER(DBCTRL_DDMA0_IF_UPDATE_WATCHDOG);
-GLOBALSEC_ALERT_COUNTER(DBCTRL_DSPS0_IF_BUS_ERR);
-GLOBALSEC_ALERT_COUNTER(DBCTRL_DSPS0_IF_UPDATE_WATCHDOG);
-GLOBALSEC_ALERT_COUNTER(DBCTRL_DUSB0_IF_BUS_ERR);
-GLOBALSEC_ALERT_COUNTER(DBCTRL_DUSB0_IF_UPDATE_WATCHDOG);
-GLOBALSEC_ALERT_COUNTER(FUSE0_FUSE_DEFAULTS);
-GLOBALSEC_ALERT_COUNTER(GLOBALSEC_DIFF_FAIL);
-GLOBALSEC_ALERT_COUNTER(GLOBALSEC_FW0);
-GLOBALSEC_ALERT_COUNTER(GLOBALSEC_FW1);
-GLOBALSEC_ALERT_COUNTER(GLOBALSEC_FW2);
-GLOBALSEC_ALERT_COUNTER(GLOBALSEC_FW3);
-GLOBALSEC_ALERT_COUNTER(GLOBALSEC_HEARTBEAT_FAIL);
-GLOBALSEC_ALERT_COUNTER(GLOBALSEC_PROC_OPCODE_HASH);
-GLOBALSEC_ALERT_COUNTER(GLOBALSEC_SRAM_PARITY_SCRUB);
-GLOBALSEC_ALERT_COUNTER(KEYMGR0_AES_EXEC_CTR_MAX);
-GLOBALSEC_ALERT_COUNTER(KEYMGR0_AES_HKEY);
-GLOBALSEC_ALERT_COUNTER(KEYMGR0_CERT_LOOKUP);
-GLOBALSEC_ALERT_COUNTER(KEYMGR0_FLASH_ENTRY);
-GLOBALSEC_ALERT_COUNTER(KEYMGR0_PW);
-GLOBALSEC_ALERT_COUNTER(KEYMGR0_SHA_EXEC_CTR_MAX);
-GLOBALSEC_ALERT_COUNTER(KEYMGR0_SHA_FAULT);
-GLOBALSEC_ALERT_COUNTER(KEYMGR0_SHA_HKEY);
-GLOBALSEC_ALERT_COUNTER(PMU_BATTERY_MON);
-GLOBALSEC_ALERT_COUNTER(PMU_PMU_WDOG);
-GLOBALSEC_ALERT_COUNTER(RTC0_RTC_DEAD);
-GLOBALSEC_ALERT_COUNTER(TEMP0_MAX_TEMP);
-GLOBALSEC_ALERT_COUNTER(TEMP0_MAX_TEMP_DIFF);
-GLOBALSEC_ALERT_COUNTER(TEMP0_MIN_TEMP);
-GLOBALSEC_ALERT_COUNTER(TRNG0_OUT_OF_SPEC);
-GLOBALSEC_ALERT_COUNTER(TRNG0_TIMEOUT);
-GLOBALSEC_ALERT_COUNTER(VOLT0_VOLT_ERR);
-GLOBALSEC_ALERT_COUNTER(XO0_JITTERY_TRIM_DIS);
-
-#define ALERTS_FORMAT_HAVEN 1
-
-struct vc_alerts_data {
-	uint16_t version_id;
-	uint16_t alerts_num;
-	uint16_t counters[ALERTS_NUM];
-} __packed;
-
-static enum vendor_cmd_rc vc_get_alerts_data(enum vendor_cmd_cc code,
-	void *buf, size_t input_size, size_t *response_size)
-{
-	int i;
-	struct vc_alerts_data *resp = buf;
-
-	if (sizeof(struct vc_alerts_data) > *response_size)
-		return VENDOR_RC_RESPONSE_TOO_BIG;
-
-	memset(resp, 0, sizeof(struct vc_alerts_data));
-	resp->version_id = htobe16(ALERTS_FORMAT_HAVEN);
-	resp->alerts_num = htobe16(ALERTS_NUM);
-	for (i = 0; i < ALERTS_NUM; i++) {
-		// Most of alert_counters[i] will be zero. We want to avoid
-		// disabling IRQ thus check counters with IRQ enabled.
-		if (alert_counters[i]) {
-			interrupt_disable();
-			resp->counters[i] = htobe16(alert_counters[i]);
-			alert_counters[i] = 0;
-			interrupt_enable();
-		}
-	}
-
-	*response_size = sizeof(struct vc_alerts_data);
-
-	return VENDOR_RC_SUCCESS;
-}
-DECLARE_VENDOR_COMMAND(VENDOR_CC_GET_ALERTS_DATA, vc_get_alerts_data);
-
-#ifdef CONFIG_ENABLE_H1_ALERTS_CONSOLE
-
-const struct alert_desc alert_descs[] = {
-	{ "camo0/breach", BROM_FWBIT_APPLYSEC_CAMO },
-	{ "crypto0/dmem_parity", BROM_FWBIT_APPLYSEC_UNKNOWN },
-	{ "crypto0/drf_parity", BROM_FWBIT_APPLYSEC_UNKNOWN },
-	{ "crypto0/imem_parity", BROM_FWBIT_APPLYSEC_UNKNOWN },
-	{ "crypto0/pgm_fault", BROM_FWBIT_APPLYSEC_UNKNOWN },
-	{ "dbctrl_cpu0_D_if/bus_err", BROM_FWBIT_APPLYSEC_BUSERR },
-	{ "dbctrl_cpu0_D_if/update_watchdog", BROM_FWBIT_APPLYSEC_BUSOBF },
-	{ "dbctrl_cpu0_I_if/bus_err", BROM_FWBIT_APPLYSEC_BUSERR },
-	{ "dbctrl_cpu0_I_if/update_watchdog", BROM_FWBIT_APPLYSEC_BUSOBF },
-	{ "dbctrl_cpu0_S_if/bus_err", BROM_FWBIT_APPLYSEC_BUSERR },
-	{ "dbctrl_cpu0_S_if/update_watchdog", BROM_FWBIT_APPLYSEC_BUSOBF },
-	{ "dbctrl_ddma0_if/bus_err", BROM_FWBIT_APPLYSEC_BUSERR },
-	{ "dbctrl_ddma0_if/update_watchdog", BROM_FWBIT_APPLYSEC_BUSOBF },
-	{ "dbctrl_dsps0_if/bus_err", BROM_FWBIT_APPLYSEC_BUSERR },
-	{ "dbctrl_dsps0_if/update_watchdog", BROM_FWBIT_APPLYSEC_BUSOBF },
-	{ "dbctrl_dusb0_if/bus_err", BROM_FWBIT_APPLYSEC_BUSERR },
-	{ "dbctrl_dusb0_if/update_watchdog", BROM_FWBIT_APPLYSEC_BUSOBF },
-	{ "fuse0/fuse_defaults", BROM_FWBIT_APPLYSEC_UNKNOWN },
-	{ "globalsec/diff_fail", BROM_FWBIT_APPLYSEC_HEARTBEAT },
-	{ "globalsec/fw0", BROM_FWBIT_APPLYSEC_UNKNOWN },
-	{ "globalsec/fw1", BROM_FWBIT_APPLYSEC_UNKNOWN },
-	{ "globalsec/fw2", BROM_FWBIT_APPLYSEC_UNKNOWN },
-	{ "globalsec/fw3", BROM_FWBIT_APPLYSEC_UNKNOWN },
-	{ "globalsec/heartbeat_fail", BROM_FWBIT_APPLYSEC_HEARTBEAT },
-	{ "globalsec/proc_opcode_hash", BROM_FWBIT_APPLYSEC_UNKNOWN },
-	{ "globalsec/sram_parity_scrub", BROM_FWBIT_APPLYSEC_UNKNOWN },
-	{ "keymgr0/aes_exec_ctr_max", BROM_FWBIT_APPLYSEC_UNKNOWN },
-	{ "keymgr0/aes_hkey", BROM_FWBIT_APPLYSEC_UNKNOWN },
-	{ "keymgr0/cert_lookup", BROM_FWBIT_APPLYSEC_UNKNOWN },
-	{ "keymgr0/flash_entry", BROM_FWBIT_APPLYSEC_UNKNOWN },
-	{ "keymgr0/pw", BROM_FWBIT_APPLYSEC_UNKNOWN },
-	{ "keymgr0/sha_exec_ctr_max", BROM_FWBIT_APPLYSEC_UNKNOWN },
-	{ "keymgr0/sha_fault", BROM_FWBIT_APPLYSEC_UNKNOWN },
-	{ "keymgr0/sha_hkey", BROM_FWBIT_APPLYSEC_UNKNOWN },
-	{ "pmu/battery_mon", BROM_FWBIT_APPLYSEC_BATMON },
-	{ "pmu/pmu_wdog", BROM_FWBIT_APPLYSEC_HEARTBEAT },
-	{ "rtc0/rtc_dead", BROM_FWBIT_APPLYSEC_RTCCHECK },
-	{ "temp0/max_temp", BROM_FWBIT_APPLYSEC_UNKNOWN },
-	{ "temp0/max_temp_diff", BROM_FWBIT_APPLYSEC_UNKNOWN },
-	{ "temp0/min_temp", BROM_FWBIT_APPLYSEC_UNKNOWN },
-	{ "trng0/out_of_spec", BROM_FWBIT_APPLYSEC_TRNG },
-	{ "trng0/timeout", BROM_FWBIT_APPLYSEC_TRNG },
-	{ "volt0/volt_err", BROM_FWBIT_APPLYSEC_VOLT },
-	{ "xo0/jittery_trim_dis", BROM_FWBIT_APPLYSEC_JITTERY },
-};
-BUILD_ASSERT(ARRAY_SIZE(alert_descs) == ALERTS_NUM);
-
-static int alert_intr_status(int alert)
-{
-	int reg = alert / 32;
-	int offset = alert % 32;
-
-	return !!(*INTR_STATUS_ADDR[reg] & BIT(offset));
-}
-
-#ifdef CONFIG_BOARD_ID_SUPPORT
-static uint32_t fuse_enabled(void)
-{
-	uint32_t fuses = GR_FUSE(FW_DEFINED_BROM_APPLYSEC);
-	// get_current_image_header() is defined in board_id.c and available
-	// only when CONFIG_BOARD_ID_SUPPORT is enabled
-	const struct SignedHeader *hdr = get_current_image_header();
-
-	return fuses & hdr->applysec_;
-}
-#else /* CONFIG_BOARD_ID_SUPPORT */
-static uint32_t fuse_enabled(void)
-{
-	return GR_FUSE(FW_DEFINED_BROM_APPLYSEC);
-}
-#endif /* CONFIG_BOARD_ID_SUPPORT */
-
-static void command_alerts_list(void)
-{
-	int i;
-	uint32_t fuses = fuse_enabled();
-
-	ccprintf("Globalsec alerts status\nColumns:\n"
-		" * name\n"
-		" * fuse state: '?' - not defined, '#' disabled, '+' enabled\n"
-		" * interrupt state\n"
-		" * alert counter\n");
-
-	for (i = 0; i < ALERTS_NUM; i++) {
-		const char *name = alert_descs[i].name;
-		char fuse_status;
-
-		int status = alert_intr_status(i);
-		int8_t fuse = alert_descs[i].fuse;
-
-		if (fuse == BROM_FWBIT_APPLYSEC_UNKNOWN)
-			fuse_status = '?';
-		else if (fuses & BIT(fuse))
-			fuse_status = '+';
-		else
-			fuse_status = '#';
-
-		ccprintf("%32s %c %d %d\n", name, fuse_status, status,
-			alert_counters[i]);
-		cflush();
-	}
-}
-
-/* Fire a software enabled alert */
-static void command_alerts_fire(int interrupt)
-{
-	int i = 0;
-	int value = 0;
-
-	for (i = 3; i >= 0; i--) {
-		/* Trigger register consists of four 2-bit fields.
-		 * pair 01 triggers the alerts, pair 10 does not trigger
-		 */
-		value <<= 2;
-		value |= (i == interrupt) ? 1 : 2;
-	}
-	GWRITE(GLOBALSEC, ALERT_FW_TRIGGER, value); // firing FW-N irq
-	GWRITE(GLOBALSEC, ALERT_FW_TRIGGER, 0xaa); // back to normal
-}
-
-static int command_alerts(int argc, char **argv)
-{
-	char *e;
-
-	if (argc == 1) {
-		command_alerts_list();
-		return EC_SUCCESS;
-	}
-
-	if (argc == 3) {
-		if (!strcasecmp(argv[1], "fire")) {
-			int alert = strtoi(argv[2], &e, 10);
-
-			if (*e || alert < 0 || alert > 3) {
-				ccprintf("interrupt number must be in range "
-					"[0..3]\n");
-				return EC_ERROR_PARAM2;
-			}
-
-			command_alerts_fire(alert);
-			return EC_SUCCESS;
-		}
-
-		return EC_ERROR_PARAM1;
-	}
-
-	return EC_ERROR_PARAM_COUNT;
-}
-
-DECLARE_CONSOLE_COMMAND(alerts, command_alerts,
-	"<|fire [INT]>",
-	"View/change alerts status");
-
-#endif /* CONFIG_ENABLE_H1_ALERTS_CONSOLE */
diff --git a/chip/g/blob.c b/chip/g/blob.c
deleted file mode 100644
index f288b2aacf..0000000000
--- a/chip/g/blob.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Handle an opaque blob of data */
-
-#include "common.h"
-#include "console.h"
-#include "consumer.h"
-#include "queue.h"
-#include "queue_policies.h"
-#include "producer.h"
-#include "task.h"
-#include "usb-stream.h"
-
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
-
-struct consumer const blob_consumer;
-struct usb_stream_config const usb_blob;
-
-static struct queue const blob_to_usb = QUEUE_DIRECT(64, uint8_t,
-						     null_producer,
-						     usb_blob.consumer);
-static struct queue const usb_to_blob = QUEUE_DIRECT(64, uint8_t,
-						     usb_blob.producer,
-						     blob_consumer);
-
-USB_STREAM_CONFIG(usb_blob,
-		  USB_IFACE_BLOB,
-		  USB_STR_BLOB_NAME,
-		  USB_EP_BLOB,
-		  USB_MAX_PACKET_SIZE,
-		  USB_MAX_PACKET_SIZE,
-		  usb_to_blob,
-		  blob_to_usb)
-
-static void blob_written(struct consumer const *consumer, size_t count)
-{
-	int i;
-	uint8_t buf[USB_MAX_PACKET_SIZE];
-
-	count = QUEUE_REMOVE_UNITS(consumer->queue, buf, count);
-
-	CPRINTS("Received: count=%d buf=((%s))", count, buf);
-
-	/*
-	 * Just to have something to test to begin with, we'll
-	 * implement "tr a-zA-Z A-Za-z" and return the result.
-	 */
-	for (i = 0; i < count; i++) {
-		char tmp = buf[i];
-
-		if (tmp >= 'a' && tmp <= 'z')
-			buf[i] = tmp - ('a' - 'A');
-		else if (tmp >= 'A' && tmp <= 'Z')
-			buf[i] = tmp + ('a' - 'A');
-	}
-
-	count = QUEUE_ADD_UNITS(&blob_to_usb, buf, count);
-	CPRINTS("Sending: count=%d buf=((%s))", count, buf);
-}
-
-struct consumer const blob_consumer = {
-	.queue = &usb_to_blob,
-	.ops   = &((struct consumer_ops const) {
-		.written = blob_written,
-	}),
-};
diff --git a/chip/g/board_id.c b/chip/g/board_id.c
deleted file mode 100644
index 6a7309e739..0000000000
--- a/chip/g/board_id.c
+++ /dev/null
@@ -1,280 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "board_id.h"
-#include "endian.h"
-#include "extension.h"
-#include "flash_info.h"
-#include "system.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-
-#define BLANK_FIELD 0xffffffff
-
-/**
- * Return the image header for the current image copy
- */
-const struct SignedHeader *get_current_image_header(void)
-{
-	return (const struct SignedHeader *)
-			get_program_memory_addr(system_get_image_copy());
-}
-
-int board_id_type_is_blank(const struct board_id *id)
-{
-	return (id->type & id->type_inv) == BLANK_FIELD;
-}
-
-static int board_id_flags_are_blank(const struct board_id *id)
-{
-	return id->flags == BLANK_FIELD;
-}
-
-int board_id_is_blank(const struct board_id *id)
-{
-	return board_id_type_is_blank(id) && board_id_flags_are_blank(id);
-}
-
-uint32_t check_board_id_vs_header(const struct board_id *id,
-				  const struct SignedHeader *h)
-{
-	uint32_t mismatch;
-	uint32_t header_board_id_type;
-	uint32_t header_board_id_mask;
-	uint32_t header_board_id_flags;
-
-	/* Blank Board ID matches all headers */
-	if (board_id_is_blank(id))
-		return 0;
-
-	header_board_id_type = SIGNED_HEADER_PADDING ^ h->board_id_type;
-	header_board_id_mask = SIGNED_HEADER_PADDING ^ h->board_id_type_mask;
-	header_board_id_flags = SIGNED_HEADER_PADDING ^ h->board_id_flags;
-
-	/*
-	 * All 1-bits in header Board ID flags must be present in flags from
-	 * flash
-	 */
-	mismatch =
-		((header_board_id_flags & id->flags) != header_board_id_flags);
-	/*
-	 * Masked bits in header Board ID type must match type and inverse from
-	 * flash.
-	 */
-	if (!mismatch && !board_id_type_is_blank(id)) {
-		mismatch = header_board_id_type ^ id->type;
-		mismatch |= header_board_id_type ^ ~id->type_inv;
-		mismatch &= header_board_id_mask;
-	}
-	return mismatch;
-}
-
-int read_board_id(struct board_id *id)
-{
-	uint32_t *id_p;
-	int i;
-
-	/*
-	 * Board ID structure size is guaranteed to be divisible by 4, and it
-	 * is guaranteed to be aligned at 4 bytes.
-	 */
-
-	id_p = (uint32_t *)id;
-
-	for (i = 0; i < sizeof(*id); i += sizeof(uint32_t)) {
-		int rv;
-
-		rv = flash_physical_info_read_word
-			(INFO_BOARD_ID_OFFSET + i, id_p);
-		if (rv != EC_SUCCESS) {
-			CPRINTF("%s: failed to read word %d, error %d\n",
-				__func__, i, rv);
-			return rv;
-		}
-		id_p++;
-	}
-	return EC_SUCCESS;
-}
-
-uint32_t board_id_mismatch(const struct SignedHeader *sh)
-{
-	struct board_id id;
-
-	if (!sh)
-		/* Get header of the currently running image. */
-		sh = get_current_image_header();
-
-	/* Get Board ID from INFO1. */
-	if (read_board_id(&id) != EC_SUCCESS) {
-		/*
-		 * On failure, set id fields to 0.  This will only match an
-		 * unrestricted image header (board_id_mask=board_id_flags=0),
-		 * which would run on any Board ID.
-		 *
-		 * Don't return error, because that would prevent all images
-		 * from running.
-		 */
-		id.type = id.type_inv = id.flags = 0;
-	}
-
-	return check_board_id_vs_header(&id, sh);
-}
-
-/**
- * Write board ID into the flash INFO1 space.
- *
- * @param id	Pointer to a Board ID structure to copy into INFO1
- *
- * @return EC_SUCCESS or an error code in cases of various failures to read or
- *              if the space has been already initialized.
- */
-static int write_board_id(struct board_id *id)
-{
-	struct board_id id_test;
-	uint32_t rv;
-
-	/* Fail if Board ID is already programmed */
-	rv = read_board_id(&id_test);
-	if (rv != EC_SUCCESS) {
-		CPRINTS("%s: error reading Board ID", __func__);
-		return rv;
-	}
-
-	if (!board_id_is_blank(&id_test)) {
-		if (!board_id_type_is_blank(&id_test)) {
-			CPRINTS("%s: Board ID already programmed", __func__);
-			return EC_ERROR_ACCESS_DENIED;
-		}
-		CPRINTS("%s: using old flags.", __func__);
-		id->flags = id_test.flags;
-	}
-
-	/*
-	 * Make sure the current header will still validate against the
-	 * proposed values.  If it doesn't, then programming these values
-	 * would cause the next boot to fail.
-	 */
-	if (check_board_id_vs_header(id, get_current_image_header()) != 0) {
-		CPRINTS("%s: Board ID wouldn't allow current header", __func__);
-		return EC_ERROR_INVAL;
-	}
-
-	flash_info_write_enable();
-
-	/* Write Board ID */
-	rv = flash_info_physical_write(INFO_BOARD_ID_OFFSET +
-			 offsetof(struct info1_board_space, bid),
-				       sizeof(*id), (const char *)id);
-	if (rv != EC_SUCCESS)
-		CPRINTS("%s: write failed", __func__);
-
-	flash_info_write_disable();
-
-	return rv;
-}
-
-static enum vendor_cmd_rc vc_set_board_id(enum vendor_cmd_cc code,
-					  void *buf,
-					  size_t input_size,
-					  size_t *response_size)
-{
-	struct board_id id;
-	uint8_t *pbuf = buf;
-
-	*response_size = 1;
-
-	/* Exactly two fields are expected. */
-	if (input_size != sizeof(id.type) + sizeof(id.flags)) {
-		*pbuf = VENDOR_RC_BOGUS_ARGS;
-		return VENDOR_RC_BOGUS_ARGS;
-	}
-
-	memcpy(&id.type, pbuf, sizeof(id.type));
-	id.type = be32toh(id.type);
-	if (id.type == BLANK_FIELD)
-		id.type_inv = BLANK_FIELD;
-	else
-		id.type_inv = ~id.type;
-
-	memcpy(&id.flags, pbuf + sizeof(id.type), sizeof(id.flags));
-	id.flags = be32toh(id.flags);
-
-	/* We care about the LSB only. */
-	*pbuf = write_board_id(&id);
-
-	return *pbuf;
-}
-DECLARE_VENDOR_COMMAND(VENDOR_CC_SET_BOARD_ID, vc_set_board_id);
-
-static int command_board_id(int argc, char **argv)
-{
-	struct board_id id;
-	int rv = EC_ERROR_PARAM_COUNT;
-
-	if (argc == 1) {
-		rv = read_board_id(&id);
-
-		if (rv != EC_SUCCESS) {
-			ccprintf("Failed to read board ID space\n");
-			return rv;
-		}
-		ccprintf("Board ID: %08x:%08x, flags %08x\n", id.type,
-			 id.type_inv, id.flags);
-
-		if (board_id_is_blank(&id))
-			return rv; /* The space is not initialized. */
-
-		if (!board_id_type_is_blank(&id) && id.type != ~id.type_inv)
-			ccprintf("Inv Type Mismatch (%08x instead of %08x)!\n",
-				 id.type_inv, ~id.type);
-	}
-#ifdef CR50_DEV
-	else if (argc == 3) {
-		char *e;
-
-		id.type = strtoi(argv[1], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM1;
-		id.type_inv = ~id.type;
-		id.flags = strtoi(argv[2], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM2;
-		rv = write_board_id(&id);
-	}
-#endif
-	return rv;
-}
-DECLARE_SAFE_CONSOLE_COMMAND(bid, command_board_id,
-#ifdef CR50_DEV
-			     "[bid flags]",
-#else
-			     NULL,
-#endif
-			     "Set/Get Board ID");
-
-static enum vendor_cmd_rc vc_get_board_id(enum vendor_cmd_cc code,
-					  void *buf,
-					  size_t input_size,
-					  size_t *response_size)
-{
-	struct board_id id;
-
-	if (read_board_id(&id))
-		return VENDOR_RC_READ_FLASH_FAIL;
-
-	/* Convert to line representation. */
-	id.type = htobe32(id.type);
-	id.type_inv = htobe32(id.type_inv);
-	id.flags = htobe32(id.flags);
-
-	memcpy(buf, &id, sizeof(id));
-	*response_size = sizeof(id);
-
-	return VENDOR_RC_SUCCESS;
-}
-DECLARE_VENDOR_COMMAND(VENDOR_CC_GET_BOARD_ID, vc_get_board_id);
diff --git a/chip/g/board_id.h b/chip/g/board_id.h
deleted file mode 100644
index 01cb7e5028..0000000000
--- a/chip/g/board_id.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __EC_CHIP_G_BOARD_ID_H
-#define __EC_CHIP_G_BOARD_ID_H
-
-#include "board_space.h"
-#include "common.h"
-#include "signed_header.h"
-#include "util.h"
-
-/**
- * Check the current header vs. the supplied Board ID
- *
- * @param board_id	Pointer to a Board ID structure to check
- * @param h		Pointer to the currently running image's header
- *
- * @return 0 if no mismatch, non-zero if mismatch
- */
-uint32_t check_board_id_vs_header(const struct board_id *id,
-				  const struct SignedHeader *h);
-
-/**
- * Check board ID from the flash INFO1 space.
- *
- * @param id	Pointer to a Board ID structure to fill
- *
- * @return EC_SUCCESS of an error code in cases of vairous failures to read.
- */
-int read_board_id(struct board_id *id);
-
-/**
- * Return the image header for the current image copy
- */
-const struct SignedHeader *get_current_image_header(void);
-
-/**
- * Check if board ID in the image matches board ID field in the INFO1.
- *
- * Pass the pointer to the image header to check. If the pointer is set to
- * NULL, check board ID against the currently running image's header. All 1
- * bits in header Board ID flags must be present in the board id from flash.
- *
- * If the board id from flash is blank, board_id_type field from the header is
- * ignored and only board_if_flags field is verified to match.
- *
- * Return true if there is a mismatch (the code should not run).
- */
-uint32_t board_id_mismatch(const struct SignedHeader *h);
-
-/**
- * Check if every field of the board id is 0xffffffff
- *
- * @param id	Pointer to a Board ID structure
- *
- * @return True if the board id is all 0xffffffff.
- */
-int board_id_is_blank(const struct board_id *id);
-
-/**
- * Check if the board id type and type_inv are 0xffffffff.
- *
- * @param id	Pointer to a Board ID structure
- *
- * @return True if the board id type and type_inv are 0xffffffff.
- */
-int board_id_type_is_blank(const struct board_id *id);
-#endif  /* ! __EC_CHIP_G_BOARD_ID_H */
diff --git a/chip/g/board_space.h b/chip/g/board_space.h
deleted file mode 100644
index 68e67e78ec..0000000000
--- a/chip/g/board_space.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __EC_CHIP_G_BOARD_SPACE_H
-#define __EC_CHIP_G_BOARD_SPACE_H
-
-#include "compile_time_macros.h"
-#include "flash_config.h"
-#include "flash_info.h"
-#include "stdint.h"
-
-/*
- * Structures for data stored in the board space of INFO1.
- */
-
-/* Structure holding Board ID */
-struct board_id {
-	uint32_t type;		/* Board type */
-	uint32_t type_inv;	/* Board type (inverted) */
-	uint32_t flags;		/* Flags */
-};
-
-/* Structure holding serial number data */
-struct sn_data {
-	uint8_t version;
-	uint8_t reserved[2];
-	uint8_t rma_status;
-	uint32_t sn_hash[3];
-};
-
-/* Current sn_data format version */
-#define SN_DATA_VERSION	0x0f
-/* Size of header elements (everything apart from sn_hash) */
-#define SN_HEADER_SIZE	offsetof(struct sn_data, sn_hash)
-/* Number of bits reserved for RMA counter */
-#define RMA_COUNT_BITS	7
-/* Value used to indicate device has been RMA'd */
-#define RMA_INDICATOR	((uint8_t) ~BIT(RMA_COUNT_BITS))
-
-/* Info1 Board space contents. */
-struct info1_board_space {
-	struct board_id bid;
-	/* Pad so that board_id occupies it's full 'protect' size */
-	uint8_t bid_padding[4];
-	struct sn_data sn;
-};
-
-/*
- * Layout of the entire 2K INFO1 space.
- *
- * - ro_info_map - maps controlling ro and rw images rollback protection.
- * - rw_info_map
- * - board_space - various objects used by Chrome OS applications
- * - manufacture_space - seed used for generating and verification of
- *                        endorsement certs.
- */
-struct info1_layout {
-	uint8_t ro_info_map[INFO_RO_MAP_SIZE];
-	uint8_t rw_info_map[INFO_RW_MAP_SIZE];
-	struct info1_board_space board_space;
-	uint8_t padding[FLASH_INFO_MANUFACTURE_STATE_OFFSET - INFO_RO_MAP_SIZE -
-			INFO_RW_MAP_SIZE - sizeof(struct info1_board_space)];
-	uint8_t manufacture_space[FLASH_INFO_MANUFACTURE_STATE_SIZE];
-};
-BUILD_ASSERT(sizeof(struct info1_layout) == FLASH_INFO_SIZE);
-
-#define INFO_BOARD_ID_SIZE		sizeof(struct board_id)
-#define INFO_BOARD_ID_OFFSET		(INFO_BOARD_SPACE_OFFSET + \
-					 offsetof(struct info1_board_space, \
-						  bid))
-
-#define INFO_SN_DATA_SIZE		 sizeof(struct sn_data)
-#define INFO_SN_DATA_OFFSET		 (INFO_BOARD_SPACE_OFFSET + \
-					  offsetof(struct info1_board_space, \
-						   sn))
-
-/*
- * Write protection for the INFO1 space allows windows with sizes that are
- * powers of 2 to be protected. Given the different write restrictions on
- * the different spaces listed above, we keep them in separate windows.
- * This implies that each space must occupy a space that has a size which
- * is a power of two.
- */
-#define INFO_BOARD_ID_PROTECT_SIZE	16
-#define INFO_SN_DATA_PROTECT_SIZE	16
-
-BUILD_ASSERT((INFO_BOARD_ID_SIZE & 3) == 0);
-BUILD_ASSERT((INFO_BOARD_ID_OFFSET & 3) == 0);
-BUILD_ASSERT(INFO_BOARD_ID_SIZE <= INFO_BOARD_ID_PROTECT_SIZE);
-
-BUILD_ASSERT((INFO_SN_DATA_SIZE & 3) == 0);
-BUILD_ASSERT((INFO_SN_DATA_OFFSET & 3) == 0);
-BUILD_ASSERT(INFO_SN_DATA_SIZE <= INFO_SN_DATA_PROTECT_SIZE);
-
-#endif  /* ! __EC_CHIP_G_BOARD_SPACE_H */
diff --git a/chip/g/build.mk b/chip/g/build.mk
deleted file mode 100644
index a46a6e8c55..0000000000
--- a/chip/g/build.mk
+++ /dev/null
@@ -1,231 +0,0 @@
-# -*- makefile -*-
-# Copyright 2014 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-#
-
-CORE:=cortex-m
-CFLAGS_CPU+=-march=armv7-m -mcpu=cortex-m3
-
-ifeq ($(CONFIG_DCRYPTO),y)
-INCLUDE_ROOT := $(abspath ./include)
-CPPFLAGS += -I$(abspath .)
-CPPFLAGS += -I$(abspath ./builtin)
-CPPFLAGS += -I$(abspath ./chip/$(CHIP))
-CPPFLAGS += -I$(INCLUDE_ROOT)
-endif
-
-# Required chip modules
-chip-y = clock.o gpio.o hwtimer.o pre_init.o system.o
-chip-$(CONFIG_BOARD_ID_SUPPORT) += board_id.o
-chip-$(CONFIG_SN_BITS_SUPPORT) += sn_bits.o
-ifeq ($(CONFIG_POLLING_UART),y)
-chip-y += polling_uart.o
-else
-chip-y += uart.o
-chip-y += uartn.o
-chip-$(CONFIG_UART_BITBANG)+= uart_bitbang.o
-endif # undef CONFIG_POLLING_UART
-
-chip-$(CONFIG_DCRYPTO)+= crypto_api.o
-
-chip-$(CONFIG_DCRYPTO)+= dcrypto/aes.o
-chip-$(CONFIG_DCRYPTO)+= dcrypto/aes_cmac.o
-chip-$(CONFIG_DCRYPTO)+= dcrypto/app_cipher.o
-chip-$(CONFIG_DCRYPTO)+= dcrypto/app_key.o
-chip-$(CONFIG_DCRYPTO)+= dcrypto/bn.o
-chip-$(CONFIG_DCRYPTO)+= dcrypto/dcrypto_bn.o
-chip-$(CONFIG_DCRYPTO)+= dcrypto/dcrypto_p256.o
-chip-$(CONFIG_DCRYPTO)+= dcrypto/compare.o
-chip-$(CONFIG_DCRYPTO)+= dcrypto/dcrypto_runtime.o
-chip-$(CONFIG_DCRYPTO)+= dcrypto/gcm.o
-chip-$(CONFIG_DCRYPTO)+= dcrypto/hkdf.o
-chip-$(CONFIG_DCRYPTO)+= dcrypto/hmac.o
-chip-$(CONFIG_DCRYPTO)+= dcrypto/hmac_drbg.o
-chip-$(CONFIG_DCRYPTO)+= dcrypto/key_ladder.o
-chip-$(CONFIG_DCRYPTO)+= dcrypto/p256.o
-chip-$(CONFIG_DCRYPTO)+= dcrypto/p256_ec.o
-chip-$(CONFIG_DCRYPTO)+= dcrypto/p256_ecies.o
-chip-$(CONFIG_DCRYPTO)+= dcrypto/rsa.o
-chip-$(CONFIG_DCRYPTO)+= dcrypto/sha1.o
-chip-$(CONFIG_DCRYPTO)+= dcrypto/sha256.o
-ifeq ($(CONFIG_UPTO_SHA512),y)
-chip-$(CONFIG_DCRYPTO)+= dcrypto/sha384.o
-ifeq ($(CONFIG_DCRYPTO_SHA512),y)
-chip-$(CONFIG_DCRYPTO)+= dcrypto/dcrypto_sha512.o
-else
-chip-$(CONFIG_DCRYPTO)+= dcrypto/sha512.o
-endif
-endif
-chip-$(CONFIG_DCRYPTO)+= dcrypto/x509.o
-
-chip-$(CONFIG_SPI_MASTER)+=spi_master.o
-
-chip-y+= jitter.o
-chip-y+= pmu.o
-chip-y+= trng.o
-chip-y+= runlevel.o
-chip-$(CONFIG_CCD_ITE_PROGRAMMING)+= ite_flash.o
-chip-$(CONFIG_CCD_ITE_PROGRAMMING)+= ite_sync.o
-chip-$(CONFIG_ENABLE_H1_ALERTS)+= alerts.o
-chip-$(CONFIG_USB_FW_UPDATE)+= usb_upgrade.o
-chip-$(CONFIG_NON_HC_FW_UPDATE)+= upgrade_fw.o post_reset.o upgrade.o
-chip-$(CONFIG_SPS)+= sps.o
-chip-$(CONFIG_TPM_SPS)+=sps_tpm.o
-chip-$(CONFIG_WATCHDOG)+=watchdog.o
-
-chip-$(CONFIG_USB)+=usb.o usb_endpoints.o
-chip-$(CONFIG_USB_CONSOLE)+=usb_console.o
-chip-$(CONFIG_USB_HID_KEYBOARD)+=usb_hid_keyboard.o
-chip-$(CONFIG_USB_BLOB)+=blob.o
-chip-$(CONFIG_USB_SPI)+=usb_spi.o
-chip-$(CONFIG_RDD)+=rdd.o
-chip-$(CONFIG_RBOX)+=rbox.o
-chip-$(CONFIG_STREAM_USB)+=usb-stream.o
-chip-$(CONFIG_STREAM_USART)+=usart.o
-chip-$(CONFIG_I2C_MASTER)+= i2cm.o
-chip-$(CONFIG_I2C_SLAVE)+= i2cs.o
-
-chip-$(CONFIG_LOW_POWER_IDLE)+=idle.o
-
-chip-$(CONFIG_FLASH_PHYSICAL) += flash.o
-dirs-y += chip/g/dcrypto
-
-ifneq ($(CONFIG_CUSTOMIZED_RO),)
-custom-ro_objs-y  = chip/g/clock.o
-custom-ro_objs-y += chip/g/dcrypto/sha256.o
-custom-ro_objs-y += chip/g/loader/key_ladder.o
-custom-ro_objs-y += chip/g/loader/debug_printf.o
-custom-ro_objs-y += chip/g/loader/launch.o
-custom-ro_objs-y += chip/g/loader/main.o
-custom-ro_objs-y += chip/g/loader/rom_flash.o
-custom-ro_objs-y += chip/g/loader/setup.o
-custom-ro_objs-y += chip/g/loader/verify.o
-custom-ro_objs-y += chip/g/pmu.o
-custom-ro_objs-y += chip/g/system.o
-custom-ro_objs-y += chip/g/trng.o
-custom-ro_objs-y += chip/g/uart.o
-custom-ro_objs-y += chip/g/uartn.o
-custom-ro_objs-y += common/printf.o
-custom-ro_objs-y += common/util.o
-custom-ro_objs-y += core/cortex-m/init.o
-custom-ro_objs-y += core/cortex-m/vecttable.o
-custom-ro_objs-y += core/cortex-m/panic.o
-dirs-y += chip/g/dcrypto
-dirs-y += chip/g/loader
-endif
-
-# Do not build any test on chip/g
-test-list-y=
-
-%.hex: %.flat
-
-ifneq ($(CONFIG_RW_B),)
-$(out)/$(PROJECT).obj: $(out)/RW/ec.RW_B.flat
-endif
-
-CR50_OPTS=
-
-ifneq ($(CR50_DEV),)
-CPPFLAGS += -DCR50_DEV=$(CR50_DEV)
-CR50_OPTS+=CR50_DEV
-endif
-
-ifneq ($(CR50_SQA),)
-CPPFLAGS += -DCR50_SQA=$(CR50_SQA)
-CR50_OPTS+=CR50_SQA
-endif
-
-# Test if more than one Cr50 build option is specified
-ifneq ($(wordlist 2,3,$(CR50_OPTS)),)
-$(error Incompatible CR50 build options specified: $(CR50_OPTS))
-endif
-
-MANIFEST := util/signer/ec_RW-manifest-dev.json
-CR50_RO_KEY ?= rom-testkey-A.pem
-
-# Make sure signing happens only when the signer is available.
-REAL_SIGNER = /usr/bin/cr50-codesigner
-ifneq ($(wildcard $(REAL_SIGNER)),)
-SIGNED_IMAGES = 1
-SIGNER := $(REAL_SIGNER)
-endif
-
-ifeq ($(CHIP_MK_INCLUDED_ONCE),)
-
-CHIP_MK_INCLUDED_ONCE := 1
-# We'll have to tweak the manifest no matter what, but different ways
-# depending on the way the image is built.
-SIGNER_MANIFEST := $(shell mktemp /tmp/h1.signer.XXXXXX)
-RW_SIGNER_EXTRAS += -j $(SIGNER_MANIFEST) -x util/signer/fuses.xml
-
-ifneq ($(CR50_SWAP_RMA_KEYS),)
-
-ifneq ($(CONFIG_RMA_AUTH_USE_P256),)
-CURVE := p256
-else
-CURVE := x25519
-endif
-
-RMA_KEY_BASE := board/$(BOARD)/rma_key_blob.$(CURVE)
-RW_SIGNER_EXTRAS += --swap $(RMA_KEY_BASE).test,$(RMA_KEY_BASE).prod
-endif
-
-endif
-
-ifeq ($(H1_DEVIDS),)
-# Signing with non-secret test key.
-CR50_RW_KEY = loader-testkey-A.pem
-# Make sure manifset Key ID field matches the actual key.
-DUM := $(shell sed 's/860844255/-764428053/' $(MANIFEST) > $(SIGNER_MANIFEST))
-else
-# The private key comes from the sighing fob.
-CR50_RW_KEY = cr50_rom0-dev-blsign.pem.pub
-
-ifneq ($(CHIP_MK_INCLUDED_ONCE),)
-#
-# When building a node locked cr50 image for an H1 device with prod RO, the
-# manifest needs to be modifed to include the device ID of the chip the image
-# is built for.
-#
-# The device ID consists of two 32 bit numbers which can be retrieved by
-# running the 'sysinfo' command on the cr50 console. These two numbers
-# need to be spliced into the signer manifest after the '"fuses": {' line
-# for the signer to pick them up. Pass the numbers on the make command line
-# like this:
-#
-# H1_DEVIDS='<num 1> <num 2>' make ...
-#
-ifneq ($(CR50_DEV),)
-
-#
-# When building a debug image, we don't want rollback protection to be in the
-# way - a debug image, which is guaranteed to be node locked should run on any
-# H1, whatever its info mask state is. The awk script below clears out the
-# info {} section of the manifest.
-#
-DUMMY := $(shell /usr/bin/awk 'BEGIN {skip = 0}; \
-	/^},/ {skip = 0}; \
-	{if (!skip) {print };} \
-	/\"info\": {/ {skip = 1};' $(MANIFEST) > $(SIGNER_MANIFEST))
-else
-DUMMY := $(shell /bin/cp $(MANIFEST) $(SIGNER_MANIFEST))
-endif
-REPLACEMENT := $(shell printf \
-	'\\n    \\"DEV_ID0\\": %s,\\n    \\"DEV_ID1\\": %s,' $(H1_DEVIDS))
-NODE_JSON :=  $(shell sed -i \
-	"s/\"fuses\": {/\"fuses\": {$(REPLACEMENT)/" $(SIGNER_MANIFEST))
-
-endif  # CHIP_MK_INCLUDED_ONCE defined
-endif  # H1_DEVIDS defined
-
-
-# This file is included twice by the Makefile, once to determine the CHIP info
-# # and then again after defining all the CONFIG_ and HAS_TASK variables. We use
-# # a guard so that recipe definitions and variable extensions only happen the
-# # second time.
-ifneq ($(CHIP_MK_INCLUDED_ONCE),)
-$(out)/RW/ec.RW_B.flat: $(out)/RW/ec.RW.flat
-$(out)/RW/ec.RW.flat $(out)/RW/ec.RW_B.flat: SIGNER_EXTRAS = $(RW_SIGNER_EXTRAS)
-
-endif   # CHIP_MK_INCLUDED_ONCE is nonempty
diff --git a/chip/g/clock.c b/chip/g/clock.c
deleted file mode 100644
index c590ee0611..0000000000
--- a/chip/g/clock.c
+++ /dev/null
@@ -1,58 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "clock.h"
-#include "registers.h"
-#include "pmu.h"
-
-void clock_init(void)
-{
-	pmu_clock_en(PERIPH_TIMEHS0);
-	pmu_clock_en(PERIPH_TIMEHS1);
-	pmu_clock_en(PERIPH_TIMELS0);
-	pmu_clock_switch_xo();
-}
-
-void clock_enable_module(enum module_id module, int enable)
-{
-	pmu_clock_func clock_func;
-	clock_func = (enable) ?  pmu_clock_en : pmu_clock_dis;
-
-	switch (module) {
-	case MODULE_UART:
-		clock_func(PERIPH_UART0);
-		clock_func(PERIPH_UART1);
-		clock_func(PERIPH_UART2);
-		break;
-	case MODULE_I2C:
-		clock_func(PERIPH_I2C0);
-		clock_func(PERIPH_I2C1);
-		break;
-	case MODULE_RBOX:
-		clock_func(PERIPH_RBOX);
-		break;
-	case MODULE_RDD:
-		clock_func(PERIPH_RDD0);
-		break;
-	case MODULE_SPI_FLASH:
-	case MODULE_SPI_MASTER:
-		clock_func(PERIPH_SPI);
-		break;
-	case MODULE_SPI:
-		clock_func(PERIPH_SPS);
-		break;
-	case MODULE_USB:
-		clock_func(PERIPH_USB0);
-		clock_func(PERIPH_USB0_USB_PHY);
-		pmu_enable_clock_doubler();
-		break;
-	case MODULE_PMU:
-		clock_func(PERIPH_PMU);
-		break;
-	default:
-		break;
-	}
-	return;
-}
diff --git a/chip/g/config_chip.h b/chip/g/config_chip.h
deleted file mode 100644
index 7c60567dfc..0000000000
--- a/chip/g/config_chip.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CONFIG_CHIP_H
-#define __CROS_EC_CONFIG_CHIP_H
-
-#if defined(BOARD)
-#include "core/cortex-m/config_core.h"
-#include "hw_regdefs.h"
-#endif
-
-/* Describe the RAM layout */
-#define CONFIG_RAM_BASE         0x10000
-#define CONFIG_RAM_SIZE         0x10000
-
-/* Flash chip specifics */
-#define CONFIG_FLASH_BANK_SIZE         0x800	/* protect bank size */
-#define CONFIG_FLASH_ERASE_SIZE        0x800	/* erase bank size */
-/* This flash can only be written as 4-byte words (aligned properly, too). */
-#define CONFIG_FLASH_WRITE_SIZE        4	/* min write size (bytes) */
-/* But we have a 32-word buffer for writing multiple adjacent cells */
-#define CONFIG_FLASH_WRITE_IDEAL_SIZE  128	/* best write size (bytes) */
-/* The flash controller prevents bulk writes that cross row boundaries */
-#define CONFIG_FLASH_ROW_SIZE          256	/* row size */
-
-/* Describe the flash layout */
-#define CONFIG_PROGRAM_MEMORY_BASE     0x40000
-#define CONFIG_FLASH_SIZE              (512 * 1024)
-#define CONFIG_FLASH_ERASED_VALUE32    (-1U)
-
-#undef CONFIG_RO_HEAD_ROOM
-#define CONFIG_RO_HEAD_ROOM	       1024	/* Room for ROM signature. */
-#undef CONFIG_RW_HEAD_ROOM
-#define CONFIG_RW_HEAD_ROOM	       CONFIG_RO_HEAD_ROOM  /* same for RW */
-
-/* Memory-mapped internal flash */
-#define CONFIG_INTERNAL_STORAGE
-#define CONFIG_MAPPED_STORAGE
-
-/* Program is run directly from storage */
-#define CONFIG_MAPPED_STORAGE_BASE CONFIG_PROGRAM_MEMORY_BASE
-
-/* Interval between HOOK_TICK notifications */
-#define HOOK_TICK_INTERVAL_MS 500
-#define HOOK_TICK_INTERVAL    (HOOK_TICK_INTERVAL_MS * MSEC)
-
-/* System stack size */
-#define CONFIG_STACK_SIZE 1024
-
-/* Idle task stack size */
-#define IDLE_TASK_STACK_SIZE 512
-
-/* Default task stack size */
-#define TASK_STACK_SIZE 488
-
-/* Larger task stack size, for hook task */
-#define LARGER_TASK_STACK_SIZE 640
-
-/* Magic for gpio.inc */
-#define GPIO_PIN(port, index) (port), (1 << (index))
-#define GPIO_PIN_MASK(p, m) .port = (p), .mask = (m)
-#define DUMMY_GPIO_BANK 0
-
-#define PCLK_FREQ  (24 * 1000 * 1000)
-
-/* Number of IRQ vectors on the NVIC */
-#define CONFIG_IRQ_COUNT (GC_INTERRUPTS_COUNT - 15)
-
-/* We'll have some special commands of our own */
-#define CONFIG_EXTENSION_COMMAND 0xbaccd00a
-
-/* Chip needs to do custom pre-init */
-#define CONFIG_CHIP_PRE_INIT
-
-/*
- * The flash memory is implemented in two halves. The SoC bootrom will look for
- * the first-stage bootloader at the beginning of each of the two halves and
- * prefer the newer one if both are valid. In EC terminology the bootloader
- * would be called the RO firmware, so we actually have two, not one. The
- * bootloader also looks in each half of the flash for a valid RW firmware, so
- * we have two possible RW images as well. The RO and RW images are not tightly
- * coupled, so either RO image can choose to boot either RW image.
- *
- * The EC firmware configuration is not (yet?) prepared to handle multiple,
- * non-contiguous, RO/RW combinations, so there's a bit of hackery to make this
- * work.
- *
- * The following macros try to make this all work.
- */
-
-/* This isn't optional, since the bootrom will always look for both */
-#define CHIP_HAS_RO_B
-
-/* It's easier for us to consider each half as having its own RO and RW */
-#define CFG_FLASH_HALF (CONFIG_FLASH_SIZE >> 1)
-
-/*
- * We'll reserve some space at the top of each flash half for persistent
- * storage and other stuff that's not part of the RW image. We don't promise to
- * use these two areas for the same thing, it's just more convenient to make
- * them the same size.
- */
-#define CFG_TOP_SIZE  0x3000
-#define CFG_TOP_A_OFF (CFG_FLASH_HALF - CFG_TOP_SIZE)
-#define CFG_TOP_B_OFF (CONFIG_FLASH_SIZE - CFG_TOP_SIZE)
-
-/* The RO images start at the very beginning of each flash half */
-#define CONFIG_RO_MEM_OFF 0
-#define CHIP_RO_B_MEM_OFF CFG_FLASH_HALF
-
-/* Size reserved for each RO image */
-#define CONFIG_RO_SIZE 0x4000
-
-/*
- * RW images start right after the reserved-for-RO areas in each half, but only
- * because that's where the RO images look for them. It's not a HW constraint.
- */
-#define CONFIG_RW_MEM_OFF CONFIG_RO_SIZE
-#define CONFIG_RW_B_MEM_OFF (CFG_FLASH_HALF + CONFIG_RW_MEM_OFF)
-
-/* Size reserved for each RW image */
-#define CONFIG_RW_SIZE (CFG_FLASH_HALF - CONFIG_RW_MEM_OFF - CFG_TOP_SIZE)
-
-/*
- * These are needed in a couple of places, but aren't very meaningful. Because
- * we have two RO and two RW images, these values don't really match what's
- * described in the EC Image Geometry Spec at www.chromium.org.
- */
-/* TODO(wfrichar): Make them meaningful or learn to do without */
-#define CONFIG_EC_PROTECTED_STORAGE_OFF    0
-#define CONFIG_EC_PROTECTED_STORAGE_SIZE   CONFIG_FLASH_SIZE
-#define CONFIG_EC_WRITABLE_STORAGE_OFF     0
-#define CONFIG_EC_WRITABLE_STORAGE_SIZE	   CONFIG_FLASH_SIZE
-#define CONFIG_RO_STORAGE_OFF              0
-#define CONFIG_RW_STORAGE_OFF              0
-#define CONFIG_WP_STORAGE_OFF		   0
-#define CONFIG_WP_STORAGE_SIZE		   CONFIG_EC_PROTECTED_STORAGE_SIZE
-
-/*
- * Note: early versions of the SoC would let us build and manually sign our own
- * bootloaders, and the RW images could be self-signed. Production SoCs require
- * officially-signed binary blobs to use for the RO bootloader(s), and the RW
- * images that we build must be manually signed. So even though we generate RO
- * firmware images, they may not be useful.
- */
-#define CONFIG_CUSTOMIZED_RO
-
-/* Number of I2C ports */
-#define I2C_PORT_COUNT 2
-
-#define CONFIG_FLASH_LOG_SPACE CONFIG_FLASH_BANK_SIZE
-
-/*
- * Flash log occupies space in the top of RO_B section, its counterpart in
- * RO_A is occupied by the certs.
- */
-#define CONFIG_FLASH_LOG_BASE                                                  \
-	(CONFIG_PROGRAM_MEMORY_BASE + CHIP_RO_B_MEM_OFF + CONFIG_RO_SIZE -     \
-	 CONFIG_FLASH_LOG_SPACE)
-
-/* Use software crypto (libcryptoc). */
-#define CONFIG_LIBCRYPTOC
-#endif /* __CROS_EC_CONFIG_CHIP_H */
diff --git a/chip/g/crypto_api.c b/chip/g/crypto_api.c
deleted file mode 100644
index 9c0c7bb8f5..0000000000
--- a/chip/g/crypto_api.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "crypto_api.h"
-#include "dcrypto.h"
-
-void app_compute_hash(uint8_t *p_buf, size_t num_bytes,
-		  uint8_t *p_hash, size_t hash_len)
-{
-	uint8_t sha1_digest[SHA_DIGEST_SIZE];
-
-	/*
-	 * Use the built in dcrypto engine to generate the sha1 hash of the
-	 * buffer.
-	 */
-	DCRYPTO_SHA1_hash((uint8_t *)p_buf, num_bytes, sha1_digest);
-
-	memcpy(p_hash, sha1_digest, MIN(hash_len, sizeof(sha1_digest)));
-
-	if (hash_len > sizeof(sha1_digest))
-		memset(p_hash + sizeof(sha1_digest), 0,
-		       hash_len - sizeof(sha1_digest));
-}
-
-int app_cipher(const void *salt, void *out, const void *in, size_t size)
-{
-	return DCRYPTO_app_cipher(NVMEM, salt, out, in, size);
-}
-
-int crypto_enabled(void)
-{
-	return DCRYPTO_ladder_is_enabled();
-}
diff --git a/chip/g/dcrypto/aes.c b/chip/g/dcrypto/aes.c
deleted file mode 100644
index f5cc0e6d8f..0000000000
--- a/chip/g/dcrypto/aes.c
+++ /dev/null
@@ -1,160 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "dcrypto.h"
-#include "internal.h"
-#include "registers.h"
-
-static void set_control_register(
-	unsigned mode, unsigned key_size, unsigned encrypt)
-{
-	GWRITE_FIELD(KEYMGR, AES_CTRL, RESET, CTRL_NO_SOFT_RESET);
-	GWRITE_FIELD(KEYMGR, AES_CTRL, KEYSIZE, key_size);
-	GWRITE_FIELD(KEYMGR, AES_CTRL, CIPHER_MODE, mode);
-	GWRITE_FIELD(KEYMGR, AES_CTRL, ENC_MODE, encrypt);
-	GWRITE_FIELD(KEYMGR, AES_CTRL, CTR_ENDIAN, CTRL_CTR_BIG_ENDIAN);
-	GWRITE_FIELD(KEYMGR, AES_CTRL, ENABLE, CTRL_ENABLE);
-
-	/* Turn off random nops (which are enabled by default). */
-	GWRITE_FIELD(KEYMGR, AES_RAND_STALL_CTL, STALL_EN, 0);
-	/* Configure random nop percentage at 25%. */
-	GWRITE_FIELD(KEYMGR, AES_RAND_STALL_CTL, FREQ, 1);
-	/* Now turn on random nops. */
-	GWRITE_FIELD(KEYMGR, AES_RAND_STALL_CTL, STALL_EN, 1);
-}
-
-static int wait_read_data(volatile uint32_t *addr)
-{
-	int empty;
-	int count = 20;     /* Wait these many ~cycles. */
-
-	do {
-		empty = REG32(addr);
-		count--;
-	} while (count && empty);
-
-	return empty ? 0 : 1;
-}
-
-int DCRYPTO_aes_init(const uint8_t *key, uint32_t key_len, const uint8_t *iv,
-		enum cipher_mode c_mode, enum encrypt_mode e_mode)
-{
-	int i;
-	const struct access_helper *p;
-	uint32_t key_mode;
-
-	switch (key_len) {
-	case 128:
-		key_mode = 0;
-		break;
-	case 192:
-		key_mode = 1;
-		break;
-	case 256:
-		key_mode = 2;
-		break;
-	default:
-		/* Invalid key length specified. */
-		return 0;
-	}
-	set_control_register(c_mode, key_mode, e_mode);
-
-	/* Initialize hardware with AES key */
-	p = (struct access_helper *) key;
-	for (i = 0; i < (key_len >> 5); i++)
-		GR_KEYMGR_AES_KEY(i) = p[i].udata;
-	/* Trigger key expansion. */
-	GREG32(KEYMGR, AES_KEY_START) = 1;
-
-	/* Wait for key expansion. */
-	if (!wait_read_data(GREG32_ADDR(KEYMGR, AES_KEY_START))) {
-		/* Should not happen. */
-		return 0;
-	}
-
-	/* Initialize IV for modes that require it. */
-	if (iv) {
-		p = (struct access_helper *) iv;
-		for (i = 0; i < 4; i++)
-			GR_KEYMGR_AES_CTR(i) = p[i].udata;
-	}
-	return 1;
-}
-
-int DCRYPTO_aes_block(const uint8_t *in, uint8_t *out)
-{
-	int i;
-	struct access_helper *outw;
-	const struct access_helper *inw = (struct access_helper *) in;
-
-	/* Write plaintext. */
-	for (i = 0; i < 4; i++)
-		GREG32(KEYMGR, AES_WFIFO_DATA) = inw[i].udata;
-
-	/* Wait for the result. */
-	if (!wait_read_data(GREG32_ADDR(KEYMGR, AES_RFIFO_EMPTY))) {
-		/* Should not happen, ciphertext not ready. */
-		return 0;
-	}
-
-	/* Read ciphertext. */
-	outw = (struct access_helper *) out;
-	for (i = 0; i < 4; i++)
-		outw[i].udata = GREG32(KEYMGR, AES_RFIFO_DATA);
-	return 1;
-}
-
-void DCRYPTO_aes_write_iv(const uint8_t *iv)
-{
-	int i;
-	const struct access_helper *p = (const struct access_helper *) iv;
-
-	for (i = 0; i < 4; i++)
-		GR_KEYMGR_AES_CTR(i) = p[i].udata;
-}
-
-void DCRYPTO_aes_read_iv(uint8_t *iv)
-{
-	int i;
-	struct access_helper *p = (struct access_helper *) iv;
-
-	for (i = 0; i < 4; i++)
-		p[i].udata = GR_KEYMGR_AES_CTR(i);
-}
-
-int DCRYPTO_aes_ctr(uint8_t *out, const uint8_t *key, uint32_t key_bits,
-		const uint8_t *iv, const uint8_t *in, size_t in_len)
-{
-	/* Initialize AES hardware. */
-	if (!DCRYPTO_aes_init(key, key_bits, iv,
-				CIPHER_MODE_CTR, ENCRYPT_MODE))
-		return 0;
-
-	while (in_len > 0) {
-		uint8_t tmpin[16];
-		uint8_t tmpout[16];
-		const uint8_t *inp;
-		uint8_t *outp;
-		const size_t count = MIN(in_len, 16);
-
-		if (count < 16) {
-			memcpy(tmpin, in, count);
-			inp = tmpin;
-			outp = tmpout;
-		} else {
-			inp = in;
-			outp = out;
-		}
-		if (!DCRYPTO_aes_block(inp, outp))
-			return 0;
-		if (outp != out)
-			memcpy(out, outp, count);
-
-		in += count;
-		out += count;
-		in_len -= count;
-	}
-	return 1;
-}
diff --git a/chip/g/dcrypto/aes_cmac.c b/chip/g/dcrypto/aes_cmac.c
deleted file mode 100644
index 4f996f42b6..0000000000
--- a/chip/g/dcrypto/aes_cmac.c
+++ /dev/null
@@ -1,346 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* AES-CMAC-128 implementation according to NIST SP 800-38B, RFC4493 */
-#include "console.h"
-#include "dcrypto.h"
-
-#define BSIZE 16 /* 16 bytes per 128-bit block */
-
-/* Given a 128-bit number in 32-bit chunks, shift to the left by one */
-static void shiftl_1(const uint8_t *in, uint8_t *out)
-{
-	int i;
-	uint8_t carry = 0;
-
-	for (i = 15; i >= 0; i--) {
-		out[i] = in[i] << 1;
-		out[i] |= carry;
-		carry = (in[i] & 0x80) ? 1 : 0;
-	}
-}
-
-static void xor128(const uint32_t in1[4], const uint32_t in2[4],
-		uint32_t out[4])
-{
-	int i;
-
-	for (i = 0; i < 4; i++)
-		out[i] = in1[i] ^ in2[i];
-}
-
-static void get_and_xor(const uint8_t *arr, const uint32_t nBytes, int i,
-			const uint8_t *xor_term, uint8_t *out)
-{
-	int j;
-	int k;
-
-	for (j = 0; j < 16; j++) {
-		k = i*16 + j; /* index in arr */
-		if (k < nBytes)
-			out[j] = arr[k];
-		else if (k == nBytes)
-			out[j] = 0x80;
-		else
-			out[j] = 0;
-		out[j] = out[j] ^ xor_term[j];
-	}
-}
-
-/* Wrapper for initializing and calling AES-128 */
-static int aes128(const uint8_t *K, const uint32_t in[4], uint32_t out[4])
-{
-	const uint32_t zero[4] = {0, 0, 0, 0};
-
-	if (!DCRYPTO_aes_init((const uint8_t *)K, 128, (const uint8_t *) zero,
-				CIPHER_MODE_ECB, ENCRYPT_MODE))
-		return 0;
-	if (!DCRYPTO_aes_block((const uint8_t *) in, (uint8_t *) out))
-		return 0;
-	return 1;
-}
-
-static int gen_subkey(const uint8_t *K, uint32_t k1[4], uint32_t k2[4])
-{
-	uint32_t L[4];
-	uint32_t tmp[4];
-	const uint32_t *xor_term;
-	static const uint32_t zero[4] = {0, 0, 0, 0};
-	static const uint32_t Rb[4] = {0, 0, 0, 0x87000000};
-
-	if (!aes128(K, zero, L))
-		return 0;
-
-	xor_term = (L[0] & 0x00000080) ? Rb : zero;
-	shiftl_1((const uint8_t *)L, (uint8_t *)tmp);
-	xor128(tmp, xor_term, k1);
-
-	xor_term = (k1[0] & 0x00000080) ? Rb : zero;
-	shiftl_1((const uint8_t *) k1, (uint8_t *) tmp);
-	xor128(tmp, xor_term, k2);
-
-	return 1;
-}
-
-int DCRYPTO_aes_cmac(const uint8_t *K, const uint8_t *M, const uint32_t len,
-		uint32_t T[4])
-{
-	uint32_t n;
-	int i;
-	int flag;
-	uint32_t k1[4];
-	uint32_t k2[4];
-	uint32_t M_last[4];
-	uint32_t Y[4];
-	uint32_t X[4] = {0, 0, 0, 0};
-
-	/* Generate the subkeys K1 and K2 */
-	if (!gen_subkey(K, k1, k2))
-		return 0;
-
-	/* Set n and flag.
-	 * flag = 1 if the last block has a full 128 bits; 0 otherwise
-	 * n = number of 128-bit blocks in input = ceil (len / BSIZE)
-	 *
-	 * Special case: if len = 0, then n = 1 and flag = 0.
-	 */
-	flag = (len % BSIZE == 0) ? 1 : 0;
-	n = len / BSIZE + (flag ? 0 : 1); // ceil (len / BSIZE)
-	if (len == 0) {
-		n = 1;
-		flag = 0;
-	}
-
-	/* M_last = padded(last 128-bit block of M) ^ (flag ? k1 : k2) */
-	get_and_xor(M, len, n-1, (uint8_t *) (flag ? k1 : k2),
-			(uint8_t *) M_last);
-
-	for (i = 0; i < n - 1; i++) {
-		/* Y = padded(nth 128-bit block of M) ^ (flag ? k1 : k2) */
-		get_and_xor(M, len, i, (uint8_t *)X, (uint8_t *)Y);
-		if (!aes128(K, Y, X))
-			return 0;
-	}
-
-	/* TODO: This block is separate from the main loop in the RFC. However,
-	 * if we set M[n-1] = M_last, then it is equivalent to running the loop
-	 * for one more step, which might be a nicer way to write it.
-	 */
-	xor128(X, M_last, Y);
-	if (!aes128(K, Y, T))
-		return 0;
-	return 1;
-}
-
-int DCRYPTO_aes_cmac_verify(const uint8_t *key, const uint8_t *M, const int len,
-		const uint32_t T[4])
-{
-	int i;
-	uint32_t T2[4];
-	int match = 1;
-
-	if (!DCRYPTO_aes_cmac(key, M, len, T2))
-		return -EC_ERROR_UNKNOWN;
-
-	for (i = 0; i < 4; i++) {
-		if (T[i] != T2[i])
-			match = 0;
-	}
-	return match;
-}
-
-#ifdef CRYPTO_TEST_SETUP
-static int check_answer(const uint32_t expected[4], uint32_t actual[4])
-{
-	int i;
-	int success = 1;
-
-	for (i = 0; i < 4; i++) {
-		if (actual[i] != expected[i])
-			success = 0;
-	}
-	if (success) {
-		ccprintf("SUCCESS\n");
-	} else {
-		ccprintf("FAILURE:\n");
-		ccprintf("actual   = 0x%08x 0x%08x 0x%08x 0x%08x\n", actual[0],
-			 actual[1], actual[2], actual[3]);
-		ccprintf("expected = 0x%08x 0x%08x 0x%08x 0x%08x\n",
-			 expected[0], expected[1], expected[2], expected[3]);
-	}
-	return success;
-}
-
-static int command_test_aes_block(int argc, char **argv)
-{
-	uint32_t actual[4];
-	const uint32_t zero[4] = {0, 0, 0, 0};
-	const uint32_t K[4] = {0x16157e2b, 0xa6d2ae28, 0x8815f7ab, 0x3c4fcf09};
-	const uint32_t expected[4] = {0x0c6bf77d, 0xb399b81a, 0x47f0423e,
-				      0x6f541bb9};
-
-	aes128((const uint8_t *) K, zero, actual);
-	check_answer(expected, actual);
-
-	return 0;
-}
-
-DECLARE_SAFE_CONSOLE_COMMAND(test_aesbk, command_test_aes_block, NULL,
-			     "Test AES block in AES-CMAC subkey generation");
-
-static int command_test_subkey_gen(int argc, char **argv)
-{
-	uint32_t k1[4];
-	uint32_t k2[4];
-	/* K:  2b7e1516 28aed2a6 abf71588 09cf4f3c
-	 * k1: fbeed618 35713366 7c85e08f 7236a8de
-	 * k2: f7ddac30 6ae266cc f90bc11e e46d513b
-	 */
-	const uint32_t K[4] = {0x16157e2b, 0xa6d2ae28, 0x8815f7ab, 0x3c4fcf09};
-	const uint32_t k1e[4] = {0x18d6eefb, 0x66337135, 0x8fe0857c,
-				 0xdea83672};
-	const uint32_t k2e[4] = {0x30acddf7, 0xcc66e26a, 0x1ec10bf9,
-				 0x3b516de4};
-
-	gen_subkey((const uint8_t *) K, k1, k2);
-
-	ccprintf("Checking K1: ");
-	check_answer(k1e, k1);
-
-	ccprintf("Checking K2: ");
-	check_answer(k2e, k2);
-
-	return 0;
-}
-
-DECLARE_SAFE_CONSOLE_COMMAND(test_skgen, command_test_subkey_gen, NULL,
-			     "Test AES-CMAC subkey generation");
-
-struct cmac_test_param {
-	uint32_t len;
-	uint8_t *M;
-	uint32_t Te[4];
-};
-
-/* N.B. The order of bytes in each 32-bit block is reversed from the form in
- * which they are written in the RFC.
- */
-const struct cmac_test_param rfctests[4] = {
-	/*  --------------------------------------------------
-	 *  Example 1: len = 0
-	 *  M	      <empty string>
-	 *  AES-CMAC       bb1d6929 e9593728 7fa37d12 9b756746
-	 *  --------------------------------------------------
-	 */
-	{ .len = 0,
-	  .M   = (uint8_t *) "",
-	  .Te  = {0x29691dbb, 0x283759e9, 0x127da37f, 0x4667759b},
-	  },
-	/*  --------------------------------------------------
-	 *  Example 2: len = 16
-	 *  M	      6bc1bee2 2e409f96 e93d7e11 7393172a
-	 *  AES-CMAC       070a16b4 6b4d4144 f79bdd9d d04a287c
-	 *  --------------------------------------------------
-	 */
-	{ .len = 16,
-	  .M   = (uint8_t *) (uint32_t[]) {
-		0xe2bec16b, 0x969f402e, 0x117e3de9, 0x2a179373
-		},
-	  .Te  = {0xb4160a07, 0x44414d6b, 0x9ddd9bf7, 0x7c284ad0},
-	  },
-	/*  --------------------------------------------------
-	 *  Example 3: len = 40
-	 *  M	      6bc1bee2 2e409f96 e93d7e11 7393172a
-	 *	      ae2d8a57 1e03ac9c 9eb76fac 45af8e51
-	 *	      30c81c46 a35ce411
-	 *  AES-CMAC       dfa66747 de9ae630 30ca3261 1497c827
-	 *  --------------------------------------------------
-	 */
-	{ .len = 40,
-	  .M   = (uint8_t *) (uint32_t[]) {
-		0xe2bec16b, 0x969f402e, 0x117e3de9, 0x2a179373,
-		0x578a2dae, 0x9cac031e, 0xac6fb79e, 0x518eaf45,
-		0x461cc830, 0x11e45ca3
-		},
-	  .Te  = {0x4767a6df, 0x30e69ade, 0x6132ca30, 0x27c89714},
-	  },
-	/*  --------------------------------------------------
-	 *  Example 4: len = 64
-	 *  M	      6bc1bee2 2e409f96 e93d7e11 7393172a
-	 *	      ae2d8a57 1e03ac9c 9eb76fac 45af8e51
-	 *	      30c81c46 a35ce411 e5fbc119 1a0a52ef
-	 *	      f69f2445 df4f9b17 ad2b417b e66c3710
-	 *  AES-CMAC       51f0bebf 7e3b9d92 fc497417 79363cfe
-	 *  --------------------------------------------------
-	 */
-	{ .len = 64,
-	  .M   = (uint8_t *) (uint32_t[]) {
-		0xe2bec16b, 0x969f402e, 0x117e3de9, 0x2a179373,
-		0x578a2dae, 0x9cac031e, 0xac6fb79e, 0x518eaf45,
-		0x461cc830, 0x11e45ca3, 0x19c1fbe5, 0xef520a1a,
-		0x45249ff6, 0x179b4fdf, 0x7b412bad, 0x10376ce6
-		},
-	  .Te  = {0xbfbef051, 0x929d3b7e, 0x177449fc, 0xfe3c3679},
-	  },
-};
-
-static int command_test_aes_cmac(int argc, char **argv)
-{
-	int i;
-	uint32_t T[4];
-	int testN;
-	struct cmac_test_param param;
-	const uint32_t K[4] = {0x16157e2b, 0xa6d2ae28, 0x8815f7ab, 0x3c4fcf09};
-
-	for (i = 1; i < argc; i++) {
-		testN = strtoi(argv[i], NULL, 10);
-		param = rfctests[testN - 1];
-
-		ccprintf("Testing RFC Example #%d (%d-byte message)...", testN,
-			 param.len);
-
-		DCRYPTO_aes_cmac((const uint8_t *)K, param.M, param.len, T);
-		check_answer(param.Te, T);
-	}
-
-	return 0;
-}
-
-DECLARE_SAFE_CONSOLE_COMMAND(test_cmac, command_test_aes_cmac,
-		"[test cases (1-4)]",
-		"Test AES-CMAC with RFC examples");
-
-static int command_test_verify(int argc, char **argv)
-{
-	int i;
-	int testN;
-	int result;
-	struct cmac_test_param param;
-	const uint32_t K[4] = {0x16157e2b, 0xa6d2ae28, 0x8815f7ab, 0x3c4fcf09};
-
-	for (i = 1; i < argc; i++) {
-		testN = strtoi(argv[i], NULL, 10);
-		param = rfctests[testN-1];
-
-		ccprintf("Testing RFC Example #%d (%d-byte message)...", testN,
-			 param.len);
-
-		result = DCRYPTO_aes_cmac_verify((const uint8_t *)K, param.M,
-				param.len, param.Te);
-		if (result == 1)
-			ccprintf("SUCCESS\n");
-		else if (result == 0)
-			ccprintf("FAILURE: verify returned INVALID\n");
-		else if (result == -EC_ERROR_UNKNOWN)
-			ccprintf("FAILURE: verify returned ERROR\n");
-	}
-
-	return 0;
-}
-
-DECLARE_SAFE_CONSOLE_COMMAND(test_cmac_ver, command_test_verify,
-		"[test cases (1-4)]",
-		"Test AES-CMAC-verify with RFC examples");
-#endif /* CRYPTO_TEST_SETUP */
diff --git a/chip/g/dcrypto/app_cipher.c b/chip/g/dcrypto/app_cipher.c
deleted file mode 100644
index e465598718..0000000000
--- a/chip/g/dcrypto/app_cipher.c
+++ /dev/null
@@ -1,452 +0,0 @@
-/*
- * Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#include "dcrypto.h"
-#include "registers.h"
-
-/* The default build options compile for size (-Os); instruct the
- * compiler to optimize for speed here.  Incidentally -O produces
- * faster code than -O2!
- */
-static int __attribute__((optimize("O")))
-inner_loop(uint32_t **out, const uint32_t **in, size_t len)
-{
-	uint32_t *outw = *out;
-	const uint32_t *inw = *in;
-
-	while (len >= 16) {
-		uint32_t w0, w1, w2, w3;
-
-		w0 = inw[0];
-		w1 = inw[1];
-		w2 = inw[2];
-		w3 = inw[3];
-		GREG32(KEYMGR, AES_WFIFO_DATA) = w0;
-		GREG32(KEYMGR, AES_WFIFO_DATA) = w1;
-		GREG32(KEYMGR, AES_WFIFO_DATA) = w2;
-		GREG32(KEYMGR, AES_WFIFO_DATA) = w3;
-
-		while (GREG32(KEYMGR, AES_RFIFO_EMPTY))
-			;
-
-		w0 = GREG32(KEYMGR, AES_RFIFO_DATA);
-		w1 = GREG32(KEYMGR, AES_RFIFO_DATA);
-		w2 = GREG32(KEYMGR, AES_RFIFO_DATA);
-		w3 = GREG32(KEYMGR, AES_RFIFO_DATA);
-		outw[0] = w0;
-		outw[1] = w1;
-		outw[2] = w2;
-		outw[3] = w3;
-
-		inw += 4;
-		outw += 4;
-		len -= 16;
-	}
-
-	*in = inw;
-	*out = outw;
-	return len;
-}
-
-static int outer_loop(uint32_t **out, const uint32_t **in, size_t len)
-{
-	uint32_t *outw = *out;
-	const uint32_t *inw = *in;
-
-	if (len >= 16) {
-		GREG32(KEYMGR, AES_WFIFO_DATA) = inw[0];
-		GREG32(KEYMGR, AES_WFIFO_DATA) = inw[1];
-		GREG32(KEYMGR, AES_WFIFO_DATA) = inw[2];
-		GREG32(KEYMGR, AES_WFIFO_DATA) = inw[3];
-		inw += 4;
-		len -= 16;
-
-		len = inner_loop(&outw, &inw, len);
-
-		while (GREG32(KEYMGR, AES_RFIFO_EMPTY))
-			;
-
-		outw[0] = GREG32(KEYMGR, AES_RFIFO_DATA);
-		outw[1] = GREG32(KEYMGR, AES_RFIFO_DATA);
-		outw[2] = GREG32(KEYMGR, AES_RFIFO_DATA);
-		outw[3] = GREG32(KEYMGR, AES_RFIFO_DATA);
-		outw += 4;
-	}
-
-	*in =  inw;
-	*out = outw;
-	return len;
-}
-
-static int aes_init(struct APPKEY_CTX *ctx, enum dcrypto_appid appid,
-		const uint32_t iv[4])
-{
-	/* Setup USR-based application key. */
-	if (!DCRYPTO_appkey_init(appid, ctx))
-		return 0;
-
-	/* Configure AES engine. */
-	GWRITE_FIELD(KEYMGR, AES_CTRL, RESET, CTRL_NO_SOFT_RESET);
-	GWRITE_FIELD(KEYMGR, AES_CTRL, KEYSIZE, 2 /* AES-256 */);
-	GWRITE_FIELD(KEYMGR, AES_CTRL, CIPHER_MODE, CIPHER_MODE_CTR);
-	GWRITE_FIELD(KEYMGR, AES_CTRL, ENC_MODE, ENCRYPT_MODE);
-	GWRITE_FIELD(KEYMGR, AES_CTRL, CTR_ENDIAN, CTRL_CTR_BIG_ENDIAN);
-
-	/*
-	 * For fixed-key, bulk ciphering, turn off random nops (which
-	 * are enabled by default).
-	 */
-	GWRITE_FIELD(KEYMGR, AES_RAND_STALL_CTL, STALL_EN, 0);
-
-	/* Enable hidden key usage, each appid gets its own
-	 * USR, with USR0 starting at 0x2a0.
-	 */
-	GWRITE_FIELD(KEYMGR, AES_USE_HIDDEN_KEY, INDEX,
-		0x2a0 + (appid * 2));
-	GWRITE_FIELD(KEYMGR, AES_USE_HIDDEN_KEY, ENABLE, 1);
-	GWRITE_FIELD(KEYMGR, AES_CTRL, ENABLE, CTRL_ENABLE);
-
-	/* Wait for key-expansion. */
-	GREG32(KEYMGR, AES_KEY_START) = 1;
-	while (GREG32(KEYMGR, AES_KEY_START))
-		;
-
-	/* Check for errors (e.g. USR not correctly setup. */
-	if (GREG32(KEYMGR, HKEY_ERR_FLAGS))
-		return 0;
-
-	/* Set IV. */
-	GR_KEYMGR_AES_CTR(0) = iv[0];
-	GR_KEYMGR_AES_CTR(1) = iv[1];
-	GR_KEYMGR_AES_CTR(2) = iv[2];
-	GR_KEYMGR_AES_CTR(3) = iv[3];
-
-	return 1;
-}
-
-int DCRYPTO_app_cipher(enum dcrypto_appid appid, const void *salt,
-		void *out, const void *in, size_t len)
-{
-	struct APPKEY_CTX ctx;
-	const uint32_t *inw = in;
-	uint32_t *outw = out;
-
-	/* Test pointers for word alignment. */
-	if (((uintptr_t) in & 0x03) || ((uintptr_t) out & 0x03))
-		return 0;
-
-	{
-		/* Initialize key, and AES engine. */
-		uint32_t iv[4];
-
-		memcpy(iv, salt, sizeof(iv));
-		if (!aes_init(&ctx, appid, iv))
-			return 0;
-	}
-
-	len = outer_loop(&outw, &inw, len);
-
-	if (len) {
-		/* Cipher the final partial block */
-		uint32_t tmpin[4];
-		uint32_t tmpout[4];
-		const uint32_t *tmpinw;
-		uint32_t *tmpoutw;
-
-		tmpinw = tmpin;
-		tmpoutw = tmpout;
-
-		memcpy(tmpin, inw, len);
-		outer_loop(&tmpoutw, &tmpinw, 16);
-		memcpy(outw, tmpout, len);
-	}
-
-	DCRYPTO_appkey_finish(&ctx);
-	return 1;
-}
-
-#ifdef CRYPTO_TEST_SETUP
-
-#include "common.h"
-#include "console.h"
-#include "hooks.h"
-#include "shared_mem.h"
-#include "task.h"
-#include "timer.h"
-#include "watchdog.h"
-
-#define HEAP_HEAD_ROOM 0x400
-static uint32_t number_of_iterations;
-static uint8_t result;
-
-/* Staticstics for ecrypt and decryp passes. */
-struct ciph_stats {
-	uint16_t min_time;
-	uint16_t max_time;
-	uint32_t total_time;
-} __packed; /* Just in case. */
-
-/* A common structure to contain information about the test run. */
-struct test_info {
-	size_t test_blob_size;
-	struct ciph_stats enc_stats;
-	struct ciph_stats dec_stats;
-	char *p; /* Pointer to an allcoated buffer of test_blob_size bytes. */
-};
-
-static void init_stats(struct ciph_stats *stats)
-{
-	stats->min_time = ~0;
-	stats->max_time = 0;
-	stats->total_time = 0;
-}
-
-static void update_stats(struct ciph_stats *stats, uint32_t time)
-{
-	if (time < stats->min_time)
-		stats->min_time = time;
-
-	if (time > stats->max_time)
-		stats->max_time = time;
-
-	stats->total_time += time;
-}
-
-static void report_stats(const char *direction, struct ciph_stats *stats)
-{
-	ccprintf("%s results: min %d us, max %d us, average %d us\n",
-		 direction, stats->min_time, stats->max_time,
-		 stats->total_time / number_of_iterations);
-}
-
-/*
- * Prepare to run the test: allocate memory, initialize stats structures.
- *
- * Returns EC_SUCCESS if everything is fine, EC_ERROR_OVERFLOW on malloc
- * failures.
- */
-static int prepare_running(struct test_info *pinfo)
-{
-	memset(pinfo, 0, sizeof(*pinfo));
-
-
-	pinfo->test_blob_size = shared_mem_size();
-	/*
-	 * Leave some room for crypto functions if they need to allocate
-	 * something, just in case. 0x20 extra bytes are needed to be able to
-	 * modify size alignment of the allocated buffer.
-	 */
-	if (pinfo->test_blob_size < (HEAP_HEAD_ROOM + 0x20)) {
-		ccprintf("Not enough memory to run the test\n");
-		return EC_ERROR_OVERFLOW;
-	}
-	pinfo->test_blob_size = (pinfo->test_blob_size - HEAP_HEAD_ROOM);
-
-	if (shared_mem_acquire(pinfo->test_blob_size,
-			       (char **)&(pinfo->p)) != EC_SUCCESS) {
-		ccprintf("Failed to allocate %d bytes\n",
-			 pinfo->test_blob_size);
-		return EC_ERROR_OVERFLOW;
-	}
-
-	/*
-	 * Use odd block size to make sure unaligned length blocks are handled
-	 * properly. This leaves room in the end of the buffer to check if the
-	 * decryption routine scratches it.
-	 */
-	pinfo->test_blob_size &= ~0x1f;
-	pinfo->test_blob_size |= 7;
-
-	ccprintf("running %d iterations\n", number_of_iterations);
-	ccprintf("blob size %d at %pP\n", pinfo->test_blob_size, pinfo->p);
-
-	init_stats(&(pinfo->enc_stats));
-	init_stats(&(pinfo->dec_stats));
-
-	return EC_SUCCESS;
-}
-
-/*
- * Let's split the buffer in two equal halves, encrypt the lower half into the
- * upper half and compare them word by word. There should be no repetitions.
- *
- * The side effect of this is starting the test with random clear text data.
- *
- * The first 16 bytes of the allocated buffer are used as the encryption IV.
- */
-static int basic_check(struct test_info *pinfo)
-{
-	size_t half;
-	int i;
-	uint32_t *p;
-
-	ccprintf("original data  %ph\n", HEX_BUF(pinfo->p, 16));
-
-	half = (pinfo->test_blob_size/2) & ~3;
-	if (!DCRYPTO_app_cipher(NVMEM, pinfo->p, pinfo->p,
-				pinfo->p + half, half)) {
-		ccprintf("first ecnryption run failed\n");
-		return EC_ERROR_UNKNOWN;
-	}
-
-	p = (uint32_t *)pinfo->p;
-	half /= sizeof(*p);
-
-	for (i = 0; i < half; i++)
-		if (p[i] == p[i + half]) {
-			ccprintf("repeating 32 bit word detected"
-				 " at offset 0x%x!\n", i * 4);
-			return EC_ERROR_UNKNOWN;
-		}
-
-	ccprintf("hashed data    %ph\n", HEX_BUF(pinfo->p, 16));
-
-	return EC_SUCCESS;
-}
-
-/*
- * Main iteration of the console command, runs ecnryption/decryption cycles,
- * vefifying that decrypted text's hash matches the original, and accumulating
- * timing statistics.
- */
-static int command_loop(struct test_info *pinfo)
-{
-	uint8_t sha[SHA_DIGEST_SIZE];
-	uint8_t sha_after[SHA_DIGEST_SIZE];
-	uint32_t iteration;
-	uint8_t *p_last_byte;
-	int rv;
-
-	/*
-	 * Prepare the hash of the original data to be able to verify
-	 * results.
-	 */
-	DCRYPTO_SHA1_hash((uint8_t *)(pinfo->p), pinfo->test_blob_size, sha);
-
-	/* Use the hash as an IV for the cipher. */
-	memcpy(sha_after, sha, sizeof(sha_after));
-
-	iteration = number_of_iterations;
-	p_last_byte = pinfo->p + pinfo->test_blob_size;
-
-	while (iteration--) {
-		char last_byte = (char) iteration;
-		uint32_t tstamp;
-
-		*p_last_byte = last_byte;
-
-		if (!(iteration % 500))
-			watchdog_reload();
-
-		tstamp = get_time().val;
-		rv = DCRYPTO_app_cipher(NVMEM, sha_after, pinfo->p,
-					pinfo->p, pinfo->test_blob_size);
-		tstamp = get_time().val - tstamp;
-
-		if (!rv) {
-			ccprintf("encryption failed\n");
-			return EC_ERROR_UNKNOWN;
-		}
-		if (*p_last_byte != last_byte) {
-			ccprintf("encryption overflowed\n");
-			return EC_ERROR_UNKNOWN;
-		}
-		update_stats(&pinfo->enc_stats, tstamp);
-
-		tstamp = get_time().val;
-		rv = DCRYPTO_app_cipher(NVMEM, sha_after, pinfo->p,
-					pinfo->p, pinfo->test_blob_size);
-		tstamp = get_time().val - tstamp;
-
-		if (!rv) {
-			ccprintf("decryption failed\n");
-			return EC_ERROR_UNKNOWN;
-		}
-		if (*p_last_byte != last_byte) {
-			ccprintf("decryption overflowed\n");
-			return EC_ERROR_UNKNOWN;
-		}
-
-		DCRYPTO_SHA1_hash((uint8_t *)(pinfo->p),
-				  pinfo->test_blob_size, sha_after);
-		if (memcmp(sha, sha_after, sizeof(sha))) {
-			ccprintf("\n"
-				 "sha1 before and after mismatch, %d to go!\n",
-				 iteration);
-			return EC_ERROR_UNKNOWN;
-		}
-
-		update_stats(&pinfo->dec_stats, tstamp);
-
-		/* get a new IV */
-		DCRYPTO_SHA1_hash(sha_after, sizeof(sha), sha_after);
-	}
-
-	return EC_SUCCESS;
-}
-
-/*
- * Run cipher command on the hooks task context, as dcrypto's stack
- * requirements exceed console tasks' allowance.
- */
-static void run_cipher_cmd(void)
-{
-	struct test_info info;
-
-	result = prepare_running(&info);
-
-	if (result == EC_SUCCESS)
-		result = basic_check(&info);
-
-	if (result == EC_SUCCESS)
-		result = command_loop(&info);
-
-	if (result == EC_SUCCESS) {
-		report_stats("Encryption", &info.enc_stats);
-		report_stats("Decryption", &info.dec_stats);
-	} else if (info.p) {
-		ccprintf("current data   %ph\n", HEX_BUF(info.p, 16));
-	}
-
-	if (info.p)
-		shared_mem_release(info.p);
-
-	task_set_event(TASK_ID_CONSOLE, TASK_EVENT_CUSTOM_BIT(0), 0);
-}
-DECLARE_DEFERRED(run_cipher_cmd);
-
-static int cmd_cipher(int argc, char **argv)
-{
-	uint32_t events;
-	uint32_t max_time;
-
-	/* Ignore potential input errors, let the user handle them. */
-	if (argc > 1)
-		number_of_iterations = strtoi(argv[1], NULL, 0);
-	else
-		number_of_iterations = 1000;
-
-	if (!number_of_iterations) {
-		ccprintf("not running zero iterations\n");
-		return EC_ERROR_PARAM1;
-	}
-
-	hook_call_deferred(&run_cipher_cmd_data, 0);
-
-	/* Roughly, .5 us per byte should be more than enough. */
-	max_time = number_of_iterations * shared_mem_size() / 2;
-
-	ccprintf("Will wait up to %d ms\n", (max_time + 500)/1000);
-
-	events = task_wait_event_mask(TASK_EVENT_CUSTOM_BIT(0), max_time);
-	if (!(events & TASK_EVENT_CUSTOM_BIT(0))) {
-		ccprintf("Timed out, you might want to reboot...\n");
-		return EC_ERROR_TIMEOUT;
-	}
-
-	return result;
-}
-DECLARE_SAFE_CONSOLE_COMMAND(cipher, cmd_cipher, NULL, NULL);
-#endif
diff --git a/chip/g/dcrypto/app_key.c b/chip/g/dcrypto/app_key.c
deleted file mode 100644
index 1fafab9d2e..0000000000
--- a/chip/g/dcrypto/app_key.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#include "dcrypto.h"
-#include "internal.h"
-#include "endian.h"
-#include "registers.h"
-
-#include "cryptoc/util.h"
-
-#include "console.h"
-
-const char *const dcrypto_app_names[] = {
-	"RESERVED",
-	"NVMEM",
-	"U2F_ATTEST",
-	"U2F_ORIGIN",
-	"U2F_WRAP",
-	/* This key signs data from H1's configured by mn50/scribe. */
-	"PERSO_AUTH",
-	"PINWEAVER",
-};
-
-static void name_hash(enum dcrypto_appid appid,
-		      uint32_t digest[SHA256_DIGEST_WORDS])
-{
-	LITE_SHA256_CTX ctx;
-	const char *name = dcrypto_app_names[appid];
-	size_t x;
-
-	/* The PERSO_AUTH digest was improperly defined, so now this exception
-	 * exists to prevent data loss.
-	 */
-	if (appid == PERSO_AUTH) {
-		digest[0] = 0x2019da34;
-		digest[1] = 0xf1a01a13;
-		digest[2] = 0x0fb9f73f;
-		digest[3] = 0xf2e85f76;
-		digest[4] = 0x5ecb7690;
-		digest[5] = 0x09f732c9;
-		digest[6] = 0xe540bf14;
-		digest[7] = 0xcc46799a;
-		return;
-	}
-
-	DCRYPTO_SHA256_init(&ctx, 0);
-	HASH_update(&ctx, name, strlen(name));
-	memcpy(digest, HASH_final(&ctx), SHA256_DIGEST_SIZE);
-
-	/* The digests were originally endian swapped because xxd was used to
-	 * print them so this operation is needed to keep the derived keys the
-	 * same. Any changes to they key derivation process must result in the
-	 * same keys being produced given the same inputs, or devices will
-	 * effectively be reset and user data will be lost by the key change.
-	 */
-	for (x = 0; x < SHA256_DIGEST_WORDS; ++x)
-		digest[x] = __builtin_bswap32(digest[x]);
-}
-
-int DCRYPTO_appkey_init(enum dcrypto_appid appid, struct APPKEY_CTX *ctx)
-{
-	uint32_t digest[SHA256_DIGEST_WORDS];
-
-	memset(ctx, 0, sizeof(*ctx));
-	name_hash(appid, digest);
-
-	if (!dcrypto_ladder_compute_usr(appid, digest))
-		return 0;
-
-	return 1;
-}
-
-void DCRYPTO_appkey_finish(struct APPKEY_CTX *ctx)
-{
-	always_memset(ctx, 0, sizeof(struct APPKEY_CTX));
-	GREG32(KEYMGR, AES_WIPE_SECRETS) = 1;
-}
-
-int DCRYPTO_appkey_derive(enum dcrypto_appid appid, const uint32_t input[8],
-			  uint32_t output[8])
-{
-	uint32_t digest[SHA256_DIGEST_WORDS];
-
-	name_hash(appid, digest);
-	return !!dcrypto_ladder_derive(appid, digest, input, output);
-}
diff --git a/chip/g/dcrypto/bn.c b/chip/g/dcrypto/bn.c
deleted file mode 100644
index 94aafa1799..0000000000
--- a/chip/g/dcrypto/bn.c
+++ /dev/null
@@ -1,1244 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifdef PRINT_PRIMES
-#include "console.h"
-#endif
-
-#include "dcrypto.h"
-#include "internal.h"
-
-#include "trng.h"
-
-#include "cryptoc/util.h"
-
-#include <assert.h>
-
-#ifdef CONFIG_WATCHDOG
-extern void watchdog_reload(void);
-#else
-static inline void watchdog_reload(void) { }
-#endif
-
-void bn_init(struct LITE_BIGNUM *b, void *buf, size_t len)
-{
-	DCRYPTO_bn_wrap(b, buf, len);
-	always_memset(buf, 0x00, len);
-}
-
-void DCRYPTO_bn_wrap(struct LITE_BIGNUM *b, void *buf, size_t len)
-{
-	/* Only word-multiple sized buffers accepted. */
-	assert((len & 0x3) == 0);
-	b->dmax = len / LITE_BN_BYTES;
-	b->d = (struct access_helper *) buf;
-}
-
-int bn_eq(const struct LITE_BIGNUM *a, const struct LITE_BIGNUM *b)
-{
-	int i;
-	uint32_t top = 0;
-
-	for (i = a->dmax - 1; i > b->dmax - 1; --i)
-		top |= BN_DIGIT(a, i);
-	if (top)
-		return 0;
-
-	for (i = b->dmax - 1; i > a->dmax - 1; --i)
-		top |= BN_DIGIT(b, i);
-	if (top)
-		return 0;
-
-	for (i = MIN(a->dmax, b->dmax) - 1; i >= 0; --i)
-		if (BN_DIGIT(a, i) != BN_DIGIT(b, i))
-			return 0;
-
-	return 1;
-}
-
-static void bn_copy(struct LITE_BIGNUM *dst, const struct LITE_BIGNUM *src)
-{
-	dst->dmax = src->dmax;
-	memcpy(dst->d, src->d, bn_size(dst));
-}
-
-int bn_check_topbit(const struct LITE_BIGNUM *N)
-{
-	return BN_DIGIT(N, N->dmax - 1) >> 31;
-}
-
-/* a[n]. */
-int bn_is_bit_set(const struct LITE_BIGNUM *a, int n)
-{
-	int i, j;
-
-	if (n < 0)
-		return 0;
-
-	i = n / LITE_BN_BITS2;
-	j = n % LITE_BN_BITS2;
-	if (a->dmax <= i)
-		return 0;
-
-	return (BN_DIGIT(a, i) >> j) & 1;
-}
-
-static int bn_set_bit(const struct LITE_BIGNUM *a, int n)
-{
-	int i, j;
-
-	if (n < 0)
-		return 0;
-
-	i = n / LITE_BN_BITS2;
-	j = n % LITE_BN_BITS2;
-	if (a->dmax <= i)
-		return 0;
-
-	BN_DIGIT(a, i) |= 1 << j;
-	return 1;
-}
-
-/* a[] >= b[]. */
-/* TODO(ngm): constant time. */
-static int bn_gte(const struct LITE_BIGNUM *a, const struct LITE_BIGNUM *b)
-{
-	int i;
-	uint32_t top = 0;
-
-	for (i = a->dmax - 1; i > b->dmax - 1; --i)
-		top |= BN_DIGIT(a, i);
-	if (top)
-		return 1;
-
-	for (i = b->dmax - 1; i > a->dmax - 1; --i)
-		top |= BN_DIGIT(b, i);
-	if (top)
-		return 0;
-
-	for (i = MIN(a->dmax, b->dmax) - 1;
-	     BN_DIGIT(a, i) == BN_DIGIT(b, i) && i > 0; --i)
-		;
-	return BN_DIGIT(a, i) >= BN_DIGIT(b, i);
-}
-
-/* c[] = c[] - a[], assumes c > a. */
-uint32_t bn_sub(struct LITE_BIGNUM *c, const struct LITE_BIGNUM *a)
-{
-	int64_t A = 0;
-	int i;
-
-	for (i = 0; i < a->dmax; i++) {
-		A += (uint64_t) BN_DIGIT(c, i) - BN_DIGIT(a, i);
-		BN_DIGIT(c, i) = (uint32_t) A;
-		A >>= 32;
-	}
-
-	for (; A && i < c->dmax; i++) {
-		A += (uint64_t) BN_DIGIT(c, i);
-		BN_DIGIT(c, i) = (uint32_t) A;
-		A >>= 32;
-	}
-
-	return (uint32_t) A;  /* 0 or -1. */
-}
-
-/* c[] = c[] - a[], negative numbers in 2's complement representation. */
-/* Returns borrow bit. */
-static uint32_t bn_signed_sub(struct LITE_BIGNUM *c, int *c_neg,
-		const struct LITE_BIGNUM *a, int a_neg)
-{
-	uint32_t carry = 0;
-	uint64_t A = 1;
-	int i;
-
-	for (i = 0; i < a->dmax; ++i) {
-		A += (uint64_t) BN_DIGIT(c, i) + ~BN_DIGIT(a, i);
-		BN_DIGIT(c, i) = (uint32_t) A;
-		A >>= 32;
-	}
-
-	for (; i < c->dmax; ++i) {
-		A += (uint64_t) BN_DIGIT(c, i) + 0xFFFFFFFF;
-		BN_DIGIT(c, i) = (uint32_t) A;
-		A >>= 32;
-	}
-
-	A &= 0x01;
-	carry = (!*c_neg && a_neg && A) || (*c_neg && !a_neg && !A);
-	*c_neg = carry ? *c_neg : (*c_neg + !a_neg + A) & 0x01;
-	return carry;
-}
-
-/* c[] = c[] + a[]. */
-uint32_t bn_add(struct LITE_BIGNUM *c, const struct LITE_BIGNUM *a)
-{
-	uint64_t A = 0;
-	int i;
-
-	for (i = 0; i < a->dmax; ++i) {
-		A += (uint64_t) BN_DIGIT(c, i) + BN_DIGIT(a, i);
-		BN_DIGIT(c, i) = (uint32_t) A;
-		A >>= 32;
-	}
-
-	for (; A && i < c->dmax; ++i) {
-		A += (uint64_t) BN_DIGIT(c, i);
-		BN_DIGIT(c, i) = (uint32_t) A;
-		A >>= 32;
-	}
-
-	return (uint32_t) A;  /* 0 or 1. */
-}
-
-/* c[] = c[] + a[], negative numbers in 2's complement representation. */
-/* Returns carry bit. */
-static uint32_t bn_signed_add(struct LITE_BIGNUM *c, int *c_neg,
-			const struct LITE_BIGNUM *a, int a_neg)
-{
-	uint32_t A = bn_add(c, a);
-	uint32_t carry;
-
-	carry = (!*c_neg && !a_neg && A) || (*c_neg && a_neg && !A);
-	*c_neg = carry ? *c_neg : (*c_neg + a_neg + A) & 0x01;
-	return carry;
-}
-
-/* r[] <<= 1. */
-static uint32_t bn_lshift(struct LITE_BIGNUM *r)
-{
-	int i;
-	uint32_t w;
-	uint32_t carry = 0;
-
-	for (i = 0; i < r->dmax; i++) {
-		w = (BN_DIGIT(r, i) << 1) | carry;
-		carry = BN_DIGIT(r, i) >> 31;
-		BN_DIGIT(r, i) = w;
-	}
-	return carry;
-}
-
-/* r[] >>= 1.  Handles 2's complement negative numbers. */
-static void bn_rshift(struct LITE_BIGNUM *r, uint32_t carry, uint32_t neg)
-{
-	int i;
-	uint32_t ones = ~0;
-	uint32_t highbit = (!carry && neg) || (carry && !neg);
-
-	for (i = 0; i < r->dmax - 1; ++i) {
-		uint32_t accu;
-
-		ones &= BN_DIGIT(r, i);
-		accu = (BN_DIGIT(r, i) >> 1);
-		accu |= (BN_DIGIT(r, i + 1) << (LITE_BN_BITS2 - 1));
-		BN_DIGIT(r, i) = accu;
-	}
-	ones &= BN_DIGIT(r, i);
-	BN_DIGIT(r, i) = (BN_DIGIT(r, i) >> 1) |
-		(highbit << (LITE_BN_BITS2 - 1));
-
-	if (ones == ~0 && highbit && neg)
-		memset(r->d, 0x00, bn_size(r));    /* -1 >> 1 = 0. */
-}
-
-/* Montgomery c[] += a * b[] / R % N. */
-/* TODO(ngm): constant time. */
-static void bn_mont_mul_add(struct LITE_BIGNUM *c, const uint32_t a,
-			const struct LITE_BIGNUM *b, const uint32_t nprime,
-			const struct LITE_BIGNUM *N)
-{
-	uint32_t A, B, d0;
-	int i;
-
-	{
-		register uint64_t tmp;
-
-		tmp = BN_DIGIT(c, 0) + (uint64_t) a * BN_DIGIT(b, 0);
-		A = tmp >> 32;
-		d0 = (uint32_t) tmp * (uint32_t) nprime;
-		tmp = (uint32_t)tmp + (uint64_t) d0 * BN_DIGIT(N, 0);
-		B = tmp >> 32;
-	}
-
-	for (i = 0; i < N->dmax - 1;) {
-		register uint64_t tmp;
-
-		tmp = A + (uint64_t) a * BN_DIGIT(b, i + 1) +
-			BN_DIGIT(c, i + 1);
-		A = tmp >> 32;
-		tmp = B + (uint64_t) d0 * BN_DIGIT(N, i + 1) + (uint32_t) tmp;
-		BN_DIGIT(c, i) = (uint32_t) tmp;
-		B = tmp >> 32;
-		++i;
-	}
-
-	{
-		uint64_t tmp = (uint64_t) A + B;
-
-		BN_DIGIT(c, i) = (uint32_t) tmp;
-		A = tmp >> 32;  /* 0 or 1. */
-		if (A)
-			bn_sub(c, N);
-	}
-}
-
-/* Montgomery c[] = a[] * b[] / R % N. */
-static void bn_mont_mul(struct LITE_BIGNUM *c, const struct LITE_BIGNUM *a,
-			const struct LITE_BIGNUM *b, const uint32_t nprime,
-			const struct LITE_BIGNUM *N)
-{
-	int i;
-
-	for (i = 0; i < N->dmax; i++)
-		BN_DIGIT(c, i) = 0;
-
-	bn_mont_mul_add(c, a ? BN_DIGIT(a, 0) : 1, b, nprime, N);
-	for (i = 1; i < N->dmax; i++)
-		bn_mont_mul_add(c, a ? BN_DIGIT(a, i) : 0, b, nprime, N);
-}
-
-/* Mongomery R * R % N, R = 1 << (1 + log2N). */
-/* TODO(ngm): constant time. */
-static void bn_compute_RR(struct LITE_BIGNUM *RR, const struct LITE_BIGNUM *N)
-{
-	int i;
-
-	bn_sub(RR, N);         /* R - N = R % N since R < 2N */
-
-	/* Repeat 2 * R % N, log2(R) times. */
-	for (i = 0; i < N->dmax * LITE_BN_BITS2; i++) {
-		if (bn_lshift(RR))
-			assert(bn_sub(RR, N) == -1);
-		if (bn_gte(RR, N))
-			bn_sub(RR, N);
-	}
-}
-
-/* Montgomery nprime = -1 / n0 % (2 ^ 32). */
-static uint32_t bn_compute_nprime(const uint32_t n0)
-{
-	int i;
-	uint32_t ninv = 1;
-
-	/* Repeated Hensel lifting. */
-	for (i = 0; i  < 5; i++)
-		ninv *= 2 - (n0 * ninv);
-
-	return ~ninv + 1;       /* Two's complement. */
-}
-
-/* TODO(ngm): this implementation not timing or side-channel safe by
- * any measure. */
-static void bn_modexp_internal(struct LITE_BIGNUM *output,
-				const struct LITE_BIGNUM *input,
-				const struct LITE_BIGNUM *exp,
-				const struct LITE_BIGNUM *N)
-{
-	int i;
-	uint32_t nprime;
-	uint32_t RR_buf[RSA_MAX_WORDS];
-	uint32_t acc_buf[RSA_MAX_WORDS];
-	uint32_t aR_buf[RSA_MAX_WORDS];
-
-	struct LITE_BIGNUM RR;
-	struct LITE_BIGNUM acc;
-	struct LITE_BIGNUM aR;
-
-	bn_init(&RR, RR_buf, bn_size(N));
-	bn_init(&acc, acc_buf, bn_size(N));
-	bn_init(&aR, aR_buf, bn_size(N));
-
-	nprime = bn_compute_nprime(BN_DIGIT(N, 0));
-	bn_compute_RR(&RR, N);
-	bn_mont_mul(&acc, NULL, &RR, nprime, N);      /* R = 1 * RR / R % N */
-	bn_mont_mul(&aR, input, &RR, nprime, N);      /* aR = a * RR / R % N */
-
-	/* TODO(ngm): burn stack space and use windowing. */
-	for (i = exp->dmax * LITE_BN_BITS2 - 1; i >= 0; i--) {
-		bn_mont_mul(output, &acc, &acc, nprime, N);
-		if (bn_is_bit_set(exp, i)) {
-			bn_mont_mul(&acc, output, &aR, nprime, N);
-		} else {
-			struct LITE_BIGNUM tmp = *output;
-
-			*output = acc;
-			acc = tmp;
-		}
-		/* Poke the watchdog.
-		 * TODO(ngm): may be unnecessary with
-		 * a faster implementation.
-		 */
-		watchdog_reload();
-	}
-
-	bn_mont_mul(output, NULL, &acc, nprime, N);     /* Convert out. */
-	/* Copy to output buffer if necessary. */
-	if (acc.d != (struct access_helper *) acc_buf) {
-		memcpy(acc.d, acc_buf, bn_size(output));
-		*output = acc;
-	}
-
-	/* TODO(ngm): constant time. */
-	if (bn_sub(output, N))
-		bn_add(output, N);                      /* Final reduce. */
-	output->dmax = N->dmax;
-
-	always_memset(RR_buf, 0, sizeof(RR_buf));
-	always_memset(acc_buf, 0, sizeof(acc_buf));
-	always_memset(aR_buf, 0, sizeof(aR_buf));
-}
-
-/* output = input ^ exp % N */
-int bn_modexp(struct LITE_BIGNUM *output, const struct LITE_BIGNUM *input,
-		const struct LITE_BIGNUM *exp, const struct LITE_BIGNUM *N)
-{
-#ifndef CR50_NO_BN_ASM
-	if ((bn_bits(N) & 255) == 0) {
-		/* Use hardware support for standard key sizes. */
-		return dcrypto_modexp(output, input, exp, N);
-	}
-#endif
-	bn_modexp_internal(output, input, exp, N);
-	return 1;
-}
-
-/* output = input ^ exp % N */
-int bn_modexp_word(struct LITE_BIGNUM *output, const struct LITE_BIGNUM *input,
-		uint32_t exp, const struct LITE_BIGNUM *N)
-{
-#ifndef CR50_NO_BN_ASM
-	if ((bn_bits(N) & 255) == 0) {
-		/* Use hardware support for standard key sizes. */
-		return dcrypto_modexp_word(output, input, exp, N);
-	}
-#endif
-	{
-	struct LITE_BIGNUM pubexp;
-
-	DCRYPTO_bn_wrap(&pubexp, &exp, sizeof(exp));
-	bn_modexp_internal(output, input, &pubexp, N);
-	return 1;
-	}
-}
-
-/* output = input ^ exp % N */
-int bn_modexp_blinded(struct LITE_BIGNUM *output,
-			const struct LITE_BIGNUM *input,
-			const struct LITE_BIGNUM *exp,
-			const struct LITE_BIGNUM *N,
-			uint32_t pubexp)
-{
-#ifndef CR50_NO_BN_ASM
-	if ((bn_bits(N) & 255) == 0) {
-		/* Use hardware support for standard key sizes. */
-		return dcrypto_modexp_blinded(output, input, exp, N, pubexp);
-	}
-#endif
-	bn_modexp_internal(output, input, exp, N);
-	return 1;
-}
-
-/* c[] += a * b[] */
-static uint32_t bn_mul_add(struct LITE_BIGNUM *c, uint32_t a,
-		const struct LITE_BIGNUM *b, uint32_t offset)
-{
-	int i;
-	uint64_t carry = 0;
-
-	for (i = 0; i < b->dmax; i++) {
-		carry += BN_DIGIT(c, offset + i) +
-			(uint64_t) BN_DIGIT(b, i) * a;
-		BN_DIGIT(c, offset + i) = (uint32_t) carry;
-		carry >>= 32;
-	}
-
-	return carry;
-}
-
-/* c[] = a[] * b[] */
-void DCRYPTO_bn_mul(struct LITE_BIGNUM *c, const struct LITE_BIGNUM *a,
-		const struct LITE_BIGNUM *b)
-{
-	int i;
-	uint32_t carry = 0;
-
-	memset(c->d, 0, bn_size(c));
-	for (i = 0; i < a->dmax; i++) {
-		BN_DIGIT(c, i + b->dmax - 1) = carry;
-		carry = bn_mul_add(c, BN_DIGIT(a, i), b, i);
-	}
-
-	BN_DIGIT(c, i + b->dmax - 1) = carry;
-}
-
-/* c[] = a[] * b[] */
-static void bn_mul_ex(struct LITE_BIGNUM *c,
-		const struct LITE_BIGNUM *a, int a_len,
-		const struct LITE_BIGNUM *b)
-{
-	int i;
-	uint32_t carry = 0;
-
-	memset(c->d, 0, bn_size(c));
-	for (i = 0; i < a_len; i++) {
-		BN_DIGIT(c, i + b->dmax - 1) = carry;
-		carry = bn_mul_add(c, BN_DIGIT(a, i), b, i);
-	}
-
-	BN_DIGIT(c, i + b->dmax - 1) = carry;
-}
-
-static int bn_div_word_ex(struct LITE_BIGNUM *q,
-		struct LITE_BIGNUM *r,
-		const struct LITE_BIGNUM *u, int m,
-		uint32_t div)
-{
-	uint32_t rem = 0;
-	int i;
-
-	for (i = m - 1; i >= 0; --i) {
-		uint64_t tmp = ((uint64_t)rem << 32) + BN_DIGIT(u, i);
-		uint32_t qd = tmp / div;
-
-		BN_DIGIT(q, i) = qd;
-		rem = tmp - (uint64_t)qd * div;
-	}
-
-	if (r != NULL)
-		BN_DIGIT(r, 0) = rem;
-
-	return 1;
-}
-
-/*
- * Knuth's long division.
- *
- * Returns 0 on error.
- * |u| >= |v|
- * v[n-1] must not be 0
- * r gets |v| digits written to.
- * q gets |u| - |v| + 1 digits written to.
- */
-static int bn_div_ex(struct LITE_BIGNUM *q,
-		struct LITE_BIGNUM *r,
-		const struct LITE_BIGNUM *u, int m,
-		const struct LITE_BIGNUM *v, int n)
-{
-	uint32_t vtop;
-	int s, i, j;
-	uint32_t vn[RSA_MAX_WORDS]; /* Normalized v */
-	uint32_t un[RSA_MAX_WORDS + 1]; /* Normalized u */
-
-	if (m < n || n <= 0)
-		return 0;
-
-	vtop = BN_DIGIT(v, n - 1);
-
-	if (vtop == 0)
-		return 0;
-
-	if (n == 1)
-		return bn_div_word_ex(q, r, u, m, vtop);
-
-	/* Compute shift factor to make v have high bit set */
-	s = 0;
-	while ((vtop & 0x80000000) == 0) {
-		s = s + 1;
-		vtop = vtop << 1;
-	}
-
-	/* Normalize u and v into un and vn.
-	 * Note un always gains a leading digit
-	 */
-	if (s != 0) {
-		for (i = n - 1; i > 0; i--)
-			vn[i] = (BN_DIGIT(v, i) << s) |
-				(BN_DIGIT(v, i - 1) >> (32 - s));
-		vn[0] = BN_DIGIT(v, 0) << s;
-
-		un[m] = BN_DIGIT(u, m - 1) >> (32 - s);
-		for (i = m - 1; i > 0; i--)
-			un[i] = (BN_DIGIT(u, i) << s) |
-			  (BN_DIGIT(u, i - 1) >> (32 - s));
-		un[0] = BN_DIGIT(u, 0) << s;
-	} else {
-		for (i = 0; i < n; ++i)
-			vn[i] = BN_DIGIT(v, i);
-		for (i = 0; i < m; ++i)
-			un[i] = BN_DIGIT(u, i);
-		un[m] = 0;
-	}
-
-	/* Main loop, reducing un digit by digit */
-	for (j = m - n; j >= 0; j--) {
-		uint32_t qd;
-		int64_t t, k;
-
-		/* Estimate quotient digit */
-		if (un[j + n] == vn[n - 1]) {
-			/* Maxed out */
-			qd = 0xFFFFFFFF;
-		} else {
-			/* Fine tune estimate */
-			uint64_t rhat = ((uint64_t)un[j + n] << 32) +
-				un[j + n - 1];
-
-			qd = rhat / vn[n - 1];
-			rhat = rhat - (uint64_t)qd * vn[n - 1];
-			while ((rhat >> 32) == 0 &&
-				(uint64_t)qd * vn[n - 2] >
-					(rhat << 32) + un[j + n - 2]) {
-				qd = qd - 1;
-				rhat = rhat + vn[n - 1];
-			}
-		}
-
-		/* Multiply and subtract */
-		k = 0;
-		for (i = 0; i < n; i++) {
-			uint64_t p = (uint64_t)qd * vn[i];
-
-			t = un[i + j] - k - (p & 0xFFFFFFFF);
-			un[i + j] = t;
-			k = (p >> 32) - (t >> 32);
-		}
-		t = un[j + n] - k;
-		un[j + n] = t;
-
-		/* If borrowed, add one back and adjust estimate */
-		if (t < 0) {
-			k = 0;
-			qd = qd - 1;
-			for (i = 0; i < n; i++) {
-				t = (uint64_t)un[i + j] + vn[i] + k;
-				un[i + j] = t;
-				k = t >> 32;
-			}
-			un[j + n] = un[j + n] + k;
-		}
-
-		BN_DIGIT(q, j) = qd;
-	}
-
-	if (r != NULL) {
-		/* Denormalize un into r */
-		if (s != 0) {
-			for (i = 0; i < n - 1; i++)
-				BN_DIGIT(r, i) = (un[i] >> s) |
-					(un[i + 1] << (32 - s));
-			BN_DIGIT(r, n - 1) = un[n - 1] >> s;
-		} else {
-			for (i = 0; i < n; i++)
-				BN_DIGIT(r, i) = un[i];
-		}
-	}
-
-	return 1;
-}
-
-static void bn_set_bn(struct LITE_BIGNUM *d, const struct LITE_BIGNUM *src,
-		size_t n)
-{
-	size_t i = 0;
-
-	for (; i < n && i < d->dmax; ++i)
-		BN_DIGIT(d, i) = BN_DIGIT(src, i);
-	for (; i < d->dmax; ++i)
-		BN_DIGIT(d, i) = 0;
-}
-
-static size_t bn_digits(const struct LITE_BIGNUM *a)
-{
-	size_t n = a->dmax - 1;
-
-	while (BN_DIGIT(a, n) == 0 && n)
-		--n;
-	return n + 1;
-}
-
-int DCRYPTO_bn_div(struct LITE_BIGNUM *quotient,
-		struct LITE_BIGNUM *remainder,
-		const struct LITE_BIGNUM *src,
-		const struct LITE_BIGNUM *divisor)
-{
-	int src_len = bn_digits(src);
-	int div_len = bn_digits(divisor);
-	int i, result;
-
-	if (src_len < div_len)
-		return 0;
-
-	result = bn_div_ex(quotient, remainder,
-			src, src_len,
-			divisor, div_len);
-
-	if (!result)
-		return 0;
-
-	/* 0-pad the destinations. */
-	for (i = src_len - div_len + 1; i < quotient->dmax; ++i)
-		BN_DIGIT(quotient, i) = 0;
-	if (remainder) {
-		for (i = div_len; i < remainder->dmax; ++i)
-			BN_DIGIT(remainder, i) = 0;
-	}
-
-	return result;
-}
-
-/*
- * Extended Euclid modular inverse.
- *
- * https://en.wikipedia.org/wiki/Extended_Euclidean_algorithm
- * #Computing_multiplicative_inverses_in_modular_structures:
-
- * function inverse(a, n)
- *  t := 0;     newt := 1;
- *  r := n;     newr := a;
- *  while newr ≠ 0
- *      quotient := r div newr
- *      (t, newt) := (newt, t - quotient * newt)
- *      (r, newr) := (newr, r - quotient * newr)
- *  if r > 1 then return "a is not invertible"
- *  if t < 0 then t := t + n
- *  return t
- */
-int bn_modinv_vartime(struct LITE_BIGNUM *dst, const struct LITE_BIGNUM *src,
-		const struct LITE_BIGNUM *mod)
-{
-	uint32_t R_buf[RSA_MAX_WORDS];
-	uint32_t nR_buf[RSA_MAX_WORDS];
-	uint32_t Q_buf[RSA_MAX_WORDS];
-
-	uint32_t nT_buf[RSA_MAX_WORDS + 1]; /* Can go negative, hence +1 */
-	uint32_t T_buf[RSA_MAX_WORDS + 1]; /* Can go negative */
-	uint32_t tmp_buf[2 * RSA_MAX_WORDS + 1]; /* needs to hold Q*nT */
-
-	struct LITE_BIGNUM R;
-	struct LITE_BIGNUM nR;
-	struct LITE_BIGNUM Q;
-	struct LITE_BIGNUM T;
-	struct LITE_BIGNUM nT;
-	struct LITE_BIGNUM tmp;
-
-	struct LITE_BIGNUM *pT = &T;
-	struct LITE_BIGNUM *pnT = &nT;
-	struct LITE_BIGNUM *pR = &R;
-	struct LITE_BIGNUM *pnR = &nR;
-	struct LITE_BIGNUM *bnswap;
-
-	int t_neg = 0;
-	int nt_neg = 0;
-	int iswap;
-
-	size_t r_len, nr_len;
-
-	bn_init(&R, R_buf, bn_size(mod));
-	bn_init(&nR, nR_buf, bn_size(mod));
-	bn_init(&Q, Q_buf, bn_size(mod));
-	bn_init(&T, T_buf, bn_size(mod) + sizeof(uint32_t));
-	bn_init(&nT, nT_buf, bn_size(mod) + sizeof(uint32_t));
-	bn_init(&tmp, tmp_buf, bn_size(mod) + sizeof(uint32_t));
-
-	r_len = bn_digits(mod);
-	nr_len = bn_digits(src);
-
-	BN_DIGIT(&nT, 0) = 1;              /* T = 0, nT = 1 */
-	bn_set_bn(&R, mod, r_len);         /* R = n */
-	bn_set_bn(&nR, src, nr_len);       /* nR = input */
-
-	/* Trim nR */
-	while (nr_len && BN_DIGIT(&nR, nr_len - 1) == 0)
-		--nr_len;
-
-	while (nr_len) {
-		size_t q_len = r_len - nr_len + 1;
-
-		/* (r, nr) = (nr, r % nr), q = r / nr */
-		if (!bn_div_ex(&Q, pR, pR, r_len, pnR, nr_len))
-			return 0;
-
-		/* swap R and nR */
-		r_len = nr_len;
-		bnswap = pR; pR = pnR; pnR = bnswap;
-
-		/* trim nR and Q */
-		while (nr_len && BN_DIGIT(pnR, nr_len - 1) == 0)
-			--nr_len;
-		while (q_len && BN_DIGIT(&Q, q_len - 1) == 0)
-			--q_len;
-
-		Q.dmax = q_len;
-
-		/* compute t - q*nt */
-		if (q_len == 1 && BN_DIGIT(&Q, 0) <= 2) {
-			/* Doing few direct subs is faster than mul + sub */
-			uint32_t n = BN_DIGIT(&Q, 0);
-
-			while (n--)
-				bn_signed_sub(pT, &t_neg, pnT, nt_neg);
-		} else {
-			/* Call bn_mul_ex with smallest operand first */
-			if (nt_neg) {
-				/* Negative numbers use all digits,
-				 * thus pnT is large
-				 */
-				bn_mul_ex(&tmp, &Q, q_len, pnT);
-			} else {
-				int nt_len = bn_digits(pnT);
-
-				if (q_len < nt_len)
-					bn_mul_ex(&tmp, &Q, q_len, pnT);
-				else
-					bn_mul_ex(&tmp, pnT, nt_len, &Q);
-			}
-			bn_signed_sub(pT, &t_neg, &tmp, nt_neg);
-		}
-
-		/* swap T and nT */
-		bnswap = pT; pT = pnT; pnT = bnswap;
-		iswap = t_neg; t_neg = nt_neg; nt_neg = iswap;
-	}
-
-	if (r_len != 1 || BN_DIGIT(pR, 0) != 1) {
-		/* gcd not 1; no direct inverse */
-		return 0;
-	}
-
-	if (t_neg)
-		bn_signed_add(pT, &t_neg, mod, 0);
-
-	bn_set_bn(dst, pT, bn_digits(pT));
-
-	return 1;
-}
-
-#define PRIME1 3
-
-/*
- * The array below is an encoding of the first 4096 primes, starting with
- * PRIME1. Using 4096 of the first primes results in at least 5% improvement
- * in running time over using the first 2048.
- *
- * Most byte entries in the array contain two sequential differentials between
- * two adjacent prime numbers, each differential halved (as the difference is
- * always even) and packed into 4 bits.
- *
- * If a halved differential value exceeds 0xf (and as such does not fit into 4
- * bits), a zero is placed in the array followed by the value literal (no
- * halving).
- *
- * If out of two consecutive differencials only the second one exceeds 0xf,
- * the first one still is put into the array in its own byte prepended by a
- * zero.
- */
-const uint8_t PRIME_DELTAS[] = {
-	  1,  18,  18,  18,  49,  50,  18,  51,  19,  33,  50,  52,
-	 33,  33,  39,  35,  21,  19,  50,  51,  21,  18,  22,  98,
-	 18,  49,  83,  51,  19,  33,  87,  33,  39,  53,  18,  52,
-	 51,  35,  66,  69,  21,  19,  35,  66,  18, 100,  36,  35,
-	 97, 147,  83,  49,  53,  51,  19,  50,  22,  81,  35,  49,
-	 98,  52,  84,  84,  51,  36,  50,  66, 117,  97,  81,  33,
-	 87,  33,  39,  33,  42,  36,  84,  35,  55,  35,  52,  54,
-	 35,  21,  19,  81,  81,  57,  33,  35,  52,  51, 177,  84,
-	 83,  52,  98,  51,  19, 101, 145,  35,  19,  33,  38,  19,
-	  0,  34,  51,  73,  87,  33,  35,  66,  19, 101,  18,  18,
-	 54, 100,  99,  35,  66,  66, 114,  49,  35,  19,  90,  50,
-	 28,  33,  86,  21,  67,  51, 147,  33, 101, 100, 135,  50,
-	 18,  21,  99,  57,  24,  27,  52,  50,  18,  67,  81,  87,
-	 83,  97,  33,  86,  24,  19,  33,  84, 156,  35,  72,  18,
-	 72,  18,  67,  50,  97, 179,  19,  35, 115,  33,  50,  54,
-	 51, 114,  54,  67,  45, 149,  66,  49,  59,  97, 132,  38,
-	117,  18,  67,  50,  18,  52,  33,  53,  21,  66, 117,  97,
-	 50,  24, 114,  52,  50, 148,  83,  52,  86, 114,  51,  30,
-	 21,  66, 114,  70,  54,  35, 165,  24, 210,  22,  50,  99,
-	 66,  75,  18,  22, 225,  51,  50,  49,  98,  97,  81, 129,
-	131, 168,  66,  18,  27,  70,  53,  18,  49,  53,  22,  81,
-	 87,  50,  52,  51, 134,  18, 115,  36,  84,  51, 179,  21,
-	114,  57,  21, 114,  21, 114,  73,  35,  18,  49,  98, 171,
-	 97,  35,  49,  59,  19, 131,  97,  54, 129,  35, 114,  25,
-	197,  49,  81,  81,  83,  21,  21,  52, 245,  21,  67,  89,
-	 54,  97, 147,  35,  57,  21, 115,  33,  44,  22,  56,  67,
-	 57, 129,  35,  19,  53,  54, 105,  19,  41,  76,  33,  35,
-	 22,  39, 245,  54, 115,  86,  18,  52,  53,  18, 115,  50,
-	 49,  81, 134,  73,  35,  97,  51,  62,  55,  36,  84, 105,
-	 33,  44,  99,  24,  51, 117, 114, 243,  51,  67,  33,  99,
-	 33,  59,  49,  41,  18,  97,  50, 211,  50,  69,   0,  32,
-	129,  50,  18,  21, 115,  36,  83, 162,  19, 242,  69,  51,
-	 67,  98,  49,  50,  49,  81, 131, 162, 103, 227, 162, 148,
-	 50,  55,  51,  81,  86,  69,  21,  70,  92,  18,  67,  36,
-	149,  51,  19,  86,  21,  51,  52,  53,  49,  51,  53,  76,
-	 59,  25,  36,  95,  73,  33,  83,  19,  41,  70, 152,  49,
-	 99,  81,  81,  53, 114, 193, 129,  81,  90,  33,  36, 131,
-	 49, 104,  66,  63,  21,  19,  35,  52,  50,  99,  70,  39,
-	101, 195,  99,  27,  73,  83, 114,  19,  84,  50,  63, 117,
-	 22,  81, 129, 156, 147, 137,  49, 146,  49,  84,  83,  52,
-	 35,  21,  22,  35,  49,  98, 121,  35, 162,  67,  36,  39,
-	 50, 118,  33, 242, 195,  54, 103,  50,  18, 147, 100,  50,
-	 97, 111, 129,  59, 115,  86,  49,  36,  83,  60, 115,  36,
-	105,  81,  81,  35, 163,  39,  33,  39,  54, 197,  52,  81,
-	242,  49,  98, 115,   0,  34, 100,  53,  18, 165,  72,  21,
-	114,  22,  56,  52,  36,  35,  67,  54,  50,  51,  73,  42,
-	 38,  21,  49,  86,  18, 163, 243,  36,  86,  49, 225,  50,
-	 24,  97,  53,  76,  99, 147,  39,  50, 100,  54,  35,  99,
-	 97, 138,  33,  89,  66, 114,  19, 179, 115,  53,  49,  81,
-	 33, 177,  35,  54,  55,  86,  52,   0,   4,   0,  36, 118,
-	 50,  49,  99, 104,  21,  75,  22,  50,  57,  22,  50, 100,
-	 54,  35,  99,  22,  98, 115, 131,  21,  73,   0,   6,   0,
-	 34,  30,  27,  49,  86,  19,  36, 179,  21,  66,  52,  38,
-	150, 162,  51,  66,  24,  97,  84,  81,  35, 118, 180, 225,
-	 42,  33,  39,  86,  22, 129, 228, 180,  35,  55,  36,  99,
-	 50, 162, 145,  99,  35, 121,  84,   0,  10,   0,  32,  53,
-	 51,  19, 131,  22,  62,  21,  72,  52,  53, 202,  81,  81,
-	 98,  58,  33, 105,  81,  81,  42, 141,  36,  50,  99,  70,
-	 99,  36, 177, 135,  83, 102, 115,  42,  38,  49,  51, 132,
-	177, 228,  50, 162, 108, 162,  69,  24,  22,   0,  12,   0,
-	 34,  18,  54,  51,  67,  33,  60,  42,  83,  55,  35,  49,
-	 99,  81,  83, 162, 210,  19, 177, 194,  49,  35, 195,  66,
-	  0,   2,   0,  34,  52, 134,  21,  21,  52,  36, 107,  55,
-	 45,  33, 101,  66,  70,  39,  56,  52,  35,  52,  53,  97,
-	 51, 132,  51, 101,  19, 146,  51,  54, 148,  53,  73,  39,
-	 57,  84,  86,  19, 102,   0,  36,  35,  66,  49,  41,  99,
-	 67,  50, 145,  33, 194,  51, 127,  50,  54,  58,  36,  36,
-	 51,  47,  21, 100,  84, 195,  98, 114,  49, 231, 129,  99,
-	 42,  83,  51,  69, 103,  87, 135,  87,  56,  52,  56, 165,
-	 19,  33,  38,  21,  19, 179,  18, 148,  84, 177,  89, 114,
-	 18, 145,  35,  69,  31,  47,  21,  25,  41,  55,  81,  42,
-	  0,  36,  50,  55,  42,  87, 179,  31, 101, 145,  39,  59,
-	145,  99,  36,  36,  53,  22, 149, 120, 114,  51,  19,  33,
-	225, 227,  18,  55,  38, 120, 114,  52,  50,  51,  52,  36,
-	 39, 132,  50, 100, 129,  84,  35, 211,  84,  35, 103, 242,
-	123,  70,  35,  69,  55,  83,  21, 102, 115,  57,  83,  73,
-	 35,  19,  81,  84,  51,  81, 149,  22,  35,  69, 103,  98,
-	 69,  51, 162, 120, 117,  69,  97, 147, 101,  97,  33,  99,
-	 36,   0,   4,   0,  44,  33,  33,  86,  51, 114,  51,  52,
-	  0,   6,   0,  36, 146,  49,  99,  51,  39, 182,  25,  83,
-	220,  33,  33,  39,  35,  52, 134,   0,   2,   0,  42,  33,
-	 44,  51,  25,  39,  62, 151,  53,  97,  54, 243,  35,  55,
-	 33, 194,  51, 213, 147,  67,  63,  38,  97, 129,  50, 105,
-	 19,  45,  99,  98, 204,  99,  22, 228,  35,  97, 147,  35,
-	 58, 129,  51, 149,  49,  36,  51, 200,  52,  83, 123,  72,
-	 49,  98,  27,  73,   0,  34,  19, 146,  51,  69,  73,  50,
-	 18,  72,  22,  99, 146,  51,  49,  54,  90, 105,  35,  24,
-	 21, 114, 241,  86,  28,  56,  69,  22, 179,  24, 165,  22,
-	105,  86,  49,  81,  53, 145,  99,  35,  28, 225,  33,  81,
-	134,  75,  19,  33,  83, 166,  84,  99,  51,  41,  18, 105,
-	 22,  50,  24, 102, 114,  73,  38, 115,  50,  67,  42, 101,
-	114,  24,  22, 242,  60, 172,  84, 101,  99, 102,  52, 135,
-	 50,   0,   6,   0,  36, 165, 246,  18,  30, 103,  59,  66,
-	147, 121,  35,  19,   0,  34, 145, 131, 145, 194,  19,  99,
-	101,  67, 134,  69,   0,  14,   0,  40,  49,  50, 103,  33,
-	 33,  36,  53,  51,  19,  51,  99, 197,  21,  54,  51, 115,
-	  0,   6,   0,  52, 163,  81,  84,  86,  97,  50, 120,  70,
-	 59,  21,  67, 177, 179,  69, 102,  21,  54,  18, 117,  19,
-	146, 100, 150,  51,  35,  55,  33, 102,  35, 153,  97, 134,
-	 73,  93,  35,  67,  50,  21, 162,  52,  42,  81,   0,  34,
-	 18, 193, 102,  83,  22, 243, 104,  97, 185, 103,  81, 102,
-	 33,  35,  97, 137,   0,   2,   0,  40,  72,  52,  81,  41,
-	 69,  70,  41,  25,  81,  33,  36, 225,  59,  99, 121,  35,
-	 67,  53,  66,  25,  83, 171,  67, 242,  18, 147, 241,  36,
-	 50,  54,   0,  14,   0,  34, 115,  33,  50, 114,  19, 225,
-	 35,  69,  21,  21,  18, 241, 102,  89, 103,  81,  99,  83,
-	118,  39,  41,  21,  66,  69, 105, 148,  57, 135,  51,  87,
-	 35,  22,  98,  51,  97, 129,  99,  39,  50,  22, 146,   0,
-	 36, 150,  97,  33,  36,  98,   0,  36,  57,  22,  83, 108,
-	 67,  56,  97, 149, 165,  19, 146,   0,   2,   0,  40,  49,
-	129,  36, 149,  99,  21,  66,  54,  21, 148,  50, 162,   0,
-	  6,   0,  36,  49,  83, 195, 120,  57,  21, 165,  67,  35,
-	 21,  22,  33,  36,  83, 105, 118, 132,  56,  66,  19, 156,
-	149,  97,  39,  83,  51, 150,  30, 151, 134, 124, 107,  49,
-	 84,  33,  39,  99,  35, 114,  18, 243,  19,  81, 251,  18,
-	 52,  51, 134,  99,  66,  28,  98,  52,  51,  81,  54, 231,
-	 50, 100,  54,  35, 115, 101,  51,  67,  50,  18,  70,  39,
-	149,  24,  58,  53,  66,   0,  30,   0,  36, 100, 182,  19,
-	104,  51,  25,  45,  36, 149,  69,  55,  42, 185, 100, 230,
-	 51,  67, 108, 135,  39,  99,  86, 163,  36, 150, 149,  18,
-	165, 114,  49,  92, 145,  42, 135,  87,  50,  58,  53,  49,
-	 99, 245,  67,  35,   0,   8,   0,  40,  18,  22, 146,  52,
-	 83, 153,  22, 132,  50,  51,   0,   2,   0,  52, 114, 168,
-	 18,  54,  19, 102,  50, 117,  51, 117, 120,  67,  98,  75,
-	 49, 155,  49, 147, 135,  83,  97,  50,  73, 104,  18, 114,
-	 70, 111, 132,  33,  59, 100,  83,  51, 115, 149,  97,  81,
-	 45,  38,  66, 148,  87, 131,  52,  83,  67, 101, 165,  66,
-	109, 146, 105,  63,  52,  59,  97,  35,  49,  81,  35,  49,
-	 59, 147, 150,  70,  53,  97, 129,  81,  89,  58,  33,  59,
-	 51, 147, 118, 129,  51,  39,  98,  25,   0,  16,   0,  36,
-	 99, 126,  22,  54,  50,  24, 244, 195, 245,  25,  35, 100,
-	177,  59, 145,  81,  95,  30,  55, 131, 168,  19,   0,   4,
-	  0,  32,  33,  35,  22,  35,  54,  19,  35,  67,  42,   0,
-	  4,   0,  32,  84, 129, 177,  35,  67, 135,  41,  66, 163,
-	102,  53,  21,  22, 230, 145, 149,  69,   0,  48,  18,  52,
-	 81,  95,   0,   2,   0,  36,  53,  49, 146,  52, 135, 131,
-	114, 162,  49,  86,  19,  99,  50,  97,  50,  99,  66,  19,
-	149,  52,  99, 177,  54, 146, 115,  42,  56,  66,  75,  70,
-	 51, 134, 159,  66,  18,  61,  39, 203,  49,  53,  55,  51,
-	101,  49, 101, 100, 153,  83,  72,  51,  72, 162,  21,  21,
-	 99,  67,  90,  89, 210,  63,  18,  67, 102, 146,  75,  49,
-	  0,  12,   0,  34,  57,  99,  30, 120, 114, 118,  35,  49,
-	  0,  36,  35, 166, 195, 177, 137, 102, 145,  51,  50,  55,
-	 33, 180,  99,  83,  70, 150,  53,  27, 115,  50, 147, 171,
-	 22, 194, 153,  27,  18, 100, 101, 114,  25,   0,  16,   0,
-	 38,  51,  54,  83, 100,  50,  55, 243,  84, 179,  70,  81,
-	 81,  53,  21, 105, 163,  36, 179,  63,  55,  54,  99,  81,
-	 95,  24,  66,  19, 146,  19,  45,  36,  53,  18,  52,  35,
-	246,  19,  50, 171,  66,  18,   0,  72,  66,  75,  18, 117,
-	 18, 163,  89,  58, 131,  67,  42, 107,  18,  22,  89,  27,
-	 57, 241,  87,  84,   0,  16,   0,  50,  53,  69,  99, 145,
-	179,  18,  52,  51,  89,  27,  24, 117,  49, 101, 162, 115,
-	  0,   4,   0,  36,  18,  54,  18, 118,  50,  49,  50, 165,
-	 21,  54,  28, 102,  51,  44,  18, 193,  50,  52, 131,  21,
-	103,   0,   6,   0,  34,  55,  50,  31, 180,  35,  66,  30,
-	 19,  45, 155,  19, 131,  24,  97,  98,  51, 117,  52,  98,
-	145,  84, 131,  63,  21, 145,  84,  36, 108,   0,  40,  22,
-	 83,  97,  98,  18,  57, 118,  50, 127,  36,  84,  53, 148,
-	 39, 131,  66,  49,  81,  98,  18,  52,  35,   0,  32, 197,
-	 73,  81,  53,  18, 147,  97, 129, 179,  52, 146, 150,  67,
-	 42,  63, 182,  19, 146,   0,  62,  33,  99,  81, 102, 225,
-	 39, 179,  19,  53, 114,  21,  52,  87,  83,  22, 185,  69,
-	150,  22,  38,  21,  19, 147,   0,   6,   0,  34,  49,  98,
-	 57, 145, 131,  52,  53, 148,  84,  81,  41, 214, 177,  33,
-	179,  55, 131, 165,  97,   0,  18,   0,  42,  44,  19,  86,
-	 19,  84,  35, 102,  66,  54, 250,  60,  53,  97,  90,  51,
-	 38, 117, 150,  67,  98, 117,  22, 248,  22,  50,  18,  61,
-	 41,  18,  55,   0,  54,   0,   6,   0,  52,  24,  51, 109,
-	 33,  59,  49, 102,  53, 145, 102,  89,  99,  67,  83,  66,
-	 18, 172,  51,  87,  81, 179, 117, 210, 148, 102,  86,  52,
-	131,  67,  59,  21, 165,   0,   6,   0,  44, 147,  81,  35,
-	114, 210,  22,  84,  36,  98, 100, 180,  53, 147,  52,  54,
-	 36, 149,  99,  97,  50,  24, 102, 117, 115,  86,  22,  50,
-	 49,  98, 211, 147,  83,  25,  84,  45,  90,  56, 166,  84,
-	 81, 131, 165, 162, 241,  36, 129, 146,  19,  89, 103, 147,
-	138,  50,  67,  35, 100,  81,  99,  33,  53,  24, 103,  83,
-	 67, 225,  57,   0,  30,   0,  34,  24,  97, 152,  52,  84,
-	 84,   0,  10,   0,  44,  51,  42,  33,  39, 228,  56, 127,
-	 63,  39,  83,  52,  41,  99,  27, 100,  54,  39,  35,  18,
-	154,  56,   0,  38, 129,  35,   0,   2,   0,  40,   0,  42,
-	114,  49, 197,  49, 149,  97, 129,  56,  52,  33,  83,  69,
-	 25, 132, 105,  99, 101,  51,
-};
-
-static uint32_t bn_mod_word16(const struct LITE_BIGNUM *p, uint16_t word)
-{
-	int i;
-	uint32_t rem = 0;
-
-	for (i = p->dmax - 1; i >= 0; i--) {
-		rem = ((rem << 16) |
-			((BN_DIGIT(p, i) >> 16) & 0xFFFFUL)) % word;
-		rem = ((rem << 16) | (BN_DIGIT(p, i) & 0xFFFFUL)) % word;
-	}
-
-	return rem;
-}
-
-static uint32_t bn_mod_f4(const struct LITE_BIGNUM *d)
-{
-	int i = bn_size(d) - 1;
-	const uint8_t *p = (const uint8_t *) (d->d);
-	uint32_t rem = 0;
-
-	for (; i >= 0; --i) {
-		uint32_t q = RSA_F4 * (rem >> 8);
-
-		if (rem < q)
-			q -= RSA_F4;
-		rem <<= 8;
-		rem |= p[i];
-		rem -= q;
-	}
-
-	if (rem >= RSA_F4)
-		rem -= RSA_F4;
-
-	return rem;
-}
-
-#define bn_is_even(b) !bn_is_bit_set((b), 0)
-/* From HAC Fact 4.48 (ii), the following number of
- * rounds suffice for ~2^145 confidence.  Each additional
- * round provides about another k/100 bits of confidence. */
-#define ROUNDS_1024 7
-#define ROUNDS_512  15
-#define ROUNDS_384  22
-
-/* Miller-Rabin from HAC, algorithm 4.24. */
-static int bn_probable_prime(const struct LITE_BIGNUM *p)
-{
-	int j;
-	int s = 0;
-
-	uint32_t ONE_buf = 1;
-	uint8_t r_buf[RSA_MAX_BYTES / 2];
-	uint8_t A_buf[RSA_MAX_BYTES / 2];
-	uint8_t y_buf[RSA_MAX_BYTES / 2];
-
-	struct LITE_BIGNUM ONE;
-	struct LITE_BIGNUM r;
-	struct LITE_BIGNUM A;
-	struct LITE_BIGNUM y;
-
-	const int rounds = bn_bits(p) >= 1024 ? ROUNDS_1024 :
-			bn_bits(p) >= 512 ? ROUNDS_512 :
-			ROUNDS_384;
-
-	/* Failsafe: update rounds table above to support smaller primes. */
-	if (bn_bits(p) < 384)
-		return 0;
-
-	if (bn_size(p) > sizeof(r_buf))
-		return 0;
-
-	DCRYPTO_bn_wrap(&ONE, &ONE_buf, sizeof(ONE_buf));
-	DCRYPTO_bn_wrap(&r, r_buf, bn_size(p));
-	bn_copy(&r, p);
-
-	/* r * (2 ^ s) = p - 1 */
-	bn_sub(&r, &ONE);
-	while (bn_is_even(&r)) {
-		bn_rshift(&r, 0, 0);
-		s++;
-	}
-
-	DCRYPTO_bn_wrap(&A, A_buf, bn_size(p));
-	DCRYPTO_bn_wrap(&y, y_buf, bn_size(p));
-	for (j = 0; j < rounds; j++) {
-		int i;
-
-		/* pick random A, such that A < p */
-		rand_bytes(A_buf, bn_size(&A));
-		for (i = A.dmax - 1; i >= 0; i--) {
-			while (BN_DIGIT(&A, i) > BN_DIGIT(p, i))
-				BN_DIGIT(&A, i) = rand();
-			if (BN_DIGIT(&A, i) < BN_DIGIT(p, i))
-				break;
-		}
-
-		/* y = a ^ r mod p */
-		bn_modexp(&y, &A, &r, p);
-		if (bn_eq(&y, &ONE))
-			continue;
-		bn_add(&y, &ONE);
-		if (bn_eq(&y, p))
-			continue;
-		bn_sub(&y, &ONE);
-
-		/* y = y ^ 2 mod p */
-		for (i = 0; i < s - 1; i++) {
-			bn_copy(&A, &y);
-			bn_modexp_word(&y, &A, 2, p);
-
-			if (bn_eq(&y, &ONE))
-				return 0;
-
-			bn_add(&y, &ONE);
-			if (bn_eq(&y, p)) {
-				bn_sub(&y, &ONE);
-				break;
-			}
-			bn_sub(&y, &ONE);
-		}
-		bn_add(&y, &ONE);
-		if (!bn_eq(&y, p))
-			return 0;
-	}
-
-	return 1;
-}
-
-/* #define PRINT_PRIMES to enable printing predefined prime numbers' set. */
-static void print_primes(uint16_t prime)
-{
-#ifdef PRINT_PRIMES
-	static uint16_t num_per_line;
-	static uint16_t max_printed;
-
-	if (prime <=  max_printed)
-		return;
-
-	if (!(num_per_line++ % 8)) {
-		if (num_per_line == 1)
-			ccprintf("Prime numbers:");
-		ccprintf("\n");
-		cflush();
-	}
-	max_printed = prime;
-	ccprintf(" %6d", prime);
-#endif
-}
-
-int DCRYPTO_bn_generate_prime(struct LITE_BIGNUM *p)
-{
-	int i;
-	int j;
-	/* Using a sieve size of 2048-bits results in a failure rate
-	 * of ~0.5% @ 1024-bit candidates.  The failure rate rises to ~6%
-	 * if the sieve size is halved. */
-	uint8_t composites_buf[256];
-	struct LITE_BIGNUM composites;
-	uint16_t prime = PRIME1;
-
-	/* Set top two bits, as well as LSB. */
-	bn_set_bit(p, 0);
-	bn_set_bit(p, bn_bits(p) - 1);
-	bn_set_bit(p, bn_bits(p) - 2);
-
-	/* Save on trial division by marking known composites. */
-	bn_init(&composites, composites_buf, sizeof(composites_buf));
-	for (i = 0; i < ARRAY_SIZE(PRIME_DELTAS); i++) {
-		uint16_t rem;
-		uint8_t unpacked_deltas[2];
-		uint8_t packed_deltas = PRIME_DELTAS[i];
-		int k;
-		int m;
-
-		if (packed_deltas) {
-			unpacked_deltas[0] = (packed_deltas >> 4) << 1;
-			unpacked_deltas[1] = (packed_deltas & 0xf) << 1;
-			m = 2;
-		} else {
-			i += 1;
-			unpacked_deltas[0] = PRIME_DELTAS[i];
-			m = 1;
-		}
-
-		for (k = 0; k < m; k++) {
-			prime += unpacked_deltas[k];
-			print_primes(prime);
-			rem = bn_mod_word16(p, prime);
-			/* Skip marking odd offsets (i.e. even candidates). */
-			for (j = (rem == 0) ? 0 : prime - rem;
-			     j < bn_bits(&composites) << 1;
-			     j += prime) {
-				if ((j & 1) == 0)
-					bn_set_bit(&composites, j >> 1);
-			}
-		}
-	}
-
-	/* composites now marked, apply Miller-Rabin to prime candidates. */
-	j = 0;
-	for (i = 0; i < bn_bits(&composites); i++) {
-		uint32_t diff_buf;
-		struct LITE_BIGNUM diff;
-
-		if (bn_is_bit_set(&composites, i))
-			continue;
-
-		/* Recover increment from the composites sieve. */
-		diff_buf = (i << 1) - j;
-		j = (i << 1);
-		DCRYPTO_bn_wrap(&diff, &diff_buf, sizeof(diff_buf));
-		bn_add(p, &diff);
-		/* Make sure prime will work with F4 public exponent. */
-		if (bn_mod_f4(p) >= 2) {
-			if (bn_probable_prime(p))
-				return 1;
-		}
-	}
-
-	always_memset(composites_buf, 0, sizeof(composites_buf));
-	return 0;
-}
diff --git a/chip/g/dcrypto/compare.c b/chip/g/dcrypto/compare.c
deleted file mode 100644
index db6193752b..0000000000
--- a/chip/g/dcrypto/compare.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "dcrypto.h"
-
-/* Constant time comparator. */
-int DCRYPTO_equals(const void *a, const void *b, size_t len)
-{
-	size_t i;
-	const uint8_t *pa = a;
-	const uint8_t *pb = b;
-	uint8_t diff = 0;
-
-	for (i = 0; i < len; i++)
-		diff |= pa[i] ^ pb[i];
-
-	return !diff;
-}
diff --git a/chip/g/dcrypto/dcrypto.h b/chip/g/dcrypto/dcrypto.h
deleted file mode 100644
index 1de0d63b03..0000000000
--- a/chip/g/dcrypto/dcrypto.h
+++ /dev/null
@@ -1,444 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * Crypto wrapper library for the g chip.
- */
-#ifndef __EC_CHIP_G_DCRYPTO_DCRYPTO_H
-#define __EC_CHIP_G_DCRYPTO_DCRYPTO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if defined(TEST_FUZZ) || !defined(TEST_BUILD)
-
-#include "internal.h"
-
-#include "crypto_api.h"
-
-#include <stddef.h>
-
-#include "cryptoc/hmac.h"
-
-enum cipher_mode {
-	CIPHER_MODE_ECB = 0, /* NIST SP 800-38A */
-	CIPHER_MODE_CTR = 1, /* NIST SP 800-38A */
-	CIPHER_MODE_CBC = 2, /* NIST SP 800-38A */
-	CIPHER_MODE_GCM = 3  /* NIST SP 800-38D */
-};
-
-enum encrypt_mode {
-	DECRYPT_MODE = 0,
-	ENCRYPT_MODE = 1
-};
-
-enum hashing_mode {
-	HASH_SHA1 = 0,
-	HASH_SHA256 = 1,
-	HASH_SHA384 = 2,  /* Only supported for PKCS#1 signing */
-	HASH_SHA512 = 3,  /* Only supported for PKCS#1 signing */
-	HASH_NULL = 4  /* Only supported for PKCS#1 signing */
-};
-
-/*
- * AES implementation, based on a hardware AES block.
- * FIPS Publication 197, The Advanced Encryption Standard (AES)
- */
-#define AES256_BLOCK_CIPHER_KEY_SIZE       32
-
-int DCRYPTO_aes_init(const uint8_t *key, uint32_t key_len, const uint8_t *iv,
-		enum cipher_mode c_mode, enum encrypt_mode e_mode);
-int DCRYPTO_aes_block(const uint8_t *in, uint8_t *out);
-
-void DCRYPTO_aes_write_iv(const uint8_t *iv);
-void DCRYPTO_aes_read_iv(uint8_t *iv);
-
-/* AES-CTR-128/192/256
- * NIST Special Publication 800-38A
- */
-int DCRYPTO_aes_ctr(uint8_t *out, const uint8_t *key, uint32_t key_bits,
-		const uint8_t *iv, const uint8_t *in, size_t in_len);
-
-/* AES-GCM-128/192/256
- * NIST Special Publication 800-38D, IV is provided externally
- * Caller should use IV length according to section 8.2 of SP 800-38D
- * And choose appropriate IV construction method, constrain number
- * of invocations according to section 8.3 of SP 800-38D
- */
-struct GCM_CTX {
-	union {
-		uint32_t d[4];
-		uint8_t c[16];
-	} block, Ej0;
-
-	uint64_t aad_len;
-	uint64_t count;
-	size_t remainder;
-};
-
-/* Initialize the GCM context structure. */
-void DCRYPTO_gcm_init(struct GCM_CTX *ctx, uint32_t key_bits,
-		const uint8_t *key, const uint8_t *iv, size_t iv_len);
-/* Additional authentication data to include in the tag calculation. */
-void DCRYPTO_gcm_aad(struct GCM_CTX *ctx, const uint8_t *aad_data, size_t len);
-/* Encrypt & decrypt return the number of bytes written to out
- * (always an integral multiple of 16), or -1 on error.  These functions
- * may be called repeatedly with incremental data.
- *
- * NOTE: if in_len is not a integral multiple of 16, then out_len must
- * be atleast in_len - (in_len % 16) + 16 bytes.
- */
-int DCRYPTO_gcm_encrypt(struct GCM_CTX *ctx, uint8_t *out, size_t out_len,
-			const uint8_t *in, size_t in_len);
-int DCRYPTO_gcm_decrypt(struct GCM_CTX *ctx, uint8_t *out, size_t out_len,
-			const uint8_t *in, size_t in_len);
-/* Encrypt & decrypt a partial final block, if any.  These functions
- * return the number of bytes written to out (<= 15), or -1 on error.
- */
-int DCRYPTO_gcm_encrypt_final(struct GCM_CTX *ctx,
-			uint8_t *out, size_t out_len);
-int DCRYPTO_gcm_decrypt_final(struct GCM_CTX *ctx,
-			uint8_t *out, size_t out_len);
-/* Compute the tag over AAD + encrypt or decrypt data, and return the
- * number of bytes written to tag.  Returns -1 on error.
- */
-int DCRYPTO_gcm_tag(struct GCM_CTX *ctx, uint8_t *tag, size_t tag_len);
-/* Cleanup secrets. */
-void DCRYPTO_gcm_finish(struct GCM_CTX *ctx);
-
-/* AES-CMAC-128
- * NIST Special Publication 800-38B, RFC 4493
- * K: 128-bit key, M: message, len: number of bytes in M
- * Writes 128-bit tag to T; returns 0 if an error is encountered and 1
- * otherwise.
- */
-int DCRYPTO_aes_cmac(const uint8_t *K, const uint8_t *M, const uint32_t len,
-		uint32_t T[4]);
-/* key: 128-bit key, M: message, len: number of bytes in M,
- *    T: tag to be verified
- * Returns 1 if the tag is correct and 0 otherwise.
- */
-int DCRYPTO_aes_cmac_verify(const uint8_t *key, const uint8_t *M, const int len,
-		const uint32_t T[4]);
-
-/*
- * SHA implementation.  This abstraction is backed by either a
- * software or hardware implementation.
- *
- * There could be only a single hardware SHA context in progress. The init
- * functions will try using the HW context, if available, unless 'sw_required'
- * is TRUE, in which case there will be no attempt to use the hardware for
- * this particular hashing session.
- */
-void DCRYPTO_SHA1_init(SHA_CTX *ctx, uint32_t sw_required);
-/*  SHA256/384/512 FIPS 180-4
- */
-void DCRYPTO_SHA256_init(LITE_SHA256_CTX *ctx, uint32_t sw_required);
-void DCRYPTO_SHA384_init(LITE_SHA384_CTX *ctx);
-void DCRYPTO_SHA512_init(LITE_SHA512_CTX *ctx);
-const uint8_t *DCRYPTO_SHA1_hash(const void *data, uint32_t n,
-				uint8_t *digest);
-const uint8_t *DCRYPTO_SHA256_hash(const void *data, uint32_t n,
-				   uint8_t *digest);
-const uint8_t *DCRYPTO_SHA384_hash(const void *data, uint32_t n,
-				   uint8_t *digest);
-const uint8_t *DCRYPTO_SHA512_hash(const void *data, uint32_t n,
-				   uint8_t *digest);
-/*
- *  HMAC. FIPS 198-1
- */
-void DCRYPTO_HMAC_SHA256_init(LITE_HMAC_CTX *ctx, const void *key,
-			unsigned int len);
-const uint8_t *DCRYPTO_HMAC_final(LITE_HMAC_CTX *ctx);
-
-/*
- * BIGNUM utility methods.
- */
-void DCRYPTO_bn_wrap(struct LITE_BIGNUM *b, void *buf, size_t len);
-
-/*
- *  RSA.
- */
-
-/* Largest supported key size for signing / encryption: 2048-bits.
- * Verification is a special case and supports 4096-bits (signing /
- * decryption could also support 4k-RSA, but is disabled since support
- * is not required, and enabling support would result in increased
- * stack usage for all key sizes.)
- */
-#define RSA_BYTES_2K    256
-#define RSA_BYTES_4K    512
-#define RSA_WORDS_2K    (RSA_BYTES_2K / sizeof(uint32_t))
-#define RSA_WORDS_4K    (RSA_BYTES_4K / sizeof(uint32_t))
-#ifndef RSA_MAX_BYTES
-#define RSA_MAX_BYTES   RSA_BYTES_2K
-#endif
-#define RSA_MAX_WORDS   (RSA_MAX_BYTES / sizeof(uint32_t))
-#define RSA_F4          65537
-
-struct RSA {
-	uint32_t e;
-	struct LITE_BIGNUM N;
-	struct LITE_BIGNUM d;
-};
-
-enum padding_mode {
-	PADDING_MODE_PKCS1 = 0,
-	PADDING_MODE_OAEP  = 1,
-	PADDING_MODE_PSS = 2,
-	/* USE OF NULL PADDING IS NOT RECOMMENDED.
-	 * SUPPORT EXISTS AS A REQUIREMENT FOR TPM2 OPERATION. */
-	PADDING_MODE_NULL  = 3
-};
-
-/* RSA support, FIPS PUB 186-4 *
- * Calculate r = m ^ e mod N
- */
-int DCRYPTO_rsa_encrypt(struct RSA *rsa, uint8_t *out, uint32_t *out_len,
-			const uint8_t *in, uint32_t in_len,
-			enum padding_mode padding, enum hashing_mode hashing,
-			const char *label);
-
-/* Calculate r = m ^ d mod N
- * return 0 if error
- */
-int DCRYPTO_rsa_decrypt(struct RSA *rsa, uint8_t *out, uint32_t *out_len,
-			const uint8_t *in, const uint32_t in_len,
-			enum padding_mode padding, enum hashing_mode hashing,
-			const char *label);
-
-/* Calculate r = m ^ d mod N
- * return 0 if error
- */
-int DCRYPTO_rsa_sign(struct RSA *rsa, uint8_t *out, uint32_t *out_len,
-		const uint8_t *in, const uint32_t in_len,
-		enum padding_mode padding, enum hashing_mode hashing);
-
-/* Calculate r = m ^ e mod N
- * return 0 if error
- */
-int DCRYPTO_rsa_verify(const struct RSA *rsa, const uint8_t *digest,
-		uint32_t digest_len, const uint8_t *sig,
-		const uint32_t sig_len,	enum padding_mode padding,
-		enum hashing_mode hashing);
-
-/* Calculate n = p * q, d = e ^ -1 mod phi. */
-int DCRYPTO_rsa_key_compute(struct LITE_BIGNUM *N, struct LITE_BIGNUM *d,
-			struct LITE_BIGNUM *p, struct LITE_BIGNUM *q,
-			uint32_t e);
-
-/*
- *  EC.
- */
-
-/* DCRYPTO_p256_base_point_mul sets {out_x,out_y} = nG, where n is < the
- * order of the group.
- */
-int DCRYPTO_p256_base_point_mul(p256_int *out_x, p256_int *out_y,
-				const p256_int *n);
-
-/* DCRYPTO_p256_point_mul sets {out_x,out_y} = n*{in_x,in_y}, where n is <
- * the order of the group.
- */
-int DCRYPTO_p256_point_mul(p256_int *out_x, p256_int *out_y,
-			const p256_int *n, const p256_int *in_x,
-			const p256_int *in_y);
-/*
- * Key selection based on FIPS-186-4, section B.4.2 (Key Pair
- * Generation by Testing Candidates).
- * Produce uniform private key from seed.
- * If x or y is NULL, the public key part is not computed.
- * Returns !0 on success.
- */
-int DCRYPTO_p256_key_from_bytes(p256_int *x, p256_int *y, p256_int *d,
-				const uint8_t bytes[P256_NBYTES]);
-
-
-/* P256 based integration encryption (DH+AES128+SHA256).
- * Not FIPS 140-2 compliant, not used other than for tests
- * Authenticated data may be provided, where the first auth_data_len
- * bytes of in will be authenticated but not encrypted. *
- * Supports in-place encryption / decryption. *
- * The output format is:
- * 0x04 || PUBKEY || AUTH_DATA || AES128_CTR(PLAINTEXT) ||
- *         HMAC_SHA256(AUTH_DATA || CIPHERTEXT)
- */
-size_t DCRYPTO_ecies_encrypt(
-	void *out, size_t out_len, const void *in, size_t in_len,
-	size_t auth_data_len, const uint8_t *iv,
-	const p256_int *pub_x, const p256_int *pub_y,
-	const uint8_t *salt, size_t salt_len,
-	const uint8_t *info, size_t info_len);
-size_t DCRYPTO_ecies_decrypt(
-	void *out, size_t out_len, const void *in, size_t in_len,
-	size_t auth_data_len, const uint8_t *iv,
-	const p256_int *d,
-	const uint8_t *salt, size_t salt_len,
-	const uint8_t *info, size_t info_len);
-
-/*
- * HKDF as per RFC 5869. Mentioned as conforming NIST SP 800-56C Rev.1
- * [RFC 5869] specifies a version of the above extraction-then-expansion
- * key-derivation procedure using HMAC for both the extraction and expansion
- * steps.
- */
-int DCRYPTO_hkdf(uint8_t *OKM, size_t OKM_len,
-		const uint8_t *salt, size_t salt_len,
-		const uint8_t *IKM, size_t IKM_len,
-		const uint8_t *info, size_t info_len);
-
-/*
- *  BN.
- */
-
-/* Apply Miller-Rabin test for prime candidate p.
- * Returns 1 if test passed, 0 otherwise
- */
-int DCRYPTO_bn_generate_prime(struct LITE_BIGNUM *p);
-void DCRYPTO_bn_wrap(struct LITE_BIGNUM *b, void *buf, size_t len);
-void DCRYPTO_bn_mul(struct LITE_BIGNUM *c, const struct LITE_BIGNUM *a,
-		const struct LITE_BIGNUM *b);
-int DCRYPTO_bn_div(struct LITE_BIGNUM *quotient, struct LITE_BIGNUM *remainder,
-		const struct LITE_BIGNUM *input,
-		const struct LITE_BIGNUM *divisor);
-
-/*
- * ASN.1 DER
- */
-size_t DCRYPTO_asn1_sigp(uint8_t *buf, const p256_int *r, const p256_int *s);
-size_t DCRYPTO_asn1_pubp(uint8_t *buf, const p256_int *x, const p256_int *y);
-
-/*
- *  X509.
- */
-/* DCRYPTO_x509_verify verifies that the provided X509 certificate was issued
- * by the specified certifcate authority.
- *
- * cert is a pointer to a DER encoded X509 certificate, as specified
- * in https://tools.ietf.org/html/rfc5280#section-4.1.  In ASN.1
- * notation, the certificate has the following structure:
- *
- *   Certificate  ::=  SEQUENCE  {
- *        tbsCertificate       TBSCertificate,
- *        signatureAlgorithm   AlgorithmIdentifier,
- *        signatureValue       BIT STRING  }
- *
- *   TBSCertificate  ::=  SEQUENCE  { }
- *   AlgorithmIdentifier  ::=  SEQUENCE  { }
- *
- * where signatureValue = SIGN(HASH(tbsCertificate)), with SIGN and
- * HASH specified by signatureAlgorithm.
- * Accepts only certs with OID: sha256WithRSAEncryption:
- * 30 0d 06 09 2a 86 48 86 f7 0d 01 01 0b 05 00
- */
-int DCRYPTO_x509_verify(const uint8_t *cert, size_t len,
-			const struct RSA *ca_pub_key);
-
-/* Generate U2F Certificate and sign it
- * Use ECDSA with NIST P-256 curve, and SHA2-256 digest
- * @param d: key handle, used for NIST SP 800-90A HMAC DRBG
- * @param pk_x, pk_y: public key
- * @param serial: serial number for certificate
- * @param name: certificate issuer and subject
- * @param cert: output buffer for certificate
- * @param n: max size of cert
- */
-int DCRYPTO_x509_gen_u2f_cert_name(const p256_int *d, const p256_int *pk_x,
-				   const p256_int *pk_y, const p256_int *serial,
-				   const char *name, uint8_t *cert,
-				   const int n);
-
-/* Generate U2F Certificate with DCRYPTO_x509_gen_u2f_cert_name
- * Providing certificate issuer as BOARD or U2F
- * @param d: key handle, used for NIST SP 800-90A HMAC DRBG
- * @param pk_x, pk_y: public key
- * @param serial: serial number for certificate
- * @param name: certificate issuer and subject
- * @param cert: output buffer for certificate
- * @param n: max size of cert
- */
-int DCRYPTO_x509_gen_u2f_cert(const p256_int *d, const p256_int *pk_x,
-			const p256_int *pk_y, const p256_int *serial,
-			uint8_t *cert, const int n);
-
-/*
- * Memory related functions.
- */
-int DCRYPTO_equals(const void *a, const void *b, size_t len);
-
-/*
- * Key-ladder and application key related functions.
- */
-enum dcrypto_appid {
-	RESERVED = 0,
-	NVMEM = 1,
-	U2F_ATTEST = 2,
-	U2F_ORIGIN = 3,
-	U2F_WRAP = 4,
-	PERSO_AUTH = 5,
-	PINWEAVER = 6,
-	/* This enum value should not exceed 7. */
-};
-
-struct APPKEY_CTX {
-#ifdef TEST_FUZZ
-	uint8_t unused_for_cxx_compatibility;
-#endif
-};
-
-int DCRYPTO_ladder_compute_frk2(size_t major_fw_version, uint8_t *frk2);
-int DCRYPTO_ladder_random(void *output);
-void DCRYPTO_ladder_revoke(void);
-
-int DCRYPTO_appkey_init(enum dcrypto_appid id, struct APPKEY_CTX *ctx);
-void DCRYPTO_appkey_finish(struct APPKEY_CTX *ctx);
-int DCRYPTO_appkey_derive(enum dcrypto_appid appid, const uint32_t input[8],
-			  uint32_t output[8]);
-
-/* Number of bytes in the salt object. */
-#define DCRYPTO_CIPHER_SALT_SIZE 16
-BUILD_ASSERT(DCRYPTO_CIPHER_SALT_SIZE == CIPHER_SALT_SIZE);
-
-/*
- * Encrypt/decrypt a flat blob.
- *
- * Encrypt or decrypt the input buffer, and write the correspondingly
- * ciphered output to out.  The number of bytes produced is equal to
- * the number of input bytes.  Note that the input and output pointers
- * MUST be word-aligned.
- *
- * This API is expected to be applied to a single contiguous region.
-
- * WARNING: A given salt/"in" pair MUST be unique, i.e. re-using a
- * salt with a logically different input buffer is catastrophic.  An
- * example of a suitable salt is one that is derived from "in", e.g. a
- * digest of the input data.
- *
- * @param appid the application-id of the calling context.
- * @param salt pointer to a unique value to be associated with this blob,
- *	       used for derivation of the proper IV, the size of the value
- *	       is as defined by DCRYPTO_CIPHER_SALT_SIZE above.
- * @param out Destination pointer where to write plaintext / ciphertext.
- * @param in  Source pointer where to read ciphertext / plaintext.
- * @param len Number of bytes to read from in / write to out.
- * @return non-zero on success, and zero otherwise.
- */
-int DCRYPTO_app_cipher(enum dcrypto_appid appid, const void *salt,
-		void *out, const void *in, size_t len);
-
-#endif  /*  ^^^^^^^^^^^^^^^^^^^^^  !TEST_BUILD   */
-/*
- * Query whether Key Ladder is enabled.
- *
- * @return 1 if Key Ladder is enabled, and 0 otherwise.
- */
-int DCRYPTO_ladder_is_enabled(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* ! __EC_CHIP_G_DCRYPTO_DCRYPTO_H */
diff --git a/chip/g/dcrypto/dcrypto_bn.c b/chip/g/dcrypto/dcrypto_bn.c
deleted file mode 100644
index b8f8fef4f4..0000000000
--- a/chip/g/dcrypto/dcrypto_bn.c
+++ /dev/null
@@ -1,1496 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#include "dcrypto.h"
-#include "internal.h"
-#include "registers.h"
-#include "trng.h"
-
-/* Firmware blob for crypto accelerator */
-
-/* AUTO-GENERATED.  DO NOT MODIFY. */
-/* clang-format off */
-static const uint32_t IMEM_dcrypto_bn[] = {
-/* @0x0: function tag[1] { */
-#define CF_tag_adr 0
-0xf8000001,	/* sigini #1 */
-/* } */
-/* @0x1: function d0inv[14] { */
-#define CF_d0inv_adr 1
-0x4c000000,	/* xor r0, r0, r0 */
-0x80000001,	/* movi r0.0l, #1 */
-0x7c740000,	/* mov r29, r0 */
-0x05100008,	/* loop #256 ( */
-0x5807bc00,	/* mul128 r1, r28l, r29l */
-0x588bbc00,	/* mul128 r2, r28u, r29l */
-0x50044110,	/* add r1, r1, r2 << 128 */
-0x590bbc00,	/* mul128 r2, r28l, r29u */
-0x50044110,	/* add r1, r1, r2 << 128 */
-0x40040100,	/* and r1, r1, r0 */
-0x44743d00,	/* or r29, r29, r1 */
-0x50000000,	/* add r0, r0, r0 */
-/*		   ) */
-0x5477bf00,	/* sub r29, r31, r29 */
-0x0c000000,	/* ret */
-/* } */
-/* @0xf: function selcxSub[25] { */
-#define CF_selcxSub_adr 15
-0x97800100,	/* ldrfp r1 */
-0x95800000,	/* lddmp r0 */
-0x99100000,	/* strnd r4 */
-0x5013e400,	/* add r4, r4, r31 */
-0x1000101e,	/* bl selcxSub_invsel */
-0x528c8402,	/* addcx r3, r4, r4 << 16 */
-0x0600c007,	/* loop *6 ( */
-0x8c081800,	/* ld *2, *0++ */
-0x7c8c0000,	/* ldr *3, *0 */
-0x7c800400,	/* ldr *0, *4 */
-0x54906200,	/* subb r4, r2, r3 */
-0x990c0000,	/* strnd r3 */
-0x660c4401,	/* sellx r3, r4, r2 */
-0x7ca00200,	/* ldr *0++, *2 */
-/*		   ) */
-0x0c000000,	/* ret */
-/*selcxSub_invsel: */
-0x528c8402,	/* addcx r3, r4, r4 << 16 */
-0x0600c007,	/* loop *6 ( */
-0x8c081800,	/* ld *2, *0++ */
-0x7c8c0000,	/* ldr *3, *0 */
-0x7c800400,	/* ldr *0, *4 */
-0x54906200,	/* subb r4, r2, r3 */
-0x990c0000,	/* strnd r3 */
-0x660c8201,	/* sellx r3, r2, r4 */
-0x7ca00200,	/* ldr *0++, *2 */
-/*		   ) */
-0x0c000000,	/* ret */
-/* } */
-/* @0x28: function computeRR[41] { */
-#define CF_computeRR_adr 40
-0x4c7fff00,	/* xor r31, r31, r31 */
-0x84004000,	/* ldi r0, [#0] */
-0x95800000,	/* lddmp r0 */
-0x4c0c6300,	/* xor r3, r3, r3 */
-0x800cffff,	/* movi r3.0l, #65535 */
-0x40040398,	/* and r1, r3, r0 >> 192 */
-0x480c6000,	/* not r3, r3 */
-0x400c0300,	/* and r3, r3, r0 */
-0x500c2301,	/* add r3, r3, r1 << 8 */
-0x94800300,	/* ldlc r3 */
-0x80040005,	/* movi r1.0l, #5 */
-0x81040003,	/* movi r1.2l, #3 */
-0x81840002,	/* movi r1.3l, #2 */
-0x82040004,	/* movi r1.4l, #4 */
-0x97800100,	/* ldrfp r1 */
-0x4c0c6300,	/* xor r3, r3, r3 */
-0x0600c001,	/* loop *6 ( */
-0x7ca00200,	/* ldr *0++, *2 */
-/*		   ) */
-0x560c1f00,	/* subx r3, r31, r0 */
-0x0800000f,	/* call &selcxSub */
-0x06000010,	/* loop *0 ( */
-0x97800100,	/* ldrfp r1 */
-0x560c6300,	/* subx r3, r3, r3 */
-0x0600c003,	/* loop *6 ( */
-0x7c8c0000,	/* ldr *3, *0 */
-0x52884200,	/* addcx r2, r2, r2 */
-0x7ca00300,	/* ldr *0++, *3 */
-/*		   ) */
-0x0800000f,	/* call &selcxSub */
-0x97800100,	/* ldrfp r1 */
-0x95800000,	/* lddmp r0 */
-0x560c6300,	/* subx r3, r3, r3 */
-0x0600c003,	/* loop *6 ( */
-0x8c081800,	/* ld *2, *0++ */
-0x7c8c0800,	/* ldr *3, *0++ */
-0x5e804300,	/* cmpbx r3, r2 */
-/*		   ) */
-0x0800000f,	/* call &selcxSub */
-0xfc000000,	/* nop */
-/*		   ) */
-0x97800100,	/* ldrfp r1 */
-0x0600c001,	/* loop *6 ( */
-0x90680800,	/* st *0++, *2++ */
-/*		   ) */
-0x0c000000,	/* ret */
-/* } */
-/* @0x51: function dmXd0[9] { */
-#define CF_dmXd0_adr 81
-0x586f3e00,	/* mul128 r27, r30l, r25l */
-0x59eb3e00,	/* mul128 r26, r30u, r25u */
-0x58df3e00,	/* mul128 r23, r30u, r25l */
-0x506efb10,	/* add r27, r27, r23 << 128 */
-0x50eafa90,	/* addc r26, r26, r23 >> 128 */
-0x595f3e00,	/* mul128 r23, r30l, r25u */
-0x506efb10,	/* add r27, r27, r23 << 128 */
-0x50eafa90,	/* addc r26, r26, r23 >> 128 */
-0x0c000000,	/* ret */
-/* } */
-/* @0x5a: function dmXa[9] { */
-#define CF_dmXa_adr 90
-0x586c5e00,	/* mul128 r27, r30l, r2l */
-0x59e85e00,	/* mul128 r26, r30u, r2u */
-0x58dc5e00,	/* mul128 r23, r30u, r2l */
-0x506efb10,	/* add r27, r27, r23 << 128 */
-0x50eafa90,	/* addc r26, r26, r23 >> 128 */
-0x595c5e00,	/* mul128 r23, r30l, r2u */
-0x506efb10,	/* add r27, r27, r23 << 128 */
-0x50eafa90,	/* addc r26, r26, r23 >> 128 */
-0x0c000000,	/* ret */
-/* } */
-/* @0x63: function mma_sub_cx[23] { */
-#define CF_mma_sub_cx_adr 99
-0x99700000,	/* strnd r28 */
-0x5073fc00,	/* add r28, r28, r31 */
-0x10001070,	/* bl mma_invsel */
-0x52f39c02,	/* addcx r28, r28, r28 << 16 */
-0x0600c007,	/* loop *6 ( */
-0x8c141800,	/* ld *5, *0++ */
-0x7c900000,	/* ldr *4, *0 */
-0x54f71e00,	/* subb r29, r30, r24 */
-0x99600000,	/* strnd r24 */
-0x7c800500,	/* ldr *0, *5 */
-0x6663dd01,	/* sellx r24, r29, r30 */
-0x7ca00500,	/* ldr *0++, *5 */
-/*		   ) */
-0x0c000000,	/* ret */
-/*mma_invsel: */
-0x52f39c02,	/* addcx r28, r28, r28 << 16 */
-0x0600c007,	/* loop *6 ( */
-0x8c141800,	/* ld *5, *0++ */
-0x7c900000,	/* ldr *4, *0 */
-0x54f71e00,	/* subb r29, r30, r24 */
-0x99600000,	/* strnd r24 */
-0x7c800500,	/* ldr *0, *5 */
-0x6663be01,	/* sellx r24, r30, r29 */
-0x7ca00500,	/* ldr *0++, *5 */
-/*		   ) */
-0x0c000000,	/* ret */
-/* } */
-/* @0x7a: function mma[39] { */
-#define CF_mma_adr 122
-0x8204001e,	/* movi r1.4l, #30 */
-0x82840018,	/* movi r1.5l, #24 */
-0x97800100,	/* ldrfp r1 */
-0x8c101b00,	/* ld *4, *3++ */
-0x0800005a,	/* call &dmXa */
-0x7c940800,	/* ldr *5, *0++ */
-0x507b1b00,	/* add r30, r27, r24 */
-0x50f7fa00,	/* addc r29, r26, r31 */
-0x7c640300,	/* mov r25, r3 */
-0x08000051,	/* call &dmXd0 */
-0x7c641b00,	/* mov r25, r27 */
-0x7c701a00,	/* mov r28, r26 */
-0x7c601e00,	/* mov r24, r30 */
-0x8c101800,	/* ld *4, *0++ */
-0x08000051,	/* call &dmXd0 */
-0x506f1b00,	/* add r27, r27, r24 */
-0x50f3fa00,	/* addc r28, r26, r31 */
-0x0600e00e,	/* loop *7 ( */
-0x8c101b00,	/* ld *4, *3++ */
-0x0800005a,	/* call &dmXa */
-0x7c940800,	/* ldr *5, *0++ */
-0x506f1b00,	/* add r27, r27, r24 */
-0x50ebfa00,	/* addc r26, r26, r31 */
-0x5063bb00,	/* add r24, r27, r29 */
-0x50f7fa00,	/* addc r29, r26, r31 */
-0x8c101800,	/* ld *4, *0++ */
-0x08000051,	/* call &dmXd0 */
-0x506f1b00,	/* add r27, r27, r24 */
-0x50ebfa00,	/* addc r26, r26, r31 */
-0x52639b00,	/* addx r24, r27, r28 */
-0x7ca80500,	/* ldr *2++, *5 */
-0x52f3fa00,	/* addcx r28, r26, r31 */
-/*		   ) */
-0x52e39d00,	/* addcx r24, r29, r28 */
-0x7ca80500,	/* ldr *2++, *5 */
-0x95800000,	/* lddmp r0 */
-0x97800100,	/* ldrfp r1 */
-0x08000063,	/* call &mma_sub_cx */
-0xfc000000,	/* nop */
-0x0c000000,	/* ret */
-/* } */
-/* @0xa1: function setupPtrs[11] { */
-#define CF_setupPtrs_adr 161
-0x847c4000,	/* ldi r31, [#0] */
-0x4c7fff00,	/* xor r31, r31, r31 */
-0x95800000,	/* lddmp r0 */
-0x94800000,	/* ldlc r0 */
-0x7c041f00,	/* mov r1, r31 */
-0x80040004,	/* movi r1.0l, #4 */
-0x80840003,	/* movi r1.1l, #3 */
-0x81040004,	/* movi r1.2l, #4 */
-0x81840002,	/* movi r1.3l, #2 */
-0x97800100,	/* ldrfp r1 */
-0x0c000000,	/* ret */
-/* } */
-/* @0xac: function mulx[19] { */
-#define CF_mulx_adr 172
-0x84004000,	/* ldi r0, [#0] */
-0x080000a1,	/* call &setupPtrs */
-0x8c041100,	/* ld *1, *1 */
-0x7c081f00,	/* mov r2, r31 */
-0x0600c001,	/* loop *6 ( */
-0x7ca80300,	/* ldr *2++, *3 */
-/*		   ) */
-0x97800100,	/* ldrfp r1 */
-0x0600c004,	/* loop *6 ( */
-0x8c0c1c00,	/* ld *3, *4++ */
-0x95000000,	/* stdmp r0 */
-0x0800007a,	/* call &mma */
-0x95800000,	/* lddmp r0 */
-/*		   ) */
-0x97800100,	/* ldrfp r1 */
-0x95800000,	/* lddmp r0 */
-0x0600c001,	/* loop *6 ( */
-0x90740800,	/* st *0++, *5++ */
-/*		   ) */
-0x97800100,	/* ldrfp r1 */
-0x95800000,	/* lddmp r0 */
-0x0c000000,	/* ret */
-/* } */
-/* @0xbf: function mm1_sub_cx[22] { */
-#define CF_mm1_sub_cx_adr 191
-0x990c0000,	/* strnd r3 */
-0x500fe300,	/* add r3, r3, r31 */
-0x100010cc,	/* bl mm1_invsel */
-0x528c6302,	/* addcx r3, r3, r3 << 16 */
-0x0600c006,	/* loop *6 ( */
-0x8c041800,	/* ld *1, *0++ */
-0x7c8c0800,	/* ldr *3, *0++ */
-0x548c6200,	/* subb r3, r2, r3 */
-0x66084301,	/* sellx r2, r3, r2 */
-0x90740300,	/* st *3, *5++ */
-0xfc000000,	/* nop */
-/*		   ) */
-0x0c000000,	/* ret */
-0xfc000000,	/* nop */
-/*mm1_invsel: */
-0x528c6302,	/* addcx r3, r3, r3 << 16 */
-0x0600c006,	/* loop *6 ( */
-0x8c041800,	/* ld *1, *0++ */
-0x7c8c0800,	/* ldr *3, *0++ */
-0x548c6200,	/* subb r3, r2, r3 */
-0x66086201,	/* sellx r2, r2, r3 */
-0x90740300,	/* st *3, *5++ */
-0xfc000000,	/* nop */
-/*		   ) */
-0x0c000000,	/* ret */
-/* } */
-/* @0xd5: function mul1_exp[23] { */
-#define CF_mul1_exp_adr 213
-0x8c041100,	/* ld *1, *1 */
-0x7c081f00,	/* mov r2, r31 */
-0x0600c001,	/* loop *6 ( */
-0x7ca80300,	/* ldr *2++, *3 */
-/*		   ) */
-0x97800100,	/* ldrfp r1 */
-0x80080001,	/* movi r2.0l, #1 */
-0x0600c003,	/* loop *6 ( */
-0x95800000,	/* lddmp r0 */
-0x0800007a,	/* call &mma */
-0x7c081f00,	/* mov r2, r31 */
-/*		   ) */
-0x97800100,	/* ldrfp r1 */
-0x95800000,	/* lddmp r0 */
-0x56084200,	/* subx r2, r2, r2 */
-0x0600c003,	/* loop *6 ( */
-0x8c041800,	/* ld *1, *0++ */
-0x7c8c0800,	/* ldr *3, *0++ */
-0x5e804300,	/* cmpbx r3, r2 */
-/*		   ) */
-0x97800100,	/* ldrfp r1 */
-0x95800000,	/* lddmp r0 */
-0x080000bf,	/* call &mm1_sub_cx */
-0x97800100,	/* ldrfp r1 */
-0x95800000,	/* lddmp r0 */
-0x0c000000,	/* ret */
-/* } */
-/* @0xec: function mul1[4] { */
-#define CF_mul1_adr 236
-0x84004000,	/* ldi r0, [#0] */
-0x080000a1,	/* call &setupPtrs */
-0x080000d5,	/* call &mul1_exp */
-0x0c000000,	/* ret */
-/* } */
-/* @0xf0: function sqrx_exp[19] { */
-#define CF_sqrx_exp_adr 240
-0x84004020,	/* ldi r0, [#1] */
-0x95800000,	/* lddmp r0 */
-0x8c041100,	/* ld *1, *1 */
-0x7c081f00,	/* mov r2, r31 */
-0x0600c001,	/* loop *6 ( */
-0x7ca80300,	/* ldr *2++, *3 */
-/*		   ) */
-0x97800100,	/* ldrfp r1 */
-0x0600c004,	/* loop *6 ( */
-0x8c0c1c00,	/* ld *3, *4++ */
-0x95000000,	/* stdmp r0 */
-0x0800007a,	/* call &mma */
-0x95800000,	/* lddmp r0 */
-/*		   ) */
-0x97800100,	/* ldrfp r1 */
-0x95800000,	/* lddmp r0 */
-0x0600c001,	/* loop *6 ( */
-0x90740800,	/* st *0++, *5++ */
-/*		   ) */
-0x97800100,	/* ldrfp r1 */
-0x95800000,	/* lddmp r0 */
-0x0c000000,	/* ret */
-/* } */
-/* @0x103: function mulx_exp[14] { */
-#define CF_mulx_exp_adr 259
-0x84004040,	/* ldi r0, [#2] */
-0x95800000,	/* lddmp r0 */
-0x8c041100,	/* ld *1, *1 */
-0x7c081f00,	/* mov r2, r31 */
-0x0600c001,	/* loop *6 ( */
-0x7ca80300,	/* ldr *2++, *3 */
-/*		   ) */
-0x97800100,	/* ldrfp r1 */
-0x0600c004,	/* loop *6 ( */
-0x8c0c1c00,	/* ld *3, *4++ */
-0x95000000,	/* stdmp r0 */
-0x0800007a,	/* call &mma */
-0x95800000,	/* lddmp r0 */
-/*		   ) */
-0x97800100,	/* ldrfp r1 */
-0x0c000000,	/* ret */
-/* } */
-/* @0x111: function selOutOrC[30] { */
-#define CF_selOutOrC_adr 273
-0x990c0000,	/* strnd r3 */
-0x440c6300,	/* or r3, r3, r3 */
-0x10001122,	/* bl selOutOrC_invsel */
-0x508c6302,	/* addc r3, r3, r3 << 16 */
-0x0600c00a,	/* loop *6 ( */
-0x990c0000,	/* strnd r3 */
-0x99080000,	/* strnd r2 */
-0x8c041500,	/* ld *1, *5 */
-0x90540300,	/* st *3, *5 */
-0x7c8c0800,	/* ldr *3, *0++ */
-0x99000000,	/* strnd r0 */
-0x7c000200,	/* mov r0, r2 */
-0x99080000,	/* strnd r2 */
-0x64086001,	/* sell r2, r0, r3 */
-0x90740300,	/* st *3, *5++ */
-/*		   ) */
-0x0c000000,	/* ret */
-0xfc000000,	/* nop */
-/*selOutOrC_invsel: */
-0x508c6302,	/* addc r3, r3, r3 << 16 */
-0x0600c00a,	/* loop *6 ( */
-0x990c0000,	/* strnd r3 */
-0x99080000,	/* strnd r2 */
-0x8c041500,	/* ld *1, *5 */
-0x90540300,	/* st *3, *5 */
-0x7c8c0800,	/* ldr *3, *0++ */
-0x99000000,	/* strnd r0 */
-0x7c000200,	/* mov r0, r2 */
-0x99080000,	/* strnd r2 */
-0x64080301,	/* sell r2, r3, r0 */
-0x90740300,	/* st *3, *5++ */
-/*		   ) */
-0x0c000000,	/* ret */
-/* } */
-/* @0x12f: function modexp[35] { */
-#define CF_modexp_adr 303
-0x080000ac,	/* call &mulx */
-0x84004060,	/* ldi r0, [#3] */
-0x95800000,	/* lddmp r0 */
-0x54084200,	/* sub r2, r2, r2 */
-0x0600c004,	/* loop *6 ( */
-0xfc000000,	/* nop */
-0x8c0c1800,	/* ld *3, *0++ */
-0x54885f00,	/* subb r2, r31, r2 */
-0x90740300,	/* st *3, *5++ */
-/*		   ) */
-0xfc000000,	/* nop */
-0x7c081f00,	/* mov r2, r31 */
-0x8008ffff,	/* movi r2.0l, #65535 */
-0x400c0298,	/* and r3, r2, r0 >> 192 */
-0x48084000,	/* not r2, r2 */
-0x40080200,	/* and r2, r2, r0 */
-0x50086201,	/* add r2, r2, r3 << 8 */
-0x94800200,	/* ldlc r2 */
-0x0600000d,	/* loop *0 ( */
-0x080000f0,	/* call &sqrx_exp */
-0x08000103,	/* call &mulx_exp */
-0x84004060,	/* ldi r0, [#3] */
-0x95800000,	/* lddmp r0 */
-0x99080000,	/* strnd r2 */
-0x50084200,	/* add r2, r2, r2 */
-0x0600c004,	/* loop *6 ( */
-0x99080000,	/* strnd r2 */
-0x8c0c1400,	/* ld *3, *4 */
-0x50884200,	/* addc r2, r2, r2 */
-0x90700300,	/* st *3, *4++ */
-/*		   ) */
-0x08000111,	/* call &selOutOrC */
-0xfc000000,	/* nop */
-/*		   ) */
-0x84004060,	/* ldi r0, [#3] */
-0x95800000,	/* lddmp r0 */
-0x080000d5,	/* call &mul1_exp */
-0x0c000000,	/* ret */
-/* } */
-/* @0x152: function modexp_blinded[76] { */
-#define CF_modexp_blinded_adr 338
-0x080000ac,	/* call &mulx */
-0x84004060,	/* ldi r0, [#3] */
-0x95800000,	/* lddmp r0 */
-0x54084200,	/* sub r2, r2, r2 */
-0x0600c004,	/* loop *6 ( */
-0xfc000000,	/* nop */
-0x8c0c1800,	/* ld *3, *0++ */
-0x54885f00,	/* subb r2, r31, r2 */
-0x90740300,	/* st *3, *5++ */
-/*		   ) */
-0xfc000000,	/* nop */
-0x8c0c1900,	/* ld *3, *1++ */
-0x8c0c1100,	/* ld *3, *1 */
-0x521c5f90,	/* addx r7, r31, r2 >> 128 */
-0x590c4200,	/* mul128 r3, r2l, r2u */
-0x7c181f00,	/* mov r6, r31 */
-0x0600c011,	/* loop *6 ( */
-0x99080000,	/* strnd r2 */
-0x8c0c1400,	/* ld *3, *4 */
-0x58106200,	/* mul128 r4, r2l, r3l */
-0x59946200,	/* mul128 r5, r2u, r3u */
-0x58806200,	/* mul128 r0, r2u, r3l */
-0x50100410,	/* add r4, r4, r0 << 128 */
-0x50940590,	/* addc r5, r5, r0 >> 128 */
-0x59006200,	/* mul128 r0, r2l, r3u */
-0x50100410,	/* add r4, r4, r0 << 128 */
-0x50940590,	/* addc r5, r5, r0 >> 128 */
-0x5010c400,	/* add r4, r4, r6 */
-0x5097e500,	/* addc r5, r5, r31 */
-0x50088200,	/* add r2, r2, r4 */
-0x509be500,	/* addc r6, r5, r31 */
-0x5688e200,	/* subbx r2, r2, r7 */
-0x90700300,	/* st *3, *4++ */
-0x541ce700,	/* sub r7, r7, r7 */
-/*		   ) */
-0x7c080600,	/* mov r2, r6 */
-0x5688e200,	/* subbx r2, r2, r7 */
-0x90500300,	/* st *3, *4 */
-0xfc000000,	/* nop */
-0x84004060,	/* ldi r0, [#3] */
-0x7c081f00,	/* mov r2, r31 */
-0x8008ffff,	/* movi r2.0l, #65535 */
-0x400c0298,	/* and r3, r2, r0 >> 192 */
-0x48084000,	/* not r2, r2 */
-0x40080200,	/* and r2, r2, r0 */
-0x510c0301,	/* addi r3, r3, #1 */
-0x50086201,	/* add r2, r2, r3 << 8 */
-0x94800200,	/* ldlc r2 */
-0x06000019,	/* loop *0 ( */
-0x080000f0,	/* call &sqrx_exp */
-0x08000103,	/* call &mulx_exp */
-0x84004060,	/* ldi r0, [#3] */
-0x95800000,	/* lddmp r0 */
-0x99080000,	/* strnd r2 */
-0x54084200,	/* sub r2, r2, r2 */
-0x0600c004,	/* loop *6 ( */
-0x99080000,	/* strnd r2 */
-0x8c0c1400,	/* ld *3, *4 */
-0x50884200,	/* addc r2, r2, r2 */
-0x90700300,	/* st *3, *4++ */
-/*		   ) */
-0x99080000,	/* strnd r2 */
-0x8c0c1400,	/* ld *3, *4 */
-0x50884200,	/* addc r2, r2, r2 */
-0x90700300,	/* st *3, *4++ */
-0x0600c008,	/* loop *6 ( */
-0x99080000,	/* strnd r2 */
-0x8c041500,	/* ld *1, *5 */
-0x90540300,	/* st *3, *5 */
-0x7c8c0800,	/* ldr *3, *0++ */
-0x7c000200,	/* mov r0, r2 */
-0x99080000,	/* strnd r2 */
-0x64086008,	/* selc r2, r0, r3 */
-0x90740300,	/* st *3, *5++ */
-/*		   ) */
-0xfc000000,	/* nop */
-/*		   ) */
-0x84004060,	/* ldi r0, [#3] */
-0x95800000,	/* lddmp r0 */
-0x080000d5,	/* call &mul1_exp */
-0x0c000000,	/* ret */
-/* } */
-/* @0x19e: function modload[12] { */
-#define CF_modload_adr 414
-0x4c7fff00,	/* xor r31, r31, r31 */
-0x84004000,	/* ldi r0, [#0] */
-0x95800000,	/* lddmp r0 */
-0x94800000,	/* ldlc r0 */
-0x8000001c,	/* movi r0.0l, #28 */
-0x8080001d,	/* movi r0.1l, #29 */
-0x97800000,	/* ldrfp r0 */
-0x8c001000,	/* ld *0, *0 */
-0x08000001,	/* call &d0inv */
-0x90440100,	/* st *1, *1 */
-0x08000028,	/* call &computeRR */
-0x0c000000,	/* ret */
-/* } */
-#ifdef CONFIG_DCRYPTO_RSA_SPEEDUP
-/* @0x1aa: function selA0orC4[16] { */
-#define CF_selA0orC4_adr 426
-0x99000000,	/* strnd r0 */
-0x44000000,	/* or r0, r0, r0 */
-0x100011b4,	/* bl selA0orC4_invsel */
-0x50840002,	/* addc r1, r0, r0 << 16 */
-0x6458da01,	/* sell r22, r26, r6 */
-0x645cfb01,	/* sell r23, r27, r7 */
-0x64611c01,	/* sell r24, r28, r8 */
-0x64653d01,	/* sell r25, r29, r9 */
-0x0c000000,	/* ret */
-0xfc000000,	/* nop */
-/*selA0orC4_invsel: */
-0x50840002,	/* addc r1, r0, r0 << 16 */
-0x645b4601,	/* sell r22, r6, r26 */
-0x645f6701,	/* sell r23, r7, r27 */
-0x64638801,	/* sell r24, r8, r28 */
-0x6467a901,	/* sell r25, r9, r29 */
-0x0c000000,	/* ret */
-/* } */
-/* @0x1ba: function mul4[169] { */
-#define CF_mul4_adr 442
-0x58594600,	/* mul128 r22, r6l, r10l */
-0x59dd4600,	/* mul128 r23, r6u, r10u */
-0x58894600,	/* mul128 r2, r6u, r10l */
-0x50585610,	/* add r22, r22, r2 << 128 */
-0x50dc5790,	/* addc r23, r23, r2 >> 128 */
-0x59094600,	/* mul128 r2, r6l, r10u */
-0x50585610,	/* add r22, r22, r2 << 128 */
-0x50dc5790,	/* addc r23, r23, r2 >> 128 */
-0x58616700,	/* mul128 r24, r7l, r11l */
-0x59e56700,	/* mul128 r25, r7u, r11u */
-0x58896700,	/* mul128 r2, r7u, r11l */
-0x50605810,	/* add r24, r24, r2 << 128 */
-0x50e45990,	/* addc r25, r25, r2 >> 128 */
-0x59096700,	/* mul128 r2, r7l, r11u */
-0x50605810,	/* add r24, r24, r2 << 128 */
-0x50e45990,	/* addc r25, r25, r2 >> 128 */
-0x58698800,	/* mul128 r26, r8l, r12l */
-0x59ed8800,	/* mul128 r27, r8u, r12u */
-0x58898800,	/* mul128 r2, r8u, r12l */
-0x50685a10,	/* add r26, r26, r2 << 128 */
-0x50ec5b90,	/* addc r27, r27, r2 >> 128 */
-0x59098800,	/* mul128 r2, r8l, r12u */
-0x50685a10,	/* add r26, r26, r2 << 128 */
-0x50ec5b90,	/* addc r27, r27, r2 >> 128 */
-0x5871a900,	/* mul128 r28, r9l, r13l */
-0x59f5a900,	/* mul128 r29, r9u, r13u */
-0x5889a900,	/* mul128 r2, r9u, r13l */
-0x50705c10,	/* add r28, r28, r2 << 128 */
-0x50f45d90,	/* addc r29, r29, r2 >> 128 */
-0x5909a900,	/* mul128 r2, r9l, r13u */
-0x50705c10,	/* add r28, r28, r2 << 128 */
-0x50f45d90,	/* addc r29, r29, r2 >> 128 */
-0x58016600,	/* mul128 r0, r6l, r11l */
-0x59856600,	/* mul128 r1, r6u, r11u */
-0x58896600,	/* mul128 r2, r6u, r11l */
-0x50004010,	/* add r0, r0, r2 << 128 */
-0x50844190,	/* addc r1, r1, r2 >> 128 */
-0x59096600,	/* mul128 r2, r6l, r11u */
-0x50004010,	/* add r0, r0, r2 << 128 */
-0x50844190,	/* addc r1, r1, r2 >> 128 */
-0x505c1700,	/* add r23, r23, r0 */
-0x50e03800,	/* addc r24, r24, r1 */
-0x508fff00,	/* addc r3, r31, r31 */
-0x58014700,	/* mul128 r0, r7l, r10l */
-0x59854700,	/* mul128 r1, r7u, r10u */
-0x58894700,	/* mul128 r2, r7u, r10l */
-0x50004010,	/* add r0, r0, r2 << 128 */
-0x50844190,	/* addc r1, r1, r2 >> 128 */
-0x59094700,	/* mul128 r2, r7l, r10u */
-0x50004010,	/* add r0, r0, r2 << 128 */
-0x50844190,	/* addc r1, r1, r2 >> 128 */
-0x505c1700,	/* add r23, r23, r0 */
-0x50e03800,	/* addc r24, r24, r1 */
-0x50e47900,	/* addc r25, r25, r3 */
-0x508fff00,	/* addc r3, r31, r31 */
-0x58018600,	/* mul128 r0, r6l, r12l */
-0x59858600,	/* mul128 r1, r6u, r12u */
-0x58898600,	/* mul128 r2, r6u, r12l */
-0x50004010,	/* add r0, r0, r2 << 128 */
-0x50844190,	/* addc r1, r1, r2 >> 128 */
-0x59098600,	/* mul128 r2, r6l, r12u */
-0x50004010,	/* add r0, r0, r2 << 128 */
-0x50844190,	/* addc r1, r1, r2 >> 128 */
-0x50601800,	/* add r24, r24, r0 */
-0x50e43900,	/* addc r25, r25, r1 */
-0x508fe300,	/* addc r3, r3, r31 */
-0x58014800,	/* mul128 r0, r8l, r10l */
-0x59854800,	/* mul128 r1, r8u, r10u */
-0x58894800,	/* mul128 r2, r8u, r10l */
-0x50004010,	/* add r0, r0, r2 << 128 */
-0x50844190,	/* addc r1, r1, r2 >> 128 */
-0x59094800,	/* mul128 r2, r8l, r10u */
-0x50004010,	/* add r0, r0, r2 << 128 */
-0x50844190,	/* addc r1, r1, r2 >> 128 */
-0x50601800,	/* add r24, r24, r0 */
-0x50e43900,	/* addc r25, r25, r1 */
-0x50e87a00,	/* addc r26, r26, r3 */
-0x508fff00,	/* addc r3, r31, r31 */
-0x5801a600,	/* mul128 r0, r6l, r13l */
-0x5985a600,	/* mul128 r1, r6u, r13u */
-0x5889a600,	/* mul128 r2, r6u, r13l */
-0x50004010,	/* add r0, r0, r2 << 128 */
-0x50844190,	/* addc r1, r1, r2 >> 128 */
-0x5909a600,	/* mul128 r2, r6l, r13u */
-0x50004010,	/* add r0, r0, r2 << 128 */
-0x50844190,	/* addc r1, r1, r2 >> 128 */
-0x50641900,	/* add r25, r25, r0 */
-0x50e83a00,	/* addc r26, r26, r1 */
-0x508fe300,	/* addc r3, r3, r31 */
-0x58018700,	/* mul128 r0, r7l, r12l */
-0x59858700,	/* mul128 r1, r7u, r12u */
-0x58898700,	/* mul128 r2, r7u, r12l */
-0x50004010,	/* add r0, r0, r2 << 128 */
-0x50844190,	/* addc r1, r1, r2 >> 128 */
-0x59098700,	/* mul128 r2, r7l, r12u */
-0x50004010,	/* add r0, r0, r2 << 128 */
-0x50844190,	/* addc r1, r1, r2 >> 128 */
-0x50641900,	/* add r25, r25, r0 */
-0x50e83a00,	/* addc r26, r26, r1 */
-0x508fe300,	/* addc r3, r3, r31 */
-0x58014900,	/* mul128 r0, r9l, r10l */
-0x59854900,	/* mul128 r1, r9u, r10u */
-0x58894900,	/* mul128 r2, r9u, r10l */
-0x50004010,	/* add r0, r0, r2 << 128 */
-0x50844190,	/* addc r1, r1, r2 >> 128 */
-0x59094900,	/* mul128 r2, r9l, r10u */
-0x50004010,	/* add r0, r0, r2 << 128 */
-0x50844190,	/* addc r1, r1, r2 >> 128 */
-0x50641900,	/* add r25, r25, r0 */
-0x50e83a00,	/* addc r26, r26, r1 */
-0x508fe300,	/* addc r3, r3, r31 */
-0x58016800,	/* mul128 r0, r8l, r11l */
-0x59856800,	/* mul128 r1, r8u, r11u */
-0x58896800,	/* mul128 r2, r8u, r11l */
-0x50004010,	/* add r0, r0, r2 << 128 */
-0x50844190,	/* addc r1, r1, r2 >> 128 */
-0x59096800,	/* mul128 r2, r8l, r11u */
-0x50004010,	/* add r0, r0, r2 << 128 */
-0x50844190,	/* addc r1, r1, r2 >> 128 */
-0x50641900,	/* add r25, r25, r0 */
-0x50e83a00,	/* addc r26, r26, r1 */
-0x50ec7b00,	/* addc r27, r27, r3 */
-0x508fff00,	/* addc r3, r31, r31 */
-0x5801a700,	/* mul128 r0, r7l, r13l */
-0x5985a700,	/* mul128 r1, r7u, r13u */
-0x5889a700,	/* mul128 r2, r7u, r13l */
-0x50004010,	/* add r0, r0, r2 << 128 */
-0x50844190,	/* addc r1, r1, r2 >> 128 */
-0x5909a700,	/* mul128 r2, r7l, r13u */
-0x50004010,	/* add r0, r0, r2 << 128 */
-0x50844190,	/* addc r1, r1, r2 >> 128 */
-0x50681a00,	/* add r26, r26, r0 */
-0x50ec3b00,	/* addc r27, r27, r1 */
-0x508fe300,	/* addc r3, r3, r31 */
-0x58016900,	/* mul128 r0, r9l, r11l */
-0x59856900,	/* mul128 r1, r9u, r11u */
-0x58896900,	/* mul128 r2, r9u, r11l */
-0x50004010,	/* add r0, r0, r2 << 128 */
-0x50844190,	/* addc r1, r1, r2 >> 128 */
-0x59096900,	/* mul128 r2, r9l, r11u */
-0x50004010,	/* add r0, r0, r2 << 128 */
-0x50844190,	/* addc r1, r1, r2 >> 128 */
-0x50681a00,	/* add r26, r26, r0 */
-0x50ec3b00,	/* addc r27, r27, r1 */
-0x50f07c00,	/* addc r28, r28, r3 */
-0x50f7fd00,	/* addc r29, r29, r31 */
-0x5801a800,	/* mul128 r0, r8l, r13l */
-0x5985a800,	/* mul128 r1, r8u, r13u */
-0x5889a800,	/* mul128 r2, r8u, r13l */
-0x50004010,	/* add r0, r0, r2 << 128 */
-0x50844190,	/* addc r1, r1, r2 >> 128 */
-0x5909a800,	/* mul128 r2, r8l, r13u */
-0x50004010,	/* add r0, r0, r2 << 128 */
-0x50844190,	/* addc r1, r1, r2 >> 128 */
-0x506c1b00,	/* add r27, r27, r0 */
-0x50f03c00,	/* addc r28, r28, r1 */
-0x50f7fd00,	/* addc r29, r29, r31 */
-0x58018900,	/* mul128 r0, r9l, r12l */
-0x59858900,	/* mul128 r1, r9u, r12u */
-0x58898900,	/* mul128 r2, r9u, r12l */
-0x50004010,	/* add r0, r0, r2 << 128 */
-0x50844190,	/* addc r1, r1, r2 >> 128 */
-0x59098900,	/* mul128 r2, r9l, r12u */
-0x50004010,	/* add r0, r0, r2 << 128 */
-0x50844190,	/* addc r1, r1, r2 >> 128 */
-0x506c1b00,	/* add r27, r27, r0 */
-0x50f03c00,	/* addc r28, r28, r1 */
-0x50f7fd00,	/* addc r29, r29, r31 */
-0x0c000000,	/* ret */
-/* } */
-/* @0x263: function sqr4[117] { */
-#define CF_sqr4_adr 611
-0x5858c600,	/* mul128 r22, r6l, r6l */
-0x59dcc600,	/* mul128 r23, r6u, r6u */
-0x5888c600,	/* mul128 r2, r6u, r6l */
-0x50585610,	/* add r22, r22, r2 << 128 */
-0x50dc5790,	/* addc r23, r23, r2 >> 128 */
-0x50585610,	/* add r22, r22, r2 << 128 */
-0x50dc5790,	/* addc r23, r23, r2 >> 128 */
-0x5860e700,	/* mul128 r24, r7l, r7l */
-0x59e4e700,	/* mul128 r25, r7u, r7u */
-0x5888e700,	/* mul128 r2, r7u, r7l */
-0x50605810,	/* add r24, r24, r2 << 128 */
-0x50e45990,	/* addc r25, r25, r2 >> 128 */
-0x50605810,	/* add r24, r24, r2 << 128 */
-0x50e45990,	/* addc r25, r25, r2 >> 128 */
-0x58690800,	/* mul128 r26, r8l, r8l */
-0x59ed0800,	/* mul128 r27, r8u, r8u */
-0x58890800,	/* mul128 r2, r8u, r8l */
-0x50685a10,	/* add r26, r26, r2 << 128 */
-0x50ec5b90,	/* addc r27, r27, r2 >> 128 */
-0x50685a10,	/* add r26, r26, r2 << 128 */
-0x50ec5b90,	/* addc r27, r27, r2 >> 128 */
-0x58712900,	/* mul128 r28, r9l, r9l */
-0x59f52900,	/* mul128 r29, r9u, r9u */
-0x58892900,	/* mul128 r2, r9u, r9l */
-0x50705c10,	/* add r28, r28, r2 << 128 */
-0x50f45d90,	/* addc r29, r29, r2 >> 128 */
-0x50705c10,	/* add r28, r28, r2 << 128 */
-0x50f45d90,	/* addc r29, r29, r2 >> 128 */
-0x5800e600,	/* mul128 r0, r6l, r7l */
-0x5984e600,	/* mul128 r1, r6u, r7u */
-0x5888e600,	/* mul128 r2, r6u, r7l */
-0x50004010,	/* add r0, r0, r2 << 128 */
-0x50844190,	/* addc r1, r1, r2 >> 128 */
-0x5908e600,	/* mul128 r2, r6l, r7u */
-0x50004010,	/* add r0, r0, r2 << 128 */
-0x50844190,	/* addc r1, r1, r2 >> 128 */
-0x505c1700,	/* add r23, r23, r0 */
-0x50e03800,	/* addc r24, r24, r1 */
-0x508fff00,	/* addc r3, r31, r31 */
-0x505c1700,	/* add r23, r23, r0 */
-0x50e03800,	/* addc r24, r24, r1 */
-0x50e47900,	/* addc r25, r25, r3 */
-0x508fff00,	/* addc r3, r31, r31 */
-0x58010600,	/* mul128 r0, r6l, r8l */
-0x59850600,	/* mul128 r1, r6u, r8u */
-0x58890600,	/* mul128 r2, r6u, r8l */
-0x50004010,	/* add r0, r0, r2 << 128 */
-0x50844190,	/* addc r1, r1, r2 >> 128 */
-0x59090600,	/* mul128 r2, r6l, r8u */
-0x50004010,	/* add r0, r0, r2 << 128 */
-0x50844190,	/* addc r1, r1, r2 >> 128 */
-0x50601800,	/* add r24, r24, r0 */
-0x50e43900,	/* addc r25, r25, r1 */
-0x508fe300,	/* addc r3, r3, r31 */
-0x50601800,	/* add r24, r24, r0 */
-0x50e43900,	/* addc r25, r25, r1 */
-0x50e87a00,	/* addc r26, r26, r3 */
-0x508fff00,	/* addc r3, r31, r31 */
-0x58012600,	/* mul128 r0, r6l, r9l */
-0x59852600,	/* mul128 r1, r6u, r9u */
-0x58892600,	/* mul128 r2, r6u, r9l */
-0x50004010,	/* add r0, r0, r2 << 128 */
-0x50844190,	/* addc r1, r1, r2 >> 128 */
-0x59092600,	/* mul128 r2, r6l, r9u */
-0x50004010,	/* add r0, r0, r2 << 128 */
-0x50844190,	/* addc r1, r1, r2 >> 128 */
-0x50641900,	/* add r25, r25, r0 */
-0x50e83a00,	/* addc r26, r26, r1 */
-0x508fe300,	/* addc r3, r3, r31 */
-0x50641900,	/* add r25, r25, r0 */
-0x50e83a00,	/* addc r26, r26, r1 */
-0x508fe300,	/* addc r3, r3, r31 */
-0x58010700,	/* mul128 r0, r7l, r8l */
-0x59850700,	/* mul128 r1, r7u, r8u */
-0x58890700,	/* mul128 r2, r7u, r8l */
-0x50004010,	/* add r0, r0, r2 << 128 */
-0x50844190,	/* addc r1, r1, r2 >> 128 */
-0x59090700,	/* mul128 r2, r7l, r8u */
-0x50004010,	/* add r0, r0, r2 << 128 */
-0x50844190,	/* addc r1, r1, r2 >> 128 */
-0x50641900,	/* add r25, r25, r0 */
-0x50e83a00,	/* addc r26, r26, r1 */
-0x508fe300,	/* addc r3, r3, r31 */
-0x50641900,	/* add r25, r25, r0 */
-0x50e83a00,	/* addc r26, r26, r1 */
-0x50ec7b00,	/* addc r27, r27, r3 */
-0x508fff00,	/* addc r3, r31, r31 */
-0x58012700,	/* mul128 r0, r7l, r9l */
-0x59852700,	/* mul128 r1, r7u, r9u */
-0x58892700,	/* mul128 r2, r7u, r9l */
-0x50004010,	/* add r0, r0, r2 << 128 */
-0x50844190,	/* addc r1, r1, r2 >> 128 */
-0x59092700,	/* mul128 r2, r7l, r9u */
-0x50004010,	/* add r0, r0, r2 << 128 */
-0x50844190,	/* addc r1, r1, r2 >> 128 */
-0x50681a00,	/* add r26, r26, r0 */
-0x50ec3b00,	/* addc r27, r27, r1 */
-0x508fe300,	/* addc r3, r3, r31 */
-0x50681a00,	/* add r26, r26, r0 */
-0x50ec3b00,	/* addc r27, r27, r1 */
-0x50f07c00,	/* addc r28, r28, r3 */
-0x50f7fd00,	/* addc r29, r29, r31 */
-0x58012800,	/* mul128 r0, r8l, r9l */
-0x59852800,	/* mul128 r1, r8u, r9u */
-0x58892800,	/* mul128 r2, r8u, r9l */
-0x50004010,	/* add r0, r0, r2 << 128 */
-0x50844190,	/* addc r1, r1, r2 >> 128 */
-0x59092800,	/* mul128 r2, r8l, r9u */
-0x50004010,	/* add r0, r0, r2 << 128 */
-0x50844190,	/* addc r1, r1, r2 >> 128 */
-0x506c1b00,	/* add r27, r27, r0 */
-0x50f03c00,	/* addc r28, r28, r1 */
-0x50f7fd00,	/* addc r29, r29, r31 */
-0x506c1b00,	/* add r27, r27, r0 */
-0x50f03c00,	/* addc r28, r28, r1 */
-0x50f7fd00,	/* addc r29, r29, r31 */
-0x0c000000,	/* ret */
-/* } */
-/* @0x2d8: function dod0[15] { */
-#define CF_dod0_adr 728
-0x8c0c1100,	/* ld *3, *1 */
-0x58140100,	/* mul128 r5, r1l, r0l */
-0x58880100,	/* mul128 r2, r1u, r0l */
-0x50144510,	/* add r5, r5, r2 << 128 */
-0x59080100,	/* mul128 r2, r1l, r0u */
-0x50144510,	/* add r5, r5, r2 << 128 */
-0x5801c500,	/* mul128 r0, r5l, r14l */
-0x5985c500,	/* mul128 r1, r5u, r14u */
-0x5889c500,	/* mul128 r2, r5u, r14l */
-0x50004010,	/* add r0, r0, r2 << 128 */
-0x50844190,	/* addc r1, r1, r2 >> 128 */
-0x5909c500,	/* mul128 r2, r5l, r14u */
-0x50004010,	/* add r0, r0, r2 << 128 */
-0x50844190,	/* addc r1, r1, r2 >> 128 */
-0x0c000000,	/* ret */
-/* } */
-/* @0x2e7: function dod1[9] { */
-#define CF_dod1_adr 743
-0x5801e500,	/* mul128 r0, r5l, r15l */
-0x5985e500,	/* mul128 r1, r5u, r15u */
-0x5889e500,	/* mul128 r2, r5u, r15l */
-0x50004010,	/* add r0, r0, r2 << 128 */
-0x50844190,	/* addc r1, r1, r2 >> 128 */
-0x5909e500,	/* mul128 r2, r5l, r15u */
-0x50004010,	/* add r0, r0, r2 << 128 */
-0x50844190,	/* addc r1, r1, r2 >> 128 */
-0x0c000000,	/* ret */
-/* } */
-/* @0x2f0: function dod2[9] { */
-#define CF_dod2_adr 752
-0x58020500,	/* mul128 r0, r5l, r16l */
-0x59860500,	/* mul128 r1, r5u, r16u */
-0x588a0500,	/* mul128 r2, r5u, r16l */
-0x50004010,	/* add r0, r0, r2 << 128 */
-0x50844190,	/* addc r1, r1, r2 >> 128 */
-0x590a0500,	/* mul128 r2, r5l, r16u */
-0x50004010,	/* add r0, r0, r2 << 128 */
-0x50844190,	/* addc r1, r1, r2 >> 128 */
-0x0c000000,	/* ret */
-/* } */
-/* @0x2f9: function dod3[9] { */
-#define CF_dod3_adr 761
-0x58022500,	/* mul128 r0, r5l, r17l */
-0x59862500,	/* mul128 r1, r5u, r17u */
-0x588a2500,	/* mul128 r2, r5u, r17l */
-0x50004010,	/* add r0, r0, r2 << 128 */
-0x50844190,	/* addc r1, r1, r2 >> 128 */
-0x590a2500,	/* mul128 r2, r5l, r17u */
-0x50004010,	/* add r0, r0, r2 << 128 */
-0x50844190,	/* addc r1, r1, r2 >> 128 */
-0x0c000000,	/* ret */
-/* } */
-/* @0x302: function redc4[97] { */
-#define CF_redc4_adr 770
-0x7c001600,	/* mov r0, r22 */
-0x080002d8,	/* call &dod0 */
-0x50581600,	/* add r22, r22, r0 */
-0x50dc3700,	/* addc r23, r23, r1 */
-0x50e3f800,	/* addc r24, r24, r31 */
-0x5093ff00,	/* addc r4, r31, r31 */
-0x080002e7,	/* call &dod1 */
-0x505c1700,	/* add r23, r23, r0 */
-0x50e03800,	/* addc r24, r24, r1 */
-0x50e49900,	/* addc r25, r25, r4 */
-0x5093ff00,	/* addc r4, r31, r31 */
-0x080002f0,	/* call &dod2 */
-0x50601800,	/* add r24, r24, r0 */
-0x50e43900,	/* addc r25, r25, r1 */
-0x50e89a00,	/* addc r26, r26, r4 */
-0x5093ff00,	/* addc r4, r31, r31 */
-0x080002f9,	/* call &dod3 */
-0x50641900,	/* add r25, r25, r0 */
-0x50e83a00,	/* addc r26, r26, r1 */
-0x50ec9b00,	/* addc r27, r27, r4 */
-0x508fff00,	/* addc r3, r31, r31 */
-0x7c001700,	/* mov r0, r23 */
-0x080002d8,	/* call &dod0 */
-0x505c1700,	/* add r23, r23, r0 */
-0x50e03800,	/* addc r24, r24, r1 */
-0x50e7f900,	/* addc r25, r25, r31 */
-0x5093ff00,	/* addc r4, r31, r31 */
-0x080002e7,	/* call &dod1 */
-0x50601800,	/* add r24, r24, r0 */
-0x50e43900,	/* addc r25, r25, r1 */
-0x50e89a00,	/* addc r26, r26, r4 */
-0x5093ff00,	/* addc r4, r31, r31 */
-0x080002f0,	/* call &dod2 */
-0x50641900,	/* add r25, r25, r0 */
-0x50e83a00,	/* addc r26, r26, r1 */
-0x50ec9b00,	/* addc r27, r27, r4 */
-0x508fff00,	/* addc r3, r31, r31 */
-0x080002f9,	/* call &dod3 */
-0x50681a00,	/* add r26, r26, r0 */
-0x50ec3b00,	/* addc r27, r27, r1 */
-0x50f07c00,	/* addc r28, r28, r3 */
-0x508fff00,	/* addc r3, r31, r31 */
-0x7c001800,	/* mov r0, r24 */
-0x080002d8,	/* call &dod0 */
-0x50601800,	/* add r24, r24, r0 */
-0x50e43900,	/* addc r25, r25, r1 */
-0x50ebfa00,	/* addc r26, r26, r31 */
-0x5093ff00,	/* addc r4, r31, r31 */
-0x080002e7,	/* call &dod1 */
-0x50641900,	/* add r25, r25, r0 */
-0x50e83a00,	/* addc r26, r26, r1 */
-0x50ec9b00,	/* addc r27, r27, r4 */
-0x5093ff00,	/* addc r4, r31, r31 */
-0x080002f0,	/* call &dod2 */
-0x50681a00,	/* add r26, r26, r0 */
-0x50ec3b00,	/* addc r27, r27, r1 */
-0x50f09c00,	/* addc r28, r28, r4 */
-0x5093e300,	/* addc r4, r3, r31 */
-0x080002f9,	/* call &dod3 */
-0x506c1b00,	/* add r27, r27, r0 */
-0x50f03c00,	/* addc r28, r28, r1 */
-0x50f49d00,	/* addc r29, r29, r4 */
-0x508fff00,	/* addc r3, r31, r31 */
-0x7c001900,	/* mov r0, r25 */
-0x080002d8,	/* call &dod0 */
-0x50641900,	/* add r25, r25, r0 */
-0x50d83a00,	/* addc r22, r26, r1 */
-0x50dffb00,	/* addc r23, r27, r31 */
-0x5093ff00,	/* addc r4, r31, r31 */
-0x080002e7,	/* call &dod1 */
-0x50581600,	/* add r22, r22, r0 */
-0x50dc3700,	/* addc r23, r23, r1 */
-0x50e09c00,	/* addc r24, r28, r4 */
-0x5093ff00,	/* addc r4, r31, r31 */
-0x080002f0,	/* call &dod2 */
-0x505c1700,	/* add r23, r23, r0 */
-0x50e03800,	/* addc r24, r24, r1 */
-0x50e49d00,	/* addc r25, r29, r4 */
-0x508fe300,	/* addc r3, r3, r31 */
-0x080002f9,	/* call &dod3 */
-0x50601800,	/* add r24, r24, r0 */
-0x50e43900,	/* addc r25, r25, r1 */
-0x508fe300,	/* addc r3, r3, r31 */
-0x56007f00,	/* subx r0, r31, r3 */
-0x99680000,	/* strnd r26 */
-0x996c0000,	/* strnd r27 */
-0x99700000,	/* strnd r28 */
-0x99740000,	/* strnd r29 */
-0x5409d600,	/* sub r2, r22, r14 */
-0x54e9f700,	/* subb r26, r23, r15 */
-0x54ee1800,	/* subb r27, r24, r16 */
-0x54f23900,	/* subb r28, r25, r17 */
-0x66773c08,	/* selcx r29, r28, r25 */
-0x66731b08,	/* selcx r28, r27, r24 */
-0x666efa08,	/* selcx r27, r26, r23 */
-0x666ac208,	/* selcx r26, r2, r22 */
-0x0c000000,	/* ret */
-/* } */
-/* @0x363: function modexp_1024[101] { */
-#define CF_modexp_1024_adr 867
-0x7c081f00,	/* mov r2, r31 */
-0x80080006,	/* movi r2.0l, #6 */
-0x8088000a,	/* movi r2.1l, #10 */
-0x81880001,	/* movi r2.3l, #1 */
-0x8208000e,	/* movi r2.4l, #14 */
-0x82880016,	/* movi r2.5l, #22 */
-0x83080012,	/* movi r2.6l, #18 */
-0x97800200,	/* ldrfp r2 */
-0x7c001f00,	/* mov r0, r31 */
-0x8180ffff,	/* movi r0.3l, #65535 */
-0x84044000,	/* ldi r1, [#0] */
-0x40040100,	/* and r1, r1, r0 */
-0x48000000,	/* not r0, r0 */
-0x84084060,	/* ldi r2, [#3] */
-0x40080200,	/* and r2, r2, r0 */
-0x44082200,	/* or r2, r2, r1 */
-0x95800200,	/* lddmp r2 */
-0x05004004,	/* loop #4 ( */
-0x8c201b00,	/* ld *0++, *3++ */
-0x8c241a00,	/* ld *1++, *2++ */
-0x8c301800,	/* ld *4++, *0++ */
-0x8c381c00,	/* ld *6++, *4++ */
-/*		   ) */
-0x99780000,	/* strnd r30 */
-0x507bde00,	/* add r30, r30, r30 */
-0x080001ba,	/* call &mul4 */
-0x08000302,	/* call &redc4 */
-0x7c281a00,	/* mov r10, r26 */
-0x7c2c1b00,	/* mov r11, r27 */
-0x7c301c00,	/* mov r12, r28 */
-0x7c341d00,	/* mov r13, r29 */
-0x99180000,	/* strnd r6 */
-0x991c0000,	/* strnd r7 */
-0x99200000,	/* strnd r8 */
-0x99240000,	/* strnd r9 */
-0x05400033,	/* loop #1024 ( */
-0x08000263,	/* call &sqr4 */
-0x08000302,	/* call &redc4 */
-0x99180000,	/* strnd r6 */
-0x991c0000,	/* strnd r7 */
-0x99200000,	/* strnd r8 */
-0x99240000,	/* strnd r9 */
-0x7c181a00,	/* mov r6, r26 */
-0x7c1c1b00,	/* mov r7, r27 */
-0x7c201c00,	/* mov r8, r28 */
-0x7c241d00,	/* mov r9, r29 */
-0x080001ba,	/* call &mul4 */
-0x08000302,	/* call &redc4 */
-0x99000000,	/* strnd r0 */
-0x5002b500,	/* add r0, r21, r21 */
-0x99000000,	/* strnd r0 */
-0x50825200,	/* addc r0, r18, r18 */
-0x99480000,	/* strnd r18 */
-0x7c480000,	/* mov r18, r0 */
-0x99000000,	/* strnd r0 */
-0x50827300,	/* addc r0, r19, r19 */
-0x994c0000,	/* strnd r19 */
-0x7c4c0000,	/* mov r19, r0 */
-0x99000000,	/* strnd r0 */
-0x50829400,	/* addc r0, r20, r20 */
-0x99500000,	/* strnd r20 */
-0x7c500000,	/* mov r20, r0 */
-0x99000000,	/* strnd r0 */
-0x5082b500,	/* addc r0, r21, r21 */
-0x99540000,	/* strnd r21 */
-0x7c540000,	/* mov r21, r0 */
-0x99580000,	/* strnd r22 */
-0x995c0000,	/* strnd r23 */
-0x99600000,	/* strnd r24 */
-0x99640000,	/* strnd r25 */
-0x080001aa,	/* call &selA0orC4 */
-0x99180000,	/* strnd r6 */
-0x991c0000,	/* strnd r7 */
-0x99200000,	/* strnd r8 */
-0x99240000,	/* strnd r9 */
-0x99000000,	/* strnd r0 */
-0x50000000,	/* add r0, r0, r0 */
-0x4c001e00,	/* xor r0, r30, r0 */
-0x99780000,	/* strnd r30 */
-0x507bde00,	/* add r30, r30, r30 */
-0x4c781e00,	/* xor r30, r30, r0 */
-0x447a5e00,	/* or r30, r30, r18 */
-0x4c03c000,	/* xor r0, r0, r30 */
-0x641aca01,	/* sell r6, r10, r22 */
-0x641eeb01,	/* sell r7, r11, r23 */
-0x64230c01,	/* sell r8, r12, r24 */
-0x64272d01,	/* sell r9, r13, r25 */
-/*		   ) */
-0x7c281f00,	/* mov r10, r31 */
-0x80280001,	/* movi r10.0l, #1 */
-0x7c2c1f00,	/* mov r11, r31 */
-0x7c301f00,	/* mov r12, r31 */
-0x7c341f00,	/* mov r13, r31 */
-0x080001ba,	/* call &mul4 */
-0x08000302,	/* call &redc4 */
-0x5419da00,	/* sub r6, r26, r14 */
-0x549dfb00,	/* subb r7, r27, r15 */
-0x54a21c00,	/* subb r8, r28, r16 */
-0x54a63d00,	/* subb r9, r29, r17 */
-0x080001aa,	/* call &selA0orC4 */
-0x05004001,	/* loop #4 ( */
-0x90740d00,	/* st *5++, *5++ */
-/*		   ) */
-0x0c000000,	/* ret */
-/* } */
-#endif // CONFIG_DCRYPTO_RSA_SPEEDUP
-};
-/* clang-format on */
-
-struct DMEM_ctx_ptrs {
-	uint32_t pMod;
-	uint32_t pDinv;
-	uint32_t pRR;
-	uint32_t pA;
-	uint32_t pB;
-	uint32_t pC;
-	uint32_t n;
-	uint32_t n1;
-};
-
-/*
- * This struct is "calling convention" for passing parameters into the
- * code block above for RSA operations.  Parameters start at &DMEM[0].
- */
-struct DMEM_ctx {
-	struct DMEM_ctx_ptrs in_ptrs;
-	struct DMEM_ctx_ptrs sqr_ptrs;
-	struct DMEM_ctx_ptrs mul_ptrs;
-	struct DMEM_ctx_ptrs out_ptrs;
-	uint32_t mod[RSA_WORDS_4K];
-	uint32_t dInv[8];
-	uint32_t pubexp;
-	uint32_t _pad1[3];
-	uint32_t rnd[2];
-	uint32_t _pad2[2];
-	uint32_t RR[RSA_WORDS_4K];
-	uint32_t in[RSA_WORDS_4K];
-	uint32_t exp[RSA_WORDS_4K + 8]; /* extra word for randomization */
-	uint32_t out[RSA_WORDS_4K];
-	uint32_t bin[RSA_WORDS_4K];
-	uint32_t bout[RSA_WORDS_4K];
-};
-
-#define DMEM_CELL_SIZE 32
-#define DMEM_INDEX(p, f)                                                       \
-	(((const uint8_t *)&(p)->f - (const uint8_t *)(p)) / DMEM_CELL_SIZE)
-
-/* Get non-0 64 bit random */
-static void rand64(uint32_t dst[2])
-{
-	do {
-		dst[0] = rand();
-		dst[1] = rand();
-	} while ((dst[0] | dst[1]) == 0);
-}
-
-/* Grab dcrypto lock and set things up for modulus and input */
-static int setup_and_lock(const struct LITE_BIGNUM *N,
-			  const struct LITE_BIGNUM *input)
-{
-	struct DMEM_ctx *ctx =
-		(struct DMEM_ctx *)GREG32_ADDR(CRYPTO, DMEM_DUMMY);
-
-	/* Initialize hardware; load code page. */
-	dcrypto_init_and_lock();
-	dcrypto_imem_load(0, IMEM_dcrypto_bn, ARRAY_SIZE(IMEM_dcrypto_bn));
-
-	/* Setup DMEM pointers (as indices into DMEM which are 256-bit cells).
-	 */
-	ctx->in_ptrs.pMod = DMEM_INDEX(ctx, mod);
-	ctx->in_ptrs.pDinv = DMEM_INDEX(ctx, dInv);
-	ctx->in_ptrs.pRR = DMEM_INDEX(ctx, RR);
-	ctx->in_ptrs.pA = DMEM_INDEX(ctx, in);
-	ctx->in_ptrs.pB = DMEM_INDEX(ctx, exp);
-	ctx->in_ptrs.pC = DMEM_INDEX(ctx, out);
-	ctx->in_ptrs.n = bn_bits(N) / (DMEM_CELL_SIZE * 8);
-	ctx->in_ptrs.n1 = ctx->in_ptrs.n - 1;
-
-	ctx->sqr_ptrs = ctx->in_ptrs;
-	ctx->mul_ptrs = ctx->in_ptrs;
-	ctx->out_ptrs = ctx->in_ptrs;
-
-	dcrypto_dmem_load(DMEM_INDEX(ctx, in), input->d, bn_words(input));
-	if (dcrypto_dmem_load(DMEM_INDEX(ctx, mod), N->d, bn_words(N)) == 0) {
-		/*
-		 * No change detected; assume modulus precomputation is cached.
-		 */
-		return 0;
-	}
-
-	/* Calculate RR and d0inv. */
-	return dcrypto_call(CF_modload_adr);
-}
-
-#define MONTMUL(ctx, a, b, c)                                                  \
-	montmul(ctx, DMEM_INDEX(ctx, a), DMEM_INDEX(ctx, b), DMEM_INDEX(ctx, c))
-
-static int montmul(struct DMEM_ctx *ctx, uint32_t pA, uint32_t pB,
-		   uint32_t pOut)
-{
-
-	ctx->in_ptrs.pA = pA;
-	ctx->in_ptrs.pB = pB;
-	ctx->in_ptrs.pC = pOut;
-
-	return dcrypto_call(CF_mulx_adr);
-}
-
-#define MONTOUT(ctx, a, b) montout(ctx, DMEM_INDEX(ctx, a), DMEM_INDEX(ctx, b))
-
-static int montout(struct DMEM_ctx *ctx, uint32_t pA, uint32_t pOut)
-{
-
-	ctx->in_ptrs.pA = pA;
-	ctx->in_ptrs.pB = 0;
-	ctx->in_ptrs.pC = pOut;
-
-	return dcrypto_call(CF_mul1_adr);
-}
-
-#define MODEXP(ctx, in, exp, out)                                              \
-	modexp(ctx, CF_modexp_adr, DMEM_INDEX(ctx, RR), DMEM_INDEX(ctx, in),   \
-	       DMEM_INDEX(ctx, exp), DMEM_INDEX(ctx, out))
-
-#define MODEXP1024(ctx, in, exp, out)                                          \
-	modexp(ctx, CF_modexp_1024_adr, DMEM_INDEX(ctx, RR),                   \
-	       DMEM_INDEX(ctx, in), DMEM_INDEX(ctx, exp),                      \
-	       DMEM_INDEX(ctx, out))
-
-#define MODEXP_BLINDED(ctx, in, exp, out)                                      \
-	modexp(ctx, CF_modexp_blinded_adr, DMEM_INDEX(ctx, RR),                \
-	       DMEM_INDEX(ctx, in), DMEM_INDEX(ctx, exp),                      \
-	       DMEM_INDEX(ctx, out))
-
-static int modexp(struct DMEM_ctx *ctx, uint32_t adr, uint32_t rr, uint32_t pIn,
-		  uint32_t pExp, uint32_t pOut)
-{
-	/* in = in * RR */
-	ctx->in_ptrs.pA = pIn;
-	ctx->in_ptrs.pB = rr;
-	ctx->in_ptrs.pC = pIn;
-
-	/* out = out * out */
-	ctx->sqr_ptrs.pA = pOut;
-	ctx->sqr_ptrs.pB = pOut;
-	ctx->sqr_ptrs.pC = pOut;
-
-	/* out = out * in */
-	ctx->mul_ptrs.pA = pIn;
-	ctx->mul_ptrs.pB = pOut;
-	ctx->mul_ptrs.pC = pOut;
-
-	/* out = out / R */
-	ctx->out_ptrs.pA = pOut;
-	ctx->out_ptrs.pB = pExp;
-	ctx->out_ptrs.pC = pOut;
-
-	return dcrypto_call(adr);
-}
-
-/* output = input ** exp % N. */
-int dcrypto_modexp_blinded(struct LITE_BIGNUM *output,
-			   const struct LITE_BIGNUM *input,
-			   const struct LITE_BIGNUM *exp,
-			   const struct LITE_BIGNUM *N, uint32_t pubexp)
-{
-	int i, result;
-	struct DMEM_ctx *ctx =
-		(struct DMEM_ctx *)GREG32_ADDR(CRYPTO, DMEM_DUMMY);
-
-	uint32_t r_buf[RSA_MAX_WORDS];
-	uint32_t rinv_buf[RSA_MAX_WORDS];
-
-	struct LITE_BIGNUM r;
-	struct LITE_BIGNUM rinv;
-
-	bn_init(&r, r_buf, bn_size(N));
-	bn_init(&rinv, rinv_buf, bn_size(N));
-
-	/*
-	 * pick 64 bit r != 0
-	 * We cannot tolerate risk of 0 since 0 breaks computation.
-	 */
-	rand64(r_buf);
-
-	/*
-	 * compute 1/r mod N
-	 * Note this cannot fail since N is product of two large primes
-	 * and r != 0, so we can ignore return value.
-	 */
-	bn_modinv_vartime(&rinv, &r, N);
-
-	/*
-	 * compute r^pubexp mod N
-	 */
-	dcrypto_modexp_word(&r, &r, pubexp, N);
-
-	result = setup_and_lock(N, input);
-
-	/* Pick !0 64-bit random for exponent blinding */
-	rand64(ctx->rnd);
-	ctx->pubexp = pubexp;
-
-	ctx->_pad1[0] = ctx->_pad1[1] = ctx->_pad1[2] = 0;
-	ctx->_pad2[0] = ctx->_pad2[1] = 0;
-
-	dcrypto_dmem_load(DMEM_INDEX(ctx, bin), r.d, bn_words(&r));
-	dcrypto_dmem_load(DMEM_INDEX(ctx, bout), rinv.d, bn_words(&rinv));
-	dcrypto_dmem_load(DMEM_INDEX(ctx, exp), exp->d, bn_words(exp));
-
-	/* 0 pad the exponent to full size + 8 */
-	for (i = bn_words(exp); i < bn_words(N) + 8; ++i)
-		ctx->exp[i] = 0;
-
-	/* Blind input */
-	result |= MONTMUL(ctx, in, RR, in);
-	result |= MONTMUL(ctx, in, bin, in);
-
-	result |= MODEXP_BLINDED(ctx, in, exp, out);
-
-	/* remove blinding factor */
-	result |= MONTMUL(ctx, out, RR, out);
-	result |= MONTMUL(ctx, out, bout, out);
-	/* fully reduce out */
-	result |= MONTMUL(ctx, out, RR, out);
-	result |= MONTOUT(ctx, out, out);
-
-	memcpy(output->d, ctx->out, bn_size(output));
-
-	dcrypto_unlock();
-	return result == 0;
-}
-
-/* output = input ** exp % N. */
-int dcrypto_modexp(struct LITE_BIGNUM *output, const struct LITE_BIGNUM *input,
-		   const struct LITE_BIGNUM *exp, const struct LITE_BIGNUM *N)
-{
-	int i, result;
-	struct DMEM_ctx *ctx =
-		(struct DMEM_ctx *)GREG32_ADDR(CRYPTO, DMEM_DUMMY);
-
-	result = setup_and_lock(N, input);
-
-	dcrypto_dmem_load(DMEM_INDEX(ctx, exp), exp->d, bn_words(exp));
-
-	/* 0 pad the exponent to full size */
-	for (i = bn_words(exp); i < bn_words(N); ++i)
-		ctx->exp[i] = 0;
-
-#ifdef CONFIG_DCRYPTO_RSA_SPEEDUP
-	if (bn_bits(N) == 1024) { /* special code for 1024 bits */
-		result |= MODEXP1024(ctx, in, exp, out);
-	} else {
-		result |= MODEXP(ctx, in, exp, out);
-	}
-#else
-	result |= MODEXP(ctx, in, exp, out);
-#endif
-
-	memcpy(output->d, ctx->out, bn_size(output));
-
-	dcrypto_unlock();
-	return result == 0;
-}
-
-/* output = input ** exp % N. */
-int dcrypto_modexp_word(struct LITE_BIGNUM *output,
-			const struct LITE_BIGNUM *input, uint32_t exp,
-			const struct LITE_BIGNUM *N)
-{
-	int result;
-	uint32_t e = exp;
-	uint32_t b = 0x80000000;
-	struct DMEM_ctx *ctx =
-		(struct DMEM_ctx *)GREG32_ADDR(CRYPTO, DMEM_DUMMY);
-
-	result = setup_and_lock(N, input);
-
-	/* Find top bit */
-	while (b != 0 && !(b & e))
-		b >>= 1;
-
-	/* out = in * RR */
-	result |= MONTMUL(ctx, in, RR, out);
-	/* in = in * RR */
-	result |= MONTMUL(ctx, in, RR, in);
-
-	while (b > 1) {
-		b >>= 1;
-
-		/* out = out * out */
-		result |= MONTMUL(ctx, out, out, out);
-
-		if ((b & e) != 0) {
-			/* out = out * in */
-			result |= MONTMUL(ctx, in, out, out);
-		}
-	}
-
-	/* out = out / R */
-	result |= MONTOUT(ctx, out, out);
-
-	memcpy(output->d, ctx->out, bn_size(output));
-
-	dcrypto_unlock();
-	return result == 0;
-}
-
-#ifdef CRYPTO_TEST_SETUP
-#include "console.h"
-#include "shared_mem.h"
-#include "timer.h"
-
-static uint8_t genp_seed[32];
-static uint32_t prime_buf[32];
-static timestamp_t genp_start;
-static timestamp_t genp_end;
-
-static int genp_core(void)
-{
-	struct LITE_BIGNUM prime;
-	int result;
-
-	// Spin seed out into prng candidate prime.
-	DCRYPTO_hkdf((uint8_t *)prime_buf, sizeof(prime_buf), genp_seed,
-		     sizeof(genp_seed), 0, 0, 0, 0);
-	DCRYPTO_bn_wrap(&prime, &prime_buf, sizeof(prime_buf));
-
-	genp_start = get_time();
-	result = (DCRYPTO_bn_generate_prime(&prime) != 0) ? EC_SUCCESS
-							  : EC_ERROR_UNKNOWN;
-	genp_end = get_time();
-
-	return result;
-}
-
-static int call_on_bigger_stack(int (*func)(void))
-{
-	int result, i;
-	char *new_stack;
-	const int new_stack_size = 4 * 1024;
-
-	result = shared_mem_acquire(new_stack_size, &new_stack);
-	if (result == EC_SUCCESS) {
-		// Paint stack arena
-		memset(new_stack, 0x01, new_stack_size);
-
-		// Call whilst switching stacks
-		__asm__ volatile("mov r4, sp\n" // save sp
-				 "mov sp, %[new_stack]\n"
-				 "blx %[func]\n"
-				 "mov sp, r4\n" // restore sp
-				 "mov %[result], r0\n"
-				 : [result] "=r"(result)
-				 : [new_stack] "r"(new_stack + new_stack_size),
-				   [func] "r"(func)
-				 : "r0", "r1", "r2", "r3", "r4",
-				   "lr" // clobbers
-		);
-
-		// Take guess at amount of stack that got used
-		for (i = 0; i < new_stack_size && new_stack[i] == 0x01; ++i)
-			;
-		ccprintf("stack: %u/%u\n", new_stack_size - i, new_stack_size);
-
-		shared_mem_release(new_stack);
-	}
-
-	return result;
-}
-
-static int command_genp(int argc, char **argv)
-{
-	int result;
-
-	memset(genp_seed, 0, sizeof(genp_seed));
-	if (argc > 1)
-		memcpy(genp_seed, argv[1], strlen(argv[1]));
-
-	result = call_on_bigger_stack(genp_core);
-
-	if (result == EC_SUCCESS) {
-		ccprintf("prime: %ph (lsb first)\n",
-			 HEX_BUF(prime_buf, sizeof(prime_buf)));
-		ccprintf("μs   : %llu\n",
-			 (long long)(genp_end.val - genp_start.val));
-	}
-
-	return result;
-}
-DECLARE_CONSOLE_COMMAND(genp, command_genp, "[seed]", "Generate prng prime");
-#endif
diff --git a/chip/g/dcrypto/dcrypto_p256.c b/chip/g/dcrypto/dcrypto_p256.c
deleted file mode 100644
index 64b06dab40..0000000000
--- a/chip/g/dcrypto/dcrypto_p256.c
+++ /dev/null
@@ -1,969 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#include "dcrypto.h"
-#include "internal.h"
-#include "registers.h"
-#include "trng.h"
-
-/* Firmware blob for crypto accelerator */
-
-/* AUTO-GENERATED.  DO NOT MODIFY. */
-/* clang-format off */
-static const uint32_t IMEM_dcrypto[] = {
-/* @0x0: function tag[1] { */
-#define CF_tag_adr 0
-	0xf8000002, /* sigini #2 */
-/* } */
-/* @0x1: function SetupP256PandMuLow[21] { */
-#define CF_SetupP256PandMuLow_adr 1
-	0x55741f01, /* subi r29, r31, #1 */
-	0x83750000, /* movi r29.6h, #0 */
-	0x83740001, /* movi r29.6l, #1 */
-	0x82f50000, /* movi r29.5h, #0 */
-	0x82f40000, /* movi r29.5l, #0 */
-	0x82750000, /* movi r29.4h, #0 */
-	0x82740000, /* movi r29.4l, #0 */
-	0x81f50000, /* movi r29.3h, #0 */
-	0x81f40000, /* movi r29.3l, #0 */
-	0x98801d00, /* ldmod r29 */
-	0x55701f01, /* subi r28, r31, #1 */
-	0x83f10000, /* movi r28.7h, #0 */
-	0x83f00000, /* movi r28.7l, #0 */
-	0x82f0fffe, /* movi r28.5l, #65534 */
-	0x8270fffe, /* movi r28.4l, #65534 */
-	0x81f0fffe, /* movi r28.3l, #65534 */
-	0x80f10000, /* movi r28.1h, #0 */
-	0x80f00000, /* movi r28.1l, #0 */
-	0x80710000, /* movi r28.0h, #0 */
-	0x80700003, /* movi r28.0l, #3 */
-	0x0c000000, /* ret */
-/* } */
-/* @0x16: function p256init[22] { */
-#define CF_p256init_adr 22
-	0x847c4000, /* ldi r31, [#0] */
-	0x4c7fff00, /* xor r31, r31, r31 */
-	0x51781f01, /* addi r30, r31, #1 */
-	0x08000001, /* call &SetupP256PandMuLow */
-	0x7c6c1f00, /* mov r27, r31 */
-	0x83ed5ac6, /* movi r27.7h, #23238 */
-	0x83ec35d8, /* movi r27.7l, #13784 */
-	0x836daa3a, /* movi r27.6h, #43578 */
-	0x836c93e7, /* movi r27.6l, #37863 */
-	0x82edb3eb, /* movi r27.5h, #46059 */
-	0x82ecbd55, /* movi r27.5l, #48469 */
-	0x826d7698, /* movi r27.4h, #30360 */
-	0x826c86bc, /* movi r27.4l, #34492 */
-	0x81ed651d, /* movi r27.3h, #25885 */
-	0x81ec06b0, /* movi r27.3l, #1712 */
-	0x816dcc53, /* movi r27.2h, #52307 */
-	0x816cb0f6, /* movi r27.2l, #45302 */
-	0x80ed3bce, /* movi r27.1h, #15310 */
-	0x80ec3c3e, /* movi r27.1l, #15422 */
-	0x806d27d2, /* movi r27.0h, #10194 */
-	0x806c604b, /* movi r27.0l, #24651 */
-	0x0c000000, /* ret */
-/* } */
-/* @0x2c: function MulMod[38] { */
-#define CF_MulMod_adr 44
-	0x584f3800, /* mul128 r19, r24l, r25l */
-	0x59d33800, /* mul128 r20, r24u, r25u */
-	0x58d73800, /* mul128 r21, r24u, r25l */
-	0x504eb310, /* add r19, r19, r21 << 128 */
-	0x50d2b490, /* addc r20, r20, r21 >> 128 */
-	0x59573800, /* mul128 r21, r24l, r25u */
-	0x504eb310, /* add r19, r19, r21 << 128 */
-	0x50d2b490, /* addc r20, r20, r21 >> 128 */
-	0x645bfc02, /* selm r22, r28, r31 */
-	0x685693ff, /* rshi r21, r19, r20 >> 255 */
-	0x585f9500, /* mul128 r23, r21l, r28l */
-	0x59e39500, /* mul128 r24, r21u, r28u */
-	0x58e79500, /* mul128 r25, r21u, r28l */
-	0x505f3710, /* add r23, r23, r25 << 128 */
-	0x50e33890, /* addc r24, r24, r25 >> 128 */
-	0x59679500, /* mul128 r25, r21l, r28u */
-	0x505f3710, /* add r23, r23, r25 << 128 */
-	0x50e33890, /* addc r24, r24, r25 >> 128 */
-	0x6867f4ff, /* rshi r25, r20, r31 >> 255 */
-	0x5062b800, /* add r24, r24, r21 */
-	0x50e7f900, /* addc r25, r25, r31 */
-	0x5062d800, /* add r24, r24, r22 */
-	0x50e7f900, /* addc r25, r25, r31 */
-	0x68573801, /* rshi r21, r24, r25 >> 1 */
-	0x585abd00, /* mul128 r22, r29l, r21l */
-	0x59debd00, /* mul128 r23, r29u, r21u */
-	0x58e2bd00, /* mul128 r24, r29u, r21l */
-	0x505b1610, /* add r22, r22, r24 << 128 */
-	0x50df1790, /* addc r23, r23, r24 >> 128 */
-	0x5962bd00, /* mul128 r24, r29l, r21u */
-	0x505b1610, /* add r22, r22, r24 << 128 */
-	0x50df1790, /* addc r23, r23, r24 >> 128 */
-	0x545ad300, /* sub r22, r19, r22 */
-	0x54d2f400, /* subb r20, r20, r23 */
-	0x6457fd01, /* sell r21, r29, r31 */
-	0x5456b600, /* sub r21, r22, r21 */
-	0x9c4ff500, /* addm r19, r21, r31 */
-	0x0c000000, /* ret */
-/* } */
-/* @0x52: function p256isoncurve[24] { */
-#define CF_p256isoncurve_adr 82
-	0x84004000, /* ldi r0, [#0] */
-	0x95800000, /* lddmp r0 */
-	0x82800018, /* movi r0.5l, #24 */
-	0x83000018, /* movi r0.6l, #24 */
-	0x80000000, /* movi r0.0l, #0 */
-	0x97800000, /* ldrfp r0 */
-	0x8c181600, /* ld *6, *6 */
-	0x7c641800, /* mov r25, r24 */
-	0x0800002c, /* call &MulMod */
-	0x7c001300, /* mov r0, r19 */
-	0x8c141500, /* ld *5, *5 */
-	0x7c641800, /* mov r25, r24 */
-	0x0800002c, /* call &MulMod */
-	0x8c141500, /* ld *5, *5 */
-	0x7c641300, /* mov r25, r19 */
-	0x0800002c, /* call &MulMod */
-	0x8c141500, /* ld *5, *5 */
-	0xa04f1300, /* subm r19, r19, r24 */
-	0xa04f1300, /* subm r19, r19, r24 */
-	0xa04f1300, /* subm r19, r19, r24 */
-	0x9c637300, /* addm r24, r19, r27 */
-	0x904c0500, /* st *5, *3 */
-	0x90500000, /* st *0, *4 */
-	0x0c000000, /* ret */
-/* } */
-/* @0x6a: function ProjAdd[80] { */
-#define CF_ProjAdd_adr 106
-	0x7c600b00, /* mov r24, r11 */
-	0x7c640800, /* mov r25, r8 */
-	0x0800002c, /* call &MulMod */
-	0x7c381300, /* mov r14, r19 */
-	0x7c600c00, /* mov r24, r12 */
-	0x7c640900, /* mov r25, r9 */
-	0x0800002c, /* call &MulMod */
-	0x7c3c1300, /* mov r15, r19 */
-	0x7c600d00, /* mov r24, r13 */
-	0x7c640a00, /* mov r25, r10 */
-	0x0800002c, /* call &MulMod */
-	0x7c401300, /* mov r16, r19 */
-	0x9c458b00, /* addm r17, r11, r12 */
-	0x9c492800, /* addm r18, r8, r9 */
-	0x7c601100, /* mov r24, r17 */
-	0x7c641200, /* mov r25, r18 */
-	0x0800002c, /* call &MulMod */
-	0x9c49ee00, /* addm r18, r14, r15 */
-	0xa0465300, /* subm r17, r19, r18 */
-	0x9c49ac00, /* addm r18, r12, r13 */
-	0x9c4d4900, /* addm r19, r9, r10 */
-	0x7c601200, /* mov r24, r18 */
-	0x7c641300, /* mov r25, r19 */
-	0x0800002c, /* call &MulMod */
-	0x7c481300, /* mov r18, r19 */
-	0x9c4e0f00, /* addm r19, r15, r16 */
-	0xa04a7200, /* subm r18, r18, r19 */
-	0x9c4dab00, /* addm r19, r11, r13 */
-	0x9c314800, /* addm r12, r8, r10 */
-	0x7c601300, /* mov r24, r19 */
-	0x7c640c00, /* mov r25, r12 */
-	0x0800002c, /* call &MulMod */
-	0x7c2c1300, /* mov r11, r19 */
-	0x9c320e00, /* addm r12, r14, r16 */
-	0xa0318b00, /* subm r12, r11, r12 */
-	0x7c601b00, /* mov r24, r27 */
-	0x7c641000, /* mov r25, r16 */
-	0x0800002c, /* call &MulMod */
-	0xa02e6c00, /* subm r11, r12, r19 */
-	0x9c356b00, /* addm r13, r11, r11 */
-	0x9c2dab00, /* addm r11, r11, r13 */
-	0xa0356f00, /* subm r13, r15, r11 */
-	0x9c2d6f00, /* addm r11, r15, r11 */
-	0x7c601b00, /* mov r24, r27 */
-	0x7c640c00, /* mov r25, r12 */
-	0x0800002c, /* call &MulMod */
-	0x9c3e1000, /* addm r15, r16, r16 */
-	0x9c420f00, /* addm r16, r15, r16 */
-	0xa0321300, /* subm r12, r19, r16 */
-	0xa031cc00, /* subm r12, r12, r14 */
-	0x9c3d8c00, /* addm r15, r12, r12 */
-	0x9c318f00, /* addm r12, r15, r12 */
-	0x9c3dce00, /* addm r15, r14, r14 */
-	0x9c39cf00, /* addm r14, r15, r14 */
-	0xa03a0e00, /* subm r14, r14, r16 */
-	0x7c601200, /* mov r24, r18 */
-	0x7c640c00, /* mov r25, r12 */
-	0x0800002c, /* call &MulMod */
-	0x7c3c1300, /* mov r15, r19 */
-	0x7c600e00, /* mov r24, r14 */
-	0x7c640c00, /* mov r25, r12 */
-	0x0800002c, /* call &MulMod */
-	0x7c401300, /* mov r16, r19 */
-	0x7c600b00, /* mov r24, r11 */
-	0x7c640d00, /* mov r25, r13 */
-	0x0800002c, /* call &MulMod */
-	0x9c321300, /* addm r12, r19, r16 */
-	0x7c601100, /* mov r24, r17 */
-	0x7c640b00, /* mov r25, r11 */
-	0x0800002c, /* call &MulMod */
-	0xa02df300, /* subm r11, r19, r15 */
-	0x7c601200, /* mov r24, r18 */
-	0x7c640d00, /* mov r25, r13 */
-	0x0800002c, /* call &MulMod */
-	0x7c341300, /* mov r13, r19 */
-	0x7c601100, /* mov r24, r17 */
-	0x7c640e00, /* mov r25, r14 */
-	0x0800002c, /* call &MulMod */
-	0x9c366d00, /* addm r13, r13, r19 */
-	0x0c000000, /* ret */
-/* } */
-/* @0xba: function ProjToAffine[116] { */
-#define CF_ProjToAffine_adr 186
-	0x9c2bea00, /* addm r10, r10, r31 */
-	0x7c600a00, /* mov r24, r10 */
-	0x7c640a00, /* mov r25, r10 */
-	0x0800002c, /* call &MulMod */
-	0x7c601300, /* mov r24, r19 */
-	0x7c640a00, /* mov r25, r10 */
-	0x0800002c, /* call &MulMod */
-	0x7c301300, /* mov r12, r19 */
-	0x7c601300, /* mov r24, r19 */
-	0x7c641300, /* mov r25, r19 */
-	0x0800002c, /* call &MulMod */
-	0x7c601300, /* mov r24, r19 */
-	0x7c641300, /* mov r25, r19 */
-	0x0800002c, /* call &MulMod */
-	0x7c601300, /* mov r24, r19 */
-	0x7c640c00, /* mov r25, r12 */
-	0x0800002c, /* call &MulMod */
-	0x7c341300, /* mov r13, r19 */
-	0x05004004, /* loop #4 ( */
-	0x7c601300, /* mov r24, r19 */
-	0x7c641300, /* mov r25, r19 */
-	0x0800002c, /* call &MulMod */
-	0xfc000000, /* nop */
-	/*		   ) */
-	0x7c601300, /* mov r24, r19 */
-	0x7c640d00, /* mov r25, r13 */
-	0x0800002c, /* call &MulMod */
-	0x7c381300, /* mov r14, r19 */
-	0x05008004, /* loop #8 ( */
-	0x7c601300, /* mov r24, r19 */
-	0x7c641300, /* mov r25, r19 */
-	0x0800002c, /* call &MulMod */
-	0xfc000000, /* nop */
-	/*		   ) */
-	0x7c601300, /* mov r24, r19 */
-	0x7c640e00, /* mov r25, r14 */
-	0x0800002c, /* call &MulMod */
-	0x7c3c1300, /* mov r15, r19 */
-	0x05010004, /* loop #16 ( */
-	0x7c601300, /* mov r24, r19 */
-	0x7c641300, /* mov r25, r19 */
-	0x0800002c, /* call &MulMod */
-	0xfc000000, /* nop */
-	/*		   ) */
-	0x7c601300, /* mov r24, r19 */
-	0x7c640f00, /* mov r25, r15 */
-	0x0800002c, /* call &MulMod */
-	0x7c401300, /* mov r16, r19 */
-	0x05020004, /* loop #32 ( */
-	0x7c601300, /* mov r24, r19 */
-	0x7c641300, /* mov r25, r19 */
-	0x0800002c, /* call &MulMod */
-	0xfc000000, /* nop */
-	/*		   ) */
-	0x7c441300, /* mov r17, r19 */
-	0x7c600a00, /* mov r24, r10 */
-	0x7c641300, /* mov r25, r19 */
-	0x0800002c, /* call &MulMod */
-	0x050c0004, /* loop #192 ( */
-	0x7c601300, /* mov r24, r19 */
-	0x7c641300, /* mov r25, r19 */
-	0x0800002c, /* call &MulMod */
-	0xfc000000, /* nop */
-	/*		   ) */
-	0x7c481300, /* mov r18, r19 */
-	0x7c601100, /* mov r24, r17 */
-	0x7c641000, /* mov r25, r16 */
-	0x0800002c, /* call &MulMod */
-	0x05010004, /* loop #16 ( */
-	0x7c601300, /* mov r24, r19 */
-	0x7c641300, /* mov r25, r19 */
-	0x0800002c, /* call &MulMod */
-	0xfc000000, /* nop */
-	/*		   ) */
-	0x7c600f00, /* mov r24, r15 */
-	0x7c641300, /* mov r25, r19 */
-	0x0800002c, /* call &MulMod */
-	0x05008004, /* loop #8 ( */
-	0x7c601300, /* mov r24, r19 */
-	0x7c641300, /* mov r25, r19 */
-	0x0800002c, /* call &MulMod */
-	0xfc000000, /* nop */
-	/*		   ) */
-	0x7c600e00, /* mov r24, r14 */
-	0x7c641300, /* mov r25, r19 */
-	0x0800002c, /* call &MulMod */
-	0x05004004, /* loop #4 ( */
-	0x7c601300, /* mov r24, r19 */
-	0x7c641300, /* mov r25, r19 */
-	0x0800002c, /* call &MulMod */
-	0xfc000000, /* nop */
-	/*		   ) */
-	0x7c600d00, /* mov r24, r13 */
-	0x7c641300, /* mov r25, r19 */
-	0x0800002c, /* call &MulMod */
-	0x05002004, /* loop #2 ( */
-	0x7c601300, /* mov r24, r19 */
-	0x7c641300, /* mov r25, r19 */
-	0x0800002c, /* call &MulMod */
-	0xfc000000, /* nop */
-	/*		   ) */
-	0x7c600c00, /* mov r24, r12 */
-	0x7c641300, /* mov r25, r19 */
-	0x0800002c, /* call &MulMod */
-	0x05002004, /* loop #2 ( */
-	0x7c601300, /* mov r24, r19 */
-	0x7c641300, /* mov r25, r19 */
-	0x0800002c, /* call &MulMod */
-	0xfc000000, /* nop */
-	/*		   ) */
-	0x7c600a00, /* mov r24, r10 */
-	0x7c641300, /* mov r25, r19 */
-	0x0800002c, /* call &MulMod */
-	0x7c601300, /* mov r24, r19 */
-	0x7c641200, /* mov r25, r18 */
-	0x0800002c, /* call &MulMod */
-	0x7c381300, /* mov r14, r19 */
-	0x7c600800, /* mov r24, r8 */
-	0x7c640e00, /* mov r25, r14 */
-	0x0800002c, /* call &MulMod */
-	0x7c2c1300, /* mov r11, r19 */
-	0x7c600900, /* mov r24, r9 */
-	0x7c640e00, /* mov r25, r14 */
-	0x0800002c, /* call &MulMod */
-	0x7c301300, /* mov r12, r19 */
-	0x0c000000, /* ret */
-/* } */
-/* @0x12e: function ModInv[17] { */
-#define CF_ModInv_adr 302
-	0x98080000, /* stmod r2 */
-	0x55080202, /* subi r2, r2, #2 */
-	0x7c041e00, /* mov r1, r30 */
-	0x0510000c, /* loop #256 ( */
-	0x7c600100, /* mov r24, r1 */
-	0x7c640100, /* mov r25, r1 */
-	0x0800002c, /* call &MulMod */
-	0x7c0c1300, /* mov r3, r19 */
-	0x50084200, /* add r2, r2, r2 */
-	0x64046108, /* selc r1, r1, r3 */
-	0x1008813d, /* bnc nomul */
-	0x7c600300, /* mov r24, r3 */
-	0x7c640000, /* mov r25, r0 */
-	0x0800002c, /* call &MulMod */
-	0x7c041300, /* mov r1, r19 */
-	/*nomul: */
-	0xfc000000, /* nop */
-	/*		   ) */
-	0x0c000000, /* ret */
-/* } */
-/* @0x13f: function FetchBandRandomize[11] { */
-#define CF_FetchBandRandomize_adr 319
-	0x99080000, /* strnd r2 */
-	0x9c6be200, /* addm r26, r2, r31 */
-	0x8c081500, /* ld *2, *5 */
-	0x7c641a00, /* mov r25, r26 */
-	0x0800002c, /* call &MulMod */
-	0x7c181300, /* mov r6, r19 */
-	0x8c081600, /* ld *2, *6 */
-	0x7c641a00, /* mov r25, r26 */
-	0x0800002c, /* call &MulMod */
-	0x7c1c1300, /* mov r7, r19 */
-	0x0c000000, /* ret */
-/* } */
-/* @0x14a: function ProjDouble[5] { */
-#define CF_ProjDouble_adr 330
-	0x7c2c0800, /* mov r11, r8 */
-	0x7c300900, /* mov r12, r9 */
-	0x7c340a00, /* mov r13, r10 */
-	0x0800006a, /* call &ProjAdd */
-	0x0c000000, /* ret */
-/* } */
-/* @0x14f: function SetupP256NandMuLow[25] { */
-#define CF_SetupP256NandMuLow_adr 335
-	0x55741f01, /* subi r29, r31, #1 */
-	0x83750000, /* movi r29.6h, #0 */
-	0x83740000, /* movi r29.6l, #0 */
-	0x81f5bce6, /* movi r29.3h, #48358 */
-	0x81f4faad, /* movi r29.3l, #64173 */
-	0x8175a717, /* movi r29.2h, #42775 */
-	0x81749e84, /* movi r29.2l, #40580 */
-	0x80f5f3b9, /* movi r29.1h, #62393 */
-	0x80f4cac2, /* movi r29.1l, #51906 */
-	0x8075fc63, /* movi r29.0h, #64611 */
-	0x80742551, /* movi r29.0l, #9553 */
-	0x55701f01, /* subi r28, r31, #1 */
-	0x83f10000, /* movi r28.7h, #0 */
-	0x83f00000, /* movi r28.7l, #0 */
-	0x82f0fffe, /* movi r28.5l, #65534 */
-	0x81f14319, /* movi r28.3h, #17177 */
-	0x81f00552, /* movi r28.3l, #1362 */
-	0x8171df1a, /* movi r28.2h, #57114 */
-	0x81706c21, /* movi r28.2l, #27681 */
-	0x80f1012f, /* movi r28.1h, #303 */
-	0x80f0fd85, /* movi r28.1l, #64901 */
-	0x8071eedf, /* movi r28.0h, #61151 */
-	0x80709bfe, /* movi r28.0l, #39934 */
-	0x98801d00, /* ldmod r29 */
-	0x0c000000, /* ret */
-/* } */
-/* @0x168: function ScalarMult_internal[51] { */
-#define CF_ScalarMult_internal_adr 360
-	0x0800014f, /* call &SetupP256NandMuLow */
-	0x8c041100, /* ld *1, *1 */
-	0x9c07e100, /* addm r1, r1, r31 */
-	0xa0002000, /* subm r0, r0, r1 */
-	0x08000001, /* call &SetupP256PandMuLow */
-	0x0800013f, /* call &FetchBandRandomize */
-	0x7c200600, /* mov r8, r6 */
-	0x7c240700, /* mov r9, r7 */
-	0x7c281a00, /* mov r10, r26 */
-	0x0800014a, /* call &ProjDouble */
-	0x7c0c0b00, /* mov r3, r11 */
-	0x7c100c00, /* mov r4, r12 */
-	0x7c140d00, /* mov r5, r13 */
-	0x7c201f00, /* mov r8, r31 */
-	0x7c241e00, /* mov r9, r30 */
-	0x7c281f00, /* mov r10, r31 */
-	0x05100020, /* loop #256 ( */
-	0x0800014a, /* call &ProjDouble */
-	0x0800013f, /* call &FetchBandRandomize */
-	0x4c202000, /* xor r8, r0, r1 */
-	0x64206602, /* selm r8, r6, r3 */
-	0x64248702, /* selm r9, r7, r4 */
-	0x6428ba02, /* selm r10, r26, r5 */
-	0x7c080b00, /* mov r2, r11 */
-	0x7c180c00, /* mov r6, r12 */
-	0x7c1c0d00, /* mov r7, r13 */
-	0x0800006a, /* call &ProjAdd */
-	0x44202000, /* or r8, r0, r1 */
-	0x64204b02, /* selm r8, r11, r2 */
-	0x6424cc02, /* selm r9, r12, r6 */
-	0x6428ed02, /* selm r10, r13, r7 */
-	0x680000ff, /* rshi r0, r0, r0 >> 255 */
-	0x680421ff, /* rshi r1, r1, r1 >> 255 */
-	0x992c0000, /* strnd r11 */
-	0x99300000, /* strnd r12 */
-	0x99340000, /* strnd r13 */
-	0x99080000, /* strnd r2 */
-	0x7c600300, /* mov r24, r3 */
-	0x7c640200, /* mov r25, r2 */
-	0x0800002c, /* call &MulMod */
-	0x7c0c1300, /* mov r3, r19 */
-	0x7c600400, /* mov r24, r4 */
-	0x7c640200, /* mov r25, r2 */
-	0x0800002c, /* call &MulMod */
-	0x7c101300, /* mov r4, r19 */
-	0x7c600500, /* mov r24, r5 */
-	0x7c640200, /* mov r25, r2 */
-	0x0800002c, /* call &MulMod */
-	0x7c141300, /* mov r5, r19 */
-	/*		   ) */
-	0x080000ba, /* call &ProjToAffine */
-	0x0c000000, /* ret */
-/* } */
-/* @0x19b: function get_P256B[35] { */
-#define CF_get_P256B_adr 411
-	0x7c201f00, /* mov r8, r31 */
-	0x83a16b17, /* movi r8.7h, #27415 */
-	0x83a0d1f2, /* movi r8.7l, #53746 */
-	0x8321e12c, /* movi r8.6h, #57644 */
-	0x83204247, /* movi r8.6l, #16967 */
-	0x82a1f8bc, /* movi r8.5h, #63676 */
-	0x82a0e6e5, /* movi r8.5l, #59109 */
-	0x822163a4, /* movi r8.4h, #25508 */
-	0x822040f2, /* movi r8.4l, #16626 */
-	0x81a17703, /* movi r8.3h, #30467 */
-	0x81a07d81, /* movi r8.3l, #32129 */
-	0x81212deb, /* movi r8.2h, #11755 */
-	0x812033a0, /* movi r8.2l, #13216 */
-	0x80a1f4a1, /* movi r8.1h, #62625 */
-	0x80a03945, /* movi r8.1l, #14661 */
-	0x8021d898, /* movi r8.0h, #55448 */
-	0x8020c296, /* movi r8.0l, #49814 */
-	0x7c241f00, /* mov r9, r31 */
-	0x83a54fe3, /* movi r9.7h, #20451 */
-	0x83a442e2, /* movi r9.7l, #17122 */
-	0x8325fe1a, /* movi r9.6h, #65050 */
-	0x83247f9b, /* movi r9.6l, #32667 */
-	0x82a58ee7, /* movi r9.5h, #36583 */
-	0x82a4eb4a, /* movi r9.5l, #60234 */
-	0x82257c0f, /* movi r9.4h, #31759 */
-	0x82249e16, /* movi r9.4l, #40470 */
-	0x81a52bce, /* movi r9.3h, #11214 */
-	0x81a43357, /* movi r9.3l, #13143 */
-	0x81256b31, /* movi r9.2h, #27441 */
-	0x81245ece, /* movi r9.2l, #24270 */
-	0x80a5cbb6, /* movi r9.1h, #52150 */
-	0x80a44068, /* movi r9.1l, #16488 */
-	0x802537bf, /* movi r9.0h, #14271 */
-	0x802451f5, /* movi r9.0l, #20981 */
-	0x0c000000, /* ret */
-/* } */
-/* @0x1be: function p256sign[34] { */
-#define CF_p256sign_adr 446
-	0xfc000000, /* nop */
-	0x84004000, /* ldi r0, [#0] */
-	0x95800000, /* lddmp r0 */
-	0x80000000, /* movi r0.0l, #0 */
-	0x80800001, /* movi r0.1l, #1 */
-	0x81000018, /* movi r0.2l, #24 */
-	0x82000008, /* movi r0.4l, #8 */
-	0x82800009, /* movi r0.5l, #9 */
-	0x97800000, /* ldrfp r0 */
-	0x0800019b, /* call &get_P256B */
-	0x90540400, /* st *4, *5 */
-	0x90580500, /* st *5, *6 */
-	0xfc000000, /* nop */
-	0x8c001000, /* ld *0, *0 */
-	0x08000168, /* call &ScalarMult_internal */
-	0x0800014f, /* call &SetupP256NandMuLow */
-	0x8c001000, /* ld *0, *0 */
-	0x0800012e, /* call &ModInv */
-	0x8c081700, /* ld *2, *7 */
-	0x7c640100, /* mov r25, r1 */
-	0x0800002c, /* call &MulMod */
-	0x9c63eb00, /* addm r24, r11, r31 */
-	0x904c0200, /* st *2, *3 */
-	0xfc000000, /* nop */
-	0x7c641300, /* mov r25, r19 */
-	0x0800002c, /* call &MulMod */
-	0x7c001300, /* mov r0, r19 */
-	0x8c081200, /* ld *2, *2 */
-	0x7c640100, /* mov r25, r1 */
-	0x0800002c, /* call &MulMod */
-	0x9c001300, /* addm r0, r19, r0 */
-	0x90500000, /* st *0, *4 */
-	0x08000001, /* call &SetupP256PandMuLow */
-	0x0c000000, /* ret */
-/* } */
-/* @0x1e0: function p256scalarbasemult[21] { */
-#define CF_p256scalarbasemult_adr 480
-	0xfc000000, /* nop */
-	0x84004000, /* ldi r0, [#0] */
-	0x95800000, /* lddmp r0 */
-	0x80000000, /* movi r0.0l, #0 */
-	0x80800001, /* movi r0.1l, #1 */
-	0x81000018, /* movi r0.2l, #24 */
-	0x8180000b, /* movi r0.3l, #11 */
-	0x82000008, /* movi r0.4l, #8 */
-	0x82800009, /* movi r0.5l, #9 */
-	0x97800000, /* ldrfp r0 */
-	0x8c001100, /* ld *0, *1 */
-	0x99800000, /* ldrnd r0 */
-	0x0800019b, /* call &get_P256B */
-	0x90540400, /* st *4, *5 */
-	0x90580500, /* st *5, *6 */
-	0xfc000000, /* nop */
-	0x8c001700, /* ld *0, *7 */
-	0x08000168, /* call &ScalarMult_internal */
-	0x90540b00, /* st *3++, *5 */
-	0x90580b00, /* st *3++, *6 */
-	0x0c000000, /* ret */
-/* } */
-/* @0x1f5: function ModInvVar[37] { */
-#define CF_ModInvVar_adr 501
-	0x7c081f00, /* mov r2, r31 */
-	0x7c0c1e00, /* mov r3, r30 */
-	0x98100000, /* stmod r4 */
-	0x981c0000, /* stmod r7 */
-	0x7c140000, /* mov r5, r0 */
-	/*impvt_Loop: */
-	0x44108400, /* or r4, r4, r4 */
-	0x10001205, /* bl impvt_Uodd */
-	0x6813e401, /* rshi r4, r4, r31 >> 1 */
-	0x44084200, /* or r2, r2, r2 */
-	0x10001201, /* bl impvt_Rodd */
-	0x680be201, /* rshi r2, r2, r31 >> 1 */
-	0x100801fa, /* b impvt_Loop */
-	/*impvt_Rodd: */
-	0x50084700, /* add r2, r7, r2 */
-	0x509bff00, /* addc r6, r31, r31 */
-	0x6808c201, /* rshi r2, r2, r6 >> 1 */
-	0x100801fa, /* b impvt_Loop */
-	/*impvt_Uodd: */
-	0x4414a500, /* or r5, r5, r5 */
-	0x10001210, /* bl impvt_UVodd */
-	0x6817e501, /* rshi r5, r5, r31 >> 1 */
-	0x440c6300, /* or r3, r3, r3 */
-	0x1000120c, /* bl impvt_Sodd */
-	0x680fe301, /* rshi r3, r3, r31 >> 1 */
-	0x100801fa, /* b impvt_Loop */
-	/*impvt_Sodd: */
-	0x500c6700, /* add r3, r7, r3 */
-	0x509bff00, /* addc r6, r31, r31 */
-	0x680cc301, /* rshi r3, r3, r6 >> 1 */
-	0x100801fa, /* b impvt_Loop */
-	/*impvt_UVodd: */
-	0x5c008500, /* cmp r5, r4 */
-	0x10088215, /* bnc impvt_V>=U */
-	0xa0086200, /* subm r2, r2, r3 */
-	0x5410a400, /* sub r4, r4, r5 */
-	0x100801fa, /* b impvt_Loop */
-	/*impvt_V>=U: */
-	0xa00c4300, /* subm r3, r3, r2 */
-	0x54148500, /* sub r5, r5, r4 */
-	0x100841fa, /* bnz impvt_Loop */
-	0x9c07e200, /* addm r1, r2, r31 */
-	0x0c000000, /* ret */
-/* } */
-/* @0x21a: function p256verify[80] { */
-#define CF_p256verify_adr 538
-	0x84184000, /* ldi r6, [#0] */
-	0x95800600, /* lddmp r6 */
-	0x81980018, /* movi r6.3l, #24 */
-	0x82180000, /* movi r6.4l, #0 */
-	0x82980008, /* movi r6.5l, #8 */
-	0x83180009, /* movi r6.6l, #9 */
-	0x8018000b, /* movi r6.0l, #11 */
-	0x8398000c, /* movi r6.7l, #12 */
-	0x81180018, /* movi r6.2l, #24 */
-	0x97800600, /* ldrfp r6 */
-	0x8c0c1300, /* ld *3, *3 */
-	0x7c600600, /* mov r24, r6 */
-	0x48630000, /* not r24, r24 */
-	0x0800014f, /* call &SetupP256NandMuLow */
-	0x5c03e600, /* cmp r6, r31 */
-	0x10004268, /* bz fail */
-	0x5c03a600, /* cmp r6, r29 */
-	0x10088268, /* bnc fail */
-	0x8c101400, /* ld *4, *4 */
-	0x5c03e000, /* cmp r0, r31 */
-	0x10004268, /* bz fail */
-	0x5c03a000, /* cmp r0, r29 */
-	0x10088268, /* bnc fail */
-	0x080001f5, /* call &ModInvVar */
-	0x8c0c1300, /* ld *3, *3 */
-	0x7c640100, /* mov r25, r1 */
-	0x0800002c, /* call &MulMod */
-	0x7c001300, /* mov r0, r19 */
-	0x8c081200, /* ld *2, *2 */
-	0x7c640100, /* mov r25, r1 */
-	0x0800002c, /* call &MulMod */
-	0x7c041300, /* mov r1, r19 */
-	0x08000001, /* call &SetupP256PandMuLow */
-	0x8c001500, /* ld *0, *5 */
-	0x8c1c1600, /* ld *7, *6 */
-	0x7c341e00, /* mov r13, r30 */
-	0x0800019b, /* call &get_P256B */
-	0x7c281e00, /* mov r10, r30 */
-	0x0800006a, /* call &ProjAdd */
-	0x7c0c0b00, /* mov r3, r11 */
-	0x7c100c00, /* mov r4, r12 */
-	0x7c140d00, /* mov r5, r13 */
-	0x40082000, /* and r2, r0, r1 */
-	0x7c2c1f00, /* mov r11, r31 */
-	0x7c301e00, /* mov r12, r30 */
-	0x7c341f00, /* mov r13, r31 */
-	0x05100018, /* loop #256 ( */
-	0x7c200b00, /* mov r8, r11 */
-	0x7c240c00, /* mov r9, r12 */
-	0x7c280d00, /* mov r10, r13 */
-	0x0800006a, /* call &ProjAdd */
-	0x50084200, /* add r2, r2, r2 */
-	0x10088254, /* bnc noBoth */
-	0x7c200300, /* mov r8, r3 */
-	0x7c240400, /* mov r9, r4 */
-	0x7c280500, /* mov r10, r5 */
-	0x0800006a, /* call &ProjAdd */
-	0x1008025f, /* b noY */
-	/*noBoth: */
-	0x50180000, /* add r6, r0, r0 */
-	0x1008825a, /* bnc noG */
-	0x8c141500, /* ld *5, *5 */
-	0x8c181600, /* ld *6, *6 */
-	0x7c281e00, /* mov r10, r30 */
-	0x0800006a, /* call &ProjAdd */
-	/*noG: */
-	0x50182100, /* add r6, r1, r1 */
-	0x1008825f, /* bnc noY */
-	0x0800019b, /* call &get_P256B */
-	0x7c281e00, /* mov r10, r30 */
-	0x0800006a, /* call &ProjAdd */
-	/*noY: */
-	0x50000000, /* add r0, r0, r0 */
-	0x50042100, /* add r1, r1, r1 */
-	/*		   ) */
-	0x7c000d00, /* mov r0, r13 */
-	0x080001f5, /* call &ModInvVar */
-	0x7c600100, /* mov r24, r1 */
-	0x7c640b00, /* mov r25, r11 */
-	0x0800002c, /* call &MulMod */
-	0x0800014f, /* call &SetupP256NandMuLow */
-	0xa063f300, /* subm r24, r19, r31 */
-	/*fail: */
-	0x90440300, /* st *3, *1 */
-	0x0c000000, /* ret */
-/* } */
-/* @0x26a: function p256scalarmult[12] { */
-#define CF_p256scalarmult_adr 618
-	0x84004000, /* ldi r0, [#0] */
-	0x95800000, /* lddmp r0 */
-	0x80000000, /* movi r0.0l, #0 */
-	0x80800001, /* movi r0.1l, #1 */
-	0x81000018, /* movi r0.2l, #24 */
-	0x8180000b, /* movi r0.3l, #11 */
-	0x97800000, /* ldrfp r0 */
-	0x8c001000, /* ld *0, *0 */
-	0x08000168, /* call &ScalarMult_internal */
-	0x90540b00, /* st *3++, *5 */
-	0x90580b00, /* st *3++, *6 */
-	0x0c000000, /* ret */
-	/* } */
-};
-/* clang-format on */
-
-/*
- * This struct is "calling convention" for passing parameters into the
- * code block above for ecc operations.  Writes to this struct should be done
- * via the cp1w() and cp8w() functions to guarantee that word writes are used,
- * as the dcrypto peripheral does not support byte writes.
- */
-struct DMEM_ecc {
-	uint32_t pK;
-	uint32_t pRnd;
-	uint32_t pMsg;
-	uint32_t pR;
-	uint32_t pS;
-	uint32_t pX;
-	uint32_t pY;
-	uint32_t pD;
-	p256_int k;
-	p256_int rnd;
-	p256_int msg;
-	p256_int r;
-	p256_int s;
-	p256_int x;
-	p256_int y;
-	p256_int d;
-};
-
-#define DMEM_CELL_SIZE 32
-#define DMEM_OFFSET(p) (offsetof(struct DMEM_ecc, p))
-#define DMEM_INDEX(p) (DMEM_OFFSET(p) / DMEM_CELL_SIZE)
-
-/*
- * Read-only pointer to read-only DMEM_ecc struct, use cp*w()
- * functions for writes.
- */
-static const volatile struct DMEM_ecc *dmem_ecc =
-	(const volatile struct DMEM_ecc *)GREG32_ADDR(CRYPTO, DMEM_DUMMY);
-
-/*
- * Writes one word to DMEM, at the address derived from the base
- * offset and number of words. These parameters can be used for example
- * by specifying the offset of a p256_int, and the index of a word within
- * that p256_int.
- */
-static void cp1w(size_t base_offset, int word, const uint32_t src)
-{
-	/* Destination address, always 32-bit aligned. */
-	volatile uint32_t *dst =
-		REG32_ADDR((uint8_t *)GREG32_ADDR(CRYPTO, DMEM_DUMMY) +
-			   base_offset + (word * sizeof(uint32_t)));
-
-	*dst = src;
-}
-
-/*
- * Copies the contents of the src p256_int to the specified offset in DMEM.
- * The src argument does not need to be aligned.
- */
-static void cp8w(size_t offset, const volatile p256_int *src)
-{
-	int i;
-
-	/*
-	 * If p256_int is packed (as it is on cr50), the compiler
-	 * cannot assume src will be aligned, and so performs
-	 * byte reads into a register before calling cp1w (which
-	 * is typically inlined).
-	 *
-	 * Note that the dcrypto peripheral supports byte reads,
-	 * so it is safe to specify a pointer based on dmem_ecc
-	 * as the src argument.
-	 */
-	for (i = 0; i < P256_NDIGITS; i++)
-		cp1w(offset, i, P256_DIGIT(src, i));
-}
-
-/* Convenience macros for above copy functions. */
-#define CP1W(a, b, c) cp1w(DMEM_OFFSET(a), b, c)
-#define CP8W(a, b) cp8w(DMEM_OFFSET(a), b)
-
-static void dcrypto_ecc_init(void)
-{
-	dcrypto_imem_load(0, IMEM_dcrypto, ARRAY_SIZE(IMEM_dcrypto));
-
-	CP1W(pK, 0, DMEM_INDEX(k));
-	CP1W(pRnd, 0, DMEM_INDEX(rnd));
-	CP1W(pMsg, 0, DMEM_INDEX(msg));
-	CP1W(pR, 0, DMEM_INDEX(r));
-	CP1W(pS, 0, DMEM_INDEX(s));
-	CP1W(pX, 0, DMEM_INDEX(x));
-	CP1W(pY, 0, DMEM_INDEX(y));
-	CP1W(pD, 0, DMEM_INDEX(d));
-
-	/* (over)write first words to ensure pairwise mismatch. */
-	CP1W(k, 0, 1);
-	CP1W(rnd, 0, 2);
-	CP1W(msg, 0, 3);
-	CP1W(r, 0, 4);
-	CP1W(s, 0, 5);
-	CP1W(x, 0, 6);
-	CP1W(y, 0, 7);
-	CP1W(d, 0, 8);
-}
-
-int dcrypto_p256_ecdsa_sign(struct drbg_ctx *drbg, const p256_int *key,
-			    const p256_int *message, p256_int *r, p256_int *s)
-{
-	int i, result;
-	p256_int rnd, k;
-
-	dcrypto_init_and_lock();
-	dcrypto_ecc_init();
-	result = dcrypto_call(CF_p256init_adr);
-
-	/* Pick uniform 0 < k < R */
-	do {
-		hmac_drbg_generate_p256(drbg, &rnd);
-	} while (p256_cmp(&SECP256r1_nMin2, &rnd) < 0);
-	drbg_exit(drbg);
-
-	p256_add_d(&rnd, 1, &k);
-
-	CP8W(k, &k);
-
-	for (i = 0; i < 8; ++i)
-		CP1W(rnd, i, rand());
-
-	/* Wipe temp rnd,k */
-	rnd = dmem_ecc->rnd;
-	k = dmem_ecc->rnd;
-
-	CP8W(msg, message);
-	CP8W(d, key);
-
-	result |= dcrypto_call(CF_p256sign_adr);
-
-	*r = dmem_ecc->r;
-	*s = dmem_ecc->s;
-
-	/* Wipe d,k */
-	CP8W(d, &rnd);
-	CP8W(k, &rnd);
-
-	dcrypto_unlock();
-	return result == 0;
-}
-
-int dcrypto_p256_base_point_mul(const p256_int *k, p256_int *x, p256_int *y)
-{
-	int i, result;
-
-	dcrypto_init_and_lock();
-	dcrypto_ecc_init();
-	result = dcrypto_call(CF_p256init_adr);
-
-	for (i = 0; i < 8; ++i)
-		CP1W(rnd, i, dmem_ecc->rnd.a[i] ^ rand());
-
-	CP8W(d, k);
-
-	result |= dcrypto_call(CF_p256scalarbasemult_adr);
-
-	*x = dmem_ecc->x;
-	*y = dmem_ecc->y;
-
-	/* Wipe d */
-	CP8W(d, &dmem_ecc->rnd);
-
-	dcrypto_unlock();
-	return result == 0;
-}
-
-int dcrypto_p256_point_mul(const p256_int *k, const p256_int *in_x,
-			   const p256_int *in_y, p256_int *x, p256_int *y)
-{
-	int i, result;
-
-	dcrypto_init_and_lock();
-	dcrypto_ecc_init();
-	result = dcrypto_call(CF_p256init_adr);
-
-	for (i = 0; i < 8; ++i)
-		CP1W(rnd, i, dmem_ecc->rnd.a[i] ^ rand());
-
-	CP8W(k, k);
-	CP8W(x, in_x);
-	CP8W(y, in_y);
-
-	result |= dcrypto_call(CF_p256scalarmult_adr);
-
-	*x = dmem_ecc->x;
-	*y = dmem_ecc->y;
-
-	/* Wipe k,x,y */
-	CP8W(k, &dmem_ecc->rnd);
-	CP8W(x, &dmem_ecc->rnd);
-	CP8W(y, &dmem_ecc->rnd);
-
-	dcrypto_unlock();
-	return result == 0;
-}
-
-int dcrypto_p256_ecdsa_verify(const p256_int *key_x, const p256_int *key_y,
-			      const p256_int *message, const p256_int *r,
-			      const p256_int *s)
-{
-	int i, result;
-
-	dcrypto_init_and_lock();
-	dcrypto_ecc_init();
-	result = dcrypto_call(CF_p256init_adr);
-
-	CP8W(msg, message);
-	CP8W(r, r);
-	CP8W(s, s);
-	CP8W(x, key_x);
-	CP8W(y, key_y);
-
-	result |= dcrypto_call(CF_p256verify_adr);
-
-	for (i = 0; i < 8; ++i)
-		result |= (dmem_ecc->rnd.a[i] ^ r->a[i]);
-
-	dcrypto_unlock();
-	return result == 0;
-}
-
-int dcrypto_p256_is_valid_point(const p256_int *x, const p256_int *y)
-{
-	int i, result;
-
-	dcrypto_init_and_lock();
-	dcrypto_ecc_init();
-	result = dcrypto_call(CF_p256init_adr);
-
-	CP8W(x, x);
-	CP8W(y, y);
-
-	result |= dcrypto_call(CF_p256isoncurve_adr);
-
-	for (i = 0; i < 8; ++i)
-		result |= (dmem_ecc->r.a[i] ^ dmem_ecc->s.a[i]);
-
-	dcrypto_unlock();
-	return result == 0;
-}
diff --git a/chip/g/dcrypto/dcrypto_runtime.c b/chip/g/dcrypto/dcrypto_runtime.c
deleted file mode 100644
index b20f561393..0000000000
--- a/chip/g/dcrypto/dcrypto_runtime.c
+++ /dev/null
@@ -1,333 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "flash_log.h"
-#include "internal.h"
-#include "registers.h"
-#include "task.h"
-
-#define DMEM_NUM_WORDS 1024
-#define IMEM_NUM_WORDS 1024
-
-static struct mutex dcrypto_mutex;
-static volatile task_id_t my_task_id;
-static uint8_t dcrypto_is_initialized;
-
-static const uint32_t wiped_value = 0xdddddddd;
-
-static void dcrypto_reset_and_wipe(void)
-{
-	int i;
-	volatile uint32_t *ptr;
-
-	/* Reset. */
-	GREG32(CRYPTO, CONTROL) = GC_CRYPTO_CONTROL_RESET_MASK;
-	GREG32(CRYPTO, CONTROL) = 0;
-
-	/* Reset all the status bits. */
-	GREG32(CRYPTO, INT_STATE) = -1;
-
-	/* Wipe state. */
-	GREG32(CRYPTO, WIPE_SECRETS) = 1;
-
-	/* Wipe DMEM. */
-	ptr = GREG32_ADDR(CRYPTO, DMEM_DUMMY);
-	for (i = 0; i < DMEM_NUM_WORDS; ++i)
-		*ptr++ = wiped_value;
-}
-
-static void dcrypto_wipe_imem(void)
-{
-	int i;
-	volatile uint32_t *ptr;
-
-	/* Wipe IMEM. */
-	ptr = GREG32_ADDR(CRYPTO, IMEM_DUMMY);
-	for (i = 0; i < IMEM_NUM_WORDS; ++i)
-		*ptr++ = wiped_value;
-}
-
-void dcrypto_init_and_lock(void)
-{
-	mutex_lock(&dcrypto_mutex);
-	my_task_id = task_get_current();
-
-	if (dcrypto_is_initialized)
-		return;
-
-	/* Enable PMU. */
-	REG_WRITE_MLV(GR_PMU_PERICLKSET0, GC_PMU_PERICLKSET0_DCRYPTO0_CLK_MASK,
-		GC_PMU_PERICLKSET0_DCRYPTO0_CLK_LSB, 1);
-
-	dcrypto_reset_and_wipe();
-	dcrypto_wipe_imem();
-
-	/* Turn off random nops (which are enabled by default). */
-	GWRITE_FIELD(CRYPTO, RAND_STALL_CTL, STALL_EN, 0);
-	/* Configure random nop percentage at 6%. */
-	GWRITE_FIELD(CRYPTO, RAND_STALL_CTL, FREQ, 3);
-	/* Now turn on random nops. */
-	GWRITE_FIELD(CRYPTO, RAND_STALL_CTL, STALL_EN, 1);
-
-	GREG32(CRYPTO, INT_STATE) = -1;   /* Reset all the status bits. */
-	GREG32(CRYPTO, INT_ENABLE) = -1;  /* Enable all status bits. */
-
-	task_enable_irq(GC_IRQNUM_CRYPTO0_HOST_CMD_DONE_INT);
-
-	dcrypto_is_initialized = 1;
-}
-
-void dcrypto_unlock(void)
-{
-	mutex_unlock(&dcrypto_mutex);
-}
-
-#ifndef DCRYPTO_CALL_TIMEOUT_US
-#define DCRYPTO_CALL_TIMEOUT_US  (700 * 1000)
-#endif
-/*
- * When running on Cr50 this event belongs in the TPM task event space. Make
- * sure there is no collision with events defined in ./common/tpm_registers.c.
- */
-#define TASK_EVENT_DCRYPTO_DONE  TASK_EVENT_CUSTOM_BIT(0)
-
-uint32_t dcrypto_call(uint32_t adr)
-{
-	uint32_t event;
-	uint32_t state = 0;
-
-	do {
-		/* Reset all the status bits. */
-		GREG32(CRYPTO, INT_STATE) = -1;
-	} while (GREG32(CRYPTO, INT_STATE) & 3);
-
-	GREG32(CRYPTO, HOST_CMD) = 0x08000000 + adr; /* Call imem:adr. */
-
-	event = task_wait_event_mask(TASK_EVENT_DCRYPTO_DONE,
-				     DCRYPTO_CALL_TIMEOUT_US);
-	/* TODO(ngm): switch return value to an enum. */
-	switch (event) {
-	case TASK_EVENT_DCRYPTO_DONE:
-		/*
-		 * We expect only the CMD_RECV status bit to be set at this
-		 * point. CMD_DONE got cleared in the interrupt handler. Any and
-		 * all other bits are indicative of error.
-		 * Except for MOD_OPERAND_OUT_OF_RANGE, which is noise.
-		 */
-		state = GREG32(CRYPTO, INT_STATE);
-		if ((state &
-		     ~(GC_CRYPTO_INT_STATE_MOD_OPERAND_OUT_OF_RANGE_MASK |
-		       GC_CRYPTO_INT_STATE_HOST_CMD_RECV_MASK)) == 0)
-			return 0;
-		/* fall through */
-	default:
-		dcrypto_reset_and_wipe();
-#ifdef CONFIG_FLASH_LOG
-		/* State value of zero indicates event timeout. */
-		flash_log_add_event(FE_LOG_DCRYPTO_FAILURE,
-				    sizeof(state), &state);
-#endif
-		return 1;
-	}
-}
-
-void __keep dcrypto_done_interrupt(void)
-{
-	GREG32(CRYPTO, INT_STATE) = GC_CRYPTO_INT_STATE_HOST_CMD_DONE_MASK;
-	task_set_event(my_task_id, TASK_EVENT_DCRYPTO_DONE, 0);
-}
-DECLARE_IRQ(GC_IRQNUM_CRYPTO0_HOST_CMD_DONE_INT, dcrypto_done_interrupt, 1);
-
-void dcrypto_imem_load(size_t offset, const uint32_t *opcodes,
-			size_t n_opcodes)
-{
-	size_t i;
-	volatile uint32_t *ptr = GREG32_ADDR(CRYPTO, IMEM_DUMMY);
-
-	ptr += offset;
-	/* Check first word and copy all only if different. */
-	if (ptr[0] != opcodes[0]) {
-		for (i = 0; i < n_opcodes; ++i)
-			ptr[i] = opcodes[i];
-	}
-}
-
-uint32_t dcrypto_dmem_load(size_t offset, const void *words, size_t n_words)
-{
-	size_t i;
-	volatile uint32_t *ptr = GREG32_ADDR(CRYPTO, DMEM_DUMMY);
-	const uint32_t *src = (const uint32_t *) words;
-	struct access_helper *word_accessor = (struct access_helper *) src;
-	uint32_t diff = 0;
-
-	ptr += offset * 8;  /* Offset is in 256 bit addresses. */
-	for (i = 0; i < n_words; ++i) {
-		/*
-		 * The implementation of memcpy makes unaligned writes if src
-		 * is unaligned. DMEM on the other hand requires writes to be
-		 * aligned, so do a word-by-word copy manually here.
-		 */
-		uint32_t v = word_accessor[i].udata;
-
-		diff |= (ptr[i] ^ v);
-		ptr[i] = v;
-	}
-	return diff;
-}
-
-#ifdef DCRYPTO_RUNTIME_TEST
-/*
- * Add console command "dcrypto_test" that runs a couple of engine failure
- * scenarios and checks for adequate handling thereof:
- * - error return code
- * - dmem erasure on error
- * - dmem preservation on success
- */
-#include "console.h"
-
-/* AUTO-GENERATED.  DO NOT MODIFY. */
-/* clang-format off */
-static const uint32_t IMEM_test_hang[] = {
-/* @0x0: function forever[2] { */
-#define CF_forever_adr 0
-/*forever: */
-	0x10080000, /* b forever */
-	0x0c000000, /* ret */
-/* } */
-/* @0x2: function func17[2] { */
-#define CF_func17_adr 2
-	0x08000000, /* call &forever */
-	0x0c000000, /* ret */
-/* } */
-/* @0x4: function func16[2] { */
-#define CF_func16_adr 4
-	0x08000002, /* call &func17 */
-	0x0c000000, /* ret */
-/* } */
-/* @0x6: function func15[2] { */
-#define CF_func15_adr 6
-	0x08000004, /* call &func16 */
-	0x0c000000, /* ret */
-/* } */
-/* @0x8: function func14[2] { */
-#define CF_func14_adr 8
-	0x08000006, /* call &func15 */
-	0x0c000000, /* ret */
-/* } */
-/* @0xa: function func13[2] { */
-#define CF_func13_adr 10
-	0x08000008, /* call &func14 */
-	0x0c000000, /* ret */
-/* } */
-/* @0xc: function func12[2] { */
-#define CF_func12_adr 12
-	0x0800000a, /* call &func13 */
-	0x0c000000, /* ret */
-/* } */
-/* @0xe: function func11[2] { */
-#define CF_func11_adr 14
-	0x0800000c, /* call &func12 */
-	0x0c000000, /* ret */
-/* } */
-/* @0x10: function func10[2] { */
-#define CF_func10_adr 16
-	0x0800000e, /* call &func11 */
-	0x0c000000, /* ret */
-/* } */
-/* @0x12: function func9[2] { */
-#define CF_func9_adr 18
-	0x08000010, /* call &func10 */
-	0x0c000000, /* ret */
-/* } */
-/* @0x14: function func8[2] { */
-#define CF_func8_adr 20
-	0x08000012, /* call &func9 */
-	0x0c000000, /* ret */
-/* } */
-/* @0x16: function func7[2] { */
-#define CF_func7_adr 22
-	0x08000014, /* call &func8 */
-	0x0c000000, /* ret */
-/* } */
-/* @0x18: function func6[2] { */
-#define CF_func6_adr 24
-	0x08000016, /* call &func7 */
-	0x0c000000, /* ret */
-/* } */
-/* @0x1a: function func5[2] { */
-#define CF_func5_adr 26
-	0x08000018, /* call &func6 */
-	0x0c000000, /* ret */
-/* } */
-/* @0x1c: function func4[2] { */
-#define CF_func4_adr 28
-	0x0800001a, /* call &func5 */
-	0x0c000000, /* ret */
-/* } */
-/* @0x1e: function func3[2] { */
-#define CF_func3_adr 30
-	0x0800001c, /* call &func4 */
-	0x0c000000, /* ret */
-/* } */
-/* @0x20: function func2[2] { */
-#define CF_func2_adr 32
-	0x0800001e, /* call &func3 */
-	0x0c000000, /* ret */
-/* } */
-/* @0x22: function func1[2] { */
-#define CF_func1_adr 34
-	0x08000020, /* call &func2 */
-	0x0c000000, /* ret */
-/* } */
-/* @0x24: function test[2] { */
-#define CF_test_adr 36
-	0x08000022, /* call &func1 */
-	0x0c000000, /* ret */
-/* } */
-/* @0x26: function sigchk[2] { */
-#define CF_sigchk_adr 38
-	0xf8000004, /* sigini #4 */
-	0xf9ccc3c2, /* sigchk #13419458 */
-/* } */
-};
-/* clang-format on */
-
-static int command_dcrypto_test(int argc, char *argv[])
-{
-	volatile uint32_t *ptr = GREG32_ADDR(CRYPTO, DMEM_DUMMY);
-	uint32_t not_wiped = ~wiped_value;
-	int result;
-
-	dcrypto_init_and_lock();
-	dcrypto_imem_load(0, IMEM_test_hang, ARRAY_SIZE(IMEM_test_hang));
-
-	*ptr = not_wiped;
-	result = dcrypto_call(CF_func2_adr); /* max legal stack, into hang */
-	if (result != 1 || *ptr != wiped_value)
-		ccprintf("dcrypto_test: fail1 %d,%08x\n", result, *ptr);
-
-	*ptr = not_wiped;
-	result = dcrypto_call(CF_test_adr); /* stack overflow */
-	if (result != 1 || *ptr != wiped_value)
-		ccprintf("dcrypto_test: fail2 %d,%08x\n", result, *ptr);
-
-	*ptr = not_wiped;
-	result = dcrypto_call(CF_sigchk_adr); /* cfi trap */
-	if (result != 1 || *ptr != wiped_value)
-		ccprintf("dcrypto_test: fail3 %d,%08x\n", result, *ptr);
-
-	*ptr = not_wiped;
-	result = dcrypto_call(CF_test_adr + 1); /* simple ret should succeed */
-	if (result != 0 || *ptr != not_wiped)
-		ccprintf("dcrypto_test: fail4 %d,%08x\n", result, *ptr);
-
-	dcrypto_unlock();
-
-	return EC_SUCCESS;
-}
-DECLARE_SAFE_CONSOLE_COMMAND(dcrypto_test, command_dcrypto_test, "",
-			     "dcrypto test");
-
-#endif /* DCRYPTO_RUNTIME_TEST */
diff --git a/chip/g/dcrypto/dcrypto_sha512.c b/chip/g/dcrypto/dcrypto_sha512.c
deleted file mode 100644
index 4938a05421..0000000000
--- a/chip/g/dcrypto/dcrypto_sha512.c
+++ /dev/null
@@ -1,772 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "dcrypto.h"
-#include "internal.h"
-#include "registers.h"
-
-#include "cryptoc/sha512.h"
-
-#ifdef CRYPTO_TEST_SETUP
-
-/* test and benchmark */
-#include "common.h"
-#include "console.h"
-#include "hooks.h"
-#include "task.h"
-
-#define cyclecounter() GREG32(M3, DWT_CYCCNT)
-#define START_PROFILE(x)                                                       \
-	{                                                                      \
-		x -= cyclecounter();                                           \
-	}
-#define END_PROFILE(x)                                                         \
-	{                                                                      \
-		x += cyclecounter();                                           \
-	}
-static uint32_t t_sw;
-static uint32_t t_hw;
-static uint32_t t_transform;
-static uint32_t t_dcrypto;
-
-#else /* CRYPTO_TEST_SETUP */
-
-#define START_PROFILE(x)
-#define END_PROFILE(x)
-
-#endif /* CRYPTO_TEST_SETUP */
-
-/* auto-generated from go test haven -test.run=TestSha512 -test.v */
-/* clang-format off */
-static const uint32_t IMEM_dcrypto[] = {
-/* @0x0: function tag[1] { */
-#define CF_tag_adr 0
-	0xf8000003, /* sigini #3 */
-/* } */
-/* @0x1: function expandw[84] { */
-#define CF_expandw_adr 1
-	0x4c3def00, /* xor r15, r15, r15 */
-	0x803c0013, /* movi r15.0l, #19 */
-	0x80bc0016, /* movi r15.1l, #22 */
-	0x97800f00, /* ldrfp r15 */
-	0x05004003, /* loop #4 ( */
-	0x8c001800, /* ld *0, *0++ */
-	0x906c0800, /* st *0++, *3++ */
-	0xfc000000, /* nop */
-	/*		   ) */
-	0x0501004a, /* loop #16 ( */
-	0x684a6080, /* rshi r18, r0, r19 >> 128 */
-	0x68443340, /* rshi r17, r19, r1 >> 64 */
-	0x683e3201, /* rshi r15, r18, r17 >> 1 */
-	0x68423208, /* rshi r16, r18, r17 >> 8 */
-	0x4c3e0f00, /* xor r15, r15, r16 */
-	0x6843f207, /* rshi r16, r18, r31 >> 7 */
-	0x4c3e0f00, /* xor r15, r15, r16 */
-	0x505df398, /* add r23, r19, r15 >> 192 */
-	0x505eb788, /* add r23, r23, r21 >> 64 */
-	0x684ac0c0, /* rshi r18, r0, r22 >> 192 */
-	0x68443680, /* rshi r17, r22, r1 >> 128 */
-	0x683e3213, /* rshi r15, r18, r17 >> 19 */
-	0x6842323d, /* rshi r16, r18, r17 >> 61 */
-	0x4c3e0f00, /* xor r15, r15, r16 */
-	0x6843f206, /* rshi r16, r18, r31 >> 6 */
-	0x4c3e0f00, /* xor r15, r15, r16 */
-	0x505df798, /* add r23, r23, r15 >> 192 */
-	0x684a60c0, /* rshi r18, r0, r19 >> 192 */
-	0x68443380, /* rshi r17, r19, r1 >> 128 */
-	0x683e3201, /* rshi r15, r18, r17 >> 1 */
-	0x68423208, /* rshi r16, r18, r17 >> 8 */
-	0x4c3e0f00, /* xor r15, r15, r16 */
-	0x6843f207, /* rshi r16, r18, r31 >> 7 */
-	0x4c3e0f00, /* xor r15, r15, r16 */
-	0x50627f88, /* add r24, r31, r19 >> 64 */
-	0x5061f898, /* add r24, r24, r15 >> 192 */
-	0x5062b890, /* add r24, r24, r21 >> 128 */
-	0x684416c0, /* rshi r17, r22, r0 >> 192 */
-	0x683e3613, /* rshi r15, r22, r17 >> 19 */
-	0x6842363d, /* rshi r16, r22, r17 >> 61 */
-	0x4c3e0f00, /* xor r15, r15, r16 */
-	0x6843f606, /* rshi r16, r22, r31 >> 6 */
-	0x4c3e0f00, /* xor r15, r15, r16 */
-	0x5061f898, /* add r24, r24, r15 >> 192 */
-	0x684433c0, /* rshi r17, r19, r1 >> 192 */
-	0x683e3301, /* rshi r15, r19, r17 >> 1 */
-	0x68423308, /* rshi r16, r19, r17 >> 8 */
-	0x4c3e0f00, /* xor r15, r15, r16 */
-	0x6843f307, /* rshi r16, r19, r31 >> 7 */
-	0x4c3e0f00, /* xor r15, r15, r16 */
-	0x50667f90, /* add r25, r31, r19 >> 128 */
-	0x5065f998, /* add r25, r25, r15 >> 192 */
-	0x5066b998, /* add r25, r25, r21 >> 192 */
-	0x684ae040, /* rshi r18, r0, r23 >> 64 */
-	0x683ef213, /* rshi r15, r18, r23 >> 19 */
-	0x6842f23d, /* rshi r16, r18, r23 >> 61 */
-	0x4c3e0f00, /* xor r15, r15, r16 */
-	0x6843f206, /* rshi r16, r18, r31 >> 6 */
-	0x4c3e0f00, /* xor r15, r15, r16 */
-	0x5065f998, /* add r25, r25, r15 >> 192 */
-	0x684a8040, /* rshi r18, r0, r20 >> 64 */
-	0x683e9201, /* rshi r15, r18, r20 >> 1 */
-	0x68429208, /* rshi r16, r18, r20 >> 8 */
-	0x4c3e0f00, /* xor r15, r15, r16 */
-	0x6843f207, /* rshi r16, r18, r31 >> 7 */
-	0x4c3e0f00, /* xor r15, r15, r16 */
-	0x506a7f98, /* add r26, r31, r19 >> 192 */
-	0x5069fa98, /* add r26, r26, r15 >> 192 */
-	0x506ada00, /* add r26, r26, r22 */
-	0x684b0040, /* rshi r18, r0, r24 >> 64 */
-	0x683f1213, /* rshi r15, r18, r24 >> 19 */
-	0x6843123d, /* rshi r16, r18, r24 >> 61 */
-	0x4c3e0f00, /* xor r15, r15, r16 */
-	0x6843f206, /* rshi r16, r18, r31 >> 6 */
-	0x4c3e0f00, /* xor r15, r15, r16 */
-	0x5069fa98, /* add r26, r26, r15 >> 192 */
-	0x7c4c1400, /* mov r19, r20 */
-	0x7c501500, /* mov r20, r21 */
-	0x7c541600, /* mov r21, r22 */
-	0x685af640, /* rshi r22, r22, r23 >> 64 */
-	0x685b1640, /* rshi r22, r22, r24 >> 64 */
-	0x685b3640, /* rshi r22, r22, r25 >> 64 */
-	0x685b5640, /* rshi r22, r22, r26 >> 64 */
-	0x906c0100, /* st *1, *3++ */
-	/*		   ) */
-	0x0c000000, /* ret */
-/* } */
-/* @0x55: function Sha512_a[125] { */
-#define CF_Sha512_a_adr 85
-	0x68580c40, /* rshi r22, r12, r0 >> 64 */
-	0x683c161c, /* rshi r15, r22, r0 >> 28 */
-	0x68541622, /* rshi r21, r22, r0 >> 34 */
-	0x4c3eaf00, /* xor r15, r15, r21 */
-	0x68541627, /* rshi r21, r22, r0 >> 39 */
-	0x4c3eaf00, /* xor r15, r15, r21 */
-	0x40402000, /* and r16, r0, r1 */
-	0x40544000, /* and r21, r0, r2 */
-	0x4c42b000, /* xor r16, r16, r21 */
-	0x40544100, /* and r21, r1, r2 */
-	0x4c42b000, /* xor r16, r16, r21 */
-	0x68458fc0, /* rshi r17, r15, r12 >> 192 */
-	0x50461100, /* add r17, r17, r16 */
-	0x68588d40, /* rshi r22, r13, r4 >> 64 */
-	0x6848960e, /* rshi r18, r22, r4 >> 14 */
-	0x68549612, /* rshi r21, r22, r4 >> 18 */
-	0x4c4ab200, /* xor r18, r18, r21 */
-	0x684c9629, /* rshi r19, r22, r4 >> 41 */
-	0x4c4a7200, /* xor r18, r18, r19 */
-	0x404ca400, /* and r19, r4, r5 */
-	0x48548000, /* not r21, r4 */
-	0x4054d500, /* and r21, r21, r6 */
-	0x4c4eb300, /* xor r19, r19, r21 */
-	0x6851b2c0, /* rshi r20, r18, r13 >> 192 */
-	0x5050f400, /* add r20, r20, r7 */
-	0x50515480, /* add r20, r20, r10 >> 0 */
-	0x68558b00, /* rshi r21, r11, r12 >> 0 */
-	0x50567500, /* add r21, r21, r19 */
-	0x5052b400, /* add r20, r20, r21 */
-	0x500e8300, /* add r3, r3, r20 */
-	0x501e3400, /* add r7, r20, r17 */
-	0x6858ec40, /* rshi r22, r12, r7 >> 64 */
-	0x683cf61c, /* rshi r15, r22, r7 >> 28 */
-	0x6854f622, /* rshi r21, r22, r7 >> 34 */
-	0x4c3eaf00, /* xor r15, r15, r21 */
-	0x6854f627, /* rshi r21, r22, r7 >> 39 */
-	0x4c3eaf00, /* xor r15, r15, r21 */
-	0x40400700, /* and r16, r7, r0 */
-	0x40542700, /* and r21, r7, r1 */
-	0x4c42b000, /* xor r16, r16, r21 */
-	0x40542000, /* and r21, r0, r1 */
-	0x4c42b000, /* xor r16, r16, r21 */
-	0x68458fc0, /* rshi r17, r15, r12 >> 192 */
-	0x50461100, /* add r17, r17, r16 */
-	0x68586d40, /* rshi r22, r13, r3 >> 64 */
-	0x6848760e, /* rshi r18, r22, r3 >> 14 */
-	0x68547612, /* rshi r21, r22, r3 >> 18 */
-	0x4c4ab200, /* xor r18, r18, r21 */
-	0x684c7629, /* rshi r19, r22, r3 >> 41 */
-	0x4c4a7200, /* xor r18, r18, r19 */
-	0x404c8300, /* and r19, r3, r4 */
-	0x48546000, /* not r21, r3 */
-	0x4054b500, /* and r21, r21, r5 */
-	0x4c4eb300, /* xor r19, r19, r21 */
-	0x6851b2c0, /* rshi r20, r18, r13 >> 192 */
-	0x5050d400, /* add r20, r20, r6 */
-	0x50515488, /* add r20, r20, r10 >> 64 */
-	0x68558b40, /* rshi r21, r11, r12 >> 64 */
-	0x50567500, /* add r21, r21, r19 */
-	0x5052b400, /* add r20, r20, r21 */
-	0x500a8200, /* add r2, r2, r20 */
-	0x501a3400, /* add r6, r20, r17 */
-	0x6858cc40, /* rshi r22, r12, r6 >> 64 */
-	0x683cd61c, /* rshi r15, r22, r6 >> 28 */
-	0x6854d622, /* rshi r21, r22, r6 >> 34 */
-	0x4c3eaf00, /* xor r15, r15, r21 */
-	0x6854d627, /* rshi r21, r22, r6 >> 39 */
-	0x4c3eaf00, /* xor r15, r15, r21 */
-	0x4040e600, /* and r16, r6, r7 */
-	0x40540600, /* and r21, r6, r0 */
-	0x4c42b000, /* xor r16, r16, r21 */
-	0x40540700, /* and r21, r7, r0 */
-	0x4c42b000, /* xor r16, r16, r21 */
-	0x68458fc0, /* rshi r17, r15, r12 >> 192 */
-	0x50461100, /* add r17, r17, r16 */
-	0x68584d40, /* rshi r22, r13, r2 >> 64 */
-	0x6848560e, /* rshi r18, r22, r2 >> 14 */
-	0x68545612, /* rshi r21, r22, r2 >> 18 */
-	0x4c4ab200, /* xor r18, r18, r21 */
-	0x684c5629, /* rshi r19, r22, r2 >> 41 */
-	0x4c4a7200, /* xor r18, r18, r19 */
-	0x404c6200, /* and r19, r2, r3 */
-	0x48544000, /* not r21, r2 */
-	0x40549500, /* and r21, r21, r4 */
-	0x4c4eb300, /* xor r19, r19, r21 */
-	0x6851b2c0, /* rshi r20, r18, r13 >> 192 */
-	0x5050b400, /* add r20, r20, r5 */
-	0x50515490, /* add r20, r20, r10 >> 128 */
-	0x68558b80, /* rshi r21, r11, r12 >> 128 */
-	0x50567500, /* add r21, r21, r19 */
-	0x5052b400, /* add r20, r20, r21 */
-	0x50068100, /* add r1, r1, r20 */
-	0x50163400, /* add r5, r20, r17 */
-	0x6858ac40, /* rshi r22, r12, r5 >> 64 */
-	0x683cb61c, /* rshi r15, r22, r5 >> 28 */
-	0x6854b622, /* rshi r21, r22, r5 >> 34 */
-	0x4c3eaf00, /* xor r15, r15, r21 */
-	0x6854b627, /* rshi r21, r22, r5 >> 39 */
-	0x4c3eaf00, /* xor r15, r15, r21 */
-	0x4040c500, /* and r16, r5, r6 */
-	0x4054e500, /* and r21, r5, r7 */
-	0x4c42b000, /* xor r16, r16, r21 */
-	0x4054e600, /* and r21, r6, r7 */
-	0x4c42b000, /* xor r16, r16, r21 */
-	0x68458fc0, /* rshi r17, r15, r12 >> 192 */
-	0x50461100, /* add r17, r17, r16 */
-	0x68582d40, /* rshi r22, r13, r1 >> 64 */
-	0x6848360e, /* rshi r18, r22, r1 >> 14 */
-	0x68543612, /* rshi r21, r22, r1 >> 18 */
-	0x4c4ab200, /* xor r18, r18, r21 */
-	0x684c3629, /* rshi r19, r22, r1 >> 41 */
-	0x4c4a7200, /* xor r18, r18, r19 */
-	0x404c4100, /* and r19, r1, r2 */
-	0x48542000, /* not r21, r1 */
-	0x40547500, /* and r21, r21, r3 */
-	0x4c4eb300, /* xor r19, r19, r21 */
-	0x6851b2c0, /* rshi r20, r18, r13 >> 192 */
-	0x50509400, /* add r20, r20, r4 */
-	0x50515498, /* add r20, r20, r10 >> 192 */
-	0x68558bc0, /* rshi r21, r11, r12 >> 192 */
-	0x50567500, /* add r21, r21, r19 */
-	0x5052b400, /* add r20, r20, r21 */
-	0x50028000, /* add r0, r0, r20 */
-	0x50123400, /* add r4, r20, r17 */
-	0x0c000000, /* ret */
-/* } */
-/* @0xd2: function Sha512_b[125] { */
-#define CF_Sha512_b_adr 210
-	0x68588d40, /* rshi r22, r13, r4 >> 64 */
-	0x683c961c, /* rshi r15, r22, r4 >> 28 */
-	0x68549622, /* rshi r21, r22, r4 >> 34 */
-	0x4c3eaf00, /* xor r15, r15, r21 */
-	0x68549627, /* rshi r21, r22, r4 >> 39 */
-	0x4c3eaf00, /* xor r15, r15, r21 */
-	0x4040a400, /* and r16, r4, r5 */
-	0x4054c400, /* and r21, r4, r6 */
-	0x4c42b000, /* xor r16, r16, r21 */
-	0x4054c500, /* and r21, r5, r6 */
-	0x4c42b000, /* xor r16, r16, r21 */
-	0x6845afc0, /* rshi r17, r15, r13 >> 192 */
-	0x50461100, /* add r17, r17, r16 */
-	0x68580c40, /* rshi r22, r12, r0 >> 64 */
-	0x6848160e, /* rshi r18, r22, r0 >> 14 */
-	0x68541612, /* rshi r21, r22, r0 >> 18 */
-	0x4c4ab200, /* xor r18, r18, r21 */
-	0x684c1629, /* rshi r19, r22, r0 >> 41 */
-	0x4c4a7200, /* xor r18, r18, r19 */
-	0x404c2000, /* and r19, r0, r1 */
-	0x48540000, /* not r21, r0 */
-	0x40545500, /* and r21, r21, r2 */
-	0x4c4eb300, /* xor r19, r19, r21 */
-	0x685192c0, /* rshi r20, r18, r12 >> 192 */
-	0x50507400, /* add r20, r20, r3 */
-	0x50515480, /* add r20, r20, r10 >> 0 */
-	0x6855ab00, /* rshi r21, r11, r13 >> 0 */
-	0x50567500, /* add r21, r21, r19 */
-	0x5052b400, /* add r20, r20, r21 */
-	0x501e8700, /* add r7, r7, r20 */
-	0x500e3400, /* add r3, r20, r17 */
-	0x68586d40, /* rshi r22, r13, r3 >> 64 */
-	0x683c761c, /* rshi r15, r22, r3 >> 28 */
-	0x68547622, /* rshi r21, r22, r3 >> 34 */
-	0x4c3eaf00, /* xor r15, r15, r21 */
-	0x68547627, /* rshi r21, r22, r3 >> 39 */
-	0x4c3eaf00, /* xor r15, r15, r21 */
-	0x40408300, /* and r16, r3, r4 */
-	0x4054a300, /* and r21, r3, r5 */
-	0x4c42b000, /* xor r16, r16, r21 */
-	0x4054a400, /* and r21, r4, r5 */
-	0x4c42b000, /* xor r16, r16, r21 */
-	0x6845afc0, /* rshi r17, r15, r13 >> 192 */
-	0x50461100, /* add r17, r17, r16 */
-	0x6858ec40, /* rshi r22, r12, r7 >> 64 */
-	0x6848f60e, /* rshi r18, r22, r7 >> 14 */
-	0x6854f612, /* rshi r21, r22, r7 >> 18 */
-	0x4c4ab200, /* xor r18, r18, r21 */
-	0x684cf629, /* rshi r19, r22, r7 >> 41 */
-	0x4c4a7200, /* xor r18, r18, r19 */
-	0x404c0700, /* and r19, r7, r0 */
-	0x4854e000, /* not r21, r7 */
-	0x40543500, /* and r21, r21, r1 */
-	0x4c4eb300, /* xor r19, r19, r21 */
-	0x685192c0, /* rshi r20, r18, r12 >> 192 */
-	0x50505400, /* add r20, r20, r2 */
-	0x50515488, /* add r20, r20, r10 >> 64 */
-	0x6855ab40, /* rshi r21, r11, r13 >> 64 */
-	0x50567500, /* add r21, r21, r19 */
-	0x5052b400, /* add r20, r20, r21 */
-	0x501a8600, /* add r6, r6, r20 */
-	0x500a3400, /* add r2, r20, r17 */
-	0x68584d40, /* rshi r22, r13, r2 >> 64 */
-	0x683c561c, /* rshi r15, r22, r2 >> 28 */
-	0x68545622, /* rshi r21, r22, r2 >> 34 */
-	0x4c3eaf00, /* xor r15, r15, r21 */
-	0x68545627, /* rshi r21, r22, r2 >> 39 */
-	0x4c3eaf00, /* xor r15, r15, r21 */
-	0x40406200, /* and r16, r2, r3 */
-	0x40548200, /* and r21, r2, r4 */
-	0x4c42b000, /* xor r16, r16, r21 */
-	0x40548300, /* and r21, r3, r4 */
-	0x4c42b000, /* xor r16, r16, r21 */
-	0x6845afc0, /* rshi r17, r15, r13 >> 192 */
-	0x50461100, /* add r17, r17, r16 */
-	0x6858cc40, /* rshi r22, r12, r6 >> 64 */
-	0x6848d60e, /* rshi r18, r22, r6 >> 14 */
-	0x6854d612, /* rshi r21, r22, r6 >> 18 */
-	0x4c4ab200, /* xor r18, r18, r21 */
-	0x684cd629, /* rshi r19, r22, r6 >> 41 */
-	0x4c4a7200, /* xor r18, r18, r19 */
-	0x404ce600, /* and r19, r6, r7 */
-	0x4854c000, /* not r21, r6 */
-	0x40541500, /* and r21, r21, r0 */
-	0x4c4eb300, /* xor r19, r19, r21 */
-	0x685192c0, /* rshi r20, r18, r12 >> 192 */
-	0x50503400, /* add r20, r20, r1 */
-	0x50515490, /* add r20, r20, r10 >> 128 */
-	0x6855ab80, /* rshi r21, r11, r13 >> 128 */
-	0x50567500, /* add r21, r21, r19 */
-	0x5052b400, /* add r20, r20, r21 */
-	0x50168500, /* add r5, r5, r20 */
-	0x50063400, /* add r1, r20, r17 */
-	0x68582d40, /* rshi r22, r13, r1 >> 64 */
-	0x683c361c, /* rshi r15, r22, r1 >> 28 */
-	0x68543622, /* rshi r21, r22, r1 >> 34 */
-	0x4c3eaf00, /* xor r15, r15, r21 */
-	0x68543627, /* rshi r21, r22, r1 >> 39 */
-	0x4c3eaf00, /* xor r15, r15, r21 */
-	0x40404100, /* and r16, r1, r2 */
-	0x40546100, /* and r21, r1, r3 */
-	0x4c42b000, /* xor r16, r16, r21 */
-	0x40546200, /* and r21, r2, r3 */
-	0x4c42b000, /* xor r16, r16, r21 */
-	0x6845afc0, /* rshi r17, r15, r13 >> 192 */
-	0x50461100, /* add r17, r17, r16 */
-	0x6858ac40, /* rshi r22, r12, r5 >> 64 */
-	0x6848b60e, /* rshi r18, r22, r5 >> 14 */
-	0x6854b612, /* rshi r21, r22, r5 >> 18 */
-	0x4c4ab200, /* xor r18, r18, r21 */
-	0x684cb629, /* rshi r19, r22, r5 >> 41 */
-	0x4c4a7200, /* xor r18, r18, r19 */
-	0x404cc500, /* and r19, r5, r6 */
-	0x4854a000, /* not r21, r5 */
-	0x4054f500, /* and r21, r21, r7 */
-	0x4c4eb300, /* xor r19, r19, r21 */
-	0x685192c0, /* rshi r20, r18, r12 >> 192 */
-	0x50501400, /* add r20, r20, r0 */
-	0x50515498, /* add r20, r20, r10 >> 192 */
-	0x6855abc0, /* rshi r21, r11, r13 >> 192 */
-	0x50567500, /* add r21, r21, r19 */
-	0x5052b400, /* add r20, r20, r21 */
-	0x50128400, /* add r4, r4, r20 */
-	0x50023400, /* add r0, r20, r17 */
-	0x0c000000, /* ret */
-/* } */
-/* @0x14f: function compress[70] { */
-#define CF_compress_adr 335
-	0xfc000000, /* nop */
-	0x4c7fff00, /* xor r31, r31, r31 */
-	0x4c000000, /* xor r0, r0, r0 */
-	0x4c042100, /* xor r1, r1, r1 */
-	0x55000001, /* subi r0, r0, #1 */
-	0x55040101, /* subi r1, r1, #1 */
-	0x84204100, /* ldi r8, [#8] */
-	0x94800800, /* ldlc r8 */
-	0x4c3def00, /* xor r15, r15, r15 */
-	0x803c000a, /* movi r15.0l, #10 */
-	0x95800f00, /* lddmp r15 */
-	0x06000039, /* loop *0 ( */
-	0x953c0000, /* stdmp r15 */
-	0x81bc002a, /* movi r15.3l, #42 */
-	0x95800f00, /* lddmp r15 */
-	0x08000001, /* call &expandw */
-	0x84004000, /* ldi r0, [#0] */
-	0x84044020, /* ldi r1, [#1] */
-	0x84084040, /* ldi r2, [#2] */
-	0x840c4060, /* ldi r3, [#3] */
-	0x84104080, /* ldi r4, [#4] */
-	0x841440a0, /* ldi r5, [#5] */
-	0x841840c0, /* ldi r6, [#6] */
-	0x841c40e0, /* ldi r7, [#7] */
-	0x4c3def00, /* xor r15, r15, r15 */
-	0x803c0060, /* movi r15.0l, #96 */
-	0x80bc000a, /* movi r15.1l, #10 */
-	0x813c000b, /* movi r15.2l, #11 */
-	0x96800f00, /* lddrp r15 */
-	0x97800f00, /* ldrfp r15 */
-	0x953c0000, /* stdmp r15 */
-	0x81bc002a, /* movi r15.3l, #42 */
-	0x95800f00, /* lddmp r15 */
-	0x4c318c00, /* xor r12, r12, r12 */
-	0x4c35ad00, /* xor r13, r13, r13 */
-	0x55300c01, /* subi r12, r12, #1 */
-	0x55340d01, /* subi r13, r13, #1 */
-	0x0500a007, /* loop #10 ( */
-	0x8c440800, /* ldc *1, *0++ */
-	0x8c081b00, /* ld *2, *3++ */
-	0x08000055, /* call &Sha512_a */
-	0x8c440800, /* ldc *1, *0++ */
-	0x8c081b00, /* ld *2, *3++ */
-	0x080000d2, /* call &Sha512_b */
-	0xfc000000, /* nop */
-	/*		   ) */
-	0x843c4000, /* ldi r15, [#0] */
-	0x5001e000, /* add r0, r0, r15 */
-	0x843c4020, /* ldi r15, [#1] */
-	0x5005e100, /* add r1, r1, r15 */
-	0x843c4040, /* ldi r15, [#2] */
-	0x5009e200, /* add r2, r2, r15 */
-	0x843c4060, /* ldi r15, [#3] */
-	0x500de300, /* add r3, r3, r15 */
-	0x843c4080, /* ldi r15, [#4] */
-	0x5011e400, /* add r4, r4, r15 */
-	0x843c40a0, /* ldi r15, [#5] */
-	0x5015e500, /* add r5, r5, r15 */
-	0x843c40c0, /* ldi r15, [#6] */
-	0x5019e600, /* add r6, r6, r15 */
-	0x843c40e0, /* ldi r15, [#7] */
-	0x501de700, /* add r7, r7, r15 */
-	0x88004000, /* sti r0, [#0] */
-	0x88044020, /* sti r1, [#1] */
-	0x88084040, /* sti r2, [#2] */
-	0x880c4060, /* sti r3, [#3] */
-	0x88104080, /* sti r4, [#4] */
-	0x881440a0, /* sti r5, [#5] */
-	0x881840c0, /* sti r6, [#6] */
-	0x881c40e0, /* sti r7, [#7] */
-	/*		   ) */
-	0x0c000000, /* ret */
-	/* } */
-};
-/* clang-format on */
-
-struct DMEM_sha512 {
-	uint64_t H0[4];
-	uint64_t H1[4];
-	uint64_t H2[4];
-	uint64_t H3[4];
-	uint64_t H4[4];
-	uint64_t H5[4];
-	uint64_t H6[4];
-	uint64_t H7[4];
-	uint32_t nblocks;
-	uint32_t unused[2 * 8 - 1];
-	uint32_t input[4 * 8 * 8]; // dmem[10..41]
-};
-
-static void copy_words(const void *in, uint32_t *dst, size_t nwords)
-{
-	const uint32_t *src = (const uint32_t *) in;
-
-	do {
-		uint32_t w1 = __builtin_bswap32(*src++);
-		uint32_t w2 = __builtin_bswap32(*src++);
-		*dst++ = w2;
-		*dst++ = w1;
-	} while (nwords -= 2);
-}
-
-static void dcrypto_SHA512_setup(void)
-{
-	dcrypto_imem_load(0, IMEM_dcrypto, ARRAY_SIZE(IMEM_dcrypto));
-}
-
-static void dcrypto_SHA512_Transform(LITE_SHA512_CTX *ctx, const uint32_t *buf,
-				     size_t nwords)
-{
-	int result = 0;
-	struct DMEM_sha512 *p512 =
-	    (struct DMEM_sha512 *) GREG32_ADDR(CRYPTO, DMEM_DUMMY);
-
-	START_PROFILE(t_transform)
-
-	/* Pass in H[] */
-	p512->H0[0] = ctx->state[0];
-	p512->H1[0] = ctx->state[1];
-	p512->H2[0] = ctx->state[2];
-	p512->H3[0] = ctx->state[3];
-	p512->H4[0] = ctx->state[4];
-	p512->H5[0] = ctx->state[5];
-	p512->H6[0] = ctx->state[6];
-	p512->H7[0] = ctx->state[7];
-
-	p512->nblocks = nwords / 32;
-
-	/* Pass in buf[] */
-	copy_words(buf, p512->input, nwords);
-
-	START_PROFILE(t_dcrypto)
-	result |= dcrypto_call(CF_compress_adr);
-	END_PROFILE(t_dcrypto)
-
-	/* Retrieve new H[] */
-	ctx->state[0] = p512->H0[0];
-	ctx->state[1] = p512->H1[0];
-	ctx->state[2] = p512->H2[0];
-	ctx->state[3] = p512->H3[0];
-	ctx->state[4] = p512->H4[0];
-	ctx->state[5] = p512->H5[0];
-	ctx->state[6] = p512->H6[0];
-	ctx->state[7] = p512->H7[0];
-
-	/* TODO: errno or such to capture errors */
-	(void) (result == 0);
-
-	END_PROFILE(t_transform)
-}
-
-static void dcrypto_SHA512_update(LITE_SHA512_CTX *ctx, const void *data,
-				  size_t len)
-{
-	int i = (int) (ctx->count & (sizeof(ctx->buf) - 1));
-	const uint8_t *p = (const uint8_t *) data;
-	uint8_t *d = &ctx->buf[i];
-
-	ctx->count += len;
-
-	dcrypto_init_and_lock();
-	dcrypto_SHA512_setup();
-
-	/* Take fast path for 32-bit aligned 1KB inputs */
-	if (i == 0 && len == 1024 && (((intptr_t) data) & 3) == 0) {
-		dcrypto_SHA512_Transform(ctx, (const uint32_t *) data, 8 * 32);
-	} else {
-		if (len <= sizeof(ctx->buf) - i) {
-			memcpy(d, p, len);
-			if (len == sizeof(ctx->buf) - i) {
-				dcrypto_SHA512_Transform(
-				    ctx, (uint32_t *) (ctx->buf), 32);
-			}
-		} else {
-			memcpy(d, p, sizeof(ctx->buf) - i);
-			dcrypto_SHA512_Transform(ctx, (uint32_t *) (ctx->buf),
-						 32);
-			d = ctx->buf;
-			len -= (sizeof(ctx->buf) - i);
-			p += (sizeof(ctx->buf) - i);
-			while (len >= sizeof(ctx->buf)) {
-				memcpy(d, p, sizeof(ctx->buf));
-				p += sizeof(ctx->buf);
-				len -= sizeof(ctx->buf);
-				dcrypto_SHA512_Transform(
-				    ctx, (uint32_t *) (ctx->buf), 32);
-			}
-			/* Leave remainder in ctx->buf */
-			memcpy(d, p, len);
-		}
-	}
-	dcrypto_unlock();
-}
-
-static const uint8_t *dcrypto_SHA512_final(LITE_SHA512_CTX *ctx)
-{
-	uint64_t cnt = ctx->count * 8;
-	int i = (int) (ctx->count & (sizeof(ctx->buf) - 1));
-	uint8_t *p = &ctx->buf[i];
-
-	*p++ = 0x80;
-	i++;
-
-	dcrypto_init_and_lock();
-	dcrypto_SHA512_setup();
-
-	if (i > sizeof(ctx->buf) - 16) {
-		memset(p, 0, sizeof(ctx->buf) - i);
-		dcrypto_SHA512_Transform(ctx, (uint32_t *) (ctx->buf), 32);
-		i = 0;
-		p = ctx->buf;
-	}
-
-	memset(p, 0, sizeof(ctx->buf) - 8 - i);
-	p += sizeof(ctx->buf) - 8 - i;
-
-	for (i = 0; i < 8; ++i) {
-		uint8_t tmp = (uint8_t)(cnt >> 56);
-		cnt <<= 8;
-		*p++ = tmp;
-	}
-
-	dcrypto_SHA512_Transform(ctx, (uint32_t *) (ctx->buf), 32);
-
-	p = ctx->buf;
-	for (i = 0; i < 8; i++) {
-		uint64_t tmp = ctx->state[i];
-		*p++ = (uint8_t)(tmp >> 56);
-		*p++ = (uint8_t)(tmp >> 48);
-		*p++ = (uint8_t)(tmp >> 40);
-		*p++ = (uint8_t)(tmp >> 32);
-		*p++ = (uint8_t)(tmp >> 24);
-		*p++ = (uint8_t)(tmp >> 16);
-		*p++ = (uint8_t)(tmp >> 8);
-		*p++ = (uint8_t)(tmp >> 0);
-	}
-
-	dcrypto_unlock();
-	return ctx->buf;
-}
-
-const uint8_t *DCRYPTO_SHA512_hash(const void *data, size_t len,
-				   uint8_t *digest)
-{
-	LITE_SHA512_CTX ctx;
-
-	DCRYPTO_SHA512_init(&ctx);
-	dcrypto_SHA512_update(&ctx, data, len);
-	memcpy(digest, dcrypto_SHA512_final(&ctx), SHA512_DIGEST_SIZE);
-
-	return digest;
-}
-
-static const HASH_VTAB dcrypto_SHA512_VTAB = {
-	DCRYPTO_SHA512_init, dcrypto_SHA512_update, dcrypto_SHA512_final,
-	DCRYPTO_SHA512_hash, SHA512_DIGEST_SIZE, SHA512_BLOCK_SIZE};
-
-void DCRYPTO_SHA512_init(LITE_SHA512_CTX *ctx)
-{
-	SHA512_init(ctx);
-	ctx->f = &dcrypto_SHA512_VTAB;
-}
-
-#ifdef CRYPTO_TEST_SETUP
-
-static uint32_t msg[256]; // 1KB
-static int msg_len;
-static int msg_loops;
-static LITE_SHA512_CTX sw;
-static LITE_SHA512_CTX hw;
-static const uint8_t *sw_digest;
-static const uint8_t *hw_digest;
-static uint32_t t_sw;
-static uint32_t t_hw;
-
-static void run_sha512_cmd(void)
-{
-	int i;
-
-	t_transform = 0;
-	t_dcrypto = 0;
-	t_sw = 0;
-	t_hw = 0;
-
-	START_PROFILE(t_sw)
-	SHA512_init(&sw);
-	for (i = 0; i < msg_loops; ++i) {
-		HASH_update(&sw, msg, msg_len);
-	}
-	sw_digest = HASH_final(&sw);
-	END_PROFILE(t_sw)
-
-	START_PROFILE(t_hw)
-	DCRYPTO_SHA512_init(&hw);
-	for (i = 0; i < msg_loops; ++i) {
-		HASH_update(&hw, msg, msg_len);
-	}
-	hw_digest = HASH_final(&hw);
-	END_PROFILE(t_hw)
-
-	ccprintf("sw(%u):\n", t_sw);
-	for (i = 0; i < 64; ++i)
-		ccprintf("%02x", sw_digest[i]);
-	ccprintf("\n");
-
-	ccprintf("hw(%u/%u/%u):\n", t_hw, t_transform, t_dcrypto);
-	for (i = 0; i < 64; ++i)
-		ccprintf("%02x", hw_digest[i]);
-	ccprintf("\n");
-
-	task_set_event(TASK_ID_CONSOLE, TASK_EVENT_CUSTOM_BIT(0), 0);
-}
-DECLARE_DEFERRED(run_sha512_cmd);
-
-static int cmd_sha512_bench(int argc, char *argv[])
-{
-	const int max_time = 1000000;
-	uint32_t events;
-
-	memset(msg, '!', sizeof(msg));
-
-	if (argc > 1) {
-		msg_loops = 1;
-		msg_len = strlen(argv[1]);
-		memcpy(msg, argv[1], msg_len);
-	} else {
-		msg_loops = 64; // benchmark 64K
-		msg_len = sizeof(msg);
-	}
-
-	hook_call_deferred(&run_sha512_cmd_data, 0);
-	ccprintf("Will wait up to %d ms\n", (max_time + 500) / 1000);
-
-	events = task_wait_event_mask(TASK_EVENT_CUSTOM_BIT(0), max_time);
-	if (!(events & TASK_EVENT_CUSTOM_BIT(0))) {
-		ccprintf("Timed out, you might want to reboot...\n");
-		return EC_ERROR_TIMEOUT;
-	}
-
-	return EC_SUCCESS;
-}
-DECLARE_SAFE_CONSOLE_COMMAND(sha512_bench, cmd_sha512_bench, NULL, NULL);
-
-static void run_sha512_test(void)
-{
-	int i;
-
-	for (i = 0; i < 129; ++i) {
-		memset(msg, i, i);
-
-		SHA512_init(&sw);
-		HASH_update(&sw, msg, i);
-		sw_digest = HASH_final(&sw);
-
-		DCRYPTO_SHA512_init(&hw);
-		HASH_update(&hw, msg, i);
-		hw_digest = HASH_final(&hw);
-
-		if (memcmp(sw_digest, hw_digest, SHA512_DIGEST_SIZE) != 0) {
-			ccprintf("sha512 self-test fail at %d!\n", i);
-			cflush();
-		}
-	}
-
-	ccprintf("sha512 self-test PASS!\n");
-	task_set_event(TASK_ID_CONSOLE, TASK_EVENT_CUSTOM_BIT(0), 0);
-}
-DECLARE_DEFERRED(run_sha512_test);
-
-static int cmd_sha512_test(int argc, char *argv[])
-{
-	hook_call_deferred(&run_sha512_test_data, 0);
-	task_wait_event_mask(TASK_EVENT_CUSTOM_BIT(0), 1000000);
-	return EC_SUCCESS;
-}
-DECLARE_SAFE_CONSOLE_COMMAND(sha512_test, cmd_sha512_test, NULL, NULL);
-
-#endif /* CRYPTO_TEST_SETUP */
diff --git a/chip/g/dcrypto/gcm.c b/chip/g/dcrypto/gcm.c
deleted file mode 100644
index cd035bbd54..0000000000
--- a/chip/g/dcrypto/gcm.c
+++ /dev/null
@@ -1,345 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "dcrypto.h"
-#include "internal.h"
-#include "registers.h"
-
-#include "endian.h"
-
-#include "cryptoc/util.h"
-
-static void gcm_mul(uint32_t *counter)
-{
-	int i;
-	volatile uint32_t *p;
-
-	/* Set HASH to zero. */
-	p = GREG32_ADDR(KEYMGR, GCM_HASH_IN0);
-	for (i = 0; i < 4; i++)
-		*p++ = 0;
-
-	/* Initialize GMAC. */
-	p = GREG32_ADDR(KEYMGR, GCM_MAC0);
-	for (i = 0; i < 4; i++)
-		*p++ = counter[i];
-
-	/* Crank GMAC. */
-	GREG32(KEYMGR, GCM_DO_ACC) = 1;
-
-	/* Read GMAC. */
-	p = GREG32_ADDR(KEYMGR, GCM_MAC0);
-	for (i = 0; i < 4; i++)
-		counter[i] = *p++;
-
-	/* Reset GMAC. */
-	p = GREG32_ADDR(KEYMGR, GCM_MAC0);
-	for (i = 0; i < 4; ++i)
-		*p++ = 0;
-}
-
-static void gcm_init_iv(
-	const uint8_t *iv, uint32_t iv_len, uint32_t *counter)
-{
-
-	if (iv_len == 12) {
-		memcpy(counter, iv, 12);
-		counter[3] = BIT(24);
-	} else {
-		size_t i;
-		uint32_t len = iv_len;
-		uint64_t len0 = len;
-		uint8_t *ctr = (uint8_t *) counter;
-
-		memset(ctr, 0, 16);
-		while (len >= 16) {
-			for (i = 0; i < 16; ++i)
-				ctr[i] ^= iv[i];
-
-			gcm_mul(counter);
-			iv += 16;
-			len -= 16;
-		}
-		if (len) {
-			for (i = 0; i < len; ++i)
-				ctr[i] ^= iv[i];
-
-			gcm_mul(counter);
-		}
-		len0 <<= 3;
-		ctr[8] ^= (uint8_t)(len0 >> 56);
-		ctr[9] ^= (uint8_t)(len0 >> 48);
-		ctr[10] ^= (uint8_t)(len0 >> 40);
-		ctr[11] ^= (uint8_t)(len0 >> 32);
-		ctr[12] ^= (uint8_t)(len0 >> 24);
-		ctr[13] ^= (uint8_t)(len0 >> 16);
-		ctr[14] ^= (uint8_t)(len0 >> 8);
-		ctr[15] ^= (uint8_t)(len0);
-
-		gcm_mul(counter);
-	}
-}
-
-void DCRYPTO_gcm_init(struct GCM_CTX *ctx, uint32_t key_bits,
-		const uint8_t *key, const uint8_t *iv, size_t iv_len)
-{
-	int i;
-	const uint32_t zero[4] = {0, 0, 0, 0};
-	uint32_t H[4];
-	uint32_t counter[4];
-
-	memset(ctx, 0, sizeof(struct GCM_CTX));
-
-	/* Initialize AES engine in CTR mode, and set the counter to 0. */
-	DCRYPTO_aes_init(key, key_bits, (const uint8_t *) zero,
-			 CIPHER_MODE_CTR, ENCRYPT_MODE);
-	/* Set H to AES(ZERO). */
-	DCRYPTO_aes_block((const uint8_t *) zero, (uint8_t *) H);
-
-	/* Initialize the GMAC accumulator to ZERO. */
-	for (i = 0; i < 4; i++)
-		GR_KEYMGR_GCM_MAC(i) = zero[i];
-
-	/* Initialize H. */
-	for (i = 0; i < 4; i++)
-		GR_KEYMGR_GCM_H(i) = H[i];
-
-	/* Map the IV to a 128-bit counter. */
-	gcm_init_iv(iv, iv_len, counter);
-
-	/* Re-initialize the IV counter. */
-	for (i = 0; i < 4; i++)
-		GR_KEYMGR_AES_CTR(i) = counter[i];
-
-	/* Calculate Ej0: encrypt IV counter XOR ZERO. */
-	DCRYPTO_aes_block((const uint8_t *) zero, ctx->Ej0.c);
-}
-
-static void gcm_aad_block(const struct GCM_CTX *ctx, const uint32_t *block)
-{
-	int i;
-	const struct access_helper *p = (struct access_helper *) block;
-
-	if (ctx->aad_len == 0 && ctx->count <= 16) {
-		/* Update GMAC. */
-		for (i = 0; i < 4; i++)
-			GR_KEYMGR_GCM_MAC(i) = p[i].udata;
-	} else {
-		for (i = 0; i < 4; i++)
-			GR_KEYMGR_GCM_HASH_IN(i) = p[i].udata;
-
-		/* Crank GMAC. */
-		GREG32(KEYMGR, GCM_DO_ACC) = 1;
-	}
-}
-
-void DCRYPTO_gcm_aad(struct GCM_CTX *ctx, const uint8_t *aad_data, size_t len)
-{
-	uint32_t block[4];
-
-	while (len) {
-		size_t count;
-
-		memset(block, 0, sizeof(block));
-		count = MIN(16, len);
-		memcpy(block, aad_data, count);
-
-		gcm_aad_block(ctx, block);
-		ctx->aad_len += count;
-
-		len -= count;
-		aad_data += count;
-	}
-
-	always_memset(block, 0, sizeof(block));
-}
-
-int DCRYPTO_gcm_encrypt(struct GCM_CTX *ctx, uint8_t *out, size_t out_len,
-			const uint8_t *in, size_t in_len)
-{
-	uint8_t *outp = out;
-
-	if (out_len < (in_len & ~0x0F) + ((in_len & 0x0F) ? 16 : 0))
-		return -1;
-
-	/* Process a previous partial block, if any. */
-	if (ctx->remainder) {
-		size_t count = MIN(in_len, 16 - ctx->remainder);
-
-		memcpy(ctx->block.c + ctx->remainder, in, count);
-		ctx->remainder += count;
-		if (ctx->remainder < 16)
-			return 0;
-
-		DCRYPTO_aes_block(ctx->block.c, outp);
-		ctx->count += 16;
-		gcm_aad_block(ctx, (uint32_t *) outp);
-		ctx->remainder = 0;
-		in += count;
-		in_len -= count;
-		outp += 16;
-	}
-
-	while (in_len >= 16) {
-		DCRYPTO_aes_block(in, outp);
-		ctx->count += 16;
-
-		gcm_aad_block(ctx, (uint32_t *) outp);
-
-		in_len -= 16;
-		in += 16;
-		outp += 16;
-	}
-
-	if (in_len) {
-		memcpy(ctx->block.c, in, in_len);
-		ctx->remainder = in_len;
-	}
-
-	return outp - out;
-}
-
-int DCRYPTO_gcm_encrypt_final(struct GCM_CTX *ctx, uint8_t *out, size_t out_len)
-{
-	if (out_len < ctx->remainder)
-		return -1;
-
-	if (ctx->remainder) {
-		size_t remainder = ctx->remainder;
-		uint8_t out_block[16];
-
-		DCRYPTO_aes_block(ctx->block.c, out_block);
-		ctx->count += ctx->remainder;
-		memcpy(out, out_block, ctx->remainder);
-
-		memset(out_block + ctx->remainder, 0, 16 - ctx->remainder);
-		gcm_aad_block(ctx, (uint32_t *) out_block);
-		ctx->remainder = 0;
-		return remainder;
-	}
-
-	return 0;
-}
-
-int DCRYPTO_gcm_decrypt(struct GCM_CTX *ctx, uint8_t *out, size_t out_len,
-			const uint8_t *in, size_t in_len)
-{
-	uint8_t *outp = out;
-
-	if (out_len < (in_len & ~0x0F) + ((in_len & 0x0F) ? 16 : 0))
-		return -1;
-
-	if (ctx->remainder) {
-		size_t count = MIN(in_len, 16 - ctx->remainder);
-
-		memcpy(ctx->block.c + ctx->remainder, in, count);
-		ctx->remainder += count;
-
-		if (ctx->remainder < 16)
-			return 0;
-
-		DCRYPTO_aes_block(ctx->block.c, outp);
-		ctx->remainder = 0;
-		ctx->count += 16;
-		gcm_aad_block(ctx, ctx->block.d);
-		in += count;
-		in_len -= count;
-		outp += count;
-	}
-
-	while (in_len >= 16) {
-		DCRYPTO_aes_block(in, outp);
-		ctx->count += 16;
-		gcm_aad_block(ctx, (uint32_t *) in);
-		in += 16;
-		in_len -= 16;
-		outp += 16;
-	}
-
-	if (in_len) {
-		memcpy(ctx->block.c, in, in_len);
-		ctx->remainder = in_len;
-	}
-
-	return outp - out;
-}
-
-int DCRYPTO_gcm_decrypt_final(struct GCM_CTX *ctx,
-			uint8_t *out, size_t out_len)
-{
-	if (out_len < ctx->remainder)
-		return -1;
-
-	if (ctx->remainder) {
-		size_t remainder = ctx->remainder;
-		uint8_t out_block[16];
-
-		DCRYPTO_aes_block(ctx->block.c, out_block);
-		ctx->count += ctx->remainder;
-		memcpy(out, out_block, ctx->remainder);
-
-		memset(ctx->block.c + ctx->remainder, 0, 16 - ctx->remainder);
-		gcm_aad_block(ctx, ctx->block.d);
-		ctx->remainder = 0;
-		return remainder;
-	}
-
-	return 0;
-}
-
-static void dcrypto_gcm_len_vector(
-	const struct GCM_CTX *ctx, void *len_vector) {
-	uint64_t aad_be;
-	uint64_t count_be;
-
-	/* Serialize counters to bit-count (big-endian). */
-	aad_be = ctx->aad_len * 8;
-	aad_be = htobe64(aad_be);
-	count_be = ctx->count * 8;
-	count_be = htobe64(count_be);
-
-	memcpy(len_vector, &aad_be, 8);
-	memcpy(((uint8_t *)len_vector) + 8, &count_be, 8);
-}
-
-static void dcrypto_gcm_tag(const struct GCM_CTX *ctx,
-			const uint32_t *len_vector, uint32_t *tag) {
-	int i;
-
-	for (i = 0; i < 4; i++)
-		GR_KEYMGR_GCM_HASH_IN(i) = len_vector[i];
-
-	/* Crank GMAC. */
-	GREG32(KEYMGR, GCM_DO_ACC) = 1;
-
-	for (i = 0; i < 4; i++)
-		GR_KEYMGR_GCM_HASH_IN(i) = ctx->Ej0.d[i];
-
-	/* Crank GMAC. */
-	GREG32(KEYMGR, GCM_DO_ACC) = 1;
-
-	/* Read tag. */
-	for (i = 0; i < 4; i++)
-		tag[i] = GR_KEYMGR_GCM_MAC(i);
-}
-
-int DCRYPTO_gcm_tag(struct GCM_CTX *ctx, uint8_t *tag, size_t tag_len)
-{
-	uint32_t len_vector[4];
-	uint32_t local_tag[4];
-	size_t count = MIN(tag_len, sizeof(local_tag));
-
-	dcrypto_gcm_len_vector(ctx, len_vector);
-	dcrypto_gcm_tag(ctx, len_vector, local_tag);
-
-	memcpy(tag, local_tag, count);
-	return count;
-}
-
-void DCRYPTO_gcm_finish(struct GCM_CTX *ctx)
-{
-	always_memset(ctx, 0, sizeof(struct GCM_CTX));
-	GREG32(KEYMGR, AES_WIPE_SECRETS) = 1;
-}
diff --git a/chip/g/dcrypto/hkdf.c b/chip/g/dcrypto/hkdf.c
deleted file mode 100644
index 3afdc6b2eb..0000000000
--- a/chip/g/dcrypto/hkdf.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-/* An implementation of HKDF as per RFC 5869. */
-
-#include "dcrypto.h"
-#include "internal.h"
-
-#include "cryptoc/sha256.h"
-#include "cryptoc/util.h"
-
-static int hkdf_extract(uint8_t *PRK, const uint8_t *salt, size_t salt_len,
-			const uint8_t *IKM, size_t IKM_len)
-{
-	LITE_HMAC_CTX ctx;
-
-	if (PRK == NULL)
-		return 0;
-	if (salt == NULL && salt_len > 0)
-		return 0;
-	if (IKM == NULL && IKM_len > 0)
-		return 0;
-
-	DCRYPTO_HMAC_SHA256_init(&ctx, salt, salt_len);
-	HASH_update(&ctx.hash, IKM, IKM_len);
-	memcpy(PRK, DCRYPTO_HMAC_final(&ctx), SHA256_DIGEST_SIZE);
-	return 1;
-}
-
-static int hkdf_expand(uint8_t *OKM, size_t OKM_len, const uint8_t *PRK,
-		const uint8_t *info, size_t info_len)
-{
-	uint8_t count = 1;
-	const uint8_t *T = OKM;
-	size_t T_len = 0;
-	uint32_t num_blocks = (OKM_len / SHA256_DIGEST_SIZE) +
-		(OKM_len % SHA256_DIGEST_SIZE ? 1 : 0);
-
-	if (OKM == NULL || OKM_len == 0)
-		return 0;
-	if (PRK == NULL)
-		return 0;
-	if (info == NULL && info_len > 0)
-		return 0;
-	if (num_blocks > 255)
-		return 0;
-
-	while (OKM_len > 0) {
-		LITE_HMAC_CTX ctx;
-		const size_t block_size = OKM_len < SHA256_DIGEST_SIZE ?
-			OKM_len : SHA256_DIGEST_SIZE;
-
-		DCRYPTO_HMAC_SHA256_init(&ctx, PRK, SHA256_DIGEST_SIZE);
-		HASH_update(&ctx.hash, T, T_len);
-		HASH_update(&ctx.hash, info, info_len);
-		HASH_update(&ctx.hash, &count, sizeof(count));
-		memcpy(OKM, DCRYPTO_HMAC_final(&ctx), block_size);
-
-		T += T_len;
-		T_len = SHA256_DIGEST_SIZE;
-		count += 1;
-		OKM += block_size;
-		OKM_len -= block_size;
-	}
-	return 1;
-}
-
-int DCRYPTO_hkdf(uint8_t *OKM, size_t OKM_len,
-		const uint8_t *salt, size_t salt_len,
-		const uint8_t *IKM, size_t IKM_len,
-		const uint8_t *info, size_t info_len)
-{
-	int result;
-	uint8_t PRK[SHA256_DIGEST_SIZE];
-
-	if (!hkdf_extract(PRK, salt, salt_len, IKM, IKM_len))
-		return 0;
-
-	result = hkdf_expand(OKM, OKM_len, PRK, info, info_len);
-	always_memset(PRK, 0, sizeof(PRK));
-	return result;
-}
diff --git a/chip/g/dcrypto/hmac.c b/chip/g/dcrypto/hmac.c
deleted file mode 100644
index ad0f01b126..0000000000
--- a/chip/g/dcrypto/hmac.c
+++ /dev/null
@@ -1,61 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "internal.h"
-#include "dcrypto.h"
-
-#include <stdint.h>
-
-#include "cryptoc/sha256.h"
-#include "cryptoc/util.h"
-
-/* TODO(ngm): add support for hardware hmac. */
-static void HMAC_init(LITE_HMAC_CTX *ctx, const void *key, unsigned int len)
-{
-	unsigned int i;
-
-	memset(&ctx->opad[0], 0, sizeof(ctx->opad));
-	/* Initialize the hash context */
-	DCRYPTO_SHA256_init(&ctx->hash, 0);
-
-	if (len > HASH_block_size(&ctx->hash)) {
-		HASH_update(&ctx->hash, key, len);
-		memcpy(&ctx->opad[0], HASH_final(&ctx->hash),
-			HASH_size(&ctx->hash));
-	} else {
-		memcpy(&ctx->opad[0], key, len);
-	}
-
-	for (i = 0; i < HASH_block_size(&ctx->hash); ++i)
-		ctx->opad[i] ^= 0x36;
-
-	DCRYPTO_SHA256_init(&ctx->hash, 0);
-	/* hash ipad */
-	HASH_update(&ctx->hash, ctx->opad, HASH_block_size(&ctx->hash));
-
-	for (i = 0; i < HASH_block_size(&ctx->hash); ++i)
-		ctx->opad[i] ^= (0x36 ^ 0x5c);
-}
-
-void DCRYPTO_HMAC_SHA256_init(LITE_HMAC_CTX *ctx, const void *key,
-			unsigned int len)
-{
-	HMAC_init(ctx, key, len);
-}
-
-const uint8_t *DCRYPTO_HMAC_final(LITE_HMAC_CTX *ctx)
-{
-	uint8_t digest[SHA_DIGEST_MAX_BYTES];  /* upto SHA2 */
-
-	memcpy(digest, HASH_final(&ctx->hash),
-		(HASH_size(&ctx->hash) <= sizeof(digest) ?
-			HASH_size(&ctx->hash) : sizeof(digest)));
-	DCRYPTO_SHA256_init(&ctx->hash, 0);
-	HASH_update(&ctx->hash, ctx->opad, HASH_block_size(&ctx->hash));
-	HASH_update(&ctx->hash, digest, HASH_size(&ctx->hash));
-	/* wipe key */
-	always_memset(&ctx->opad[0], 0, HASH_block_size(&ctx->hash));
-	return HASH_final(&ctx->hash);
-}
diff --git a/chip/g/dcrypto/hmac_drbg.c b/chip/g/dcrypto/hmac_drbg.c
deleted file mode 100644
index 0643c9bf84..0000000000
--- a/chip/g/dcrypto/hmac_drbg.c
+++ /dev/null
@@ -1,476 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "console.h"
-#include "cryptoc/util.h"
-#include "dcrypto.h"
-#include "extension.h"
-#include "internal.h"
-#include "trng.h"
-
-/* HMAC_DRBG flow in NIST SP 800-90Ar1, 10.2, RFC 6979
- */
-/* V = HMAC(K, V) */
-static void update_v(const uint32_t *k, uint32_t *v)
-{
-	LITE_HMAC_CTX ctx;
-
-	DCRYPTO_HMAC_SHA256_init(&ctx, k, SHA256_DIGEST_SIZE);
-	HASH_update(&ctx.hash, v, SHA256_DIGEST_SIZE);
-	memcpy(v, DCRYPTO_HMAC_final(&ctx), SHA256_DIGEST_SIZE);
-}
-
-/* K = HMAC(K, V || tag || p0 || p1 || p2) */
-/* V = HMAC(K, V) */
-static void update_kv(uint32_t *k, uint32_t *v, uint8_t tag,
-		      const void *p0, size_t p0_len,
-		      const void *p1, size_t p1_len,
-		      const void *p2, size_t p2_len)
-{
-	LITE_HMAC_CTX ctx;
-
-	DCRYPTO_HMAC_SHA256_init(&ctx, k, SHA256_DIGEST_SIZE);
-	HASH_update(&ctx.hash, v, SHA256_DIGEST_SIZE);
-	HASH_update(&ctx.hash, &tag, 1);
-	HASH_update(&ctx.hash, p0, p0_len);
-	HASH_update(&ctx.hash, p1, p1_len);
-	HASH_update(&ctx.hash, p2, p2_len);
-	memcpy(k, DCRYPTO_HMAC_final(&ctx), SHA256_DIGEST_SIZE);
-
-	update_v(k, v);
-}
-
-static void update(struct drbg_ctx *ctx,
-		   const void *p0, size_t p0_len,
-		   const void *p1, size_t p1_len,
-		   const void *p2, size_t p2_len)
-{
-	/* K = HMAC(K, V || 0x00 || provided_data) */
-	/* V = HMAC(K, V) */
-	update_kv(ctx->k, ctx->v, 0x00,
-		  p0, p0_len, p1, p1_len, p2, p2_len);
-
-	/* If no provided_data, stop. */
-	if (p0_len + p1_len + p2_len == 0)
-		return;
-
-	/* K = HMAC(K, V || 0x01 || provided_data) */
-	/* V = HMAC(K, V) */
-	update_kv(ctx->k, ctx->v,
-		  0x01,
-		  p0, p0_len, p1, p1_len, p2, p2_len);
-}
-
-void hmac_drbg_init(struct drbg_ctx *ctx,
-		    const void *p0, size_t p0_len,
-		    const void *p1, size_t p1_len,
-		    const void *p2, size_t p2_len)
-{
-	/* K = 0x00 0x00 0x00 ... 0x00 */
-	always_memset(ctx->k,  0x00, sizeof(ctx->k));
-	/* V = 0x01 0x01 0x01 ... 0x01 */
-	always_memset(ctx->v,  0x01, sizeof(ctx->v));
-
-	update(ctx, p0, p0_len, p1, p1_len, p2, p2_len);
-
-	ctx->reseed_counter = 1;
-}
-
-void hmac_drbg_init_rfc6979(struct drbg_ctx *ctx, const p256_int *key,
-			    const p256_int *message)
-{
-	hmac_drbg_init(ctx,
-		       key->a, sizeof(key->a),
-		       message->a, sizeof(message->a),
-		       NULL, 0);
-}
-
-void hmac_drbg_init_rand(struct drbg_ctx *ctx, size_t nbits)
-{
-	int i;
-	uint32_t x[(nbits + 31) / 32];
-
-	for (i = 0; i < ARRAY_SIZE(x); ++i)
-		x[i] = rand();
-
-	hmac_drbg_init(ctx, &x, sizeof(x), NULL, 0, NULL, 0);
-}
-
-void hmac_drbg_reseed(struct drbg_ctx *ctx,
-		      const void *p0, size_t p0_len,
-		      const void *p1, size_t p1_len,
-		      const void *p2, size_t p2_len)
-{
-	update(ctx, p0, p0_len, p1, p1_len, p2, p2_len);
-	ctx->reseed_counter = 1;
-}
-
-int hmac_drbg_generate(struct drbg_ctx *ctx,
-		       void *out, size_t out_len,
-		       const void *input, size_t input_len)
-{
-	/* TODO(louiscollard): Assert maximum output length? */
-
-	if (ctx->reseed_counter >= 10000)
-		return 2;
-
-	if (input_len)
-		update(ctx, input, input_len, NULL, 0, NULL, 0);
-
-	while (out_len) {
-		size_t n = out_len > sizeof(ctx->v) ? sizeof(ctx->v) : out_len;
-
-		update_v(ctx->k, ctx->v);
-
-		memcpy(out, ctx->v, n);
-		out += n;
-		out_len -= n;
-	}
-
-	update(ctx, input, input_len, NULL, 0, NULL, 0);
-	ctx->reseed_counter++;
-
-	return 0;
-}
-
-void hmac_drbg_generate_p256(struct drbg_ctx *ctx, p256_int *k_out)
-{
-	hmac_drbg_generate(ctx,
-			   k_out->a, sizeof(k_out->a),
-			   NULL, 0);
-}
-
-void drbg_exit(struct drbg_ctx *ctx)
-{
-	always_memset(ctx->k,  0x00, sizeof(ctx->k));
-	always_memset(ctx->v,  0x00, sizeof(ctx->v));
-}
-
-#ifdef CRYPTO_TEST_SETUP
-
-/*
- * from the RFC 6979 A.2.5 example:
- *
- * curve: NIST P-256
- *
- * q = FFFFFFFF00000000FFFFFFFFFFFFFFFFBCE6FAADA7179E84F3B9CAC2FC632551
- * (qlen = 256 bits)
- *
- * private key:
- * x = C9AFA9D845BA75166B5C215767B1D6934E50C3DB36E89B127B8A622B120F6721
- *
- * public key: U = xG
- * Ux = 60FED4BA255A9D31C961EB74C6356D68C049B8923B61FA6CE669622E60F29FB6
- * Uy = 7903FE1008B8BC99A41AE9E95628BC64F2F1B20C2D7E9F5177A3C294D4462299
- *
- * Signature:
- * With SHA-256, message = "sample":
- * k = A6E3C57DD01ABE90086538398355DD4C3B17AA873382B0F24D6129493D8AAD60
- * r = EFD48B2AACB6A8FD1140DD9CD45E81D69D2C877B56AAF991C34D0EA84EAF3716
- * s = F7CB1C942D657C41D436C7A1B6E29F65F3E900DBB9AFF4064DC4AB2F843ACDA8
- */
-static int cmd_rfc6979(int argc, char **argv)
-{
-	static p256_int h1;
-	static p256_int k;
-	static const char message[] = "sample";
-	static struct drbg_ctx drbg;
-
-	static HASH_CTX ctx;
-	int result;
-	static const uint8_t priv_from_rfc[] = {
-		0xC9, 0xAF, 0xA9, 0xD8, 0x45, 0xBA, 0x75, 0x16,
-		0x6B, 0x5C, 0x21, 0x57, 0x67, 0xB1, 0xD6, 0x93,
-		0x4E, 0x50, 0xC3, 0xDB, 0x36, 0xE8, 0x9B, 0x12,
-		0x7B, 0x8A, 0x62, 0x2B, 0x12, 0x0F, 0x67, 0x21
-	};
-	static const uint8_t k_from_rfc[] = {
-		0xA6, 0xE3, 0xC5, 0x7D, 0xD0, 0x1A, 0xBE, 0x90,
-		0x08, 0x65, 0x38, 0x39, 0x83, 0x55, 0xDD, 0x4C,
-		0x3B, 0x17, 0xAA, 0x87, 0x33, 0x82, 0xB0, 0xF2,
-		0x4D, 0x61, 0x29, 0x49, 0x3D, 0x8A, 0xAD, 0x60
-	};
-	p256_int *x = (p256_int *)priv_from_rfc;
-	p256_int *reference_k = (p256_int *)k_from_rfc;
-
-	/* h1 = H(m) */
-	DCRYPTO_SHA256_init(&ctx, 1);
-	HASH_update(&ctx, message, sizeof(message) - 1);
-	memcpy(&h1, HASH_final(&ctx), SHA256_DIGEST_SIZE);
-
-	hmac_drbg_init_rfc6979(&drbg, x, &h1);
-	do {
-		hmac_drbg_generate_p256(&drbg, &k);
-		ccprintf("K = %ph\n", HEX_BUF(&k, 32));
-	} while (p256_cmp(&SECP256r1_nMin2, &k) < 0);
-	drbg_exit(&drbg);
-	result = p256_cmp(&k, reference_k);
-	ccprintf("K generation: %s\n", result ? "FAIL" : "PASS");
-
-	return result ? EC_ERROR_INVAL : EC_SUCCESS;
-}
-DECLARE_SAFE_CONSOLE_COMMAND(rfc6979, cmd_rfc6979, NULL, NULL);
-
-/*
- * Test vectors from the NIST Cryptographic Algorithm Validation Program.
- *
- * These are the first two examples from the SHA-256, without prediction
- * resistance, and with reseed supported.
- */
-#define HMAC_TEST_COUNT 2
-static int cmd_hmac_drbg(int argc, char **argv)
-{
-	static struct drbg_ctx ctx;
-
-	static const uint8_t init_entropy[HMAC_TEST_COUNT][32] = {
-		{
-			0x06, 0x03, 0x2C, 0xD5, 0xEE, 0xD3, 0x3F, 0x39, 0x26,
-			0x5F, 0x49, 0xEC, 0xB1, 0x42, 0xC5, 0x11, 0xDA, 0x9A,
-			0xFF, 0x2A, 0xF7, 0x12, 0x03, 0xBF, 0xFA, 0xF3, 0x4A,
-			0x9C, 0xA5, 0xBD, 0x9C, 0x0D
-		},
-		{
-			0xAA, 0xDC, 0xF3, 0x37, 0x78, 0x8B, 0xB8, 0xAC, 0x01,
-			0x97, 0x66, 0x40, 0x72, 0x6B, 0xC5, 0x16, 0x35, 0xD4,
-			0x17, 0x77, 0x7F, 0xE6, 0x93, 0x9E, 0xDE, 0xD9, 0xCC,
-			0xC8, 0xA3, 0x78, 0xC7, 0x6A
-		},
-	};
-
-	static const uint8_t init_nonce[HMAC_TEST_COUNT][16] = {
-		{
-			0x0E, 0x66, 0xF7, 0x1E, 0xDC, 0x43, 0xE4, 0x2A, 0x45,
-			0xAD, 0x3C, 0x6F, 0xC6, 0xCD, 0xC4, 0xDF
-		},
-		{
-			0x9C, 0xCC, 0x9D, 0x80, 0xC8, 0x9A, 0xC5, 0x5A, 0x8C,
-			0xFE, 0x0F, 0x99, 0x94, 0x2F, 0x5A, 0x4D
-		},
-	};
-
-	static const uint8_t reseed_entropy[HMAC_TEST_COUNT][32] = {
-		{
-			0x01, 0x92, 0x0A, 0x4E, 0x66, 0x9E, 0xD3, 0xA8, 0x5A,
-			0xE8, 0xA3, 0x3B, 0x35, 0xA7, 0x4A, 0xD7, 0xFB, 0x2A,
-			0x6B, 0xB4, 0xCF, 0x39, 0x5C, 0xE0, 0x03, 0x34, 0xA9,
-			0xC9, 0xA5, 0xA5, 0xD5, 0x52
-		},
-		{
-			0x03, 0xA5, 0x77, 0x92, 0x54, 0x7E, 0x0C, 0x98, 0xEA,
-			0x17, 0x76, 0xE4, 0xBA, 0x80, 0xC0, 0x07, 0x34, 0x62,
-			0x96, 0xA5, 0x6A, 0x27, 0x0A, 0x35, 0xFD, 0x9E, 0xA2,
-			0x84, 0x5C, 0x7E, 0x81, 0xE2
-		}
-	};
-
-	static const uint8_t expected_output[HMAC_TEST_COUNT][128] = {
-		{
-			0x76, 0xFC, 0x79, 0xFE, 0x9B, 0x50, 0xBE, 0xCC, 0xC9,
-			0x91, 0xA1, 0x1B, 0x56, 0x35, 0x78, 0x3A, 0x83, 0x53,
-			0x6A, 0xDD, 0x03, 0xC1, 0x57, 0xFB, 0x30, 0x64, 0x5E,
-			0x61, 0x1C, 0x28, 0x98, 0xBB, 0x2B, 0x1B, 0xC2, 0x15,
-			0x00, 0x02, 0x09, 0x20, 0x8C, 0xD5, 0x06, 0xCB, 0x28,
-			0xDA, 0x2A, 0x51, 0xBD, 0xB0, 0x38, 0x26, 0xAA, 0xF2,
-			0xBD, 0x23, 0x35, 0xD5, 0x76, 0xD5, 0x19, 0x16, 0x08,
-			0x42, 0xE7, 0x15, 0x8A, 0xD0, 0x94, 0x9D, 0x1A, 0x9E,
-			0xC3, 0xE6, 0x6E, 0xA1, 0xB1, 0xA0, 0x64, 0xB0, 0x05,
-			0xDE, 0x91, 0x4E, 0xAC, 0x2E, 0x9D, 0x4F, 0x2D, 0x72,
-			0xA8, 0x61, 0x6A, 0x80, 0x22, 0x54, 0x22, 0x91, 0x82,
-			0x50, 0xFF, 0x66, 0xA4, 0x1B, 0xD2, 0xF8, 0x64, 0xA6,
-			0xA3, 0x8C, 0xC5, 0xB6, 0x49, 0x9D, 0xC4, 0x3F, 0x7F,
-			0x2B, 0xD0, 0x9E, 0x1E, 0x0F, 0x8F, 0x58, 0x85, 0x93,
-			0x51, 0x24
-		},
-		{
-			0x17, 0xD0, 0x9F, 0x40, 0xA4, 0x37, 0x71, 0xF4, 0xA2,
-			0xF0, 0xDB, 0x32, 0x7D, 0xF6, 0x37, 0xDE, 0xA9, 0x72,
-			0xBF, 0xFF, 0x30, 0xC9, 0x8E, 0xBC, 0x88, 0x42, 0xDC,
-			0x7A, 0x9E, 0x3D, 0x68, 0x1C, 0x61, 0x90, 0x2F, 0x71,
-			0xBF, 0xFA, 0xF5, 0x09, 0x36, 0x07, 0xFB, 0xFB, 0xA9,
-			0x67, 0x4A, 0x70, 0xD0, 0x48, 0xE5, 0x62, 0xEE, 0x88,
-			0xF0, 0x27, 0xF6, 0x30, 0xA7, 0x85, 0x22, 0xEC, 0x6F,
-			0x70, 0x6B, 0xB4, 0x4A, 0xE1, 0x30, 0xE0, 0x5C, 0x8D,
-			0x7E, 0xAC, 0x66, 0x8B, 0xF6, 0x98, 0x0D, 0x99, 0xB4,
-			0xC0, 0x24, 0x29, 0x46, 0x45, 0x23, 0x99, 0xCB, 0x03,
-			0x2C, 0xC6, 0xF9, 0xFD, 0x96, 0x28, 0x47, 0x09, 0xBD,
-			0x2F, 0xA5, 0x65, 0xB9, 0xEB, 0x9F, 0x20, 0x04, 0xBE,
-			0x6C, 0x9E, 0xA9, 0xFF, 0x91, 0x28, 0xC3, 0xF9, 0x3B,
-			0x60, 0xDC, 0x30, 0xC5, 0xFC, 0x85, 0x87, 0xA1, 0x0D,
-			0xE6, 0x8C
-		}
-	};
-
-	static uint8_t output[128];
-
-	int i, cmp_result;
-
-	for (i = 0; i < HMAC_TEST_COUNT; i++) {
-		hmac_drbg_init(&ctx,
-			       init_entropy[i], sizeof(init_entropy[i]),
-			       init_nonce[i], sizeof(init_nonce[i]),
-			       NULL, 0);
-
-		hmac_drbg_reseed(&ctx,
-				 reseed_entropy[i], sizeof(reseed_entropy[i]),
-				 NULL, 0,
-				 NULL, 0);
-
-		hmac_drbg_generate(&ctx,
-				   output, sizeof(output),
-				   NULL, 0);
-
-		hmac_drbg_generate(&ctx,
-				   output, sizeof(output),
-				   NULL, 0);
-
-		cmp_result = memcmp(output, expected_output[i], sizeof(output));
-		ccprintf("HMAC DRBG generate test %d, %s\n",
-			 i, cmp_result ? "failed" : "passed");
-	}
-
-	return 0;
-}
-DECLARE_SAFE_CONSOLE_COMMAND(hmac_drbg, cmd_hmac_drbg, NULL, NULL);
-
-/*
- * Sanity check to exercise random initialization.
- */
-static int cmd_hmac_drbg_rand(int argc, char **argv)
-{
-	static struct drbg_ctx ctx;
-	static uint8_t output[128];
-
-	int i;
-
-	hmac_drbg_init_rand(&ctx, 256);
-
-	hmac_drbg_generate(&ctx, output, sizeof(output), NULL, 0);
-
-	ccprintf("Randomly initialized HMAC DRBG, 1024 bit output: ");
-
-	for (i = 0; i < sizeof(output); i++)
-		ccprintf("%x", output[i]);
-	ccprintf("\n");
-
-	return 0;
-}
-DECLARE_SAFE_CONSOLE_COMMAND(hmac_drbg_rand, cmd_hmac_drbg_rand, NULL, NULL);
-
-enum drbg_command {
-	DRBG_INIT = 0,
-	DRBG_RESEED = 1,
-	DRBG_GENERATE = 2
-};
-
-/*
- * DRBG_TEST command structure:
- *
- * field       |    size  |              note
- * ==========================================================================
- * mode        |    1     | 0 - DRBG_INIT, 1 - DRBG_RESEED, 2 - DRBG_GENERATE
- * p0_len      |    2     | size of first input in bytes
- * p0          |  p0_len  | entropy for INIT & SEED, input for GENERATE
- * p1_len      |    2     | size of second input in bytes (for INIT & RESEED)
- *             |          | or size of expected output for GENERATE
- * p1          |  p1_len  | nonce for INIT & SEED
- * p2_len      |    2     | size of third input in bytes for DRBG_INIT
- * p2          |  p2_len  | personalization for INIT & SEED
- *
- * DRBG_INIT (entropy, nonce, perso)
- * DRBG_RESEED (entropy, additional input 1, additional input 2)
- * DRBG_INIT and DRBG_RESEED returns empty response
- * DRBG_GENERATE (p0_len, p0 - additional input 1, p1_len - size of output)
- * DRBG_GENERATE returns p1_len bytes of generated data
- * (up to a maximum of 128 bytes)
- */
-static enum vendor_cmd_rc drbg_test(enum vendor_cmd_cc code, void *buf,
-				    size_t input_size, size_t *response_size)
-{
-	static struct drbg_ctx drbg_ctx;
-	static uint8_t output[128];
-	uint8_t *p0 = NULL, *p1 = NULL, *p2 = NULL;
-	uint16_t p0_len = 0, p1_len = 0, p2_len = 0;
-	uint8_t *cmd = (uint8_t *)buf;
-	size_t max_out_len = *response_size;
-	enum drbg_command drbg_op;
-
-	*response_size = 0;
-	/* there is always op + first parameter, even if zero length */
-	if (input_size < sizeof(p0_len) + 1)
-		return VENDOR_RC_BOGUS_ARGS;
-	drbg_op = *cmd++;
-	p0_len = *cmd++;
-	p0_len = p0_len * 256 + *cmd++;
-	input_size -= 3;
-	if (p0_len > input_size)
-		return VENDOR_RC_BOGUS_ARGS;
-	input_size -= p0_len;
-	if (p0_len)
-		p0 = cmd;
-	cmd += p0_len;
-
-	/* there should be enough space for p1_len */
-	if (input_size && input_size < sizeof(p1_len))
-		return VENDOR_RC_BOGUS_ARGS;
-
-	/* DRBG_GENERATE should just have p1_len defined */
-	if (drbg_op == DRBG_GENERATE && input_size != sizeof(p1_len))
-		return VENDOR_RC_BOGUS_ARGS;
-
-	if (input_size) {
-		p1_len = *cmd++;
-		p1_len = p1_len * 256 + *cmd++;
-		input_size -= 2;
-
-		if (drbg_op != DRBG_GENERATE) {
-			if (p1_len > input_size)
-				return VENDOR_RC_BOGUS_ARGS;
-			input_size -= p1_len;
-			if (p1_len)
-				p1 = cmd;
-			cmd += p1_len;
-		}
-	}
-
-	if (input_size) {
-		if (drbg_op == DRBG_GENERATE)
-			return VENDOR_RC_BOGUS_ARGS;
-		p2_len = *cmd++;
-		p2_len = p2_len * 256 + *cmd++;
-		input_size -= 2;
-		if (p2_len > input_size)
-			return VENDOR_RC_BOGUS_ARGS;
-		if (p2_len)
-			p2 = cmd;
-	}
-
-	switch (drbg_op) {
-	case DRBG_INIT: {
-		hmac_drbg_init(&drbg_ctx, p0, p0_len, p1, p1_len, p2, p2_len);
-		break;
-	}
-	case DRBG_RESEED: {
-		hmac_drbg_reseed(&drbg_ctx, p0, p0_len, p1, p1_len, p2, p2_len);
-		break;
-	}
-	case DRBG_GENERATE: {
-		if (p1_len > sizeof(output) || max_out_len < p1_len)
-			return VENDOR_RC_BOGUS_ARGS;
-
-		hmac_drbg_generate(&drbg_ctx, output, p1_len, p0, p0_len);
-
-		memcpy(buf, output, p1_len);
-		*response_size = p1_len;
-		break;
-	}
-	default:
-		return VENDOR_RC_BOGUS_ARGS;
-	}
-
-	return VENDOR_RC_SUCCESS;
-}
-DECLARE_VENDOR_COMMAND(VENDOR_CC_DRBG_TEST, drbg_test);
-
-#endif /* CRYPTO_TEST_SETUP */
diff --git a/chip/g/dcrypto/internal.h b/chip/g/dcrypto/internal.h
deleted file mode 100644
index 69c54da4d4..0000000000
--- a/chip/g/dcrypto/internal.h
+++ /dev/null
@@ -1,208 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __EC_CHIP_G_DCRYPTO_INTERNAL_H
-#define __EC_CHIP_G_DCRYPTO_INTERNAL_H
-
-#include <stddef.h>
-#include <string.h>
-
-#include "common.h"
-#include "util.h"
-
-#include "cryptoc/p256.h"
-#include "cryptoc/sha.h"
-#include "cryptoc/sha256.h"
-#include "cryptoc/sha384.h"
-#include "cryptoc/sha512.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- * SHA.
- */
-#define CTRL_CTR_BIG_ENDIAN (__BYTE_ORDER__  == __ORDER_BIG_ENDIAN__)
-#define CTRL_ENABLE         1
-#define CTRL_ENCRYPT        1
-#define CTRL_NO_SOFT_RESET  0
-
-#define SHA_DIGEST_WORDS   (SHA_DIGEST_SIZE / sizeof(uint32_t))
-#define SHA256_DIGEST_WORDS (SHA256_DIGEST_SIZE / sizeof(uint32_t))
-
-#ifdef SHA512_SUPPORT
-#define SHA_DIGEST_MAX_BYTES SHA512_DIGEST_SIZE
-#else
-#define SHA_DIGEST_MAX_BYTES SHA256_DIGEST_SIZE
-#endif
-
-enum sha_mode {
-	SHA1_MODE = 0,
-	SHA256_MODE = 1
-};
-
-/*
- * Use this structure to avoid alignment problems with input and output
- * pointers.
- */
-struct access_helper {
-	uint32_t udata;
-} __packed;
-
-#ifndef SECTION_IS_RO
-int dcrypto_grab_sha_hw(void);
-void dcrypto_release_sha_hw(void);
-#endif
-void dcrypto_sha_hash(enum sha_mode mode, const uint8_t *data,
-		uint32_t n, uint8_t *digest);
-void dcrypto_sha_init(enum sha_mode mode);
-void dcrypto_sha_update(struct HASH_CTX *unused,
-			const void *data, uint32_t n);
-void dcrypto_sha_wait(enum sha_mode mode, uint32_t *digest);
-
-/*
- * BIGNUM.
- */
-#define LITE_BN_BITS2        32
-#define LITE_BN_BYTES        4
-
-struct LITE_BIGNUM {
-	uint32_t dmax;              /* Size of d, in 32-bit words. */
-	struct access_helper *d;  /* Word array, little endian format ... */
-};
-
-#define BN_DIGIT(b, i) ((b)->d[(i)].udata)
-
-void bn_init(struct LITE_BIGNUM *bn, void *buf, size_t len);
-#define bn_size(b) ((b)->dmax * LITE_BN_BYTES)
-#define bn_words(b) ((b)->dmax)
-#define bn_bits(b) ((b)->dmax * LITE_BN_BITS2)
-int bn_eq(const struct LITE_BIGNUM *a, const struct LITE_BIGNUM *b);
-int bn_check_topbit(const struct LITE_BIGNUM *N);
-int bn_modexp(struct LITE_BIGNUM *output,
-			const struct LITE_BIGNUM *input,
-			const struct LITE_BIGNUM *exp,
-			const struct LITE_BIGNUM *N);
-int bn_modexp_word(struct LITE_BIGNUM *output,
-			const struct LITE_BIGNUM *input,
-			uint32_t pubexp,
-			const struct LITE_BIGNUM *N);
-int bn_modexp_blinded(struct LITE_BIGNUM *output,
-			const struct LITE_BIGNUM *input,
-			const struct LITE_BIGNUM *exp,
-			const struct LITE_BIGNUM *N,
-			uint32_t pubexp);
-uint32_t bn_add(struct LITE_BIGNUM *c,
-		const struct LITE_BIGNUM *a);
-uint32_t bn_sub(struct LITE_BIGNUM *c,
-		const struct LITE_BIGNUM *a);
-int bn_modinv_vartime(struct LITE_BIGNUM *r,
-			const struct LITE_BIGNUM *e,
-			const struct LITE_BIGNUM *MOD);
-int bn_is_bit_set(const struct LITE_BIGNUM *a, int n);
-
-/*
- * Accelerated bn.
- */
-int dcrypto_modexp(struct LITE_BIGNUM *output,
-			const struct LITE_BIGNUM *input,
-			const struct LITE_BIGNUM *exp,
-			const struct LITE_BIGNUM *N);
-int dcrypto_modexp_word(struct LITE_BIGNUM *output,
-			const struct LITE_BIGNUM *input,
-			uint32_t pubexp,
-			const struct LITE_BIGNUM *N);
-int dcrypto_modexp_blinded(struct LITE_BIGNUM *output,
-			const struct LITE_BIGNUM *input,
-			const struct LITE_BIGNUM *exp,
-			const struct LITE_BIGNUM *N,
-			uint32_t pubexp);
-
-struct drbg_ctx {
-	uint32_t k[SHA256_DIGEST_WORDS];
-	uint32_t v[SHA256_DIGEST_WORDS];
-	uint32_t reseed_counter;
-};
-
-/*
- * NIST SP 800-90A HMAC DRBG.
- */
-
-/* Standard initialization. */
-void hmac_drbg_init(struct drbg_ctx *ctx,
-		    const void *p0, size_t p0_len,
-		    const void *p1, size_t p1_len,
-		    const void *p2, size_t p2_len);
-/* Initialize for use as RFC6979 DRBG. */
-void hmac_drbg_init_rfc6979(struct drbg_ctx *ctx,
-			    const p256_int *key,
-			    const p256_int *message);
-/* Initialize with at least nbits of random entropy. */
-void hmac_drbg_init_rand(struct drbg_ctx *ctx, size_t nbits);
-void hmac_drbg_reseed(struct drbg_ctx *ctx,
-		      const void *p0, size_t p0_len,
-		      const void *p1, size_t p1_len,
-		      const void *p2, size_t p2_len);
-int hmac_drbg_generate(struct drbg_ctx *ctx,
-		       void *out, size_t out_len,
-		       const void *input, size_t input_len);
-/* Generate p256, with no additional input. */
-void hmac_drbg_generate_p256(struct drbg_ctx *ctx, p256_int *k_out);
-void drbg_exit(struct drbg_ctx *ctx);
-
-/*
- * Accelerated p256. FIPS PUB 186-4
- */
-int dcrypto_p256_ecdsa_sign(struct drbg_ctx *drbg, const p256_int *key,
-			    const p256_int *message, p256_int *r, p256_int *s)
-	__attribute__((warn_unused_result));
-int dcrypto_p256_base_point_mul(const p256_int *k, p256_int *x, p256_int *y)
-	 __attribute__((warn_unused_result));
-int dcrypto_p256_point_mul(const p256_int *k,
-		const p256_int *in_x, const p256_int *in_y,
-		p256_int *x, p256_int *y)
-	__attribute__((warn_unused_result));
-int dcrypto_p256_ecdsa_verify(const p256_int *key_x, const p256_int *key_y,
-		const p256_int *message, const p256_int *r,
-		const p256_int *s)
-	__attribute__((warn_unused_result));
-int dcrypto_p256_is_valid_point(const p256_int *x, const p256_int *y)
-	__attribute__((warn_unused_result));
-
-/*
- * Accelerator runtime.
- *
- * Note dcrypto_init_and_lock grabs a mutex and dcrypto_unlock releases it.
- * Do not use dcrypto_call, dcrypto_imem_load or dcrypto_dmem_load w/o holding
- * the mutex.
- */
-void dcrypto_init_and_lock(void);
-void dcrypto_unlock(void);
-uint32_t dcrypto_call(uint32_t adr) __attribute__((warn_unused_result));
-void dcrypto_imem_load(size_t offset, const uint32_t *opcodes,
-		       size_t n_opcodes);
-/*
- * Returns 0 iff no difference was observed between existing and new content.
- */
-uint32_t dcrypto_dmem_load(size_t offset, const void *words, size_t n_words);
-
-/*
- * Key ladder.
- */
-#ifndef __cplusplus
-enum dcrypto_appid;      /* Forward declaration. */
-
-int dcrypto_ladder_compute_usr(enum dcrypto_appid id,
-			const uint32_t usr_salt[8]);
-int dcrypto_ladder_derive(enum dcrypto_appid appid, const uint32_t salt[8],
-			  const uint32_t input[8], uint32_t output[8]);
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif  /* ! __EC_CHIP_G_DCRYPTO_INTERNAL_H */
diff --git a/chip/g/dcrypto/key_ladder.c b/chip/g/dcrypto/key_ladder.c
deleted file mode 100644
index 77055e4159..0000000000
--- a/chip/g/dcrypto/key_ladder.c
+++ /dev/null
@@ -1,300 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#include "dcrypto.h"
-#include "internal.h"
-#include "endian.h"
-#include "registers.h"
-#include "trng.h"
-
-static void ladder_init(void)
-{
-	/* Do not reset keyladder engine here, as before.
-	 *
-	 * Should not be needed and if it is, it is indicative
-	 * of sync error between this and sha engine usage.
-	 * Reset will make this flow work, but will have broken
-	 * the other pending sha flow.
-	 * Hence leave as is and observe the error.
-	 */
-
-	/* Enable random stalls for key-ladder usage.  Note that
-	 * the stall rate used for key-ladder operations is
-	 * 25% (vs. 12% for generic SHA operations).  This distinction
-	 * is made so as to increase the difficulty in characterizng
-	 * the key-ladder engine via random inputs provided over the
-	 * generic SHA interface.
-	 */
-	/* Turn off random nops (which are enabled by default). */
-	GWRITE_FIELD(KEYMGR, SHA_RAND_STALL_CTL, STALL_EN, 0);
-	/* Configure random nop percentage at 25%. */
-	GWRITE_FIELD(KEYMGR, SHA_RAND_STALL_CTL, FREQ, 1);
-	/* Now turn on random nops. */
-	GWRITE_FIELD(KEYMGR, SHA_RAND_STALL_CTL, STALL_EN, 1);
-}
-
-static int ladder_step(uint32_t cert, const uint32_t input[8])
-{
-	GREG32(KEYMGR, SHA_ITOP) = 0;  /* clear status */
-
-	GREG32(KEYMGR, SHA_USE_CERT_INDEX) =
-		(cert << GC_KEYMGR_SHA_USE_CERT_INDEX_LSB) |
-		GC_KEYMGR_SHA_USE_CERT_ENABLE_MASK;
-
-	GREG32(KEYMGR, SHA_CFG_EN) =
-		GC_KEYMGR_SHA_CFG_EN_INT_EN_DONE_MASK;
-	GREG32(KEYMGR, SHA_TRIG) =
-		GC_KEYMGR_SHA_TRIG_TRIG_GO_MASK;
-
-	if (input) {
-		GREG32(KEYMGR, SHA_INPUT_FIFO) = input[0];
-		GREG32(KEYMGR, SHA_INPUT_FIFO) = input[1];
-		GREG32(KEYMGR, SHA_INPUT_FIFO) = input[2];
-		GREG32(KEYMGR, SHA_INPUT_FIFO) = input[3];
-		GREG32(KEYMGR, SHA_INPUT_FIFO) = input[4];
-		GREG32(KEYMGR, SHA_INPUT_FIFO) = input[5];
-		GREG32(KEYMGR, SHA_INPUT_FIFO) = input[6];
-		GREG32(KEYMGR, SHA_INPUT_FIFO) = input[7];
-
-		GREG32(KEYMGR, SHA_TRIG) = GC_KEYMGR_SHA_TRIG_TRIG_STOP_MASK;
-	}
-
-	while (!GREG32(KEYMGR, SHA_ITOP))
-		;
-
-	GREG32(KEYMGR, SHA_ITOP) = 0;  /* clear status */
-
-	return !!GREG32(KEYMGR, HKEY_ERR_FLAGS);
-}
-
-static int compute_certs(const uint32_t *certs, size_t num_certs)
-{
-	int i;
-
-	for (i = 0; i < num_certs; i++) {
-		if (ladder_step(certs[i], NULL))
-			return 0;
-	}
-
-	return 1;
-}
-
-#define KEYMGR_CERT_0 0
-#define KEYMGR_CERT_3 3
-#define KEYMGR_CERT_4 4
-#define KEYMGR_CERT_5 5
-#define KEYMGR_CERT_7 7
-#define KEYMGR_CERT_15 15
-#define KEYMGR_CERT_20 20
-#define KEYMGR_CERT_25 25
-#define KEYMGR_CERT_26 26
-#define KEYMGR_CERT_27 27
-#define KEYMGR_CERT_28 28
-#define KEYMGR_CERT_34 34
-#define KEYMGR_CERT_35 35
-#define KEYMGR_CERT_38 38
-
-static const uint32_t FRK2_CERTS_PREFIX[] = {
-	KEYMGR_CERT_0,
-	KEYMGR_CERT_3,
-	KEYMGR_CERT_4,
-	KEYMGR_CERT_5,
-	KEYMGR_CERT_7,
-	KEYMGR_CERT_15,
-	KEYMGR_CERT_20,
-};
-
-static const uint32_t FRK2_CERTS_POSTFIX[] = {
-	KEYMGR_CERT_26,
-};
-
-#define MAX_MAJOR_FW_VERSION 254
-
-int DCRYPTO_ladder_compute_frk2(size_t fw_version, uint8_t *frk2)
-{
-	int result = 0;
-
-	if (fw_version > MAX_MAJOR_FW_VERSION)
-		return 0;
-
-	if (!dcrypto_grab_sha_hw())
-		return 0;
-
-	do {
-		int i;
-
-		ladder_init();
-
-		if (!compute_certs(FRK2_CERTS_PREFIX,
-					ARRAY_SIZE(FRK2_CERTS_PREFIX)))
-			break;
-
-		for (i = 0; i < MAX_MAJOR_FW_VERSION - fw_version; i++) {
-			if (ladder_step(KEYMGR_CERT_25, NULL))
-				break;
-		}
-
-		if (!compute_certs(FRK2_CERTS_POSTFIX,
-					ARRAY_SIZE(FRK2_CERTS_POSTFIX)))
-			break;
-
-		memcpy(frk2, (void *) GREG32_ADDR(KEYMGR, HKEY_FRR0),
-			AES256_BLOCK_CIPHER_KEY_SIZE);
-
-		result = 1;
-	} while (0);
-
-	dcrypto_release_sha_hw();
-	return result;
-}
-
-/* ISR salt (SHA256("ISR_SALT")) to use for USR generation. */
-static const uint32_t ISR_SALT[8] = {
-	0x6ba1b495, 0x4b7ca214, 0xfe07e922, 0x09735185,
-	0xfcca43ca, 0xc6d4dfd9, 0x5fc2fcca, 0xaa45400b
-};
-
-/* Map of populated USR registers. */
-static int usr_ready[8]  = {};
-
-int dcrypto_ladder_compute_usr(enum dcrypto_appid id,
-			       const uint32_t usr_salt[8])
-{
-	int result = 0;
-
-	/* Check for USR readiness. */
-	if (usr_ready[id])
-		return 1;
-
-	if (!dcrypto_grab_sha_hw())
-		return 0;
-
-	do {
-		int i;
-
-		/* The previous check performed without lock acquisition. */
-		if (usr_ready[id]) {
-			result = 1;
-			break;
-		}
-
-		ladder_init();
-
-		if (!compute_certs(FRK2_CERTS_PREFIX,
-					ARRAY_SIZE(FRK2_CERTS_PREFIX)))
-			break;
-
-		/* USR generation requires running the key-ladder till
-		 * the end (version 0), plus one additional iteration.
-		 */
-		for (i = 0; i < MAX_MAJOR_FW_VERSION - 0 + 1; i++) {
-			if (ladder_step(KEYMGR_CERT_25, NULL))
-				break;
-		}
-		if (i != MAX_MAJOR_FW_VERSION - 0 + 1)
-			break;
-
-		if (ladder_step(KEYMGR_CERT_34, ISR_SALT))
-			break;
-
-		/* Output goes to USR[appid] (the multiply by 2 is an
-		 * artifact of slot addressing).
-		 */
-		GWRITE_FIELD(KEYMGR, SHA_CERT_OVERRIDE, DIGEST_PTR, 2 * id);
-		if (ladder_step(KEYMGR_CERT_35, usr_salt))
-			break;
-
-		/* Check for key-ladder errors. */
-		if (GREG32(KEYMGR, HKEY_ERR_FLAGS))
-			break;
-
-		/* Key deposited in USR[id], and ready to use. */
-		usr_ready[id] = 1;
-
-		result = 1;
-	} while (0);
-
-	dcrypto_release_sha_hw();
-	return result;
-}
-
-static void ladder_out(uint32_t output[8])
-{
-	output[0] = GREG32(KEYMGR, SHA_STS_H0);
-	output[1] = GREG32(KEYMGR, SHA_STS_H1);
-	output[2] = GREG32(KEYMGR, SHA_STS_H2);
-	output[3] = GREG32(KEYMGR, SHA_STS_H3);
-	output[4] = GREG32(KEYMGR, SHA_STS_H4);
-	output[5] = GREG32(KEYMGR, SHA_STS_H5);
-	output[6] = GREG32(KEYMGR, SHA_STS_H6);
-	output[7] = GREG32(KEYMGR, SHA_STS_H7);
-}
-
-/*
- * Stir TRNG entropy into RSR and pull some out.
- */
-int DCRYPTO_ladder_random(void *output)
-{
-	int error = 1;
-	uint32_t tmp[8];
-
-	if (!dcrypto_grab_sha_hw())
-		goto fail;
-
-	rand_bytes(tmp, sizeof(tmp));
-	/* Mix TRNG bytes with RSR entropy */
-	error = ladder_step(KEYMGR_CERT_27, tmp);
-	if (!error)
-		ladder_out(output);
-
-fail:
-	dcrypto_release_sha_hw();
-	return !error;
-}
-
-int dcrypto_ladder_derive(enum dcrypto_appid appid, const uint32_t salt[8],
-			  const uint32_t input[8], uint32_t output[8])
-{
-	int error;
-
-	if (!dcrypto_grab_sha_hw())
-		return 0;
-
-	GWRITE_FIELD(KEYMGR, SHA_CERT_OVERRIDE, KEY_PTR, 2 * appid);
-	error = ladder_step(KEYMGR_CERT_38, input); /* HMAC */
-	if (!error)
-		ladder_out(output);
-
-	dcrypto_release_sha_hw();
-	return !error;
-}
-
-void DCRYPTO_ladder_revoke(void)
-{
-	/* Revoke certificates */
-	GWRITE(KEYMGR, CERT_REVOKE_CTRL0, 0xffffffff);
-	GWRITE(KEYMGR, CERT_REVOKE_CTRL1, 0xffffffff);
-
-	/* Wipe out the hidden keys cached in AES and SHA engines. */
-	GWRITE_FIELD(KEYMGR, AES_USE_HIDDEN_KEY, ENABLE, 0);
-	GWRITE_FIELD(KEYMGR, SHA_USE_HIDDEN_KEY, ENABLE, 0);
-
-	/* Clear usr_ready[] */
-	memset(usr_ready, 0, sizeof(usr_ready));
-}
-
-#define KEYMGR_CERT_REVOKE_CTRL0_DEFAULT_VAL	0xa8028a82
-#define KEYMGR_CERT_REVOKE_CTRL1_DEFAULT_VAL	0xaaaaaaaa
-
-int DCRYPTO_ladder_is_enabled(void)
-{
-	uint32_t ctrl0;
-	uint32_t ctrl1;
-
-	ctrl0 = GREAD(KEYMGR, CERT_REVOKE_CTRL0);
-	ctrl1 = GREAD(KEYMGR, CERT_REVOKE_CTRL1);
-
-	return  ctrl0 == KEYMGR_CERT_REVOKE_CTRL0_DEFAULT_VAL &&
-		ctrl1 == KEYMGR_CERT_REVOKE_CTRL1_DEFAULT_VAL;
-}
diff --git a/chip/g/dcrypto/p256.c b/chip/g/dcrypto/p256.c
deleted file mode 100644
index 665144e31b..0000000000
--- a/chip/g/dcrypto/p256.c
+++ /dev/null
@@ -1,30 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "dcrypto.h"
-
-#include "cryptoc/p256.h"
-#include "cryptoc/util.h"
-
-static const p256_int p256_one = P256_ONE;
-
-/*
- * Key selection based on FIPS-186-4, section B.4.2 (Key Pair
- * Generation by Testing Candidates).
- */
-int DCRYPTO_p256_key_from_bytes(p256_int *x, p256_int *y, p256_int *d,
-				const uint8_t key_bytes[P256_NBYTES])
-{
-	p256_int key;
-
-	p256_from_bin(key_bytes, &key);
-	if (p256_cmp(&SECP256r1_nMin2, &key) < 0)
-		return 0;
-	p256_add(&key, &p256_one, d);
-	always_memset(&key, 0, sizeof(key));
-	if (x == NULL || y == NULL)
-		return 1;
-	return dcrypto_p256_base_point_mul(d, x, y);
-}
diff --git a/chip/g/dcrypto/p256_ec.c b/chip/g/dcrypto/p256_ec.c
deleted file mode 100644
index cb33a15774..0000000000
--- a/chip/g/dcrypto/p256_ec.c
+++ /dev/null
@@ -1,39 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "dcrypto.h"
-
-#include <stdint.h>
-
-#include "cryptoc/p256.h"
-
-/* p256_base_point_mul sets {out_x,out_y} = nG, where n is < the
- * order of the group. */
-int DCRYPTO_p256_base_point_mul(p256_int *out_x, p256_int *out_y,
-				const p256_int *n)
-{
-	if (p256_is_zero(n) != 0) {
-		p256_clear(out_x);
-		p256_clear(out_y);
-		return 0;
-	}
-
-	return dcrypto_p256_base_point_mul(n, out_x, out_y);
-}
-
-/* DCRYPTO_p256_point_mul sets {out_x,out_y} = n*{in_x,in_y}, where n is <
- * the order of the group. */
-int DCRYPTO_p256_point_mul(p256_int *out_x, p256_int *out_y,
-			const p256_int *n, const p256_int *in_x,
-			const p256_int *in_y)
-{
-	if (p256_is_zero(n) != 0) {
-		p256_clear(out_x);
-		p256_clear(out_y);
-		return 0;
-	}
-
-	return dcrypto_p256_point_mul(n, in_x, in_y, out_x, out_y);
-}
diff --git a/chip/g/dcrypto/p256_ecies.c b/chip/g/dcrypto/p256_ecies.c
deleted file mode 100644
index 30a410d828..0000000000
--- a/chip/g/dcrypto/p256_ecies.c
+++ /dev/null
@@ -1,175 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "internal.h"
-#include "dcrypto.h"
-
-#include "trng.h"
-#include "util.h"
-
-#include "cryptoc/p256.h"
-#include "cryptoc/sha256.h"
-
-#define AES_KEY_BYTES  16
-#define HMAC_KEY_BYTES 32
-
-#define AES_BLOCK_BYTES 16
-
-/* P256 based hybrid encryption.  The output format is:
- *
- *   0x04 || PUBKEY || AUTH_DATA || AES128_CTR(PLAINTEXT) ||
- *      HMAC_SHA256(AUTH_DATA || CIPHERTEXT)
- */
-size_t DCRYPTO_ecies_encrypt(
-	void *out, size_t out_len, const void *in, size_t in_len,
-	size_t auth_data_len, const uint8_t *iv,
-	const p256_int *pub_x, const p256_int *pub_y,
-	const uint8_t *salt, size_t salt_len,
-	const uint8_t *info, size_t info_len)
-{
-	p256_int eph_d;
-	p256_int eph_x;
-	p256_int eph_y;
-	uint8_t seed[P256_NBYTES];
-	p256_int secret_x;
-	p256_int secret_y;
-	/* Key bytes to be extracted from HKDF. */
-	uint8_t key[AES_KEY_BYTES + HMAC_KEY_BYTES];
-	const uint8_t *aes_key;
-	const uint8_t *hmac_key;
-	LITE_HMAC_CTX ctx;
-	uint8_t *outp = out;
-	uint8_t *ciphertext;
-
-	if (auth_data_len > in_len)
-		return 0;
-	if (out_len < 1 + P256_NBYTES + P256_NBYTES +
-		in_len + SHA256_DIGEST_SIZE)
-		return 0;
-
-	/* Generate emphemeral EC key. */
-	rand_bytes(seed, sizeof(seed));
-	if (!DCRYPTO_p256_key_from_bytes(&eph_x, &eph_y, &eph_d, seed))
-		return 0;
-	/* Compute DH point. */
-	if (!DCRYPTO_p256_point_mul(&secret_x, &secret_y,
-					&eph_d, pub_x, pub_y))
-		return 0;
-	/* Check for computational errors. */
-	if (!dcrypto_p256_is_valid_point(&secret_x, &secret_y))
-		return 0;
-	/* Convert secret to big-endian. */
-	reverse(&secret_x, sizeof(secret_x));
-	/* Derive shared secret. */
-	if (!DCRYPTO_hkdf(key, sizeof(key), salt, salt_len,
-				(uint8_t *) &secret_x, sizeof(secret_x),
-				info, info_len))
-		return 0;
-
-	aes_key = &key[0];
-	hmac_key = &key[AES_KEY_BYTES];
-
-	if (out == in)
-		ciphertext = out + auth_data_len;    /* In place encrypt. */
-	else
-		ciphertext = out + 1 + P256_NBYTES + P256_NBYTES +
-			auth_data_len;
-
-	/* Compute ciphertext. */
-	if (!DCRYPTO_aes_ctr(ciphertext, aes_key, AES_KEY_BYTES * 8, iv,
-				in + auth_data_len, in_len - auth_data_len))
-		return 0;
-
-	/* Write out auth_data / ciphertext. */
-	outp = out + 1 + P256_NBYTES + P256_NBYTES;
-	if (out == in)
-		memmove(outp, in, in_len);
-	else
-		memcpy(outp, in, auth_data_len);
-
-	/* Write out ephemeral pub key. */
-	outp = out;
-	*outp++ = 0x04;  /* uncompressed EC public key. */
-	p256_to_bin(&eph_x, outp);
-	outp += P256_NBYTES;
-	p256_to_bin(&eph_y, outp);
-	outp += P256_NBYTES;
-
-	/* Calculate HMAC(auth_data || ciphertext). */
-	DCRYPTO_HMAC_SHA256_init(&ctx, hmac_key, HMAC_KEY_BYTES);
-	HASH_update(&ctx.hash, outp, in_len);
-	outp += in_len;
-	memcpy(outp, DCRYPTO_HMAC_final(&ctx), SHA256_DIGEST_SIZE);
-	outp += SHA256_DIGEST_SIZE;
-
-	return outp - (uint8_t *) out;
-}
-
-size_t DCRYPTO_ecies_decrypt(
-	void *out, size_t out_len, const void *in, size_t in_len,
-	size_t auth_data_len, const uint8_t *iv,
-	const p256_int *d,
-	const uint8_t *salt, size_t salt_len,
-	const uint8_t *info, size_t info_len)
-{
-	p256_int eph_x;
-	p256_int eph_y;
-	p256_int secret_x;
-	p256_int secret_y;
-	uint8_t key[AES_KEY_BYTES + HMAC_KEY_BYTES];
-	const uint8_t *aes_key;
-	const uint8_t *hmac_key;
-	LITE_HMAC_CTX ctx;
-	const uint8_t *inp = in;
-	uint8_t *outp = out;
-
-	if (in_len < 1 + P256_NBYTES + P256_NBYTES + auth_data_len +
-		SHA256_DIGEST_SIZE)
-		return 0;
-	if (inp[0] != 0x04)
-		return 0;
-
-	in_len -= 1 + P256_NBYTES + P256_NBYTES + SHA256_DIGEST_SIZE;
-
-	inp++;
-	p256_from_bin(inp, &eph_x);
-	inp += P256_NBYTES;
-	p256_from_bin(inp, &eph_y);
-	inp += P256_NBYTES;
-
-	/* Verify that the public point is on the curve. */
-	if (!dcrypto_p256_is_valid_point(&eph_x, &eph_y))
-		return 0;
-	/* Compute the DH point. */
-	if (!DCRYPTO_p256_point_mul(&secret_x, &secret_y,
-					d, &eph_x, &eph_y))
-		return 0;
-	/* Check for computational errors. */
-	if (!dcrypto_p256_is_valid_point(&secret_x, &secret_y))
-		return 0;
-	/* Convert secret to big-endian. */
-	reverse(&secret_x, sizeof(secret_x));
-	/* Derive shared secret. */
-	if (!DCRYPTO_hkdf(key, sizeof(key), salt, salt_len,
-				(uint8_t *) &secret_x, sizeof(secret_x),
-				info, info_len))
-		return 0;
-
-	aes_key = &key[0];
-	hmac_key = &key[AES_KEY_BYTES];
-	DCRYPTO_HMAC_SHA256_init(&ctx, hmac_key, HMAC_KEY_BYTES);
-	HASH_update(&ctx.hash, inp, in_len);
-	if (!DCRYPTO_equals(inp + in_len, DCRYPTO_HMAC_final(&ctx),
-				SHA256_DIGEST_SIZE))
-		return 0;
-
-	memmove(outp, inp, auth_data_len);
-	inp += auth_data_len;
-	outp += auth_data_len;
-	if (!DCRYPTO_aes_ctr(outp, aes_key, AES_KEY_BYTES * 8, iv,
-				inp, in_len - auth_data_len))
-		return 0;
-	return in_len;
-}
diff --git a/chip/g/dcrypto/proofs_p256.md b/chip/g/dcrypto/proofs_p256.md
deleted file mode 100644
index c0fa7ef6ad..0000000000
--- a/chip/g/dcrypto/proofs_p256.md
+++ /dev/null
@@ -1,28 +0,0 @@
-Proving P256 dcrypto code
-=========================
-
-In 2018, partial proofs of modular reduction were written in the Coq proof
-assistant.
-They can be used against the crypto accelerator code in [chip/g/dcrypto/dcrypto_p256.c](dcrypto_p256.c).
-
-The Coq code is in this file:
-[github.com/mit-plv/fiat-crypto/.../Experiments/SimplyTypedArithmetic.v](https://github.com/mit-plv/fiat-crypto/blob/e469076c37fc8b1b6d66eb700e379b9b2a093cb7/src/Experiments/SimplyTypedArithmetic.v)
-
-Specific lines of interest:
-
-Instruction specifications:
-[fiat-crypto/.../Experiments/SimplyTypedArithmetic.v#L10014](https://github.com/mit-plv/fiat-crypto/blob/e469076c37fc8b1b6d66eb700e379b9b2a093cb7/src/Experiments/SimplyTypedArithmetic.v#L10014)
-
-Printouts of verified code versions with explanatory comments are at the very
-end of the same file (which GitHub cuts off, so here is the link to the raw
-version):
-https://raw.githubusercontent.com/mit-plv/fiat-crypto/e469076c37fc8b1b6d66eb700e379b9b2a093cb7/src/Experiments/SimplyTypedArithmetic.v
-
-Additionally, the MulMod procedure in p256 uses a non-standard Barrett
-reduction optimization. In particular, it assumes that the quotient estimate is
-off by no more than 1, while most resources say it can be off by 2. This
-assumption was proven correct for most primes (including p256) here:
-
-[fiat-crypto/.../Arithmetic/BarrettReduction/Generalized.v#L140](https://github.com/mit-plv/fiat-crypto/blob/e469076c37fc8b1b6d66eb700e379b9b2a093cb7/src/Arithmetic/BarrettReduction/Generalized.v#L140)
-
-The proofs can be re-checked using Coq version 8.7 or 8.8 (or above, probably).
diff --git a/chip/g/dcrypto/rsa.c b/chip/g/dcrypto/rsa.c
deleted file mode 100644
index 8a4115398d..0000000000
--- a/chip/g/dcrypto/rsa.c
+++ /dev/null
@@ -1,743 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "dcrypto.h"
-#include "internal.h"
-
-#include "trng.h"
-#include "util.h"
-
-#include <assert.h>
-
-#include "cryptoc/sha.h"
-#include "cryptoc/sha256.h"
-#include "cryptoc/sha384.h"
-#include "cryptoc/sha512.h"
-#include "cryptoc/util.h"
-
-/* Extend the MSB throughout the word. */
-static uint32_t msb_extend(uint32_t a)
-{
-	return 0u - (a >> 31);
-}
-
-/* Return 0xFF..FF if a is zero, and zero otherwise. */
-static uint32_t is_zero(uint32_t a)
-{
-	return msb_extend(~a & (a - 1));
-}
-
-/* Select a or b based on mask.  Mask expected to be 0xFF..FF or 0. */
-static uint32_t select(uint32_t mask, uint32_t a, uint32_t b)
-{
-	return (mask & a) | (~mask & b);
-}
-
-static void MGF1_xor(uint8_t *dst, uint32_t dst_len,
-		const uint8_t *seed, uint32_t seed_len,
-		enum hashing_mode hashing)
-{
-	HASH_CTX ctx;
-	struct {
-		uint8_t b3;
-		uint8_t b2;
-		uint8_t b1;
-		uint8_t b0;
-	} cnt;
-	const uint8_t *digest;
-	const size_t hash_size = (hashing == HASH_SHA1) ? SHA_DIGEST_SIZE
-		: SHA256_DIGEST_SIZE;
-
-	cnt.b0 = cnt.b1 = cnt.b2 = cnt.b3 = 0;
-	while (dst_len) {
-		int i;
-
-		if (hashing == HASH_SHA1)
-			DCRYPTO_SHA1_init(&ctx, 0);
-		else
-			DCRYPTO_SHA256_init(&ctx, 0);
-
-		HASH_update(&ctx, seed, seed_len);
-		HASH_update(&ctx, (uint8_t *) &cnt, sizeof(cnt));
-		digest = HASH_final(&ctx);
-		for (i = 0; i < dst_len && i < hash_size; ++i)
-			*dst++ ^= *digest++;
-		dst_len -= i;
-		if (!++cnt.b0)
-			++cnt.b1;
-	}
-}
-
-/*
- * struct OAEP {                  // MSB to LSB.
- *      uint8_t zero;
- *      uint8_t seed[HASH_SIZE];
- *      uint8_t phash[HASH_SIZE];
- *      uint8_t PS[];             // Variable length (optional) zero-pad.
- *      uint8_t one;              // 0x01, message demarcator.
- *      uint8_t msg[];            // Input message.
- * };
- */
-/* encrypt */
-static int oaep_pad(uint8_t *output, uint32_t output_len,
-		const uint8_t *msg, uint32_t msg_len,
-		enum hashing_mode hashing, const char *label)
-{
-	int i;
-	const size_t hash_size = (hashing == HASH_SHA1) ? SHA_DIGEST_SIZE
-		: SHA256_DIGEST_SIZE;
-	uint8_t *const seed = output + 1;
-	uint8_t *const phash = seed + hash_size;
-	uint8_t *const PS = phash + hash_size;
-	const uint32_t max_msg_len = output_len - 2 - 2 * hash_size;
-	const uint32_t ps_len = max_msg_len - msg_len;
-	uint8_t *const one = PS + ps_len;
-	struct HASH_CTX ctx;
-
-	if (output_len < 2 + 2 * hash_size)
-		return 0;       /* Key size too small for chosen hash. */
-	if (msg_len > output_len - 2 - 2 * hash_size)
-		return 0;       /* Input message too large for key size. */
-
-	always_memset(output, 0, output_len);
-	for (i = 0; i < hash_size;) {
-		uint32_t r = rand();
-
-		seed[i++] = r >> 0;
-		seed[i++] = r >> 8;
-		seed[i++] = r >> 16;
-		seed[i++] = r >> 24;
-	}
-
-	if (hashing == HASH_SHA1)
-		DCRYPTO_SHA1_init(&ctx, 0);
-	else
-		DCRYPTO_SHA256_init(&ctx, 0);
-
-	HASH_update(&ctx, label, label ? strlen(label) + 1 : 0);
-	memcpy(phash, HASH_final(&ctx), hash_size);
-	*one = 1;
-	memcpy(one + 1, msg, msg_len);
-	MGF1_xor(phash, hash_size + 1 + max_msg_len,
-		seed, hash_size, hashing);
-	MGF1_xor(seed, hash_size, phash, hash_size + 1 + max_msg_len,
-		hashing);
-	return 1;
-}
-
-/* decrypt */
-static int check_oaep_pad(uint8_t *out, uint32_t *out_len,
-			uint8_t *padded, uint32_t padded_len,
-			enum hashing_mode hashing, const char *label)
-{
-	const size_t hash_size = (hashing == HASH_SHA1) ? SHA_DIGEST_SIZE
-		: SHA256_DIGEST_SIZE;
-	uint8_t *seed = padded + 1;
-	uint8_t *phash = seed + hash_size;
-	uint8_t *PS = phash + hash_size;
-	const uint32_t max_msg_len = padded_len - 2 - 2 * hash_size;
-	struct HASH_CTX ctx;
-	size_t one_index = 0;
-	uint32_t looking_for_one_byte = ~0;
-	int bad;
-	int i;
-
-	if (padded_len < 2 + 2 * hash_size)
-		return 0;       /* Invalid input size. */
-
-	/* Recover seed. */
-	MGF1_xor(seed, hash_size, phash, hash_size + 1 + max_msg_len, hashing);
-	/* Recover db. */
-	MGF1_xor(phash, hash_size + 1 + max_msg_len, seed, hash_size, hashing);
-
-	if (hashing == HASH_SHA1)
-		DCRYPTO_SHA1_init(&ctx, 0);
-	else
-		DCRYPTO_SHA256_init(&ctx, 0);
-	HASH_update(&ctx, label, label ? strlen(label) + 1 : 0);
-
-	bad = !DCRYPTO_equals(phash, HASH_final(&ctx), hash_size);
-	bad |= padded[0];
-
-	for (i = PS - padded; i <  padded_len; i++) {
-		uint32_t equals0 = is_zero(padded[i]);
-		uint32_t equals1 = is_zero(padded[i] ^ 1);
-
-		one_index = select(looking_for_one_byte & equals1,
-				i, one_index);
-		looking_for_one_byte = select(equals1, 0, looking_for_one_byte);
-
-		/* Bad padding if padded[i] is neither 1 nor 0. */
-		bad |= looking_for_one_byte & ~equals0;
-	}
-
-	bad |= looking_for_one_byte;
-
-	if (bad)
-		return 0;
-
-	one_index++;
-	if (*out_len < padded_len - one_index)
-		return 0;
-	memcpy(out, padded + one_index, padded_len - one_index);
-	*out_len = padded_len - one_index;
-	return 1;
-}
-
-/* Constants from RFC 3447. */
-#define RSA_PKCS1_PADDING_SIZE 11
-
-/* encrypt */
-static int pkcs1_type2_pad(uint8_t *padded, uint32_t padded_len,
-		const uint8_t *in, uint32_t in_len)
-{
-	uint32_t PS_len;
-
-	if (padded_len < RSA_PKCS1_PADDING_SIZE)
-		return 0;
-	if (in_len > padded_len - RSA_PKCS1_PADDING_SIZE)
-		return 0;
-	PS_len = padded_len - 3 - in_len;
-
-	*(padded++) = 0;
-	*(padded++) = 2;
-	while (PS_len) {
-		int i;
-		uint32_t r = rand();
-
-		for (i = 0; i < 4 && PS_len; i++) {
-			uint8_t b = ((uint8_t *) &r)[i];
-
-			if (b) {
-				*padded++ = b;
-				PS_len--;
-			}
-		}
-	}
-	*(padded++) = 0;
-	memcpy(padded, in, in_len);
-	return 1;
-}
-
-/* decrypt */
-static int check_pkcs1_type2_pad(uint8_t *out, uint32_t *out_len,
-				const uint8_t *padded, uint32_t padded_len)
-{
-	int i;
-	int valid;
-	uint32_t zero_index = 0;
-	uint32_t looking_for_index = ~0;
-
-	if (padded_len < RSA_PKCS1_PADDING_SIZE)
-		return 0;
-
-	valid = (padded[0] == 0);
-	valid &= (padded[1] == 2);
-
-	for (i = 2; i < padded_len; i++) {
-		uint32_t found = is_zero(padded[i]);
-
-		zero_index = select(looking_for_index & found, i, zero_index);
-		looking_for_index = select(found, 0, looking_for_index);
-	}
-
-	zero_index++;
-
-	valid &= ~looking_for_index;
-	valid &= (zero_index >= RSA_PKCS1_PADDING_SIZE);
-	if (!valid)
-		return 0;
-
-	if (*out_len < padded_len - zero_index)
-		return 0;
-	memcpy(out, &padded[zero_index], padded_len - zero_index);
-	*out_len = padded_len - zero_index;
-	return 1;
-}
-
-static const uint8_t SHA1_DER[] = {
-	0x30, 0x21, 0x30, 0x09, 0x06, 0x05, 0x2b, 0x0e,
-	0x03, 0x02, 0x1a, 0x05, 0x00, 0x04, 0x14
-};
-static const uint8_t SHA256_DER[] = {
-	0x30, 0x31, 0x30, 0x0D, 0x06, 0x09, 0x60, 0x86,
-	0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05,
-	0x00, 0x04, 0x20
-};
-static const uint8_t SHA384_DER[] = {
-	0x30, 0x41, 0x30, 0x0d, 0x06, 0x09, 0x60, 0x86,
-	0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x02, 0x05,
-	0x00, 0x04, 0x30
-};
-static const uint8_t SHA512_DER[] = {
-	0x30, 0x51, 0x30, 0x0d, 0x06, 0x09, 0x60, 0x86,
-	0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x03, 0x05,
-	0x00, 0x04, 0x40
-};
-
-static int pkcs1_get_der(enum hashing_mode hashing, const uint8_t **der,
-			uint32_t *der_size, uint32_t *hash_size)
-{
-	switch (hashing) {
-	case HASH_SHA1:
-		*der = &SHA1_DER[0];
-		*der_size = sizeof(SHA1_DER);
-		*hash_size = SHA_DIGEST_SIZE;
-		break;
-	case HASH_SHA256:
-		*der = &SHA256_DER[0];
-		*der_size = sizeof(SHA256_DER);
-		*hash_size = SHA256_DIGEST_SIZE;
-		break;
-	case HASH_SHA384:
-		*der = &SHA384_DER[0];
-		*der_size = sizeof(SHA384_DER);
-		*hash_size = SHA384_DIGEST_SIZE;
-		break;
-	case HASH_SHA512:
-		*der = &SHA512_DER[0];
-		*der_size = sizeof(SHA512_DER);
-		*hash_size = SHA512_DIGEST_SIZE;
-		break;
-	case HASH_NULL:
-		*der = NULL;
-		*der_size = 0;
-		*hash_size = 0;  /* any size allowed */
-		break;
-	default:
-		return 0;
-	}
-
-	return 1;
-}
-
-/* sign */
-static int pkcs1_type1_pad(uint8_t *padded, uint32_t padded_len,
-			const uint8_t *in, uint32_t in_len,
-			enum hashing_mode hashing)
-{
-	const uint8_t *der;
-	uint32_t der_size;
-	uint32_t hash_size;
-	uint32_t ps_len;
-
-	if (!pkcs1_get_der(hashing, &der, &der_size, &hash_size))
-		return 0;
-	if (padded_len < RSA_PKCS1_PADDING_SIZE + der_size)
-		return 0;
-	if (!in_len || (hash_size && in_len != hash_size))
-		return 0;
-	if (in_len > padded_len - RSA_PKCS1_PADDING_SIZE - der_size)
-		return 0;
-	ps_len = padded_len - 3 - der_size - in_len;
-
-	*(padded++) = 0;
-	*(padded++) = 1;
-	always_memset(padded, 0xFF, ps_len);
-	padded += ps_len;
-	*(padded++) = 0;
-	memcpy(padded, der, der_size);
-	padded += der_size;
-	memcpy(padded, in, in_len);
-	return 1;
-}
-
-/* verify */
-static int check_pkcs1_type1_pad(const uint8_t *msg, uint32_t msg_len,
-				const uint8_t *padded, uint32_t padded_len,
-				enum hashing_mode hashing)
-{
-	int i;
-	const uint8_t *der;
-	uint32_t der_size;
-	uint32_t hash_size;
-	uint32_t ps_len;
-
-	if (!pkcs1_get_der(hashing, &der, &der_size, &hash_size))
-		return 0;
-	if (msg_len != hash_size)
-		return 0;
-	if (padded_len < RSA_PKCS1_PADDING_SIZE + der_size + hash_size)
-		return 0;
-	ps_len = padded_len - 3 - der_size - hash_size;
-
-	if (padded[0] != 0 || padded[1] != 1)
-		return 0;
-	for (i = 2; i < ps_len + 2; i++) {
-		if (padded[i] != 0xFF)
-			return 0;
-	}
-
-	if (padded[i++] != 0)
-		return 0;
-	if (!DCRYPTO_equals(&padded[i], der, der_size))
-		return 0;
-	i += der_size;
-	return DCRYPTO_equals(msg, &padded[i], hash_size);
-}
-
-/* sign */
-static int pkcs1_pss_pad(uint8_t *padded, uint32_t padded_len,
-			const uint8_t *in, uint32_t in_len,
-			enum hashing_mode hashing)
-{
-	const uint32_t hash_size = (hashing == HASH_SHA1) ? SHA_DIGEST_SIZE
-		: SHA256_DIGEST_SIZE;
-	const uint32_t salt_len = MIN(padded_len - hash_size - 2, hash_size);
-	uint32_t db_len;
-	uint32_t ps_len;
-	struct HASH_CTX ctx;
-
-	if (in_len != hash_size)
-		return 0;
-	if (padded_len < hash_size + 2)
-		return 0;
-	db_len = padded_len - hash_size - 1;
-
-	if (hashing == HASH_SHA1)
-		DCRYPTO_SHA1_init(&ctx, 0);
-	else
-		DCRYPTO_SHA256_init(&ctx, 0);
-
-	/* Pilfer bits of output for temporary use. */
-	memset(padded, 0, 8);
-	HASH_update(&ctx, padded, 8);
-	HASH_update(&ctx, in, in_len);
-	/* Pilfer bits of output for temporary use. */
-	rand_bytes(padded, salt_len);
-	HASH_update(&ctx, padded, salt_len);
-
-	/* Output hash. */
-	memcpy(padded + db_len, HASH_final(&ctx), hash_size);
-
-	/* Prepare DB. */
-	ps_len = db_len - salt_len - 1;
-	memmove(padded + ps_len + 1, padded, salt_len);
-	memset(padded, 0, ps_len);
-	padded[ps_len] = 0x01;
-	MGF1_xor(padded, db_len, padded + db_len, hash_size, hashing);
-
-	/* Clear most significant bit. */
-	padded[0] &= 0x7F;
-	/* Set trailing byte. */
-	padded[padded_len - 1] = 0xBC;
-	return 1;
-}
-
-/* verify */
-static int check_pkcs1_pss_pad(const uint8_t *in, uint32_t in_len,
-			uint8_t *padded, uint32_t padded_len,
-			enum hashing_mode hashing)
-{
-	const uint32_t hash_size = (hashing == HASH_SHA1) ? SHA_DIGEST_SIZE
-		: SHA256_DIGEST_SIZE;
-	const uint8_t zeros[8] = {0, 0, 0, 0, 0, 0, 0, 0};
-	uint32_t db_len;
-	uint32_t max_ps_len;
-	uint32_t salt_len;
-	HASH_CTX ctx;
-	int bad = 0;
-	int i;
-
-	if (in_len != hash_size)
-		return 0;
-	if (padded_len < hash_size + 2)
-		return 0;
-	db_len = padded_len - hash_size - 1;
-
-	/* Top bit should be zero. */
-	bad |= padded[0] & 0x80;
-	/* Check trailing byte. */
-	bad |= padded[padded_len - 1] ^ 0xBC;
-
-	/* Recover DB. */
-	MGF1_xor(padded, db_len, padded + db_len, hash_size, hashing);
-	/* Clear top bit. */
-	padded[0] &= 0x7F;
-	/* Verify padding2. */
-	max_ps_len = db_len - 1;
-	for (i = 0; i < max_ps_len; i++) {
-		if (padded[i] == 0x01)
-			break;
-		else
-			bad |= padded[i];
-	}
-	bad |= (padded[i] ^ 0x01);
-	/* Continue with zero-length salt if 0x01 was not found. */
-	salt_len = max_ps_len - i;
-
-	if (hashing == HASH_SHA1)
-		DCRYPTO_SHA1_init(&ctx, 0);
-	else
-		DCRYPTO_SHA256_init(&ctx, 0);
-	HASH_update(&ctx, zeros, sizeof(zeros));
-	HASH_update(&ctx, in, in_len);
-	HASH_update(&ctx, padded + db_len - salt_len, salt_len);
-	bad |= !DCRYPTO_equals(padded + db_len, HASH_final(&ctx), hash_size);
-	return !bad;
-}
-
-static int check_modulus_params(
-	const struct LITE_BIGNUM *N, size_t rsa_max_bytes, uint32_t *out_len)
-{
-	if (bn_size(N) > rsa_max_bytes)
-		return 0;                      /* Unsupported key size. */
-	if (!bn_check_topbit(N))               /* Check that top bit is set. */
-		return 0;
-	if (out_len && *out_len < bn_size(N))
-		return 0;                      /* Output buffer too small. */
-	return 1;
-}
-
-int DCRYPTO_rsa_encrypt(struct RSA *rsa, uint8_t *out, uint32_t *out_len,
-			const uint8_t *in, uint32_t in_len,
-			enum padding_mode padding, enum hashing_mode hashing,
-			const char *label)
-{
-	uint8_t *p;
-	uint32_t padded_buf[RSA_MAX_WORDS];
-	uint32_t e_buf[LITE_BN_BYTES / sizeof(uint32_t)];
-
-	struct LITE_BIGNUM padded;
-	struct LITE_BIGNUM encrypted;
-	int ret;
-
-	if (!check_modulus_params(&rsa->N, sizeof(padded_buf), out_len))
-		return 0;
-
-	bn_init(&padded, padded_buf, bn_size(&rsa->N));
-	bn_init(&encrypted, out, bn_size(&rsa->N));
-
-	switch (padding) {
-	case PADDING_MODE_OAEP:
-		if (!oaep_pad((uint8_t *) padded.d, bn_size(&padded),
-				(const uint8_t *) in, in_len, hashing, label))
-			return 0;
-		break;
-	case PADDING_MODE_PKCS1:
-		if (!pkcs1_type2_pad((uint8_t *) padded.d, bn_size(&padded),
-					(const uint8_t *) in, in_len))
-			return 0;
-		break;
-	case PADDING_MODE_NULL:
-		/* Input is allowed to have more bytes than N, in
-		 * which case the excess must be zero. */
-		for (; in_len > bn_size(&padded); in_len--)
-			if (*in++ != 0)
-				return 0;
-		p = (uint8_t *) padded.d;
-		/* If in_len < bn_size(&padded), padded will
-		 * have leading zero bytes. */
-		memcpy(&p[bn_size(&padded) - in_len], in, in_len);
-		/* TODO(ngm): in may be > N, bn_mod_exp() should
-		 * handle this case. */
-		break;
-	default:
-		return 0;                       /* Unsupported padding mode. */
-	}
-
-	/* Reverse from big-endian to little-endian notation. */
-	reverse((uint8_t *) padded.d, bn_size(&padded));
-	ret = bn_modexp_word(&encrypted, &padded, rsa->e, &rsa->N);
-	/* Back to big-endian notation. */
-	reverse((uint8_t *) encrypted.d, bn_size(&encrypted));
-	*out_len = bn_size(&encrypted);
-
-	always_memset(padded_buf, 0, sizeof(padded_buf));
-	always_memset(e_buf, 0, sizeof(e_buf));
-	return ret;
-}
-
-int DCRYPTO_rsa_decrypt(struct RSA *rsa, uint8_t *out, uint32_t *out_len,
-			const uint8_t *in, const uint32_t in_len,
-			enum padding_mode padding, enum hashing_mode hashing,
-			const char *label)
-{
-	uint32_t encrypted_buf[RSA_MAX_WORDS];
-	uint32_t padded_buf[RSA_MAX_WORDS];
-
-	struct LITE_BIGNUM encrypted;
-	struct LITE_BIGNUM padded;
-	int ret;
-
-	if (!check_modulus_params(&rsa->N, sizeof(padded_buf), NULL))
-		return 0;
-	if (in_len != bn_size(&rsa->N))
-		return 0;                      /* Invalid input length. */
-
-	/* TODO(ngm): this copy can be eliminated if input may be modified. */
-	bn_init(&encrypted, encrypted_buf, in_len);
-	memcpy(encrypted_buf, in, in_len);
-	bn_init(&padded, padded_buf, in_len);
-
-	/* Reverse from big-endian to little-endian notation. */
-	reverse((uint8_t *) encrypted.d, encrypted.dmax * LITE_BN_BYTES);
-	ret = bn_modexp_blinded(&padded, &encrypted, &rsa->d, &rsa->N, rsa->e);
-	/* Back to big-endian notation. */
-	reverse((uint8_t *) padded.d, padded.dmax * LITE_BN_BYTES);
-
-	switch (padding) {
-	case PADDING_MODE_OAEP:
-		if (!check_oaep_pad(out, out_len, (uint8_t *) padded.d,
-					bn_size(&padded), hashing, label))
-			ret = 0;
-		break;
-	case PADDING_MODE_PKCS1:
-		if (!check_pkcs1_type2_pad(
-				out, out_len, (const uint8_t *) padded.d,
-				bn_size(&padded)))
-			ret = 0;
-		break;
-	case PADDING_MODE_NULL:
-		if (*out_len < bn_size(&padded)) {
-			ret = 0;
-		} else {
-			*out_len = bn_size(&padded);
-			memcpy(out, padded.d, *out_len);
-		}
-		break;
-	default:
-		/* Unsupported padding mode. */
-		ret = 0;
-		break;
-	}
-
-	always_memset(encrypted_buf, 0, sizeof(encrypted_buf));
-	always_memset(padded_buf, 0, sizeof(padded_buf));
-	return ret;
-}
-
-int DCRYPTO_rsa_sign(struct RSA *rsa, uint8_t *out, uint32_t *out_len,
-		const uint8_t *in, const uint32_t in_len,
-		enum padding_mode padding, enum hashing_mode hashing)
-{
-	uint32_t padded_buf[RSA_MAX_WORDS];
-
-	struct LITE_BIGNUM padded;
-	struct LITE_BIGNUM signature;
-	int ret;
-
-	if (!check_modulus_params(&rsa->N, sizeof(padded_buf), out_len))
-		return 0;
-
-	bn_init(&padded, padded_buf, bn_size(&rsa->N));
-	bn_init(&signature, out, bn_size(&rsa->N));
-
-	switch (padding) {
-	case PADDING_MODE_PKCS1:
-		if (!pkcs1_type1_pad((uint8_t *) padded.d, bn_size(&padded),
-					(const uint8_t *) in, in_len, hashing))
-			return 0;
-		break;
-	case PADDING_MODE_PSS:
-		if (!pkcs1_pss_pad((uint8_t *) padded.d, bn_size(&padded),
-					(const uint8_t *) in, in_len, hashing))
-			return 0;
-		break;
-	default:
-		return 0;
-	}
-
-	/* Reverse from big-endian to little-endian notation. */
-	reverse((uint8_t *) padded.d, bn_size(&padded));
-	ret = bn_modexp_blinded(&signature, &padded, &rsa->d, &rsa->N, rsa->e);
-	/* Back to big-endian notation. */
-	reverse((uint8_t *) signature.d, bn_size(&signature));
-	*out_len = bn_size(&rsa->N);
-
-	always_memset(padded_buf, 0, sizeof(padded_buf));
-	return ret;
-}
-
-int DCRYPTO_rsa_verify(const struct RSA *rsa, const uint8_t *digest,
-		uint32_t digest_len, const uint8_t *sig,
-		const uint32_t sig_len,	enum padding_mode padding,
-		enum hashing_mode hashing)
-{
-	uint32_t padded_buf[RSA_WORDS_4K];
-	uint32_t signature_buf[RSA_WORDS_4K];
-
-	struct LITE_BIGNUM padded;
-	struct LITE_BIGNUM signature;
-	int ret;
-
-	if (!check_modulus_params(&rsa->N, sizeof(padded_buf), NULL))
-		return 0;
-	if (sig_len != bn_size(&rsa->N))
-		return 0;                      /* Invalid input length. */
-
-	bn_init(&signature, signature_buf, bn_size(&rsa->N));
-	memcpy(signature_buf, sig, bn_size(&rsa->N));
-	bn_init(&padded, padded_buf, bn_size(&rsa->N));
-
-	/* Reverse from big-endian to little-endian notation. */
-	reverse((uint8_t *) signature.d, bn_size(&signature));
-	ret = bn_modexp_word(&padded, &signature, rsa->e, &rsa->N);
-	/* Back to big-endian notation. */
-	reverse((uint8_t *) padded.d, bn_size(&padded));
-
-	switch (padding) {
-	case PADDING_MODE_PKCS1:
-		if (!check_pkcs1_type1_pad(
-				digest, digest_len, (uint8_t *) padded.d,
-				bn_size(&padded), hashing))
-			ret = 0;
-		break;
-	case PADDING_MODE_PSS:
-		if (!check_pkcs1_pss_pad(
-				digest, digest_len, (uint8_t *) padded.d,
-				bn_size(&padded), hashing))
-			ret = 0;
-		break;
-	default:
-		/* Unsupported padding mode. */
-		ret = 0;
-		break;
-	}
-
-	always_memset(padded_buf, 0, sizeof(padded_buf));
-	always_memset(signature_buf, 0, sizeof(signature_buf));
-	return ret;
-}
-
-int DCRYPTO_rsa_key_compute(struct LITE_BIGNUM *N, struct LITE_BIGNUM *d,
-			struct LITE_BIGNUM *p, struct LITE_BIGNUM *q,
-			uint32_t e_buf)
-{
-	uint32_t ONE_buf = 1;
-	uint32_t phi_buf[RSA_MAX_WORDS];
-	uint32_t q_buf[RSA_MAX_WORDS / 2 + 1];
-
-	struct LITE_BIGNUM ONE;
-	struct LITE_BIGNUM e;
-	struct LITE_BIGNUM phi;
-	struct LITE_BIGNUM q_local;
-
-	DCRYPTO_bn_wrap(&ONE, &ONE_buf, sizeof(ONE_buf));
-	DCRYPTO_bn_wrap(&phi, phi_buf, bn_size(N));
-	if (!q) {
-		/* q not provided, calculate it. */
-		memcpy(phi_buf, N->d, bn_size(N));
-		bn_init(&q_local, q_buf, bn_size(p));
-		q = &q_local;
-
-		if (!DCRYPTO_bn_div(q, NULL, &phi, p))
-			return 0;
-
-		/* Check that p * q == N */
-		DCRYPTO_bn_mul(&phi, p, q);
-		if (!bn_eq(N, &phi))
-			return 0;
-	} else {
-		DCRYPTO_bn_mul(N, p, q);
-		memcpy(phi_buf, N->d, bn_size(N));
-	}
-
-	bn_sub(&phi, p);
-	bn_sub(&phi, q);
-	bn_add(&phi, &ONE);
-	DCRYPTO_bn_wrap(&e, &e_buf, sizeof(e_buf));
-	return bn_modinv_vartime(d, &e, &phi);
-}
diff --git a/chip/g/dcrypto/sha1.c b/chip/g/dcrypto/sha1.c
deleted file mode 100644
index 912c4500f5..0000000000
--- a/chip/g/dcrypto/sha1.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "dcrypto.h"
-#include "internal.h"
-#include "registers.h"
-
-#include "cryptoc/sha.h"
-
-static void dcrypto_sha1_init(SHA_CTX *ctx);
-static const uint8_t *dcrypto_sha1_final(SHA_CTX *unused);
-
-/*
- * Hardware SHA implementation.
- */
-static const HASH_VTAB HW_SHA1_VTAB = {
-	dcrypto_sha1_init,
-	dcrypto_sha_update,
-	dcrypto_sha1_final,
-	DCRYPTO_SHA1_hash,
-	SHA_DIGEST_SIZE,
-#ifdef SHA512_SUPPORT
-	SHA_BLOCK_SIZE,
-#endif
-};
-
-/* Requires dcrypto_grab_sha_hw() to be called first. */
-static void dcrypto_sha1_init(SHA_CTX *ctx)
-{
-	ctx->f = &HW_SHA1_VTAB;
-	dcrypto_sha_init(SHA1_MODE);
-}
-
-/* Select and initialize either the software or hardware
- * implementation.  If "multi-threaded" behaviour is required, then
- * callers must set sw_required to 1.  This is because SHA1 state
- * internal to the hardware cannot be extracted, so it is not possible
- * to suspend and resume a hardware based SHA operation.
- *
- * If the caller has no preference as to implementation, then hardware
- * is preferred based on availability.  Hardware is considered to be
- * in use between init() and finished() calls. */
-void DCRYPTO_SHA1_init(SHA_CTX *ctx, uint32_t sw_required)
-{
-	if (!sw_required && dcrypto_grab_sha_hw())
-		dcrypto_sha1_init(ctx);
-	else
-		SHA_init(ctx);
-}
-
-static const uint8_t *dcrypto_sha1_final(SHA_CTX *ctx)
-{
-	dcrypto_sha_wait(SHA1_MODE, (uint32_t *) ctx->buf);
-	return ctx->buf;
-}
-
-const uint8_t *DCRYPTO_SHA1_hash(const void *data, uint32_t n,
-				uint8_t *digest)
-{
-	if (dcrypto_grab_sha_hw())
-		/* dcrypto_sha_wait() will release the hw. */
-		dcrypto_sha_hash(SHA1_MODE, data, n, digest);
-	else
-		SHA_hash(data, n, digest);
-	return digest;
-}
diff --git a/chip/g/dcrypto/sha256.c b/chip/g/dcrypto/sha256.c
deleted file mode 100644
index 788ca2cb97..0000000000
--- a/chip/g/dcrypto/sha256.c
+++ /dev/null
@@ -1,198 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "dcrypto.h"
-#include "internal.h"
-#include "registers.h"
-#include "util.h"
-
-#include "cryptoc/sha256.h"
-
-static void dcrypto_sha256_init(LITE_SHA256_CTX *ctx);
-static const uint8_t *dcrypto_sha256_final(LITE_SHA256_CTX *ctx);
-
-#ifdef SECTION_IS_RO
-/* RO is single threaded. */
-#define mutex_lock(x)
-#define mutex_unlock(x)
-static inline int dcrypto_grab_sha_hw(void)
-{
-	return 1;
-}
-static inline void dcrypto_release_sha_hw(void)
-{
-}
-#else
-#include "task.h"
-static struct mutex hw_busy_mutex;
-
-static int hw_busy;
-
-int dcrypto_grab_sha_hw(void)
-{
-	int rv = 0;
-
-	mutex_lock(&hw_busy_mutex);
-	if (!hw_busy) {
-		rv = 1;
-		hw_busy = 1;
-	}
-	mutex_unlock(&hw_busy_mutex);
-
-	return rv;
-}
-
-void dcrypto_release_sha_hw(void)
-{
-	mutex_lock(&hw_busy_mutex);
-	hw_busy = 0;
-	mutex_unlock(&hw_busy_mutex);
-}
-
-#endif  /* ! SECTION_IS_RO */
-
-void dcrypto_sha_wait(enum sha_mode mode, uint32_t *digest)
-{
-	int i;
-	const int digest_len = (mode == SHA1_MODE) ?
-		SHA_DIGEST_SIZE :
-		SHA256_DIGEST_SIZE;
-
-	/* Stop LIVESTREAM mode. */
-	GREG32(KEYMGR, SHA_TRIG) = GC_KEYMGR_SHA_TRIG_TRIG_STOP_MASK;
-
-	/* Wait for SHA DONE interrupt. */
-	while (!GREG32(KEYMGR, SHA_ITOP))
-		;
-
-	/* Read out final digest. */
-	for (i = 0; i < digest_len / 4; ++i)
-		*digest++ = GR_KEYMGR_SHA_HASH(i);
-	dcrypto_release_sha_hw();
-}
-
-/* Hardware SHA implementation. */
-static const HASH_VTAB HW_SHA256_VTAB = {
-	dcrypto_sha256_init,
-	dcrypto_sha_update,
-	dcrypto_sha256_final,
-	DCRYPTO_SHA256_hash,
-	SHA256_DIGEST_SIZE,
-#ifdef SHA512_SUPPORT
-	SHA256_BLOCK_SIZE,
-#endif
-};
-
-void dcrypto_sha_hash(enum sha_mode mode, const uint8_t *data, uint32_t n,
-		uint8_t *digest)
-{
-	dcrypto_sha_init(mode);
-	dcrypto_sha_update(NULL, data, n);
-	dcrypto_sha_wait(mode, (uint32_t *) digest);
-}
-
-void dcrypto_sha_update(struct HASH_CTX *unused,
-			const void *data, uint32_t n)
-{
-	const uint8_t *bp = (const uint8_t *) data;
-	const uint32_t *wp;
-
-	/* Feed unaligned start bytes. */
-	while (n != 0 && ((uint32_t)bp & 3)) {
-		GREG8(KEYMGR, SHA_INPUT_FIFO) = *bp++;
-		n -= 1;
-	}
-
-	/* Feed groups of aligned words. */
-	wp = (uint32_t *)bp;
-	while (n >= 8*4) {
-		GREG32(KEYMGR, SHA_INPUT_FIFO) = *wp++;
-		GREG32(KEYMGR, SHA_INPUT_FIFO) = *wp++;
-		GREG32(KEYMGR, SHA_INPUT_FIFO) = *wp++;
-		GREG32(KEYMGR, SHA_INPUT_FIFO) = *wp++;
-		GREG32(KEYMGR, SHA_INPUT_FIFO) = *wp++;
-		GREG32(KEYMGR, SHA_INPUT_FIFO) = *wp++;
-		GREG32(KEYMGR, SHA_INPUT_FIFO) = *wp++;
-		GREG32(KEYMGR, SHA_INPUT_FIFO) = *wp++;
-		n -= 8*4;
-	}
-	/* Feed individual aligned words. */
-	while (n >= 4) {
-		GREG32(KEYMGR, SHA_INPUT_FIFO) = *wp++;
-		n -= 4;
-	}
-
-	/* Feed remaing bytes. */
-	bp = (uint8_t *) wp;
-	while (n != 0) {
-		GREG8(KEYMGR, SHA_INPUT_FIFO) = *bp++;
-		n -= 1;
-	}
-}
-
-void dcrypto_sha_init(enum sha_mode mode)
-{
-	int val;
-
-	/* Stop LIVESTREAM mode, in case final() was not called. */
-	GREG32(KEYMGR, SHA_TRIG) = GC_KEYMGR_SHA_TRIG_TRIG_STOP_MASK;
-	/* Clear interrupt status. */
-	GREG32(KEYMGR, SHA_ITOP) = 0;
-
-	/* Enable streaming mode. */
-	val = GC_KEYMGR_SHA_CFG_EN_LIVESTREAM_MASK;
-	/* Enable SHA DONE interrupt. */
-	val |= GC_KEYMGR_SHA_CFG_EN_INT_EN_DONE_MASK;
-	/* Select SHA mode. */
-	if (mode == SHA1_MODE)
-		val |= GC_KEYMGR_SHA_CFG_EN_SHA1_MASK;
-	GREG32(KEYMGR, SHA_CFG_EN) = val;
-
-	/* Turn off random nops (which are enabled by default). */
-	GWRITE_FIELD(KEYMGR, SHA_RAND_STALL_CTL, STALL_EN, 0);
-	/* Configure random nop percentage at 12%. */
-	GWRITE_FIELD(KEYMGR, SHA_RAND_STALL_CTL, FREQ, 2);
-	/* Now turn on random nops. */
-	GWRITE_FIELD(KEYMGR, SHA_RAND_STALL_CTL, STALL_EN, 1);
-
-	/* Start SHA engine. */
-	GREG32(KEYMGR, SHA_TRIG) = GC_KEYMGR_SHA_TRIG_TRIG_GO_MASK;
-}
-
-static void dcrypto_sha256_init(LITE_SHA256_CTX *ctx)
-{
-	ctx->f = &HW_SHA256_VTAB;
-	dcrypto_sha_init(SHA256_MODE);
-}
-
-/* Requires dcrypto_grab_sha_hw() to be called first. */
-void DCRYPTO_SHA256_init(LITE_SHA256_CTX *ctx, uint32_t sw_required)
-{
-	if (!sw_required && dcrypto_grab_sha_hw())
-		dcrypto_sha256_init(ctx);
-#ifndef SECTION_IS_RO
-	else
-		SHA256_init(ctx);
-#endif
-}
-
-static const uint8_t *dcrypto_sha256_final(LITE_SHA256_CTX *ctx)
-{
-	dcrypto_sha_wait(SHA256_MODE, (uint32_t *) ctx->buf);
-	return ctx->buf;
-}
-
-const uint8_t *DCRYPTO_SHA256_hash(const void *data, uint32_t n,
-				uint8_t *digest)
-{
-	if (dcrypto_grab_sha_hw())
-		/* dcrypto_sha_wait() will release the hw. */
-		dcrypto_sha_hash(SHA256_MODE, data, n, digest);
-#ifndef SECTION_IS_RO
-	else
-		SHA256_hash(data, n, digest);
-#endif
-	return digest;
-}
diff --git a/chip/g/dcrypto/sha384.c b/chip/g/dcrypto/sha384.c
deleted file mode 100644
index 6f3c6ca096..0000000000
--- a/chip/g/dcrypto/sha384.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "dcrypto.h"
-#include "internal.h"
-
-#include "cryptoc/sha384.h"
-
-void DCRYPTO_SHA384_init(LITE_SHA512_CTX *ctx)
-{
-	SHA384_init(ctx);
-}
-
-const uint8_t *DCRYPTO_SHA384_hash(const void *data, uint32_t n,
-				uint8_t *digest)
-{
-	return SHA384_hash(data, n, digest);
-}
diff --git a/chip/g/dcrypto/sha512.c b/chip/g/dcrypto/sha512.c
deleted file mode 100644
index 1446970174..0000000000
--- a/chip/g/dcrypto/sha512.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "dcrypto.h"
-#include "internal.h"
-
-#include "cryptoc/sha512.h"
-
-void DCRYPTO_SHA512_init(LITE_SHA512_CTX *ctx)
-{
-	SHA512_init(ctx);
-}
-
-const uint8_t *DCRYPTO_SHA512_hash(const void *data, uint32_t n,
-				uint8_t *digest)
-{
-	return SHA512_hash(data, n, digest);
-}
diff --git a/chip/g/dcrypto/x509.c b/chip/g/dcrypto/x509.c
deleted file mode 100644
index 81f1674db1..0000000000
--- a/chip/g/dcrypto/x509.c
+++ /dev/null
@@ -1,545 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "dcrypto.h"
-
-#include <stdint.h>
-
-/* Limit the size of long form encoded objects to < 64 kB. */
-#define MAX_ASN1_OBJ_LEN_BYTES 3
-
-/* Reserve space for TLV encoding */
-#define SEQ_SMALL 2  /* < 128 bytes (1B type, 1B 7-bit length) */
-#define SEQ_MEDIUM 3 /* < 256 bytes (1B type, 1B length size, 1B length) */
-#define SEQ_LARGE 4  /* < 65536 bytes (1B type, 1B length size, 2B length) */
-
-/* Tag related constants. */
-enum {
-	V_ASN1_INT = 0x02,
-	V_ASN1_BIT_STRING  = 0x03,
-	V_ASN1_BYTES = 0x04,
-	V_ASN1_OBJ = 0x06,
-	V_ASN1_UTF8 = 0x0c,
-	V_ASN1_SEQUENCE    = 0x10,
-	V_ASN1_SET         = 0x11,
-	V_ASN1_ASCII = 0x13,
-	V_ASN1_TIME = 0x18,
-	V_ASN1_CONSTRUCTED = 0x20,
-	/* short helpers */
-	V_BITS = V_ASN1_BIT_STRING,
-	V_SEQ = V_ASN1_CONSTRUCTED | V_ASN1_SEQUENCE,
-	V_SET = V_ASN1_CONSTRUCTED | V_ASN1_SET,
-};
-
-struct asn1 {
-	uint8_t *p;
-	size_t n;
-};
-
-
-#define SEQ_START(X, T, L) \
-	do {                     \
-		int __old = (X).n;       \
-		uint8_t __t = (T);       \
-		int __l = (L);           \
-		(X).n += __l;
-#define SEQ_END(X)                                                             \
-	(X).n = asn1_seq((X).p + __old, __t, __l, (X).n - __old - __l) + __old;\
-	}                                                                      \
-	while (0)
-
-/* The SHA256 OID, from https://tools.ietf.org/html/rfc5754#section-3.2
- * Only the object bytes below, the DER encoding header ([0x30 0x0d])
- * is verified by the parser. */
-static const uint8_t OID_SHA256_WITH_RSA_ENCRYPTION[13] = {
-	0x06, 0x09, 0x2a, 0x86, 0x48, 0x86, 0xf7, 0x0d,
-	0x01, 0x01, 0x0b, 0x05, 0x00
-};
-static const uint8_t OID_commonName[3] = {0x55, 0x04, 0x03};
-static const uint8_t OID_ecdsa_with_SHA256[8] = {0x2A, 0x86, 0x48, 0xCE,
-						 0x3D, 0x04, 0x03, 0x02};
-static const uint8_t OID_id_ecPublicKey[7] = {0x2A, 0x86, 0x48, 0xCE, 0x3D,
-					      0x02, 0x01};
-static const uint8_t OID_prime256v1[8] = {0x2A, 0x86, 0x48, 0xCE,
-					  0x3D, 0x03, 0x01, 0x07};
-static const uint8_t OID_fido_u2f[11] = {0x2B, 0x06, 0x01, 0x04, 0x01, 0x82,
-					 0xE5, 0x1C, 0x02, 0x01, 0x01};
-#define OID(X) sizeof(OID_##X), OID_##X
-
-/* ---- ASN.1 Generation ---- */
-
-/* start a tag and return write ptr */
-static uint8_t *asn1_tag(struct asn1 *ctx, uint8_t tag)
-{
-	ctx->p[(ctx->n)++] = tag;
-	return ctx->p + ctx->n;
-}
-
-/* DER encode length and return encoded size thereof */
-static int asn1_len(uint8_t *p, size_t size)
-{
-	if (size < 128) {
-		p[0] = size;
-		return 1;
-	} else if (size < 256) {
-		p[0] = 0x81;
-		p[1] = size;
-		return 2;
-	} else {
-		p[0] = 0x82;
-		p[1] = size >> 8;
-		p[2] = size;
-		return 3;
-	}
-}
-
-/*
- * close sequence and move encapsulated data if needed
- * return total length.
- */
-static size_t asn1_seq(uint8_t *p, uint8_t tag, size_t l, size_t size)
-{
-	size_t tl;
-
-	p[0] = tag;
-	tl = asn1_len(p + 1, size) + 1;
-	/* TODO: tl > l fail */
-	if (tl < l)
-		memmove(p + tl, p + l, size);
-
-	return tl + size;
-}
-
-/* DER encode (small positive) integer */
-static void asn1_int(struct asn1 *ctx, uint32_t val)
-{
-	uint8_t *p = asn1_tag(ctx, V_ASN1_INT);
-
-	if (!val) {
-		*p++ = 1;
-		*p++ = 0;
-	} else {
-		int nbits = 32 - __builtin_clz(val);
-		int nbytes = (nbits + 7) / 8;
-
-		if ((nbits & 7) == 0) {
-			*p++ = nbytes + 1;
-			*p++ = 0;
-		} else {
-			*p++ = nbytes;
-		}
-		while (nbytes--)
-			*p++ = val >> (nbytes * 8);
-	}
-
-	ctx->n = p - ctx->p;
-}
-
-/* DER encode positive p256_int */
-static void asn1_p256_int(struct asn1 *ctx, const p256_int *n)
-{
-	uint8_t *p = asn1_tag(ctx, V_ASN1_INT);
-	uint8_t bn[P256_NBYTES];
-	int i;
-
-	p256_to_bin(n, bn);
-	for (i = 0; i < P256_NBYTES; ++i) {
-		if (bn[i] != 0)
-			break;
-	}
-	if (bn[i] & 0x80) {
-		*p++ = P256_NBYTES - i + 1;
-		*p++ = 0;
-	} else {
-		*p++ = P256_NBYTES - i;
-	}
-	for (; i < P256_NBYTES; ++i)
-		*p++ = bn[i];
-
-	ctx->n = p - ctx->p;
-}
-
-/* DER encode p256 signature */
-static void asn1_sig(struct asn1 *ctx, const p256_int *r, const p256_int *s)
-{
-	SEQ_START(*ctx, V_SEQ, SEQ_SMALL) {
-		asn1_p256_int(ctx, r);
-		asn1_p256_int(ctx, s);
-	}
-	SEQ_END(*ctx);
-}
-
-/* DER encode printable string */
-static void asn1_string(struct asn1 *ctx, uint8_t tag, const char *s)
-{
-	uint8_t *p = asn1_tag(ctx, tag);
-	size_t n = strlen(s);
-
-	p += asn1_len(p, n);
-	while (n--)
-		*p++ = *s++;
-
-	ctx->n = p - ctx->p;
-}
-
-/* DER encode bytes */
-static void asn1_object(struct asn1 *ctx, size_t n, const uint8_t *b)
-{
-	uint8_t *p = asn1_tag(ctx, V_ASN1_OBJ);
-
-	p += asn1_len(p, n);
-	while (n--)
-		*p++ = *b++;
-
-	ctx->n = p - ctx->p;
-}
-
-/* DER encode p256 pk */
-static void asn1_pub(struct asn1 *ctx, const p256_int *x, const p256_int *y)
-{
-	uint8_t *p = asn1_tag(ctx, 4); /* uncompressed format */
-
-	p256_to_bin(x, p); p += P256_NBYTES;
-	p256_to_bin(y, p); p += P256_NBYTES;
-
-	ctx->n = p - ctx->p;
-}
-
-size_t DCRYPTO_asn1_sigp(uint8_t *buf, const p256_int *r, const p256_int *s)
-{
-	struct asn1 asn1 = {buf, 0};
-
-	asn1_sig(&asn1, r, s);
-	return asn1.n;
-}
-
-size_t DCRYPTO_asn1_pubp(uint8_t *buf, const p256_int *x, const p256_int *y)
-{
-	struct asn1 asn1 = {buf, 0};
-
-	asn1_pub(&asn1, x, y);
-	return asn1.n;
-}
-
-/* ---- ASN.1 Parsing ---- */
-
-/*
- * An ASN.1 DER (Definite Encoding Rules) parser.
- * Details about the format are available here:
- *     https://en.wikipedia.org/wiki/X.690#Definite_form
- */
-static size_t asn1_parse(const uint8_t **p, size_t available,
-			uint8_t expected_type, const uint8_t **out,
-			size_t *out_len, size_t *remaining)
-{
-	const size_t tag_len = 1;
-	const uint8_t *in = *p;
-	size_t obj_len = 0;
-	size_t obj_len_bytes;
-	size_t consumed;
-
-	if (available < 2)
-		return 0;
-	if (in[0] != expected_type)  /* in[0] specifies the tag. */
-		return 0;
-
-	if ((in[1] & 128) == 0) {
-		/* Short-length encoding (i.e. obj_len <= 127). */
-		obj_len = in[1];
-		obj_len_bytes = 1;
-	} else {
-		int i;
-
-		obj_len_bytes = 1 + (in[1] & 127);
-		if (obj_len_bytes > MAX_ASN1_OBJ_LEN_BYTES ||
-			tag_len + obj_len_bytes > available)
-			return 0;
-
-		if (in[2] == 0)
-			/* Definite form encoding requires minimal
-			 * length encoding. */
-			return 0;
-		for (i = 0; i < obj_len_bytes - 1; i++) {
-			obj_len <<= 8;
-			obj_len |= in[tag_len + 1 + i];
-		}
-	}
-
-	consumed = tag_len + obj_len_bytes + obj_len;
-	if (consumed > available)
-		return 0;    /* Invalid object length.*/
-	if (out)
-		*out = &in[tag_len + obj_len_bytes];
-	if (out_len)
-		*out_len = obj_len;
-
-	*p = in + consumed;
-	if (remaining)
-		*remaining = available - consumed;
-	return consumed;
-}
-
-static size_t asn1_parse_certificate(const uint8_t **p, size_t *available)
-{
-	size_t consumed;
-	size_t obj_len;
-	const uint8_t *in = *p;
-
-	consumed = asn1_parse(&in, *available,
-			V_ASN1_CONSTRUCTED | V_ASN1_SEQUENCE,
-			NULL, &obj_len, NULL);
-	if (consumed == 0 || consumed != *available)  /* Invalid SEQUENCE. */
-		return 0;
-	*p += consumed - obj_len;
-	*available -= consumed - obj_len;
-	return 1;
-}
-
-static size_t asn1_parse_tbs(const uint8_t **p, size_t *available,
-			size_t *tbs_len)
-{
-	size_t consumed;
-
-	consumed = asn1_parse(p, *available,
-			V_ASN1_CONSTRUCTED | V_ASN1_SEQUENCE,
-			NULL, NULL, available);
-	if (consumed == 0)
-		return 0;
-	*tbs_len = consumed;
-	return 1;
-}
-
-static size_t asn1_parse_signature_algorithm(const uint8_t **p,
-					size_t *available)
-{
-	const uint8_t *alg_oid;
-	size_t alg_oid_len;
-
-	if (!asn1_parse(p, *available, V_ASN1_CONSTRUCTED | V_ASN1_SEQUENCE,
-				&alg_oid, &alg_oid_len, available))
-		return 0;
-	if (alg_oid_len != sizeof(OID_SHA256_WITH_RSA_ENCRYPTION))
-		return 0;
-	if (memcmp(alg_oid, OID_SHA256_WITH_RSA_ENCRYPTION,
-			sizeof(OID_SHA256_WITH_RSA_ENCRYPTION)) != 0)
-		return 0;
-	return 1;
-}
-
-static size_t asn1_parse_signature_value(const uint8_t **p, size_t *available,
-					const uint8_t **sig, size_t *sig_len)
-{
-	if (!asn1_parse(p, *available, V_ASN1_BIT_STRING,
-				sig, sig_len, available))
-		return 0;
-	if (*available != 0)
-		return 0;     /* Not all input bytes consumed. */
-	return 1;
-}
-
-/* This method verifies that the provided X509 certificate was issued
- * by the specified certifcate authority.
- *
- * cert is a pointer to a DER encoded X509 certificate, as specified
- * in https://tools.ietf.org/html/rfc5280#section-4.1.  In ASN.1
- * notation, the certificate has the following structure:
- *
- *   Certificate  ::=  SEQUENCE  {
- *        tbsCertificate       TBSCertificate,
- *        signatureAlgorithm   AlgorithmIdentifier,
- *        signatureValue       BIT STRING  }
- *
- *   TBSCertificate  ::=  SEQUENCE  { }
- *   AlgorithmIdentifier  ::=  SEQUENCE  { }
- *
- * where signatureValue = SIGN(HASH(tbsCertificate)), with SIGN and
- * HASH specified by signatureAlgorithm.
- */
-int DCRYPTO_x509_verify(const uint8_t *cert, size_t len,
-			const struct RSA *ca_pub_key)
-{
-	const uint8_t *p = cert;
-	const uint8_t *tbs;
-	size_t tbs_len;
-	const uint8_t *sig;
-	size_t sig_len;
-
-	uint8_t digest[SHA256_DIGEST_SIZE];
-
-	/* Read Certificate SEQUENCE. */
-	if (!asn1_parse_certificate(&p, &len))
-		return 0;
-
-	/* Read tbsCertificate SEQUENCE. */
-	tbs = p;
-	if (!asn1_parse_tbs(&p, &len, &tbs_len))
-		return 0;
-
-	/* Read signatureAlgorithm SEQUENCE. */
-	if (!asn1_parse_signature_algorithm(&p, &len))
-		return 0;
-
-	/* Read signatureValue BIT STRING. */
-	if (!asn1_parse_signature_value(&p, &len, &sig, &sig_len))
-		return 0;
-
-	/* Check that the signature length corresponds to the issuer's
-	 * public key size. */
-	if (sig_len != bn_size(&ca_pub_key->N) &&
-		sig_len != bn_size(&ca_pub_key->N) + 1)
-		return 0;
-	/* Check that leading signature bytes (if any) are zero. */
-	if (sig_len == bn_size(&ca_pub_key->N) + 1) {
-		if (sig[0] != 0)
-			return 0;
-		sig++;
-		sig_len--;
-	}
-
-	DCRYPTO_SHA256_hash(tbs, tbs_len, digest);
-	return DCRYPTO_rsa_verify(ca_pub_key, digest, sizeof(digest),
-				sig, sig_len, PADDING_MODE_PKCS1, HASH_SHA256);
-}
-
-/* ---- Certificate generation ---- */
-
-static void add_common_name(struct asn1 *ctx, const char *cname)
-{
-	SEQ_START(*ctx, V_SEQ, SEQ_SMALL) {
-		SEQ_START(*ctx, V_SET, SEQ_SMALL) {
-			SEQ_START(*ctx, V_SEQ, SEQ_SMALL) {
-				asn1_object(ctx, OID(commonName));
-				asn1_string(ctx, V_ASN1_ASCII, cname);
-			}
-			SEQ_END(*ctx);
-		}
-		SEQ_END(*ctx);
-	}
-	SEQ_END(*ctx);
-}
-
-int DCRYPTO_x509_gen_u2f_cert_name(const p256_int *d, const p256_int *pk_x,
-				   const p256_int *pk_y, const p256_int *serial,
-				   const char *name, uint8_t *cert, const int n)
-{
-	struct asn1 ctx = {cert, 0};
-	HASH_CTX sha;
-	p256_int h, r, s;
-	struct drbg_ctx drbg;
-
-	SEQ_START(ctx, V_SEQ, SEQ_LARGE) {  /* outer seq */
-	/*
-	 * Grab current pointer to data to hash later.
-	 * Note this will fail if cert body + cert sign is less
-	 * than 256 bytes (SEQ_MEDIUM) -- not likely.
-	 */
-	uint8_t *body = ctx.p + ctx.n;
-
-	/* Cert body seq */
-	SEQ_START(ctx, V_SEQ, SEQ_MEDIUM) {
-		/* X509 v3 */
-		SEQ_START(ctx, 0xa0, SEQ_SMALL) {
-			asn1_int(&ctx, 2);
-		}
-		SEQ_END(ctx);
-
-		/* Serial number */
-		if (serial)
-			asn1_p256_int(&ctx, serial);
-		else
-			asn1_int(&ctx, 1);
-
-		/* Signature algo */
-		SEQ_START(ctx, V_SEQ, SEQ_SMALL) {
-			asn1_object(&ctx, OID(ecdsa_with_SHA256));
-		}
-		SEQ_END(ctx);
-
-		/* Issuer */
-		add_common_name(&ctx, name);
-
-		/* Expiry */
-		SEQ_START(ctx, V_SEQ, SEQ_SMALL) {
-			asn1_string(&ctx, V_ASN1_TIME, "20000101000000Z");
-			asn1_string(&ctx, V_ASN1_TIME, "20991231235959Z");
-		}
-		SEQ_END(ctx);
-
-		/* Subject */
-		add_common_name(&ctx, name);
-
-		/* Subject pk */
-		SEQ_START(ctx, V_SEQ, SEQ_SMALL) {
-			/* pk parameters */
-			SEQ_START(ctx, V_SEQ, SEQ_SMALL) {
-				asn1_object(&ctx, OID(id_ecPublicKey));
-				asn1_object(&ctx, OID(prime256v1));
-			}
-			SEQ_END(ctx);
-			/* pk bits */
-			SEQ_START(ctx, V_BITS, SEQ_SMALL) {
-				/* No unused bit at the end */
-				asn1_tag(&ctx, 0);
-				asn1_pub(&ctx, pk_x, pk_y);
-			}
-			SEQ_END(ctx);
-		}
-		SEQ_END(ctx);
-
-		/* U2F transports indicator extension */
-		SEQ_START(ctx, 0xa3, SEQ_SMALL) {
-			SEQ_START(ctx, V_SEQ, SEQ_SMALL) {
-			SEQ_START(ctx, V_SEQ, SEQ_SMALL) {
-				asn1_object(&ctx, OID(fido_u2f));
-				SEQ_START(ctx, V_ASN1_BYTES, SEQ_SMALL) {
-					SEQ_START(ctx, V_BITS, SEQ_SMALL) {
-						/* 3 zero bits */
-						asn1_tag(&ctx, 3);
-						/* usb-internal transport */
-						asn1_tag(&ctx, 0x08);
-					}
-					SEQ_END(ctx);
-				}
-				SEQ_END(ctx);
-			}
-			SEQ_END(ctx);
-			}
-			SEQ_END(ctx);
-		}
-		SEQ_END(ctx);
-	}
-	SEQ_END(ctx);  /* Cert body */
-
-	/* Sign all of cert body */
-	DCRYPTO_SHA256_init(&sha, 0);
-	HASH_update(&sha, body, (ctx.p + ctx.n) - body);
-	p256_from_bin(HASH_final(&sha), &h);
-	hmac_drbg_init_rfc6979(&drbg, d, &h);
-	if (!dcrypto_p256_ecdsa_sign(&drbg, d, &h, &r, &s))
-		return 0;
-
-	/* Append X509 signature */
-	SEQ_START(ctx, V_SEQ, SEQ_SMALL);
-	asn1_object(&ctx, OID(ecdsa_with_SHA256));
-	SEQ_END(ctx);
-	SEQ_START(ctx, V_BITS, SEQ_SMALL) {
-		/* no unused/zero bit at the end */
-		asn1_tag(&ctx, 0);
-		asn1_sig(&ctx, &r, &s);
-	} SEQ_END(ctx);
-
-	} SEQ_END(ctx); /* end of outer seq */
-
-	return ctx.n;
-}
-
-int DCRYPTO_x509_gen_u2f_cert(const p256_int *d, const p256_int *pk_x,
-			      const p256_int *pk_y, const p256_int *serial,
-			      uint8_t *cert, const int n)
-{
-	return DCRYPTO_x509_gen_u2f_cert_name(d, pk_x, pk_y, serial,
-					      serial ? STRINGIFY(BOARD) : "U2F",
-					      cert, n);
-}
diff --git a/chip/g/flash.c b/chip/g/flash.c
deleted file mode 100644
index 4829c986c8..0000000000
--- a/chip/g/flash.c
+++ /dev/null
@@ -1,629 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * The SoC's internal flash consists of two separate "banks" of 256K bytes each
- * (sometimes called "macros" because of how they're implemented in Verilog).
- *
- * Each flash bank contains 128 "blocks" or "pages" of 2K bytes each. These
- * blocks can be erased individually, or the entire bank can be erased at once.
- *
- * When the flash content is erased, all its bits are set to 1.
- *
- * The flash content can be read directly as bytes, halfwords, or words, just
- * like any memory region. However, writes can only happen through special
- * operations, in units of properly aligned 32-bit words.
- *
- * The flash controller has a 32-word write buffer. This allows up to 32
- * adjacent words (128 bytes) within a bank to be written in one operation.
- *
- * Multiple writes to the same flash word can be done without first erasing the
- * block, however:
- *
- * A) writes can only change stored bits from 1 to 0, and
- *
- * B) the manufacturer recommends that no more than two writes be done between
- *    erase cycles for best results (in terms of reliability, longevity, etc.)
- *
- * All of this is fairly typical of most flash parts. This next thing is NOT
- * typical:
- *
- * +--------------------------------------------------------------------------+
- * + While any write or erase operation is in progress, ALL other access to   +
- * + that entire bank is stalled. Data reads, instruction fetches, interrupt  +
- * + vector lookup -- every access blocks until the flash operation finishes. +
- * +--------------------------------------------------------------------------+
- *
- */
-
-#include "common.h"
-#include "board_id.h"
-#include "console.h"
-#include "cryptoc/util.h"
-#include "extension.h"
-#include "flash.h"
-#include "flash_log.h"
-#include "registers.h"
-#include "shared_mem.h"
-#include "task.h"
-#include "timer.h"
-#include "watchdog.h"
-
-#define CPRINTS(format, args...) cprints(CC_EXTENSION, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_EXTENSION, format, ## args)
-
-/* Mutex to prevent concurrent accesses to flash engine. */
-static struct mutex flash_mtx;
-
-#ifdef CONFIG_FLASH_LOG
-static void flash_log_space_control(int enable)
-{
-	GWRITE_FIELD(GLOBALSEC, FLASH_REGION5_CTRL, WR_EN, !!enable);
-}
-#endif
-
-int flash_pre_init(void)
-{
-	struct g_flash_region regions[4];
-	int i, num_regions;
-
-	num_regions = flash_regions_to_enable(regions, ARRAY_SIZE(regions));
-
-	for (i = 0; i < num_regions; i++) {
-		int reg_base;
-
-		/* Region range */
-		reg_base = GBASE(GLOBALSEC) +
-			GOFFSET(GLOBALSEC, FLASH_REGION2_BASE_ADDR) +
-			i * 8;
-
-		REG32(reg_base) = regions[i].reg_base;
-
-		/*
-		 * The hardware requires a value which is 1 less than the
-		 * actual region size.
-		 */
-		REG32(reg_base + 4) = regions[i].reg_size - 1;
-
-		/* Region permissions. */
-		reg_base = GBASE(GLOBALSEC) +
-			GOFFSET(GLOBALSEC, FLASH_REGION2_CTRL) +
-			i * 4;
-		REG32(reg_base) = regions[i].reg_perms;
-	}
-
-#ifdef CONFIG_FLASH_LOG
-	/*
-	 * Allow access to flash elog space and register the access control
-	 * function.
-	 */
-	GREG32(GLOBALSEC, FLASH_REGION5_BASE_ADDR) = CONFIG_FLASH_LOG_BASE;
-	GREG32(GLOBALSEC, FLASH_REGION5_SIZE) = CONFIG_FLASH_LOG_SPACE - 1;
-	GWRITE_FIELD(GLOBALSEC, FLASH_REGION5_CTRL, EN, 1);
-	GWRITE_FIELD(GLOBALSEC, FLASH_REGION5_CTRL, RD_EN, 1);
-	flash_log_register_flash_control_callback(flash_log_space_control);
-#endif
-
-	/* Create a flash region window for INFO1 access. */
-	GREG32(GLOBALSEC, FLASH_REGION7_BASE_ADDR) = FLASH_INFO_MEMORY_BASE;
-	GREG32(GLOBALSEC, FLASH_REGION7_SIZE) = FLASH_INFO_SIZE - 1;
-	GWRITE_FIELD(GLOBALSEC, FLASH_REGION7_CTRL, EN, 1);
-	GWRITE_FIELD(GLOBALSEC, FLASH_REGION7_CTRL, RD_EN, 1);
-
-	return EC_SUCCESS;
-}
-
-int flash_physical_get_protect(int bank)
-{
-	return 0;				/* Not protected */
-}
-
-uint32_t flash_physical_get_protect_flags(void)
-{
-	return 0;				/* no flags set */
-}
-
-uint32_t flash_physical_get_valid_flags(void)
-{
-	/* These are the flags we're going to pay attention to */
-	return EC_FLASH_PROTECT_RO_AT_BOOT |
-		EC_FLASH_PROTECT_RO_NOW |
-		EC_FLASH_PROTECT_ALL_NOW;
-}
-
-uint32_t flash_physical_get_writable_flags(uint32_t cur_flags)
-{
-	return 0;				/* no flags writable */
-}
-
-int flash_physical_protect_at_boot(uint32_t new_flags)
-{
-	return EC_SUCCESS;			/* yeah, I did it. */
-}
-
-int flash_physical_protect_now(int all)
-{
-	return EC_SUCCESS;			/* yeah, I did it. */
-}
-
-
-enum flash_op {
-	OP_ERASE_BLOCK,
-	OP_WRITE_BLOCK,
-	OP_READ_BLOCK,
-};
-
-static int do_flash_op(enum flash_op op, int is_info_bank,
-		       int byte_offset, int words)
-{
-	volatile uint32_t *fsh_pe_control;
-	uint32_t opcode, tmp, errors;
-	int retry_count, max_attempts, extra_prog_pulse, i;
-	int timedelay_us = 100;
-	uint32_t prev_error = 0;
-
-	/* Make sure the smart program/erase algorithms are enabled. */
-	if (!GREAD(FLASH, FSH_TIMING_PROG_SMART_ALGO_ON) ||
-	    !GREAD(FLASH, FSH_TIMING_ERASE_SMART_ALGO_ON)) {
-		CPRINTF("%s:%d\n", __func__, __LINE__);
-		return EC_ERROR_UNIMPLEMENTED;
-	}
-
-	/* Error status is self-clearing. Read it until it does (we hope). */
-	for (i = 0; i < 50; i++) {
-		tmp = GREAD(FLASH, FSH_ERROR);
-		if (!tmp)
-			break;
-		usleep(timedelay_us);
-	}
-	/* If we can't clear the error status register then something is wrong.
-	 */
-	if (tmp) {
-		CPRINTF("%s:%d\n", __func__, __LINE__);
-		return EC_ERROR_UNKNOWN;
-	}
-
-	/* We have two flash banks. Adjust offset and registers accordingly. */
-	if (is_info_bank) {
-		/* Only INFO bank operations are supported. */
-		fsh_pe_control = GREG32_ADDR(FLASH, FSH_PE_CONTROL1);
-	} else if (byte_offset >= CFG_FLASH_HALF) {
-		byte_offset -= CFG_FLASH_HALF;
-		fsh_pe_control = GREG32_ADDR(FLASH, FSH_PE_CONTROL1);
-	} else {
-		fsh_pe_control = GREG32_ADDR(FLASH, FSH_PE_CONTROL0);
-	}
-
-	/* What are we doing? */
-	switch (op) {
-	case OP_ERASE_BLOCK:
-#ifndef CR50_RELAXED
-		if (is_info_bank)
-			/* Erasing the INFO bank from the RW section is
-			 * unsupported. */
-			return EC_ERROR_INVAL;
-#endif
-		opcode = 0x31415927;
-		words = 0;			/* don't care, really */
-		/* This number is based on the TSMC spec Nme=Terase/Tsme */
-		max_attempts = 45;
-		break;
-	case OP_WRITE_BLOCK:
-		opcode = 0x27182818;
-		words--;		     /* count register is zero-based */
-		/* This number is based on the TSMC spec Nmp=Tprog/Tsmp */
-		max_attempts = 9;
-		break;
-	case OP_READ_BLOCK:
-		if (!is_info_bank)
-			/* This code path only supports reading from
-			 * the INFO bank.
-			 */
-			return EC_ERROR_INVAL;
-		opcode = 0x16021765;
-		words = 1;
-		max_attempts = 9;
-		break;
-	default:
-		return EC_ERROR_INVAL;
-	}
-
-	/*
-	 * Set the parameters. For writes, we assume the write buffer is
-	 * already filled before we call this function.
-	 */
-	GWRITE_FIELD(FLASH, FSH_TRANS, OFFSET,
-		     byte_offset / 4);		  /* word offset */
-	GWRITE_FIELD(FLASH, FSH_TRANS, MAINB, is_info_bank ? 1 : 0);
-	GWRITE_FIELD(FLASH, FSH_TRANS, SIZE, words);
-
-	/* TODO: Make sure this function isn't getting called "too often" in
-	 * between erases.
-	 */
-	extra_prog_pulse = 0;
-	for (retry_count = 0; retry_count < max_attempts; retry_count++) {
-		/* Kick it off */
-		GWRITE(FLASH, FSH_PE_EN, 0xb11924e1);
-		*fsh_pe_control = opcode;
-
-		/* Wait for completion. 150ms should be enough
-		 * (crosbug.com/p/45366).
-		 */
-		for (i = 0; i < 1500; i++) {
-			tmp = *fsh_pe_control;
-			if (!tmp)
-				break;
-			usleep(timedelay_us);
-		}
-
-		/* Timed out waiting for control register to clear */
-		if (tmp) {
-			/* Stop the failed operation. */
-			*fsh_pe_control = 0;
-			CPRINTF("%s:%d\n", __func__, __LINE__);
-			return EC_ERROR_UNKNOWN;
-		}
-		/* Check error status */
-		errors = GREAD(FLASH, FSH_ERROR);
-
-		if (errors && (errors != prev_error)) {
-			prev_error = errors;
-			CPRINTF("%s:%d errors %x fsh_pe_control %pP\n",
-				__func__, __LINE__, errors, fsh_pe_control);
-		}
-		/* Error status is self-clearing. Read it until it does
-		 * (we hope).
-		 */
-		for (i = 0; i < 50; i++) {
-			tmp = GREAD(FLASH, FSH_ERROR);
-			if (!tmp)
-				break;
-			usleep(timedelay_us);
-		}
-		/* If we can't clear the error status register then something
-		 * is wrong.
-		 */
-		if (tmp) {
-			CPRINTF("%s:%d\n", __func__, __LINE__);
-			return EC_ERROR_UNKNOWN;
-		}
-		/* The operation was successful. */
-		if (!errors) {
-			/* From the spec:
-			 * "In addition, one more program pulse is needed after
-			 * program verification is passed."
-			 */
-			if (op == OP_WRITE_BLOCK && !extra_prog_pulse) {
-				extra_prog_pulse = 1;
-				max_attempts++;
-				continue;
-			}
-			return EC_SUCCESS;
-		}
-		/* If there were errors after completion retry. */
-		watchdog_reload();
-	}
-	CPRINTF("%s:%d, retry count %d\n", __func__, __LINE__, retry_count);
-	return EC_ERROR_UNKNOWN;
-}
-
-/* Write up to CONFIG_FLASH_WRITE_IDEAL_SIZE bytes at once */
-static int write_batch(int byte_offset, int is_info_bank,
-		       int words, const uint8_t *data)
-{
-	volatile uint32_t *fsh_wr_data = GREG32_ADDR(FLASH, FSH_WR_DATA0);
-	uint32_t val;
-	int i;
-	int rv;
-
-	mutex_lock(&flash_mtx);
-
-	/* Load the write buffer. */
-	for (i = 0; i < words; i++) {
-		/*
-		 * We have to write 32-bit values, but we can't guarantee
-		 * alignment for the data. We'll just assemble the word
-		 * manually to avoid alignment faults. Note that we're assuming
-		 * little-endian order here.
-		 */
-		val = ((data[3] << 24) | (data[2] << 16) |
-		       (data[1] << 8) | data[0]);
-
-		*fsh_wr_data = val;
-		data += 4;
-		fsh_wr_data++;
-	}
-
-	rv = do_flash_op(OP_WRITE_BLOCK, is_info_bank, byte_offset, words);
-
-	mutex_unlock(&flash_mtx);
-
-	return rv;
-}
-
-static int flash_physical_write_internal(int byte_offset, int is_info_bank,
-				int num_bytes, const char *data)
-{
-	int num, ret;
-
-	/* The offset and size must be a multiple of CONFIG_FLASH_WRITE_SIZE */
-	if (byte_offset % CONFIG_FLASH_WRITE_SIZE ||
-	    num_bytes % CONFIG_FLASH_WRITE_SIZE)
-		return EC_ERROR_INVAL;
-
-	while (num_bytes) {
-		num = MIN(num_bytes, CONFIG_FLASH_WRITE_IDEAL_SIZE);
-		/*
-		 * Make sure that the write operation will not go
-		 * past a CONFIG_FLASH_ROW_SIZE boundary.
-		 */
-		num = MIN(num, CONFIG_FLASH_ROW_SIZE -
-			  byte_offset % CONFIG_FLASH_ROW_SIZE);
-		ret = write_batch(byte_offset,
-				  is_info_bank,
-				  num / 4,	/* word count */
-				  (const uint8_t *)data);
-		if (ret)
-			return ret;
-
-		num_bytes -= num;
-		byte_offset += num;
-		data += num;
-	}
-
-	return EC_SUCCESS;
-}
-
-int flash_physical_write(int byte_offset, int num_bytes, const char *data)
-{
-	return flash_physical_write_internal(byte_offset, 0, num_bytes, data);
-}
-
-int flash_physical_info_read_word(int byte_offset, uint32_t *dst)
-{
-	int ret;
-
-	if (byte_offset % CONFIG_FLASH_WRITE_SIZE)
-		return EC_ERROR_INVAL;
-
-	mutex_lock(&flash_mtx);
-
-	ret = do_flash_op(OP_READ_BLOCK, 1, byte_offset, 1);
-	if (ret == EC_SUCCESS)
-		*dst = GREG32(FLASH, FSH_DOUT_VAL1);
-
-	mutex_unlock(&flash_mtx);
-
-	return ret;
-}
-
-void flash_info_write_enable(void)
-{
-	GWRITE_FIELD(GLOBALSEC, FLASH_REGION7_CTRL, WR_EN, 1);
-}
-
-void flash_info_write_disable(void)
-{
-	GWRITE_FIELD(GLOBALSEC, FLASH_REGION7_CTRL, WR_EN, 0);
-}
-
-int flash_info_physical_write(int byte_offset, int num_bytes, const char *data)
-{
-	if (byte_offset < 0 || num_bytes < 0 ||
-		byte_offset + num_bytes > FLASH_INFO_SIZE ||
-		(byte_offset | num_bytes) & (CONFIG_FLASH_WRITE_SIZE - 1))
-		return EC_ERROR_INVAL;
-
-	return flash_physical_write_internal(byte_offset, 1, num_bytes, data);
-}
-
-int flash_physical_erase(int byte_offset, int num_bytes)
-{
-	int ret;
-
-	/* Offset and size must be a multiple of CONFIG_FLASH_ERASE_SIZE */
-	if (byte_offset % CONFIG_FLASH_ERASE_SIZE ||
-	    num_bytes % CONFIG_FLASH_ERASE_SIZE)
-		return EC_ERROR_INVAL;
-
-	while (num_bytes) {
-
-		mutex_lock(&flash_mtx);
-
-		/* We may be asked to erase multiple banks */
-		ret = do_flash_op(OP_ERASE_BLOCK,
-				  0,              /* not the INFO bank */
-				  byte_offset,
-				  num_bytes / 4); /* word count */
-
-		mutex_unlock(&flash_mtx);
-
-		if (ret) {
-			CPRINTF("Failed to erase block at %x\n", byte_offset);
-			return ret;
-		}
-
-		num_bytes -= CONFIG_FLASH_ERASE_SIZE;
-		byte_offset += CONFIG_FLASH_ERASE_SIZE;
-	}
-
-	return EC_SUCCESS;
-}
-
-
-/* Enable write access to the backup RO section. */
-void flash_open_ro_window(uint32_t offset, size_t size_b)
-{
-	GREG32(GLOBALSEC, FLASH_REGION6_BASE_ADDR) =
-		offset + CONFIG_PROGRAM_MEMORY_BASE;
-	GREG32(GLOBALSEC, FLASH_REGION6_SIZE) = size_b - 1;
-	GWRITE_FIELD(GLOBALSEC, FLASH_REGION6_CTRL, EN, 1);
-	GWRITE_FIELD(GLOBALSEC, FLASH_REGION6_CTRL, RD_EN, 1);
-	GWRITE_FIELD(GLOBALSEC, FLASH_REGION6_CTRL, WR_EN, 1);
-}
-
-#ifdef CR50_DEV
-/*
- * The seed is the first 32 bytes of the manufacture state space. That is all
- * we care about. We can ignore the rest of the manufacture state.
- */
-#define ENDORSEMENT_SEED_SIZE 32
-
-static enum vendor_cmd_rc vc_endorsement_seed(enum vendor_cmd_cc code,
-					      void *buf,
-					      size_t input_size,
-					      size_t *response_size)
-{
-	uint8_t endorsement_seed[ENDORSEMENT_SEED_SIZE];
-	int rv = VENDOR_RC_SUCCESS;
-	int is_erased = 1;
-	int set_seed = input_size == ENDORSEMENT_SEED_SIZE;
-	int i;
-	uint32_t *p;
-	int offset;
-
-	*response_size = 0;
-	if (input_size && !set_seed) {
-		CPRINTS("%s: invalid seed", __func__);
-		return VENDOR_RC_BOGUS_ARGS;
-	}
-
-	/* Read the endorsement key seed. */
-	p = (uint32_t *)endorsement_seed;
-	for (i = 0; i < (ENDORSEMENT_SEED_SIZE / sizeof(*p)); i++) {
-		offset = FLASH_INFO_MANUFACTURE_STATE_OFFSET + i * sizeof(*p);
-		if (flash_physical_info_read_word(offset, p + i) !=
-		    EC_SUCCESS) {
-			CPRINTS("%s: failed read", __func__);
-			return VENDOR_RC_INTERNAL_ERROR;
-		}
-		if (p[i] != 0xffffffff)
-			is_erased = 0;
-	}
-
-	if (set_seed && !is_erased)  {
-		CPRINTS("%s: seed already set!", __func__);
-		return VENDOR_RC_NOT_ALLOWED;
-	}
-
-	if (!input_size) {
-		*response_size = ENDORSEMENT_SEED_SIZE;
-		memcpy(buf, endorsement_seed, *response_size);
-		return VENDOR_RC_SUCCESS;
-	}
-
-	flash_info_write_enable();
-	if (flash_info_physical_write(FLASH_INFO_MANUFACTURE_STATE_OFFSET,
-				      input_size,
-				      (char *)buf) != EC_SUCCESS) {
-		CPRINTS("%s: failed write", __func__);
-		rv = VENDOR_RC_INTERNAL_ERROR;
-	}
-	flash_info_write_disable();
-	return rv;
-}
-DECLARE_VENDOR_COMMAND(VENDOR_CC_ENDORSEMENT_SEED, vc_endorsement_seed);
-#endif
-#ifdef CR50_RELAXED
-static int command_erase_flash_info(int argc, char **argv)
-{
-	int i;
-	int rv;
-	struct info1_layout *info1;
-	uint32_t *p;
-
-	rv = shared_mem_acquire(sizeof(*info1), (char **)&info1);
-	if (rv != EC_SUCCESS) {
-		ccprintf("Failed to allocate memory for info1!\n");
-		return rv;
-	}
-
-	/* Read the entire info1. */
-	p = (uint32_t *)info1;
-	for (i = 0; i < (sizeof(*info1) / sizeof(*p)); i++) {
-		if (flash_physical_info_read_word(i * sizeof(*p), p + i) !=
-		    EC_SUCCESS) {
-			ccprintf("Failed to read word %d!\n", i);
-			goto exit;
-		}
-	}
-
-#ifdef CR50_SQA
-	/*
-	 * SQA images erase INFO1 RW mask, but do not allow erasing board ID.
-	 *
-	 * If compiled with CR50_SQA=1, board ID flags will set to zero, if
-	 * compiled with CR50_SQA=2 or greater, board ID flags can be set to
-	 * an arbitrary value passed in on the command line, but guaranteeing
-	 * not to lock out the currently running image.
-	 */
-	{
-		uint32_t flags = 0;
-#if CR50_SQA > 1
-		if (argc > 1) {
-			char *e;
-
-			flags = strtoi(argv[1], &e, 0);
-			if (*e) {
-				rv = EC_ERROR_PARAM1;
-				goto exit;
-			}
-		}
-#endif
-		if (board_id_is_blank(&info1->board_space.bid)) {
-			ccprintf("BID is erased. Not modifying flags\n");
-		} else {
-			ccprintf("setting BID flags to %x\n", flags);
-			info1->board_space.bid.flags = flags;
-		}
-		if (check_board_id_vs_header(&info1->board_space.bid,
-					     get_current_image_header())) {
-			ccprintf("Flags %x would lock out current image\n",
-				 flags);
-			rv = EC_ERROR_PARAM1;
-			goto exit;
-		}
-	}
-#else  /* CR50_SQA   ^^^^^^ defined    vvvvvvv Not defined. */
-	/*
-	 * This must be CR50_DEV=1 image, just erase the board information
-	 * space.
-	 */
-	memset(&info1->board_space, 0xff, sizeof(info1->board_space));
-#endif /* CR50_SQA Not defined. */
-
-	memset(info1->rw_info_map, 0xff, sizeof(info1->rw_info_map));
-
-	mutex_lock(&flash_mtx);
-
-	flash_info_write_enable();
-
-	rv = do_flash_op(OP_ERASE_BLOCK, 1, 0, 512);
-
-	mutex_unlock(&flash_mtx);
-
-	if (rv != EC_SUCCESS) {
-		ccprintf("Failed to erase info space!\n");
-		goto exit;
-	}
-
-	rv = flash_info_physical_write(0, sizeof(*info1), (char *)info1);
-	if (rv != EC_SUCCESS)
-		ccprintf("Failed write back info1 contents!\n");
-
- exit:
-	flash_info_write_disable();
-	always_memset(info1, 0, sizeof(*info1));
-	shared_mem_release(info1);
-	return rv;
-}
-DECLARE_SAFE_CONSOLE_COMMAND(eraseflashinfo, command_erase_flash_info,
-#if defined(CR50_SQA) && (CR50_SQA > 1)
-			     "[bid flags]",
-			     "Erase INFO1 flash space and set Board ID flags");
-#else
-			     "", "Erase INFO1 flash space");
-#endif
-#endif
diff --git a/chip/g/flash_config.h b/chip/g/flash_config.h
deleted file mode 100644
index 73dd2eec60..0000000000
--- a/chip/g/flash_config.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#ifndef __EC_CHIP_G_FLASH_CONFIG_H
-#define __EC_CHIP_G_FLASH_CONFIG_H
-
-#include "stdint.h"
-
-#define FLASH_INFO_SIZE                      (2 * 1024)
-#define FLASH_INFO_MEMORY_BASE              0x28000
-/* INFO is a 2-KB flash page that consists of four regions.  The
- * first two regions are used by the boot-room and boot-loader
- * respectively.  Manufacture related state is written to the fourth
- * region. */
-#define FLASH_INFO_MANUFACTURE_STATE_OFFSET 0x600
-#define FLASH_INFO_MANUFACTURE_STATE_SIZE   0x200
-
-
-#define FLASH_REGION_EN_ALL (BIT(GC_GLOBALSEC_FLASH_REGION0_CTRL_EN_LSB) |\
-			     BIT(GC_GLOBALSEC_FLASH_REGION0_CTRL_RD_EN_LSB) |\
-			     BIT(GC_GLOBALSEC_FLASH_REGION0_CTRL_WR_EN_LSB))
-
-/*
- * The below structure describes a single flash region (the hardware supports
- * up to eight). The reg_size field is the actual region size, The reg_perms
- * bits are as used in the above macro, allowing to enable the region and its
- * read and write accesses separately.
- */
-struct g_flash_region {
-	uint32_t reg_base;
-	uint32_t reg_size;
-	uint32_t reg_perms;
-};
-
-/*
- * This function is provided by the board layer to describe necessary flash
- * regions' configuration to allow the flash driver to set the regions
- * properly.
- *
- * The function is passed an array of the g_flash_region structures of the
- * max_regions size, it fills as many entries as necessary and returns the
- * number of set up entries.
- */
-int flash_regions_to_enable(struct g_flash_region *regions,
-			    int max_regions);
-
-#endif  /* ! __EC_CHIP_G_FLASH_CONFIG_H */
-
diff --git a/chip/g/flash_info.h b/chip/g/flash_info.h
deleted file mode 100644
index 464eb70dbd..0000000000
--- a/chip/g/flash_info.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#ifndef __EC_CHIP_G_FLASH_INFO_H
-#define __EC_CHIP_G_FLASH_INFO_H
-
-#include <stddef.h>
-
-#include "signed_header.h"
-
-/*
- * Info1 space available to the app firmware is split in four equal size
- * areas, used as follows:
- *
- * Area 0 - RO rollback prevention
- * Area 1 - RW rollback prevention
- * Area 2 - Board specific stuff
- * Area 3 - Crypto scratch
- */
-#define INFO_AREA_SIZE	   (INFO_MAX * 4)
-#define INFO_TOTAL_SIZE	   (INFO_AREA_SIZE * 4)
-
-#define INFO_RO_MAP_OFFSET 0
-#define INFO_RO_MAP_SIZE   INFO_AREA_SIZE
-
-#define INFO_RW_MAP_OFFSET (INFO_RO_MAP_OFFSET + INFO_RO_MAP_SIZE)
-#define INFO_RW_MAP_SIZE   INFO_AREA_SIZE
-
-#define INFO_BOARD_SPACE_OFFSET (INFO_RW_MAP_OFFSET + INFO_RW_MAP_SIZE)
-
-/* This in fact enables both read and write. */
-void flash_info_write_enable(void);
-void flash_info_write_disable(void);
-int flash_info_physical_write(int byte_offset, int num_bytes, const char *data);
-int flash_physical_info_read_word(int byte_offset, uint32_t *dst);
-
-void flash_open_ro_window(uint32_t offset, size_t size_b);
-
-#endif  /* ! __EC_CHIP_G_FLASH_INFO_H */
diff --git a/chip/g/gpio.c b/chip/g/gpio.c
deleted file mode 100644
index f55e0fad35..0000000000
--- a/chip/g/gpio.c
+++ /dev/null
@@ -1,615 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-
-/*
- * The Cr50's ARM core has two GPIO ports of 16 bits each. Each GPIO signal
- * can be routed through a full NxM crossbar to any of a number of external
- * pins. When setting up GPIOs, both the ARM core and the crossbar must be
- * configured correctly. This file is only concerned with the ARM core.
- */
-
-test_mockable int gpio_get_level(enum gpio_signal signal)
-{
-	const struct gpio_info *g = gpio_list + signal;
-	return !!(GR_GPIO_DATAIN(g->port) & g->mask);
-}
-
-static void set_one_gpio_bit(uint32_t port, uint16_t mask, int value)
-{
-	if (!mask)
-		return;
-
-	/* Assumes mask has one and only one bit set */
-	if (mask & 0x00FF)
-		GR_GPIO_MASKLOWBYTE(port, mask) = value ? mask : 0;
-	else
-		GR_GPIO_MASKHIGHBYTE(port, mask >> 8) = value ? mask : 0;
-}
-
-void gpio_set_level(enum gpio_signal signal, int value)
-{
-	const struct gpio_info *g = gpio_list + signal;
-
-	if (g->flags & GPIO_OPEN_DRAIN) {
-		if (value) {
-			GR_GPIO_CLRDOUTEN(g->port) = g->mask;
-			/* Don't ever set ODR output to HIGH. */
-			return;
-		}
-		GR_GPIO_SETDOUTEN(g->port) = g->mask;
-	}
-
-	set_one_gpio_bit(g->port, g->mask, value);
-}
-
-static void configure_wakepin(int bitmask, uint32_t flags)
-{
-	/* not VIOn ! */
-	if (bitmask > GC_PINMUX_EXITEN0_DIOB7_MASK)
-		return;
-
-	if (!(flags & DIO_WAKE_EN0)) {
-		/* Disable the pin */
-		GREG32(PINMUX, EXITEN0) &= ~bitmask;
-		return;
-	}
-
-	/* level (0) or edge sensitive (1) */
-	if (flags & DIO_WAKE_EDGE0)
-		GREG32(PINMUX, EXITEDGE0) |= bitmask;
-	else
-		GREG32(PINMUX, EXITEDGE0) &= ~bitmask;
-
-	/* high/rising (0) or low/falling (1) */
-	if (flags & DIO_WAKE_INV0)
-		GREG32(PINMUX, EXITINV0) |= bitmask;
-	else
-		GREG32(PINMUX, EXITINV0) &= ~bitmask;
-
-	/* Enable the pin */
-	GREG32(PINMUX, EXITEN0) |= bitmask;
-}
-
-int gpio_get_flags_by_mask(uint32_t port, uint32_t mask)
-{
-	uint32_t flags = 0;
-	uint32_t val = 0;
-
-	/* Only one bit must be set. */
-	if ((mask != (mask & -mask)) || (mask == 0))
-		return 0;
-
-	/* Check mode. */
-	/* ARM DDI 0479B: 3.5.2 */
-	val = GR_GPIO_SETDOUTEN(port) & mask;
-	if (val) {
-		flags |= GPIO_OUTPUT;
-		val = GR_GPIO_DOUT(port) & mask;
-		if (val)
-			flags |= GPIO_HIGH;
-		else
-			flags |= GPIO_LOW;
-	} else
-		flags |= GPIO_INPUT;
-
-	return flags;
-}
-
-void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
-{
-	/* Output must be enabled when needed, input is always enabled */
-	if (flags & GPIO_OUTPUT) {
-
-		if (flags & GPIO_LOW)
-			set_one_gpio_bit(port, mask, 0);
-		else if ((flags & GPIO_HIGH) && !(flags & GPIO_OPEN_DRAIN))
-			/* Set to HIGH only if not open drain. */
-			set_one_gpio_bit(port, mask, 1);
-
-		if (!(flags & GPIO_OPEN_DRAIN) || (flags & GPIO_LOW))
-			/*
-			 * Enable output for push-pull (high or low), or
-			 * open-drain low.
-			 */
-			GR_GPIO_SETDOUTEN(port) = mask;
-		else if (flags & GPIO_OPEN_DRAIN)
-			/*
-			 * Disable output for other open-drain cases to get a
-			 * high-Z pin.
-			 */
-			GR_GPIO_CLRDOUTEN(port) = mask;
-	} else {
-		GR_GPIO_CLRDOUTEN(port) = mask;
-	}
-
-	/* Interrupt types */
-	if (flags & GPIO_INT_F_LOW) {
-		GR_GPIO_CLRINTTYPE(port) = mask;
-		GR_GPIO_CLRINTPOL(port) = mask;
-	}
-	if (flags & GPIO_INT_F_HIGH) {
-		GR_GPIO_CLRINTTYPE(port) = mask;
-		GR_GPIO_SETINTPOL(port) = mask;
-	}
-	if (flags & GPIO_INT_F_FALLING) {
-		GR_GPIO_SETINTTYPE(port) = mask;
-		GR_GPIO_CLRINTPOL(port) = mask;
-	}
-	if (flags & GPIO_INT_F_RISING) {
-		GR_GPIO_SETINTTYPE(port) = mask;
-		GR_GPIO_SETINTPOL(port) = mask;
-	}
-	/* No way to trigger on both rising and falling edges, darn it. */
-}
-
-void gpio_set_wakepin(enum gpio_signal signal, uint32_t flags)
-{
-	const struct gpio_info *g = gpio_list + signal;
-	const int gpio_bitnum = GPIO_MASK_TO_NUM(g->mask);
-	const int dio_val = GET_GPIO_SEL_REG(g->port, gpio_bitnum);
-	int dio_mask;
-	int dio_wake_flags;
-
-	/* Can't do anything if the gpio is not connected to a pin */
-	if (!dio_val)
-		return;
-
-	/* Convert the gpio wake flags to the dio wake pin configuration */
-	flags &= GPIO_HIB_WAKE_MASK;
-	switch (flags) {
-	case 0:  /* Disable Wakepin */
-		dio_wake_flags = 0;
-		break;
-	case GPIO_HIB_WAKE_HIGH:
-		dio_wake_flags = DIO_WAKE_HIGH;
-		break;
-	case GPIO_HIB_WAKE_LOW:
-		dio_wake_flags = DIO_WAKE_LOW;
-		break;
-	case GPIO_HIB_WAKE_RISING:
-		dio_wake_flags = DIO_WAKE_RISING;
-		break;
-	case GPIO_HIB_WAKE_FALLING:
-		dio_wake_flags = DIO_WAKE_FALLING;
-		break;
-	default:
-		/* Wake contions cannot be more than one. */
-		return;
-	}
-
-	/*
-	 * GC_PINMUX_{PIN}_SEL values start from 0x1e (DIOM0)
-	 * down to 0x03 (DIOB7). Meanwhile, GC_PINMUX_{wake_cond}_{pin}_MASK
-	 * has BIT(0) for DIOM0 and BIT(27) for DIOB7.
-	 */
-	dio_mask = 1 << (GC_PINMUX_DIOM0_SEL - dio_val);
-	configure_wakepin(dio_mask, dio_wake_flags);
-}
-
-void gpio_set_alternate_function(uint32_t port, uint32_t mask,
-				enum gpio_alternate_func func)
-{
-	/* This HW feature is not present in the Cr50 ARM core */
-}
-
-/*
- * A pinmux_config contains the selector offset and selector value for a
- * particular pinmux entry.
- */
-struct pinmux_config {
-	uint16_t offset;
-	uint16_t value;
-};
-
-#define PINMUX_CONFIG(name) {						\
-		.offset = CONCAT3(GC_PINMUX_, name, _SEL_OFFSET),	\
-		.value  = CONCAT3(GC_PINMUX_, name, _SEL),		\
-	}
-
-/*
- * The pinmux struct contains a full description of the connection of a DIO to
- * a GPIO, an internal peripheral, or as a direct input.  The flag
- * DIO_TO_PERIPHERAL is used to select between the two union entries.  There
- * is no union entry for direct input because it requires no parameters.
- */
-struct pinmux {
-	union {
-		enum gpio_signal     signal;
-		struct pinmux_config peripheral;
-	};
-	struct pinmux_config dio;
-	uint16_t             flags;
-};
-
-/*
- * These macros are used to add flags indicating the type of mapping requested.
- * DIO_TO_PERIPHERAL for FUNC mappings.
- * DIO_ENABLE_DIRECT_INPUT for DIRECT mappings.
- */
-#define FLAGS_FUNC(name) DIO_TO_PERIPHERAL
-#define FLAGS_GPIO(name) 0
-#define FLAGS_DIRECT     DIO_ENABLE_DIRECT_INPUT
-
-/*
- * These macros are used to selectively initialize the anonymous union based
- * on the type of pinmux mapping requested (FUNC, GPIO, or DIRECT).
- */
-#define PINMUX_FUNC(name) .peripheral = PINMUX_CONFIG(name),
-#define PINMUX_GPIO(name) .signal     = CONCAT2(GPIO_, name),
-#define PINMUX_DIRECT
-
-/*
- * Initialize an entry for the pinmux list.  The first parameter can be either
- * FUNC(name) or GPIO(name) depending on the type of mapping required.  The
- * second argument is the DIO name to map to.  And the final argument is the
- * flags set for this mapping, this macro adds the DIO_TO_PERIPHERAL flag for
- * a FUNC mapping.
- */
-#define PINMUX(name, dio_name, dio_flags) {		\
-		PINMUX_##name				\
-		.dio   = PINMUX_CONFIG(DIO##dio_name),	\
-		.flags = dio_flags | FLAGS_##name	\
-	},
-
-static const struct pinmux pinmux_list[] = {
-	#include "gpio.wrap"
-};
-
-/* Return true if DIO should be a digital input */
-static int connect_dio_to_peripheral(struct pinmux const *p)
-{
-	if (p->flags & DIO_OUTPUT)
-		DIO_SEL_REG(p->dio.offset) = p->peripheral.value;
-
-	if (p->flags & DIO_INPUT)
-		DIO_SEL_REG(p->peripheral.offset) = p->dio.value;
-
-	return p->flags & DIO_INPUT;
-}
-
-/* Return true if DIO should be a digital input */
-static int connect_dio_to_gpio(struct pinmux const *p)
-{
-	const struct gpio_info *g = gpio_list + p->signal;
-	int bitnum = GPIO_MASK_TO_NUM(g->mask);
-
-	if ((g->flags & GPIO_OUTPUT) || (p->flags & DIO_OUTPUT))
-		DIO_SEL_REG(p->dio.offset) = GET_GPIO_FUNC(g->port, bitnum);
-
-	if ((g->flags & GPIO_INPUT) || (p->flags & DIO_INPUT))
-		GET_GPIO_SEL_REG(g->port, bitnum) = p->dio.value;
-
-	if (g->flags & GPIO_PULL_UP)
-		REG_WRITE_MLV(DIO_CTL_REG(p->dio.offset),
-			      DIO_CTL_PU_MASK,
-			      DIO_CTL_PU_LSB, 1);
-
-	if (g->flags & GPIO_PULL_DOWN)
-		REG_WRITE_MLV(DIO_CTL_REG(p->dio.offset),
-			      DIO_CTL_PD_MASK,
-			      DIO_CTL_PD_LSB, 1);
-
-	return (g->flags & GPIO_INPUT) || (p->flags & DIO_INPUT);
-}
-
-static void connect_pinmux(struct pinmux const *p)
-{
-	int is_input;
-
-	if (p->flags & DIO_ENABLE_DIRECT_INPUT) {
-		/* We don't have to setup any muxes for directly connected
-		 * pads. The only ones that we are likely to ever care about
-		 * are tied to the SPS and SPI peripherals, and they're all
-		 * inouts, so we can just enable the digital input for them
-		 * regardless. */
-		is_input = 1;
-	} else {
-		/* Pads that must be muxed to specific GPIOs or peripherals may
-		 * or may not be inputs. We'll check those individually. */
-		if (p->flags & DIO_TO_PERIPHERAL)
-			is_input = connect_dio_to_peripheral(p);
-		else
-			is_input = connect_dio_to_gpio(p);
-	}
-
-	/* Configure the DIO pad controls */
-	if (is_input)
-		REG_WRITE_MLV(DIO_CTL_REG(p->dio.offset),
-			      DIO_CTL_IE_MASK,
-			      DIO_CTL_IE_LSB, 1);
-	if (p->flags & DIO_PULL_UP)
-		REG_WRITE_MLV(DIO_CTL_REG(p->dio.offset),
-			      DIO_CTL_PU_MASK,
-			      DIO_CTL_PU_LSB, 1);
-	if (p->flags & DIO_PULL_DOWN)
-		REG_WRITE_MLV(DIO_CTL_REG(p->dio.offset),
-			      DIO_CTL_PD_MASK,
-			      DIO_CTL_PD_LSB, 1);
-
-	/* Enable any wake pins needed to exit low-power modes */
-	if (p->flags & DIO_WAKE_EN0) {
-		/*
-		 * p->dio.offset is the offset of GC_PINMUX_*_SEL register.
-		 * The next GC_PINMUX_*_SEL register is 8 byte away.
-		 */
-		const uint32_t dio_mask = (1 << (p->dio.offset / 8));
-
-		configure_wakepin(dio_mask, p->flags);
-	}
-}
-
-int gpio_enable_interrupt(enum gpio_signal signal)
-{
-	const struct gpio_info *g = gpio_list + signal;
-	GR_GPIO_SETINTEN(g->port) = g->mask;
-	return EC_SUCCESS;
-}
-
-int gpio_disable_interrupt(enum gpio_signal signal)
-{
-	const struct gpio_info *g = gpio_list + signal;
-	GR_GPIO_CLRINTEN(g->port) = g->mask;
-	return EC_SUCCESS;
-}
-
-int gpio_clear_pending_interrupt(enum gpio_signal signal)
-{
-	const struct gpio_info *g = gpio_list + signal;
-	GR_GPIO_CLRINTSTAT(g->port) = g->mask;
-	return EC_SUCCESS;
-}
-
-void gpio_pre_init(void)
-{
-	const struct gpio_info *g = gpio_list;
-
-	int i;
-
-	/* Enable clocks */
-	REG_WRITE_MLV(GR_PMU_PERICLKSET0,
-		      GC_PMU_PERICLKSET0_DGPIO0_CLK_MASK,
-		      GC_PMU_PERICLKSET0_DGPIO0_CLK_LSB, 1);
-	REG_WRITE_MLV(GR_PMU_PERICLKSET0,
-		      GC_PMU_PERICLKSET0_DGPIO1_CLK_MASK,
-		      GC_PMU_PERICLKSET0_DGPIO1_CLK_LSB, 1);
-
-	/* Set up the pinmux */
-	for (i = 0; i < ARRAY_SIZE(pinmux_list); i++)
-		connect_pinmux(pinmux_list + i);
-
-	/* Set up ARM core GPIOs */
-	for (i = 0; i < GPIO_COUNT; i++, g++)
-		if (g->mask && !(g->flags & GPIO_DEFAULT))
-			gpio_set_flags_by_mask(g->port, g->mask, g->flags);
-}
-
-static void gpio_init(void)
-{
-	task_enable_irq(GC_IRQNUM_GPIO0_GPIOCOMBINT);
-	task_enable_irq(GC_IRQNUM_GPIO1_GPIOCOMBINT);
-}
-DECLARE_HOOK(HOOK_INIT, gpio_init, HOOK_PRIO_DEFAULT);
-
-/*****************************************************************************/
-/* Interrupt handler stuff */
-
-static void gpio_invoke_handler(uint32_t port, uint32_t mask)
-{
-	const struct gpio_info *g = gpio_list;
-	int i;
-	for (i = 0; i < GPIO_IH_COUNT; i++, g++)
-		if (port == g->port && (mask & g->mask))
-			gpio_irq_handlers[i](i);
-}
-
-static void gpio_interrupt(int port)
-{
-	int bitnum;
-	uint32_t mask;
-	uint32_t pending = GR_GPIO_CLRINTSTAT(port);
-
-	while (pending) {
-		bitnum = GPIO_MASK_TO_NUM(pending);
-		mask = 1 << bitnum;
-		pending &= ~mask;
-		gpio_invoke_handler(port, mask);
-		GR_GPIO_CLRINTSTAT(port) = mask;
-	}
-}
-
-void _gpio0_interrupt(void)
-{
-	gpio_interrupt(0);
-}
-void _gpio1_interrupt(void)
-{
-	gpio_interrupt(1);
-}
-DECLARE_IRQ(GC_IRQNUM_GPIO0_GPIOCOMBINT, _gpio0_interrupt, 1);
-DECLARE_IRQ(GC_IRQNUM_GPIO1_GPIOCOMBINT, _gpio1_interrupt, 1);
-
-/*
- * The uart, i2c, and spi suffix arrays must match the order of the pinmux
- * select registers in chip/g/hw_regdefs.h. If the order is incorrect, the
- * pinmux command output will be wrong.
- */
-static const char * const uart_str[] = {
-	"0_CTS", "0_RTS", "0_RX", "0_TX",
-	"1_CTS", "1_RTS", "1_RX", "1_TX",
-	"2_CTS", "2_RTS", "2_RX", "2_TX",
-};
-
-static const char * const i2c_str[] = {
-	"0_SCL", "0_SDA",
-	"1_SCL", "1_SDA",
-	"S0_SCL", "S0_SDA",
-};
-
-static const char * const spi_str[] = {
-	"SPICLK", "SPICSB", "SPIMISO", "SPIMOSI",
-};
-
-static void print_periph(int sel)
-{
-	if (sel >= 1 && sel <= 16)
-		ccprintf("GPIO0_GPIO%d", sel - 1);
-	else if (sel >= 17 && sel <= 32)
-		ccprintf("GPIO1_GPIO%d", sel - 17);
-	else if (sel >= 33 && sel <= 38)
-		ccprintf("I2C%s", i2c_str[sel - 33]);
-	else if (sel >= 49 && sel <= 52)
-		ccprintf("SPI1_%s", spi_str[sel - 49]);
-	else if (sel >= 67 && sel <= 78)
-		ccprintf("UART%s", uart_str[sel - 67]);
-	else if (sel)
-		ccprintf("UNDEF");
-}
-
-static void show_pinmux(const char name, int i, int ofs)
-{
-	uint32_t sel = DIO_SEL_REG(i * 8 + ofs);
-	uint32_t ctl = DIO_CTL_REG(i * 8 + ofs);
-	uint32_t bitmask = 1 << (i + ofs / 8);
-	uint32_t edge = GREG32(PINMUX, EXITEDGE0) & bitmask;
-
-	/* skip empty ones (ignoring drive strength bits) */
-	if (!sel && !(ctl & (0xf << 2)) && !(GREG32(PINMUX, EXITEN0) & bitmask))
-		return;
-
-	ccprintf("%08x: DIO%c%-2d  %2d %3s%3s%3s%4s ",
-		 GC_PINMUX_BASE_ADDR + i * 8 + ofs,
-		 name, i, sel,
-		 (ctl & BIT(2)) ? " IN" : "",
-		 (ctl & BIT(3)) ? " PD" : "",
-		 (ctl & BIT(4)) ? " PU" : "",
-		 (ctl & BIT(5)) ? " INV" : "");
-
-	print_periph(sel);
-
-	if (GREG32(PINMUX, EXITEN0) & bitmask) {
-		ccprintf("  WAKE_");
-		if (GREG32(PINMUX, EXITINV0) & bitmask)
-			ccprintf("%s", edge ? "FALLING" : "LOW");
-		else
-			ccprintf("%s", edge ? "RISING" : "HIGH");
-	}
-	ccprintf("\n");
-	cflush();
-}
-
-static void print_dio_str(uint32_t sel)
-{
-	if (sel >= 1 && sel <= 2)
-		ccprintf("  VIO%d\n", 2 - sel);
-	else if (sel >= 3 && sel <= 10)
-		ccprintf("  DIOB%d\n", 10 - sel);
-	else if (sel >= 11 && sel <= 25)
-		ccprintf("  DIOA%d\n", 25 - sel);
-	else if (sel >= 26 && sel <= 30)
-		ccprintf("  DIOM%d\n", 30 - sel);
-	else
-		ccprintf("\n");
-	cflush();
-}
-
-static void show_pinmux_periph(int i)
-{
-	uint32_t ofs = GC_PINMUX_GPIO0_GPIO0_SEL_OFFSET + i * 4;
-	uint32_t sel = DIO_SEL_REG(ofs);
-
-	if (sel == 0)
-		return;
-
-	ccprintf("%08x: ", GC_PINMUX_BASE_ADDR + ofs);
-	print_periph(i + 1);
-
-	ccprintf("\t%2d", sel);
-	print_dio_str(sel);
-}
-
-static int command_pinmux(int argc, char **argv)
-{
-	size_t i;
-
-	const struct {
-		char name;
-		uint8_t count;
-		uint8_t base_offset;
-	} pads[] = {
-		{'M',  5,    0},
-		{'A', 15, 0x28},
-		{'B',  8, 0xa0},
-		{'V',  2, 0xe8},
-	};
-
-	for (i = 0; i < ARRAY_SIZE(pads); i++) {
-		uint8_t j;
-
-		for (j = 0; j < pads[i].count; j++)
-			show_pinmux(pads[i].name, j, pads[i].base_offset);
-	}
-
-	ccprintf("\n");
-
-	/* GPIO & Peripheral sources */
-	for (i = 0; i <= 98; i++)
-		show_pinmux_periph(i);
-
-	ccprintf("\n");
-	return EC_SUCCESS;
-}
-DECLARE_SAFE_CONSOLE_COMMAND(pinmux, command_pinmux,
-			     "",
-			     "Display pinmux info");
-
-static const char * const int_str[] = {
-	"LOW", "FALLING", "HIGH", "RISING",
-};
-
-static void show_gpiocfg(int n)
-{
-	uint32_t din = GR_GPIO_DATAIN(n);
-	uint32_t dout = GR_GPIO_DOUT(n);
-	uint32_t outen = GR_GPIO_SETDOUTEN(n);
-	uint32_t inten = GR_GPIO_SETINTEN(n);
-	uint32_t intpol = GR_GPIO_SETINTPOL(n);
-	uint32_t inttype = GR_GPIO_SETINTTYPE(n);
-	uint32_t mask;
-	int i, j;
-
-	for (i = 0, mask = 0x1; i < 16; i++, mask <<= 1) {
-		/* Skip it unless it's an output or an interrupt */
-		if (!((outen & mask) || (inten & mask)))
-			continue;
-
-		ccprintf("GPIO%d_GPIO%d:\tread %d", n, i, !!(din & mask));
-		if (outen & mask)
-			ccprintf(" drive %d", !!(dout & mask));
-		if (inten & mask) {
-			j = ((intpol & mask) ? 2 : 0) +
-				((inttype & mask) ? 1 : 0);
-			ccprintf(" INT_%s", int_str[j]);
-		}
-		ccprintf("\n");
-	}
-}
-
-static int command_gpiocfg(int argc, char **argv)
-{
-	show_gpiocfg(0);
-	show_gpiocfg(1);
-
-	return EC_SUCCESS;
-}
-DECLARE_SAFE_CONSOLE_COMMAND(gpiocfg, command_gpiocfg,
-			     "",
-			     "Display GPIO configs");
diff --git a/chip/g/hw_regdefs.h b/chip/g/hw_regdefs.h
deleted file mode 100644
index dabf9dfc40..0000000000
--- a/chip/g/hw_regdefs.h
+++ /dev/null
@@ -1,27633 +0,0 @@
-/*
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* This file is autogenerated by the g_regs utility. Do not edit. */
-
-#ifndef __EC_CHIP_G_CR50_FPGA_REGDEFS_H
-#define __EC_CHIP_G_CR50_FPGA_REGDEFS_H
-#define GC___REVA__                              1
-#define GC___REVB__                              2
-#define GC___REVC__                              3
-#define GC___REVD__                              4
-#define GC___REVE__                              5
-#define GC___HAVEN__                             1
-#define GC___MAJOR_REV__                         __REVB__
-#define GC___MINOR_REV__                         1
-#define GC_PINMUX_DIOA0_SEL                      0x19
-#define GC_PINMUX_DIOA1_SEL                      0x18
-#define GC_PINMUX_DIOA2_SEL                      0x17
-#define GC_PINMUX_DIOA3_SEL                      0x16
-#define GC_PINMUX_DIOA4_SEL                      0x15
-#define GC_PINMUX_DIOA5_SEL                      0x14
-#define GC_PINMUX_DIOA6_SEL                      0x13
-#define GC_PINMUX_DIOA7_SEL                      0x12
-#define GC_PINMUX_DIOA8_SEL                      0x11
-#define GC_PINMUX_DIOA9_SEL                      0x10
-#define GC_PINMUX_DIOA10_SEL                     0xf
-#define GC_PINMUX_DIOA11_SEL                     0xe
-#define GC_PINMUX_DIOA12_SEL                     0xd
-#define GC_PINMUX_DIOA13_SEL                     0xc
-#define GC_PINMUX_DIOA14_SEL                     0xb
-#define GC_PINMUX_DIOB0_SEL                      0xa
-#define GC_PINMUX_DIOB1_SEL                      0x9
-#define GC_PINMUX_DIOB2_SEL                      0x8
-#define GC_PINMUX_DIOB3_SEL                      0x7
-#define GC_PINMUX_DIOB4_SEL                      0x6
-#define GC_PINMUX_DIOB5_SEL                      0x5
-#define GC_PINMUX_DIOB6_SEL                      0x4
-#define GC_PINMUX_DIOB7_SEL                      0x3
-#define GC_PINMUX_DIOM0_SEL                      0x1e
-#define GC_PINMUX_DIOM1_SEL                      0x1d
-#define GC_PINMUX_DIOM2_SEL                      0x1c
-#define GC_PINMUX_DIOM3_SEL                      0x1b
-#define GC_PINMUX_DIOM4_SEL                      0x1a
-#define GC_PINMUX_GPIO0_GPIO0_SEL                0x1
-#define GC_PINMUX_GPIO0_GPIO1_SEL                0x2
-#define GC_PINMUX_GPIO0_GPIO2_SEL                0x3
-#define GC_PINMUX_GPIO0_GPIO3_SEL                0x4
-#define GC_PINMUX_GPIO0_GPIO4_SEL                0x5
-#define GC_PINMUX_GPIO0_GPIO5_SEL                0x6
-#define GC_PINMUX_GPIO0_GPIO6_SEL                0x7
-#define GC_PINMUX_GPIO0_GPIO7_SEL                0x8
-#define GC_PINMUX_GPIO0_GPIO8_SEL                0x9
-#define GC_PINMUX_GPIO0_GPIO9_SEL                0xa
-#define GC_PINMUX_GPIO0_GPIO10_SEL               0xb
-#define GC_PINMUX_GPIO0_GPIO11_SEL               0xc
-#define GC_PINMUX_GPIO0_GPIO12_SEL               0xd
-#define GC_PINMUX_GPIO0_GPIO13_SEL               0xe
-#define GC_PINMUX_GPIO0_GPIO14_SEL               0xf
-#define GC_PINMUX_GPIO0_GPIO15_SEL               0x10
-#define GC_PINMUX_GPIO1_GPIO0_SEL                0x11
-#define GC_PINMUX_GPIO1_GPIO1_SEL                0x12
-#define GC_PINMUX_GPIO1_GPIO2_SEL                0x13
-#define GC_PINMUX_GPIO1_GPIO3_SEL                0x14
-#define GC_PINMUX_GPIO1_GPIO4_SEL                0x15
-#define GC_PINMUX_GPIO1_GPIO5_SEL                0x16
-#define GC_PINMUX_GPIO1_GPIO6_SEL                0x17
-#define GC_PINMUX_GPIO1_GPIO7_SEL                0x18
-#define GC_PINMUX_GPIO1_GPIO8_SEL                0x19
-#define GC_PINMUX_GPIO1_GPIO9_SEL                0x1a
-#define GC_PINMUX_GPIO1_GPIO10_SEL               0x1b
-#define GC_PINMUX_GPIO1_GPIO11_SEL               0x1c
-#define GC_PINMUX_GPIO1_GPIO12_SEL               0x1d
-#define GC_PINMUX_GPIO1_GPIO13_SEL               0x1e
-#define GC_PINMUX_GPIO1_GPIO14_SEL               0x1f
-#define GC_PINMUX_GPIO1_GPIO15_SEL               0x20
-#define GC_PINMUX_I2C0_SCL_SEL                   0x21
-#define GC_PINMUX_I2C0_SDA_SEL                   0x22
-#define GC_PINMUX_I2C1_SCL_SEL                   0x23
-#define GC_PINMUX_I2C1_SDA_SEL                   0x24
-#define GC_PINMUX_I2CS0_SCL_SEL                  0x25
-#define GC_PINMUX_I2CS0_SDA_SEL                  0x26
-#define GC_PINMUX_PMU_BROWNOUT_DET_SEL           0x27
-#define GC_PINMUX_PMU_TESTBUS0_SEL               0x28
-#define GC_PINMUX_PMU_TESTBUS1_SEL               0x29
-#define GC_PINMUX_PMU_TESTBUS2_SEL               0x2a
-#define GC_PINMUX_PMU_TESTBUS3_SEL               0x2b
-#define GC_PINMUX_PMU_TESTBUS4_SEL               0x2c
-#define GC_PINMUX_PMU_TESTBUS5_SEL               0x2d
-#define GC_PINMUX_PMU_TESTBUS6_SEL               0x2e
-#define GC_PINMUX_PMU_TESTBUS7_SEL               0x2f
-#define GC_PINMUX_RTC0_RTC_CLK_TEST_SEL          0x30
-#define GC_PINMUX_SPI1_SPICLK_SEL                0x31
-#define GC_PINMUX_SPI1_SPICSB_SEL                0x32
-#define GC_PINMUX_SPI1_SPIMISO_SEL               0x33
-#define GC_PINMUX_SPI1_SPIMOSI_SEL               0x34
-#define GC_PINMUX_SPS0_TESTBUS0_SEL              0x35
-#define GC_PINMUX_SPS0_TESTBUS1_SEL              0x36
-#define GC_PINMUX_SPS0_TESTBUS2_SEL              0x37
-#define GC_PINMUX_SPS0_TESTBUS3_SEL              0x38
-#define GC_PINMUX_SPS0_TESTBUS4_SEL              0x39
-#define GC_PINMUX_SPS0_TESTBUS5_SEL              0x3a
-#define GC_PINMUX_SPS0_TESTBUS6_SEL              0x3b
-#define GC_PINMUX_SPS0_TESTBUS7_SEL              0x3c
-#define GC_PINMUX_TEMP0_TST_ADC_CLK_SEL          0x3d
-#define GC_PINMUX_TEMP0_TST_ADC_HI_SER_SEL       0x3e
-#define GC_PINMUX_TEMP0_TST_ADC_LO_SER_SEL       0x3f
-#define GC_PINMUX_TEMP0_TST_ADC_VLD_SER_SEL      0x40
-#define GC_PINMUX_TRNG0_TRNG_RO_DIV_SEL          0x41
-#define GC_PINMUX_TRNG0_TRNG_RO_REF_DIV_SEL      0x42
-#define GC_PINMUX_UART0_CTS_SEL                  0x43
-#define GC_PINMUX_UART0_RTS_SEL                  0x44
-#define GC_PINMUX_UART0_RX_SEL                   0x45
-#define GC_PINMUX_UART0_TX_SEL                   0x46
-#define GC_PINMUX_UART1_CTS_SEL                  0x47
-#define GC_PINMUX_UART1_RTS_SEL                  0x48
-#define GC_PINMUX_UART1_RX_SEL                   0x49
-#define GC_PINMUX_UART1_TX_SEL                   0x4a
-#define GC_PINMUX_UART2_CTS_SEL                  0x4b
-#define GC_PINMUX_UART2_RTS_SEL                  0x4c
-#define GC_PINMUX_UART2_RX_SEL                   0x4d
-#define GC_PINMUX_UART2_TX_SEL                   0x4e
-#define GC_PINMUX_USB0_EXT_DM_PULLUP_EN_SEL      0x4f
-#define GC_PINMUX_USB0_EXT_DP_RPU1_ENB_SEL       0x50
-#define GC_PINMUX_USB0_EXT_DP_RPU2_ENB_SEL       0x51
-#define GC_PINMUX_USB0_EXT_FS_EDGE_SEL_SEL       0x52
-#define GC_PINMUX_USB0_EXT_RX_DMI_SEL            0x53
-#define GC_PINMUX_USB0_EXT_RX_DPI_SEL            0x54
-#define GC_PINMUX_USB0_EXT_RX_RCV_SEL            0x55
-#define GC_PINMUX_USB0_EXT_SUSPENDB_SEL          0x56
-#define GC_PINMUX_USB0_EXT_TX_DMO_SEL            0x57
-#define GC_PINMUX_USB0_EXT_TX_DPO_SEL            0x58
-#define GC_PINMUX_USB0_EXT_TX_OEB_SEL            0x59
-#define GC_PINMUX_VIO0_SEL                       0x2
-#define GC_PINMUX_VIO1_SEL                       0x1
-#define GC_PINMUX_VOLT0_TST_NEG_GLITCH_DET_SEL   0x5a
-#define GC_PINMUX_VOLT0_TST_POS_GLITCH_DET_SEL   0x5b
-#define GC_PINMUX_XO0_TESTBUS0_SEL               0x5c
-#define GC_PINMUX_XO0_TESTBUS1_SEL               0x5d
-#define GC_PINMUX_XO0_TESTBUS2_SEL               0x5e
-#define GC_PINMUX_XO0_TESTBUS3_SEL               0x5f
-#define GC_PINMUX_XO0_TESTBUS4_SEL               0x60
-#define GC_PINMUX_XO0_TESTBUS5_SEL               0x61
-#define GC_PINMUX_XO0_TESTBUS6_SEL               0x62
-#define GC_PINMUX_XO0_TESTBUS7_SEL               0x63
-#define GC_PINMUX_SEL_COUNT                      129
-#define GC_EXCEPTNUM_RESET                       0x1
-#define GC_EXCEPTNUM_NMI                         0x2
-#define GC_EXCEPTNUM_HARDFAULT                   0x3
-#define GC_EXCEPTNUM_MEMORYMANAGEMENT            0x4
-#define GC_EXCEPTNUM_BUSFAULT                    0x5
-#define GC_EXCEPTNUM_USAGEFAULT                  0x6
-#define GC_EXCEPTNUM_RESERVED7                   0x7
-#define GC_EXCEPTNUM_RESERVED8                   0x8
-#define GC_EXCEPTNUM_RESERVED9                   0x9
-#define GC_EXCEPTNUM_RESERVED10                  0xa
-#define GC_EXCEPTNUM_SVCALL                      0xb
-#define GC_EXCEPTNUM_DEBUGMONITOR                0xc
-#define GC_EXCEPTNUM_RESERVED13                  0xd
-#define GC_EXCEPTNUM_PENDSV                      0xe
-#define GC_EXCEPTNUM_SYSTICK                     0xf
-#define GC_EXCEPTNUM_CRYPTO0_BREAK_INT           0x10
-#define GC_EXCEPTNUM_CRYPTO0_DMEM_PTRS_OVERFLOW_INT 0x11
-#define GC_EXCEPTNUM_CRYPTO0_DONE_WIPE_SECRETS_INT 0x12
-#define GC_EXCEPTNUM_CRYPTO0_DRF_PTRS_OVERFLOW_INT 0x13
-#define GC_EXCEPTNUM_CRYPTO0_HOST_CMD_DONE_INT   0x14
-#define GC_EXCEPTNUM_CRYPTO0_HOST_CMD_RECV_INT   0x15
-#define GC_EXCEPTNUM_CRYPTO0_LOOP_STACK_OVERFLOW_INT 0x16
-#define GC_EXCEPTNUM_CRYPTO0_LOOP_STACK_UNDERFLOW_INT 0x17
-#define GC_EXCEPTNUM_CRYPTO0_MOD_OPERAND_OUT_OF_RANGE_INT 0x18
-#define GC_EXCEPTNUM_CRYPTO0_PC_STACK_OVERFLOW_INT 0x19
-#define GC_EXCEPTNUM_CRYPTO0_PGM_FAULT_INT       0x1a
-#define GC_EXCEPTNUM_CRYPTO0_TRAP_INT            0x1b
-#define GC_EXCEPTNUM_DMA0_INTR_COMPLETE_CHAN_INT 0x1c
-#define GC_EXCEPTNUM_DMA0_INTR_ERROR_CHAN_INT    0x1d
-#define GC_EXCEPTNUM_DMA0_INTR_PROG_CHAN_INT     0x1e
-#define GC_EXCEPTNUM_DMA0_INTR_TIMEOUT_CHAN_INT  0x1f
-#define GC_EXCEPTNUM_FLASH0_EDONEINT             0x20
-#define GC_EXCEPTNUM_FLASH0_PDONEINT             0x21
-#define GC_EXCEPTNUM_GLOBALSEC_CAMO0_BREACH_ALERT_INT 0x22
-#define GC_EXCEPTNUM_GLOBALSEC_CRYPTO0_DMEM_PARITY_ALERT_INT 0x23
-#define GC_EXCEPTNUM_GLOBALSEC_CRYPTO0_DRF_PARITY_ALERT_INT 0x24
-#define GC_EXCEPTNUM_GLOBALSEC_CRYPTO0_IMEM_PARITY_ALERT_INT 0x25
-#define GC_EXCEPTNUM_GLOBALSEC_CRYPTO0_PGM_FAULT_ALERT_INT 0x26
-#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_INT 0x27
-#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_INT 0x28
-#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_INT 0x29
-#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_INT 0x2a
-#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_INT 0x2b
-#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_INT 0x2c
-#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_INT 0x2d
-#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_INT 0x2e
-#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_INT 0x2f
-#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_INT 0x30
-#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_INT 0x31
-#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_INT 0x32
-#define GC_EXCEPTNUM_GLOBALSEC_FUSE0_FUSE_DEFAULTS_ALERT_INT 0x33
-#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_ALERT_GROUPA_INT 0x34
-#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_ALERT_GROUPB_INT 0x35
-#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_ALERT_GROUPC_INT 0x36
-#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_DIFF_FAIL_ALERT_INT 0x37
-#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_FW0_ALERT_INT 0x38
-#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_FW1_ALERT_INT 0x39
-#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_FW2_ALERT_INT 0x3a
-#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_FW3_ALERT_INT 0x3b
-#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_HEARTBEAT_FAIL_ALERT_INT 0x3c
-#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_PROC_OPCODE_HASH_ALERT_INT 0x3d
-#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_INT 0x3e
-#define GC_EXCEPTNUM_GLOBALSEC_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_INT 0x3f
-#define GC_EXCEPTNUM_GLOBALSEC_KEYMGR0_AES_HKEY_ALERT_INT 0x40
-#define GC_EXCEPTNUM_GLOBALSEC_KEYMGR0_CERT_LOOKUP_ALERT_INT 0x41
-#define GC_EXCEPTNUM_GLOBALSEC_KEYMGR0_FLASH_ENTRY_ALERT_INT 0x42
-#define GC_EXCEPTNUM_GLOBALSEC_KEYMGR0_PW_ALERT_INT 0x43
-#define GC_EXCEPTNUM_GLOBALSEC_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_INT 0x44
-#define GC_EXCEPTNUM_GLOBALSEC_KEYMGR0_SHA_FAULT_ALERT_INT 0x45
-#define GC_EXCEPTNUM_GLOBALSEC_KEYMGR0_SHA_HKEY_ALERT_INT 0x46
-#define GC_EXCEPTNUM_GLOBALSEC_PMU_BATTERY_MON_ALERT_INT 0x47
-#define GC_EXCEPTNUM_GLOBALSEC_PMU_PMU_WDOG_ALERT_INT 0x48
-#define GC_EXCEPTNUM_GLOBALSEC_RTC0_RTC_DEAD_ALERT_INT 0x49
-#define GC_EXCEPTNUM_GLOBALSEC_TEMP0_MAX_TEMP_ALERT_INT 0x4a
-#define GC_EXCEPTNUM_GLOBALSEC_TEMP0_MAX_TEMP_DIFF_ALERT_INT 0x4b
-#define GC_EXCEPTNUM_GLOBALSEC_TEMP0_MIN_TEMP_ALERT_INT 0x4c
-#define GC_EXCEPTNUM_GLOBALSEC_TRNG0_OUT_OF_SPEC_ALERT_INT 0x4d
-#define GC_EXCEPTNUM_GLOBALSEC_TRNG0_TIMEOUT_ALERT_INT 0x4e
-#define GC_EXCEPTNUM_GLOBALSEC_VOLT0_VOLT_ERR_ALERT_INT 0x4f
-#define GC_EXCEPTNUM_GLOBALSEC_XO0_JITTERY_TRIM_DIS_ALERT_INT 0x50
-#define GC_EXCEPTNUM_GPIO0_GPIO0INT              0x51
-#define GC_EXCEPTNUM_GPIO0_GPIO1INT              0x52
-#define GC_EXCEPTNUM_GPIO0_GPIO2INT              0x53
-#define GC_EXCEPTNUM_GPIO0_GPIO3INT              0x54
-#define GC_EXCEPTNUM_GPIO0_GPIO4INT              0x55
-#define GC_EXCEPTNUM_GPIO0_GPIO5INT              0x56
-#define GC_EXCEPTNUM_GPIO0_GPIO6INT              0x57
-#define GC_EXCEPTNUM_GPIO0_GPIO7INT              0x58
-#define GC_EXCEPTNUM_GPIO0_GPIO8INT              0x59
-#define GC_EXCEPTNUM_GPIO0_GPIO9INT              0x5a
-#define GC_EXCEPTNUM_GPIO0_GPIO10INT             0x5b
-#define GC_EXCEPTNUM_GPIO0_GPIO11INT             0x5c
-#define GC_EXCEPTNUM_GPIO0_GPIO12INT             0x5d
-#define GC_EXCEPTNUM_GPIO0_GPIO13INT             0x5e
-#define GC_EXCEPTNUM_GPIO0_GPIO14INT             0x5f
-#define GC_EXCEPTNUM_GPIO0_GPIO15INT             0x60
-#define GC_EXCEPTNUM_GPIO0_GPIOCOMBINT           0x61
-#define GC_EXCEPTNUM_GPIO1_GPIO0INT              0x62
-#define GC_EXCEPTNUM_GPIO1_GPIO1INT              0x63
-#define GC_EXCEPTNUM_GPIO1_GPIO2INT              0x64
-#define GC_EXCEPTNUM_GPIO1_GPIO3INT              0x65
-#define GC_EXCEPTNUM_GPIO1_GPIO4INT              0x66
-#define GC_EXCEPTNUM_GPIO1_GPIO5INT              0x67
-#define GC_EXCEPTNUM_GPIO1_GPIO6INT              0x68
-#define GC_EXCEPTNUM_GPIO1_GPIO7INT              0x69
-#define GC_EXCEPTNUM_GPIO1_GPIO8INT              0x6a
-#define GC_EXCEPTNUM_GPIO1_GPIO9INT              0x6b
-#define GC_EXCEPTNUM_GPIO1_GPIO10INT             0x6c
-#define GC_EXCEPTNUM_GPIO1_GPIO11INT             0x6d
-#define GC_EXCEPTNUM_GPIO1_GPIO12INT             0x6e
-#define GC_EXCEPTNUM_GPIO1_GPIO13INT             0x6f
-#define GC_EXCEPTNUM_GPIO1_GPIO14INT             0x70
-#define GC_EXCEPTNUM_GPIO1_GPIO15INT             0x71
-#define GC_EXCEPTNUM_GPIO1_GPIOCOMBINT           0x72
-#define GC_EXCEPTNUM_I2C0_I2CINT                 0x73
-#define GC_EXCEPTNUM_I2C1_I2CINT                 0x74
-#define GC_EXCEPTNUM_I2CS0_INTR_READ_BEGIN_INT   0x75
-#define GC_EXCEPTNUM_I2CS0_INTR_READ_COMPLETE_INT 0x76
-#define GC_EXCEPTNUM_I2CS0_INTR_WRITE_COMPLETE_INT 0x77
-#define GC_EXCEPTNUM_KEYMGR0_AES_DONE_CIPHER_INT 0x78
-#define GC_EXCEPTNUM_KEYMGR0_AES_DONE_KEYEXPANSION_INT 0x79
-#define GC_EXCEPTNUM_KEYMGR0_AES_DONE_WIPE_SECRETS_INT 0x7a
-#define GC_EXCEPTNUM_KEYMGR0_AES_RFIFO_OVERFLOW_INT 0x7b
-#define GC_EXCEPTNUM_KEYMGR0_AES_RFIFO_UNDERFLOW_INT 0x7c
-#define GC_EXCEPTNUM_KEYMGR0_AES_WFIFO_OVERFLOW_INT 0x7d
-#define GC_EXCEPTNUM_KEYMGR0_DSHA_INT            0x7e
-#define GC_EXCEPTNUM_KEYMGR0_SHA_WFIFO_FULL_INT  0x7f
-#define GC_EXCEPTNUM_PMU_INTR_WAKEUP_INT         0x80
-#define GC_EXCEPTNUM_RBOX0_INTR_AC_PRESENT_FED_INT 0x81
-#define GC_EXCEPTNUM_RBOX0_INTR_AC_PRESENT_RED_INT 0x82
-#define GC_EXCEPTNUM_RBOX0_INTR_BUTTON_COMBO0_RDY_INT 0x83
-#define GC_EXCEPTNUM_RBOX0_INTR_BUTTON_COMBO1_RDY_INT 0x84
-#define GC_EXCEPTNUM_RBOX0_INTR_BUTTON_COMBO2_RDY_INT 0x85
-#define GC_EXCEPTNUM_RBOX0_INTR_EC_RST_FED_INT   0x86
-#define GC_EXCEPTNUM_RBOX0_INTR_EC_RST_RED_INT   0x87
-#define GC_EXCEPTNUM_RBOX0_INTR_KEY0_IN_FED_INT  0x88
-#define GC_EXCEPTNUM_RBOX0_INTR_KEY0_IN_RED_INT  0x89
-#define GC_EXCEPTNUM_RBOX0_INTR_KEY1_IN_FED_INT  0x8a
-#define GC_EXCEPTNUM_RBOX0_INTR_KEY1_IN_RED_INT  0x8b
-#define GC_EXCEPTNUM_RBOX0_INTR_PWRB_IN_FED_INT  0x8c
-#define GC_EXCEPTNUM_RBOX0_INTR_PWRB_IN_RED_INT  0x8d
-#define GC_EXCEPTNUM_RDD0_INTR_DEBUG_STATE_DETECTED_INT 0x8e
-#define GC_EXCEPTNUM_SPI0_SPITXINT               0x8f
-#define GC_EXCEPTNUM_SPI1_SPITXINT               0x90
-#define GC_EXCEPTNUM_SPS0_CS_ASSERT_INTR         0x91
-#define GC_EXCEPTNUM_SPS0_CS_DEASSERT_INTR       0x92
-#define GC_EXCEPTNUM_SPS0_INTR_CMD_ADDR_FIFO_NOT_EMPTY_INT 0x93
-#define GC_EXCEPTNUM_SPS0_INTR_CMD_ADDR_FIFO_OVFL_INT 0x94
-#define GC_EXCEPTNUM_SPS0_INTR_CMD_MEM_OVFL_INT  0x95
-#define GC_EXCEPTNUM_SPS0_INTR_RAM_PAGE0_LVL_INT 0x96
-#define GC_EXCEPTNUM_SPS0_INTR_RAM_PAGE1_LVL_INT 0x97
-#define GC_EXCEPTNUM_SPS0_INTR_RAM_PAGE2_LVL_INT 0x98
-#define GC_EXCEPTNUM_SPS0_INTR_RAM_PAGE3_LVL_INT 0x99
-#define GC_EXCEPTNUM_SPS0_RXFIFO_LVL_INTR        0x9a
-#define GC_EXCEPTNUM_SPS0_RXFIFO_OVERFLOW_INTR   0x9b
-#define GC_EXCEPTNUM_SPS0_SPSCTRLINT0            0x9c
-#define GC_EXCEPTNUM_SPS0_SPSCTRLINT1            0x9d
-#define GC_EXCEPTNUM_SPS0_SPSCTRLINT2            0x9e
-#define GC_EXCEPTNUM_SPS0_SPSCTRLINT3            0x9f
-#define GC_EXCEPTNUM_SPS0_SPSCTRLINT4            0xa0
-#define GC_EXCEPTNUM_SPS0_SPSCTRLINT5            0xa1
-#define GC_EXCEPTNUM_SPS0_SPSCTRLINT6            0xa2
-#define GC_EXCEPTNUM_SPS0_SPSCTRLINT7            0xa3
-#define GC_EXCEPTNUM_SPS0_TXFIFO_EMPTY_INTR      0xa4
-#define GC_EXCEPTNUM_SPS0_TXFIFO_FULL_INTR       0xa5
-#define GC_EXCEPTNUM_SPS0_TXFIFO_LVL_INTR        0xa6
-#define GC_EXCEPTNUM_TEMP0_ADC_ICLKDV_INT        0xa7
-#define GC_EXCEPTNUM_TEMP0_COMP_OVERFLOW_INT     0xa8
-#define GC_EXCEPTNUM_TIMEHS0_TIMINT1             0xa9
-#define GC_EXCEPTNUM_TIMEHS0_TIMINT2             0xaa
-#define GC_EXCEPTNUM_TIMEHS0_TIMINTC             0xab
-#define GC_EXCEPTNUM_TIMEHS1_TIMINT1             0xac
-#define GC_EXCEPTNUM_TIMEHS1_TIMINT2             0xad
-#define GC_EXCEPTNUM_TIMEHS1_TIMINTC             0xae
-#define GC_EXCEPTNUM_TIMELS0_TIMINT0             0xaf
-#define GC_EXCEPTNUM_TIMELS0_TIMINT1             0xb0
-#define GC_EXCEPTNUM_TIMEUS0_INTR_MAX_COUNT_HIT0_INT 0xb1
-#define GC_EXCEPTNUM_TIMEUS0_INTR_MAX_COUNT_HIT1_INT 0xb2
-#define GC_EXCEPTNUM_TIMEUS0_INTR_MAX_COUNT_HIT2_INT 0xb3
-#define GC_EXCEPTNUM_TIMEUS0_INTR_MAX_COUNT_HIT3_INT 0xb4
-#define GC_EXCEPTNUM_TIMEUS0_INTR_PROG_COUNT_HIT0_INT 0xb5
-#define GC_EXCEPTNUM_TIMEUS0_INTR_PROG_COUNT_HIT1_INT 0xb6
-#define GC_EXCEPTNUM_TIMEUS0_INTR_PROG_COUNT_HIT2_INT 0xb7
-#define GC_EXCEPTNUM_TIMEUS0_INTR_PROG_COUNT_HIT3_INT 0xb8
-#define GC_EXCEPTNUM_TRNG0_INTR_BUFFER_FULL_INT  0xb9
-#define GC_EXCEPTNUM_TRNG0_INTR_ONE_SHOT_DONE_INT 0xba
-#define GC_EXCEPTNUM_TRNG0_INTR_READ_EMPTY_INT   0xbb
-#define GC_EXCEPTNUM_UART0_RXBINT                0xbc
-#define GC_EXCEPTNUM_UART0_RXFINT                0xbd
-#define GC_EXCEPTNUM_UART0_RXINT                 0xbe
-#define GC_EXCEPTNUM_UART0_RXOVINT               0xbf
-#define GC_EXCEPTNUM_UART0_RXTOINT               0xc0
-#define GC_EXCEPTNUM_UART0_TXINT                 0xc1
-#define GC_EXCEPTNUM_UART0_TXOVINT               0xc2
-#define GC_EXCEPTNUM_UART1_RXBINT                0xc3
-#define GC_EXCEPTNUM_UART1_RXFINT                0xc4
-#define GC_EXCEPTNUM_UART1_RXINT                 0xc5
-#define GC_EXCEPTNUM_UART1_RXOVINT               0xc6
-#define GC_EXCEPTNUM_UART1_RXTOINT               0xc7
-#define GC_EXCEPTNUM_UART1_TXINT                 0xc8
-#define GC_EXCEPTNUM_UART1_TXOVINT               0xc9
-#define GC_EXCEPTNUM_UART2_RXBINT                0xca
-#define GC_EXCEPTNUM_UART2_RXFINT                0xcb
-#define GC_EXCEPTNUM_UART2_RXINT                 0xcc
-#define GC_EXCEPTNUM_UART2_RXOVINT               0xcd
-#define GC_EXCEPTNUM_UART2_RXTOINT               0xce
-#define GC_EXCEPTNUM_UART2_TXINT                 0xcf
-#define GC_EXCEPTNUM_UART2_TXOVINT               0xd0
-#define GC_EXCEPTNUM_USB0_USBINTR                0xd1
-#define GC_EXCEPTNUM_WATCHDOG0_WDOGINT           0xd2
-#define GC_EXCEPTNUM_XO0_CLK_JTR_NOP_SEEN_INT    0xd3
-#define GC_EXCEPTNUM_XO0_CLK_JTR_SW_TRIM_DONE_INT 0xd4
-#define GC_EXCEPTNUM_XO0_CLK_TIMER_NOP_SEEN_INT  0xd5
-#define GC_EXCEPTNUM_XO0_CLK_TIMER_SW_TRIM_DONE_INT 0xd6
-#define GC_EXCEPTNUM_XO0_FAST_CALIB_OVERFLOW_INT 0xd7
-#define GC_EXCEPTNUM_XO0_FAST_CALIB_UNDERRUN_INT 0xd8
-#define GC_EXCEPTNUM_XO0_SLOW_CALIB_OVERFLOW_INT 0xd9
-#define GC_EXCEPTNUM_XO0_SLOW_CALIB_UNDERRUN_INT 0xda
-#define GC_EXCEPTIONS_COUNT                      218
-#define GC_IRQNUM_RESET                          0
-#define GC_IRQNUM_NMI                            0
-#define GC_IRQNUM_HARDFAULT                      0
-#define GC_IRQNUM_MEMORYMANAGEMENT               0
-#define GC_IRQNUM_BUSFAULT                       0
-#define GC_IRQNUM_USAGEFAULT                     0
-#define GC_IRQNUM_RESERVED7                      0
-#define GC_IRQNUM_RESERVED8                      0
-#define GC_IRQNUM_RESERVED9                      0
-#define GC_IRQNUM_RESERVED10                     0
-#define GC_IRQNUM_SVCALL                         0
-#define GC_IRQNUM_DEBUGMONITOR                   0
-#define GC_IRQNUM_RESERVED13                     0
-#define GC_IRQNUM_PENDSV                         0
-#define GC_IRQNUM_SYSTICK                        0
-#define GC_IRQNUM_CRYPTO0_BREAK_INT              0
-#define GC_IRQNUM_CRYPTO0_DMEM_PTRS_OVERFLOW_INT 1
-#define GC_IRQNUM_CRYPTO0_DONE_WIPE_SECRETS_INT  2
-#define GC_IRQNUM_CRYPTO0_DRF_PTRS_OVERFLOW_INT  3
-#define GC_IRQNUM_CRYPTO0_HOST_CMD_DONE_INT      4
-#define GC_IRQNUM_CRYPTO0_HOST_CMD_RECV_INT      5
-#define GC_IRQNUM_CRYPTO0_LOOP_STACK_OVERFLOW_INT 6
-#define GC_IRQNUM_CRYPTO0_LOOP_STACK_UNDERFLOW_INT 7
-#define GC_IRQNUM_CRYPTO0_MOD_OPERAND_OUT_OF_RANGE_INT 8
-#define GC_IRQNUM_CRYPTO0_PC_STACK_OVERFLOW_INT  9
-#define GC_IRQNUM_CRYPTO0_PGM_FAULT_INT          10
-#define GC_IRQNUM_CRYPTO0_TRAP_INT               11
-#define GC_IRQNUM_DMA0_INTR_COMPLETE_CHAN_INT    12
-#define GC_IRQNUM_DMA0_INTR_ERROR_CHAN_INT       13
-#define GC_IRQNUM_DMA0_INTR_PROG_CHAN_INT        14
-#define GC_IRQNUM_DMA0_INTR_TIMEOUT_CHAN_INT     15
-#define GC_IRQNUM_FLASH0_EDONEINT                16
-#define GC_IRQNUM_FLASH0_PDONEINT                17
-#define GC_IRQNUM_GLOBALSEC_CAMO0_BREACH_ALERT_INT 18
-#define GC_IRQNUM_GLOBALSEC_CRYPTO0_DMEM_PARITY_ALERT_INT 19
-#define GC_IRQNUM_GLOBALSEC_CRYPTO0_DRF_PARITY_ALERT_INT 20
-#define GC_IRQNUM_GLOBALSEC_CRYPTO0_IMEM_PARITY_ALERT_INT 21
-#define GC_IRQNUM_GLOBALSEC_CRYPTO0_PGM_FAULT_ALERT_INT 22
-#define GC_IRQNUM_GLOBALSEC_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_INT 23
-#define GC_IRQNUM_GLOBALSEC_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_INT 24
-#define GC_IRQNUM_GLOBALSEC_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_INT 25
-#define GC_IRQNUM_GLOBALSEC_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_INT 26
-#define GC_IRQNUM_GLOBALSEC_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_INT 27
-#define GC_IRQNUM_GLOBALSEC_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_INT 28
-#define GC_IRQNUM_GLOBALSEC_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_INT 29
-#define GC_IRQNUM_GLOBALSEC_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_INT 30
-#define GC_IRQNUM_GLOBALSEC_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_INT 31
-#define GC_IRQNUM_GLOBALSEC_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_INT 32
-#define GC_IRQNUM_GLOBALSEC_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_INT 33
-#define GC_IRQNUM_GLOBALSEC_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_INT 34
-#define GC_IRQNUM_GLOBALSEC_FUSE0_FUSE_DEFAULTS_ALERT_INT 35
-#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_ALERT_GROUPA_INT 36
-#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_ALERT_GROUPB_INT 37
-#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_ALERT_GROUPC_INT 38
-#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_DIFF_FAIL_ALERT_INT 39
-#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_FW0_ALERT_INT 40
-#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_FW1_ALERT_INT 41
-#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_FW2_ALERT_INT 42
-#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_FW3_ALERT_INT 43
-#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_HEARTBEAT_FAIL_ALERT_INT 44
-#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_PROC_OPCODE_HASH_ALERT_INT 45
-#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_INT 46
-#define GC_IRQNUM_GLOBALSEC_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_INT 47
-#define GC_IRQNUM_GLOBALSEC_KEYMGR0_AES_HKEY_ALERT_INT 48
-#define GC_IRQNUM_GLOBALSEC_KEYMGR0_CERT_LOOKUP_ALERT_INT 49
-#define GC_IRQNUM_GLOBALSEC_KEYMGR0_FLASH_ENTRY_ALERT_INT 50
-#define GC_IRQNUM_GLOBALSEC_KEYMGR0_PW_ALERT_INT 51
-#define GC_IRQNUM_GLOBALSEC_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_INT 52
-#define GC_IRQNUM_GLOBALSEC_KEYMGR0_SHA_FAULT_ALERT_INT 53
-#define GC_IRQNUM_GLOBALSEC_KEYMGR0_SHA_HKEY_ALERT_INT 54
-#define GC_IRQNUM_GLOBALSEC_PMU_BATTERY_MON_ALERT_INT 55
-#define GC_IRQNUM_GLOBALSEC_PMU_PMU_WDOG_ALERT_INT 56
-#define GC_IRQNUM_GLOBALSEC_RTC0_RTC_DEAD_ALERT_INT 57
-#define GC_IRQNUM_GLOBALSEC_TEMP0_MAX_TEMP_ALERT_INT 58
-#define GC_IRQNUM_GLOBALSEC_TEMP0_MAX_TEMP_DIFF_ALERT_INT 59
-#define GC_IRQNUM_GLOBALSEC_TEMP0_MIN_TEMP_ALERT_INT 60
-#define GC_IRQNUM_GLOBALSEC_TRNG0_OUT_OF_SPEC_ALERT_INT 61
-#define GC_IRQNUM_GLOBALSEC_TRNG0_TIMEOUT_ALERT_INT 62
-#define GC_IRQNUM_GLOBALSEC_VOLT0_VOLT_ERR_ALERT_INT 63
-#define GC_IRQNUM_GLOBALSEC_XO0_JITTERY_TRIM_DIS_ALERT_INT 64
-#define GC_IRQNUM_GPIO0_GPIO0INT                 65
-#define GC_IRQNUM_GPIO0_GPIO1INT                 66
-#define GC_IRQNUM_GPIO0_GPIO2INT                 67
-#define GC_IRQNUM_GPIO0_GPIO3INT                 68
-#define GC_IRQNUM_GPIO0_GPIO4INT                 69
-#define GC_IRQNUM_GPIO0_GPIO5INT                 70
-#define GC_IRQNUM_GPIO0_GPIO6INT                 71
-#define GC_IRQNUM_GPIO0_GPIO7INT                 72
-#define GC_IRQNUM_GPIO0_GPIO8INT                 73
-#define GC_IRQNUM_GPIO0_GPIO9INT                 74
-#define GC_IRQNUM_GPIO0_GPIO10INT                75
-#define GC_IRQNUM_GPIO0_GPIO11INT                76
-#define GC_IRQNUM_GPIO0_GPIO12INT                77
-#define GC_IRQNUM_GPIO0_GPIO13INT                78
-#define GC_IRQNUM_GPIO0_GPIO14INT                79
-#define GC_IRQNUM_GPIO0_GPIO15INT                80
-#define GC_IRQNUM_GPIO0_GPIOCOMBINT              81
-#define GC_IRQNUM_GPIO1_GPIO0INT                 82
-#define GC_IRQNUM_GPIO1_GPIO1INT                 83
-#define GC_IRQNUM_GPIO1_GPIO2INT                 84
-#define GC_IRQNUM_GPIO1_GPIO3INT                 85
-#define GC_IRQNUM_GPIO1_GPIO4INT                 86
-#define GC_IRQNUM_GPIO1_GPIO5INT                 87
-#define GC_IRQNUM_GPIO1_GPIO6INT                 88
-#define GC_IRQNUM_GPIO1_GPIO7INT                 89
-#define GC_IRQNUM_GPIO1_GPIO8INT                 90
-#define GC_IRQNUM_GPIO1_GPIO9INT                 91
-#define GC_IRQNUM_GPIO1_GPIO10INT                92
-#define GC_IRQNUM_GPIO1_GPIO11INT                93
-#define GC_IRQNUM_GPIO1_GPIO12INT                94
-#define GC_IRQNUM_GPIO1_GPIO13INT                95
-#define GC_IRQNUM_GPIO1_GPIO14INT                96
-#define GC_IRQNUM_GPIO1_GPIO15INT                97
-#define GC_IRQNUM_GPIO1_GPIOCOMBINT              98
-#define GC_IRQNUM_I2C0_I2CINT                    99
-#define GC_IRQNUM_I2C1_I2CINT                    100
-#define GC_IRQNUM_I2CS0_INTR_READ_BEGIN_INT      101
-#define GC_IRQNUM_I2CS0_INTR_READ_COMPLETE_INT   102
-#define GC_IRQNUM_I2CS0_INTR_WRITE_COMPLETE_INT  103
-#define GC_IRQNUM_KEYMGR0_AES_DONE_CIPHER_INT    104
-#define GC_IRQNUM_KEYMGR0_AES_DONE_KEYEXPANSION_INT 105
-#define GC_IRQNUM_KEYMGR0_AES_DONE_WIPE_SECRETS_INT 106
-#define GC_IRQNUM_KEYMGR0_AES_RFIFO_OVERFLOW_INT 107
-#define GC_IRQNUM_KEYMGR0_AES_RFIFO_UNDERFLOW_INT 108
-#define GC_IRQNUM_KEYMGR0_AES_WFIFO_OVERFLOW_INT 109
-#define GC_IRQNUM_KEYMGR0_DSHA_INT               110
-#define GC_IRQNUM_KEYMGR0_SHA_WFIFO_FULL_INT     111
-#define GC_IRQNUM_PMU_INTR_WAKEUP_INT            112
-#define GC_IRQNUM_RBOX0_INTR_AC_PRESENT_FED_INT  113
-#define GC_IRQNUM_RBOX0_INTR_AC_PRESENT_RED_INT  114
-#define GC_IRQNUM_RBOX0_INTR_BUTTON_COMBO0_RDY_INT 115
-#define GC_IRQNUM_RBOX0_INTR_BUTTON_COMBO1_RDY_INT 116
-#define GC_IRQNUM_RBOX0_INTR_BUTTON_COMBO2_RDY_INT 117
-#define GC_IRQNUM_RBOX0_INTR_EC_RST_FED_INT      118
-#define GC_IRQNUM_RBOX0_INTR_EC_RST_RED_INT      119
-#define GC_IRQNUM_RBOX0_INTR_KEY0_IN_FED_INT     120
-#define GC_IRQNUM_RBOX0_INTR_KEY0_IN_RED_INT     121
-#define GC_IRQNUM_RBOX0_INTR_KEY1_IN_FED_INT     122
-#define GC_IRQNUM_RBOX0_INTR_KEY1_IN_RED_INT     123
-#define GC_IRQNUM_RBOX0_INTR_PWRB_IN_FED_INT     124
-#define GC_IRQNUM_RBOX0_INTR_PWRB_IN_RED_INT     125
-#define GC_IRQNUM_RDD0_INTR_DEBUG_STATE_DETECTED_INT 126
-#define GC_IRQNUM_SPI0_SPITXINT                  127
-#define GC_IRQNUM_SPI1_SPITXINT                  128
-#define GC_IRQNUM_SPS0_CS_ASSERT_INTR            129
-#define GC_IRQNUM_SPS0_CS_DEASSERT_INTR          130
-#define GC_IRQNUM_SPS0_INTR_CMD_ADDR_FIFO_NOT_EMPTY_INT 131
-#define GC_IRQNUM_SPS0_INTR_CMD_ADDR_FIFO_OVFL_INT 132
-#define GC_IRQNUM_SPS0_INTR_CMD_MEM_OVFL_INT     133
-#define GC_IRQNUM_SPS0_INTR_RAM_PAGE0_LVL_INT    134
-#define GC_IRQNUM_SPS0_INTR_RAM_PAGE1_LVL_INT    135
-#define GC_IRQNUM_SPS0_INTR_RAM_PAGE2_LVL_INT    136
-#define GC_IRQNUM_SPS0_INTR_RAM_PAGE3_LVL_INT    137
-#define GC_IRQNUM_SPS0_RXFIFO_LVL_INTR           138
-#define GC_IRQNUM_SPS0_RXFIFO_OVERFLOW_INTR      139
-#define GC_IRQNUM_SPS0_SPSCTRLINT0               140
-#define GC_IRQNUM_SPS0_SPSCTRLINT1               141
-#define GC_IRQNUM_SPS0_SPSCTRLINT2               142
-#define GC_IRQNUM_SPS0_SPSCTRLINT3               143
-#define GC_IRQNUM_SPS0_SPSCTRLINT4               144
-#define GC_IRQNUM_SPS0_SPSCTRLINT5               145
-#define GC_IRQNUM_SPS0_SPSCTRLINT6               146
-#define GC_IRQNUM_SPS0_SPSCTRLINT7               147
-#define GC_IRQNUM_SPS0_TXFIFO_EMPTY_INTR         148
-#define GC_IRQNUM_SPS0_TXFIFO_FULL_INTR          149
-#define GC_IRQNUM_SPS0_TXFIFO_LVL_INTR           150
-#define GC_IRQNUM_TEMP0_ADC_ICLKDV_INT           151
-#define GC_IRQNUM_TEMP0_COMP_OVERFLOW_INT        152
-#define GC_IRQNUM_TIMEHS0_TIMINT1                153
-#define GC_IRQNUM_TIMEHS0_TIMINT2                154
-#define GC_IRQNUM_TIMEHS0_TIMINTC                155
-#define GC_IRQNUM_TIMEHS1_TIMINT1                156
-#define GC_IRQNUM_TIMEHS1_TIMINT2                157
-#define GC_IRQNUM_TIMEHS1_TIMINTC                158
-#define GC_IRQNUM_TIMELS0_TIMINT0                159
-#define GC_IRQNUM_TIMELS0_TIMINT1                160
-#define GC_IRQNUM_TIMEUS0_INTR_MAX_COUNT_HIT0_INT 161
-#define GC_IRQNUM_TIMEUS0_INTR_MAX_COUNT_HIT1_INT 162
-#define GC_IRQNUM_TIMEUS0_INTR_MAX_COUNT_HIT2_INT 163
-#define GC_IRQNUM_TIMEUS0_INTR_MAX_COUNT_HIT3_INT 164
-#define GC_IRQNUM_TIMEUS0_INTR_PROG_COUNT_HIT0_INT 165
-#define GC_IRQNUM_TIMEUS0_INTR_PROG_COUNT_HIT1_INT 166
-#define GC_IRQNUM_TIMEUS0_INTR_PROG_COUNT_HIT2_INT 167
-#define GC_IRQNUM_TIMEUS0_INTR_PROG_COUNT_HIT3_INT 168
-#define GC_IRQNUM_TRNG0_INTR_BUFFER_FULL_INT     169
-#define GC_IRQNUM_TRNG0_INTR_ONE_SHOT_DONE_INT   170
-#define GC_IRQNUM_TRNG0_INTR_READ_EMPTY_INT      171
-#define GC_IRQNUM_UART0_RXBINT                   172
-#define GC_IRQNUM_UART0_RXFINT                   173
-#define GC_IRQNUM_UART0_RXINT                    174
-#define GC_IRQNUM_UART0_RXOVINT                  175
-#define GC_IRQNUM_UART0_RXTOINT                  176
-#define GC_IRQNUM_UART0_TXINT                    177
-#define GC_IRQNUM_UART0_TXOVINT                  178
-#define GC_IRQNUM_UART1_RXBINT                   179
-#define GC_IRQNUM_UART1_RXFINT                   180
-#define GC_IRQNUM_UART1_RXINT                    181
-#define GC_IRQNUM_UART1_RXOVINT                  182
-#define GC_IRQNUM_UART1_RXTOINT                  183
-#define GC_IRQNUM_UART1_TXINT                    184
-#define GC_IRQNUM_UART1_TXOVINT                  185
-#define GC_IRQNUM_UART2_RXBINT                   186
-#define GC_IRQNUM_UART2_RXFINT                   187
-#define GC_IRQNUM_UART2_RXINT                    188
-#define GC_IRQNUM_UART2_RXOVINT                  189
-#define GC_IRQNUM_UART2_RXTOINT                  190
-#define GC_IRQNUM_UART2_TXINT                    191
-#define GC_IRQNUM_UART2_TXOVINT                  192
-#define GC_IRQNUM_USB0_USBINTR                   193
-#define GC_IRQNUM_WATCHDOG0_WDOGINT              194
-#define GC_IRQNUM_XO0_CLK_JTR_NOP_SEEN_INT       195
-#define GC_IRQNUM_XO0_CLK_JTR_SW_TRIM_DONE_INT   196
-#define GC_IRQNUM_XO0_CLK_TIMER_NOP_SEEN_INT     197
-#define GC_IRQNUM_XO0_CLK_TIMER_SW_TRIM_DONE_INT 198
-#define GC_IRQNUM_XO0_FAST_CALIB_OVERFLOW_INT    199
-#define GC_IRQNUM_XO0_FAST_CALIB_UNDERRUN_INT    200
-#define GC_IRQNUM_XO0_SLOW_CALIB_OVERFLOW_INT    201
-#define GC_IRQNUM_XO0_SLOW_CALIB_UNDERRUN_INT    202
-#define GC_INTERRUPTS_COUNT                      218
-#define GC_CAMO0_BASE_ADDR                       0x40560000
-#define GC_CAMO_BASE_ADDR                        0x40560000
-#define GC_CRYPTO0_BASE_ADDR                     0x40420000
-#define GC_CRYPTO_BASE_ADDR                      0x40420000
-#define GC_DMA0_BASE_ADDR                        0x40430000
-#define GC_DMA_BASE_ADDR                         0x40430000
-#define GC_FLASH0_BASE_ADDR                      0x40720000
-#define GC_FLASH_BASE_ADDR                       0x40720000
-#define GC_FUSE0_BASE_ADDR                       0x40450000
-#define GC_FUSE_BASE_ADDR                        0x40450000
-#define GC_GLOBALSEC_BASE_ADDR                   0x40090000
-#define GC_GPIO0_BASE_ADDR                       0x40200000
-#define GC_GPIO_BASE_ADDR                        0x40200000
-#define GC_GPIO1_BASE_ADDR                       0x40210000
-#define GC_I2C0_BASE_ADDR                        0x40630000
-#define GC_I2C_BASE_ADDR                         0x40630000
-#define GC_I2C1_BASE_ADDR                        0x40640000
-#define GC_I2CS0_BASE_ADDR                       0x40530000
-#define GC_I2CS_BASE_ADDR                        0x40530000
-#define GC_KEYMGR0_BASE_ADDR                     0x40570000
-#define GC_KEYMGR_BASE_ADDR                      0x40570000
-#define GC_PINMUX_BASE_ADDR                      0x40060000
-#define GC_PMU_BASE_ADDR                         0x40000000
-#define GC_M3_BASE_ADDR                          0xe0000000
-#define GC_RBOX0_BASE_ADDR                       0x40550000
-#define GC_RBOX_BASE_ADDR                        0x40550000
-#define GC_RDD0_BASE_ADDR                        0x40440000
-#define GC_RDD_BASE_ADDR                         0x40440000
-#define GC_RTC0_BASE_ADDR                        0x400a0000
-#define GC_RTC_BASE_ADDR                         0x400a0000
-#define GC_SPI0_BASE_ADDR                        0x40700000
-#define GC_SPI_BASE_ADDR                         0x40700000
-#define GC_SPI1_BASE_ADDR                        0x40710000
-#define GC_SPS0_BASE_ADDR                        0x40510000
-#define GC_SPS_BASE_ADDR                         0x40510000
-#define GC_SWDP0_BASE_ADDR                       0x40520000
-#define GC_SWDP_BASE_ADDR                        0x40520000
-#define GC_TEMP0_BASE_ADDR                       0x40400000
-#define GC_TEMP_BASE_ADDR                        0x40400000
-#define GC_TIMEHS0_BASE_ADDR                     0x40650000
-#define GC_TIMEHS_BASE_ADDR                      0x40650000
-#define GC_TIMEHS1_BASE_ADDR                     0x40660000
-#define GC_TIMELS0_BASE_ADDR                     0x40540000
-#define GC_TIMELS_BASE_ADDR                      0x40540000
-#define GC_TIMEUS0_BASE_ADDR                     0x40670000
-#define GC_TIMEUS_BASE_ADDR                      0x40670000
-#define GC_TRNG0_BASE_ADDR                       0x40410000
-#define GC_TRNG_BASE_ADDR                        0x40410000
-#define GC_UART0_BASE_ADDR                       0x40600000
-#define GC_UART_BASE_ADDR                        0x40600000
-#define GC_UART1_BASE_ADDR                       0x40610000
-#define GC_UART2_BASE_ADDR                       0x40620000
-#define GC_USB0_BASE_ADDR                        0x40300000
-#define GC_USB_BASE_ADDR                         0x40300000
-#define GC_VOLT0_BASE_ADDR                       0x40460000
-#define GC_VOLT_BASE_ADDR                        0x40460000
-#define GC_WATCHDOG0_BASE_ADDR                   0x40500000
-#define GC_WATCHDOG_BASE_ADDR                    0x40500000
-#define GC_XO0_BASE_ADDR                         0x400b0000
-#define GC_XO_BASE_ADDR                          0x400b0000
-#define GC_CAMO_BREACH_COUNT_OFFSET              0x0
-#define GC_CAMO_BREACH_COUNT_DEFAULT             0x0
-#define GC_CAMO_CLEAR_COUNTER_OFFSET             0x4
-#define GC_CAMO_CLEAR_COUNTER_DEFAULT            0x0
-#define GC_CAMO_VERSION_OFFSET                   0x8
-#define GC_CAMO_VERSION_DEFAULT                  0x1014125
-#define GC_CRYPTO_VERSION_OFFSET                 0x0
-#define GC_CRYPTO_VERSION_DEFAULT                0x101424a
-#define GC_CRYPTO_CONTROL_OFFSET                 0x4
-#define GC_CRYPTO_CONTROL_DEFAULT                0x0
-#define GC_CRYPTO_PARITY_CFG_OFFSET              0x8
-#define GC_CRYPTO_PARITY_CFG_DEFAULT             0x10
-#define GC_CRYPTO_IMEM_SCRUB_RANGE_OFFSET        0xc
-#define GC_CRYPTO_IMEM_SCRUB_RANGE_DEFAULT       0x3ff
-#define GC_CRYPTO_DMEM_SCRUB_RANGE_OFFSET        0x10
-#define GC_CRYPTO_DMEM_SCRUB_RANGE_DEFAULT       0x7f
-#define GC_CRYPTO_INT_ENABLE_OFFSET              0x14
-#define GC_CRYPTO_INT_ENABLE_DEFAULT             0x0
-#define GC_CRYPTO_INT_STATE_OFFSET               0x18
-#define GC_CRYPTO_INT_STATE_DEFAULT              0x0
-#define GC_CRYPTO_INT_TEST_OFFSET                0x1c
-#define GC_CRYPTO_INT_TEST_DEFAULT               0x0
-#define GC_CRYPTO_HOST_CMD_OFFSET                0x20
-#define GC_CRYPTO_HOST_CMD_DEFAULT               0xffffffff
-#define GC_CRYPTO_INSTR_OFFSET                   0x24
-#define GC_CRYPTO_INSTR_DEFAULT                  0x0
-#define GC_CRYPTO_STATUS_OFFSET                  0x28
-#define GC_CRYPTO_STATUS_DEFAULT                 0x0
-#define GC_CRYPTO_AUX_CC_OFFSET                  0x2c
-#define GC_CRYPTO_AUX_CC_DEFAULT                 0x0
-#define GC_CRYPTO_RAND_STALL_CTL_OFFSET          0x30
-#define GC_CRYPTO_RAND_STALL_CTL_DEFAULT         0x5
-#define GC_CRYPTO_RAND256_OFFSET                 0x34
-#define GC_CRYPTO_RAND256_DEFAULT                0x1
-#define GC_CRYPTO_IMEM_PARITY_ERRS_CTR_STATE_OFFSET 0x38
-#define GC_CRYPTO_IMEM_PARITY_ERRS_CTR_STATE_DEFAULT 0x0
-#define GC_CRYPTO_DMEM_PARITY_ERRS_CTR_STATE_OFFSET 0x3c
-#define GC_CRYPTO_DMEM_PARITY_ERRS_CTR_STATE_DEFAULT 0x0
-#define GC_CRYPTO_DRF_PARITY_ERRS_CTR_STATE_OFFSET 0x40
-#define GC_CRYPTO_DRF_PARITY_ERRS_CTR_STATE_DEFAULT 0x0
-#define GC_CRYPTO_PGM_LFSR_OFFSET                0x44
-#define GC_CRYPTO_PGM_LFSR_DEFAULT               0x0
-#define GC_CRYPTO_DEBUG_BRKPT0_OFFSET            0x48
-#define GC_CRYPTO_DEBUG_BRKPT0_DEFAULT           0x0
-#define GC_CRYPTO_DEBUG_BRKPT1_OFFSET            0x4c
-#define GC_CRYPTO_DEBUG_BRKPT1_DEFAULT           0x0
-#define GC_CRYPTO_WIPE_SECRETS_OFFSET            0x50
-#define GC_CRYPTO_WIPE_SECRETS_DEFAULT           0x0
-#define GC_CRYPTO_DMEM_DUMMY_OFFSET              0x4000
-#define GC_CRYPTO_IMEM_DUMMY_OFFSET              0x8000
-#define GC_DMA_VERSION_OFFSET                    0x0
-#define GC_DMA_VERSION_DEFAULT                   0x101424a
-#define GC_DMA_INT_ENABLE_OFFSET                 0x4
-#define GC_DMA_INT_ENABLE_DEFAULT                0x0
-#define GC_DMA_INT_STATE_OFFSET                  0x8
-#define GC_DMA_INT_STATE_DEFAULT                 0x0
-#define GC_DMA_INT_TEST_OFFSET                   0xc
-#define GC_DMA_INT_TEST_DEFAULT                  0x0
-#define GC_DMA_START_CHAN0_OFFSET                0x100
-#define GC_DMA_START_CHAN0_DEFAULT               0x0
-#define GC_DMA_STOP_CHAN0_OFFSET                 0x104
-#define GC_DMA_STOP_CHAN0_DEFAULT                0x0
-#define GC_DMA_CTRL_CHAN0_OFFSET                 0x108
-#define GC_DMA_CTRL_CHAN0_DEFAULT                0xa
-#define GC_DMA_SRC_ADDR_CHAN0_OFFSET             0x10c
-#define GC_DMA_SRC_ADDR_CHAN0_DEFAULT            0x0
-#define GC_DMA_DST_ADDR_CHAN0_OFFSET             0x110
-#define GC_DMA_DST_ADDR_CHAN0_DEFAULT            0x0
-#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN0_OFFSET 0x114
-#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN0_DEFAULT 0x3ff
-#define GC_DMA_PROG_COUNT_CHAN0_OFFSET           0x118
-#define GC_DMA_PROG_COUNT_CHAN0_DEFAULT          0x0
-#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN0_OFFSET 0x11c
-#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN0_DEFAULT 0x0
-#define GC_DMA_MAX_NUM_TIMEOUT_CHAN0_OFFSET      0x120
-#define GC_DMA_MAX_NUM_TIMEOUT_CHAN0_DEFAULT     0xf9f
-#define GC_DMA_PAUSE_COUNTER_CHAN0_OFFSET        0x124
-#define GC_DMA_PAUSE_COUNTER_CHAN0_DEFAULT       0x0
-#define GC_DMA_FSM_STATE_CHAN0_OFFSET            0x128
-#define GC_DMA_FSM_STATE_CHAN0_DEFAULT           0x1
-#define GC_DMA_START_CHAN1_OFFSET                0x200
-#define GC_DMA_START_CHAN1_DEFAULT               0x0
-#define GC_DMA_STOP_CHAN1_OFFSET                 0x204
-#define GC_DMA_STOP_CHAN1_DEFAULT                0x0
-#define GC_DMA_CTRL_CHAN1_OFFSET                 0x208
-#define GC_DMA_CTRL_CHAN1_DEFAULT                0xa
-#define GC_DMA_SRC_ADDR_CHAN1_OFFSET             0x20c
-#define GC_DMA_SRC_ADDR_CHAN1_DEFAULT            0x0
-#define GC_DMA_DST_ADDR_CHAN1_OFFSET             0x210
-#define GC_DMA_DST_ADDR_CHAN1_DEFAULT            0x0
-#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN1_OFFSET 0x214
-#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN1_DEFAULT 0x3ff
-#define GC_DMA_PROG_COUNT_CHAN1_OFFSET           0x218
-#define GC_DMA_PROG_COUNT_CHAN1_DEFAULT          0x0
-#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN1_OFFSET 0x21c
-#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN1_DEFAULT 0x0
-#define GC_DMA_MAX_NUM_TIMEOUT_CHAN1_OFFSET      0x220
-#define GC_DMA_MAX_NUM_TIMEOUT_CHAN1_DEFAULT     0xf9f
-#define GC_DMA_PAUSE_COUNTER_CHAN1_OFFSET        0x224
-#define GC_DMA_PAUSE_COUNTER_CHAN1_DEFAULT       0x0
-#define GC_DMA_FSM_STATE_CHAN1_OFFSET            0x228
-#define GC_DMA_FSM_STATE_CHAN1_DEFAULT           0x1
-#define GC_DMA_START_CHAN2_OFFSET                0x300
-#define GC_DMA_START_CHAN2_DEFAULT               0x0
-#define GC_DMA_STOP_CHAN2_OFFSET                 0x304
-#define GC_DMA_STOP_CHAN2_DEFAULT                0x0
-#define GC_DMA_CTRL_CHAN2_OFFSET                 0x308
-#define GC_DMA_CTRL_CHAN2_DEFAULT                0xa
-#define GC_DMA_SRC_ADDR_CHAN2_OFFSET             0x30c
-#define GC_DMA_SRC_ADDR_CHAN2_DEFAULT            0x0
-#define GC_DMA_DST_ADDR_CHAN2_OFFSET             0x310
-#define GC_DMA_DST_ADDR_CHAN2_DEFAULT            0x0
-#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN2_OFFSET 0x314
-#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN2_DEFAULT 0x3ff
-#define GC_DMA_PROG_COUNT_CHAN2_OFFSET           0x318
-#define GC_DMA_PROG_COUNT_CHAN2_DEFAULT          0x0
-#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN2_OFFSET 0x31c
-#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN2_DEFAULT 0x0
-#define GC_DMA_MAX_NUM_TIMEOUT_CHAN2_OFFSET      0x320
-#define GC_DMA_MAX_NUM_TIMEOUT_CHAN2_DEFAULT     0xf9f
-#define GC_DMA_PAUSE_COUNTER_CHAN2_OFFSET        0x324
-#define GC_DMA_PAUSE_COUNTER_CHAN2_DEFAULT       0x0
-#define GC_DMA_FSM_STATE_CHAN2_OFFSET            0x328
-#define GC_DMA_FSM_STATE_CHAN2_DEFAULT           0x1
-#define GC_DMA_START_CHAN3_OFFSET                0x400
-#define GC_DMA_START_CHAN3_DEFAULT               0x0
-#define GC_DMA_STOP_CHAN3_OFFSET                 0x404
-#define GC_DMA_STOP_CHAN3_DEFAULT                0x0
-#define GC_DMA_CTRL_CHAN3_OFFSET                 0x408
-#define GC_DMA_CTRL_CHAN3_DEFAULT                0xa
-#define GC_DMA_SRC_ADDR_CHAN3_OFFSET             0x40c
-#define GC_DMA_SRC_ADDR_CHAN3_DEFAULT            0x0
-#define GC_DMA_DST_ADDR_CHAN3_OFFSET             0x410
-#define GC_DMA_DST_ADDR_CHAN3_DEFAULT            0x0
-#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN3_OFFSET 0x414
-#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN3_DEFAULT 0x3ff
-#define GC_DMA_PROG_COUNT_CHAN3_OFFSET           0x418
-#define GC_DMA_PROG_COUNT_CHAN3_DEFAULT          0x0
-#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN3_OFFSET 0x41c
-#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN3_DEFAULT 0x0
-#define GC_DMA_MAX_NUM_TIMEOUT_CHAN3_OFFSET      0x420
-#define GC_DMA_MAX_NUM_TIMEOUT_CHAN3_DEFAULT     0xf9f
-#define GC_DMA_PAUSE_COUNTER_CHAN3_OFFSET        0x424
-#define GC_DMA_PAUSE_COUNTER_CHAN3_DEFAULT       0x0
-#define GC_DMA_FSM_STATE_CHAN3_OFFSET            0x428
-#define GC_DMA_FSM_STATE_CHAN3_DEFAULT           0x1
-#define GC_DMA_START_CHAN4_OFFSET                0x500
-#define GC_DMA_START_CHAN4_DEFAULT               0x0
-#define GC_DMA_STOP_CHAN4_OFFSET                 0x504
-#define GC_DMA_STOP_CHAN4_DEFAULT                0x0
-#define GC_DMA_CTRL_CHAN4_OFFSET                 0x508
-#define GC_DMA_CTRL_CHAN4_DEFAULT                0xa
-#define GC_DMA_SRC_ADDR_CHAN4_OFFSET             0x50c
-#define GC_DMA_SRC_ADDR_CHAN4_DEFAULT            0x0
-#define GC_DMA_DST_ADDR_CHAN4_OFFSET             0x510
-#define GC_DMA_DST_ADDR_CHAN4_DEFAULT            0x0
-#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN4_OFFSET 0x514
-#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN4_DEFAULT 0x3ff
-#define GC_DMA_PROG_COUNT_CHAN4_OFFSET           0x518
-#define GC_DMA_PROG_COUNT_CHAN4_DEFAULT          0x0
-#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN4_OFFSET 0x51c
-#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN4_DEFAULT 0x0
-#define GC_DMA_MAX_NUM_TIMEOUT_CHAN4_OFFSET      0x520
-#define GC_DMA_MAX_NUM_TIMEOUT_CHAN4_DEFAULT     0xf9f
-#define GC_DMA_PAUSE_COUNTER_CHAN4_OFFSET        0x524
-#define GC_DMA_PAUSE_COUNTER_CHAN4_DEFAULT       0x0
-#define GC_DMA_FSM_STATE_CHAN4_OFFSET            0x528
-#define GC_DMA_FSM_STATE_CHAN4_DEFAULT           0x1
-#define GC_DMA_START_CHAN5_OFFSET                0x600
-#define GC_DMA_START_CHAN5_DEFAULT               0x0
-#define GC_DMA_STOP_CHAN5_OFFSET                 0x604
-#define GC_DMA_STOP_CHAN5_DEFAULT                0x0
-#define GC_DMA_CTRL_CHAN5_OFFSET                 0x608
-#define GC_DMA_CTRL_CHAN5_DEFAULT                0xa
-#define GC_DMA_SRC_ADDR_CHAN5_OFFSET             0x60c
-#define GC_DMA_SRC_ADDR_CHAN5_DEFAULT            0x0
-#define GC_DMA_DST_ADDR_CHAN5_OFFSET             0x610
-#define GC_DMA_DST_ADDR_CHAN5_DEFAULT            0x0
-#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN5_OFFSET 0x614
-#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN5_DEFAULT 0x3ff
-#define GC_DMA_PROG_COUNT_CHAN5_OFFSET           0x618
-#define GC_DMA_PROG_COUNT_CHAN5_DEFAULT          0x0
-#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN5_OFFSET 0x61c
-#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN5_DEFAULT 0x0
-#define GC_DMA_MAX_NUM_TIMEOUT_CHAN5_OFFSET      0x620
-#define GC_DMA_MAX_NUM_TIMEOUT_CHAN5_DEFAULT     0xf9f
-#define GC_DMA_PAUSE_COUNTER_CHAN5_OFFSET        0x624
-#define GC_DMA_PAUSE_COUNTER_CHAN5_DEFAULT       0x0
-#define GC_DMA_FSM_STATE_CHAN5_OFFSET            0x628
-#define GC_DMA_FSM_STATE_CHAN5_DEFAULT           0x1
-#define GC_DMA_START_CHAN6_OFFSET                0x700
-#define GC_DMA_START_CHAN6_DEFAULT               0x0
-#define GC_DMA_STOP_CHAN6_OFFSET                 0x704
-#define GC_DMA_STOP_CHAN6_DEFAULT                0x0
-#define GC_DMA_CTRL_CHAN6_OFFSET                 0x708
-#define GC_DMA_CTRL_CHAN6_DEFAULT                0xa
-#define GC_DMA_SRC_ADDR_CHAN6_OFFSET             0x70c
-#define GC_DMA_SRC_ADDR_CHAN6_DEFAULT            0x0
-#define GC_DMA_DST_ADDR_CHAN6_OFFSET             0x710
-#define GC_DMA_DST_ADDR_CHAN6_DEFAULT            0x0
-#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN6_OFFSET 0x714
-#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN6_DEFAULT 0x3ff
-#define GC_DMA_PROG_COUNT_CHAN6_OFFSET           0x718
-#define GC_DMA_PROG_COUNT_CHAN6_DEFAULT          0x0
-#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN6_OFFSET 0x71c
-#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN6_DEFAULT 0x0
-#define GC_DMA_MAX_NUM_TIMEOUT_CHAN6_OFFSET      0x720
-#define GC_DMA_MAX_NUM_TIMEOUT_CHAN6_DEFAULT     0xf9f
-#define GC_DMA_PAUSE_COUNTER_CHAN6_OFFSET        0x724
-#define GC_DMA_PAUSE_COUNTER_CHAN6_DEFAULT       0x0
-#define GC_DMA_FSM_STATE_CHAN6_OFFSET            0x728
-#define GC_DMA_FSM_STATE_CHAN6_DEFAULT           0x1
-#define GC_DMA_START_CHAN7_OFFSET                0x800
-#define GC_DMA_START_CHAN7_DEFAULT               0x0
-#define GC_DMA_STOP_CHAN7_OFFSET                 0x804
-#define GC_DMA_STOP_CHAN7_DEFAULT                0x0
-#define GC_DMA_CTRL_CHAN7_OFFSET                 0x808
-#define GC_DMA_CTRL_CHAN7_DEFAULT                0xa
-#define GC_DMA_SRC_ADDR_CHAN7_OFFSET             0x80c
-#define GC_DMA_SRC_ADDR_CHAN7_DEFAULT            0x0
-#define GC_DMA_DST_ADDR_CHAN7_OFFSET             0x810
-#define GC_DMA_DST_ADDR_CHAN7_DEFAULT            0x0
-#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN7_OFFSET 0x814
-#define GC_DMA_NUM_TRANSACTION_COUNT_CHAN7_DEFAULT 0x3ff
-#define GC_DMA_PROG_COUNT_CHAN7_OFFSET           0x818
-#define GC_DMA_PROG_COUNT_CHAN7_DEFAULT          0x0
-#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN7_OFFSET 0x81c
-#define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN7_DEFAULT 0x0
-#define GC_DMA_MAX_NUM_TIMEOUT_CHAN7_OFFSET      0x820
-#define GC_DMA_MAX_NUM_TIMEOUT_CHAN7_DEFAULT     0xf9f
-#define GC_DMA_PAUSE_COUNTER_CHAN7_OFFSET        0x824
-#define GC_DMA_PAUSE_COUNTER_CHAN7_DEFAULT       0x0
-#define GC_DMA_FSM_STATE_CHAN7_OFFSET            0x828
-#define GC_DMA_FSM_STATE_CHAN7_DEFAULT           0x1
-#define GC_FLASH_FSH_PE_CONTROL0_OFFSET          0x0
-#define GC_FLASH_FSH_PE_CONTROL0_DEFAULT         0x0
-#define GC_FLASH_FSH_PE_CONTROL0_PROG            0x27182818
-#define GC_FLASH_FSH_PE_CONTROL0_READ            0x16021765
-#define GC_FLASH_FSH_PE_CONTROL0_BULKERASE       0x1d1e2bad
-#define GC_FLASH_FSH_PE_CONTROL0_ERASE           0x31415927
-#define GC_FLASH_FSH_PE_CONTROL1_OFFSET          0x4
-#define GC_FLASH_FSH_PE_CONTROL1_DEFAULT         0x0
-#define GC_FLASH_FSH_PE_CONTROL1_PROG            0x27182818
-#define GC_FLASH_FSH_PE_CONTROL1_READ            0x16021765
-#define GC_FLASH_FSH_PE_CONTROL1_BULKERASE       0x1d1e2bad
-#define GC_FLASH_FSH_PE_CONTROL1_ERASE           0x31415927
-#define GC_FLASH_FSH_TRANS_OFFSET                0x8
-#define GC_FLASH_FSH_TRANS_DEFAULT               0x0
-#define GC_FLASH_FSH_PROTECT_INFO1_OFFSET        0xc
-#define GC_FLASH_FSH_PROTECT_INFO1_DEFAULT       0x0
-#define GC_FLASH_FSH_ENABLE_INFO0_SHADOW_READ_OFFSET 0x10
-#define GC_FLASH_FSH_ENABLE_INFO0_SHADOW_READ_DEFAULT 0x0
-#define GC_FLASH_FSH_ICTRL_OFFSET                0x14
-#define GC_FLASH_FSH_ICTRL_DEFAULT               0x0
-#define GC_FLASH_FSH_ISTATE_OFFSET               0x18
-#define GC_FLASH_FSH_ISTATE_DEFAULT              0x0
-#define GC_FLASH_FSH_OVRD0_UNLOCK_OFFSET         0x1c
-#define GC_FLASH_FSH_OVRD0_UNLOCK_DEFAULT        0x0
-#define GC_FLASH_FSH_OVRD0_UNLOCK_KEY            0x13806488
-#define GC_FLASH_FSH_OVRD1_UNLOCK_OFFSET         0x20
-#define GC_FLASH_FSH_OVRD1_UNLOCK_DEFAULT        0x0
-#define GC_FLASH_FSH_OVRD1_UNLOCK_KEY            0x13806488
-#define GC_FLASH_FSH_OVRD_SIGVAL_DIN_OFFSET      0x24
-#define GC_FLASH_FSH_OVRD_SIGVAL_DIN_DEFAULT     0x0
-#define GC_FLASH_FSH_OVRD_SIGVAL_OFFSET_OFFSET   0x28
-#define GC_FLASH_FSH_OVRD_SIGVAL_OFFSET_DEFAULT  0x0
-#define GC_FLASH_FSH_OVRD_SIGVAL_OFFSET          0x2c
-#define GC_FLASH_FSH_OVRD_SIGVAL_DEFAULT         0x0
-#define GC_FLASH_FSH_OVRD_SIGEN_OFFSET           0x30
-#define GC_FLASH_FSH_OVRD_SIGEN_DEFAULT          0x0
-#define GC_FLASH_FSH_NO_WAIT_ON_BOUT_SEQ_OFFSET  0x34
-#define GC_FLASH_FSH_NO_WAIT_ON_BOUT_SEQ_DEFAULT 0x0
-#define GC_FLASH_FSH_DOUT_VAL0_OFFSET            0x38
-#define GC_FLASH_FSH_DOUT_VAL0_DEFAULT           0x0
-#define GC_FLASH_FSH_OVRD_SIGVAL_TC0_OFFSET      0x3c
-#define GC_FLASH_FSH_OVRD_SIGVAL_TC0_DEFAULT     0x0
-#define GC_FLASH_FSH_DOUT_VAL1_OFFSET            0x40
-#define GC_FLASH_FSH_DOUT_VAL1_DEFAULT           0x0
-#define GC_FLASH_FSH_OVRD_SIGVAL_TC1_OFFSET      0x44
-#define GC_FLASH_FSH_OVRD_SIGVAL_TC1_DEFAULT     0x0
-#define GC_FLASH_FSH_WR_DATA0_OFFSET             0x48
-#define GC_FLASH_FSH_WR_DATA0_DEFAULT            0x0
-#define GC_FLASH_FSH_WR_DATA1_OFFSET             0x4c
-#define GC_FLASH_FSH_WR_DATA1_DEFAULT            0x0
-#define GC_FLASH_FSH_WR_DATA2_OFFSET             0x50
-#define GC_FLASH_FSH_WR_DATA2_DEFAULT            0x0
-#define GC_FLASH_FSH_WR_DATA3_OFFSET             0x54
-#define GC_FLASH_FSH_WR_DATA3_DEFAULT            0x0
-#define GC_FLASH_FSH_WR_DATA4_OFFSET             0x58
-#define GC_FLASH_FSH_WR_DATA4_DEFAULT            0x0
-#define GC_FLASH_FSH_WR_DATA5_OFFSET             0x5c
-#define GC_FLASH_FSH_WR_DATA5_DEFAULT            0x0
-#define GC_FLASH_FSH_WR_DATA6_OFFSET             0x60
-#define GC_FLASH_FSH_WR_DATA6_DEFAULT            0x0
-#define GC_FLASH_FSH_WR_DATA7_OFFSET             0x64
-#define GC_FLASH_FSH_WR_DATA7_DEFAULT            0x0
-#define GC_FLASH_FSH_WR_DATA8_OFFSET             0x68
-#define GC_FLASH_FSH_WR_DATA8_DEFAULT            0x0
-#define GC_FLASH_FSH_WR_DATA9_OFFSET             0x6c
-#define GC_FLASH_FSH_WR_DATA9_DEFAULT            0x0
-#define GC_FLASH_FSH_WR_DATA10_OFFSET            0x70
-#define GC_FLASH_FSH_WR_DATA10_DEFAULT           0x0
-#define GC_FLASH_FSH_WR_DATA11_OFFSET            0x74
-#define GC_FLASH_FSH_WR_DATA11_DEFAULT           0x0
-#define GC_FLASH_FSH_WR_DATA12_OFFSET            0x78
-#define GC_FLASH_FSH_WR_DATA12_DEFAULT           0x0
-#define GC_FLASH_FSH_WR_DATA13_OFFSET            0x7c
-#define GC_FLASH_FSH_WR_DATA13_DEFAULT           0x0
-#define GC_FLASH_FSH_WR_DATA14_OFFSET            0x80
-#define GC_FLASH_FSH_WR_DATA14_DEFAULT           0x0
-#define GC_FLASH_FSH_WR_DATA15_OFFSET            0x84
-#define GC_FLASH_FSH_WR_DATA15_DEFAULT           0x0
-#define GC_FLASH_FSH_WR_DATA16_OFFSET            0x88
-#define GC_FLASH_FSH_WR_DATA16_DEFAULT           0x0
-#define GC_FLASH_FSH_WR_DATA17_OFFSET            0x8c
-#define GC_FLASH_FSH_WR_DATA17_DEFAULT           0x0
-#define GC_FLASH_FSH_WR_DATA18_OFFSET            0x90
-#define GC_FLASH_FSH_WR_DATA18_DEFAULT           0x0
-#define GC_FLASH_FSH_WR_DATA19_OFFSET            0x94
-#define GC_FLASH_FSH_WR_DATA19_DEFAULT           0x0
-#define GC_FLASH_FSH_WR_DATA20_OFFSET            0x98
-#define GC_FLASH_FSH_WR_DATA20_DEFAULT           0x0
-#define GC_FLASH_FSH_WR_DATA21_OFFSET            0x9c
-#define GC_FLASH_FSH_WR_DATA21_DEFAULT           0x0
-#define GC_FLASH_FSH_WR_DATA22_OFFSET            0xa0
-#define GC_FLASH_FSH_WR_DATA22_DEFAULT           0x0
-#define GC_FLASH_FSH_WR_DATA23_OFFSET            0xa4
-#define GC_FLASH_FSH_WR_DATA23_DEFAULT           0x0
-#define GC_FLASH_FSH_WR_DATA24_OFFSET            0xa8
-#define GC_FLASH_FSH_WR_DATA24_DEFAULT           0x0
-#define GC_FLASH_FSH_WR_DATA25_OFFSET            0xac
-#define GC_FLASH_FSH_WR_DATA25_DEFAULT           0x0
-#define GC_FLASH_FSH_WR_DATA26_OFFSET            0xb0
-#define GC_FLASH_FSH_WR_DATA26_DEFAULT           0x0
-#define GC_FLASH_FSH_WR_DATA27_OFFSET            0xb4
-#define GC_FLASH_FSH_WR_DATA27_DEFAULT           0x0
-#define GC_FLASH_FSH_WR_DATA28_OFFSET            0xb8
-#define GC_FLASH_FSH_WR_DATA28_DEFAULT           0x0
-#define GC_FLASH_FSH_WR_DATA29_OFFSET            0xbc
-#define GC_FLASH_FSH_WR_DATA29_DEFAULT           0x0
-#define GC_FLASH_FSH_WR_DATA30_OFFSET            0xc0
-#define GC_FLASH_FSH_WR_DATA30_DEFAULT           0x0
-#define GC_FLASH_FSH_WR_DATA31_OFFSET            0xc4
-#define GC_FLASH_FSH_WR_DATA31_DEFAULT           0x0
-#define GC_FLASH_FSH_PE_EN_OFFSET                0xc8
-#define GC_FLASH_FSH_PE_EN_DEFAULT               0x0
-#define GC_FLASH_FSH_PE_EN_KEY                   0xb11924e1
-#define GC_FLASH_FSH_REDUN0_OFFSET               0xcc
-#define GC_FLASH_FSH_REDUN0_DEFAULT              0x0
-#define GC_FLASH_FSH_REDUN1_OFFSET               0xd0
-#define GC_FLASH_FSH_REDUN1_DEFAULT              0x0
-#define GC_FLASH_FSH_ERROR_OFFSET                0xd4
-#define GC_FLASH_FSH_ERROR_DEFAULT               0x0
-#define GC_FLASH_FSH_TIMING_READ_TOTAL_CYC_OFFSET 0xd8
-#define GC_FLASH_FSH_TIMING_READ_TOTAL_CYC_DEFAULT 0x1
-#define GC_FLASH_FSH_TIMING_READ_XE_FRST_CYC_OFFSET 0xdc
-#define GC_FLASH_FSH_TIMING_READ_XE_FRST_CYC_DEFAULT 0x0
-#define GC_FLASH_FSH_TIMING_READ_XE_LAST_CYC_OFFSET 0xe0
-#define GC_FLASH_FSH_TIMING_READ_XE_LAST_CYC_DEFAULT 0x0
-#define GC_FLASH_FSH_TIMING_READ_YE_FRST_CYC_OFFSET 0xe4
-#define GC_FLASH_FSH_TIMING_READ_YE_FRST_CYC_DEFAULT 0x0
-#define GC_FLASH_FSH_TIMING_READ_YE_LAST_CYC_OFFSET 0xe8
-#define GC_FLASH_FSH_TIMING_READ_YE_LAST_CYC_DEFAULT 0x0
-#define GC_FLASH_FSH_TIMING_READ_SE_FRST_CYC_OFFSET 0xec
-#define GC_FLASH_FSH_TIMING_READ_SE_FRST_CYC_DEFAULT 0x0
-#define GC_FLASH_FSH_TIMING_READ_SE_LAST_CYC_OFFSET 0xf0
-#define GC_FLASH_FSH_TIMING_READ_SE_LAST_CYC_DEFAULT 0x0
-#define GC_FLASH_FSH_TIMING_READ_PV_FRST_CYC_OFFSET 0xf4
-#define GC_FLASH_FSH_TIMING_READ_PV_FRST_CYC_DEFAULT 0x0
-#define GC_FLASH_FSH_TIMING_READ_PV_LAST_CYC_OFFSET 0xf8
-#define GC_FLASH_FSH_TIMING_READ_PV_LAST_CYC_DEFAULT 0x0
-#define GC_FLASH_FSH_TIMING_READ_EV_FRST_CYC_OFFSET 0xfc
-#define GC_FLASH_FSH_TIMING_READ_EV_FRST_CYC_DEFAULT 0x0
-#define GC_FLASH_FSH_TIMING_READ_EV_LAST_CYC_OFFSET 0x100
-#define GC_FLASH_FSH_TIMING_READ_EV_LAST_CYC_DEFAULT 0x0
-#define GC_FLASH_FSH_TIMING_PROG_SMART_ALGO_ON_OFFSET 0x104
-#define GC_FLASH_FSH_TIMING_PROG_SMART_ALGO_ON_DEFAULT 0x1
-#define GC_FLASH_FSH_TIMING_PROG_TOTAL_CYC_OFFSET 0x108
-#define GC_FLASH_FSH_TIMING_PROG_TOTAL_CYC_DEFAULT 0x37e
-#define GC_FLASH_FSH_TIMING_PROG_XE_FRST_CYC_OFFSET 0x10c
-#define GC_FLASH_FSH_TIMING_PROG_XE_FRST_CYC_DEFAULT 0x0
-#define GC_FLASH_FSH_TIMING_PROG_XE_LAST_CYC_OFFSET 0x110
-#define GC_FLASH_FSH_TIMING_PROG_XE_LAST_CYC_DEFAULT 0x265
-#define GC_FLASH_FSH_TIMING_PROG_YE_FRST_CYC_OFFSET 0x114
-#define GC_FLASH_FSH_TIMING_PROG_YE_FRST_CYC_DEFAULT 0x1a7
-#define GC_FLASH_FSH_TIMING_PROG_YE_LAST_CYC_OFFSET 0x118
-#define GC_FLASH_FSH_TIMING_PROG_YE_LAST_CYC_DEFAULT 0x1d6
-#define GC_FLASH_FSH_TIMING_PROG_ONEWRD_FRST_CYC_OFFSET 0x11c
-#define GC_FLASH_FSH_TIMING_PROG_ONEWRD_FRST_CYC_DEFAULT 0x1a6
-#define GC_FLASH_FSH_TIMING_PROG_ONEWRD_LAST_CYC_OFFSET 0x120
-#define GC_FLASH_FSH_TIMING_PROG_ONEWRD_LAST_CYC_DEFAULT 0x1d7
-#define GC_FLASH_FSH_TIMING_PROG_PROGSIG_FRST_CYC_OFFSET 0x124
-#define GC_FLASH_FSH_TIMING_PROG_PROGSIG_FRST_CYC_DEFAULT 0x1
-#define GC_FLASH_FSH_TIMING_PROG_PROGSIG_LAST_CYC_OFFSET 0x128
-#define GC_FLASH_FSH_TIMING_PROG_PROGSIG_LAST_CYC_DEFAULT 0x1d7
-#define GC_FLASH_FSH_TIMING_PROG_NVSTR_FRST_CYC_OFFSET 0x12c
-#define GC_FLASH_FSH_TIMING_PROG_NVSTR_FRST_CYC_DEFAULT 0x8d
-#define GC_FLASH_FSH_TIMING_PROG_NVSTR_LAST_CYC_OFFSET 0x130
-#define GC_FLASH_FSH_TIMING_PROG_NVSTR_LAST_CYC_DEFAULT 0x264
-#define GC_FLASH_FSH_TIMING_ERASE_SMART_ALGO_ON_OFFSET 0x134
-#define GC_FLASH_FSH_TIMING_ERASE_SMART_ALGO_ON_DEFAULT 0x1
-#define GC_FLASH_FSH_TIMING_ERASE_TOTAL_CYC_OFFSET 0x138
-#define GC_FLASH_FSH_TIMING_ERASE_TOTAL_CYC_DEFAULT 0xbb12
-#define GC_FLASH_FSH_TIMING_ERASE_XE_FRST_CYC_OFFSET 0x13c
-#define GC_FLASH_FSH_TIMING_ERASE_XE_FRST_CYC_DEFAULT 0x0
-#define GC_FLASH_FSH_TIMING_ERASE_XE_LAST_CYC_OFFSET 0x140
-#define GC_FLASH_FSH_TIMING_ERASE_XE_LAST_CYC_DEFAULT 0xb9f9
-#define GC_FLASH_FSH_TIMING_ERASE_ERASESIG_FRST_CYC_OFFSET 0x144
-#define GC_FLASH_FSH_TIMING_ERASE_ERASESIG_FRST_CYC_DEFAULT 0x1
-#define GC_FLASH_FSH_TIMING_ERASE_ERASESIG_LAST_CYC_OFFSET 0x148
-#define GC_FLASH_FSH_TIMING_ERASE_ERASESIG_LAST_CYC_DEFAULT 0xb96b
-#define GC_FLASH_FSH_TIMING_ERASE_NVSTR_FRST_CYC_OFFSET 0x14c
-#define GC_FLASH_FSH_TIMING_ERASE_NVSTR_FRST_CYC_DEFAULT 0x8d
-#define GC_FLASH_FSH_TIMING_ERASE_NVSTR_LAST_CYC_OFFSET 0x150
-#define GC_FLASH_FSH_TIMING_ERASE_NVSTR_LAST_CYC_DEFAULT 0xb9f8
-#define GC_FLASH_FSH_TIMING_BULKERASE_SMART_ALGO_ON_OFFSET 0x154
-#define GC_FLASH_FSH_TIMING_BULKERASE_SMART_ALGO_ON_DEFAULT 0x1
-#define GC_FLASH_FSH_TIMING_BULKERASE_TOTAL_CYC_OFFSET 0x158
-#define GC_FLASH_FSH_TIMING_BULKERASE_TOTAL_CYC_DEFAULT 0xc585
-#define GC_FLASH_FSH_TIMING_BULKERASE_XE_FRST_CYC_OFFSET 0x15c
-#define GC_FLASH_FSH_TIMING_BULKERASE_XE_FRST_CYC_DEFAULT 0x0
-#define GC_FLASH_FSH_TIMING_BULKERASE_XE_LAST_CYC_OFFSET 0x160
-#define GC_FLASH_FSH_TIMING_BULKERASE_XE_LAST_CYC_DEFAULT 0xc46c
-#define GC_FLASH_FSH_TIMING_BULKERASE_ERASESIG_FRST_CYC_OFFSET 0x164
-#define GC_FLASH_FSH_TIMING_BULKERASE_ERASESIG_FRST_CYC_DEFAULT 0x1
-#define GC_FLASH_FSH_TIMING_BULKERASE_ERASESIG_LAST_CYC_OFFSET 0x168
-#define GC_FLASH_FSH_TIMING_BULKERASE_ERASESIG_LAST_CYC_DEFAULT 0xb96b
-#define GC_FLASH_FSH_TIMING_BULKERASE_MAS1_FRST_CYC_OFFSET 0x16c
-#define GC_FLASH_FSH_TIMING_BULKERASE_MAS1_FRST_CYC_DEFAULT 0x0
-#define GC_FLASH_FSH_TIMING_BULKERASE_MAS1_LAST_CYC_OFFSET 0x170
-#define GC_FLASH_FSH_TIMING_BULKERASE_MAS1_LAST_CYC_DEFAULT 0xc46c
-#define GC_FLASH_FSH_TIMING_BULKERASE_NVSTR_FRST_CYC_OFFSET 0x174
-#define GC_FLASH_FSH_TIMING_BULKERASE_NVSTR_FRST_CYC_DEFAULT 0x8d
-#define GC_FLASH_FSH_TIMING_BULKERASE_NVSTR_LAST_CYC_OFFSET 0x178
-#define GC_FLASH_FSH_TIMING_BULKERASE_NVSTR_LAST_CYC_DEFAULT 0xc46b
-#define GC_FLASH_FSH_DBG_OFFSET                  0x17c
-#define GC_FLASH_FSH_DBG_DEFAULT                 0x0
-#define GC_FLASH_FSH_ITCR_OFFSET                 0xf00
-#define GC_FLASH_FSH_ITCR_DEFAULT                0x0
-#define GC_FLASH_FSH_ITOP_OFFSET                 0xf04
-#define GC_FLASH_FSH_ITOP_DEFAULT                0x0
-#define GC_FUSE_STATUS_OFFSET                    0x0
-#define GC_FUSE_STATUS_DEFAULT                   0x0
-#define GC_FUSE_READ_START_OFFSET                0x4
-#define GC_FUSE_READ_START_DEFAULT               0x0
-#define GC_FUSE_READ_START_DISABLE               0x0
-#define GC_FUSE_READ_START_ENABLE                0xc8eca61e
-#define GC_FUSE_PROG_START_OFFSET                0x8
-#define GC_FUSE_PROG_START_DEFAULT               0x0
-#define GC_FUSE_PROG_START_DISABLE               0x0
-#define GC_FUSE_PROG_START_ENABLE                0xdc98157b
-#define GC_FUSE_OVERRIDE_START_OFFSET            0xc
-#define GC_FUSE_OVERRIDE_START_DEFAULT           0x0
-#define GC_FUSE_OVERRIDE_START_DISABLE           0x0
-#define GC_FUSE_OVERRIDE_START_ENABLE            0x894e4cf3
-#define GC_FUSE_FPGA_MODEL_CTRL_OFFSET           0x10
-#define GC_FUSE_FPGA_MODEL_CTRL_DEFAULT          0x0
-#define GC_FUSE_SCRUB_PRBS_CLK_DIV_OFFSET        0x14
-#define GC_FUSE_SCRUB_PRBS_CLK_DIV_DEFAULT       0xffffff
-#define GC_FUSE_SCRUB_PRBS_THRESHOLD_VAL_OFFSET  0x18
-#define GC_FUSE_SCRUB_PRBS_THRESHOLD_VAL_DEFAULT 0x7fff
-#define GC_FUSE_SCRUB_ENABLE_OFFSET              0x1c
-#define GC_FUSE_SCRUB_ENABLE_DEFAULT             0x0
-#define GC_FUSE_SCRUB_ENABLE_DISABLE             0x0
-#define GC_FUSE_SCRUB_ENABLE_ENABLE              0x5
-#define GC_FUSE_ERROR_INJECT_OFFSET              0x20
-#define GC_FUSE_ERROR_INJECT_DEFAULT             0x0
-#define GC_FUSE_ERROR_INJECT_DISABLE             0x0
-#define GC_FUSE_ERROR_INJECT_ENABLE              0x690c7334
-#define GC_FUSE_VDDQ_RAMP_TIMING_OFFSET          0x24
-#define GC_FUSE_VDDQ_RAMP_TIMING_DEFAULT         0x1d4c0
-#define GC_FUSE_ANTEST_EN_OFFSET                 0x28
-#define GC_FUSE_ANTEST_EN_DEFAULT                0x0
-#define GC_FUSE_VERSION_OFFSET                   0x2c
-#define GC_FUSE_VERSION_DEFAULT                  0x1014125
-#define GC_FUSE_BNK0_INTG_CHKSUM_OFFSET          0x30
-#define GC_FUSE_BNK0_INTG_CHKSUM_DEFAULT         0x55000000
-#define GC_FUSE_BNK0_INTG_LOCK_OFFSET            0x34
-#define GC_FUSE_BNK0_INTG_LOCK_DEFAULT           0x55555550
-#define GC_FUSE_DS_GRP0_OFFSET                   0x38
-#define GC_FUSE_DS_GRP0_DEFAULT                  0x55555400
-#define GC_FUSE_DS_GRP1_OFFSET                   0x3c
-#define GC_FUSE_DS_GRP1_DEFAULT                  0x55555400
-#define GC_FUSE_DS_GRP2_OFFSET                   0x40
-#define GC_FUSE_DS_GRP2_DEFAULT                  0x55555400
-#define GC_FUSE_DEV_ID0_OFFSET                   0x44
-#define GC_FUSE_DEV_ID0_DEFAULT                  0x0
-#define GC_FUSE_DEV_ID1_OFFSET                   0x48
-#define GC_FUSE_DEV_ID1_DEFAULT                  0x0
-#define GC_FUSE_BNK1_INTG_CHKSUM_OFFSET          0x4c
-#define GC_FUSE_BNK1_INTG_CHKSUM_DEFAULT         0x55000000
-#define GC_FUSE_BNK1_INTG_LOCK_OFFSET            0x50
-#define GC_FUSE_BNK1_INTG_LOCK_DEFAULT           0x55555550
-#define GC_FUSE_LB0_POST_OVRD_OFFSET             0x54
-#define GC_FUSE_LB0_POST_OVRD_DEFAULT            0x55555550
-#define GC_FUSE_LB0_POST_PATCNT_OFFSET           0x58
-#define GC_FUSE_LB0_POST_PATCNT_DEFAULT          0x55555554
-#define GC_FUSE_LB0_POST_WARMUP_OVRD_OFFSET      0x5c
-#define GC_FUSE_LB0_POST_WARMUP_OVRD_DEFAULT     0x55555550
-#define GC_FUSE_LB0_POST_WARMUP_CNT_OFFSET       0x60
-#define GC_FUSE_LB0_POST_WARMUP_CNT_DEFAULT      0x55555554
-#define GC_FUSE_LB1_POST_OVRD_OFFSET             0x64
-#define GC_FUSE_LB1_POST_OVRD_DEFAULT            0x55555550
-#define GC_FUSE_LB1_POST_PATCNT_OFFSET           0x68
-#define GC_FUSE_LB1_POST_PATCNT_DEFAULT          0x55555554
-#define GC_FUSE_LB1_POST_WARMUP_OVRD_OFFSET      0x6c
-#define GC_FUSE_LB1_POST_WARMUP_OVRD_DEFAULT     0x55555550
-#define GC_FUSE_LB1_POST_WARMUP_CNT_OFFSET       0x70
-#define GC_FUSE_LB1_POST_WARMUP_CNT_DEFAULT      0x55555554
-#define GC_FUSE_LB2_POST_OVRD_OFFSET             0x74
-#define GC_FUSE_LB2_POST_OVRD_DEFAULT            0x55555550
-#define GC_FUSE_LB2_POST_PATCNT_OFFSET           0x78
-#define GC_FUSE_LB2_POST_PATCNT_DEFAULT          0x55555554
-#define GC_FUSE_LB2_POST_WARMUP_OVRD_OFFSET      0x7c
-#define GC_FUSE_LB2_POST_WARMUP_OVRD_DEFAULT     0x55555550
-#define GC_FUSE_LB2_POST_WARMUP_CNT_OFFSET       0x80
-#define GC_FUSE_LB2_POST_WARMUP_CNT_DEFAULT      0x55555554
-#define GC_FUSE_LB3_POST_OVRD_OFFSET             0x84
-#define GC_FUSE_LB3_POST_OVRD_DEFAULT            0x55555550
-#define GC_FUSE_LB3_POST_PATCNT_OFFSET           0x88
-#define GC_FUSE_LB3_POST_PATCNT_DEFAULT          0x55555554
-#define GC_FUSE_LB3_POST_WARMUP_OVRD_OFFSET      0x8c
-#define GC_FUSE_LB3_POST_WARMUP_OVRD_DEFAULT     0x55555550
-#define GC_FUSE_LB3_POST_WARMUP_CNT_OFFSET       0x90
-#define GC_FUSE_LB3_POST_WARMUP_CNT_DEFAULT      0x55555554
-#define GC_FUSE_LB4_POST_OVRD_OFFSET             0x94
-#define GC_FUSE_LB4_POST_OVRD_DEFAULT            0x55555550
-#define GC_FUSE_LB4_POST_PATCNT_OFFSET           0x98
-#define GC_FUSE_LB4_POST_PATCNT_DEFAULT          0x55555554
-#define GC_FUSE_LB4_POST_WARMUP_OVRD_OFFSET      0x9c
-#define GC_FUSE_LB4_POST_WARMUP_OVRD_DEFAULT     0x55555550
-#define GC_FUSE_LB4_POST_WARMUP_CNT_OFFSET       0xa0
-#define GC_FUSE_LB4_POST_WARMUP_CNT_DEFAULT      0x55555554
-#define GC_FUSE_MBIST_POST_SEQ_OFFSET            0xa4
-#define GC_FUSE_MBIST_POST_SEQ_DEFAULT           0x54000000
-#define GC_FUSE_LBIST_POST_SEQ_OFFSET            0xa8
-#define GC_FUSE_LBIST_POST_SEQ_DEFAULT           0x54000000
-#define GC_FUSE_LBIST_VIA_TAP_DIS_OFFSET         0xac
-#define GC_FUSE_LBIST_VIA_TAP_DIS_DEFAULT        0x55555550
-#define GC_FUSE_MBIST_VIA_TAP_DIS_OFFSET         0xb0
-#define GC_FUSE_MBIST_VIA_TAP_DIS_DEFAULT        0x55555550
-#define GC_FUSE_TAP_DISABLE_OFFSET               0xb4
-#define GC_FUSE_TAP_DISABLE_DEFAULT              0x55555550
-#define GC_FUSE_RNGBIST_AR_EN_OFFSET             0xb8
-#define GC_FUSE_RNGBIST_AR_EN_DEFAULT            0x55555550
-#define GC_FUSE_TESTMODE_KEYS_EN_OFFSET          0xbc
-#define GC_FUSE_TESTMODE_KEYS_EN_DEFAULT         0x55555550
-#define GC_FUSE_PKG_ID_OFFSET                    0xc0
-#define GC_FUSE_PKG_ID_DEFAULT                   0x55555550
-#define GC_FUSE_BIN_ID_OFFSET                    0xc4
-#define GC_FUSE_BIN_ID_DEFAULT                   0x55555550
-#define GC_FUSE_RC_JTR_OSC48_CC_TRIM_OFFSET      0xc8
-#define GC_FUSE_RC_JTR_OSC48_CC_TRIM_DEFAULT     0x55555500
-#define GC_FUSE_RC_JTR_OSC48_CC_EN_OFFSET        0xcc
-#define GC_FUSE_RC_JTR_OSC48_CC_EN_DEFAULT       0x55555550
-#define GC_FUSE_RC_JTR_OSC60_CC_TRIM_OFFSET      0xd0
-#define GC_FUSE_RC_JTR_OSC60_CC_TRIM_DEFAULT     0x55555500
-#define GC_FUSE_RC_JTR_OSC60_CC_EN_OFFSET        0xd4
-#define GC_FUSE_RC_JTR_OSC60_CC_EN_DEFAULT       0x55555550
-#define GC_FUSE_RC_TIMER_OSC48_CC_TRIM_OFFSET    0xd8
-#define GC_FUSE_RC_TIMER_OSC48_CC_TRIM_DEFAULT   0x55555500
-#define GC_FUSE_RC_TIMER_OSC48_CC_EN_OFFSET      0xdc
-#define GC_FUSE_RC_TIMER_OSC48_CC_EN_DEFAULT     0x55555550
-#define GC_FUSE_RC_TIMER_OSC48_FC_TRIM_OFFSET    0xe0
-#define GC_FUSE_RC_TIMER_OSC48_FC_TRIM_DEFAULT   0x55555540
-#define GC_FUSE_RC_TIMER_OSC48_FC_EN_OFFSET      0xe4
-#define GC_FUSE_RC_TIMER_OSC48_FC_EN_DEFAULT     0x55555550
-#define GC_FUSE_RC_RTC_OSC256K_CC_TRIM_OFFSET    0xe8
-#define GC_FUSE_RC_RTC_OSC256K_CC_TRIM_DEFAULT   0x55555500
-#define GC_FUSE_RC_RTC_OSC256K_CC_EN_OFFSET      0xec
-#define GC_FUSE_RC_RTC_OSC256K_CC_EN_DEFAULT     0x55555550
-#define GC_FUSE_SEL_VREG_REG_EN_OFFSET           0xf0
-#define GC_FUSE_SEL_VREG_REG_EN_DEFAULT          0x55555550
-#define GC_FUSE_SEL_VREF_REG_OFFSET              0xf4
-#define GC_FUSE_SEL_VREF_REG_DEFAULT             0x55555550
-#define GC_FUSE_SEL_VREF_BATMON_EN_OFFSET        0xf8
-#define GC_FUSE_SEL_VREF_BATMON_EN_DEFAULT       0x55555550
-#define GC_FUSE_SEL_VREF_BATMON_OFFSET           0xfc
-#define GC_FUSE_SEL_VREF_BATMON_DEFAULT          0x55555550
-#define GC_FUSE_X_OSC_LDO_CTRL_EN_OFFSET         0x100
-#define GC_FUSE_X_OSC_LDO_CTRL_EN_DEFAULT        0x55555550
-#define GC_FUSE_X_OSC_LDO_CTRL_OFFSET            0x104
-#define GC_FUSE_X_OSC_LDO_CTRL_DEFAULT           0x55555550
-#define GC_FUSE_TEMP_OFFSET_CAL_OFFSET           0x108
-#define GC_FUSE_TEMP_OFFSET_CAL_DEFAULT          0x55555000
-#define GC_FUSE_TRNG_LDO_CTRL_EN_OFFSET          0x10c
-#define GC_FUSE_TRNG_LDO_CTRL_EN_DEFAULT         0x55555550
-#define GC_FUSE_TRNG_LDO_CTRL_OFFSET             0x110
-#define GC_FUSE_TRNG_LDO_CTRL_DEFAULT            0x55555540
-#define GC_FUSE_TRNG_ANALOG_CTRL_EN_OFFSET       0x114
-#define GC_FUSE_TRNG_ANALOG_CTRL_EN_DEFAULT      0x55555550
-#define GC_FUSE_TRNG_ANALOG_CTRL_OFFSET          0x118
-#define GC_FUSE_TRNG_ANALOG_CTRL_DEFAULT         0x55555550
-#define GC_FUSE_EXT_XTAL_PDB_OFFSET              0x11c
-#define GC_FUSE_EXT_XTAL_PDB_DEFAULT             0x55555554
-#define GC_FUSE_DIS_EXT_XTAL_CLK_TREE_OFFSET     0x120
-#define GC_FUSE_DIS_EXT_XTAL_CLK_TREE_DEFAULT    0x55555550
-#define GC_FUSE_OBFUSCATION_EN_OFFSET            0x124
-#define GC_FUSE_OBFUSCATION_EN_DEFAULT           0x55555550
-#define GC_FUSE_HIK_CREATE_LOCK_OFFSET           0x128
-#define GC_FUSE_HIK_CREATE_LOCK_DEFAULT          0x55555550
-#define GC_FUSE_BNK2_INTG_CHKSUM_OFFSET          0x12c
-#define GC_FUSE_BNK2_INTG_CHKSUM_DEFAULT         0x55000000
-#define GC_FUSE_BNK2_INTG_LOCK_OFFSET            0x130
-#define GC_FUSE_BNK2_INTG_LOCK_DEFAULT           0x55555550
-#define GC_FUSE_TESTMODE_OTPW_DIS_OFFSET         0x134
-#define GC_FUSE_TESTMODE_OTPW_DIS_DEFAULT        0x55555550
-#define GC_FUSE_HKEY_WDOG_TIMER_EN_OFFSET        0x138
-#define GC_FUSE_HKEY_WDOG_TIMER_EN_DEFAULT       0x55555550
-#define GC_FUSE_FLASH_PERSO_PAGE_LOCK_OFFSET     0x13c
-#define GC_FUSE_FLASH_PERSO_PAGE_LOCK_DEFAULT    0x55555550
-#define GC_FUSE_ALERT_RSP_CFG_OFFSET             0x140
-#define GC_FUSE_ALERT_RSP_CFG_DEFAULT            0x55555500
-#define GC_FUSE_BNK3_INTG_CHKSUM_OFFSET          0x144
-#define GC_FUSE_BNK3_INTG_CHKSUM_DEFAULT         0x55000000
-#define GC_FUSE_BNK3_INTG_LOCK_OFFSET            0x148
-#define GC_FUSE_BNK3_INTG_LOCK_DEFAULT           0x55555550
-#define GC_FUSE_FW_DEFINED_DATA_BLK0_OFFSET      0x14c
-#define GC_FUSE_FW_DEFINED_DATA_BLK0_DEFAULT     0x55555500
-#define GC_FUSE_FW_DEFINED_BROM_ERR_RESPONSE_OFFSET 0x150
-#define GC_FUSE_FW_DEFINED_BROM_ERR_RESPONSE_DEFAULT 0x55550000
-#define GC_FUSE_FW_DEFINED_BROM_APPLYSEC_OFFSET  0x154
-#define GC_FUSE_FW_DEFINED_BROM_APPLYSEC_DEFAULT 0x55555000
-#define GC_FUSE_FW_DEFINED_BROM_CONFIG0_OFFSET   0x158
-#define GC_FUSE_FW_DEFINED_BROM_CONFIG0_DEFAULT  0x55555500
-#define GC_FUSE_FW_DEFINED_BROM_CONFIG1_OFFSET   0x15c
-#define GC_FUSE_FW_DEFINED_BROM_CONFIG1_DEFAULT  0x55555500
-#define GC_FUSE_RBOX_MODE_DBG_OVRD_DIS_OFFSET    0x160
-#define GC_FUSE_RBOX_MODE_DBG_OVRD_DIS_DEFAULT   0x55555554
-#define GC_FUSE_RBOX_MODE_OUTPUT_OVRD_DIS_OFFSET 0x164
-#define GC_FUSE_RBOX_MODE_OUTPUT_OVRD_DIS_DEFAULT 0x55555500
-#define GC_FUSE_RBOX_CLK10HZ_COUNT_OFFSET        0x168
-#define GC_FUSE_RBOX_CLK10HZ_COUNT_DEFAULT       0x55550000
-#define GC_FUSE_RBOX_SHORT_DELAY_COUNT_OFFSET    0x16c
-#define GC_FUSE_RBOX_SHORT_DELAY_COUNT_DEFAULT   0x55550000
-#define GC_FUSE_RBOX_LONG_DELAY_COUNT_OFFSET     0x170
-#define GC_FUSE_RBOX_LONG_DELAY_COUNT_DEFAULT    0x55555500
-#define GC_FUSE_RBOX_DEBOUNCE_PERIOD_OFFSET      0x174
-#define GC_FUSE_RBOX_DEBOUNCE_PERIOD_DEFAULT     0x55550000
-#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_PWRB_OFFSET 0x178
-#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_PWRB_DEFAULT 0x55555554
-#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY0_OFFSET 0x17c
-#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY0_DEFAULT 0x55555554
-#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY1_OFFSET 0x180
-#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY1_DEFAULT 0x55555554
-#define GC_FUSE_RBOX_KEY_COMBO0_VAL_OFFSET       0x184
-#define GC_FUSE_RBOX_KEY_COMBO0_VAL_DEFAULT      0x55555500
-#define GC_FUSE_RBOX_KEY_COMBO1_VAL_OFFSET       0x188
-#define GC_FUSE_RBOX_KEY_COMBO1_VAL_DEFAULT      0x55555500
-#define GC_FUSE_RBOX_KEY_COMBO2_VAL_OFFSET       0x18c
-#define GC_FUSE_RBOX_KEY_COMBO2_VAL_DEFAULT      0x55555500
-#define GC_FUSE_RBOX_KEY_COMBO0_HOLD_OFFSET      0x190
-#define GC_FUSE_RBOX_KEY_COMBO0_HOLD_DEFAULT     0x55555500
-#define GC_FUSE_RBOX_KEY_COMBO1_HOLD_OFFSET      0x194
-#define GC_FUSE_RBOX_KEY_COMBO1_HOLD_DEFAULT     0x55555500
-#define GC_FUSE_RBOX_KEY_COMBO2_HOLD_OFFSET      0x198
-#define GC_FUSE_RBOX_KEY_COMBO2_HOLD_DEFAULT     0x55555500
-#define GC_FUSE_RBOX_BLOCK_KEY0_SEL_OFFSET       0x19c
-#define GC_FUSE_RBOX_BLOCK_KEY0_SEL_DEFAULT      0x55555554
-#define GC_FUSE_RBOX_BLOCK_KEY1_SEL_OFFSET       0x1a0
-#define GC_FUSE_RBOX_BLOCK_KEY1_SEL_DEFAULT      0x55555554
-#define GC_FUSE_RBOX_BLOCK_KEY0_VAL_OFFSET       0x1a4
-#define GC_FUSE_RBOX_BLOCK_KEY0_VAL_DEFAULT      0x55555554
-#define GC_FUSE_RBOX_BLOCK_KEY1_VAL_OFFSET       0x1a8
-#define GC_FUSE_RBOX_BLOCK_KEY1_VAL_DEFAULT      0x55555554
-#define GC_FUSE_RBOX_POL_AC_PRESENT_OFFSET       0x1ac
-#define GC_FUSE_RBOX_POL_AC_PRESENT_DEFAULT      0x55555554
-#define GC_FUSE_RBOX_POL_PWRB_IN_OFFSET          0x1b0
-#define GC_FUSE_RBOX_POL_PWRB_IN_DEFAULT         0x55555554
-#define GC_FUSE_RBOX_POL_PWRB_OUT_OFFSET         0x1b4
-#define GC_FUSE_RBOX_POL_PWRB_OUT_DEFAULT        0x55555554
-#define GC_FUSE_RBOX_POL_KEY0_IN_OFFSET          0x1b8
-#define GC_FUSE_RBOX_POL_KEY0_IN_DEFAULT         0x55555554
-#define GC_FUSE_RBOX_POL_KEY0_OUT_OFFSET         0x1bc
-#define GC_FUSE_RBOX_POL_KEY0_OUT_DEFAULT        0x55555554
-#define GC_FUSE_RBOX_POL_KEY1_IN_OFFSET          0x1c0
-#define GC_FUSE_RBOX_POL_KEY1_IN_DEFAULT         0x55555554
-#define GC_FUSE_RBOX_POL_KEY1_OUT_OFFSET         0x1c4
-#define GC_FUSE_RBOX_POL_KEY1_OUT_DEFAULT        0x55555554
-#define GC_FUSE_RBOX_POL_EC_RST_OFFSET           0x1c8
-#define GC_FUSE_RBOX_POL_EC_RST_DEFAULT          0x55555554
-#define GC_FUSE_RBOX_POL_BATT_DISABLE_OFFSET     0x1cc
-#define GC_FUSE_RBOX_POL_BATT_DISABLE_DEFAULT    0x55555554
-#define GC_FUSE_RBOX_TERM_AC_PRESENT_OFFSET      0x1d0
-#define GC_FUSE_RBOX_TERM_AC_PRESENT_DEFAULT     0x55555554
-#define GC_FUSE_RBOX_TERM_ENTERING_RW_OFFSET     0x1d4
-#define GC_FUSE_RBOX_TERM_ENTERING_RW_DEFAULT    0x55555554
-#define GC_FUSE_RBOX_TERM_PWRB_IN_OFFSET         0x1d8
-#define GC_FUSE_RBOX_TERM_PWRB_IN_DEFAULT        0x55555554
-#define GC_FUSE_RBOX_TERM_PWRB_OUT_OFFSET        0x1dc
-#define GC_FUSE_RBOX_TERM_PWRB_OUT_DEFAULT       0x55555554
-#define GC_FUSE_RBOX_TERM_KEY0_IN_OFFSET         0x1e0
-#define GC_FUSE_RBOX_TERM_KEY0_IN_DEFAULT        0x55555554
-#define GC_FUSE_RBOX_TERM_KEY0_OUT_OFFSET        0x1e4
-#define GC_FUSE_RBOX_TERM_KEY0_OUT_DEFAULT       0x55555554
-#define GC_FUSE_RBOX_TERM_KEY1_IN_OFFSET         0x1e8
-#define GC_FUSE_RBOX_TERM_KEY1_IN_DEFAULT        0x55555554
-#define GC_FUSE_RBOX_TERM_KEY1_OUT_OFFSET        0x1ec
-#define GC_FUSE_RBOX_TERM_KEY1_OUT_DEFAULT       0x55555554
-#define GC_FUSE_RBOX_DRIVE_PWRB_OUT_OFFSET       0x1f0
-#define GC_FUSE_RBOX_DRIVE_PWRB_OUT_DEFAULT      0x55555554
-#define GC_FUSE_RBOX_DRIVE_KEY0_OUT_OFFSET       0x1f4
-#define GC_FUSE_RBOX_DRIVE_KEY0_OUT_DEFAULT      0x55555554
-#define GC_FUSE_RBOX_DRIVE_KEY1_OUT_OFFSET       0x1f8
-#define GC_FUSE_RBOX_DRIVE_KEY1_OUT_DEFAULT      0x55555554
-#define GC_FUSE_RBOX_DRIVE_EC_RST_OFFSET         0x1fc
-#define GC_FUSE_RBOX_DRIVE_EC_RST_DEFAULT        0x55555554
-#define GC_FUSE_RBOX_DRIVE_BATT_DISABLE_OFFSET   0x200
-#define GC_FUSE_RBOX_DRIVE_BATT_DISABLE_DEFAULT  0x55555554
-#define GC_FUSE_BNK4_INTG_CHKSUM_OFFSET          0x204
-#define GC_FUSE_BNK4_INTG_CHKSUM_DEFAULT         0x55000000
-#define GC_FUSE_BNK4_INTG_LOCK_OFFSET            0x208
-#define GC_FUSE_BNK4_INTG_LOCK_DEFAULT           0x55555550
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK0_OFFSET 0x20c
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK0_DEFAULT 0x55555500
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK1_OFFSET 0x210
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK1_DEFAULT 0x55555500
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK2_OFFSET 0x214
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK2_DEFAULT 0x55555500
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK3_OFFSET 0x218
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK3_DEFAULT 0x55555500
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK4_OFFSET 0x21c
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK4_DEFAULT 0x55555500
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK5_OFFSET 0x220
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK5_DEFAULT 0x55555500
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK6_OFFSET 0x224
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK6_DEFAULT 0x55555540
-#define GC_FUSE_PROG_BNK0_INTG_CHKSUM_OFFSET     0x228
-#define GC_FUSE_PROG_BNK0_INTG_CHKSUM_DEFAULT    0x0
-#define GC_FUSE_PROG_BNK0_INTG_LOCK_OFFSET       0x22c
-#define GC_FUSE_PROG_BNK0_INTG_LOCK_DEFAULT      0x0
-#define GC_FUSE_PROG_DS_GRP0_OFFSET              0x230
-#define GC_FUSE_PROG_DS_GRP0_DEFAULT             0x0
-#define GC_FUSE_PROG_DS_GRP1_OFFSET              0x234
-#define GC_FUSE_PROG_DS_GRP1_DEFAULT             0x0
-#define GC_FUSE_PROG_DS_GRP2_OFFSET              0x238
-#define GC_FUSE_PROG_DS_GRP2_DEFAULT             0x0
-#define GC_FUSE_PROG_DEV_ID0_OFFSET              0x23c
-#define GC_FUSE_PROG_DEV_ID0_DEFAULT             0x0
-#define GC_FUSE_PROG_DEV_ID1_OFFSET              0x240
-#define GC_FUSE_PROG_DEV_ID1_DEFAULT             0x0
-#define GC_FUSE_PROG_BNK1_INTG_CHKSUM_OFFSET     0x244
-#define GC_FUSE_PROG_BNK1_INTG_CHKSUM_DEFAULT    0x0
-#define GC_FUSE_PROG_BNK1_INTG_LOCK_OFFSET       0x248
-#define GC_FUSE_PROG_BNK1_INTG_LOCK_DEFAULT      0x0
-#define GC_FUSE_PROG_LB0_POST_OVRD_OFFSET        0x24c
-#define GC_FUSE_PROG_LB0_POST_OVRD_DEFAULT       0x0
-#define GC_FUSE_PROG_LB0_POST_PATCNT_OFFSET      0x250
-#define GC_FUSE_PROG_LB0_POST_PATCNT_DEFAULT     0x0
-#define GC_FUSE_PROG_LB0_POST_WARMUP_OVRD_OFFSET 0x254
-#define GC_FUSE_PROG_LB0_POST_WARMUP_OVRD_DEFAULT 0x0
-#define GC_FUSE_PROG_LB0_POST_WARMUP_CNT_OFFSET  0x258
-#define GC_FUSE_PROG_LB0_POST_WARMUP_CNT_DEFAULT 0x0
-#define GC_FUSE_PROG_LB1_POST_OVRD_OFFSET        0x25c
-#define GC_FUSE_PROG_LB1_POST_OVRD_DEFAULT       0x0
-#define GC_FUSE_PROG_LB1_POST_PATCNT_OFFSET      0x260
-#define GC_FUSE_PROG_LB1_POST_PATCNT_DEFAULT     0x0
-#define GC_FUSE_PROG_LB1_POST_WARMUP_OVRD_OFFSET 0x264
-#define GC_FUSE_PROG_LB1_POST_WARMUP_OVRD_DEFAULT 0x0
-#define GC_FUSE_PROG_LB1_POST_WARMUP_CNT_OFFSET  0x268
-#define GC_FUSE_PROG_LB1_POST_WARMUP_CNT_DEFAULT 0x0
-#define GC_FUSE_PROG_LB2_POST_OVRD_OFFSET        0x26c
-#define GC_FUSE_PROG_LB2_POST_OVRD_DEFAULT       0x0
-#define GC_FUSE_PROG_LB2_POST_PATCNT_OFFSET      0x270
-#define GC_FUSE_PROG_LB2_POST_PATCNT_DEFAULT     0x0
-#define GC_FUSE_PROG_LB2_POST_WARMUP_OVRD_OFFSET 0x274
-#define GC_FUSE_PROG_LB2_POST_WARMUP_OVRD_DEFAULT 0x0
-#define GC_FUSE_PROG_LB2_POST_WARMUP_CNT_OFFSET  0x278
-#define GC_FUSE_PROG_LB2_POST_WARMUP_CNT_DEFAULT 0x0
-#define GC_FUSE_PROG_LB3_POST_OVRD_OFFSET        0x27c
-#define GC_FUSE_PROG_LB3_POST_OVRD_DEFAULT       0x0
-#define GC_FUSE_PROG_LB3_POST_PATCNT_OFFSET      0x280
-#define GC_FUSE_PROG_LB3_POST_PATCNT_DEFAULT     0x0
-#define GC_FUSE_PROG_LB3_POST_WARMUP_OVRD_OFFSET 0x284
-#define GC_FUSE_PROG_LB3_POST_WARMUP_OVRD_DEFAULT 0x0
-#define GC_FUSE_PROG_LB3_POST_WARMUP_CNT_OFFSET  0x288
-#define GC_FUSE_PROG_LB3_POST_WARMUP_CNT_DEFAULT 0x0
-#define GC_FUSE_PROG_LB4_POST_OVRD_OFFSET        0x28c
-#define GC_FUSE_PROG_LB4_POST_OVRD_DEFAULT       0x0
-#define GC_FUSE_PROG_LB4_POST_PATCNT_OFFSET      0x290
-#define GC_FUSE_PROG_LB4_POST_PATCNT_DEFAULT     0x0
-#define GC_FUSE_PROG_LB4_POST_WARMUP_OVRD_OFFSET 0x294
-#define GC_FUSE_PROG_LB4_POST_WARMUP_OVRD_DEFAULT 0x0
-#define GC_FUSE_PROG_LB4_POST_WARMUP_CNT_OFFSET  0x298
-#define GC_FUSE_PROG_LB4_POST_WARMUP_CNT_DEFAULT 0x0
-#define GC_FUSE_PROG_MBIST_POST_SEQ_OFFSET       0x29c
-#define GC_FUSE_PROG_MBIST_POST_SEQ_DEFAULT      0x0
-#define GC_FUSE_PROG_LBIST_POST_SEQ_OFFSET       0x2a0
-#define GC_FUSE_PROG_LBIST_POST_SEQ_DEFAULT      0x0
-#define GC_FUSE_PROG_LBIST_VIA_TAP_DIS_OFFSET    0x2a4
-#define GC_FUSE_PROG_LBIST_VIA_TAP_DIS_DEFAULT   0x0
-#define GC_FUSE_PROG_MBIST_VIA_TAP_DIS_OFFSET    0x2a8
-#define GC_FUSE_PROG_MBIST_VIA_TAP_DIS_DEFAULT   0x0
-#define GC_FUSE_PROG_MBIST_BOOTROM_MISR_EN_OFFSET 0x2ac
-#define GC_FUSE_PROG_MBIST_BOOTROM_MISR_EN_DEFAULT 0x0
-#define GC_FUSE_PROG_MBIST_BOOTROM_MISR_OFFSET   0x2b0
-#define GC_FUSE_PROG_MBIST_BOOTROM_MISR_DEFAULT  0x0
-#define GC_FUSE_PROG_TAP_DISABLE_OFFSET          0x2b4
-#define GC_FUSE_PROG_TAP_DISABLE_DEFAULT         0x0
-#define GC_FUSE_PROG_RNGBIST_AR_EN_OFFSET        0x2b8
-#define GC_FUSE_PROG_RNGBIST_AR_EN_DEFAULT       0x0
-#define GC_FUSE_PROG_TESTMODE_KEYS_EN_OFFSET     0x2bc
-#define GC_FUSE_PROG_TESTMODE_KEYS_EN_DEFAULT    0x0
-#define GC_FUSE_PROG_PKG_ID_OFFSET               0x2c0
-#define GC_FUSE_PROG_PKG_ID_DEFAULT              0x0
-#define GC_FUSE_PROG_BIN_ID_OFFSET               0x2c4
-#define GC_FUSE_PROG_BIN_ID_DEFAULT              0x0
-#define GC_FUSE_PROG_RC_JTR_OSC48_CC_TRIM_OFFSET 0x2c8
-#define GC_FUSE_PROG_RC_JTR_OSC48_CC_TRIM_DEFAULT 0x0
-#define GC_FUSE_PROG_RC_JTR_OSC48_CC_EN_OFFSET   0x2cc
-#define GC_FUSE_PROG_RC_JTR_OSC48_CC_EN_DEFAULT  0x0
-#define GC_FUSE_PROG_RC_JTR_OSC60_CC_TRIM_OFFSET 0x2d0
-#define GC_FUSE_PROG_RC_JTR_OSC60_CC_TRIM_DEFAULT 0x0
-#define GC_FUSE_PROG_RC_JTR_OSC60_CC_EN_OFFSET   0x2d4
-#define GC_FUSE_PROG_RC_JTR_OSC60_CC_EN_DEFAULT  0x0
-#define GC_FUSE_PROG_RC_TIMER_OSC48_CC_TRIM_OFFSET 0x2d8
-#define GC_FUSE_PROG_RC_TIMER_OSC48_CC_TRIM_DEFAULT 0x0
-#define GC_FUSE_PROG_RC_TIMER_OSC48_CC_EN_OFFSET 0x2dc
-#define GC_FUSE_PROG_RC_TIMER_OSC48_CC_EN_DEFAULT 0x0
-#define GC_FUSE_PROG_RC_TIMER_OSC48_FC_TRIM_OFFSET 0x2e0
-#define GC_FUSE_PROG_RC_TIMER_OSC48_FC_TRIM_DEFAULT 0x0
-#define GC_FUSE_PROG_RC_TIMER_OSC48_FC_EN_OFFSET 0x2e4
-#define GC_FUSE_PROG_RC_TIMER_OSC48_FC_EN_DEFAULT 0x0
-#define GC_FUSE_PROG_RC_RTC_OSC256K_CC_TRIM_OFFSET 0x2e8
-#define GC_FUSE_PROG_RC_RTC_OSC256K_CC_TRIM_DEFAULT 0x0
-#define GC_FUSE_PROG_RC_RTC_OSC256K_CC_EN_OFFSET 0x2ec
-#define GC_FUSE_PROG_RC_RTC_OSC256K_CC_EN_DEFAULT 0x0
-#define GC_FUSE_PROG_SEL_VREG_REG_EN_OFFSET      0x2f0
-#define GC_FUSE_PROG_SEL_VREG_REG_EN_DEFAULT     0x0
-#define GC_FUSE_PROG_SEL_VREF_REG_OFFSET         0x2f4
-#define GC_FUSE_PROG_SEL_VREF_REG_DEFAULT        0x0
-#define GC_FUSE_PROG_SEL_VREF_BATMON_EN_OFFSET   0x2f8
-#define GC_FUSE_PROG_SEL_VREF_BATMON_EN_DEFAULT  0x0
-#define GC_FUSE_PROG_SEL_VREF_BATMON_OFFSET      0x2fc
-#define GC_FUSE_PROG_SEL_VREF_BATMON_DEFAULT     0x0
-#define GC_FUSE_PROG_X_OSC_LDO_CTRL_EN_OFFSET    0x300
-#define GC_FUSE_PROG_X_OSC_LDO_CTRL_EN_DEFAULT   0x0
-#define GC_FUSE_PROG_X_OSC_LDO_CTRL_OFFSET       0x304
-#define GC_FUSE_PROG_X_OSC_LDO_CTRL_DEFAULT      0x0
-#define GC_FUSE_PROG_TEMP_OFFSET_CAL_OFFSET      0x308
-#define GC_FUSE_PROG_TEMP_OFFSET_CAL_DEFAULT     0x0
-#define GC_FUSE_PROG_TRNG_LDO_CTRL_EN_OFFSET     0x30c
-#define GC_FUSE_PROG_TRNG_LDO_CTRL_EN_DEFAULT    0x0
-#define GC_FUSE_PROG_TRNG_LDO_CTRL_OFFSET        0x310
-#define GC_FUSE_PROG_TRNG_LDO_CTRL_DEFAULT       0x0
-#define GC_FUSE_PROG_TRNG_ANALOG_CTRL_EN_OFFSET  0x314
-#define GC_FUSE_PROG_TRNG_ANALOG_CTRL_EN_DEFAULT 0x0
-#define GC_FUSE_PROG_TRNG_ANALOG_CTRL_OFFSET     0x318
-#define GC_FUSE_PROG_TRNG_ANALOG_CTRL_DEFAULT    0x0
-#define GC_FUSE_PROG_EXT_XTAL_PDB_OFFSET         0x31c
-#define GC_FUSE_PROG_EXT_XTAL_PDB_DEFAULT        0x0
-#define GC_FUSE_PROG_DIS_EXT_XTAL_CLK_TREE_OFFSET 0x320
-#define GC_FUSE_PROG_DIS_EXT_XTAL_CLK_TREE_DEFAULT 0x0
-#define GC_FUSE_PROG_OBFUSCATION_EN_OFFSET       0x324
-#define GC_FUSE_PROG_OBFUSCATION_EN_DEFAULT      0x0
-#define GC_FUSE_PROG_OBS0_OFFSET                 0x328
-#define GC_FUSE_PROG_OBS0_DEFAULT                0x0
-#define GC_FUSE_PROG_OBS1_OFFSET                 0x32c
-#define GC_FUSE_PROG_OBS1_DEFAULT                0x0
-#define GC_FUSE_PROG_OBS2_OFFSET                 0x330
-#define GC_FUSE_PROG_OBS2_DEFAULT                0x0
-#define GC_FUSE_PROG_OBS3_OFFSET                 0x334
-#define GC_FUSE_PROG_OBS3_DEFAULT                0x0
-#define GC_FUSE_PROG_OBS4_OFFSET                 0x338
-#define GC_FUSE_PROG_OBS4_DEFAULT                0x0
-#define GC_FUSE_PROG_OBS5_OFFSET                 0x33c
-#define GC_FUSE_PROG_OBS5_DEFAULT                0x0
-#define GC_FUSE_PROG_OBS6_OFFSET                 0x340
-#define GC_FUSE_PROG_OBS6_DEFAULT                0x0
-#define GC_FUSE_PROG_OBS7_OFFSET                 0x344
-#define GC_FUSE_PROG_OBS7_DEFAULT                0x0
-#define GC_FUSE_PROG_HIK_CREATE_LOCK_OFFSET      0x348
-#define GC_FUSE_PROG_HIK_CREATE_LOCK_DEFAULT     0x0
-#define GC_FUSE_PROG_BNK2_INTG_CHKSUM_OFFSET     0x34c
-#define GC_FUSE_PROG_BNK2_INTG_CHKSUM_DEFAULT    0x0
-#define GC_FUSE_PROG_BNK2_INTG_LOCK_OFFSET       0x350
-#define GC_FUSE_PROG_BNK2_INTG_LOCK_DEFAULT      0x0
-#define GC_FUSE_PROG_TESTMODE_OTPW_DIS_OFFSET    0x354
-#define GC_FUSE_PROG_TESTMODE_OTPW_DIS_DEFAULT   0x0
-#define GC_FUSE_PROG_HKEY_WDOG_TIMER_EN_OFFSET   0x358
-#define GC_FUSE_PROG_HKEY_WDOG_TIMER_EN_DEFAULT  0x0
-#define GC_FUSE_PROG_FLASH_PERSO_PAGE_LOCK_OFFSET 0x35c
-#define GC_FUSE_PROG_FLASH_PERSO_PAGE_LOCK_DEFAULT 0x0
-#define GC_FUSE_PROG_ALERT_RSP_CFG_OFFSET        0x360
-#define GC_FUSE_PROG_ALERT_RSP_CFG_DEFAULT       0x0
-#define GC_FUSE_PROG_BNK3_INTG_CHKSUM_OFFSET     0x364
-#define GC_FUSE_PROG_BNK3_INTG_CHKSUM_DEFAULT    0x0
-#define GC_FUSE_PROG_BNK3_INTG_LOCK_OFFSET       0x368
-#define GC_FUSE_PROG_BNK3_INTG_LOCK_DEFAULT      0x0
-#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK0_OFFSET 0x36c
-#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK0_DEFAULT 0x0
-#define GC_FUSE_PROG_FW_DEFINED_BROM_ERR_RESPONSE_OFFSET 0x370
-#define GC_FUSE_PROG_FW_DEFINED_BROM_ERR_RESPONSE_DEFAULT 0x0
-#define GC_FUSE_PROG_FW_DEFINED_BROM_APPLYSEC_OFFSET 0x374
-#define GC_FUSE_PROG_FW_DEFINED_BROM_APPLYSEC_DEFAULT 0x0
-#define GC_FUSE_PROG_FW_DEFINED_BROM_CONFIG0_OFFSET 0x378
-#define GC_FUSE_PROG_FW_DEFINED_BROM_CONFIG0_DEFAULT 0x0
-#define GC_FUSE_PROG_FW_DEFINED_BROM_CONFIG1_OFFSET 0x37c
-#define GC_FUSE_PROG_FW_DEFINED_BROM_CONFIG1_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_MODE_DBG_OVRD_DIS_OFFSET 0x380
-#define GC_FUSE_PROG_RBOX_MODE_DBG_OVRD_DIS_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_MODE_OUTPUT_OVRD_DIS_OFFSET 0x384
-#define GC_FUSE_PROG_RBOX_MODE_OUTPUT_OVRD_DIS_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_CLK10HZ_COUNT_OFFSET   0x388
-#define GC_FUSE_PROG_RBOX_CLK10HZ_COUNT_DEFAULT  0x0
-#define GC_FUSE_PROG_RBOX_SHORT_DELAY_COUNT_OFFSET 0x38c
-#define GC_FUSE_PROG_RBOX_SHORT_DELAY_COUNT_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_LONG_DELAY_COUNT_OFFSET 0x390
-#define GC_FUSE_PROG_RBOX_LONG_DELAY_COUNT_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_DEBOUNCE_PERIOD_OFFSET 0x394
-#define GC_FUSE_PROG_RBOX_DEBOUNCE_PERIOD_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_PWRB_OFFSET 0x398
-#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_PWRB_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY0_OFFSET 0x39c
-#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY0_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY1_OFFSET 0x3a0
-#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY1_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_KEY_COMBO0_VAL_OFFSET  0x3a4
-#define GC_FUSE_PROG_RBOX_KEY_COMBO0_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_KEY_COMBO1_VAL_OFFSET  0x3a8
-#define GC_FUSE_PROG_RBOX_KEY_COMBO1_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_KEY_COMBO2_VAL_OFFSET  0x3ac
-#define GC_FUSE_PROG_RBOX_KEY_COMBO2_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_KEY_COMBO0_HOLD_OFFSET 0x3b0
-#define GC_FUSE_PROG_RBOX_KEY_COMBO0_HOLD_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_KEY_COMBO1_HOLD_OFFSET 0x3b4
-#define GC_FUSE_PROG_RBOX_KEY_COMBO1_HOLD_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_KEY_COMBO2_HOLD_OFFSET 0x3b8
-#define GC_FUSE_PROG_RBOX_KEY_COMBO2_HOLD_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_BLOCK_KEY0_SEL_OFFSET  0x3bc
-#define GC_FUSE_PROG_RBOX_BLOCK_KEY0_SEL_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_BLOCK_KEY1_SEL_OFFSET  0x3c0
-#define GC_FUSE_PROG_RBOX_BLOCK_KEY1_SEL_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_BLOCK_KEY0_VAL_OFFSET  0x3c4
-#define GC_FUSE_PROG_RBOX_BLOCK_KEY0_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_BLOCK_KEY1_VAL_OFFSET  0x3c8
-#define GC_FUSE_PROG_RBOX_BLOCK_KEY1_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_POL_AC_PRESENT_OFFSET  0x3cc
-#define GC_FUSE_PROG_RBOX_POL_AC_PRESENT_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_POL_PWRB_IN_OFFSET     0x3d0
-#define GC_FUSE_PROG_RBOX_POL_PWRB_IN_DEFAULT    0x0
-#define GC_FUSE_PROG_RBOX_POL_PWRB_OUT_OFFSET    0x3d4
-#define GC_FUSE_PROG_RBOX_POL_PWRB_OUT_DEFAULT   0x0
-#define GC_FUSE_PROG_RBOX_POL_KEY0_IN_OFFSET     0x3d8
-#define GC_FUSE_PROG_RBOX_POL_KEY0_IN_DEFAULT    0x0
-#define GC_FUSE_PROG_RBOX_POL_KEY0_OUT_OFFSET    0x3dc
-#define GC_FUSE_PROG_RBOX_POL_KEY0_OUT_DEFAULT   0x0
-#define GC_FUSE_PROG_RBOX_POL_KEY1_IN_OFFSET     0x3e0
-#define GC_FUSE_PROG_RBOX_POL_KEY1_IN_DEFAULT    0x0
-#define GC_FUSE_PROG_RBOX_POL_KEY1_OUT_OFFSET    0x3e4
-#define GC_FUSE_PROG_RBOX_POL_KEY1_OUT_DEFAULT   0x0
-#define GC_FUSE_PROG_RBOX_POL_EC_RST_OFFSET      0x3e8
-#define GC_FUSE_PROG_RBOX_POL_EC_RST_DEFAULT     0x0
-#define GC_FUSE_PROG_RBOX_POL_BATT_DISABLE_OFFSET 0x3ec
-#define GC_FUSE_PROG_RBOX_POL_BATT_DISABLE_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_TERM_AC_PRESENT_OFFSET 0x3f0
-#define GC_FUSE_PROG_RBOX_TERM_AC_PRESENT_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_TERM_ENTERING_RW_OFFSET 0x3f4
-#define GC_FUSE_PROG_RBOX_TERM_ENTERING_RW_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_TERM_PWRB_IN_OFFSET    0x3f8
-#define GC_FUSE_PROG_RBOX_TERM_PWRB_IN_DEFAULT   0x0
-#define GC_FUSE_PROG_RBOX_TERM_PWRB_OUT_OFFSET   0x3fc
-#define GC_FUSE_PROG_RBOX_TERM_PWRB_OUT_DEFAULT  0x0
-#define GC_FUSE_PROG_RBOX_TERM_KEY0_IN_OFFSET    0x400
-#define GC_FUSE_PROG_RBOX_TERM_KEY0_IN_DEFAULT   0x0
-#define GC_FUSE_PROG_RBOX_TERM_KEY0_OUT_OFFSET   0x404
-#define GC_FUSE_PROG_RBOX_TERM_KEY0_OUT_DEFAULT  0x0
-#define GC_FUSE_PROG_RBOX_TERM_KEY1_IN_OFFSET    0x408
-#define GC_FUSE_PROG_RBOX_TERM_KEY1_IN_DEFAULT   0x0
-#define GC_FUSE_PROG_RBOX_TERM_KEY1_OUT_OFFSET   0x40c
-#define GC_FUSE_PROG_RBOX_TERM_KEY1_OUT_DEFAULT  0x0
-#define GC_FUSE_PROG_RBOX_DRIVE_PWRB_OUT_OFFSET  0x410
-#define GC_FUSE_PROG_RBOX_DRIVE_PWRB_OUT_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_DRIVE_KEY0_OUT_OFFSET  0x414
-#define GC_FUSE_PROG_RBOX_DRIVE_KEY0_OUT_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_DRIVE_KEY1_OUT_OFFSET  0x418
-#define GC_FUSE_PROG_RBOX_DRIVE_KEY1_OUT_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_DRIVE_EC_RST_OFFSET    0x41c
-#define GC_FUSE_PROG_RBOX_DRIVE_EC_RST_DEFAULT   0x0
-#define GC_FUSE_PROG_RBOX_DRIVE_BATT_DISABLE_OFFSET 0x420
-#define GC_FUSE_PROG_RBOX_DRIVE_BATT_DISABLE_DEFAULT 0x0
-#define GC_FUSE_PROG_BNK4_INTG_CHKSUM_OFFSET     0x424
-#define GC_FUSE_PROG_BNK4_INTG_CHKSUM_DEFAULT    0x0
-#define GC_FUSE_PROG_BNK4_INTG_LOCK_OFFSET       0x428
-#define GC_FUSE_PROG_BNK4_INTG_LOCK_DEFAULT      0x0
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK0_OFFSET 0x42c
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK0_DEFAULT 0x0
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK1_OFFSET 0x430
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK1_DEFAULT 0x0
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK2_OFFSET 0x434
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK2_DEFAULT 0x0
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK3_OFFSET 0x438
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK3_DEFAULT 0x0
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK4_OFFSET 0x43c
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK4_DEFAULT 0x0
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK5_OFFSET 0x440
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK5_DEFAULT 0x0
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK6_OFFSET 0x444
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK6_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_D_REGION0_CTRL_OFFSET  0x0
-#define GC_GLOBALSEC_CPU0_D_REGION0_CTRL_DEFAULT 0x7
-#define GC_GLOBALSEC_CPU0_D_REGION1_CTRL_OFFSET  0x4
-#define GC_GLOBALSEC_CPU0_D_REGION1_CTRL_DEFAULT 0x7
-#define GC_GLOBALSEC_CPU0_D_REGION2_CTRL_OFFSET  0x8
-#define GC_GLOBALSEC_CPU0_D_REGION2_CTRL_DEFAULT 0x7
-#define GC_GLOBALSEC_CPU0_D_REGION3_CTRL_OFFSET  0xc
-#define GC_GLOBALSEC_CPU0_D_REGION3_CTRL_DEFAULT 0x7
-#define GC_GLOBALSEC_CPU0_D_REGION4_CTRL_OFFSET  0x10
-#define GC_GLOBALSEC_CPU0_D_REGION4_CTRL_DEFAULT 0x7
-#define GC_GLOBALSEC_CPU0_D_REGION5_CTRL_OFFSET  0x14
-#define GC_GLOBALSEC_CPU0_D_REGION5_CTRL_DEFAULT 0x7
-#define GC_GLOBALSEC_CPU0_D_REGION6_CTRL_OFFSET  0x18
-#define GC_GLOBALSEC_CPU0_D_REGION6_CTRL_DEFAULT 0x7
-#define GC_GLOBALSEC_CPU0_D_REGION7_CTRL_OFFSET  0x1c
-#define GC_GLOBALSEC_CPU0_D_REGION7_CTRL_DEFAULT 0x7
-#define GC_GLOBALSEC_CPU0_D_REGION0_CTRL_CFG_EN_OFFSET 0x20
-#define GC_GLOBALSEC_CPU0_D_REGION0_CTRL_CFG_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION1_CTRL_CFG_EN_OFFSET 0x24
-#define GC_GLOBALSEC_CPU0_D_REGION1_CTRL_CFG_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION2_CTRL_CFG_EN_OFFSET 0x28
-#define GC_GLOBALSEC_CPU0_D_REGION2_CTRL_CFG_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION3_CTRL_CFG_EN_OFFSET 0x2c
-#define GC_GLOBALSEC_CPU0_D_REGION3_CTRL_CFG_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION4_CTRL_CFG_EN_OFFSET 0x30
-#define GC_GLOBALSEC_CPU0_D_REGION4_CTRL_CFG_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION5_CTRL_CFG_EN_OFFSET 0x34
-#define GC_GLOBALSEC_CPU0_D_REGION5_CTRL_CFG_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION6_CTRL_CFG_EN_OFFSET 0x38
-#define GC_GLOBALSEC_CPU0_D_REGION6_CTRL_CFG_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION7_CTRL_CFG_EN_OFFSET 0x3c
-#define GC_GLOBALSEC_CPU0_D_REGION7_CTRL_CFG_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_CTRL_OFFSET 0x40
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_CTRL_DEFAULT 0x7
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_CTRL_OFFSET 0x44
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_CTRL_DEFAULT 0x7
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_CTRL_OFFSET 0x48
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_CTRL_DEFAULT 0x7
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_CTRL_OFFSET 0x4c
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_CTRL_DEFAULT 0x7
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_CTRL_CFG_EN_OFFSET 0x50
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_CTRL_CFG_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_CTRL_CFG_EN_OFFSET 0x54
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_CTRL_CFG_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_CTRL_CFG_EN_OFFSET 0x58
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_CTRL_CFG_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_CTRL_CFG_EN_OFFSET 0x5c
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_CTRL_CFG_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_CPU0_I_REGION0_CTRL_OFFSET  0x60
-#define GC_GLOBALSEC_CPU0_I_REGION0_CTRL_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_REGION1_CTRL_OFFSET  0x64
-#define GC_GLOBALSEC_CPU0_I_REGION1_CTRL_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_REGION2_CTRL_OFFSET  0x68
-#define GC_GLOBALSEC_CPU0_I_REGION2_CTRL_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_REGION3_CTRL_OFFSET  0x6c
-#define GC_GLOBALSEC_CPU0_I_REGION3_CTRL_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_REGION4_CTRL_OFFSET  0x70
-#define GC_GLOBALSEC_CPU0_I_REGION4_CTRL_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_REGION5_CTRL_OFFSET  0x74
-#define GC_GLOBALSEC_CPU0_I_REGION5_CTRL_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_REGION6_CTRL_OFFSET  0x78
-#define GC_GLOBALSEC_CPU0_I_REGION6_CTRL_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_REGION7_CTRL_OFFSET  0x7c
-#define GC_GLOBALSEC_CPU0_I_REGION7_CTRL_DEFAULT 0x0
-#define GC_GLOBALSEC_DDMA0_REGION0_CTRL_OFFSET   0x80
-#define GC_GLOBALSEC_DDMA0_REGION0_CTRL_DEFAULT  0x0
-#define GC_GLOBALSEC_DDMA0_REGION1_CTRL_OFFSET   0x84
-#define GC_GLOBALSEC_DDMA0_REGION1_CTRL_DEFAULT  0x0
-#define GC_GLOBALSEC_DDMA0_REGION2_CTRL_OFFSET   0x88
-#define GC_GLOBALSEC_DDMA0_REGION2_CTRL_DEFAULT  0x0
-#define GC_GLOBALSEC_DDMA0_REGION3_CTRL_OFFSET   0x8c
-#define GC_GLOBALSEC_DDMA0_REGION3_CTRL_DEFAULT  0x0
-#define GC_GLOBALSEC_DDMA0_REGION0_CTRL_CFG_EN_OFFSET 0x90
-#define GC_GLOBALSEC_DDMA0_REGION0_CTRL_CFG_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_DDMA0_REGION1_CTRL_CFG_EN_OFFSET 0x94
-#define GC_GLOBALSEC_DDMA0_REGION1_CTRL_CFG_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_DDMA0_REGION2_CTRL_CFG_EN_OFFSET 0x98
-#define GC_GLOBALSEC_DDMA0_REGION2_CTRL_CFG_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_DDMA0_REGION3_CTRL_CFG_EN_OFFSET 0x9c
-#define GC_GLOBALSEC_DDMA0_REGION3_CTRL_CFG_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_DSPS0_REGION0_CTRL_OFFSET   0xa0
-#define GC_GLOBALSEC_DSPS0_REGION0_CTRL_DEFAULT  0x0
-#define GC_GLOBALSEC_DSPS0_REGION1_CTRL_OFFSET   0xa4
-#define GC_GLOBALSEC_DSPS0_REGION1_CTRL_DEFAULT  0x0
-#define GC_GLOBALSEC_DSPS0_REGION2_CTRL_OFFSET   0xa8
-#define GC_GLOBALSEC_DSPS0_REGION2_CTRL_DEFAULT  0x0
-#define GC_GLOBALSEC_DSPS0_REGION3_CTRL_OFFSET   0xac
-#define GC_GLOBALSEC_DSPS0_REGION3_CTRL_DEFAULT  0x0
-#define GC_GLOBALSEC_DSPS0_REGION0_CTRL_CFG_EN_OFFSET 0xb0
-#define GC_GLOBALSEC_DSPS0_REGION0_CTRL_CFG_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_DSPS0_REGION1_CTRL_CFG_EN_OFFSET 0xb4
-#define GC_GLOBALSEC_DSPS0_REGION1_CTRL_CFG_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_DSPS0_REGION2_CTRL_CFG_EN_OFFSET 0xb8
-#define GC_GLOBALSEC_DSPS0_REGION2_CTRL_CFG_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_DSPS0_REGION3_CTRL_CFG_EN_OFFSET 0xbc
-#define GC_GLOBALSEC_DSPS0_REGION3_CTRL_CFG_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_DUSB0_REGION0_CTRL_OFFSET   0xc0
-#define GC_GLOBALSEC_DUSB0_REGION0_CTRL_DEFAULT  0x0
-#define GC_GLOBALSEC_DUSB0_REGION1_CTRL_OFFSET   0xc4
-#define GC_GLOBALSEC_DUSB0_REGION1_CTRL_DEFAULT  0x0
-#define GC_GLOBALSEC_DUSB0_REGION2_CTRL_OFFSET   0xc8
-#define GC_GLOBALSEC_DUSB0_REGION2_CTRL_DEFAULT  0x0
-#define GC_GLOBALSEC_DUSB0_REGION3_CTRL_OFFSET   0xcc
-#define GC_GLOBALSEC_DUSB0_REGION3_CTRL_DEFAULT  0x0
-#define GC_GLOBALSEC_DUSB0_REGION0_CTRL_CFG_EN_OFFSET 0xd0
-#define GC_GLOBALSEC_DUSB0_REGION0_CTRL_CFG_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_DUSB0_REGION1_CTRL_CFG_EN_OFFSET 0xd4
-#define GC_GLOBALSEC_DUSB0_REGION1_CTRL_CFG_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_DUSB0_REGION2_CTRL_CFG_EN_OFFSET 0xd8
-#define GC_GLOBALSEC_DUSB0_REGION2_CTRL_CFG_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_DUSB0_REGION3_CTRL_CFG_EN_OFFSET 0xdc
-#define GC_GLOBALSEC_DUSB0_REGION3_CTRL_CFG_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_FLASH_REGION0_CTRL_OFFSET   0xe0
-#define GC_GLOBALSEC_FLASH_REGION0_CTRL_DEFAULT  0x0
-#define GC_GLOBALSEC_FLASH_REGION1_CTRL_OFFSET   0xe4
-#define GC_GLOBALSEC_FLASH_REGION1_CTRL_DEFAULT  0x0
-#define GC_GLOBALSEC_FLASH_REGION2_CTRL_OFFSET   0xe8
-#define GC_GLOBALSEC_FLASH_REGION2_CTRL_DEFAULT  0x0
-#define GC_GLOBALSEC_FLASH_REGION3_CTRL_OFFSET   0xec
-#define GC_GLOBALSEC_FLASH_REGION3_CTRL_DEFAULT  0x0
-#define GC_GLOBALSEC_FLASH_REGION4_CTRL_OFFSET   0xf0
-#define GC_GLOBALSEC_FLASH_REGION4_CTRL_DEFAULT  0x0
-#define GC_GLOBALSEC_FLASH_REGION5_CTRL_OFFSET   0xf4
-#define GC_GLOBALSEC_FLASH_REGION5_CTRL_DEFAULT  0x0
-#define GC_GLOBALSEC_FLASH_REGION6_CTRL_OFFSET   0xf8
-#define GC_GLOBALSEC_FLASH_REGION6_CTRL_DEFAULT  0x0
-#define GC_GLOBALSEC_FLASH_REGION7_CTRL_OFFSET   0xfc
-#define GC_GLOBALSEC_FLASH_REGION7_CTRL_DEFAULT  0x0
-#define GC_GLOBALSEC_FLASH_REGION0_CTRL_CFG_EN_OFFSET 0x100
-#define GC_GLOBALSEC_FLASH_REGION0_CTRL_CFG_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_FLASH_REGION1_CTRL_CFG_EN_OFFSET 0x104
-#define GC_GLOBALSEC_FLASH_REGION1_CTRL_CFG_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_FLASH_REGION2_CTRL_CFG_EN_OFFSET 0x108
-#define GC_GLOBALSEC_FLASH_REGION2_CTRL_CFG_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_FLASH_REGION3_CTRL_CFG_EN_OFFSET 0x10c
-#define GC_GLOBALSEC_FLASH_REGION3_CTRL_CFG_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_FLASH_REGION4_CTRL_CFG_EN_OFFSET 0x110
-#define GC_GLOBALSEC_FLASH_REGION4_CTRL_CFG_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_FLASH_REGION5_CTRL_CFG_EN_OFFSET 0x114
-#define GC_GLOBALSEC_FLASH_REGION5_CTRL_CFG_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_FLASH_REGION6_CTRL_CFG_EN_OFFSET 0x118
-#define GC_GLOBALSEC_FLASH_REGION6_CTRL_CFG_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_FLASH_REGION7_CTRL_CFG_EN_OFFSET 0x11c
-#define GC_GLOBALSEC_FLASH_REGION7_CTRL_CFG_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_FLASH0_BULKERASE_CFG_EN_OFFSET 0x120
-#define GC_GLOBALSEC_FLASH0_BULKERASE_CFG_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_FLASH0_BULKERASE_CTRL_OFFSET 0x124
-#define GC_GLOBALSEC_FLASH0_BULKERASE_CTRL_DEFAULT 0x0
-#define GC_GLOBALSEC_FLASH1_BULKERASE_CFG_EN_OFFSET 0x128
-#define GC_GLOBALSEC_FLASH1_BULKERASE_CFG_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_FLASH1_BULKERASE_CTRL_OFFSET 0x12c
-#define GC_GLOBALSEC_FLASH1_BULKERASE_CTRL_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_D_REGION0_BASE_ADDR_OFFSET 0x130
-#define GC_GLOBALSEC_CPU0_D_REGION0_BASE_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_D_REGION0_SIZE_OFFSET  0x134
-#define GC_GLOBALSEC_CPU0_D_REGION0_SIZE_DEFAULT 0xffffffff
-#define GC_GLOBALSEC_CPU0_D_REGION1_BASE_ADDR_OFFSET 0x138
-#define GC_GLOBALSEC_CPU0_D_REGION1_BASE_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_D_REGION1_SIZE_OFFSET  0x13c
-#define GC_GLOBALSEC_CPU0_D_REGION1_SIZE_DEFAULT 0xffffffff
-#define GC_GLOBALSEC_CPU0_D_REGION2_BASE_ADDR_OFFSET 0x140
-#define GC_GLOBALSEC_CPU0_D_REGION2_BASE_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_D_REGION2_SIZE_OFFSET  0x144
-#define GC_GLOBALSEC_CPU0_D_REGION2_SIZE_DEFAULT 0xffffffff
-#define GC_GLOBALSEC_CPU0_D_REGION3_BASE_ADDR_OFFSET 0x148
-#define GC_GLOBALSEC_CPU0_D_REGION3_BASE_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_D_REGION3_SIZE_OFFSET  0x14c
-#define GC_GLOBALSEC_CPU0_D_REGION3_SIZE_DEFAULT 0xffffffff
-#define GC_GLOBALSEC_CPU0_D_REGION4_BASE_ADDR_OFFSET 0x150
-#define GC_GLOBALSEC_CPU0_D_REGION4_BASE_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_D_REGION4_SIZE_OFFSET  0x154
-#define GC_GLOBALSEC_CPU0_D_REGION4_SIZE_DEFAULT 0xffffffff
-#define GC_GLOBALSEC_CPU0_D_REGION5_BASE_ADDR_OFFSET 0x158
-#define GC_GLOBALSEC_CPU0_D_REGION5_BASE_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_D_REGION5_SIZE_OFFSET  0x15c
-#define GC_GLOBALSEC_CPU0_D_REGION5_SIZE_DEFAULT 0xffffffff
-#define GC_GLOBALSEC_CPU0_D_REGION6_BASE_ADDR_OFFSET 0x160
-#define GC_GLOBALSEC_CPU0_D_REGION6_BASE_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_D_REGION6_SIZE_OFFSET  0x164
-#define GC_GLOBALSEC_CPU0_D_REGION6_SIZE_DEFAULT 0xffffffff
-#define GC_GLOBALSEC_CPU0_D_REGION7_BASE_ADDR_OFFSET 0x168
-#define GC_GLOBALSEC_CPU0_D_REGION7_BASE_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_D_REGION7_SIZE_OFFSET  0x16c
-#define GC_GLOBALSEC_CPU0_D_REGION7_SIZE_DEFAULT 0xffffffff
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_BASE_ADDR_OFFSET 0x170
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_BASE_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_SIZE_OFFSET 0x174
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_SIZE_DEFAULT 0xffffffff
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_BASE_ADDR_OFFSET 0x178
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_BASE_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_SIZE_OFFSET 0x17c
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_SIZE_DEFAULT 0xffffffff
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_BASE_ADDR_OFFSET 0x180
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_BASE_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_SIZE_OFFSET 0x184
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_SIZE_DEFAULT 0xffffffff
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_BASE_ADDR_OFFSET 0x188
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_BASE_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_SIZE_OFFSET 0x18c
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_SIZE_DEFAULT 0xffffffff
-#define GC_GLOBALSEC_CPU0_I_REGION0_BASE_ADDR_OFFSET 0x190
-#define GC_GLOBALSEC_CPU0_I_REGION0_BASE_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_REGION0_SIZE_OFFSET  0x194
-#define GC_GLOBALSEC_CPU0_I_REGION0_SIZE_DEFAULT 0xffffffff
-#define GC_GLOBALSEC_CPU0_I_REGION1_BASE_ADDR_OFFSET 0x198
-#define GC_GLOBALSEC_CPU0_I_REGION1_BASE_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_REGION1_SIZE_OFFSET  0x19c
-#define GC_GLOBALSEC_CPU0_I_REGION1_SIZE_DEFAULT 0xffffffff
-#define GC_GLOBALSEC_CPU0_I_REGION2_BASE_ADDR_OFFSET 0x1a0
-#define GC_GLOBALSEC_CPU0_I_REGION2_BASE_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_REGION2_SIZE_OFFSET  0x1a4
-#define GC_GLOBALSEC_CPU0_I_REGION2_SIZE_DEFAULT 0xffffffff
-#define GC_GLOBALSEC_CPU0_I_REGION3_BASE_ADDR_OFFSET 0x1a8
-#define GC_GLOBALSEC_CPU0_I_REGION3_BASE_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_REGION3_SIZE_OFFSET  0x1ac
-#define GC_GLOBALSEC_CPU0_I_REGION3_SIZE_DEFAULT 0xffffffff
-#define GC_GLOBALSEC_CPU0_I_REGION4_BASE_ADDR_OFFSET 0x1b0
-#define GC_GLOBALSEC_CPU0_I_REGION4_BASE_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_REGION4_SIZE_OFFSET  0x1b4
-#define GC_GLOBALSEC_CPU0_I_REGION4_SIZE_DEFAULT 0xffffffff
-#define GC_GLOBALSEC_CPU0_I_REGION5_BASE_ADDR_OFFSET 0x1b8
-#define GC_GLOBALSEC_CPU0_I_REGION5_BASE_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_REGION5_SIZE_OFFSET  0x1bc
-#define GC_GLOBALSEC_CPU0_I_REGION5_SIZE_DEFAULT 0xffffffff
-#define GC_GLOBALSEC_CPU0_I_REGION6_BASE_ADDR_OFFSET 0x1c0
-#define GC_GLOBALSEC_CPU0_I_REGION6_BASE_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_REGION6_SIZE_OFFSET  0x1c4
-#define GC_GLOBALSEC_CPU0_I_REGION6_SIZE_DEFAULT 0xffffffff
-#define GC_GLOBALSEC_CPU0_I_REGION7_BASE_ADDR_OFFSET 0x1c8
-#define GC_GLOBALSEC_CPU0_I_REGION7_BASE_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_REGION7_SIZE_OFFSET  0x1cc
-#define GC_GLOBALSEC_CPU0_I_REGION7_SIZE_DEFAULT 0xffffffff
-#define GC_GLOBALSEC_DDMA0_REGION0_BASE_ADDR_OFFSET 0x1d0
-#define GC_GLOBALSEC_DDMA0_REGION0_BASE_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_DDMA0_REGION0_SIZE_OFFSET   0x1d4
-#define GC_GLOBALSEC_DDMA0_REGION0_SIZE_DEFAULT  0xffffffff
-#define GC_GLOBALSEC_DDMA0_REGION1_BASE_ADDR_OFFSET 0x1d8
-#define GC_GLOBALSEC_DDMA0_REGION1_BASE_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_DDMA0_REGION1_SIZE_OFFSET   0x1dc
-#define GC_GLOBALSEC_DDMA0_REGION1_SIZE_DEFAULT  0xffffffff
-#define GC_GLOBALSEC_DDMA0_REGION2_BASE_ADDR_OFFSET 0x1e0
-#define GC_GLOBALSEC_DDMA0_REGION2_BASE_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_DDMA0_REGION2_SIZE_OFFSET   0x1e4
-#define GC_GLOBALSEC_DDMA0_REGION2_SIZE_DEFAULT  0xffffffff
-#define GC_GLOBALSEC_DDMA0_REGION3_BASE_ADDR_OFFSET 0x1e8
-#define GC_GLOBALSEC_DDMA0_REGION3_BASE_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_DDMA0_REGION3_SIZE_OFFSET   0x1ec
-#define GC_GLOBALSEC_DDMA0_REGION3_SIZE_DEFAULT  0xffffffff
-#define GC_GLOBALSEC_DSPS0_REGION0_BASE_ADDR_OFFSET 0x1f0
-#define GC_GLOBALSEC_DSPS0_REGION0_BASE_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_DSPS0_REGION0_SIZE_OFFSET   0x1f4
-#define GC_GLOBALSEC_DSPS0_REGION0_SIZE_DEFAULT  0xffffffff
-#define GC_GLOBALSEC_DSPS0_REGION1_BASE_ADDR_OFFSET 0x1f8
-#define GC_GLOBALSEC_DSPS0_REGION1_BASE_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_DSPS0_REGION1_SIZE_OFFSET   0x1fc
-#define GC_GLOBALSEC_DSPS0_REGION1_SIZE_DEFAULT  0xffffffff
-#define GC_GLOBALSEC_DSPS0_REGION2_BASE_ADDR_OFFSET 0x200
-#define GC_GLOBALSEC_DSPS0_REGION2_BASE_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_DSPS0_REGION2_SIZE_OFFSET   0x204
-#define GC_GLOBALSEC_DSPS0_REGION2_SIZE_DEFAULT  0xffffffff
-#define GC_GLOBALSEC_DSPS0_REGION3_BASE_ADDR_OFFSET 0x208
-#define GC_GLOBALSEC_DSPS0_REGION3_BASE_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_DSPS0_REGION3_SIZE_OFFSET   0x20c
-#define GC_GLOBALSEC_DSPS0_REGION3_SIZE_DEFAULT  0xffffffff
-#define GC_GLOBALSEC_DUSB0_REGION0_BASE_ADDR_OFFSET 0x210
-#define GC_GLOBALSEC_DUSB0_REGION0_BASE_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_DUSB0_REGION0_SIZE_OFFSET   0x214
-#define GC_GLOBALSEC_DUSB0_REGION0_SIZE_DEFAULT  0xffffffff
-#define GC_GLOBALSEC_DUSB0_REGION1_BASE_ADDR_OFFSET 0x218
-#define GC_GLOBALSEC_DUSB0_REGION1_BASE_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_DUSB0_REGION1_SIZE_OFFSET   0x21c
-#define GC_GLOBALSEC_DUSB0_REGION1_SIZE_DEFAULT  0xffffffff
-#define GC_GLOBALSEC_DUSB0_REGION2_BASE_ADDR_OFFSET 0x220
-#define GC_GLOBALSEC_DUSB0_REGION2_BASE_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_DUSB0_REGION2_SIZE_OFFSET   0x224
-#define GC_GLOBALSEC_DUSB0_REGION2_SIZE_DEFAULT  0xffffffff
-#define GC_GLOBALSEC_DUSB0_REGION3_BASE_ADDR_OFFSET 0x228
-#define GC_GLOBALSEC_DUSB0_REGION3_BASE_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_DUSB0_REGION3_SIZE_OFFSET   0x22c
-#define GC_GLOBALSEC_DUSB0_REGION3_SIZE_DEFAULT  0xffffffff
-#define GC_GLOBALSEC_FLASH_REGION0_BASE_ADDR_OFFSET 0x230
-#define GC_GLOBALSEC_FLASH_REGION0_BASE_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_FLASH_REGION0_SIZE_OFFSET   0x234
-#define GC_GLOBALSEC_FLASH_REGION0_SIZE_DEFAULT  0x0
-#define GC_GLOBALSEC_FLASH_REGION1_BASE_ADDR_OFFSET 0x238
-#define GC_GLOBALSEC_FLASH_REGION1_BASE_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_FLASH_REGION1_SIZE_OFFSET   0x23c
-#define GC_GLOBALSEC_FLASH_REGION1_SIZE_DEFAULT  0x0
-#define GC_GLOBALSEC_FLASH_REGION2_BASE_ADDR_OFFSET 0x240
-#define GC_GLOBALSEC_FLASH_REGION2_BASE_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_FLASH_REGION2_SIZE_OFFSET   0x244
-#define GC_GLOBALSEC_FLASH_REGION2_SIZE_DEFAULT  0x0
-#define GC_GLOBALSEC_FLASH_REGION3_BASE_ADDR_OFFSET 0x248
-#define GC_GLOBALSEC_FLASH_REGION3_BASE_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_FLASH_REGION3_SIZE_OFFSET   0x24c
-#define GC_GLOBALSEC_FLASH_REGION3_SIZE_DEFAULT  0x0
-#define GC_GLOBALSEC_FLASH_REGION4_BASE_ADDR_OFFSET 0x250
-#define GC_GLOBALSEC_FLASH_REGION4_BASE_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_FLASH_REGION4_SIZE_OFFSET   0x254
-#define GC_GLOBALSEC_FLASH_REGION4_SIZE_DEFAULT  0x0
-#define GC_GLOBALSEC_FLASH_REGION5_BASE_ADDR_OFFSET 0x258
-#define GC_GLOBALSEC_FLASH_REGION5_BASE_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_FLASH_REGION5_SIZE_OFFSET   0x25c
-#define GC_GLOBALSEC_FLASH_REGION5_SIZE_DEFAULT  0x0
-#define GC_GLOBALSEC_FLASH_REGION6_BASE_ADDR_OFFSET 0x260
-#define GC_GLOBALSEC_FLASH_REGION6_BASE_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_FLASH_REGION6_SIZE_OFFSET   0x264
-#define GC_GLOBALSEC_FLASH_REGION6_SIZE_DEFAULT  0x0
-#define GC_GLOBALSEC_FLASH_REGION7_BASE_ADDR_OFFSET 0x268
-#define GC_GLOBALSEC_FLASH_REGION7_BASE_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_FLASH_REGION7_SIZE_OFFSET   0x26c
-#define GC_GLOBALSEC_FLASH_REGION7_SIZE_DEFAULT  0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_OFFSET 0x270
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_BASE_ADDR_OFFSET 0x274
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_BASE_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_SIZE_OFFSET 0x278
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_SIZE_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_OFFSET 0x27c
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_BASE_ADDR_OFFSET 0x280
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_BASE_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_SIZE_OFFSET 0x284
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_SIZE_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_OFFSET 0x288
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_BASE_ADDR_OFFSET 0x28c
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_BASE_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_SIZE_OFFSET 0x290
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_SIZE_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_OFFSET 0x294
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_BASE_ADDR_OFFSET 0x298
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_BASE_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_SIZE_OFFSET 0x29c
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_SIZE_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_OFFSET 0x2a0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_BASE_ADDR_OFFSET 0x2a4
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_BASE_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_SIZE_OFFSET 0x2a8
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_SIZE_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_OFFSET 0x2ac
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_BASE_ADDR_OFFSET 0x2b0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_BASE_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_SIZE_OFFSET 0x2b4
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_SIZE_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_OFFSET 0x2b8
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_BASE_ADDR_OFFSET 0x2bc
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_BASE_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_SIZE_OFFSET 0x2c0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_SIZE_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_OFFSET 0x2c4
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_BASE_ADDR_OFFSET 0x2c8
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_BASE_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_SIZE_OFFSET 0x2cc
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_SIZE_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_S_PERMISSION_OFFSET    0x2d0
-#define GC_GLOBALSEC_CPU0_S_PERMISSION_DEFAULT   0x55
-#define GC_GLOBALSEC_CPU0_S_DAP_PERMISSION_OFFSET 0x2d4
-#define GC_GLOBALSEC_CPU0_S_DAP_PERMISSION_DEFAULT 0x55
-#define GC_GLOBALSEC_DDMA0_PERMISSION_OFFSET     0x2d8
-#define GC_GLOBALSEC_DDMA0_PERMISSION_DEFAULT    0x55
-#define GC_GLOBALSEC_SOFTWARE_LVL_OFFSET         0x2dc
-#define GC_GLOBALSEC_SOFTWARE_LVL_DEFAULT        0x55
-#define GC_GLOBALSEC_SB_COMP_STATUS_OFFSET       0x1000
-#define GC_GLOBALSEC_SB_COMP_STATUS_DEFAULT      0x0
-#define GC_GLOBALSEC_SB_BL_SIG0_OFFSET           0x1004
-#define GC_GLOBALSEC_SB_BL_SIG0_DEFAULT          0xfacecafe
-#define GC_GLOBALSEC_SB_BL_SIG1_OFFSET           0x1008
-#define GC_GLOBALSEC_SB_BL_SIG1_DEFAULT          0xfacecafe
-#define GC_GLOBALSEC_SB_BL_SIG2_OFFSET           0x100c
-#define GC_GLOBALSEC_SB_BL_SIG2_DEFAULT          0xfacecafe
-#define GC_GLOBALSEC_SB_BL_SIG3_OFFSET           0x1010
-#define GC_GLOBALSEC_SB_BL_SIG3_DEFAULT          0xfacecafe
-#define GC_GLOBALSEC_SB_BL_SIG4_OFFSET           0x1014
-#define GC_GLOBALSEC_SB_BL_SIG4_DEFAULT          0xfacecafe
-#define GC_GLOBALSEC_SB_BL_SIG5_OFFSET           0x1018
-#define GC_GLOBALSEC_SB_BL_SIG5_DEFAULT          0xfacecafe
-#define GC_GLOBALSEC_SB_BL_SIG6_OFFSET           0x101c
-#define GC_GLOBALSEC_SB_BL_SIG6_DEFAULT          0xfacecafe
-#define GC_GLOBALSEC_SB_BL_SIG7_OFFSET           0x1020
-#define GC_GLOBALSEC_SB_BL_SIG7_DEFAULT          0xfacecafe
-#define GC_GLOBALSEC_SIG_UNLOCK_OFFSET           0x1024
-#define GC_GLOBALSEC_SIG_UNLOCK_DEFAULT          0x0
-#define GC_GLOBALSEC_INT_ERR_FLAGS_OFFSET        0x1028
-#define GC_GLOBALSEC_INT_ERR_FLAGS_DEFAULT       0x0
-#define GC_GLOBALSEC_ALERT_CFG_LOCK_OFFSET       0x102c
-#define GC_GLOBALSEC_ALERT_CFG_LOCK_DEFAULT      0x1
-#define GC_GLOBALSEC_ALERT_FW_TRIGGER_OFFSET     0x4000
-#define GC_GLOBALSEC_ALERT_FW_TRIGGER_DEFAULT    0xaa
-#define GC_GLOBALSEC_ALERT_INTR_STS0_OFFSET      0x4004
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DEFAULT     0x0
-#define GC_GLOBALSEC_ALERT_INTR_STS1_OFFSET      0x4008
-#define GC_GLOBALSEC_ALERT_INTR_STS1_DEFAULT     0x0
-#define GC_GLOBALSEC_ALERT_NMI_EN0_OFFSET        0x400c
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DEFAULT       0x0
-#define GC_GLOBALSEC_ALERT_NMI_EN1_OFFSET        0x4010
-#define GC_GLOBALSEC_ALERT_NMI_EN1_DEFAULT       0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_OFFSET     0x4014
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DEFAULT    0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_OFFSET     0x4018
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_DEFAULT    0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_OFFSET     0x401c
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DEFAULT    0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_OFFSET     0x4020
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_DEFAULT    0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_OFFSET     0x4024
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DEFAULT    0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_OFFSET     0x4028
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_DEFAULT    0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_OFFSET    0x402c
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DEFAULT   0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_OFFSET    0x4030
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_DEFAULT   0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_OFFSET    0x4034
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DEFAULT   0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_OFFSET    0x4038
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_DEFAULT   0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_OFFSET    0x403c
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DEFAULT   0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_OFFSET    0x4040
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_DEFAULT   0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_CTR_OFFSET     0x4044
-#define GC_GLOBALSEC_ALERT_GROUPA_CTR_DEFAULT    0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_CTR_OFFSET     0x4048
-#define GC_GLOBALSEC_ALERT_GROUPB_CTR_DEFAULT    0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_CTR_OFFSET     0x404c
-#define GC_GLOBALSEC_ALERT_GROUPC_CTR_DEFAULT    0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_THRESHOLD_OFFSET 0x4050
-#define GC_GLOBALSEC_ALERT_GROUPA_THRESHOLD_DEFAULT 0x64
-#define GC_GLOBALSEC_ALERT_GROUPB_THRESHOLD_OFFSET 0x4054
-#define GC_GLOBALSEC_ALERT_GROUPB_THRESHOLD_DEFAULT 0x64
-#define GC_GLOBALSEC_ALERT_GROUPC_THRESHOLD_OFFSET 0x4058
-#define GC_GLOBALSEC_ALERT_GROUPC_THRESHOLD_DEFAULT 0x64
-#define GC_GLOBALSEC_ALERT_CONTROL_OFFSET        0x405c
-#define GC_GLOBALSEC_ALERT_CONTROL_DEFAULT       0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_OFFSET        0x4060
-#define GC_GLOBALSEC_ALERT_DLYCTR0_DEFAULT       0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_OFFSET        0x4064
-#define GC_GLOBALSEC_ALERT_DLYCTR1_DEFAULT       0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_OFFSET        0x4068
-#define GC_GLOBALSEC_ALERT_DLYCTR2_DEFAULT       0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_LEN_OFFSET    0x406c
-#define GC_GLOBALSEC_ALERT_DLYCTR0_LEN_DEFAULT   0xffff
-#define GC_GLOBALSEC_ALERT_DLYCTR1_LEN_OFFSET    0x4070
-#define GC_GLOBALSEC_ALERT_DLYCTR1_LEN_DEFAULT   0xffff
-#define GC_GLOBALSEC_ALERT_DLYCTR2_LEN_OFFSET    0x4074
-#define GC_GLOBALSEC_ALERT_DLYCTR2_LEN_DEFAULT   0xffff
-#define GC_GLOBALSEC_ALERT_DLYCTR0_SHUTDOWN_EN_OFFSET 0x4078
-#define GC_GLOBALSEC_ALERT_DLYCTR0_SHUTDOWN_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_SHUTDOWN_EN_OFFSET 0x407c
-#define GC_GLOBALSEC_ALERT_DLYCTR1_SHUTDOWN_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_SHUTDOWN_EN_OFFSET 0x4080
-#define GC_GLOBALSEC_ALERT_DLYCTR2_SHUTDOWN_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_CLEAR_OFFSET  0x4084
-#define GC_GLOBALSEC_ALERT_DLYCTR0_CLEAR_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_CLEAR_OFFSET  0x4088
-#define GC_GLOBALSEC_ALERT_DLYCTR1_CLEAR_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_CLEAR_OFFSET  0x408c
-#define GC_GLOBALSEC_ALERT_DLYCTR2_CLEAR_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_D_ERROR_HISTORY_OFFSET 0x4090
-#define GC_GLOBALSEC_CPU0_D_ERROR_HISTORY_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_D_ERROR_HISTORY_EMPTY_OFFSET 0x4094
-#define GC_GLOBALSEC_CPU0_D_ERROR_HISTORY_EMPTY_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_ERROR_HISTORY_OFFSET 0x4098
-#define GC_GLOBALSEC_CPU0_I_ERROR_HISTORY_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_ERROR_HISTORY_EMPTY_OFFSET 0x409c
-#define GC_GLOBALSEC_CPU0_I_ERROR_HISTORY_EMPTY_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_S_ERROR_HISTORY_OFFSET 0x40a0
-#define GC_GLOBALSEC_CPU0_S_ERROR_HISTORY_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_S_ERROR_HISTORY_EMPTY_OFFSET 0x40a4
-#define GC_GLOBALSEC_CPU0_S_ERROR_HISTORY_EMPTY_DEFAULT 0x0
-#define GC_GLOBALSEC_DSPS0_ERROR_HISTORY_OFFSET  0x40a8
-#define GC_GLOBALSEC_DSPS0_ERROR_HISTORY_DEFAULT 0x0
-#define GC_GLOBALSEC_DSPS0_ERROR_HISTORY_EMPTY_OFFSET 0x40ac
-#define GC_GLOBALSEC_DSPS0_ERROR_HISTORY_EMPTY_DEFAULT 0x0
-#define GC_GLOBALSEC_DUSB0_ERROR_HISTORY_OFFSET  0x40b0
-#define GC_GLOBALSEC_DUSB0_ERROR_HISTORY_DEFAULT 0x0
-#define GC_GLOBALSEC_DUSB0_ERROR_HISTORY_EMPTY_OFFSET 0x40b4
-#define GC_GLOBALSEC_DUSB0_ERROR_HISTORY_EMPTY_DEFAULT 0x0
-#define GC_GLOBALSEC_OBFS_SW_EN_OFFSET           0x40b8
-#define GC_GLOBALSEC_OBFS_SW_EN_DEFAULT          0x0
-#define GC_GLOBALSEC_TRANSMISSION_PARITY_EN_OFFSET 0x40bc
-#define GC_GLOBALSEC_TRANSMISSION_PARITY_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_SRAM_PARITY_CHECK_ENABLE_OFFSET 0x40c0
-#define GC_GLOBALSEC_SRAM_PARITY_CHECK_ENABLE_DEFAULT 0x0
-#define GC_GLOBALSEC_SRAM_PARITY_SCRUB_FREQ_OFFSET 0x40c4
-#define GC_GLOBALSEC_SRAM_PARITY_SCRUB_FREQ_DEFAULT 0x0
-#define GC_GLOBALSEC_SRAM_PARITY_SCRUB_ERROR_COUNT_OFFSET 0x40c8
-#define GC_GLOBALSEC_SRAM_PARITY_SCRUB_ERROR_COUNT_DEFAULT 0x0
-#define GC_GLOBALSEC_SRAM_PARITY_SCRUB_ERROR_ADDR_OFFSET 0x40cc
-#define GC_GLOBALSEC_SRAM_PARITY_SCRUB_ERROR_ADDR_DEFAULT 0x0
-#define GC_GLOBALSEC_HIDE_ROM_OFFSET             0x40d0
-#define GC_GLOBALSEC_HIDE_ROM_DEFAULT            0x0
-#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_OFFSET 0x40d4
-#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_DEFAULT 0x2f
-#define GC_GLOBALSEC_ANTEST_SEN_LSR_OUTPUT_OFFSET 0x40d8
-#define GC_GLOBALSEC_ANTEST_SEN_LSR_OUTPUT_DEFAULT 0x0
-#define GC_GLOBALSEC_VERSION_OFFSET              0x40dc
-#define GC_GLOBALSEC_VERSION_DEFAULT             0x59010913
-#define GC_GPIO_DATAIN_OFFSET                    0x0
-#define GC_GPIO_DATAIN_DEFAULT                   0x0
-#define GC_GPIO_DOUT_OFFSET                      0x4
-#define GC_GPIO_DOUT_DEFAULT                     0x0
-#define GC_GPIO_SETDOUTEN_OFFSET                 0x10
-#define GC_GPIO_SETDOUTEN_DEFAULT                0x0
-#define GC_GPIO_CLRDOUTEN_OFFSET                 0x14
-#define GC_GPIO_CLRDOUTEN_DEFAULT                0x0
-#define GC_GPIO_RESERVED0_OFFSET                 0x18
-#define GC_GPIO_RESERVED0_DEFAULT                0x0
-#define GC_GPIO_RESERVED1_OFFSET                 0x1c
-#define GC_GPIO_RESERVED1_DEFAULT                0x0
-#define GC_GPIO_SETINTEN_OFFSET                  0x20
-#define GC_GPIO_SETINTEN_DEFAULT                 0x0
-#define GC_GPIO_CLRINTEN_OFFSET                  0x24
-#define GC_GPIO_CLRINTEN_DEFAULT                 0x0
-#define GC_GPIO_SETINTTYPE_OFFSET                0x28
-#define GC_GPIO_SETINTTYPE_DEFAULT               0x0
-#define GC_GPIO_CLRINTTYPE_OFFSET                0x2c
-#define GC_GPIO_CLRINTTYPE_DEFAULT               0x0
-#define GC_GPIO_SETINTPOL_OFFSET                 0x30
-#define GC_GPIO_SETINTPOL_DEFAULT                0x0
-#define GC_GPIO_CLRINTPOL_OFFSET                 0x34
-#define GC_GPIO_CLRINTPOL_DEFAULT                0x0
-#define GC_GPIO_CLRINTSTAT_OFFSET                0x38
-#define GC_GPIO_CLRINTSTAT_DEFAULT               0x0
-#define GC_GPIO_MASKLOWBYTE_400_OFFSET           0x400
-#define GC_GPIO_MASKLOWBYTE_400_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_404_OFFSET           0x404
-#define GC_GPIO_MASKLOWBYTE_404_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_408_OFFSET           0x408
-#define GC_GPIO_MASKLOWBYTE_408_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_40C_OFFSET           0x40c
-#define GC_GPIO_MASKLOWBYTE_40C_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_410_OFFSET           0x410
-#define GC_GPIO_MASKLOWBYTE_410_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_414_OFFSET           0x414
-#define GC_GPIO_MASKLOWBYTE_414_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_418_OFFSET           0x418
-#define GC_GPIO_MASKLOWBYTE_418_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_41C_OFFSET           0x41c
-#define GC_GPIO_MASKLOWBYTE_41C_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_420_OFFSET           0x420
-#define GC_GPIO_MASKLOWBYTE_420_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_424_OFFSET           0x424
-#define GC_GPIO_MASKLOWBYTE_424_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_428_OFFSET           0x428
-#define GC_GPIO_MASKLOWBYTE_428_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_42C_OFFSET           0x42c
-#define GC_GPIO_MASKLOWBYTE_42C_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_430_OFFSET           0x430
-#define GC_GPIO_MASKLOWBYTE_430_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_434_OFFSET           0x434
-#define GC_GPIO_MASKLOWBYTE_434_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_438_OFFSET           0x438
-#define GC_GPIO_MASKLOWBYTE_438_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_43C_OFFSET           0x43c
-#define GC_GPIO_MASKLOWBYTE_43C_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_440_OFFSET           0x440
-#define GC_GPIO_MASKLOWBYTE_440_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_444_OFFSET           0x444
-#define GC_GPIO_MASKLOWBYTE_444_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_448_OFFSET           0x448
-#define GC_GPIO_MASKLOWBYTE_448_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_44C_OFFSET           0x44c
-#define GC_GPIO_MASKLOWBYTE_44C_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_450_OFFSET           0x450
-#define GC_GPIO_MASKLOWBYTE_450_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_454_OFFSET           0x454
-#define GC_GPIO_MASKLOWBYTE_454_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_458_OFFSET           0x458
-#define GC_GPIO_MASKLOWBYTE_458_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_45C_OFFSET           0x45c
-#define GC_GPIO_MASKLOWBYTE_45C_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_460_OFFSET           0x460
-#define GC_GPIO_MASKLOWBYTE_460_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_464_OFFSET           0x464
-#define GC_GPIO_MASKLOWBYTE_464_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_468_OFFSET           0x468
-#define GC_GPIO_MASKLOWBYTE_468_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_46C_OFFSET           0x46c
-#define GC_GPIO_MASKLOWBYTE_46C_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_470_OFFSET           0x470
-#define GC_GPIO_MASKLOWBYTE_470_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_474_OFFSET           0x474
-#define GC_GPIO_MASKLOWBYTE_474_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_478_OFFSET           0x478
-#define GC_GPIO_MASKLOWBYTE_478_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_47C_OFFSET           0x47c
-#define GC_GPIO_MASKLOWBYTE_47C_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_480_OFFSET           0x480
-#define GC_GPIO_MASKLOWBYTE_480_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_484_OFFSET           0x484
-#define GC_GPIO_MASKLOWBYTE_484_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_488_OFFSET           0x488
-#define GC_GPIO_MASKLOWBYTE_488_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_48C_OFFSET           0x48c
-#define GC_GPIO_MASKLOWBYTE_48C_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_490_OFFSET           0x490
-#define GC_GPIO_MASKLOWBYTE_490_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_494_OFFSET           0x494
-#define GC_GPIO_MASKLOWBYTE_494_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_498_OFFSET           0x498
-#define GC_GPIO_MASKLOWBYTE_498_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_49C_OFFSET           0x49c
-#define GC_GPIO_MASKLOWBYTE_49C_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_4A0_OFFSET           0x4a0
-#define GC_GPIO_MASKLOWBYTE_4A0_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_4A4_OFFSET           0x4a4
-#define GC_GPIO_MASKLOWBYTE_4A4_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_4A8_OFFSET           0x4a8
-#define GC_GPIO_MASKLOWBYTE_4A8_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_4AC_OFFSET           0x4ac
-#define GC_GPIO_MASKLOWBYTE_4AC_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_4B0_OFFSET           0x4b0
-#define GC_GPIO_MASKLOWBYTE_4B0_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_4B4_OFFSET           0x4b4
-#define GC_GPIO_MASKLOWBYTE_4B4_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_4B8_OFFSET           0x4b8
-#define GC_GPIO_MASKLOWBYTE_4B8_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_4BC_OFFSET           0x4bc
-#define GC_GPIO_MASKLOWBYTE_4BC_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_4C0_OFFSET           0x4c0
-#define GC_GPIO_MASKLOWBYTE_4C0_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_4C4_OFFSET           0x4c4
-#define GC_GPIO_MASKLOWBYTE_4C4_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_4C8_OFFSET           0x4c8
-#define GC_GPIO_MASKLOWBYTE_4C8_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_4CC_OFFSET           0x4cc
-#define GC_GPIO_MASKLOWBYTE_4CC_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_4D0_OFFSET           0x4d0
-#define GC_GPIO_MASKLOWBYTE_4D0_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_4D4_OFFSET           0x4d4
-#define GC_GPIO_MASKLOWBYTE_4D4_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_4D8_OFFSET           0x4d8
-#define GC_GPIO_MASKLOWBYTE_4D8_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_4DC_OFFSET           0x4dc
-#define GC_GPIO_MASKLOWBYTE_4DC_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_4E0_OFFSET           0x4e0
-#define GC_GPIO_MASKLOWBYTE_4E0_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_4E4_OFFSET           0x4e4
-#define GC_GPIO_MASKLOWBYTE_4E4_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_4E8_OFFSET           0x4e8
-#define GC_GPIO_MASKLOWBYTE_4E8_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_4EC_OFFSET           0x4ec
-#define GC_GPIO_MASKLOWBYTE_4EC_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_4F0_OFFSET           0x4f0
-#define GC_GPIO_MASKLOWBYTE_4F0_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_4F4_OFFSET           0x4f4
-#define GC_GPIO_MASKLOWBYTE_4F4_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_4F8_OFFSET           0x4f8
-#define GC_GPIO_MASKLOWBYTE_4F8_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_4FC_OFFSET           0x4fc
-#define GC_GPIO_MASKLOWBYTE_4FC_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_500_OFFSET           0x500
-#define GC_GPIO_MASKLOWBYTE_500_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_504_OFFSET           0x504
-#define GC_GPIO_MASKLOWBYTE_504_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_508_OFFSET           0x508
-#define GC_GPIO_MASKLOWBYTE_508_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_50C_OFFSET           0x50c
-#define GC_GPIO_MASKLOWBYTE_50C_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_510_OFFSET           0x510
-#define GC_GPIO_MASKLOWBYTE_510_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_514_OFFSET           0x514
-#define GC_GPIO_MASKLOWBYTE_514_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_518_OFFSET           0x518
-#define GC_GPIO_MASKLOWBYTE_518_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_51C_OFFSET           0x51c
-#define GC_GPIO_MASKLOWBYTE_51C_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_520_OFFSET           0x520
-#define GC_GPIO_MASKLOWBYTE_520_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_524_OFFSET           0x524
-#define GC_GPIO_MASKLOWBYTE_524_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_528_OFFSET           0x528
-#define GC_GPIO_MASKLOWBYTE_528_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_52C_OFFSET           0x52c
-#define GC_GPIO_MASKLOWBYTE_52C_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_530_OFFSET           0x530
-#define GC_GPIO_MASKLOWBYTE_530_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_534_OFFSET           0x534
-#define GC_GPIO_MASKLOWBYTE_534_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_538_OFFSET           0x538
-#define GC_GPIO_MASKLOWBYTE_538_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_53C_OFFSET           0x53c
-#define GC_GPIO_MASKLOWBYTE_53C_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_540_OFFSET           0x540
-#define GC_GPIO_MASKLOWBYTE_540_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_544_OFFSET           0x544
-#define GC_GPIO_MASKLOWBYTE_544_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_548_OFFSET           0x548
-#define GC_GPIO_MASKLOWBYTE_548_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_54C_OFFSET           0x54c
-#define GC_GPIO_MASKLOWBYTE_54C_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_550_OFFSET           0x550
-#define GC_GPIO_MASKLOWBYTE_550_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_554_OFFSET           0x554
-#define GC_GPIO_MASKLOWBYTE_554_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_558_OFFSET           0x558
-#define GC_GPIO_MASKLOWBYTE_558_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_55C_OFFSET           0x55c
-#define GC_GPIO_MASKLOWBYTE_55C_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_560_OFFSET           0x560
-#define GC_GPIO_MASKLOWBYTE_560_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_564_OFFSET           0x564
-#define GC_GPIO_MASKLOWBYTE_564_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_568_OFFSET           0x568
-#define GC_GPIO_MASKLOWBYTE_568_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_56C_OFFSET           0x56c
-#define GC_GPIO_MASKLOWBYTE_56C_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_570_OFFSET           0x570
-#define GC_GPIO_MASKLOWBYTE_570_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_574_OFFSET           0x574
-#define GC_GPIO_MASKLOWBYTE_574_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_578_OFFSET           0x578
-#define GC_GPIO_MASKLOWBYTE_578_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_57C_OFFSET           0x57c
-#define GC_GPIO_MASKLOWBYTE_57C_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_580_OFFSET           0x580
-#define GC_GPIO_MASKLOWBYTE_580_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_584_OFFSET           0x584
-#define GC_GPIO_MASKLOWBYTE_584_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_588_OFFSET           0x588
-#define GC_GPIO_MASKLOWBYTE_588_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_58C_OFFSET           0x58c
-#define GC_GPIO_MASKLOWBYTE_58C_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_590_OFFSET           0x590
-#define GC_GPIO_MASKLOWBYTE_590_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_594_OFFSET           0x594
-#define GC_GPIO_MASKLOWBYTE_594_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_598_OFFSET           0x598
-#define GC_GPIO_MASKLOWBYTE_598_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_59C_OFFSET           0x59c
-#define GC_GPIO_MASKLOWBYTE_59C_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_5A0_OFFSET           0x5a0
-#define GC_GPIO_MASKLOWBYTE_5A0_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_5A4_OFFSET           0x5a4
-#define GC_GPIO_MASKLOWBYTE_5A4_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_5A8_OFFSET           0x5a8
-#define GC_GPIO_MASKLOWBYTE_5A8_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_5AC_OFFSET           0x5ac
-#define GC_GPIO_MASKLOWBYTE_5AC_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_5B0_OFFSET           0x5b0
-#define GC_GPIO_MASKLOWBYTE_5B0_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_5B4_OFFSET           0x5b4
-#define GC_GPIO_MASKLOWBYTE_5B4_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_5B8_OFFSET           0x5b8
-#define GC_GPIO_MASKLOWBYTE_5B8_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_5BC_OFFSET           0x5bc
-#define GC_GPIO_MASKLOWBYTE_5BC_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_5C0_OFFSET           0x5c0
-#define GC_GPIO_MASKLOWBYTE_5C0_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_5C4_OFFSET           0x5c4
-#define GC_GPIO_MASKLOWBYTE_5C4_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_5C8_OFFSET           0x5c8
-#define GC_GPIO_MASKLOWBYTE_5C8_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_5CC_OFFSET           0x5cc
-#define GC_GPIO_MASKLOWBYTE_5CC_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_5D0_OFFSET           0x5d0
-#define GC_GPIO_MASKLOWBYTE_5D0_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_5D4_OFFSET           0x5d4
-#define GC_GPIO_MASKLOWBYTE_5D4_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_5D8_OFFSET           0x5d8
-#define GC_GPIO_MASKLOWBYTE_5D8_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_5DC_OFFSET           0x5dc
-#define GC_GPIO_MASKLOWBYTE_5DC_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_5E0_OFFSET           0x5e0
-#define GC_GPIO_MASKLOWBYTE_5E0_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_5E4_OFFSET           0x5e4
-#define GC_GPIO_MASKLOWBYTE_5E4_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_5E8_OFFSET           0x5e8
-#define GC_GPIO_MASKLOWBYTE_5E8_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_5EC_OFFSET           0x5ec
-#define GC_GPIO_MASKLOWBYTE_5EC_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_5F0_OFFSET           0x5f0
-#define GC_GPIO_MASKLOWBYTE_5F0_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_5F4_OFFSET           0x5f4
-#define GC_GPIO_MASKLOWBYTE_5F4_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_5F8_OFFSET           0x5f8
-#define GC_GPIO_MASKLOWBYTE_5F8_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_5FC_OFFSET           0x5fc
-#define GC_GPIO_MASKLOWBYTE_5FC_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_600_OFFSET           0x600
-#define GC_GPIO_MASKLOWBYTE_600_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_604_OFFSET           0x604
-#define GC_GPIO_MASKLOWBYTE_604_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_608_OFFSET           0x608
-#define GC_GPIO_MASKLOWBYTE_608_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_60C_OFFSET           0x60c
-#define GC_GPIO_MASKLOWBYTE_60C_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_610_OFFSET           0x610
-#define GC_GPIO_MASKLOWBYTE_610_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_614_OFFSET           0x614
-#define GC_GPIO_MASKLOWBYTE_614_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_618_OFFSET           0x618
-#define GC_GPIO_MASKLOWBYTE_618_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_61C_OFFSET           0x61c
-#define GC_GPIO_MASKLOWBYTE_61C_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_620_OFFSET           0x620
-#define GC_GPIO_MASKLOWBYTE_620_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_624_OFFSET           0x624
-#define GC_GPIO_MASKLOWBYTE_624_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_628_OFFSET           0x628
-#define GC_GPIO_MASKLOWBYTE_628_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_62C_OFFSET           0x62c
-#define GC_GPIO_MASKLOWBYTE_62C_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_630_OFFSET           0x630
-#define GC_GPIO_MASKLOWBYTE_630_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_634_OFFSET           0x634
-#define GC_GPIO_MASKLOWBYTE_634_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_638_OFFSET           0x638
-#define GC_GPIO_MASKLOWBYTE_638_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_63C_OFFSET           0x63c
-#define GC_GPIO_MASKLOWBYTE_63C_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_640_OFFSET           0x640
-#define GC_GPIO_MASKLOWBYTE_640_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_644_OFFSET           0x644
-#define GC_GPIO_MASKLOWBYTE_644_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_648_OFFSET           0x648
-#define GC_GPIO_MASKLOWBYTE_648_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_64C_OFFSET           0x64c
-#define GC_GPIO_MASKLOWBYTE_64C_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_650_OFFSET           0x650
-#define GC_GPIO_MASKLOWBYTE_650_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_654_OFFSET           0x654
-#define GC_GPIO_MASKLOWBYTE_654_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_658_OFFSET           0x658
-#define GC_GPIO_MASKLOWBYTE_658_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_65C_OFFSET           0x65c
-#define GC_GPIO_MASKLOWBYTE_65C_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_660_OFFSET           0x660
-#define GC_GPIO_MASKLOWBYTE_660_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_664_OFFSET           0x664
-#define GC_GPIO_MASKLOWBYTE_664_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_668_OFFSET           0x668
-#define GC_GPIO_MASKLOWBYTE_668_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_66C_OFFSET           0x66c
-#define GC_GPIO_MASKLOWBYTE_66C_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_670_OFFSET           0x670
-#define GC_GPIO_MASKLOWBYTE_670_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_674_OFFSET           0x674
-#define GC_GPIO_MASKLOWBYTE_674_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_678_OFFSET           0x678
-#define GC_GPIO_MASKLOWBYTE_678_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_67C_OFFSET           0x67c
-#define GC_GPIO_MASKLOWBYTE_67C_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_680_OFFSET           0x680
-#define GC_GPIO_MASKLOWBYTE_680_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_684_OFFSET           0x684
-#define GC_GPIO_MASKLOWBYTE_684_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_688_OFFSET           0x688
-#define GC_GPIO_MASKLOWBYTE_688_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_68C_OFFSET           0x68c
-#define GC_GPIO_MASKLOWBYTE_68C_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_690_OFFSET           0x690
-#define GC_GPIO_MASKLOWBYTE_690_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_694_OFFSET           0x694
-#define GC_GPIO_MASKLOWBYTE_694_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_698_OFFSET           0x698
-#define GC_GPIO_MASKLOWBYTE_698_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_69C_OFFSET           0x69c
-#define GC_GPIO_MASKLOWBYTE_69C_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_6A0_OFFSET           0x6a0
-#define GC_GPIO_MASKLOWBYTE_6A0_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_6A4_OFFSET           0x6a4
-#define GC_GPIO_MASKLOWBYTE_6A4_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_6A8_OFFSET           0x6a8
-#define GC_GPIO_MASKLOWBYTE_6A8_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_6AC_OFFSET           0x6ac
-#define GC_GPIO_MASKLOWBYTE_6AC_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_6B0_OFFSET           0x6b0
-#define GC_GPIO_MASKLOWBYTE_6B0_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_6B4_OFFSET           0x6b4
-#define GC_GPIO_MASKLOWBYTE_6B4_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_6B8_OFFSET           0x6b8
-#define GC_GPIO_MASKLOWBYTE_6B8_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_6BC_OFFSET           0x6bc
-#define GC_GPIO_MASKLOWBYTE_6BC_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_6C0_OFFSET           0x6c0
-#define GC_GPIO_MASKLOWBYTE_6C0_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_6C4_OFFSET           0x6c4
-#define GC_GPIO_MASKLOWBYTE_6C4_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_6C8_OFFSET           0x6c8
-#define GC_GPIO_MASKLOWBYTE_6C8_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_6CC_OFFSET           0x6cc
-#define GC_GPIO_MASKLOWBYTE_6CC_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_6D0_OFFSET           0x6d0
-#define GC_GPIO_MASKLOWBYTE_6D0_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_6D4_OFFSET           0x6d4
-#define GC_GPIO_MASKLOWBYTE_6D4_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_6D8_OFFSET           0x6d8
-#define GC_GPIO_MASKLOWBYTE_6D8_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_6DC_OFFSET           0x6dc
-#define GC_GPIO_MASKLOWBYTE_6DC_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_6E0_OFFSET           0x6e0
-#define GC_GPIO_MASKLOWBYTE_6E0_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_6E4_OFFSET           0x6e4
-#define GC_GPIO_MASKLOWBYTE_6E4_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_6E8_OFFSET           0x6e8
-#define GC_GPIO_MASKLOWBYTE_6E8_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_6EC_OFFSET           0x6ec
-#define GC_GPIO_MASKLOWBYTE_6EC_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_6F0_OFFSET           0x6f0
-#define GC_GPIO_MASKLOWBYTE_6F0_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_6F4_OFFSET           0x6f4
-#define GC_GPIO_MASKLOWBYTE_6F4_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_6F8_OFFSET           0x6f8
-#define GC_GPIO_MASKLOWBYTE_6F8_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_6FC_OFFSET           0x6fc
-#define GC_GPIO_MASKLOWBYTE_6FC_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_700_OFFSET           0x700
-#define GC_GPIO_MASKLOWBYTE_700_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_704_OFFSET           0x704
-#define GC_GPIO_MASKLOWBYTE_704_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_708_OFFSET           0x708
-#define GC_GPIO_MASKLOWBYTE_708_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_70C_OFFSET           0x70c
-#define GC_GPIO_MASKLOWBYTE_70C_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_710_OFFSET           0x710
-#define GC_GPIO_MASKLOWBYTE_710_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_714_OFFSET           0x714
-#define GC_GPIO_MASKLOWBYTE_714_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_718_OFFSET           0x718
-#define GC_GPIO_MASKLOWBYTE_718_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_71C_OFFSET           0x71c
-#define GC_GPIO_MASKLOWBYTE_71C_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_720_OFFSET           0x720
-#define GC_GPIO_MASKLOWBYTE_720_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_724_OFFSET           0x724
-#define GC_GPIO_MASKLOWBYTE_724_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_728_OFFSET           0x728
-#define GC_GPIO_MASKLOWBYTE_728_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_72C_OFFSET           0x72c
-#define GC_GPIO_MASKLOWBYTE_72C_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_730_OFFSET           0x730
-#define GC_GPIO_MASKLOWBYTE_730_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_734_OFFSET           0x734
-#define GC_GPIO_MASKLOWBYTE_734_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_738_OFFSET           0x738
-#define GC_GPIO_MASKLOWBYTE_738_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_73C_OFFSET           0x73c
-#define GC_GPIO_MASKLOWBYTE_73C_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_740_OFFSET           0x740
-#define GC_GPIO_MASKLOWBYTE_740_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_744_OFFSET           0x744
-#define GC_GPIO_MASKLOWBYTE_744_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_748_OFFSET           0x748
-#define GC_GPIO_MASKLOWBYTE_748_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_74C_OFFSET           0x74c
-#define GC_GPIO_MASKLOWBYTE_74C_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_750_OFFSET           0x750
-#define GC_GPIO_MASKLOWBYTE_750_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_754_OFFSET           0x754
-#define GC_GPIO_MASKLOWBYTE_754_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_758_OFFSET           0x758
-#define GC_GPIO_MASKLOWBYTE_758_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_75C_OFFSET           0x75c
-#define GC_GPIO_MASKLOWBYTE_75C_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_760_OFFSET           0x760
-#define GC_GPIO_MASKLOWBYTE_760_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_764_OFFSET           0x764
-#define GC_GPIO_MASKLOWBYTE_764_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_768_OFFSET           0x768
-#define GC_GPIO_MASKLOWBYTE_768_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_76C_OFFSET           0x76c
-#define GC_GPIO_MASKLOWBYTE_76C_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_770_OFFSET           0x770
-#define GC_GPIO_MASKLOWBYTE_770_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_774_OFFSET           0x774
-#define GC_GPIO_MASKLOWBYTE_774_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_778_OFFSET           0x778
-#define GC_GPIO_MASKLOWBYTE_778_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_77C_OFFSET           0x77c
-#define GC_GPIO_MASKLOWBYTE_77C_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_780_OFFSET           0x780
-#define GC_GPIO_MASKLOWBYTE_780_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_784_OFFSET           0x784
-#define GC_GPIO_MASKLOWBYTE_784_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_788_OFFSET           0x788
-#define GC_GPIO_MASKLOWBYTE_788_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_78C_OFFSET           0x78c
-#define GC_GPIO_MASKLOWBYTE_78C_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_790_OFFSET           0x790
-#define GC_GPIO_MASKLOWBYTE_790_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_794_OFFSET           0x794
-#define GC_GPIO_MASKLOWBYTE_794_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_798_OFFSET           0x798
-#define GC_GPIO_MASKLOWBYTE_798_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_79C_OFFSET           0x79c
-#define GC_GPIO_MASKLOWBYTE_79C_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_7A0_OFFSET           0x7a0
-#define GC_GPIO_MASKLOWBYTE_7A0_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_7A4_OFFSET           0x7a4
-#define GC_GPIO_MASKLOWBYTE_7A4_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_7A8_OFFSET           0x7a8
-#define GC_GPIO_MASKLOWBYTE_7A8_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_7AC_OFFSET           0x7ac
-#define GC_GPIO_MASKLOWBYTE_7AC_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_7B0_OFFSET           0x7b0
-#define GC_GPIO_MASKLOWBYTE_7B0_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_7B4_OFFSET           0x7b4
-#define GC_GPIO_MASKLOWBYTE_7B4_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_7B8_OFFSET           0x7b8
-#define GC_GPIO_MASKLOWBYTE_7B8_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_7BC_OFFSET           0x7bc
-#define GC_GPIO_MASKLOWBYTE_7BC_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_7C0_OFFSET           0x7c0
-#define GC_GPIO_MASKLOWBYTE_7C0_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_7C4_OFFSET           0x7c4
-#define GC_GPIO_MASKLOWBYTE_7C4_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_7C8_OFFSET           0x7c8
-#define GC_GPIO_MASKLOWBYTE_7C8_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_7CC_OFFSET           0x7cc
-#define GC_GPIO_MASKLOWBYTE_7CC_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_7D0_OFFSET           0x7d0
-#define GC_GPIO_MASKLOWBYTE_7D0_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_7D4_OFFSET           0x7d4
-#define GC_GPIO_MASKLOWBYTE_7D4_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_7D8_OFFSET           0x7d8
-#define GC_GPIO_MASKLOWBYTE_7D8_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_7DC_OFFSET           0x7dc
-#define GC_GPIO_MASKLOWBYTE_7DC_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_7E0_OFFSET           0x7e0
-#define GC_GPIO_MASKLOWBYTE_7E0_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_7E4_OFFSET           0x7e4
-#define GC_GPIO_MASKLOWBYTE_7E4_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_7E8_OFFSET           0x7e8
-#define GC_GPIO_MASKLOWBYTE_7E8_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_7EC_OFFSET           0x7ec
-#define GC_GPIO_MASKLOWBYTE_7EC_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_7F0_OFFSET           0x7f0
-#define GC_GPIO_MASKLOWBYTE_7F0_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_7F4_OFFSET           0x7f4
-#define GC_GPIO_MASKLOWBYTE_7F4_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_7F8_OFFSET           0x7f8
-#define GC_GPIO_MASKLOWBYTE_7F8_DEFAULT          0x0
-#define GC_GPIO_MASKLOWBYTE_7FC_OFFSET           0x7fc
-#define GC_GPIO_MASKLOWBYTE_7FC_DEFAULT          0x0
-#define GC_GPIO_MASKHIGHBYTE_800_OFFSET          0x800
-#define GC_GPIO_MASKHIGHBYTE_800_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_804_OFFSET          0x804
-#define GC_GPIO_MASKHIGHBYTE_804_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_808_OFFSET          0x808
-#define GC_GPIO_MASKHIGHBYTE_808_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_80C_OFFSET          0x80c
-#define GC_GPIO_MASKHIGHBYTE_80C_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_810_OFFSET          0x810
-#define GC_GPIO_MASKHIGHBYTE_810_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_814_OFFSET          0x814
-#define GC_GPIO_MASKHIGHBYTE_814_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_818_OFFSET          0x818
-#define GC_GPIO_MASKHIGHBYTE_818_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_81C_OFFSET          0x81c
-#define GC_GPIO_MASKHIGHBYTE_81C_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_820_OFFSET          0x820
-#define GC_GPIO_MASKHIGHBYTE_820_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_824_OFFSET          0x824
-#define GC_GPIO_MASKHIGHBYTE_824_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_828_OFFSET          0x828
-#define GC_GPIO_MASKHIGHBYTE_828_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_82C_OFFSET          0x82c
-#define GC_GPIO_MASKHIGHBYTE_82C_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_830_OFFSET          0x830
-#define GC_GPIO_MASKHIGHBYTE_830_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_834_OFFSET          0x834
-#define GC_GPIO_MASKHIGHBYTE_834_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_838_OFFSET          0x838
-#define GC_GPIO_MASKHIGHBYTE_838_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_83C_OFFSET          0x83c
-#define GC_GPIO_MASKHIGHBYTE_83C_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_840_OFFSET          0x840
-#define GC_GPIO_MASKHIGHBYTE_840_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_844_OFFSET          0x844
-#define GC_GPIO_MASKHIGHBYTE_844_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_848_OFFSET          0x848
-#define GC_GPIO_MASKHIGHBYTE_848_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_84C_OFFSET          0x84c
-#define GC_GPIO_MASKHIGHBYTE_84C_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_850_OFFSET          0x850
-#define GC_GPIO_MASKHIGHBYTE_850_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_854_OFFSET          0x854
-#define GC_GPIO_MASKHIGHBYTE_854_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_858_OFFSET          0x858
-#define GC_GPIO_MASKHIGHBYTE_858_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_85C_OFFSET          0x85c
-#define GC_GPIO_MASKHIGHBYTE_85C_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_860_OFFSET          0x860
-#define GC_GPIO_MASKHIGHBYTE_860_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_864_OFFSET          0x864
-#define GC_GPIO_MASKHIGHBYTE_864_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_868_OFFSET          0x868
-#define GC_GPIO_MASKHIGHBYTE_868_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_86C_OFFSET          0x86c
-#define GC_GPIO_MASKHIGHBYTE_86C_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_870_OFFSET          0x870
-#define GC_GPIO_MASKHIGHBYTE_870_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_874_OFFSET          0x874
-#define GC_GPIO_MASKHIGHBYTE_874_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_878_OFFSET          0x878
-#define GC_GPIO_MASKHIGHBYTE_878_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_87C_OFFSET          0x87c
-#define GC_GPIO_MASKHIGHBYTE_87C_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_880_OFFSET          0x880
-#define GC_GPIO_MASKHIGHBYTE_880_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_884_OFFSET          0x884
-#define GC_GPIO_MASKHIGHBYTE_884_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_888_OFFSET          0x888
-#define GC_GPIO_MASKHIGHBYTE_888_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_88C_OFFSET          0x88c
-#define GC_GPIO_MASKHIGHBYTE_88C_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_890_OFFSET          0x890
-#define GC_GPIO_MASKHIGHBYTE_890_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_894_OFFSET          0x894
-#define GC_GPIO_MASKHIGHBYTE_894_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_898_OFFSET          0x898
-#define GC_GPIO_MASKHIGHBYTE_898_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_89C_OFFSET          0x89c
-#define GC_GPIO_MASKHIGHBYTE_89C_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_8A0_OFFSET          0x8a0
-#define GC_GPIO_MASKHIGHBYTE_8A0_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_8A4_OFFSET          0x8a4
-#define GC_GPIO_MASKHIGHBYTE_8A4_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_8A8_OFFSET          0x8a8
-#define GC_GPIO_MASKHIGHBYTE_8A8_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_8AC_OFFSET          0x8ac
-#define GC_GPIO_MASKHIGHBYTE_8AC_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_8B0_OFFSET          0x8b0
-#define GC_GPIO_MASKHIGHBYTE_8B0_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_8B4_OFFSET          0x8b4
-#define GC_GPIO_MASKHIGHBYTE_8B4_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_8B8_OFFSET          0x8b8
-#define GC_GPIO_MASKHIGHBYTE_8B8_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_8BC_OFFSET          0x8bc
-#define GC_GPIO_MASKHIGHBYTE_8BC_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_8C0_OFFSET          0x8c0
-#define GC_GPIO_MASKHIGHBYTE_8C0_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_8C4_OFFSET          0x8c4
-#define GC_GPIO_MASKHIGHBYTE_8C4_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_8C8_OFFSET          0x8c8
-#define GC_GPIO_MASKHIGHBYTE_8C8_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_8CC_OFFSET          0x8cc
-#define GC_GPIO_MASKHIGHBYTE_8CC_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_8D0_OFFSET          0x8d0
-#define GC_GPIO_MASKHIGHBYTE_8D0_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_8D4_OFFSET          0x8d4
-#define GC_GPIO_MASKHIGHBYTE_8D4_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_8D8_OFFSET          0x8d8
-#define GC_GPIO_MASKHIGHBYTE_8D8_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_8DC_OFFSET          0x8dc
-#define GC_GPIO_MASKHIGHBYTE_8DC_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_8E0_OFFSET          0x8e0
-#define GC_GPIO_MASKHIGHBYTE_8E0_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_8E4_OFFSET          0x8e4
-#define GC_GPIO_MASKHIGHBYTE_8E4_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_8E8_OFFSET          0x8e8
-#define GC_GPIO_MASKHIGHBYTE_8E8_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_8EC_OFFSET          0x8ec
-#define GC_GPIO_MASKHIGHBYTE_8EC_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_8F0_OFFSET          0x8f0
-#define GC_GPIO_MASKHIGHBYTE_8F0_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_8F4_OFFSET          0x8f4
-#define GC_GPIO_MASKHIGHBYTE_8F4_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_8F8_OFFSET          0x8f8
-#define GC_GPIO_MASKHIGHBYTE_8F8_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_8FC_OFFSET          0x8fc
-#define GC_GPIO_MASKHIGHBYTE_8FC_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_900_OFFSET          0x900
-#define GC_GPIO_MASKHIGHBYTE_900_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_904_OFFSET          0x904
-#define GC_GPIO_MASKHIGHBYTE_904_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_908_OFFSET          0x908
-#define GC_GPIO_MASKHIGHBYTE_908_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_90C_OFFSET          0x90c
-#define GC_GPIO_MASKHIGHBYTE_90C_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_910_OFFSET          0x910
-#define GC_GPIO_MASKHIGHBYTE_910_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_914_OFFSET          0x914
-#define GC_GPIO_MASKHIGHBYTE_914_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_918_OFFSET          0x918
-#define GC_GPIO_MASKHIGHBYTE_918_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_91C_OFFSET          0x91c
-#define GC_GPIO_MASKHIGHBYTE_91C_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_920_OFFSET          0x920
-#define GC_GPIO_MASKHIGHBYTE_920_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_924_OFFSET          0x924
-#define GC_GPIO_MASKHIGHBYTE_924_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_928_OFFSET          0x928
-#define GC_GPIO_MASKHIGHBYTE_928_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_92C_OFFSET          0x92c
-#define GC_GPIO_MASKHIGHBYTE_92C_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_930_OFFSET          0x930
-#define GC_GPIO_MASKHIGHBYTE_930_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_934_OFFSET          0x934
-#define GC_GPIO_MASKHIGHBYTE_934_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_938_OFFSET          0x938
-#define GC_GPIO_MASKHIGHBYTE_938_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_93C_OFFSET          0x93c
-#define GC_GPIO_MASKHIGHBYTE_93C_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_940_OFFSET          0x940
-#define GC_GPIO_MASKHIGHBYTE_940_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_944_OFFSET          0x944
-#define GC_GPIO_MASKHIGHBYTE_944_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_948_OFFSET          0x948
-#define GC_GPIO_MASKHIGHBYTE_948_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_94C_OFFSET          0x94c
-#define GC_GPIO_MASKHIGHBYTE_94C_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_950_OFFSET          0x950
-#define GC_GPIO_MASKHIGHBYTE_950_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_954_OFFSET          0x954
-#define GC_GPIO_MASKHIGHBYTE_954_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_958_OFFSET          0x958
-#define GC_GPIO_MASKHIGHBYTE_958_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_95C_OFFSET          0x95c
-#define GC_GPIO_MASKHIGHBYTE_95C_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_960_OFFSET          0x960
-#define GC_GPIO_MASKHIGHBYTE_960_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_964_OFFSET          0x964
-#define GC_GPIO_MASKHIGHBYTE_964_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_968_OFFSET          0x968
-#define GC_GPIO_MASKHIGHBYTE_968_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_96C_OFFSET          0x96c
-#define GC_GPIO_MASKHIGHBYTE_96C_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_970_OFFSET          0x970
-#define GC_GPIO_MASKHIGHBYTE_970_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_974_OFFSET          0x974
-#define GC_GPIO_MASKHIGHBYTE_974_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_978_OFFSET          0x978
-#define GC_GPIO_MASKHIGHBYTE_978_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_97C_OFFSET          0x97c
-#define GC_GPIO_MASKHIGHBYTE_97C_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_980_OFFSET          0x980
-#define GC_GPIO_MASKHIGHBYTE_980_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_984_OFFSET          0x984
-#define GC_GPIO_MASKHIGHBYTE_984_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_988_OFFSET          0x988
-#define GC_GPIO_MASKHIGHBYTE_988_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_98C_OFFSET          0x98c
-#define GC_GPIO_MASKHIGHBYTE_98C_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_990_OFFSET          0x990
-#define GC_GPIO_MASKHIGHBYTE_990_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_994_OFFSET          0x994
-#define GC_GPIO_MASKHIGHBYTE_994_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_998_OFFSET          0x998
-#define GC_GPIO_MASKHIGHBYTE_998_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_99C_OFFSET          0x99c
-#define GC_GPIO_MASKHIGHBYTE_99C_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_9A0_OFFSET          0x9a0
-#define GC_GPIO_MASKHIGHBYTE_9A0_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_9A4_OFFSET          0x9a4
-#define GC_GPIO_MASKHIGHBYTE_9A4_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_9A8_OFFSET          0x9a8
-#define GC_GPIO_MASKHIGHBYTE_9A8_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_9AC_OFFSET          0x9ac
-#define GC_GPIO_MASKHIGHBYTE_9AC_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_9B0_OFFSET          0x9b0
-#define GC_GPIO_MASKHIGHBYTE_9B0_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_9B4_OFFSET          0x9b4
-#define GC_GPIO_MASKHIGHBYTE_9B4_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_9B8_OFFSET          0x9b8
-#define GC_GPIO_MASKHIGHBYTE_9B8_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_9BC_OFFSET          0x9bc
-#define GC_GPIO_MASKHIGHBYTE_9BC_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_9C0_OFFSET          0x9c0
-#define GC_GPIO_MASKHIGHBYTE_9C0_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_9C4_OFFSET          0x9c4
-#define GC_GPIO_MASKHIGHBYTE_9C4_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_9C8_OFFSET          0x9c8
-#define GC_GPIO_MASKHIGHBYTE_9C8_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_9CC_OFFSET          0x9cc
-#define GC_GPIO_MASKHIGHBYTE_9CC_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_9D0_OFFSET          0x9d0
-#define GC_GPIO_MASKHIGHBYTE_9D0_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_9D4_OFFSET          0x9d4
-#define GC_GPIO_MASKHIGHBYTE_9D4_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_9D8_OFFSET          0x9d8
-#define GC_GPIO_MASKHIGHBYTE_9D8_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_9DC_OFFSET          0x9dc
-#define GC_GPIO_MASKHIGHBYTE_9DC_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_9E0_OFFSET          0x9e0
-#define GC_GPIO_MASKHIGHBYTE_9E0_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_9E4_OFFSET          0x9e4
-#define GC_GPIO_MASKHIGHBYTE_9E4_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_9E8_OFFSET          0x9e8
-#define GC_GPIO_MASKHIGHBYTE_9E8_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_9EC_OFFSET          0x9ec
-#define GC_GPIO_MASKHIGHBYTE_9EC_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_9F0_OFFSET          0x9f0
-#define GC_GPIO_MASKHIGHBYTE_9F0_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_9F4_OFFSET          0x9f4
-#define GC_GPIO_MASKHIGHBYTE_9F4_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_9F8_OFFSET          0x9f8
-#define GC_GPIO_MASKHIGHBYTE_9F8_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_9FC_OFFSET          0x9fc
-#define GC_GPIO_MASKHIGHBYTE_9FC_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_A00_OFFSET          0xa00
-#define GC_GPIO_MASKHIGHBYTE_A00_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_A04_OFFSET          0xa04
-#define GC_GPIO_MASKHIGHBYTE_A04_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_A08_OFFSET          0xa08
-#define GC_GPIO_MASKHIGHBYTE_A08_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_A0C_OFFSET          0xa0c
-#define GC_GPIO_MASKHIGHBYTE_A0C_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_A10_OFFSET          0xa10
-#define GC_GPIO_MASKHIGHBYTE_A10_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_A14_OFFSET          0xa14
-#define GC_GPIO_MASKHIGHBYTE_A14_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_A18_OFFSET          0xa18
-#define GC_GPIO_MASKHIGHBYTE_A18_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_A1C_OFFSET          0xa1c
-#define GC_GPIO_MASKHIGHBYTE_A1C_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_A20_OFFSET          0xa20
-#define GC_GPIO_MASKHIGHBYTE_A20_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_A24_OFFSET          0xa24
-#define GC_GPIO_MASKHIGHBYTE_A24_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_A28_OFFSET          0xa28
-#define GC_GPIO_MASKHIGHBYTE_A28_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_A2C_OFFSET          0xa2c
-#define GC_GPIO_MASKHIGHBYTE_A2C_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_A30_OFFSET          0xa30
-#define GC_GPIO_MASKHIGHBYTE_A30_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_A34_OFFSET          0xa34
-#define GC_GPIO_MASKHIGHBYTE_A34_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_A38_OFFSET          0xa38
-#define GC_GPIO_MASKHIGHBYTE_A38_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_A3C_OFFSET          0xa3c
-#define GC_GPIO_MASKHIGHBYTE_A3C_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_A40_OFFSET          0xa40
-#define GC_GPIO_MASKHIGHBYTE_A40_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_A44_OFFSET          0xa44
-#define GC_GPIO_MASKHIGHBYTE_A44_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_A48_OFFSET          0xa48
-#define GC_GPIO_MASKHIGHBYTE_A48_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_A4C_OFFSET          0xa4c
-#define GC_GPIO_MASKHIGHBYTE_A4C_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_A50_OFFSET          0xa50
-#define GC_GPIO_MASKHIGHBYTE_A50_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_A54_OFFSET          0xa54
-#define GC_GPIO_MASKHIGHBYTE_A54_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_A58_OFFSET          0xa58
-#define GC_GPIO_MASKHIGHBYTE_A58_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_A5C_OFFSET          0xa5c
-#define GC_GPIO_MASKHIGHBYTE_A5C_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_A60_OFFSET          0xa60
-#define GC_GPIO_MASKHIGHBYTE_A60_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_A64_OFFSET          0xa64
-#define GC_GPIO_MASKHIGHBYTE_A64_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_A68_OFFSET          0xa68
-#define GC_GPIO_MASKHIGHBYTE_A68_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_A6C_OFFSET          0xa6c
-#define GC_GPIO_MASKHIGHBYTE_A6C_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_A70_OFFSET          0xa70
-#define GC_GPIO_MASKHIGHBYTE_A70_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_A74_OFFSET          0xa74
-#define GC_GPIO_MASKHIGHBYTE_A74_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_A78_OFFSET          0xa78
-#define GC_GPIO_MASKHIGHBYTE_A78_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_A7C_OFFSET          0xa7c
-#define GC_GPIO_MASKHIGHBYTE_A7C_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_A80_OFFSET          0xa80
-#define GC_GPIO_MASKHIGHBYTE_A80_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_A84_OFFSET          0xa84
-#define GC_GPIO_MASKHIGHBYTE_A84_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_A88_OFFSET          0xa88
-#define GC_GPIO_MASKHIGHBYTE_A88_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_A8C_OFFSET          0xa8c
-#define GC_GPIO_MASKHIGHBYTE_A8C_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_A90_OFFSET          0xa90
-#define GC_GPIO_MASKHIGHBYTE_A90_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_A94_OFFSET          0xa94
-#define GC_GPIO_MASKHIGHBYTE_A94_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_A98_OFFSET          0xa98
-#define GC_GPIO_MASKHIGHBYTE_A98_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_A9C_OFFSET          0xa9c
-#define GC_GPIO_MASKHIGHBYTE_A9C_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_AA0_OFFSET          0xaa0
-#define GC_GPIO_MASKHIGHBYTE_AA0_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_AA4_OFFSET          0xaa4
-#define GC_GPIO_MASKHIGHBYTE_AA4_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_AA8_OFFSET          0xaa8
-#define GC_GPIO_MASKHIGHBYTE_AA8_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_AAC_OFFSET          0xaac
-#define GC_GPIO_MASKHIGHBYTE_AAC_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_AB0_OFFSET          0xab0
-#define GC_GPIO_MASKHIGHBYTE_AB0_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_AB4_OFFSET          0xab4
-#define GC_GPIO_MASKHIGHBYTE_AB4_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_AB8_OFFSET          0xab8
-#define GC_GPIO_MASKHIGHBYTE_AB8_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_ABC_OFFSET          0xabc
-#define GC_GPIO_MASKHIGHBYTE_ABC_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_AC0_OFFSET          0xac0
-#define GC_GPIO_MASKHIGHBYTE_AC0_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_AC4_OFFSET          0xac4
-#define GC_GPIO_MASKHIGHBYTE_AC4_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_AC8_OFFSET          0xac8
-#define GC_GPIO_MASKHIGHBYTE_AC8_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_ACC_OFFSET          0xacc
-#define GC_GPIO_MASKHIGHBYTE_ACC_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_AD0_OFFSET          0xad0
-#define GC_GPIO_MASKHIGHBYTE_AD0_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_AD4_OFFSET          0xad4
-#define GC_GPIO_MASKHIGHBYTE_AD4_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_AD8_OFFSET          0xad8
-#define GC_GPIO_MASKHIGHBYTE_AD8_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_ADC_OFFSET          0xadc
-#define GC_GPIO_MASKHIGHBYTE_ADC_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_AE0_OFFSET          0xae0
-#define GC_GPIO_MASKHIGHBYTE_AE0_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_AE4_OFFSET          0xae4
-#define GC_GPIO_MASKHIGHBYTE_AE4_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_AE8_OFFSET          0xae8
-#define GC_GPIO_MASKHIGHBYTE_AE8_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_AEC_OFFSET          0xaec
-#define GC_GPIO_MASKHIGHBYTE_AEC_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_AF0_OFFSET          0xaf0
-#define GC_GPIO_MASKHIGHBYTE_AF0_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_AF4_OFFSET          0xaf4
-#define GC_GPIO_MASKHIGHBYTE_AF4_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_AF8_OFFSET          0xaf8
-#define GC_GPIO_MASKHIGHBYTE_AF8_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_AFC_OFFSET          0xafc
-#define GC_GPIO_MASKHIGHBYTE_AFC_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_B00_OFFSET          0xb00
-#define GC_GPIO_MASKHIGHBYTE_B00_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_B04_OFFSET          0xb04
-#define GC_GPIO_MASKHIGHBYTE_B04_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_B08_OFFSET          0xb08
-#define GC_GPIO_MASKHIGHBYTE_B08_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_B0C_OFFSET          0xb0c
-#define GC_GPIO_MASKHIGHBYTE_B0C_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_B10_OFFSET          0xb10
-#define GC_GPIO_MASKHIGHBYTE_B10_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_B14_OFFSET          0xb14
-#define GC_GPIO_MASKHIGHBYTE_B14_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_B18_OFFSET          0xb18
-#define GC_GPIO_MASKHIGHBYTE_B18_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_B1C_OFFSET          0xb1c
-#define GC_GPIO_MASKHIGHBYTE_B1C_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_B20_OFFSET          0xb20
-#define GC_GPIO_MASKHIGHBYTE_B20_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_B24_OFFSET          0xb24
-#define GC_GPIO_MASKHIGHBYTE_B24_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_B28_OFFSET          0xb28
-#define GC_GPIO_MASKHIGHBYTE_B28_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_B2C_OFFSET          0xb2c
-#define GC_GPIO_MASKHIGHBYTE_B2C_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_B30_OFFSET          0xb30
-#define GC_GPIO_MASKHIGHBYTE_B30_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_B34_OFFSET          0xb34
-#define GC_GPIO_MASKHIGHBYTE_B34_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_B38_OFFSET          0xb38
-#define GC_GPIO_MASKHIGHBYTE_B38_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_B3C_OFFSET          0xb3c
-#define GC_GPIO_MASKHIGHBYTE_B3C_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_B40_OFFSET          0xb40
-#define GC_GPIO_MASKHIGHBYTE_B40_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_B44_OFFSET          0xb44
-#define GC_GPIO_MASKHIGHBYTE_B44_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_B48_OFFSET          0xb48
-#define GC_GPIO_MASKHIGHBYTE_B48_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_B4C_OFFSET          0xb4c
-#define GC_GPIO_MASKHIGHBYTE_B4C_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_B50_OFFSET          0xb50
-#define GC_GPIO_MASKHIGHBYTE_B50_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_B54_OFFSET          0xb54
-#define GC_GPIO_MASKHIGHBYTE_B54_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_B58_OFFSET          0xb58
-#define GC_GPIO_MASKHIGHBYTE_B58_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_B5C_OFFSET          0xb5c
-#define GC_GPIO_MASKHIGHBYTE_B5C_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_B60_OFFSET          0xb60
-#define GC_GPIO_MASKHIGHBYTE_B60_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_B64_OFFSET          0xb64
-#define GC_GPIO_MASKHIGHBYTE_B64_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_B68_OFFSET          0xb68
-#define GC_GPIO_MASKHIGHBYTE_B68_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_B6C_OFFSET          0xb6c
-#define GC_GPIO_MASKHIGHBYTE_B6C_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_B70_OFFSET          0xb70
-#define GC_GPIO_MASKHIGHBYTE_B70_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_B74_OFFSET          0xb74
-#define GC_GPIO_MASKHIGHBYTE_B74_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_B78_OFFSET          0xb78
-#define GC_GPIO_MASKHIGHBYTE_B78_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_B7C_OFFSET          0xb7c
-#define GC_GPIO_MASKHIGHBYTE_B7C_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_B80_OFFSET          0xb80
-#define GC_GPIO_MASKHIGHBYTE_B80_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_B84_OFFSET          0xb84
-#define GC_GPIO_MASKHIGHBYTE_B84_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_B88_OFFSET          0xb88
-#define GC_GPIO_MASKHIGHBYTE_B88_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_B8C_OFFSET          0xb8c
-#define GC_GPIO_MASKHIGHBYTE_B8C_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_B90_OFFSET          0xb90
-#define GC_GPIO_MASKHIGHBYTE_B90_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_B94_OFFSET          0xb94
-#define GC_GPIO_MASKHIGHBYTE_B94_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_B98_OFFSET          0xb98
-#define GC_GPIO_MASKHIGHBYTE_B98_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_B9C_OFFSET          0xb9c
-#define GC_GPIO_MASKHIGHBYTE_B9C_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_BA0_OFFSET          0xba0
-#define GC_GPIO_MASKHIGHBYTE_BA0_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_BA4_OFFSET          0xba4
-#define GC_GPIO_MASKHIGHBYTE_BA4_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_BA8_OFFSET          0xba8
-#define GC_GPIO_MASKHIGHBYTE_BA8_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_BAC_OFFSET          0xbac
-#define GC_GPIO_MASKHIGHBYTE_BAC_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_BB0_OFFSET          0xbb0
-#define GC_GPIO_MASKHIGHBYTE_BB0_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_BB4_OFFSET          0xbb4
-#define GC_GPIO_MASKHIGHBYTE_BB4_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_BB8_OFFSET          0xbb8
-#define GC_GPIO_MASKHIGHBYTE_BB8_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_BBC_OFFSET          0xbbc
-#define GC_GPIO_MASKHIGHBYTE_BBC_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_BC0_OFFSET          0xbc0
-#define GC_GPIO_MASKHIGHBYTE_BC0_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_BC4_OFFSET          0xbc4
-#define GC_GPIO_MASKHIGHBYTE_BC4_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_BC8_OFFSET          0xbc8
-#define GC_GPIO_MASKHIGHBYTE_BC8_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_BCC_OFFSET          0xbcc
-#define GC_GPIO_MASKHIGHBYTE_BCC_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_BD0_OFFSET          0xbd0
-#define GC_GPIO_MASKHIGHBYTE_BD0_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_BD4_OFFSET          0xbd4
-#define GC_GPIO_MASKHIGHBYTE_BD4_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_BD8_OFFSET          0xbd8
-#define GC_GPIO_MASKHIGHBYTE_BD8_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_BDC_OFFSET          0xbdc
-#define GC_GPIO_MASKHIGHBYTE_BDC_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_BE0_OFFSET          0xbe0
-#define GC_GPIO_MASKHIGHBYTE_BE0_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_BE4_OFFSET          0xbe4
-#define GC_GPIO_MASKHIGHBYTE_BE4_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_BE8_OFFSET          0xbe8
-#define GC_GPIO_MASKHIGHBYTE_BE8_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_BEC_OFFSET          0xbec
-#define GC_GPIO_MASKHIGHBYTE_BEC_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_BF0_OFFSET          0xbf0
-#define GC_GPIO_MASKHIGHBYTE_BF0_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_BF4_OFFSET          0xbf4
-#define GC_GPIO_MASKHIGHBYTE_BF4_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_BF8_OFFSET          0xbf8
-#define GC_GPIO_MASKHIGHBYTE_BF8_DEFAULT         0x0
-#define GC_GPIO_MASKHIGHBYTE_BFC_OFFSET          0xbfc
-#define GC_GPIO_MASKHIGHBYTE_BFC_DEFAULT         0x0
-#define GC_GPIO_ARMPID4_OFFSET                   0xfd0
-#define GC_GPIO_ARMPID4_DEFAULT                  0x4
-#define GC_GPIO_ARMPID5_OFFSET                   0xfd4
-#define GC_GPIO_ARMPID5_DEFAULT                  0x0
-#define GC_GPIO_ARMPID6_OFFSET                   0xfd8
-#define GC_GPIO_ARMPID6_DEFAULT                  0x0
-#define GC_GPIO_ARMPID7_OFFSET                   0xfdc
-#define GC_GPIO_ARMPID7_DEFAULT                  0x0
-#define GC_GPIO_ARMPID0_OFFSET                   0xfe0
-#define GC_GPIO_ARMPID0_DEFAULT                  0x20
-#define GC_GPIO_ARMPID1_OFFSET                   0xfe4
-#define GC_GPIO_ARMPID1_DEFAULT                  0xb8
-#define GC_GPIO_ARMPID2_OFFSET                   0xfe8
-#define GC_GPIO_ARMPID2_DEFAULT                  0xb
-#define GC_GPIO_ARMPID3_OFFSET                   0xfec
-#define GC_GPIO_ARMPID3_DEFAULT                  0x0
-#define GC_GPIO_ARMCID0_OFFSET                   0xff0
-#define GC_GPIO_ARMCID0_DEFAULT                  0xd
-#define GC_GPIO_ARMCID1_OFFSET                   0xff4
-#define GC_GPIO_ARMCID1_DEFAULT                  0xf0
-#define GC_GPIO_ARMCID2_OFFSET                   0xff8
-#define GC_GPIO_ARMCID2_DEFAULT                  0x5
-#define GC_GPIO_ARMCID3_OFFSET                   0xffc
-#define GC_GPIO_ARMCID3_DEFAULT                  0xb1
-#define GC_I2C_CTRL_MODE_OFFSET                  0x0
-#define GC_I2C_CTRL_MODE_DEFAULT                 0x0
-#define GC_I2C_CTRL_CLKDIV_OFFSET                0x4
-#define GC_I2C_CTRL_CLKDIV_DEFAULT               0xa
-#define GC_I2C_CTRL_PHASESTEPS_OFFSET            0x8
-#define GC_I2C_CTRL_PHASESTEPS_DEFAULT           0x188186
-#define GC_I2C_CTRL_SDA_VAL_OFFSET               0xc
-#define GC_I2C_CTRL_SDA_VAL_DEFAULT              0x1897f0f
-#define GC_I2C_CTRL_SDA_OVRD_OFFSET              0x10
-#define GC_I2C_CTRL_SDA_OVRD_DEFAULT             0x300
-#define GC_I2C_CTRL_SCL_VAL_OFFSET               0x14
-#define GC_I2C_CTRL_SCL_VAL_DEFAULT              0x67666e
-#define GC_I2C_CTRL_SCL_OVRD_OFFSET              0x18
-#define GC_I2C_CTRL_SCL_OVRD_DEFAULT             0x600
-#define GC_I2C_CTRL_INT_EN_OFFSET                0x1c
-#define GC_I2C_CTRL_INT_EN_DEFAULT               0x1
-#define GC_I2C_CTRL_AL_OFFSET                    0x20
-#define GC_I2C_CTRL_AL_DEFAULT                   0x1f
-#define GC_I2C_CTRL_CS_OFFSET                    0x24
-#define GC_I2C_CTRL_CS_DEFAULT                   0x13883
-#define GC_I2C_INST_OFFSET                       0x28
-#define GC_I2C_INST_DEFAULT                      0x0
-#define GC_I2C_STATUS_OFFSET                     0x2c
-#define GC_I2C_STATUS_DEFAULT                    0x0
-#define GC_I2C_FW_OFFSET                         0x30
-#define GC_I2C_FW_DEFAULT                        0x0
-#define GC_I2C_RW_PTR_OFFSET                     0x34
-#define GC_I2C_RW_PTR_DEFAULT                    0x0
-#define GC_I2C_RW0_OFFSET                        0x38
-#define GC_I2C_RW0_DEFAULT                       0x0
-#define GC_I2C_RW1_OFFSET                        0x3c
-#define GC_I2C_RW1_DEFAULT                       0x0
-#define GC_I2C_RW2_OFFSET                        0x40
-#define GC_I2C_RW2_DEFAULT                       0x0
-#define GC_I2C_RW3_OFFSET                        0x44
-#define GC_I2C_RW3_DEFAULT                       0x0
-#define GC_I2C_RW4_OFFSET                        0x48
-#define GC_I2C_RW4_DEFAULT                       0x0
-#define GC_I2C_RW5_OFFSET                        0x4c
-#define GC_I2C_RW5_DEFAULT                       0x0
-#define GC_I2C_RW6_OFFSET                        0x50
-#define GC_I2C_RW6_DEFAULT                       0x0
-#define GC_I2C_RW7_OFFSET                        0x54
-#define GC_I2C_RW7_DEFAULT                       0x0
-#define GC_I2C_RW8_OFFSET                        0x58
-#define GC_I2C_RW8_DEFAULT                       0x0
-#define GC_I2C_RW9_OFFSET                        0x5c
-#define GC_I2C_RW9_DEFAULT                       0x0
-#define GC_I2C_RW10_OFFSET                       0x60
-#define GC_I2C_RW10_DEFAULT                      0x0
-#define GC_I2C_RW11_OFFSET                       0x64
-#define GC_I2C_RW11_DEFAULT                      0x0
-#define GC_I2C_RW12_OFFSET                       0x68
-#define GC_I2C_RW12_DEFAULT                      0x0
-#define GC_I2C_RW13_OFFSET                       0x6c
-#define GC_I2C_RW13_DEFAULT                      0x0
-#define GC_I2C_RW14_OFFSET                       0x70
-#define GC_I2C_RW14_DEFAULT                      0x0
-#define GC_I2C_RW15_OFFSET                       0x74
-#define GC_I2C_RW15_DEFAULT                      0x0
-#define GC_I2C_READVAL_OFFSET                    0x78
-#define GC_I2C_READVAL_DEFAULT                   0x0
-#define GC_I2C_CTRL_MSR_OFFSET                   0x7c
-#define GC_I2C_CTRL_MSR_DEFAULT                  0xa
-#define GC_I2C_ITCR_OFFSET                       0xf00
-#define GC_I2C_ITCR_DEFAULT                      0x0
-#define GC_I2C_ITOP_OFFSET                       0xf04
-#define GC_I2C_ITOP_DEFAULT                      0x0
-#define GC_I2CS_VERSION_OFFSET                   0x0
-#define GC_I2CS_VERSION_DEFAULT                  0x101424a
-#define GC_I2CS_INT_ENABLE_OFFSET                0x4
-#define GC_I2CS_INT_ENABLE_DEFAULT               0x0
-#define GC_I2CS_INT_STATE_OFFSET                 0x8
-#define GC_I2CS_INT_STATE_DEFAULT                0x0
-#define GC_I2CS_INT_TEST_OFFSET                  0xc
-#define GC_I2CS_INT_TEST_DEFAULT                 0x0
-#define GC_I2CS_CTRL_SDA_VAL_OFFSET              0x10
-#define GC_I2CS_CTRL_SDA_VAL_DEFAULT             0x3d
-#define GC_I2CS_SLAVE_DEVADDRVAL_OFFSET          0x14
-#define GC_I2CS_SLAVE_DEVADDRVAL_DEFAULT         0x0
-#define GC_I2CS_CLOCK_STRETCH_OFFSET             0x18
-#define GC_I2CS_CLOCK_STRETCH_DEFAULT            0x0
-#define GC_I2CS_AUTO_WAIT_AFTER_WRITE_MODE_OFFSET 0x1c
-#define GC_I2CS_AUTO_WAIT_AFTER_WRITE_MODE_DEFAULT 0x0
-#define GC_I2CS_CLOCK_STRETCH_MODE_OFFSET        0x20
-#define GC_I2CS_CLOCK_STRETCH_MODE_DEFAULT       0x0
-#define GC_I2CS_READ_PTR_OFFSET                  0x24
-#define GC_I2CS_READ_PTR_DEFAULT                 0x0
-#define GC_I2CS_WRITE_PTR_OFFSET                 0x28
-#define GC_I2CS_WRITE_PTR_DEFAULT                0x0
-#define GC_I2CS_READVAL_OFFSET                   0x2c
-#define GC_I2CS_READVAL_DEFAULT                  0x0
-#define GC_I2CS_CTRL_MSR_OFFSET                  0x30
-#define GC_I2CS_CTRL_MSR_DEFAULT                 0xa
-#define GC_I2CS_READ_BUFFER0_OFFSET              0x34
-#define GC_I2CS_READ_BUFFER0_DEFAULT             0x0
-#define GC_I2CS_READ_BUFFER1_OFFSET              0x38
-#define GC_I2CS_READ_BUFFER1_DEFAULT             0x0
-#define GC_I2CS_READ_BUFFER2_OFFSET              0x3c
-#define GC_I2CS_READ_BUFFER2_DEFAULT             0x0
-#define GC_I2CS_READ_BUFFER3_OFFSET              0x40
-#define GC_I2CS_READ_BUFFER3_DEFAULT             0x0
-#define GC_I2CS_READ_BUFFER4_OFFSET              0x44
-#define GC_I2CS_READ_BUFFER4_DEFAULT             0x0
-#define GC_I2CS_READ_BUFFER5_OFFSET              0x48
-#define GC_I2CS_READ_BUFFER5_DEFAULT             0x0
-#define GC_I2CS_READ_BUFFER6_OFFSET              0x4c
-#define GC_I2CS_READ_BUFFER6_DEFAULT             0x0
-#define GC_I2CS_READ_BUFFER7_OFFSET              0x50
-#define GC_I2CS_READ_BUFFER7_DEFAULT             0x0
-#define GC_I2CS_READ_BUFFER8_OFFSET              0x54
-#define GC_I2CS_READ_BUFFER8_DEFAULT             0x0
-#define GC_I2CS_READ_BUFFER9_OFFSET              0x58
-#define GC_I2CS_READ_BUFFER9_DEFAULT             0x0
-#define GC_I2CS_READ_BUFFER10_OFFSET             0x5c
-#define GC_I2CS_READ_BUFFER10_DEFAULT            0x0
-#define GC_I2CS_READ_BUFFER11_OFFSET             0x60
-#define GC_I2CS_READ_BUFFER11_DEFAULT            0x0
-#define GC_I2CS_READ_BUFFER12_OFFSET             0x64
-#define GC_I2CS_READ_BUFFER12_DEFAULT            0x0
-#define GC_I2CS_READ_BUFFER13_OFFSET             0x68
-#define GC_I2CS_READ_BUFFER13_DEFAULT            0x0
-#define GC_I2CS_READ_BUFFER14_OFFSET             0x6c
-#define GC_I2CS_READ_BUFFER14_DEFAULT            0x0
-#define GC_I2CS_READ_BUFFER15_OFFSET             0x70
-#define GC_I2CS_READ_BUFFER15_DEFAULT            0x0
-#define GC_I2CS_WRITE_BUFFER0_OFFSET             0x74
-#define GC_I2CS_WRITE_BUFFER0_DEFAULT            0x0
-#define GC_I2CS_WRITE_BUFFER1_OFFSET             0x78
-#define GC_I2CS_WRITE_BUFFER1_DEFAULT            0x0
-#define GC_I2CS_WRITE_BUFFER2_OFFSET             0x7c
-#define GC_I2CS_WRITE_BUFFER2_DEFAULT            0x0
-#define GC_I2CS_WRITE_BUFFER3_OFFSET             0x80
-#define GC_I2CS_WRITE_BUFFER3_DEFAULT            0x0
-#define GC_I2CS_WRITE_BUFFER4_OFFSET             0x84
-#define GC_I2CS_WRITE_BUFFER4_DEFAULT            0x0
-#define GC_I2CS_WRITE_BUFFER5_OFFSET             0x88
-#define GC_I2CS_WRITE_BUFFER5_DEFAULT            0x0
-#define GC_I2CS_WRITE_BUFFER6_OFFSET             0x8c
-#define GC_I2CS_WRITE_BUFFER6_DEFAULT            0x0
-#define GC_I2CS_WRITE_BUFFER7_OFFSET             0x90
-#define GC_I2CS_WRITE_BUFFER7_DEFAULT            0x0
-#define GC_I2CS_WRITE_BUFFER8_OFFSET             0x94
-#define GC_I2CS_WRITE_BUFFER8_DEFAULT            0x0
-#define GC_I2CS_WRITE_BUFFER9_OFFSET             0x98
-#define GC_I2CS_WRITE_BUFFER9_DEFAULT            0x0
-#define GC_I2CS_WRITE_BUFFER10_OFFSET            0x9c
-#define GC_I2CS_WRITE_BUFFER10_DEFAULT           0x0
-#define GC_I2CS_WRITE_BUFFER11_OFFSET            0xa0
-#define GC_I2CS_WRITE_BUFFER11_DEFAULT           0x0
-#define GC_I2CS_WRITE_BUFFER12_OFFSET            0xa4
-#define GC_I2CS_WRITE_BUFFER12_DEFAULT           0x0
-#define GC_I2CS_WRITE_BUFFER13_OFFSET            0xa8
-#define GC_I2CS_WRITE_BUFFER13_DEFAULT           0x0
-#define GC_I2CS_WRITE_BUFFER14_OFFSET            0xac
-#define GC_I2CS_WRITE_BUFFER14_DEFAULT           0x0
-#define GC_I2CS_WRITE_BUFFER15_OFFSET            0xb0
-#define GC_I2CS_WRITE_BUFFER15_DEFAULT           0x0
-#define GC_KEYMGR_AES_CTRL_OFFSET                0x0
-#define GC_KEYMGR_AES_CTRL_DEFAULT               0x0
-#define GC_KEYMGR_AES_WFIFO_DATA_OFFSET          0x8
-#define GC_KEYMGR_AES_WFIFO_DATA_DEFAULT         0xdeadbeef
-#define GC_KEYMGR_AES_RFIFO_DATA_OFFSET          0xc
-#define GC_KEYMGR_AES_RFIFO_DATA_DEFAULT         0xdeadbeef
-#define GC_KEYMGR_AES_KEY0_OFFSET                0x2c
-#define GC_KEYMGR_AES_KEY0_DEFAULT               0x0
-#define GC_KEYMGR_AES_KEY1_OFFSET                0x30
-#define GC_KEYMGR_AES_KEY1_DEFAULT               0x0
-#define GC_KEYMGR_AES_KEY2_OFFSET                0x34
-#define GC_KEYMGR_AES_KEY2_DEFAULT               0x0
-#define GC_KEYMGR_AES_KEY3_OFFSET                0x38
-#define GC_KEYMGR_AES_KEY3_DEFAULT               0x0
-#define GC_KEYMGR_AES_KEY4_OFFSET                0x3c
-#define GC_KEYMGR_AES_KEY4_DEFAULT               0x0
-#define GC_KEYMGR_AES_KEY5_OFFSET                0x40
-#define GC_KEYMGR_AES_KEY5_DEFAULT               0x0
-#define GC_KEYMGR_AES_KEY6_OFFSET                0x44
-#define GC_KEYMGR_AES_KEY6_DEFAULT               0x0
-#define GC_KEYMGR_AES_KEY7_OFFSET                0x48
-#define GC_KEYMGR_AES_KEY7_DEFAULT               0x0
-#define GC_KEYMGR_AES_KEY_START_OFFSET           0x4c
-#define GC_KEYMGR_AES_KEY_START_DEFAULT          0x0
-#define GC_KEYMGR_AES_CTR0_OFFSET                0x50
-#define GC_KEYMGR_AES_CTR0_DEFAULT               0x0
-#define GC_KEYMGR_AES_CTR1_OFFSET                0x54
-#define GC_KEYMGR_AES_CTR1_DEFAULT               0x0
-#define GC_KEYMGR_AES_CTR2_OFFSET                0x58
-#define GC_KEYMGR_AES_CTR2_DEFAULT               0x0
-#define GC_KEYMGR_AES_CTR3_OFFSET                0x5c
-#define GC_KEYMGR_AES_CTR3_DEFAULT               0x0
-#define GC_KEYMGR_AES_RAND_STALL_CTL_OFFSET      0x60
-#define GC_KEYMGR_AES_RAND_STALL_CTL_DEFAULT     0x7
-#define GC_KEYMGR_AES_WFIFO_LEVEL_OFFSET         0x64
-#define GC_KEYMGR_AES_WFIFO_LEVEL_DEFAULT        0x0
-#define GC_KEYMGR_AES_WFIFO_FULL_OFFSET          0x68
-#define GC_KEYMGR_AES_WFIFO_FULL_DEFAULT         0x0
-#define GC_KEYMGR_AES_RFIFO_LEVEL_OFFSET         0x6c
-#define GC_KEYMGR_AES_RFIFO_LEVEL_DEFAULT        0x0
-#define GC_KEYMGR_AES_RFIFO_EMPTY_OFFSET         0x70
-#define GC_KEYMGR_AES_RFIFO_EMPTY_DEFAULT        0x1
-#define GC_KEYMGR_AES_EXECUTE_COUNT_STATE_OFFSET 0x74
-#define GC_KEYMGR_AES_EXECUTE_COUNT_STATE_DEFAULT 0x0
-#define GC_KEYMGR_AES_EXECUTE_COUNT_MAX_OFFSET   0x78
-#define GC_KEYMGR_AES_EXECUTE_COUNT_MAX_DEFAULT  0x0
-#define GC_KEYMGR_GCM_DO_ACC_OFFSET              0x7c
-#define GC_KEYMGR_GCM_DO_ACC_DEFAULT             0x0
-#define GC_KEYMGR_GCM_H0_OFFSET                  0x80
-#define GC_KEYMGR_GCM_H0_DEFAULT                 0x0
-#define GC_KEYMGR_GCM_H1_OFFSET                  0x84
-#define GC_KEYMGR_GCM_H1_DEFAULT                 0x0
-#define GC_KEYMGR_GCM_H2_OFFSET                  0x88
-#define GC_KEYMGR_GCM_H2_DEFAULT                 0x0
-#define GC_KEYMGR_GCM_H3_OFFSET                  0x8c
-#define GC_KEYMGR_GCM_H3_DEFAULT                 0x0
-#define GC_KEYMGR_GCM_MAC0_OFFSET                0x90
-#define GC_KEYMGR_GCM_MAC0_DEFAULT               0x0
-#define GC_KEYMGR_GCM_MAC1_OFFSET                0x94
-#define GC_KEYMGR_GCM_MAC1_DEFAULT               0x0
-#define GC_KEYMGR_GCM_MAC2_OFFSET                0x98
-#define GC_KEYMGR_GCM_MAC2_DEFAULT               0x0
-#define GC_KEYMGR_GCM_MAC3_OFFSET                0x9c
-#define GC_KEYMGR_GCM_MAC3_DEFAULT               0x0
-#define GC_KEYMGR_GCM_HASH_IN0_OFFSET            0xa0
-#define GC_KEYMGR_GCM_HASH_IN0_DEFAULT           0x0
-#define GC_KEYMGR_GCM_HASH_IN1_OFFSET            0xa4
-#define GC_KEYMGR_GCM_HASH_IN1_DEFAULT           0x0
-#define GC_KEYMGR_GCM_HASH_IN2_OFFSET            0xa8
-#define GC_KEYMGR_GCM_HASH_IN2_DEFAULT           0x0
-#define GC_KEYMGR_GCM_HASH_IN3_OFFSET            0xac
-#define GC_KEYMGR_GCM_HASH_IN3_DEFAULT           0x0
-#define GC_KEYMGR_AES_WIPE_SECRETS_OFFSET        0xb0
-#define GC_KEYMGR_AES_WIPE_SECRETS_DEFAULT       0x0
-#define GC_KEYMGR_AES_INT_ENABLE_OFFSET          0xb4
-#define GC_KEYMGR_AES_INT_ENABLE_DEFAULT         0x0
-#define GC_KEYMGR_AES_INT_STATE_OFFSET           0xb8
-#define GC_KEYMGR_AES_INT_STATE_DEFAULT          0x0
-#define GC_KEYMGR_AES_INT_TEST_OFFSET            0xbc
-#define GC_KEYMGR_AES_INT_TEST_DEFAULT           0x0
-#define GC_KEYMGR_AES_USE_HIDDEN_KEY_OFFSET      0xc0
-#define GC_KEYMGR_AES_USE_HIDDEN_KEY_DEFAULT     0x0
-#define GC_KEYMGR_INT_ENABLE_OFFSET              0xc4
-#define GC_KEYMGR_INT_ENABLE_DEFAULT             0x0
-#define GC_KEYMGR_INT_STATE_OFFSET               0xc8
-#define GC_KEYMGR_INT_STATE_DEFAULT              0x0
-#define GC_KEYMGR_INT_TEST_OFFSET                0xcc
-#define GC_KEYMGR_INT_TEST_DEFAULT               0x0
-#define GC_KEYMGR_SHA_CFG_MSGLEN_LO_OFFSET       0x400
-#define GC_KEYMGR_SHA_CFG_MSGLEN_LO_DEFAULT      0x0
-#define GC_KEYMGR_SHA_CFG_MSGLEN_HI_OFFSET       0x404
-#define GC_KEYMGR_SHA_CFG_MSGLEN_HI_DEFAULT      0x0
-#define GC_KEYMGR_SHA_CFG_EN_OFFSET              0x408
-#define GC_KEYMGR_SHA_CFG_EN_DEFAULT             0x1
-#define GC_KEYMGR_SHA_CFG_WR_EN_OFFSET           0x40c
-#define GC_KEYMGR_SHA_CFG_WR_EN_DEFAULT          0x1
-#define GC_KEYMGR_SHA_TRIG_OFFSET                0x410
-#define GC_KEYMGR_SHA_TRIG_DEFAULT               0x0
-#define GC_KEYMGR_SHA_INPUT_FIFO_OFFSET          0x440
-#define GC_KEYMGR_SHA_INPUT_FIFO_DEFAULT         0x0
-#define GC_KEYMGR_SHA_STS_H0_OFFSET              0x444
-#define GC_KEYMGR_SHA_STS_H0_DEFAULT             0x0
-#define GC_KEYMGR_SHA_STS_H1_OFFSET              0x448
-#define GC_KEYMGR_SHA_STS_H1_DEFAULT             0x0
-#define GC_KEYMGR_SHA_STS_H2_OFFSET              0x44c
-#define GC_KEYMGR_SHA_STS_H2_DEFAULT             0x0
-#define GC_KEYMGR_SHA_STS_H3_OFFSET              0x450
-#define GC_KEYMGR_SHA_STS_H3_DEFAULT             0x0
-#define GC_KEYMGR_SHA_STS_H4_OFFSET              0x454
-#define GC_KEYMGR_SHA_STS_H4_DEFAULT             0x0
-#define GC_KEYMGR_SHA_STS_H5_OFFSET              0x458
-#define GC_KEYMGR_SHA_STS_H5_DEFAULT             0x0
-#define GC_KEYMGR_SHA_STS_H6_OFFSET              0x45c
-#define GC_KEYMGR_SHA_STS_H6_DEFAULT             0x0
-#define GC_KEYMGR_SHA_STS_H7_OFFSET              0x460
-#define GC_KEYMGR_SHA_STS_H7_DEFAULT             0x0
-#define GC_KEYMGR_SHA_KEY_W0_OFFSET              0x464
-#define GC_KEYMGR_SHA_KEY_W0_DEFAULT             0x0
-#define GC_KEYMGR_SHA_KEY_W1_OFFSET              0x468
-#define GC_KEYMGR_SHA_KEY_W1_DEFAULT             0x0
-#define GC_KEYMGR_SHA_KEY_W2_OFFSET              0x46c
-#define GC_KEYMGR_SHA_KEY_W2_DEFAULT             0x0
-#define GC_KEYMGR_SHA_KEY_W3_OFFSET              0x470
-#define GC_KEYMGR_SHA_KEY_W3_DEFAULT             0x0
-#define GC_KEYMGR_SHA_KEY_W4_OFFSET              0x474
-#define GC_KEYMGR_SHA_KEY_W4_DEFAULT             0x0
-#define GC_KEYMGR_SHA_KEY_W5_OFFSET              0x478
-#define GC_KEYMGR_SHA_KEY_W5_DEFAULT             0x0
-#define GC_KEYMGR_SHA_KEY_W6_OFFSET              0x47c
-#define GC_KEYMGR_SHA_KEY_W6_DEFAULT             0x0
-#define GC_KEYMGR_SHA_KEY_W7_OFFSET              0x480
-#define GC_KEYMGR_SHA_KEY_W7_DEFAULT             0x0
-#define GC_KEYMGR_SHA_STS_OFFSET                 0x484
-#define GC_KEYMGR_SHA_STS_DEFAULT                0x0
-#define GC_KEYMGR_SHA_ITCR_OFFSET                0x488
-#define GC_KEYMGR_SHA_ITCR_DEFAULT               0x0
-#define GC_KEYMGR_SHA_ITOP_OFFSET                0x48c
-#define GC_KEYMGR_SHA_ITOP_DEFAULT               0x0
-#define GC_KEYMGR_SHA_USE_HIDDEN_KEY_OFFSET      0x490
-#define GC_KEYMGR_SHA_USE_HIDDEN_KEY_DEFAULT     0x0
-#define GC_KEYMGR_SHA_USE_CERT_OFFSET            0x494
-#define GC_KEYMGR_SHA_USE_CERT_DEFAULT           0x0
-#define GC_KEYMGR_SHA_CERT_OVERRIDE_OFFSET       0x498
-#define GC_KEYMGR_SHA_CERT_OVERRIDE_DEFAULT      0x0
-#define GC_KEYMGR_SHA_RAND_STALL_CTL_OFFSET      0x49c
-#define GC_KEYMGR_SHA_RAND_STALL_CTL_DEFAULT     0x7
-#define GC_KEYMGR_SHA_EXECUTE_COUNT_STATE_OFFSET 0x4a0
-#define GC_KEYMGR_SHA_EXECUTE_COUNT_STATE_DEFAULT 0x0
-#define GC_KEYMGR_SHA_EXECUTE_COUNT_MAX_OFFSET   0x4a4
-#define GC_KEYMGR_SHA_EXECUTE_COUNT_MAX_DEFAULT  0x0
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_OFFSET       0x4a8
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DEFAULT      0xaaaaaaaa
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_OFFSET       0x4ac
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_DEFAULT      0xaaaaaaaa
-#define GC_KEYMGR_CERT_REVOKE_CTRL2_OFFSET       0x4b0
-#define GC_KEYMGR_CERT_REVOKE_CTRL2_DEFAULT      0xaaaa
-#define GC_KEYMGR_TM_PW_ATTEMPT0_OFFSET          0x2100
-#define GC_KEYMGR_TM_PW_ATTEMPT0_DEFAULT         0x0
-#define GC_KEYMGR_TM_PW_ATTEMPT1_OFFSET          0x2104
-#define GC_KEYMGR_TM_PW_ATTEMPT1_DEFAULT         0x0
-#define GC_KEYMGR_TM_PW_ATTEMPT2_OFFSET          0x2108
-#define GC_KEYMGR_TM_PW_ATTEMPT2_DEFAULT         0x0
-#define GC_KEYMGR_TM_PW_ATTEMPT3_OFFSET          0x210c
-#define GC_KEYMGR_TM_PW_ATTEMPT3_DEFAULT         0x0
-#define GC_KEYMGR_TM_PW_ATTEMPT4_OFFSET          0x2110
-#define GC_KEYMGR_TM_PW_ATTEMPT4_DEFAULT         0x0
-#define GC_KEYMGR_TM_PW_ATTEMPT5_OFFSET          0x2114
-#define GC_KEYMGR_TM_PW_ATTEMPT5_DEFAULT         0x0
-#define GC_KEYMGR_TM_PW_ATTEMPT6_OFFSET          0x2118
-#define GC_KEYMGR_TM_PW_ATTEMPT6_DEFAULT         0x0
-#define GC_KEYMGR_TM_PW_ATTEMPT7_OFFSET          0x211c
-#define GC_KEYMGR_TM_PW_ATTEMPT7_DEFAULT         0x0
-#define GC_KEYMGR_TM_PW_UNLOCK_OFFSET            0x2120
-#define GC_KEYMGR_TM_PW_UNLOCK_DEFAULT           0x0
-#define GC_KEYMGR_HKEY_RWR0_OFFSET               0x3000
-#define GC_KEYMGR_HKEY_RWR0_DEFAULT              0x0
-#define GC_KEYMGR_HKEY_RWR1_OFFSET               0x3004
-#define GC_KEYMGR_HKEY_RWR1_DEFAULT              0x0
-#define GC_KEYMGR_HKEY_RWR2_OFFSET               0x3008
-#define GC_KEYMGR_HKEY_RWR2_DEFAULT              0x0
-#define GC_KEYMGR_HKEY_RWR3_OFFSET               0x300c
-#define GC_KEYMGR_HKEY_RWR3_DEFAULT              0x0
-#define GC_KEYMGR_HKEY_RWR4_OFFSET               0x3010
-#define GC_KEYMGR_HKEY_RWR4_DEFAULT              0x0
-#define GC_KEYMGR_HKEY_RWR5_OFFSET               0x3014
-#define GC_KEYMGR_HKEY_RWR5_DEFAULT              0x0
-#define GC_KEYMGR_HKEY_RWR6_OFFSET               0x3018
-#define GC_KEYMGR_HKEY_RWR6_DEFAULT              0x0
-#define GC_KEYMGR_HKEY_RWR7_OFFSET               0x301c
-#define GC_KEYMGR_HKEY_RWR7_DEFAULT              0x0
-#define GC_KEYMGR_RWR_VLD_OFFSET                 0x3020
-#define GC_KEYMGR_RWR_VLD_DEFAULT                0x1
-#define GC_KEYMGR_RWR_LOCK_OFFSET                0x3024
-#define GC_KEYMGR_RWR_LOCK_DEFAULT               0x1
-#define GC_KEYMGR_HKEY_FWR0_OFFSET               0x3100
-#define GC_KEYMGR_HKEY_FWR0_DEFAULT              0x0
-#define GC_KEYMGR_HKEY_FWR1_OFFSET               0x3104
-#define GC_KEYMGR_HKEY_FWR1_DEFAULT              0x0
-#define GC_KEYMGR_HKEY_FWR2_OFFSET               0x3108
-#define GC_KEYMGR_HKEY_FWR2_DEFAULT              0x0
-#define GC_KEYMGR_HKEY_FWR3_OFFSET               0x310c
-#define GC_KEYMGR_HKEY_FWR3_DEFAULT              0x0
-#define GC_KEYMGR_HKEY_FWR4_OFFSET               0x3110
-#define GC_KEYMGR_HKEY_FWR4_DEFAULT              0x0
-#define GC_KEYMGR_HKEY_FWR5_OFFSET               0x3114
-#define GC_KEYMGR_HKEY_FWR5_DEFAULT              0x0
-#define GC_KEYMGR_HKEY_FWR6_OFFSET               0x3118
-#define GC_KEYMGR_HKEY_FWR6_DEFAULT              0x0
-#define GC_KEYMGR_HKEY_FWR7_OFFSET               0x311c
-#define GC_KEYMGR_HKEY_FWR7_DEFAULT              0x0
-#define GC_KEYMGR_FWR_VLD_OFFSET                 0x3120
-#define GC_KEYMGR_FWR_VLD_DEFAULT                0x1
-#define GC_KEYMGR_FW_MAJOR_VERSION_OFFSET        0x3124
-#define GC_KEYMGR_FW_MAJOR_VERSION_DEFAULT       0x0
-#define GC_KEYMGR_FWR_LOCK_OFFSET                0x3128
-#define GC_KEYMGR_FWR_LOCK_DEFAULT               0x1
-#define GC_KEYMGR_HKEY_HWR0_OFFSET               0x3200
-#define GC_KEYMGR_HKEY_HWR0_DEFAULT              0x0
-#define GC_KEYMGR_HKEY_HWR1_OFFSET               0x3204
-#define GC_KEYMGR_HKEY_HWR1_DEFAULT              0x0
-#define GC_KEYMGR_HKEY_HWR2_OFFSET               0x3208
-#define GC_KEYMGR_HKEY_HWR2_DEFAULT              0x0
-#define GC_KEYMGR_HKEY_HWR3_OFFSET               0x320c
-#define GC_KEYMGR_HKEY_HWR3_DEFAULT              0x0
-#define GC_KEYMGR_HKEY_HWR4_OFFSET               0x3210
-#define GC_KEYMGR_HKEY_HWR4_DEFAULT              0x0
-#define GC_KEYMGR_HKEY_HWR5_OFFSET               0x3214
-#define GC_KEYMGR_HKEY_HWR5_DEFAULT              0x0
-#define GC_KEYMGR_HKEY_HWR6_OFFSET               0x3218
-#define GC_KEYMGR_HKEY_HWR6_DEFAULT              0x0
-#define GC_KEYMGR_HKEY_HWR7_OFFSET               0x321c
-#define GC_KEYMGR_HKEY_HWR7_DEFAULT              0x0
-#define GC_KEYMGR_HWR_VLD_OFFSET                 0x3220
-#define GC_KEYMGR_HWR_VLD_DEFAULT                0x1
-#define GC_KEYMGR_HWR_LOCK_OFFSET                0x3224
-#define GC_KEYMGR_HWR_LOCK_DEFAULT               0x1
-#define GC_KEYMGR_HKEY_FRR0_OFFSET               0x3300
-#define GC_KEYMGR_HKEY_FRR0_DEFAULT              0x0
-#define GC_KEYMGR_HKEY_FRR1_OFFSET               0x3304
-#define GC_KEYMGR_HKEY_FRR1_DEFAULT              0x0
-#define GC_KEYMGR_HKEY_FRR2_OFFSET               0x3308
-#define GC_KEYMGR_HKEY_FRR2_DEFAULT              0x0
-#define GC_KEYMGR_HKEY_FRR3_OFFSET               0x330c
-#define GC_KEYMGR_HKEY_FRR3_DEFAULT              0x0
-#define GC_KEYMGR_HKEY_FRR4_OFFSET               0x3310
-#define GC_KEYMGR_HKEY_FRR4_DEFAULT              0x0
-#define GC_KEYMGR_HKEY_FRR5_OFFSET               0x3314
-#define GC_KEYMGR_HKEY_FRR5_DEFAULT              0x0
-#define GC_KEYMGR_HKEY_FRR6_OFFSET               0x3318
-#define GC_KEYMGR_HKEY_FRR6_DEFAULT              0x0
-#define GC_KEYMGR_HKEY_FRR7_OFFSET               0x331c
-#define GC_KEYMGR_HKEY_FRR7_DEFAULT              0x0
-#define GC_KEYMGR_FLASH_RCV_WIPE_OFFSET          0x3320
-#define GC_KEYMGR_FLASH_RCV_WIPE_DEFAULT         0x0
-#define GC_KEYMGR_HKEY_ERR_FLAGS_OFFSET          0x3324
-#define GC_KEYMGR_HKEY_ERR_FLAGS_DEFAULT         0x0
-#define GC_KEYMGR_HKEY_ERR_CTRL_OFFSET           0x3328
-#define GC_KEYMGR_HKEY_ERR_CTRL_DEFAULT          0x0
-#define GC_KEYMGR_HKEY_FLASH_RCV_STATUS_OFFSET   0x332c
-#define GC_KEYMGR_HKEY_FLASH_RCV_STATUS_DEFAULT  0x0
-#define GC_KEYMGR_HKEY_TESTMODE_UNLOCKED_STATUS_OFFSET 0x3330
-#define GC_KEYMGR_HKEY_TESTMODE_UNLOCKED_STATUS_DEFAULT 0x0
-#define GC_PINMUX_DIOM0_SEL_OFFSET               0x0
-#define GC_PINMUX_DIOM0_SEL_DEFAULT              0x0
-#define GC_PINMUX_DIOM0_CTL_OFFSET               0x4
-#define GC_PINMUX_DIOM0_CTL_DEFAULT              0x3
-#define GC_PINMUX_DIOM1_SEL_OFFSET               0x8
-#define GC_PINMUX_DIOM1_SEL_DEFAULT              0x0
-#define GC_PINMUX_DIOM1_CTL_OFFSET               0xc
-#define GC_PINMUX_DIOM1_CTL_DEFAULT              0x3
-#define GC_PINMUX_DIOM2_SEL_OFFSET               0x10
-#define GC_PINMUX_DIOM2_SEL_DEFAULT              0x0
-#define GC_PINMUX_DIOM2_CTL_OFFSET               0x14
-#define GC_PINMUX_DIOM2_CTL_DEFAULT              0x3
-#define GC_PINMUX_DIOM3_SEL_OFFSET               0x18
-#define GC_PINMUX_DIOM3_SEL_DEFAULT              0x0
-#define GC_PINMUX_DIOM3_CTL_OFFSET               0x1c
-#define GC_PINMUX_DIOM3_CTL_DEFAULT              0x3
-#define GC_PINMUX_DIOM4_SEL_OFFSET               0x20
-#define GC_PINMUX_DIOM4_SEL_DEFAULT              0x0
-#define GC_PINMUX_DIOM4_CTL_OFFSET               0x24
-#define GC_PINMUX_DIOM4_CTL_DEFAULT              0x3
-#define GC_PINMUX_DIOA0_SEL_OFFSET               0x28
-#define GC_PINMUX_DIOA0_SEL_DEFAULT              0x0
-#define GC_PINMUX_DIOA0_CTL_OFFSET               0x2c
-#define GC_PINMUX_DIOA0_CTL_DEFAULT              0x3
-#define GC_PINMUX_DIOA1_SEL_OFFSET               0x30
-#define GC_PINMUX_DIOA1_SEL_DEFAULT              0x0
-#define GC_PINMUX_DIOA1_CTL_OFFSET               0x34
-#define GC_PINMUX_DIOA1_CTL_DEFAULT              0x3
-#define GC_PINMUX_DIOA2_SEL_OFFSET               0x38
-#define GC_PINMUX_DIOA2_SEL_DEFAULT              0x0
-#define GC_PINMUX_DIOA2_CTL_OFFSET               0x3c
-#define GC_PINMUX_DIOA2_CTL_DEFAULT              0x3
-#define GC_PINMUX_DIOA3_SEL_OFFSET               0x40
-#define GC_PINMUX_DIOA3_SEL_DEFAULT              0x0
-#define GC_PINMUX_DIOA3_CTL_OFFSET               0x44
-#define GC_PINMUX_DIOA3_CTL_DEFAULT              0x3
-#define GC_PINMUX_DIOA4_SEL_OFFSET               0x48
-#define GC_PINMUX_DIOA4_SEL_DEFAULT              0x0
-#define GC_PINMUX_DIOA4_CTL_OFFSET               0x4c
-#define GC_PINMUX_DIOA4_CTL_DEFAULT              0x3
-#define GC_PINMUX_DIOA5_SEL_OFFSET               0x50
-#define GC_PINMUX_DIOA5_SEL_DEFAULT              0x0
-#define GC_PINMUX_DIOA5_CTL_OFFSET               0x54
-#define GC_PINMUX_DIOA5_CTL_DEFAULT              0x3
-#define GC_PINMUX_DIOA6_SEL_OFFSET               0x58
-#define GC_PINMUX_DIOA6_SEL_DEFAULT              0x0
-#define GC_PINMUX_DIOA6_CTL_OFFSET               0x5c
-#define GC_PINMUX_DIOA6_CTL_DEFAULT              0x3
-#define GC_PINMUX_DIOA7_SEL_OFFSET               0x60
-#define GC_PINMUX_DIOA7_SEL_DEFAULT              0x0
-#define GC_PINMUX_DIOA7_CTL_OFFSET               0x64
-#define GC_PINMUX_DIOA7_CTL_DEFAULT              0x3
-#define GC_PINMUX_DIOA8_SEL_OFFSET               0x68
-#define GC_PINMUX_DIOA8_SEL_DEFAULT              0x0
-#define GC_PINMUX_DIOA8_CTL_OFFSET               0x6c
-#define GC_PINMUX_DIOA8_CTL_DEFAULT              0x3
-#define GC_PINMUX_DIOA9_SEL_OFFSET               0x70
-#define GC_PINMUX_DIOA9_SEL_DEFAULT              0x0
-#define GC_PINMUX_DIOA9_CTL_OFFSET               0x74
-#define GC_PINMUX_DIOA9_CTL_DEFAULT              0x3
-#define GC_PINMUX_DIOA10_SEL_OFFSET              0x78
-#define GC_PINMUX_DIOA10_SEL_DEFAULT             0x0
-#define GC_PINMUX_DIOA10_CTL_OFFSET              0x7c
-#define GC_PINMUX_DIOA10_CTL_DEFAULT             0x3
-#define GC_PINMUX_DIOA11_SEL_OFFSET              0x80
-#define GC_PINMUX_DIOA11_SEL_DEFAULT             0x0
-#define GC_PINMUX_DIOA11_CTL_OFFSET              0x84
-#define GC_PINMUX_DIOA11_CTL_DEFAULT             0x3
-#define GC_PINMUX_DIOA12_SEL_OFFSET              0x88
-#define GC_PINMUX_DIOA12_SEL_DEFAULT             0x0
-#define GC_PINMUX_DIOA12_CTL_OFFSET              0x8c
-#define GC_PINMUX_DIOA12_CTL_DEFAULT             0x3
-#define GC_PINMUX_DIOA13_SEL_OFFSET              0x90
-#define GC_PINMUX_DIOA13_SEL_DEFAULT             0x0
-#define GC_PINMUX_DIOA13_CTL_OFFSET              0x94
-#define GC_PINMUX_DIOA13_CTL_DEFAULT             0x3
-#define GC_PINMUX_DIOA14_SEL_OFFSET              0x98
-#define GC_PINMUX_DIOA14_SEL_DEFAULT             0x0
-#define GC_PINMUX_DIOA14_CTL_OFFSET              0x9c
-#define GC_PINMUX_DIOA14_CTL_DEFAULT             0x3
-#define GC_PINMUX_DIOB0_SEL_OFFSET               0xa0
-#define GC_PINMUX_DIOB0_SEL_DEFAULT              0x0
-#define GC_PINMUX_DIOB0_CTL_OFFSET               0xa4
-#define GC_PINMUX_DIOB0_CTL_DEFAULT              0x3
-#define GC_PINMUX_DIOB1_SEL_OFFSET               0xa8
-#define GC_PINMUX_DIOB1_SEL_DEFAULT              0x0
-#define GC_PINMUX_DIOB1_CTL_OFFSET               0xac
-#define GC_PINMUX_DIOB1_CTL_DEFAULT              0x3
-#define GC_PINMUX_DIOB2_SEL_OFFSET               0xb0
-#define GC_PINMUX_DIOB2_SEL_DEFAULT              0x0
-#define GC_PINMUX_DIOB2_CTL_OFFSET               0xb4
-#define GC_PINMUX_DIOB2_CTL_DEFAULT              0x3
-#define GC_PINMUX_DIOB3_SEL_OFFSET               0xb8
-#define GC_PINMUX_DIOB3_SEL_DEFAULT              0x0
-#define GC_PINMUX_DIOB3_CTL_OFFSET               0xbc
-#define GC_PINMUX_DIOB3_CTL_DEFAULT              0x3
-#define GC_PINMUX_DIOB4_SEL_OFFSET               0xc0
-#define GC_PINMUX_DIOB4_SEL_DEFAULT              0x0
-#define GC_PINMUX_DIOB4_CTL_OFFSET               0xc4
-#define GC_PINMUX_DIOB4_CTL_DEFAULT              0x3
-#define GC_PINMUX_DIOB5_SEL_OFFSET               0xc8
-#define GC_PINMUX_DIOB5_SEL_DEFAULT              0x0
-#define GC_PINMUX_DIOB5_CTL_OFFSET               0xcc
-#define GC_PINMUX_DIOB5_CTL_DEFAULT              0x3
-#define GC_PINMUX_DIOB6_SEL_OFFSET               0xd0
-#define GC_PINMUX_DIOB6_SEL_DEFAULT              0x0
-#define GC_PINMUX_DIOB6_CTL_OFFSET               0xd4
-#define GC_PINMUX_DIOB6_CTL_DEFAULT              0x3
-#define GC_PINMUX_DIOB7_SEL_OFFSET               0xd8
-#define GC_PINMUX_DIOB7_SEL_DEFAULT              0x0
-#define GC_PINMUX_DIOB7_CTL_OFFSET               0xdc
-#define GC_PINMUX_DIOB7_CTL_DEFAULT              0x3
-#define GC_PINMUX_RESETB_SEL_OFFSET              0xe0
-#define GC_PINMUX_RESETB_SEL_DEFAULT             0x0
-#define GC_PINMUX_RESETB_CTL_OFFSET              0xe4
-#define GC_PINMUX_RESETB_CTL_DEFAULT             0x7
-#define GC_PINMUX_VIO0_SEL_OFFSET                0xe8
-#define GC_PINMUX_VIO0_SEL_DEFAULT               0x0
-#define GC_PINMUX_VIO0_CTL_OFFSET                0xec
-#define GC_PINMUX_VIO0_CTL_DEFAULT               0x3
-#define GC_PINMUX_VIO1_SEL_OFFSET                0xf0
-#define GC_PINMUX_VIO1_SEL_DEFAULT               0x0
-#define GC_PINMUX_VIO1_CTL_OFFSET                0xf4
-#define GC_PINMUX_VIO1_CTL_DEFAULT               0x3
-#define GC_PINMUX_GPIO0_GPIO0_SEL_OFFSET         0xf8
-#define GC_PINMUX_GPIO0_GPIO0_SEL_DEFAULT        0x0
-#define GC_PINMUX_GPIO0_GPIO1_SEL_OFFSET         0xfc
-#define GC_PINMUX_GPIO0_GPIO1_SEL_DEFAULT        0x0
-#define GC_PINMUX_GPIO0_GPIO2_SEL_OFFSET         0x100
-#define GC_PINMUX_GPIO0_GPIO2_SEL_DEFAULT        0x0
-#define GC_PINMUX_GPIO0_GPIO3_SEL_OFFSET         0x104
-#define GC_PINMUX_GPIO0_GPIO3_SEL_DEFAULT        0x0
-#define GC_PINMUX_GPIO0_GPIO4_SEL_OFFSET         0x108
-#define GC_PINMUX_GPIO0_GPIO4_SEL_DEFAULT        0x0
-#define GC_PINMUX_GPIO0_GPIO5_SEL_OFFSET         0x10c
-#define GC_PINMUX_GPIO0_GPIO5_SEL_DEFAULT        0x0
-#define GC_PINMUX_GPIO0_GPIO6_SEL_OFFSET         0x110
-#define GC_PINMUX_GPIO0_GPIO6_SEL_DEFAULT        0x0
-#define GC_PINMUX_GPIO0_GPIO7_SEL_OFFSET         0x114
-#define GC_PINMUX_GPIO0_GPIO7_SEL_DEFAULT        0x0
-#define GC_PINMUX_GPIO0_GPIO8_SEL_OFFSET         0x118
-#define GC_PINMUX_GPIO0_GPIO8_SEL_DEFAULT        0x0
-#define GC_PINMUX_GPIO0_GPIO9_SEL_OFFSET         0x11c
-#define GC_PINMUX_GPIO0_GPIO9_SEL_DEFAULT        0x0
-#define GC_PINMUX_GPIO0_GPIO10_SEL_OFFSET        0x120
-#define GC_PINMUX_GPIO0_GPIO10_SEL_DEFAULT       0x0
-#define GC_PINMUX_GPIO0_GPIO11_SEL_OFFSET        0x124
-#define GC_PINMUX_GPIO0_GPIO11_SEL_DEFAULT       0x0
-#define GC_PINMUX_GPIO0_GPIO12_SEL_OFFSET        0x128
-#define GC_PINMUX_GPIO0_GPIO12_SEL_DEFAULT       0x0
-#define GC_PINMUX_GPIO0_GPIO13_SEL_OFFSET        0x12c
-#define GC_PINMUX_GPIO0_GPIO13_SEL_DEFAULT       0x0
-#define GC_PINMUX_GPIO0_GPIO14_SEL_OFFSET        0x130
-#define GC_PINMUX_GPIO0_GPIO14_SEL_DEFAULT       0x0
-#define GC_PINMUX_GPIO0_GPIO15_SEL_OFFSET        0x134
-#define GC_PINMUX_GPIO0_GPIO15_SEL_DEFAULT       0x0
-#define GC_PINMUX_GPIO1_GPIO0_SEL_OFFSET         0x138
-#define GC_PINMUX_GPIO1_GPIO0_SEL_DEFAULT        0x0
-#define GC_PINMUX_GPIO1_GPIO1_SEL_OFFSET         0x13c
-#define GC_PINMUX_GPIO1_GPIO1_SEL_DEFAULT        0x0
-#define GC_PINMUX_GPIO1_GPIO2_SEL_OFFSET         0x140
-#define GC_PINMUX_GPIO1_GPIO2_SEL_DEFAULT        0x0
-#define GC_PINMUX_GPIO1_GPIO3_SEL_OFFSET         0x144
-#define GC_PINMUX_GPIO1_GPIO3_SEL_DEFAULT        0x0
-#define GC_PINMUX_GPIO1_GPIO4_SEL_OFFSET         0x148
-#define GC_PINMUX_GPIO1_GPIO4_SEL_DEFAULT        0x0
-#define GC_PINMUX_GPIO1_GPIO5_SEL_OFFSET         0x14c
-#define GC_PINMUX_GPIO1_GPIO5_SEL_DEFAULT        0x0
-#define GC_PINMUX_GPIO1_GPIO6_SEL_OFFSET         0x150
-#define GC_PINMUX_GPIO1_GPIO6_SEL_DEFAULT        0x0
-#define GC_PINMUX_GPIO1_GPIO7_SEL_OFFSET         0x154
-#define GC_PINMUX_GPIO1_GPIO7_SEL_DEFAULT        0x0
-#define GC_PINMUX_GPIO1_GPIO8_SEL_OFFSET         0x158
-#define GC_PINMUX_GPIO1_GPIO8_SEL_DEFAULT        0x0
-#define GC_PINMUX_GPIO1_GPIO9_SEL_OFFSET         0x15c
-#define GC_PINMUX_GPIO1_GPIO9_SEL_DEFAULT        0x0
-#define GC_PINMUX_GPIO1_GPIO10_SEL_OFFSET        0x160
-#define GC_PINMUX_GPIO1_GPIO10_SEL_DEFAULT       0x0
-#define GC_PINMUX_GPIO1_GPIO11_SEL_OFFSET        0x164
-#define GC_PINMUX_GPIO1_GPIO11_SEL_DEFAULT       0x0
-#define GC_PINMUX_GPIO1_GPIO12_SEL_OFFSET        0x168
-#define GC_PINMUX_GPIO1_GPIO12_SEL_DEFAULT       0x0
-#define GC_PINMUX_GPIO1_GPIO13_SEL_OFFSET        0x16c
-#define GC_PINMUX_GPIO1_GPIO13_SEL_DEFAULT       0x0
-#define GC_PINMUX_GPIO1_GPIO14_SEL_OFFSET        0x170
-#define GC_PINMUX_GPIO1_GPIO14_SEL_DEFAULT       0x0
-#define GC_PINMUX_GPIO1_GPIO15_SEL_OFFSET        0x174
-#define GC_PINMUX_GPIO1_GPIO15_SEL_DEFAULT       0x0
-#define GC_PINMUX_I2C0_SCL_SEL_OFFSET            0x178
-#define GC_PINMUX_I2C0_SCL_SEL_DEFAULT           0x0
-#define GC_PINMUX_I2C0_SDA_SEL_OFFSET            0x17c
-#define GC_PINMUX_I2C0_SDA_SEL_DEFAULT           0x0
-#define GC_PINMUX_I2C1_SCL_SEL_OFFSET            0x180
-#define GC_PINMUX_I2C1_SCL_SEL_DEFAULT           0x0
-#define GC_PINMUX_I2C1_SDA_SEL_OFFSET            0x184
-#define GC_PINMUX_I2C1_SDA_SEL_DEFAULT           0x0
-#define GC_PINMUX_I2CS0_SCL_SEL_OFFSET           0x188
-#define GC_PINMUX_I2CS0_SCL_SEL_DEFAULT          0x0
-#define GC_PINMUX_I2CS0_SDA_SEL_OFFSET           0x18c
-#define GC_PINMUX_I2CS0_SDA_SEL_DEFAULT          0x0
-#define GC_PINMUX_PMU_BROWNOUT_DET_SEL_OFFSET    0x190
-#define GC_PINMUX_PMU_BROWNOUT_DET_SEL_DEFAULT   0x0
-#define GC_PINMUX_PMU_TESTBUS0_SEL_OFFSET        0x194
-#define GC_PINMUX_PMU_TESTBUS0_SEL_DEFAULT       0x0
-#define GC_PINMUX_PMU_TESTBUS1_SEL_OFFSET        0x198
-#define GC_PINMUX_PMU_TESTBUS1_SEL_DEFAULT       0x0
-#define GC_PINMUX_PMU_TESTBUS2_SEL_OFFSET        0x19c
-#define GC_PINMUX_PMU_TESTBUS2_SEL_DEFAULT       0x0
-#define GC_PINMUX_PMU_TESTBUS3_SEL_OFFSET        0x1a0
-#define GC_PINMUX_PMU_TESTBUS3_SEL_DEFAULT       0x0
-#define GC_PINMUX_PMU_TESTBUS4_SEL_OFFSET        0x1a4
-#define GC_PINMUX_PMU_TESTBUS4_SEL_DEFAULT       0x0
-#define GC_PINMUX_PMU_TESTBUS5_SEL_OFFSET        0x1a8
-#define GC_PINMUX_PMU_TESTBUS5_SEL_DEFAULT       0x0
-#define GC_PINMUX_PMU_TESTBUS6_SEL_OFFSET        0x1ac
-#define GC_PINMUX_PMU_TESTBUS6_SEL_DEFAULT       0x0
-#define GC_PINMUX_PMU_TESTBUS7_SEL_OFFSET        0x1b0
-#define GC_PINMUX_PMU_TESTBUS7_SEL_DEFAULT       0x0
-#define GC_PINMUX_RTC0_RTC_CLK_TEST_SEL_OFFSET   0x1b4
-#define GC_PINMUX_RTC0_RTC_CLK_TEST_SEL_DEFAULT  0x0
-#define GC_PINMUX_SPI1_SPICLK_SEL_OFFSET         0x1b8
-#define GC_PINMUX_SPI1_SPICLK_SEL_DEFAULT        0x0
-#define GC_PINMUX_SPI1_SPICSB_SEL_OFFSET         0x1bc
-#define GC_PINMUX_SPI1_SPICSB_SEL_DEFAULT        0x0
-#define GC_PINMUX_SPI1_SPIMISO_SEL_OFFSET        0x1c0
-#define GC_PINMUX_SPI1_SPIMISO_SEL_DEFAULT       0x0
-#define GC_PINMUX_SPI1_SPIMOSI_SEL_OFFSET        0x1c4
-#define GC_PINMUX_SPI1_SPIMOSI_SEL_DEFAULT       0x0
-#define GC_PINMUX_SPS0_TESTBUS0_SEL_OFFSET       0x1c8
-#define GC_PINMUX_SPS0_TESTBUS0_SEL_DEFAULT      0x0
-#define GC_PINMUX_SPS0_TESTBUS1_SEL_OFFSET       0x1cc
-#define GC_PINMUX_SPS0_TESTBUS1_SEL_DEFAULT      0x0
-#define GC_PINMUX_SPS0_TESTBUS2_SEL_OFFSET       0x1d0
-#define GC_PINMUX_SPS0_TESTBUS2_SEL_DEFAULT      0x0
-#define GC_PINMUX_SPS0_TESTBUS3_SEL_OFFSET       0x1d4
-#define GC_PINMUX_SPS0_TESTBUS3_SEL_DEFAULT      0x0
-#define GC_PINMUX_SPS0_TESTBUS4_SEL_OFFSET       0x1d8
-#define GC_PINMUX_SPS0_TESTBUS4_SEL_DEFAULT      0x0
-#define GC_PINMUX_SPS0_TESTBUS5_SEL_OFFSET       0x1dc
-#define GC_PINMUX_SPS0_TESTBUS5_SEL_DEFAULT      0x0
-#define GC_PINMUX_SPS0_TESTBUS6_SEL_OFFSET       0x1e0
-#define GC_PINMUX_SPS0_TESTBUS6_SEL_DEFAULT      0x0
-#define GC_PINMUX_SPS0_TESTBUS7_SEL_OFFSET       0x1e4
-#define GC_PINMUX_SPS0_TESTBUS7_SEL_DEFAULT      0x0
-#define GC_PINMUX_TEMP0_TST_ADC_CLK_SEL_OFFSET   0x1e8
-#define GC_PINMUX_TEMP0_TST_ADC_CLK_SEL_DEFAULT  0x0
-#define GC_PINMUX_TEMP0_TST_ADC_HI_SER_SEL_OFFSET 0x1ec
-#define GC_PINMUX_TEMP0_TST_ADC_HI_SER_SEL_DEFAULT 0x0
-#define GC_PINMUX_TEMP0_TST_ADC_LO_SER_SEL_OFFSET 0x1f0
-#define GC_PINMUX_TEMP0_TST_ADC_LO_SER_SEL_DEFAULT 0x0
-#define GC_PINMUX_TEMP0_TST_ADC_VLD_SER_SEL_OFFSET 0x1f4
-#define GC_PINMUX_TEMP0_TST_ADC_VLD_SER_SEL_DEFAULT 0x0
-#define GC_PINMUX_TRNG0_TRNG_RO_DIV_SEL_OFFSET   0x1f8
-#define GC_PINMUX_TRNG0_TRNG_RO_DIV_SEL_DEFAULT  0x0
-#define GC_PINMUX_TRNG0_TRNG_RO_REF_DIV_SEL_OFFSET 0x1fc
-#define GC_PINMUX_TRNG0_TRNG_RO_REF_DIV_SEL_DEFAULT 0x0
-#define GC_PINMUX_UART0_CTS_SEL_OFFSET           0x200
-#define GC_PINMUX_UART0_CTS_SEL_DEFAULT          0x0
-#define GC_PINMUX_UART0_RTS_SEL_OFFSET           0x204
-#define GC_PINMUX_UART0_RTS_SEL_DEFAULT          0x0
-#define GC_PINMUX_UART0_RX_SEL_OFFSET            0x208
-#define GC_PINMUX_UART0_RX_SEL_DEFAULT           0x0
-#define GC_PINMUX_UART0_TX_SEL_OFFSET            0x20c
-#define GC_PINMUX_UART0_TX_SEL_DEFAULT           0x0
-#define GC_PINMUX_UART1_CTS_SEL_OFFSET           0x210
-#define GC_PINMUX_UART1_CTS_SEL_DEFAULT          0x0
-#define GC_PINMUX_UART1_RTS_SEL_OFFSET           0x214
-#define GC_PINMUX_UART1_RTS_SEL_DEFAULT          0x0
-#define GC_PINMUX_UART1_RX_SEL_OFFSET            0x218
-#define GC_PINMUX_UART1_RX_SEL_DEFAULT           0x0
-#define GC_PINMUX_UART1_TX_SEL_OFFSET            0x21c
-#define GC_PINMUX_UART1_TX_SEL_DEFAULT           0x0
-#define GC_PINMUX_UART2_CTS_SEL_OFFSET           0x220
-#define GC_PINMUX_UART2_CTS_SEL_DEFAULT          0x0
-#define GC_PINMUX_UART2_RTS_SEL_OFFSET           0x224
-#define GC_PINMUX_UART2_RTS_SEL_DEFAULT          0x0
-#define GC_PINMUX_UART2_RX_SEL_OFFSET            0x228
-#define GC_PINMUX_UART2_RX_SEL_DEFAULT           0x0
-#define GC_PINMUX_UART2_TX_SEL_OFFSET            0x22c
-#define GC_PINMUX_UART2_TX_SEL_DEFAULT           0x0
-#define GC_PINMUX_USB0_EXT_DM_PULLUP_EN_SEL_OFFSET 0x230
-#define GC_PINMUX_USB0_EXT_DM_PULLUP_EN_SEL_DEFAULT 0x0
-#define GC_PINMUX_USB0_EXT_DP_RPU1_ENB_SEL_OFFSET 0x234
-#define GC_PINMUX_USB0_EXT_DP_RPU1_ENB_SEL_DEFAULT 0x0
-#define GC_PINMUX_USB0_EXT_DP_RPU2_ENB_SEL_OFFSET 0x238
-#define GC_PINMUX_USB0_EXT_DP_RPU2_ENB_SEL_DEFAULT 0x0
-#define GC_PINMUX_USB0_EXT_FS_EDGE_SEL_SEL_OFFSET 0x23c
-#define GC_PINMUX_USB0_EXT_FS_EDGE_SEL_SEL_DEFAULT 0x0
-#define GC_PINMUX_USB0_EXT_RX_DMI_SEL_OFFSET     0x240
-#define GC_PINMUX_USB0_EXT_RX_DMI_SEL_DEFAULT    0x0
-#define GC_PINMUX_USB0_EXT_RX_DPI_SEL_OFFSET     0x244
-#define GC_PINMUX_USB0_EXT_RX_DPI_SEL_DEFAULT    0x0
-#define GC_PINMUX_USB0_EXT_RX_RCV_SEL_OFFSET     0x248
-#define GC_PINMUX_USB0_EXT_RX_RCV_SEL_DEFAULT    0x0
-#define GC_PINMUX_USB0_EXT_SUSPENDB_SEL_OFFSET   0x24c
-#define GC_PINMUX_USB0_EXT_SUSPENDB_SEL_DEFAULT  0x0
-#define GC_PINMUX_USB0_EXT_TX_DMO_SEL_OFFSET     0x250
-#define GC_PINMUX_USB0_EXT_TX_DMO_SEL_DEFAULT    0x0
-#define GC_PINMUX_USB0_EXT_TX_DPO_SEL_OFFSET     0x254
-#define GC_PINMUX_USB0_EXT_TX_DPO_SEL_DEFAULT    0x0
-#define GC_PINMUX_USB0_EXT_TX_OEB_SEL_OFFSET     0x258
-#define GC_PINMUX_USB0_EXT_TX_OEB_SEL_DEFAULT    0x0
-#define GC_PINMUX_VOLT0_TST_NEG_GLITCH_DET_SEL_OFFSET 0x25c
-#define GC_PINMUX_VOLT0_TST_NEG_GLITCH_DET_SEL_DEFAULT 0x0
-#define GC_PINMUX_VOLT0_TST_POS_GLITCH_DET_SEL_OFFSET 0x260
-#define GC_PINMUX_VOLT0_TST_POS_GLITCH_DET_SEL_DEFAULT 0x0
-#define GC_PINMUX_XO0_TESTBUS0_SEL_OFFSET        0x264
-#define GC_PINMUX_XO0_TESTBUS0_SEL_DEFAULT       0x0
-#define GC_PINMUX_XO0_TESTBUS1_SEL_OFFSET        0x268
-#define GC_PINMUX_XO0_TESTBUS1_SEL_DEFAULT       0x0
-#define GC_PINMUX_XO0_TESTBUS2_SEL_OFFSET        0x26c
-#define GC_PINMUX_XO0_TESTBUS2_SEL_DEFAULT       0x0
-#define GC_PINMUX_XO0_TESTBUS3_SEL_OFFSET        0x270
-#define GC_PINMUX_XO0_TESTBUS3_SEL_DEFAULT       0x0
-#define GC_PINMUX_XO0_TESTBUS4_SEL_OFFSET        0x274
-#define GC_PINMUX_XO0_TESTBUS4_SEL_DEFAULT       0x0
-#define GC_PINMUX_XO0_TESTBUS5_SEL_OFFSET        0x278
-#define GC_PINMUX_XO0_TESTBUS5_SEL_DEFAULT       0x0
-#define GC_PINMUX_XO0_TESTBUS6_SEL_OFFSET        0x27c
-#define GC_PINMUX_XO0_TESTBUS6_SEL_DEFAULT       0x0
-#define GC_PINMUX_XO0_TESTBUS7_SEL_OFFSET        0x280
-#define GC_PINMUX_XO0_TESTBUS7_SEL_DEFAULT       0x0
-#define GC_PINMUX_EXITEN0_OFFSET                 0x284
-#define GC_PINMUX_EXITEN0_DEFAULT                0x0
-#define GC_PINMUX_EXITEDGE0_OFFSET               0x288
-#define GC_PINMUX_EXITEDGE0_DEFAULT              0x0
-#define GC_PINMUX_EXITINV0_OFFSET                0x28c
-#define GC_PINMUX_EXITINV0_DEFAULT               0x0
-#define GC_PINMUX_HOLD_OFFSET                    0x290
-#define GC_PINMUX_HOLD_DEFAULT                   0x0
-#define GC_PMU_RESET_OFFSET                      0x0
-#define GC_PMU_RESET_DEFAULT                     0x3
-#define GC_PMU_SETRST_OFFSET                     0x4
-#define GC_PMU_SETRST_DEFAULT                    0x0
-#define GC_PMU_CLRRST_OFFSET                     0x8
-#define GC_PMU_CLRRST_DEFAULT                    0x0
-#define GC_PMU_RSTSRC_OFFSET                     0xc
-#define GC_PMU_RSTSRC_DEFAULT                    0x0
-#define GC_PMU_GLOBAL_RESET_OFFSET               0x10
-#define GC_PMU_GLOBAL_RESET_DEFAULT              0x0
-#define GC_PMU_GLOBAL_RESET_KEY                  0x7041776
-#define GC_PMU_LOW_POWER_DIS_OFFSET              0x14
-#define GC_PMU_LOW_POWER_DIS_DEFAULT             0x1e
-#define GC_PMU_LOW_POWER_BYPASS_OFFSET           0x18
-#define GC_PMU_LOW_POWER_BYPASS_DEFAULT          0x0
-#define GC_PMU_LOW_POWER_BYPASS_VALUE_OFFSET     0x1c
-#define GC_PMU_LOW_POWER_BYPASS_VALUE_DEFAULT    0x0
-#define GC_PMU_SETWIC_OFFSET                     0x20
-#define GC_PMU_SETWIC_DEFAULT                    0x0
-#define GC_PMU_CLRWIC_OFFSET                     0x24
-#define GC_PMU_CLRWIC_DEFAULT                    0x0
-#define GC_PMU_SYSVTOR_OFFSET                    0x28
-#define GC_PMU_SYSVTOR_DEFAULT                   0xffffffff
-#define GC_PMU_NAP_EN_OFFSET                     0x2c
-#define GC_PMU_NAP_EN_DEFAULT                    0x0
-#define GC_PMU_SW_PDB_OFFSET                     0x30
-#define GC_PMU_SW_PDB_DEFAULT                    0x0
-#define GC_PMU_SW_PDB_SECURE_OFFSET              0x34
-#define GC_PMU_SW_PDB_SECURE_DEFAULT             0x0
-#define GC_PMU_VREF_OFFSET                       0x38
-#define GC_PMU_VREF_DEFAULT                      0xdb
-#define GC_PMU_XTL_OSC_BYPASS_OFFSET             0x3c
-#define GC_PMU_XTL_OSC_BYPASS_DEFAULT            0x0
-#define GC_PMU_FLASH_TM0_TEST_EN_BYPASS_OFFSET   0x40
-#define GC_PMU_FLASH_TM0_TEST_EN_BYPASS_DEFAULT  0x0
-#define GC_PMU_BAT_LVL_OK_OFFSET                 0x44
-#define GC_PMU_BAT_LVL_OK_DEFAULT                0x0
-#define GC_PMU_B_REG_DIG_CTRL_OFFSET             0x48
-#define GC_PMU_B_REG_DIG_CTRL_DEFAULT            0x2
-#define GC_PMU_EXITPD_MASK_OFFSET                0x4c
-#define GC_PMU_EXITPD_MASK_DEFAULT               0x0
-#define GC_PMU_EXITPD_SRC_OFFSET                 0x50
-#define GC_PMU_EXITPD_SRC_DEFAULT                0x0
-#define GC_PMU_EXITPD_MON_OFFSET                 0x54
-#define GC_PMU_EXITPD_MON_DEFAULT                0x0
-#define GC_PMU_OSC_CTRL_OFFSET                   0x58
-#define GC_PMU_OSC_CTRL_DEFAULT                  0x1
-#define GC_PMU_MEMCLKSET_OFFSET                  0x5c
-#define GC_PMU_MEMCLKSET_DEFAULT                 0x7f
-#define GC_PMU_MEMCLKCLR_OFFSET                  0x60
-#define GC_PMU_MEMCLKCLR_DEFAULT                 0x7f
-#define GC_PMU_PERICLKSET0_OFFSET                0x64
-#define GC_PMU_PERICLKSET0_DEFAULT               0xff3fe0fb
-#define GC_PMU_PERICLKCLR0_OFFSET                0x68
-#define GC_PMU_PERICLKCLR0_DEFAULT               0xff3fe0fb
-#define GC_PMU_PERICLKSET1_OFFSET                0x6c
-#define GC_PMU_PERICLKSET1_DEFAULT               0xff10
-#define GC_PMU_PERICLKCLR1_OFFSET                0x70
-#define GC_PMU_PERICLKCLR1_DEFAULT               0xff10
-#define GC_PMU_CLK_RO_MASK0_OFFSET               0x74
-#define GC_PMU_CLK_RO_MASK0_DEFAULT              0x800fc0e1
-#define GC_PMU_CLK_RO_MASK1_OFFSET               0x78
-#define GC_PMU_CLK_RO_MASK1_DEFAULT              0xcc00
-#define GC_PMU_PERIGATEONSLEEPSET0_OFFSET        0x7c
-#define GC_PMU_PERIGATEONSLEEPSET0_DEFAULT       0x0
-#define GC_PMU_PERIGATEONSLEEPCLR0_OFFSET        0x80
-#define GC_PMU_PERIGATEONSLEEPCLR0_DEFAULT       0x0
-#define GC_PMU_PERIGATEONSLEEPSET1_OFFSET        0x84
-#define GC_PMU_PERIGATEONSLEEPSET1_DEFAULT       0x0
-#define GC_PMU_PERIGATEONSLEEPCLR1_OFFSET        0x88
-#define GC_PMU_PERIGATEONSLEEPCLR1_DEFAULT       0x0
-#define GC_PMU_CLK0_OFFSET                       0x8c
-#define GC_PMU_CLK0_DEFAULT                      0x1f
-#define GC_PMU_RST0_WR_EN_OFFSET                 0x90
-#define GC_PMU_RST0_WR_EN_DEFAULT                0x1
-#define GC_PMU_RST0_OFFSET                       0x94
-#define GC_PMU_RST0_DEFAULT                      0x0
-#define GC_PMU_RST1_WR_EN_OFFSET                 0x98
-#define GC_PMU_RST1_WR_EN_DEFAULT                0x1
-#define GC_PMU_RST1_OFFSET                       0x9c
-#define GC_PMU_RST1_DEFAULT                      0x0
-#define GC_PMU_PWRDN_SCRATCH0_OFFSET             0xa0
-#define GC_PMU_PWRDN_SCRATCH0_DEFAULT            0x7020eceb
-#define GC_PMU_PWRDN_SCRATCH1_OFFSET             0xa4
-#define GC_PMU_PWRDN_SCRATCH1_DEFAULT            0x2ebe9116
-#define GC_PMU_PWRDN_SCRATCH2_OFFSET             0xa8
-#define GC_PMU_PWRDN_SCRATCH2_DEFAULT            0x13b4a4d9
-#define GC_PMU_PWRDN_SCRATCH3_OFFSET             0xac
-#define GC_PMU_PWRDN_SCRATCH3_DEFAULT            0x3d2dd072
-#define GC_PMU_PWRDN_SCRATCH4_OFFSET             0xb0
-#define GC_PMU_PWRDN_SCRATCH4_DEFAULT            0x13eda68b
-#define GC_PMU_PWRDN_SCRATCH5_OFFSET             0xb4
-#define GC_PMU_PWRDN_SCRATCH5_DEFAULT            0x295c9f66
-#define GC_PMU_PWRDN_SCRATCH6_OFFSET             0xb8
-#define GC_PMU_PWRDN_SCRATCH6_DEFAULT            0x2a23c2db
-#define GC_PMU_PWRDN_SCRATCH7_OFFSET             0xbc
-#define GC_PMU_PWRDN_SCRATCH7_DEFAULT            0x8ef4ab68
-#define GC_PMU_PWRDN_SCRATCH8_OFFSET             0xc0
-#define GC_PMU_PWRDN_SCRATCH8_DEFAULT            0x35057fa1
-#define GC_PMU_PWRDN_SCRATCH9_OFFSET             0xc4
-#define GC_PMU_PWRDN_SCRATCH9_DEFAULT            0x4bfc60a3
-#define GC_PMU_PWRDN_SCRATCH10_OFFSET            0xc8
-#define GC_PMU_PWRDN_SCRATCH10_DEFAULT           0xa82ff9e
-#define GC_PMU_PWRDN_SCRATCH11_OFFSET            0xcc
-#define GC_PMU_PWRDN_SCRATCH11_DEFAULT           0x3898bda0
-#define GC_PMU_PWRDN_SCRATCH12_OFFSET            0xd0
-#define GC_PMU_PWRDN_SCRATCH12_DEFAULT           0x3c64367b
-#define GC_PMU_PWRDN_SCRATCH13_OFFSET            0xd4
-#define GC_PMU_PWRDN_SCRATCH13_DEFAULT           0x1f653095
-#define GC_PMU_PWRDN_SCRATCH14_OFFSET            0xd8
-#define GC_PMU_PWRDN_SCRATCH14_DEFAULT           0x21d285ad
-#define GC_PMU_PWRDN_SCRATCH15_OFFSET            0xdc
-#define GC_PMU_PWRDN_SCRATCH15_DEFAULT           0x2fe32196
-#define GC_PMU_PWRDN_SCRATCH16_OFFSET            0xe0
-#define GC_PMU_PWRDN_SCRATCH16_DEFAULT           0x0
-#define GC_PMU_PWRDN_SCRATCH17_OFFSET            0xe4
-#define GC_PMU_PWRDN_SCRATCH17_DEFAULT           0x0
-#define GC_PMU_PWRDN_SCRATCH18_OFFSET            0xe8
-#define GC_PMU_PWRDN_SCRATCH18_DEFAULT           0x0
-#define GC_PMU_PWRDN_SCRATCH19_OFFSET            0xec
-#define GC_PMU_PWRDN_SCRATCH19_DEFAULT           0x0
-#define GC_PMU_PWRDN_SCRATCH20_OFFSET            0xf0
-#define GC_PMU_PWRDN_SCRATCH20_DEFAULT           0x0
-#define GC_PMU_PWRDN_SCRATCH21_OFFSET            0xf4
-#define GC_PMU_PWRDN_SCRATCH21_DEFAULT           0x0
-#define GC_PMU_PWRDN_SCRATCH22_OFFSET            0xf8
-#define GC_PMU_PWRDN_SCRATCH22_DEFAULT           0x0
-#define GC_PMU_PWRDN_SCRATCH23_OFFSET            0xfc
-#define GC_PMU_PWRDN_SCRATCH23_DEFAULT           0x0
-#define GC_PMU_PWRDN_SCRATCH24_OFFSET            0x100
-#define GC_PMU_PWRDN_SCRATCH24_DEFAULT           0x0
-#define GC_PMU_PWRDN_SCRATCH25_OFFSET            0x104
-#define GC_PMU_PWRDN_SCRATCH25_DEFAULT           0x0
-#define GC_PMU_PWRDN_SCRATCH26_OFFSET            0x108
-#define GC_PMU_PWRDN_SCRATCH26_DEFAULT           0x0
-#define GC_PMU_PWRDN_SCRATCH27_OFFSET            0x10c
-#define GC_PMU_PWRDN_SCRATCH27_DEFAULT           0x0
-#define GC_PMU_PWRDN_SCRATCH28_OFFSET            0x110
-#define GC_PMU_PWRDN_SCRATCH28_DEFAULT           0x0
-#define GC_PMU_PWRDN_SCRATCH29_OFFSET            0x114
-#define GC_PMU_PWRDN_SCRATCH29_DEFAULT           0x0
-#define GC_PMU_PWRDN_SCRATCH30_OFFSET            0x118
-#define GC_PMU_PWRDN_SCRATCH30_DEFAULT           0x0
-#define GC_PMU_PWRDN_SCRATCH31_OFFSET            0x11c
-#define GC_PMU_PWRDN_SCRATCH31_DEFAULT           0x0
-#define GC_PMU_PWRDN_SCRATCH_LOCK_OFFSET         0x120
-#define GC_PMU_PWRDN_SCRATCH_LOCK_DEFAULT        0x0
-#define GC_PMU_PWRDN_SCRATCH_LOCK1_OFFSET        0x124
-#define GC_PMU_PWRDN_SCRATCH_LOCK1_DEFAULT       0x0
-#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_OFFSET    0x128
-#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_DEFAULT   0x0
-#define GC_PMU_LONG_LIFE_SCRATCH0_OFFSET         0x12c
-#define GC_PMU_LONG_LIFE_SCRATCH0_DEFAULT        0x0
-#define GC_PMU_LONG_LIFE_SCRATCH1_OFFSET         0x130
-#define GC_PMU_LONG_LIFE_SCRATCH1_DEFAULT        0x0
-#define GC_PMU_LONG_LIFE_SCRATCH2_OFFSET         0x134
-#define GC_PMU_LONG_LIFE_SCRATCH2_DEFAULT        0x0
-#define GC_PMU_LONG_LIFE_SCRATCH3_OFFSET         0x138
-#define GC_PMU_LONG_LIFE_SCRATCH3_DEFAULT        0x0
-#define GC_PMU_INT_ENABLE_OFFSET                 0x13c
-#define GC_PMU_INT_ENABLE_DEFAULT                0x0
-#define GC_PMU_INT_STATE_OFFSET                  0x140
-#define GC_PMU_INT_STATE_DEFAULT                 0x0
-#define GC_PMU_INT_TEST_OFFSET                   0x144
-#define GC_PMU_INT_TEST_DEFAULT                  0x0
-#define GC_PMU_ANTEST_TOP_CTRL_OFFSET            0x1008
-#define GC_PMU_ANTEST_TOP_CTRL_DEFAULT           0x3
-#define GC_PMU_ANTEST_REGDIG_OFFSET              0x1010
-#define GC_PMU_ANTEST_REGDIG_DEFAULT             0x0
-#define GC_PMU_TESTBUS_CTRL_BOUT_EN_OFFSET       0x2000
-#define GC_PMU_TESTBUS_CTRL_BOUT_EN_DEFAULT      0x0
-#define GC_PMU_TESTBUS_CTRL_OFFSET               0x2004
-#define GC_PMU_TESTBUS_CTRL_DEFAULT              0x0
-#define GC_PMU_TESTBUS_STATUS_OFFSET             0x2008
-#define GC_PMU_TESTBUS_STATUS_DEFAULT            0x0
-#define GC_PMU_CHIP_ID_OFFSET                    0x1fff8
-#define GC_PMU_CHIP_ID_DEFAULT                   0x1485694d
-#define GC_PMU_VERSION_OFFSET                    0x1fffc
-#define GC_PMU_VERSION_DEFAULT                   0x24011f6d
-#define GC_RBOX_INT_ENABLE_OFFSET                0x0
-#define GC_RBOX_INT_ENABLE_DEFAULT               0x0
-#define GC_RBOX_INT_STATE_OFFSET                 0x4
-#define GC_RBOX_INT_STATE_DEFAULT                0x0
-#define GC_RBOX_INT_TEST_OFFSET                  0x8
-#define GC_RBOX_INT_TEST_DEFAULT                 0x0
-#define GC_RBOX_EC_WP_L_OFFSET                   0xc
-#define GC_RBOX_EC_WP_L_DEFAULT                  0x0
-#define GC_RBOX_ASSERT_EC_RST_OFFSET             0x10
-#define GC_RBOX_ASSERT_EC_RST_DEFAULT            0x0
-#define GC_RBOX_OVERRIDE_OUTPUT_OFFSET           0x14
-#define GC_RBOX_OVERRIDE_OUTPUT_DEFAULT          0x2e80
-#define GC_RBOX_CHECK_INPUT_OFFSET               0x18
-#define GC_RBOX_CHECK_INPUT_DEFAULT              0x0
-#define GC_RBOX_CHECK_OUTPUT_OFFSET              0x1c
-#define GC_RBOX_CHECK_OUTPUT_DEFAULT             0x0
-#define GC_RBOX_CHECK_OEN_OFFSET                 0x20
-#define GC_RBOX_CHECK_OEN_DEFAULT                0x0
-#define GC_RBOX_CHECK_TERM_OFFSET                0x24
-#define GC_RBOX_CHECK_TERM_DEFAULT               0x0
-#define GC_RBOX_STATUS_OFFSET                    0x28
-#define GC_RBOX_STATUS_DEFAULT                   0x0
-#define GC_RBOX_FUSE_CTRL_OFFSET                 0x2c
-#define GC_RBOX_FUSE_CTRL_DEFAULT                0x0
-#define GC_RBOX_DEBUG_DEBOUNCE_OFFSET            0x30
-#define GC_RBOX_DEBUG_DEBOUNCE_DEFAULT           0x70000
-#define GC_RBOX_DEBUG_KEY_COMBO0_OFFSET          0x34
-#define GC_RBOX_DEBUG_KEY_COMBO0_DEFAULT         0xc0
-#define GC_RBOX_DEBUG_KEY_COMBO1_OFFSET          0x38
-#define GC_RBOX_DEBUG_KEY_COMBO1_DEFAULT         0x0
-#define GC_RBOX_DEBUG_KEY_COMBO2_OFFSET          0x3c
-#define GC_RBOX_DEBUG_KEY_COMBO2_DEFAULT         0x0
-#define GC_RBOX_DEBUG_BLOCK_OUTPUT_OFFSET        0x40
-#define GC_RBOX_DEBUG_BLOCK_OUTPUT_DEFAULT       0x0
-#define GC_RBOX_DEBUG_POL_OFFSET                 0x44
-#define GC_RBOX_DEBUG_POL_DEFAULT                0x1
-#define GC_RBOX_DEBUG_TERM_OFFSET                0x48
-#define GC_RBOX_DEBUG_TERM_DEFAULT               0x0
-#define GC_RBOX_DEBUG_DRIVE_OFFSET               0x4c
-#define GC_RBOX_DEBUG_DRIVE_DEFAULT              0x17f
-#define GC_RBOX_DEBUG_CLK10HZ_COUNT_OFFSET       0x50
-#define GC_RBOX_DEBUG_CLK10HZ_COUNT_DEFAULT      0x63ff
-#define GC_RBOX_DEBUG_SHORT_DELAY_COUNT_OFFSET   0x54
-#define GC_RBOX_DEBUG_SHORT_DELAY_COUNT_DEFAULT  0x4ff
-#define GC_RBOX_DEBUG_LONG_DELAY_COUNT_OFFSET    0x58
-#define GC_RBOX_DEBUG_LONG_DELAY_COUNT_DEFAULT   0x31
-#define GC_RBOX_CHECK_STATE_ENABLE_OFFSET        0x5c
-#define GC_RBOX_CHECK_STATE_ENABLE_DEFAULT       0x0
-#define GC_RBOX_CHECK_STATE0_OFFSET              0x60
-#define GC_RBOX_CHECK_STATE0_DEFAULT             0x0
-#define GC_RBOX_CHECK_STATE1_OFFSET              0x64
-#define GC_RBOX_CHECK_STATE1_DEFAULT             0x0
-#define GC_RBOX_CHECK_STATE2_OFFSET              0x68
-#define GC_RBOX_CHECK_STATE2_DEFAULT             0x0
-#define GC_RBOX_CONFIG_DEBOUNCE_OFFSET           0x6c
-#define GC_RBOX_CONFIG_DEBOUNCE_DEFAULT          0x0
-#define GC_RBOX_CONFIG_KEY_COMBO0_OFFSET         0x70
-#define GC_RBOX_CONFIG_KEY_COMBO0_DEFAULT        0x0
-#define GC_RBOX_CONFIG_KEY_COMBO1_OFFSET         0x74
-#define GC_RBOX_CONFIG_KEY_COMBO1_DEFAULT        0x0
-#define GC_RBOX_CONFIG_KEY_COMBO2_OFFSET         0x78
-#define GC_RBOX_CONFIG_KEY_COMBO2_DEFAULT        0x0
-#define GC_RBOX_CONFIG_BLOCK_OUTPUT_OFFSET       0x7c
-#define GC_RBOX_CONFIG_BLOCK_OUTPUT_DEFAULT      0x0
-#define GC_RBOX_CONFIG_POL_OFFSET                0x80
-#define GC_RBOX_CONFIG_POL_DEFAULT               0x1
-#define GC_RBOX_CONFIG_TERM_OFFSET               0x84
-#define GC_RBOX_CONFIG_TERM_DEFAULT              0x0
-#define GC_RBOX_CONFIG_DRIVE_OFFSET              0x88
-#define GC_RBOX_CONFIG_DRIVE_DEFAULT             0x0
-#define GC_RBOX_CONFIG_CLK10HZ_COUNT_OFFSET      0x8c
-#define GC_RBOX_CONFIG_CLK10HZ_COUNT_DEFAULT     0x0
-#define GC_RBOX_CONFIG_SHORT_DELAY_COUNT_OFFSET  0x90
-#define GC_RBOX_CONFIG_SHORT_DELAY_COUNT_DEFAULT 0x0
-#define GC_RBOX_CONFIG_LONG_DELAY_COUNT_OFFSET   0x94
-#define GC_RBOX_CONFIG_LONG_DELAY_COUNT_DEFAULT  0x0
-#define GC_RBOX_WAKEUP_OFFSET                    0x98
-#define GC_RBOX_WAKEUP_DEFAULT                   0x0
-#define GC_RBOX_WAKEUP_INTR_OFFSET               0x9c
-#define GC_RBOX_WAKEUP_INTR_DEFAULT              0x0
-#define GC_RBOX_VERSION_OFFSET                   0xa0
-#define GC_RBOX_VERSION_DEFAULT                  0x1014125
-#define GC_RDD_VERSION_OFFSET                    0x0
-#define GC_RDD_VERSION_DEFAULT                   0x24011f09
-#define GC_RDD_INT_ENABLE_OFFSET                 0x4
-#define GC_RDD_INT_ENABLE_DEFAULT                0x0
-#define GC_RDD_INT_STATE_OFFSET                  0x8
-#define GC_RDD_INT_STATE_DEFAULT                 0x0
-#define GC_RDD_INT_TEST_OFFSET                   0xc
-#define GC_RDD_INT_TEST_DEFAULT                  0x0
-#define GC_RDD_POWER_DOWN_B_OFFSET               0x10
-#define GC_RDD_POWER_DOWN_B_DEFAULT              0x0
-#define GC_RDD_ANTEST_OFFSET                     0x14
-#define GC_RDD_ANTEST_DEFAULT                    0x0
-#define GC_RDD_MAX_WAIT_TIME_COUNTER_OFFSET      0x18
-#define GC_RDD_MAX_WAIT_TIME_COUNTER_DEFAULT     0xc80
-#define GC_RDD_CUR_WAIT_TIME_COUNTER_OFFSET      0x1c
-#define GC_RDD_CUR_WAIT_TIME_COUNTER_DEFAULT     0x0
-#define GC_RDD_REF_ADJ_OFFSET                    0x20
-#define GC_RDD_REF_ADJ_DEFAULT                   0x15
-#define GC_RDD_INPUT_PIN_VALUES_OFFSET           0x24
-#define GC_RDD_INPUT_PIN_VALUES_DEFAULT          0x18
-#define GC_RDD_PROG_DEBUG_STATE_MAP_OFFSET       0x28
-#define GC_RDD_PROG_DEBUG_STATE_MAP_DEFAULT      0x420
-#define GC_RDD_CUR_STABLE_STATE_OFFSET           0x2c
-#define GC_RDD_CUR_STABLE_STATE_DEFAULT          0x2
-#define GC_RTC_CTRL_OFFSET                       0x0
-#define GC_RTC_CTRL_DEFAULT                      0x0
-#define GC_RTC_PINMUX_EN_OFFSET                  0x4
-#define GC_RTC_PINMUX_EN_DEFAULT                 0x0
-#define GC_RTC_PULSE_STRETCH_OFFSET              0x8
-#define GC_RTC_PULSE_STRETCH_DEFAULT             0x0
-#define GC_RTC_SW_TRIM_EN_OFFSET                 0xc
-#define GC_RTC_SW_TRIM_EN_DEFAULT                0x0
-#define GC_RTC_SW_TRIM_COUNTER_OFFSET            0x10
-#define GC_RTC_SW_TRIM_COUNTER_DEFAULT           0x0
-#define GC_SPI_CTRL_OFFSET                       0x0
-#define GC_SPI_CTRL_DEFAULT                      0x2800800
-#define GC_SPI_XACT_OFFSET                       0x4
-#define GC_SPI_XACT_DEFAULT                      0xe
-#define GC_SPI_ICTRL_OFFSET                      0x8
-#define GC_SPI_ICTRL_DEFAULT                     0x0
-#define GC_SPI_ISTATE_OFFSET                     0xc
-#define GC_SPI_ISTATE_DEFAULT                    0x0
-#define GC_SPI_ISTATE_CLR_OFFSET                 0x10
-#define GC_SPI_ISTATE_CLR_DEFAULT                0x0
-#define GC_SPI_OVRD_OFFSET                       0x14
-#define GC_SPI_OVRD_DEFAULT                      0x8
-#define GC_SPI_VAL_OFFSET                        0x18
-#define GC_SPI_VAL_DEFAULT                       0x0
-#define GC_SPI_ITCR_OFFSET                       0xf00
-#define GC_SPI_ITCR_DEFAULT                      0x0
-#define GC_SPI_ITOP_OFFSET                       0xf04
-#define GC_SPI_ITOP_DEFAULT                      0x0
-#define GC_SPI_DATA_OFFSET                       0x1000
-#define GC_SPI_TX_DATA_OFFSET                    0x1000
-#define GC_SPI_RX_DATA_OFFSET                    0x1080
-#define GC_SPS_CTRL_OFFSET                       0x0
-#define GC_SPS_CTRL_DEFAULT                      0x1
-#define GC_SPS_DUMMY_WORD_OFFSET                 0x4
-#define GC_SPS_DUMMY_WORD_DEFAULT                0xff
-#define GC_SPS_STATUS01_OFFSET                   0x8
-#define GC_SPS_STATUS01_DEFAULT                  0x0
-#define GC_SPS_STATUS23_OFFSET                   0xc
-#define GC_SPS_STATUS23_DEFAULT                  0x0
-#define GC_SPS_STATUS45_OFFSET                   0x10
-#define GC_SPS_STATUS45_DEFAULT                  0x0
-#define GC_SPS_STATUS67_OFFSET                   0x14
-#define GC_SPS_STATUS67_DEFAULT                  0x0
-#define GC_SPS_CTRL01_OFFSET                     0x18
-#define GC_SPS_CTRL01_DEFAULT                    0x0
-#define GC_SPS_CTRL23_OFFSET                     0x1c
-#define GC_SPS_CTRL23_DEFAULT                    0x0
-#define GC_SPS_CTRL45_OFFSET                     0x20
-#define GC_SPS_CTRL45_DEFAULT                    0x0
-#define GC_SPS_CTRL67_OFFSET                     0x24
-#define GC_SPS_CTRL67_DEFAULT                    0x0
-#define GC_SPS_FIFO_CTRL_OFFSET                  0x28
-#define GC_SPS_FIFO_CTRL_DEFAULT                 0x0
-#define GC_SPS_TXFIFO_SIZE_OFFSET                0x2c
-#define GC_SPS_TXFIFO_SIZE_DEFAULT               0x0
-#define GC_SPS_TXFIFO_RPTR_OFFSET                0x30
-#define GC_SPS_TXFIFO_RPTR_DEFAULT               0x0
-#define GC_SPS_TXFIFO_WPTR_OFFSET                0x34
-#define GC_SPS_TXFIFO_WPTR_DEFAULT               0x0
-#define GC_SPS_TXFIFO_THRESHOLD_OFFSET           0x38
-#define GC_SPS_TXFIFO_THRESHOLD_DEFAULT          0x0
-#define GC_SPS_RXFIFO_SIZE_OFFSET                0x3c
-#define GC_SPS_RXFIFO_SIZE_DEFAULT               0x0
-#define GC_SPS_RXFIFO_RPTR_OFFSET                0x40
-#define GC_SPS_RXFIFO_RPTR_DEFAULT               0x0
-#define GC_SPS_RXFIFO_WPTR_OFFSET                0x44
-#define GC_SPS_RXFIFO_WPTR_DEFAULT               0x0
-#define GC_SPS_RXFIFO_THRESHOLD_OFFSET           0x48
-#define GC_SPS_RXFIFO_THRESHOLD_DEFAULT          0x0
-#define GC_SPS_OVRD_OFFSET                       0x4c
-#define GC_SPS_OVRD_DEFAULT                      0x0
-#define GC_SPS_VAL_OFFSET                        0x50
-#define GC_SPS_VAL_DEFAULT                       0x0
-#define GC_SPS_ISTATE_OFFSET                     0x54
-#define GC_SPS_ISTATE_DEFAULT                    0x0
-#define GC_SPS_ISTATE_CLR_OFFSET                 0x58
-#define GC_SPS_ISTATE_CLR_DEFAULT                0x0
-#define GC_SPS_ITCR_OFFSET                       0x5c
-#define GC_SPS_ITCR_DEFAULT                      0x0
-#define GC_SPS_ITOP_OFFSET                       0x60
-#define GC_SPS_ITOP_DEFAULT                      0x0
-#define GC_SPS_ICTRL_OFFSET                      0x64
-#define GC_SPS_ICTRL_DEFAULT                     0x0
-#define GC_SPS_EEPROM_CTRL_OFFSET                0x400
-#define GC_SPS_EEPROM_CTRL_DEFAULT               0x480
-#define GC_SPS_MAILBOX_RD_OPCODE_OFFSET          0x404
-#define GC_SPS_MAILBOX_RD_OPCODE_DEFAULT         0x0
-#define GC_SPS_FAST_DUAL_RD_OPCODE_OFFSET        0x408
-#define GC_SPS_FAST_DUAL_RD_OPCODE_DEFAULT       0x3b
-#define GC_SPS_BUSY_OPCODE0_OFFSET               0x40c
-#define GC_SPS_BUSY_OPCODE0_DEFAULT              0x0
-#define GC_SPS_BUSY_OPCODE1_OFFSET               0x410
-#define GC_SPS_BUSY_OPCODE1_DEFAULT              0x0
-#define GC_SPS_BUSY_OPCODE2_OFFSET               0x414
-#define GC_SPS_BUSY_OPCODE2_DEFAULT              0x0
-#define GC_SPS_BUSY_OPCODE3_OFFSET               0x418
-#define GC_SPS_BUSY_OPCODE3_DEFAULT              0x0
-#define GC_SPS_BUSY_OPCODE4_OFFSET               0x41c
-#define GC_SPS_BUSY_OPCODE4_DEFAULT              0x0
-#define GC_SPS_BUSY_OPCODE5_OFFSET               0x420
-#define GC_SPS_BUSY_OPCODE5_DEFAULT              0x0
-#define GC_SPS_BUSY_OPCODE6_OFFSET               0x424
-#define GC_SPS_BUSY_OPCODE6_DEFAULT              0x0
-#define GC_SPS_BUSY_OPCODE7_OFFSET               0x428
-#define GC_SPS_BUSY_OPCODE7_DEFAULT              0x0
-#define GC_SPS_EEPROM_STATUS_OFFSET              0x42c
-#define GC_SPS_EEPROM_STATUS_DEFAULT             0x0
-#define GC_SPS_EEPROM_BUSY_STATUS_OFFSET         0x430
-#define GC_SPS_EEPROM_BUSY_STATUS_DEFAULT        0x0
-#define GC_SPS_EEPROM_BUSY_BIT_VECTOR_OFFSET     0x434
-#define GC_SPS_EEPROM_BUSY_BIT_VECTOR_DEFAULT    0x1
-#define GC_SPS_EEPROM_WEL_STATUS_OFFSET          0x438
-#define GC_SPS_EEPROM_WEL_STATUS_DEFAULT         0x0
-#define GC_SPS_JEDEC_ID0_OFFSET                  0x43c
-#define GC_SPS_JEDEC_ID0_DEFAULT                 0x0
-#define GC_SPS_JEDEC_ID1_OFFSET                  0x440
-#define GC_SPS_JEDEC_ID1_DEFAULT                 0x0
-#define GC_SPS_JEDEC_ID2_OFFSET                  0x444
-#define GC_SPS_JEDEC_ID2_DEFAULT                 0x0
-#define GC_SPS_SELF_DISCV_PARAM0_OFFSET          0x448
-#define GC_SPS_SELF_DISCV_PARAM0_DEFAULT         0x0
-#define GC_SPS_SELF_DISCV_PARAM1_OFFSET          0x44c
-#define GC_SPS_SELF_DISCV_PARAM1_DEFAULT         0x0
-#define GC_SPS_SELF_DISCV_PARAM2_OFFSET          0x450
-#define GC_SPS_SELF_DISCV_PARAM2_DEFAULT         0x0
-#define GC_SPS_SELF_DISCV_PARAM3_OFFSET          0x454
-#define GC_SPS_SELF_DISCV_PARAM3_DEFAULT         0x0
-#define GC_SPS_SELF_DISCV_PARAM4_OFFSET          0x458
-#define GC_SPS_SELF_DISCV_PARAM4_DEFAULT         0x0
-#define GC_SPS_SELF_DISCV_PARAM5_OFFSET          0x45c
-#define GC_SPS_SELF_DISCV_PARAM5_DEFAULT         0x0
-#define GC_SPS_SELF_DISCV_PARAM6_OFFSET          0x460
-#define GC_SPS_SELF_DISCV_PARAM6_DEFAULT         0x0
-#define GC_SPS_SELF_DISCV_PARAM7_OFFSET          0x464
-#define GC_SPS_SELF_DISCV_PARAM7_DEFAULT         0x0
-#define GC_SPS_SELF_DISCV_PARAM8_OFFSET          0x468
-#define GC_SPS_SELF_DISCV_PARAM8_DEFAULT         0x0
-#define GC_SPS_SELF_DISCV_PARAM9_OFFSET          0x46c
-#define GC_SPS_SELF_DISCV_PARAM9_DEFAULT         0x0
-#define GC_SPS_SELF_DISCV_PARAM10_OFFSET         0x470
-#define GC_SPS_SELF_DISCV_PARAM10_DEFAULT        0x0
-#define GC_SPS_SELF_DISCV_PARAM11_OFFSET         0x474
-#define GC_SPS_SELF_DISCV_PARAM11_DEFAULT        0x0
-#define GC_SPS_SELF_DISCV_PARAM12_OFFSET         0x478
-#define GC_SPS_SELF_DISCV_PARAM12_DEFAULT        0x0
-#define GC_SPS_SELF_DISCV_PARAM13_OFFSET         0x47c
-#define GC_SPS_SELF_DISCV_PARAM13_DEFAULT        0x0
-#define GC_SPS_SELF_DISCV_PARAM14_OFFSET         0x480
-#define GC_SPS_SELF_DISCV_PARAM14_DEFAULT        0x0
-#define GC_SPS_SELF_DISCV_PARAM15_OFFSET         0x484
-#define GC_SPS_SELF_DISCV_PARAM15_DEFAULT        0x0
-#define GC_SPS_SELF_DISCV_PARAM16_OFFSET         0x488
-#define GC_SPS_SELF_DISCV_PARAM16_DEFAULT        0x0
-#define GC_SPS_SELF_DISCV_PARAM17_OFFSET         0x48c
-#define GC_SPS_SELF_DISCV_PARAM17_DEFAULT        0x0
-#define GC_SPS_SELF_DISCV_PARAM18_OFFSET         0x490
-#define GC_SPS_SELF_DISCV_PARAM18_DEFAULT        0x0
-#define GC_SPS_SELF_DISCV_PARAM19_OFFSET         0x494
-#define GC_SPS_SELF_DISCV_PARAM19_DEFAULT        0x0
-#define GC_SPS_SELF_DISCV_PARAM20_OFFSET         0x498
-#define GC_SPS_SELF_DISCV_PARAM20_DEFAULT        0x0
-#define GC_SPS_SELF_DISCV_PARAM21_OFFSET         0x49c
-#define GC_SPS_SELF_DISCV_PARAM21_DEFAULT        0x0
-#define GC_SPS_SELF_DISCV_PARAM22_OFFSET         0x4a0
-#define GC_SPS_SELF_DISCV_PARAM22_DEFAULT        0x0
-#define GC_SPS_SELF_DISCV_PARAM23_OFFSET         0x4a4
-#define GC_SPS_SELF_DISCV_PARAM23_DEFAULT        0x0
-#define GC_SPS_SELF_DISCV_PARAM24_OFFSET         0x4a8
-#define GC_SPS_SELF_DISCV_PARAM24_DEFAULT        0x0
-#define GC_SPS_SELF_DISCV_PARAM25_OFFSET         0x4ac
-#define GC_SPS_SELF_DISCV_PARAM25_DEFAULT        0x0
-#define GC_SPS_SELF_DISCV_PARAM26_OFFSET         0x4b0
-#define GC_SPS_SELF_DISCV_PARAM26_DEFAULT        0x0
-#define GC_SPS_SELF_DISCV_PARAM27_OFFSET         0x4b4
-#define GC_SPS_SELF_DISCV_PARAM27_DEFAULT        0x0
-#define GC_SPS_SELF_DISCV_PARAM28_OFFSET         0x4b8
-#define GC_SPS_SELF_DISCV_PARAM28_DEFAULT        0x0
-#define GC_SPS_SELF_DISCV_PARAM29_OFFSET         0x4bc
-#define GC_SPS_SELF_DISCV_PARAM29_DEFAULT        0x0
-#define GC_SPS_SELF_DISCV_PARAM30_OFFSET         0x4c0
-#define GC_SPS_SELF_DISCV_PARAM30_DEFAULT        0x0
-#define GC_SPS_SELF_DISCV_PARAM31_OFFSET         0x4c4
-#define GC_SPS_SELF_DISCV_PARAM31_DEFAULT        0x0
-#define GC_SPS_UNMAPPED_RETURN_VAL_OFFSET        0x4c8
-#define GC_SPS_UNMAPPED_RETURN_VAL_DEFAULT       0x0
-#define GC_SPS_RAM_VIRTUAL_PAGE0_OFFSET          0x4cc
-#define GC_SPS_RAM_VIRTUAL_PAGE0_DEFAULT         0x0
-#define GC_SPS_RAM_VIRTUAL_PAGE1_OFFSET          0x4d0
-#define GC_SPS_RAM_VIRTUAL_PAGE1_DEFAULT         0x0
-#define GC_SPS_RAM_VIRTUAL_PAGE2_OFFSET          0x4d4
-#define GC_SPS_RAM_VIRTUAL_PAGE2_DEFAULT         0x0
-#define GC_SPS_RAM_VIRTUAL_PAGE3_OFFSET          0x4d8
-#define GC_SPS_RAM_VIRTUAL_PAGE3_DEFAULT         0x0
-#define GC_SPS_RAM_CTRL_PAGE0_OFFSET             0x4dc
-#define GC_SPS_RAM_CTRL_PAGE0_DEFAULT            0x0
-#define GC_SPS_RAM_CTRL_PAGE1_OFFSET             0x4e0
-#define GC_SPS_RAM_CTRL_PAGE1_DEFAULT            0x0
-#define GC_SPS_RAM_CTRL_PAGE2_OFFSET             0x4e4
-#define GC_SPS_RAM_CTRL_PAGE2_DEFAULT            0x0
-#define GC_SPS_RAM_CTRL_PAGE3_OFFSET             0x4e8
-#define GC_SPS_RAM_CTRL_PAGE3_DEFAULT            0x0
-#define GC_SPS_INT_FLASH_BASE_PAGE_OFFSET        0x4ec
-#define GC_SPS_INT_FLASH_BASE_PAGE_DEFAULT       0x0
-#define GC_SPS_INT_FLASH_LIMIT_PAGE_OFFSET       0x4f0
-#define GC_SPS_INT_FLASH_LIMIT_PAGE_DEFAULT      0x0
-#define GC_SPS_EXT_FLASH_BASE_PAGE_OFFSET        0x4f4
-#define GC_SPS_EXT_FLASH_BASE_PAGE_DEFAULT       0x0
-#define GC_SPS_EXT_FLASH_LIMIT_PAGE_OFFSET       0x4f8
-#define GC_SPS_EXT_FLASH_LIMIT_PAGE_DEFAULT      0x0
-#define GC_SPS_INT_FLASH_TRANS_BIT_VECTOR_OFFSET 0x4fc
-#define GC_SPS_INT_FLASH_TRANS_BIT_VECTOR_DEFAULT 0x0
-#define GC_SPS_INT_FLASH_TRANS_ADDR_OFFSET       0x500
-#define GC_SPS_INT_FLASH_TRANS_ADDR_DEFAULT      0x0
-#define GC_SPS_EXT_FLASH_TRANS_BIT_VECTOR_OFFSET 0x504
-#define GC_SPS_EXT_FLASH_TRANS_BIT_VECTOR_DEFAULT 0x0
-#define GC_SPS_EXT_FLASH_TRANS_ADDR_OFFSET       0x508
-#define GC_SPS_EXT_FLASH_TRANS_ADDR_DEFAULT      0x0
-#define GC_SPS_CMD_MEM_RPTR_OFFSET               0x50c
-#define GC_SPS_CMD_MEM_RPTR_DEFAULT              0x0
-#define GC_SPS_CMD_ADDR_FIFO_OFFSET              0x510
-#define GC_SPS_CMD_ADDR_FIFO_DEFAULT             0x0
-#define GC_SPS_CMD_ADDR_FIFO_EMPTY_OFFSET        0x514
-#define GC_SPS_CMD_ADDR_FIFO_EMPTY_DEFAULT       0x0
-#define GC_SPS_FDA_MSB_ROTATE_BASE_ADDR_OFFSET   0x518
-#define GC_SPS_FDA_MSB_ROTATE_BASE_ADDR_DEFAULT  0x0
-#define GC_SPS_FDA_MSB_LEVEL2_ROTATE_BASE_ADDR_OFFSET 0x51c
-#define GC_SPS_FDA_MSB_LEVEL2_ROTATE_BASE_ADDR_DEFAULT 0x0
-#define GC_SPS_PASSTHRU_FILTER_RULE0_OFFSET      0x520
-#define GC_SPS_PASSTHRU_FILTER_RULE0_DEFAULT     0x0
-#define GC_SPS_PASSTHRU_FILTER_RULE1_OFFSET      0x524
-#define GC_SPS_PASSTHRU_FILTER_RULE1_DEFAULT     0x0
-#define GC_SPS_PASSTHRU_FILTER_RULE2_OFFSET      0x528
-#define GC_SPS_PASSTHRU_FILTER_RULE2_DEFAULT     0x0
-#define GC_SPS_PASSTHRU_FILTER_RULE3_OFFSET      0x52c
-#define GC_SPS_PASSTHRU_FILTER_RULE3_DEFAULT     0x0
-#define GC_SPS_PASSTHRU_FILTER_RULE4_OFFSET      0x530
-#define GC_SPS_PASSTHRU_FILTER_RULE4_DEFAULT     0x0
-#define GC_SPS_PASSTHRU_FILTER_RULE5_OFFSET      0x534
-#define GC_SPS_PASSTHRU_FILTER_RULE5_DEFAULT     0x0
-#define GC_SPS_PASSTHRU_FILTER_RULE6_OFFSET      0x538
-#define GC_SPS_PASSTHRU_FILTER_RULE6_DEFAULT     0x0
-#define GC_SPS_PASSTHRU_FILTER_RULE7_OFFSET      0x53c
-#define GC_SPS_PASSTHRU_FILTER_RULE7_DEFAULT     0x0
-#define GC_SPS_PASSTHRU_FILTER_RULE8_OFFSET      0x540
-#define GC_SPS_PASSTHRU_FILTER_RULE8_DEFAULT     0x0
-#define GC_SPS_PASSTHRU_FILTER_RULE9_OFFSET      0x544
-#define GC_SPS_PASSTHRU_FILTER_RULE9_DEFAULT     0x0
-#define GC_SPS_PASSTHRU_FILTER_RULE10_OFFSET     0x548
-#define GC_SPS_PASSTHRU_FILTER_RULE10_DEFAULT    0x0
-#define GC_SPS_PASSTHRU_FILTER_RULE11_OFFSET     0x54c
-#define GC_SPS_PASSTHRU_FILTER_RULE11_DEFAULT    0x0
-#define GC_SPS_PASSTHRU_FILTER_RULE12_OFFSET     0x550
-#define GC_SPS_PASSTHRU_FILTER_RULE12_DEFAULT    0x0
-#define GC_SPS_PASSTHRU_FILTER_RULE13_OFFSET     0x554
-#define GC_SPS_PASSTHRU_FILTER_RULE13_DEFAULT    0x0
-#define GC_SPS_PASSTHRU_FILTER_RULE14_OFFSET     0x558
-#define GC_SPS_PASSTHRU_FILTER_RULE14_DEFAULT    0x0
-#define GC_SPS_PASSTHRU_FILTER_RULE15_OFFSET     0x55c
-#define GC_SPS_PASSTHRU_FILTER_RULE15_DEFAULT    0x0
-#define GC_SPS_VIRTUAL_ADDR_FILTER_OFFSET        0x560
-#define GC_SPS_VIRTUAL_ADDR_FILTER_DEFAULT       0xffffffff
-#define GC_SPS_DEBUG_CS_CNT_OFFSET               0x564
-#define GC_SPS_DEBUG_CS_CNT_DEFAULT              0x0
-#define GC_SPS_TESTBUS_SEL_OFFSET                0x568
-#define GC_SPS_TESTBUS_SEL_DEFAULT               0x0
-#define GC_SPS_DPU_TESTBUS_OFFSET                0x56c
-#define GC_SPS_DPU_TESTBUS_DEFAULT               0x0
-#define GC_SPS_RD_CMD_TESTBUS_OFFSET             0x570
-#define GC_SPS_RD_CMD_TESTBUS_DEFAULT            0x0
-#define GC_SPS_CMD_PASSTHRU_TESTBUS_OFFSET       0x574
-#define GC_SPS_CMD_PASSTHRU_TESTBUS_DEFAULT      0x0
-#define GC_SPS_EEPROM_INT_ENABLE_OFFSET          0x578
-#define GC_SPS_EEPROM_INT_ENABLE_DEFAULT         0x0
-#define GC_SPS_EEPROM_INT_STATE_OFFSET           0x57c
-#define GC_SPS_EEPROM_INT_STATE_DEFAULT          0x0
-#define GC_SPS_EEPROM_INT_TEST_OFFSET            0x580
-#define GC_SPS_EEPROM_INT_TEST_DEFAULT           0x0
-#define GC_SPS_DATA_OFFSET                       0x1000
-#define GC_SPS_TX_DATA_OFFSET                    0x1000
-#define GC_SPS_RX_DATA_OFFSET                    0x1400
-#define GC_SPS_ROM_SP_OFFSET                     0x1000
-#define GC_SPS_ROM_CMD_OFFSET                    0x2000
-#define GC_SWDP_TRICKBOX_HALT_OFFSET             0x0
-#define GC_SWDP_TRICKBOX_HALT_DEFAULT            0x0
-#define GC_SWDP_TRICKBOX_UART_OFFSET             0x4
-#define GC_SWDP_TRICKBOX_UART_DEFAULT            0x0
-#define GC_SWDP_TRICKBOX_ERROR_OFFSET            0x8
-#define GC_SWDP_TRICKBOX_ERROR_DEFAULT           0x0
-#define GC_SWDP_TRICKBOX_FATAL_OFFSET            0xc
-#define GC_SWDP_TRICKBOX_FATAL_DEFAULT           0x0
-#define GC_SWDP_SCRATCH_REG0_OFFSET              0x10
-#define GC_SWDP_SCRATCH_REG0_DEFAULT             0x0
-#define GC_SWDP_SCRATCH_REG1_OFFSET              0x14
-#define GC_SWDP_SCRATCH_REG1_DEFAULT             0x0
-#define GC_SWDP_SCRATCH_REG2_OFFSET              0x18
-#define GC_SWDP_SCRATCH_REG2_DEFAULT             0x0
-#define GC_SWDP_SCRATCH_REG3_OFFSET              0x1c
-#define GC_SWDP_SCRATCH_REG3_DEFAULT             0x0
-#define GC_SWDP_APPSVTOR_OFFSET                  0x20
-#define GC_SWDP_APPSVTOR_DEFAULT                 0xffffffff
-#define GC_SWDP_XML_MD5SUM_OFFSET                0x24
-#define GC_SWDP_XML_MD5SUM_DEFAULT               0x0
-#define GC_SWDP_HEADER_MD5SUM_OFFSET             0x28
-#define GC_SWDP_HEADER_MD5SUM_DEFAULT            0x0
-#define GC_SWDP_P4_LAST_SYNC_OFFSET              0x2c
-#define GC_SWDP_P4_LAST_SYNC_DEFAULT             0x0
-#define GC_SWDP_BUILD_DATE_OFFSET                0x30
-#define GC_SWDP_BUILD_DATE_DEFAULT               0x0
-#define GC_SWDP_BUILD_TIME_OFFSET                0x34
-#define GC_SWDP_BUILD_TIME_DEFAULT               0x0
-#define GC_SWDP_TEST_PORT_DISABLE_OFFSET         0x38
-#define GC_SWDP_TEST_PORT_DISABLE_DEFAULT        0x0
-#define GC_TEMP_VERSION_OFFSET                   0x0
-#define GC_TEMP_VERSION_DEFAULT                  0x1014125
-#define GC_TEMP_ADC_INT_ENABLE_OFFSET            0x4
-#define GC_TEMP_ADC_INT_ENABLE_DEFAULT           0x0
-#define GC_TEMP_ADC_INT_STATE_OFFSET             0x8
-#define GC_TEMP_ADC_INT_STATE_DEFAULT            0x0
-#define GC_TEMP_ADC_INT_TEST_OFFSET              0xc
-#define GC_TEMP_ADC_INT_TEST_DEFAULT             0x0
-#define GC_TEMP_SENSE_CAL_OFFSET_OFFSET          0x10
-#define GC_TEMP_SENSE_CAL_OFFSET_DEFAULT         0x0
-#define GC_TEMP_ADC_ANALOG_CTRL_OFFSET           0x14
-#define GC_TEMP_ADC_ANALOG_CTRL_DEFAULT          0x35
-#define GC_TEMP_ADC_FSM_CTRL_OFFSET              0x18
-#define GC_TEMP_ADC_FSM_CTRL_DEFAULT             0x38864
-#define GC_TEMP_ADC_CLKDIV2_ENABLE_OFFSET        0x1c
-#define GC_TEMP_ADC_CLKDIV2_ENABLE_DEFAULT       0x0
-#define GC_TEMP_ADC_ONESHOT_ACQ_OFFSET           0x20
-#define GC_TEMP_ADC_ONESHOT_ACQ_DEFAULT          0x0
-#define GC_TEMP_ADC_POWER_DOWN_B_OFFSET          0x24
-#define GC_TEMP_ADC_POWER_DOWN_B_DEFAULT         0x0
-#define GC_TEMP_ADC_OPERATION_OFFSET             0x28
-#define GC_TEMP_ADC_OPERATION_DEFAULT            0x0
-#define GC_TEMP_ADC_IOUT_OFFSET                  0x2c
-#define GC_TEMP_ADC_IOUT_DEFAULT                 0x0
-#define GC_TEMP_ADC_SUM2_OFFSET                  0x30
-#define GC_TEMP_ADC_SUM2_DEFAULT                 0x0
-#define GC_TEMP_ADC_SUM4_OFFSET                  0x34
-#define GC_TEMP_ADC_SUM4_DEFAULT                 0x0
-#define GC_TEMP_ADC_SUM8_OFFSET                  0x38
-#define GC_TEMP_ADC_SUM8_DEFAULT                 0x0
-#define GC_TEMP_ADC_REF_CHOP_OFFSET              0x3c
-#define GC_TEMP_ADC_REF_CHOP_DEFAULT             0x0
-#define GC_TEMP_ADC_CONFIG_OFFSET                0x40
-#define GC_TEMP_ADC_CONFIG_DEFAULT               0x0
-#define GC_TEMP_ABS_LIMIT_OFFSET                 0x44
-#define GC_TEMP_ABS_LIMIT_DEFAULT                0x0
-#define GC_TEMP_DIFF_PARAM_OFFSET                0x48
-#define GC_TEMP_DIFF_PARAM_DEFAULT               0x0
-#define GC_TEMP_METRIC_OFFSET                    0x4c
-#define GC_TEMP_METRIC_DEFAULT                   0x0
-#define GC_TEMP_SAMPLE_CTR_STATE_OFFSET          0x50
-#define GC_TEMP_SAMPLE_CTR_STATE_DEFAULT         0x0
-#define GC_TEMP_ANTEST_EN_OFFSET                 0x54
-#define GC_TEMP_ANTEST_EN_DEFAULT                0x0
-#define GC_TIMEHS_TIMER1LOAD_OFFSET              0x0
-#define GC_TIMEHS_TIMER1LOAD_DEFAULT             0x0
-#define GC_TIMEHS_TIMER1VALUE_OFFSET             0x4
-#define GC_TIMEHS_TIMER1VALUE_DEFAULT            0x0
-#define GC_TIMEHS_TIMER1CONTROL_OFFSET           0x8
-#define GC_TIMEHS_TIMER1CONTROL_DEFAULT          0x20
-#define GC_TIMEHS_TIMER1INTCLR_OFFSET            0xc
-#define GC_TIMEHS_TIMER1INTCLR_DEFAULT           0x0
-#define GC_TIMEHS_TIMER1RIS_OFFSET               0x10
-#define GC_TIMEHS_TIMER1RIS_DEFAULT              0x0
-#define GC_TIMEHS_TIMER1MIS_OFFSET               0x14
-#define GC_TIMEHS_TIMER1MIS_DEFAULT              0x0
-#define GC_TIMEHS_TIMER1BGLOAD_OFFSET            0x18
-#define GC_TIMEHS_TIMER1BGLOAD_DEFAULT           0x0
-#define GC_TIMEHS_TIMER2LOAD_OFFSET              0x20
-#define GC_TIMEHS_TIMER2LOAD_DEFAULT             0x0
-#define GC_TIMEHS_TIMER2VALUE_OFFSET             0x24
-#define GC_TIMEHS_TIMER2VALUE_DEFAULT            0x0
-#define GC_TIMEHS_TIMER2CONTROL_OFFSET           0x28
-#define GC_TIMEHS_TIMER2CONTROL_DEFAULT          0x20
-#define GC_TIMEHS_TIMER2INTCLR_OFFSET            0x2c
-#define GC_TIMEHS_TIMER2INTCLR_DEFAULT           0x0
-#define GC_TIMEHS_TIMER2RIS_OFFSET               0x30
-#define GC_TIMEHS_TIMER2RIS_DEFAULT              0x0
-#define GC_TIMEHS_TIMER2MIS_OFFSET               0x34
-#define GC_TIMEHS_TIMER2MIS_DEFAULT              0x0
-#define GC_TIMEHS_TIMER2BGLOAD_OFFSET            0x38
-#define GC_TIMEHS_TIMER2BGLOAD_DEFAULT           0x0
-#define GC_TIMEHS_TIMERITCR_OFFSET               0xf00
-#define GC_TIMEHS_TIMERITCR_DEFAULT              0x0
-#define GC_TIMEHS_TIMERITOP_OFFSET               0xf04
-#define GC_TIMEHS_TIMERITOP_DEFAULT              0x0
-#define GC_TIMEHS_TIMERPERIPHID4_OFFSET          0xfd0
-#define GC_TIMEHS_TIMERPERIPHID4_DEFAULT         0x4
-#define GC_TIMEHS_TIMERPERIPHID5_OFFSET          0xfd4
-#define GC_TIMEHS_TIMERPERIPHID5_DEFAULT         0x0
-#define GC_TIMEHS_TIMERPERIPHID6_OFFSET          0xfd8
-#define GC_TIMEHS_TIMERPERIPHID6_DEFAULT         0x0
-#define GC_TIMEHS_TIMERPERIPHID7_OFFSET          0xfdc
-#define GC_TIMEHS_TIMERPERIPHID7_DEFAULT         0x0
-#define GC_TIMEHS_TIMERPERIPHID0_OFFSET          0xfe0
-#define GC_TIMEHS_TIMERPERIPHID0_DEFAULT         0x23
-#define GC_TIMEHS_TIMERPERIPHID1_OFFSET          0xfe4
-#define GC_TIMEHS_TIMERPERIPHID1_DEFAULT         0xb8
-#define GC_TIMEHS_TIMERPERIPHID2_OFFSET          0xfe8
-#define GC_TIMEHS_TIMERPERIPHID2_DEFAULT         0xb
-#define GC_TIMEHS_TIMERPERIPHID3_OFFSET          0xfec
-#define GC_TIMEHS_TIMERPERIPHID3_DEFAULT         0x0
-#define GC_TIMEHS_TIMERPCELLID0_OFFSET           0xff0
-#define GC_TIMEHS_TIMERPCELLID0_DEFAULT          0xd
-#define GC_TIMEHS_TIMERPCELLID1_OFFSET           0xff4
-#define GC_TIMEHS_TIMERPCELLID1_DEFAULT          0xf0
-#define GC_TIMEHS_TIMERPCELLID2_OFFSET           0xff8
-#define GC_TIMEHS_TIMERPCELLID2_DEFAULT          0x5
-#define GC_TIMEHS_TIMERPCELLID3_OFFSET           0xffc
-#define GC_TIMEHS_TIMERPCELLID3_DEFAULT          0xb1
-#define GC_TIMELS_TIMER0_CONTROL_OFFSET          0x0
-#define GC_TIMELS_TIMER0_CONTROL_DEFAULT         0x0
-#define GC_TIMELS_TIMER0_STATUS_OFFSET           0x4
-#define GC_TIMELS_TIMER0_STATUS_DEFAULT          0x0
-#define GC_TIMELS_TIMER0_LOAD_OFFSET             0x8
-#define GC_TIMELS_TIMER0_LOAD_DEFAULT            0x0
-#define GC_TIMELS_TIMER0_RELOADVAL_OFFSET        0xc
-#define GC_TIMELS_TIMER0_RELOADVAL_DEFAULT       0xffffffff
-#define GC_TIMELS_TIMER0_VALUE_OFFSET            0x10
-#define GC_TIMELS_TIMER0_VALUE_DEFAULT           0x0
-#define GC_TIMELS_TIMER0_STEP_OFFSET             0x14
-#define GC_TIMELS_TIMER0_STEP_DEFAULT            0x0
-#define GC_TIMELS_TIMER0_IER_OFFSET              0x18
-#define GC_TIMELS_TIMER0_IER_DEFAULT             0x0
-#define GC_TIMELS_TIMER0_ISR_OFFSET              0x1c
-#define GC_TIMELS_TIMER0_ISR_DEFAULT             0x0
-#define GC_TIMELS_TIMER0_IPR_OFFSET              0x20
-#define GC_TIMELS_TIMER0_IPR_DEFAULT             0x0
-#define GC_TIMELS_TIMER0_IAR_OFFSET              0x24
-#define GC_TIMELS_TIMER0_IAR_DEFAULT             0x0
-#define GC_TIMELS_TIMER0_WAKEUP_ACK_OFFSET       0x28
-#define GC_TIMELS_TIMER0_WAKEUP_ACK_DEFAULT      0x0
-#define GC_TIMELS_TIMER1_CONTROL_OFFSET          0x40
-#define GC_TIMELS_TIMER1_CONTROL_DEFAULT         0x0
-#define GC_TIMELS_TIMER1_STATUS_OFFSET           0x44
-#define GC_TIMELS_TIMER1_STATUS_DEFAULT          0x0
-#define GC_TIMELS_TIMER1_LOAD_OFFSET             0x48
-#define GC_TIMELS_TIMER1_LOAD_DEFAULT            0x0
-#define GC_TIMELS_TIMER1_RELOADVAL_OFFSET        0x4c
-#define GC_TIMELS_TIMER1_RELOADVAL_DEFAULT       0xffffffff
-#define GC_TIMELS_TIMER1_VALUE_OFFSET            0x50
-#define GC_TIMELS_TIMER1_VALUE_DEFAULT           0x0
-#define GC_TIMELS_TIMER1_STEP_OFFSET             0x54
-#define GC_TIMELS_TIMER1_STEP_DEFAULT            0x0
-#define GC_TIMELS_TIMER1_IER_OFFSET              0x58
-#define GC_TIMELS_TIMER1_IER_DEFAULT             0x0
-#define GC_TIMELS_TIMER1_ISR_OFFSET              0x5c
-#define GC_TIMELS_TIMER1_ISR_DEFAULT             0x0
-#define GC_TIMELS_TIMER1_IPR_OFFSET              0x60
-#define GC_TIMELS_TIMER1_IPR_DEFAULT             0x0
-#define GC_TIMELS_TIMER1_IAR_OFFSET              0x64
-#define GC_TIMELS_TIMER1_IAR_DEFAULT             0x0
-#define GC_TIMELS_TIMER1_WAKEUP_ACK_OFFSET       0x68
-#define GC_TIMELS_TIMER1_WAKEUP_ACK_DEFAULT      0x0
-#define GC_TIMELS_ITCR_OFFSET                    0xf00
-#define GC_TIMELS_ITCR_DEFAULT                   0x0
-#define GC_TIMELS_ITOP_OFFSET                    0xf04
-#define GC_TIMELS_ITOP_DEFAULT                   0x0
-#define GC_TIMEUS_VERSION_OFFSET                 0x0
-#define GC_TIMEUS_VERSION_DEFAULT                0x101424a
-#define GC_TIMEUS_INT_ENABLE_OFFSET              0x4
-#define GC_TIMEUS_INT_ENABLE_DEFAULT             0x0
-#define GC_TIMEUS_INT_STATE_OFFSET               0x8
-#define GC_TIMEUS_INT_STATE_DEFAULT              0x0
-#define GC_TIMEUS_INT_TEST_OFFSET                0xc
-#define GC_TIMEUS_INT_TEST_DEFAULT               0x0
-#define GC_TIMEUS_ENABLE_CNTR0_OFFSET            0x100
-#define GC_TIMEUS_ENABLE_CNTR0_DEFAULT           0x0
-#define GC_TIMEUS_ONESHOT_MODE_CNTR0_OFFSET      0x104
-#define GC_TIMEUS_ONESHOT_MODE_CNTR0_DEFAULT     0x0
-#define GC_TIMEUS_MAXVAL_CNTR0_OFFSET            0x108
-#define GC_TIMEUS_MAXVAL_CNTR0_DEFAULT           0x2710
-#define GC_TIMEUS_PROGVAL_CNTR0_OFFSET           0x10c
-#define GC_TIMEUS_PROGVAL_CNTR0_DEFAULT          0x3e8
-#define GC_TIMEUS_DIVIDER_CNTR0_OFFSET           0x110
-#define GC_TIMEUS_DIVIDER_CNTR0_DEFAULT          0x1
-#define GC_TIMEUS_CUR_MAJOR_CNTR0_OFFSET         0x114
-#define GC_TIMEUS_CUR_MAJOR_CNTR0_DEFAULT        0x0
-#define GC_TIMEUS_CUR_MINOR_CNTR0_OFFSET         0x118
-#define GC_TIMEUS_CUR_MINOR_CNTR0_DEFAULT        0x0
-#define GC_TIMEUS_ENABLE_CNTR1_OFFSET            0x200
-#define GC_TIMEUS_ENABLE_CNTR1_DEFAULT           0x0
-#define GC_TIMEUS_ONESHOT_MODE_CNTR1_OFFSET      0x204
-#define GC_TIMEUS_ONESHOT_MODE_CNTR1_DEFAULT     0x0
-#define GC_TIMEUS_MAXVAL_CNTR1_OFFSET            0x208
-#define GC_TIMEUS_MAXVAL_CNTR1_DEFAULT           0x2710
-#define GC_TIMEUS_PROGVAL_CNTR1_OFFSET           0x20c
-#define GC_TIMEUS_PROGVAL_CNTR1_DEFAULT          0x3e8
-#define GC_TIMEUS_DIVIDER_CNTR1_OFFSET           0x210
-#define GC_TIMEUS_DIVIDER_CNTR1_DEFAULT          0x1
-#define GC_TIMEUS_CUR_MAJOR_CNTR1_OFFSET         0x214
-#define GC_TIMEUS_CUR_MAJOR_CNTR1_DEFAULT        0x0
-#define GC_TIMEUS_CUR_MINOR_CNTR1_OFFSET         0x218
-#define GC_TIMEUS_CUR_MINOR_CNTR1_DEFAULT        0x0
-#define GC_TIMEUS_ENABLE_CNTR2_OFFSET            0x300
-#define GC_TIMEUS_ENABLE_CNTR2_DEFAULT           0x0
-#define GC_TIMEUS_ONESHOT_MODE_CNTR2_OFFSET      0x304
-#define GC_TIMEUS_ONESHOT_MODE_CNTR2_DEFAULT     0x0
-#define GC_TIMEUS_MAXVAL_CNTR2_OFFSET            0x308
-#define GC_TIMEUS_MAXVAL_CNTR2_DEFAULT           0x2710
-#define GC_TIMEUS_PROGVAL_CNTR2_OFFSET           0x30c
-#define GC_TIMEUS_PROGVAL_CNTR2_DEFAULT          0x3e8
-#define GC_TIMEUS_DIVIDER_CNTR2_OFFSET           0x310
-#define GC_TIMEUS_DIVIDER_CNTR2_DEFAULT          0x1
-#define GC_TIMEUS_CUR_MAJOR_CNTR2_OFFSET         0x314
-#define GC_TIMEUS_CUR_MAJOR_CNTR2_DEFAULT        0x0
-#define GC_TIMEUS_CUR_MINOR_CNTR2_OFFSET         0x318
-#define GC_TIMEUS_CUR_MINOR_CNTR2_DEFAULT        0x0
-#define GC_TIMEUS_ENABLE_CNTR3_OFFSET            0x400
-#define GC_TIMEUS_ENABLE_CNTR3_DEFAULT           0x0
-#define GC_TIMEUS_ONESHOT_MODE_CNTR3_OFFSET      0x404
-#define GC_TIMEUS_ONESHOT_MODE_CNTR3_DEFAULT     0x0
-#define GC_TIMEUS_MAXVAL_CNTR3_OFFSET            0x408
-#define GC_TIMEUS_MAXVAL_CNTR3_DEFAULT           0x2710
-#define GC_TIMEUS_PROGVAL_CNTR3_OFFSET           0x40c
-#define GC_TIMEUS_PROGVAL_CNTR3_DEFAULT          0x3e8
-#define GC_TIMEUS_DIVIDER_CNTR3_OFFSET           0x410
-#define GC_TIMEUS_DIVIDER_CNTR3_DEFAULT          0x1
-#define GC_TIMEUS_CUR_MAJOR_CNTR3_OFFSET         0x414
-#define GC_TIMEUS_CUR_MAJOR_CNTR3_DEFAULT        0x0
-#define GC_TIMEUS_CUR_MINOR_CNTR3_OFFSET         0x418
-#define GC_TIMEUS_CUR_MINOR_CNTR3_DEFAULT        0x0
-#define GC_TRNG_VERSION_OFFSET                   0x0
-#define GC_TRNG_VERSION_DEFAULT                  0x1014125
-#define GC_TRNG_INT_ENABLE_OFFSET                0x4
-#define GC_TRNG_INT_ENABLE_DEFAULT               0x0
-#define GC_TRNG_INT_STATE_OFFSET                 0x8
-#define GC_TRNG_INT_STATE_DEFAULT                0x0
-#define GC_TRNG_INT_TEST_OFFSET                  0xc
-#define GC_TRNG_INT_TEST_DEFAULT                 0x0
-#define GC_TRNG_SECURE_POST_PROCESSING_CTRL_OFFSET 0x10
-#define GC_TRNG_SECURE_POST_PROCESSING_CTRL_DEFAULT 0x1
-#define GC_TRNG_POST_PROCESSING_CTRL_OFFSET      0x14
-#define GC_TRNG_POST_PROCESSING_CTRL_DEFAULT     0xf
-#define GC_TRNG_GO_EVENT_OFFSET                  0x18
-#define GC_TRNG_GO_EVENT_DEFAULT                 0x0
-#define GC_TRNG_TIMEOUT_COUNTER_OFFSET           0x1c
-#define GC_TRNG_TIMEOUT_COUNTER_DEFAULT          0x7d0
-#define GC_TRNG_TIMEOUT_MAX_TRY_NUM_OFFSET       0x20
-#define GC_TRNG_TIMEOUT_MAX_TRY_NUM_DEFAULT      0x4
-#define GC_TRNG_OUTPUT_TIME_COUNTER_OFFSET       0x24
-#define GC_TRNG_OUTPUT_TIME_COUNTER_DEFAULT      0x10000
-#define GC_TRNG_STOP_WORK_OFFSET                 0x28
-#define GC_TRNG_STOP_WORK_DEFAULT                0x0
-#define GC_TRNG_FSM_STATE_OFFSET                 0x2c
-#define GC_TRNG_FSM_STATE_DEFAULT                0x1
-#define GC_TRNG_ALLOWED_VALUES_OFFSET            0x30
-#define GC_TRNG_ALLOWED_VALUES_DEFAULT           0x21
-#define GC_TRNG_TIMER_COUNTER_OFFSET             0x34
-#define GC_TRNG_TIMER_COUNTER_DEFAULT            0x0
-#define GC_TRNG_SLICE_MAX_UPPER_LIMIT_OFFSET     0x38
-#define GC_TRNG_SLICE_MAX_UPPER_LIMIT_DEFAULT    0xf
-#define GC_TRNG_SLICE_MIN_LOWER_LIMIT_OFFSET     0x3c
-#define GC_TRNG_SLICE_MIN_LOWER_LIMIT_DEFAULT    0x0
-#define GC_TRNG_MAX_VALUE_OFFSET                 0x40
-#define GC_TRNG_MAX_VALUE_DEFAULT                0x0
-#define GC_TRNG_MIN_VALUE_OFFSET                 0x44
-#define GC_TRNG_MIN_VALUE_DEFAULT                0x0
-#define GC_TRNG_LDO_CTRL_OFFSET                  0x48
-#define GC_TRNG_LDO_CTRL_DEFAULT                 0x5
-#define GC_TRNG_POWER_DOWN_B_OFFSET              0x4c
-#define GC_TRNG_POWER_DOWN_B_DEFAULT             0x0
-#define GC_TRNG_PROC_LOCK_POWER_DOWN_B_OFFSET    0x50
-#define GC_TRNG_PROC_LOCK_POWER_DOWN_B_DEFAULT   0x1
-#define GC_TRNG_ANTEST_OFFSET                    0x54
-#define GC_TRNG_ANTEST_DEFAULT                   0x0
-#define GC_TRNG_ANALOG_SEN_LSR_INPUT_OFFSET      0x58
-#define GC_TRNG_ANALOG_SEN_LSR_INPUT_DEFAULT     0xb
-#define GC_TRNG_ANALOG_SEN_LSR_OUTPUT_OFFSET     0x5c
-#define GC_TRNG_ANALOG_SEN_LSR_OUTPUT_DEFAULT    0x0
-#define GC_TRNG_ANALOG_TEST_OFFSET               0x60
-#define GC_TRNG_ANALOG_TEST_DEFAULT              0x0
-#define GC_TRNG_ANALOG_CTRL_OFFSET               0x64
-#define GC_TRNG_ANALOG_CTRL_DEFAULT              0x0
-#define GC_TRNG_ONE_SHOT_MODE_OFFSET             0x68
-#define GC_TRNG_ONE_SHOT_MODE_DEFAULT            0x0
-#define GC_TRNG_ONE_SHOT_REG_OFFSET              0x6c
-#define GC_TRNG_ONE_SHOT_REG_DEFAULT             0x0
-#define GC_TRNG_READ_DATA_OFFSET                 0x70
-#define GC_TRNG_READ_DATA_DEFAULT                0x0
-#define GC_TRNG_FREQUENCY_CALLS_OFFSET           0x74
-#define GC_TRNG_FREQUENCY_CALLS_DEFAULT          0x0
-#define GC_TRNG_CUR_NUM_ONES_OFFSET              0x78
-#define GC_TRNG_CUR_NUM_ONES_DEFAULT             0x0
-#define GC_TRNG_EMPTY_OFFSET                     0x7c
-#define GC_TRNG_EMPTY_DEFAULT                    0x1
-#define GC_UART_RDATA_OFFSET                     0x0
-#define GC_UART_RDATA_DEFAULT                    0x0
-#define GC_UART_WDATA_OFFSET                     0x4
-#define GC_UART_WDATA_DEFAULT                    0x0
-#define GC_UART_NCO_OFFSET                       0x8
-#define GC_UART_NCO_DEFAULT                      0x0
-#define GC_UART_CTRL_OFFSET                      0xc
-#define GC_UART_CTRL_DEFAULT                     0x0
-#define GC_UART_ICTRL_OFFSET                     0x10
-#define GC_UART_ICTRL_DEFAULT                    0x0
-#define GC_UART_STATE_OFFSET                     0x14
-#define GC_UART_STATE_DEFAULT                    0x90
-#define GC_UART_STATECLR_OFFSET                  0x18
-#define GC_UART_STATECLR_DEFAULT                 0x0
-#define GC_UART_ISTATE_OFFSET                    0x1c
-#define GC_UART_ISTATE_DEFAULT                   0x0
-#define GC_UART_ISTATECLR_OFFSET                 0x20
-#define GC_UART_ISTATECLR_DEFAULT                0x0
-#define GC_UART_FIFO_OFFSET                      0x24
-#define GC_UART_FIFO_DEFAULT                     0x0
-#define GC_UART_RFIFO_OFFSET                     0x28
-#define GC_UART_RFIFO_DEFAULT                    0x0
-#define GC_UART_OVRD_OFFSET                      0x2c
-#define GC_UART_OVRD_DEFAULT                     0x0
-#define GC_UART_VAL_OFFSET                       0x30
-#define GC_UART_VAL_DEFAULT                      0x0
-#define GC_UART_RXTO_OFFSET                      0x34
-#define GC_UART_RXTO_DEFAULT                     0x0
-#define GC_UART_ITCR_OFFSET                      0xf00
-#define GC_UART_ITCR_DEFAULT                     0x0
-#define GC_UART_ITOP_OFFSET                      0xf04
-#define GC_UART_ITOP_DEFAULT                     0x0
-#define GC_USB_GOTGCTL_OFFSET                    0x0
-#define GC_USB_GOTGCTL_DEFAULT                   0x0
-#define GC_USB_GOTGINT_OFFSET                    0x4
-#define GC_USB_GOTGINT_DEFAULT                   0x0
-#define GC_USB_GAHBCFG_OFFSET                    0x8
-#define GC_USB_GAHBCFG_DEFAULT                   0x0
-#define GC_USB_GUSBCFG_OFFSET                    0xc
-#define GC_USB_GUSBCFG_DEFAULT                   0x0
-#define GC_USB_GRSTCTL_OFFSET                    0x10
-#define GC_USB_GRSTCTL_DEFAULT                   0x0
-#define GC_USB_GINTSTS_OFFSET                    0x14
-#define GC_USB_GINTSTS_DEFAULT                   0x0
-#define GC_USB_GINTMSK_OFFSET                    0x18
-#define GC_USB_GINTMSK_DEFAULT                   0x0
-#define GC_USB_GRXSTSR_OFFSET                    0x1c
-#define GC_USB_GRXSTSR_DEFAULT                   0x0
-#define GC_USB_GRXSTSP_OFFSET                    0x20
-#define GC_USB_GRXSTSP_DEFAULT                   0x0
-#define GC_USB_GRXFSIZ_OFFSET                    0x24
-#define GC_USB_GRXFSIZ_DEFAULT                   0x0
-#define GC_USB_GNPTXFSIZ_OFFSET                  0x28
-#define GC_USB_GNPTXFSIZ_DEFAULT                 0x0
-#define GC_USB_GGPIO_OFFSET                      0x38
-#define GC_USB_GGPIO_DEFAULT                     0x0
-#define GC_USB_GUID_OFFSET                       0x3c
-#define GC_USB_GUID_DEFAULT                      0x0
-#define GC_USB_GSNPSID_OFFSET                    0x40
-#define GC_USB_GSNPSID_DEFAULT                   0x0
-#define GC_USB_GHWCFG1_OFFSET                    0x44
-#define GC_USB_GHWCFG1_DEFAULT                   0x0
-#define GC_USB_GHWCFG2_OFFSET                    0x48
-#define GC_USB_GHWCFG2_DEFAULT                   0x0
-#define GC_USB_GHWCFG3_OFFSET                    0x4c
-#define GC_USB_GHWCFG3_DEFAULT                   0x0
-#define GC_USB_GHWCFG4_OFFSET                    0x50
-#define GC_USB_GHWCFG4_DEFAULT                   0x0
-#define GC_USB_GDFIFOCFG_OFFSET                  0x5c
-#define GC_USB_GDFIFOCFG_DEFAULT                 0x0
-#define GC_USB_DIEPTXF1_OFFSET                   0x104
-#define GC_USB_DIEPTXF1_DEFAULT                  0x1000
-#define GC_USB_DIEPTXF2_OFFSET                   0x108
-#define GC_USB_DIEPTXF2_DEFAULT                  0x0
-#define GC_USB_DIEPTXF3_OFFSET                   0x10c
-#define GC_USB_DIEPTXF3_DEFAULT                  0x0
-#define GC_USB_DIEPTXF4_OFFSET                   0x110
-#define GC_USB_DIEPTXF4_DEFAULT                  0x0
-#define GC_USB_DIEPTXF5_OFFSET                   0x114
-#define GC_USB_DIEPTXF5_DEFAULT                  0x0
-#define GC_USB_DIEPTXF6_OFFSET                   0x118
-#define GC_USB_DIEPTXF6_DEFAULT                  0x0
-#define GC_USB_DIEPTXF7_OFFSET                   0x11c
-#define GC_USB_DIEPTXF7_DEFAULT                  0x0
-#define GC_USB_DIEPTXF8_OFFSET                   0x120
-#define GC_USB_DIEPTXF8_DEFAULT                  0x0
-#define GC_USB_DIEPTXF9_OFFSET                   0x124
-#define GC_USB_DIEPTXF9_DEFAULT                  0x0
-#define GC_USB_DIEPTXF10_OFFSET                  0x128
-#define GC_USB_DIEPTXF10_DEFAULT                 0x0
-#define GC_USB_DIEPTXF11_OFFSET                  0x12c
-#define GC_USB_DIEPTXF11_DEFAULT                 0x0
-#define GC_USB_DIEPTXF12_OFFSET                  0x130
-#define GC_USB_DIEPTXF12_DEFAULT                 0x0
-#define GC_USB_DIEPTXF13_OFFSET                  0x134
-#define GC_USB_DIEPTXF13_DEFAULT                 0x0
-#define GC_USB_DIEPTXF14_OFFSET                  0x138
-#define GC_USB_DIEPTXF14_DEFAULT                 0x0
-#define GC_USB_DIEPTXF15_OFFSET                  0x13c
-#define GC_USB_DIEPTXF15_DEFAULT                 0x0
-#define GC_USB_DCFG_OFFSET                       0x800
-#define GC_USB_DCFG_DEFAULT                      0x8000000
-#define GC_USB_DCTL_OFFSET                       0x804
-#define GC_USB_DCTL_DEFAULT                      0x0
-#define GC_USB_DSTS_OFFSET                       0x808
-#define GC_USB_DSTS_DEFAULT                      0x0
-#define GC_USB_DIEPMSK_OFFSET                    0x810
-#define GC_USB_DIEPMSK_DEFAULT                   0x80
-#define GC_USB_DOEPMSK_OFFSET                    0x814
-#define GC_USB_DOEPMSK_DEFAULT                   0x0
-#define GC_USB_DAINT_OFFSET                      0x818
-#define GC_USB_DAINT_DEFAULT                     0x0
-#define GC_USB_DAINTMSK_OFFSET                   0x81c
-#define GC_USB_DAINTMSK_DEFAULT                  0x0
-#define GC_USB_DVBUSDIS_OFFSET                   0x828
-#define GC_USB_DVBUSDIS_DEFAULT                  0x0
-#define GC_USB_DVBUSPULSE_OFFSET                 0x82c
-#define GC_USB_DVBUSPULSE_DEFAULT                0x0
-#define GC_USB_DTHRCTL_OFFSET                    0x830
-#define GC_USB_DTHRCTL_DEFAULT                   0x0
-#define GC_USB_DIEPEMPMSK_OFFSET                 0x834
-#define GC_USB_DIEPEMPMSK_DEFAULT                0x0
-#define GC_USB_DIEPCTL0_OFFSET                   0x900
-#define GC_USB_DIEPCTL0_DEFAULT                  0x0
-#define GC_USB_DIEPINT0_OFFSET                   0x908
-#define GC_USB_DIEPINT0_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ0_OFFSET                  0x910
-#define GC_USB_DIEPTSIZ0_DEFAULT                 0x0
-#define GC_USB_DIEPDMA0_OFFSET                   0x914
-#define GC_USB_DIEPDMA0_DEFAULT                  0x0
-#define GC_USB_DTXFSTS0_OFFSET                   0x918
-#define GC_USB_DTXFSTS0_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB0_OFFSET                  0x91c
-#define GC_USB_DIEPDMAB0_DEFAULT                 0x0
-#define GC_USB_DIEPCTL1_OFFSET                   0x920
-#define GC_USB_DIEPCTL1_DEFAULT                  0x0
-#define GC_USB_DIEPINT1_OFFSET                   0x928
-#define GC_USB_DIEPINT1_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ1_OFFSET                  0x930
-#define GC_USB_DIEPTSIZ1_DEFAULT                 0x0
-#define GC_USB_DIEPDMA1_OFFSET                   0x934
-#define GC_USB_DIEPDMA1_DEFAULT                  0x0
-#define GC_USB_DTXFSTS1_OFFSET                   0x938
-#define GC_USB_DTXFSTS1_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB1_OFFSET                  0x93c
-#define GC_USB_DIEPDMAB1_DEFAULT                 0x0
-#define GC_USB_DIEPCTL2_OFFSET                   0x940
-#define GC_USB_DIEPCTL2_DEFAULT                  0x0
-#define GC_USB_DIEPINT2_OFFSET                   0x948
-#define GC_USB_DIEPINT2_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ2_OFFSET                  0x950
-#define GC_USB_DIEPTSIZ2_DEFAULT                 0x0
-#define GC_USB_DIEPDMA2_OFFSET                   0x954
-#define GC_USB_DIEPDMA2_DEFAULT                  0x0
-#define GC_USB_DTXFSTS2_OFFSET                   0x958
-#define GC_USB_DTXFSTS2_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB2_OFFSET                  0x95c
-#define GC_USB_DIEPDMAB2_DEFAULT                 0x0
-#define GC_USB_DIEPCTL3_OFFSET                   0x960
-#define GC_USB_DIEPCTL3_DEFAULT                  0x0
-#define GC_USB_DIEPINT3_OFFSET                   0x968
-#define GC_USB_DIEPINT3_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ3_OFFSET                  0x970
-#define GC_USB_DIEPTSIZ3_DEFAULT                 0x0
-#define GC_USB_DIEPDMA3_OFFSET                   0x974
-#define GC_USB_DIEPDMA3_DEFAULT                  0x0
-#define GC_USB_DTXFSTS3_OFFSET                   0x978
-#define GC_USB_DTXFSTS3_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB3_OFFSET                  0x97c
-#define GC_USB_DIEPDMAB3_DEFAULT                 0x0
-#define GC_USB_DIEPCTL4_OFFSET                   0x980
-#define GC_USB_DIEPCTL4_DEFAULT                  0x0
-#define GC_USB_DIEPINT4_OFFSET                   0x988
-#define GC_USB_DIEPINT4_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ4_OFFSET                  0x990
-#define GC_USB_DIEPTSIZ4_DEFAULT                 0x0
-#define GC_USB_DIEPDMA4_OFFSET                   0x994
-#define GC_USB_DIEPDMA4_DEFAULT                  0x0
-#define GC_USB_DTXFSTS4_OFFSET                   0x998
-#define GC_USB_DTXFSTS4_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB4_OFFSET                  0x99c
-#define GC_USB_DIEPDMAB4_DEFAULT                 0x0
-#define GC_USB_DIEPCTL5_OFFSET                   0x9a0
-#define GC_USB_DIEPCTL5_DEFAULT                  0x0
-#define GC_USB_DIEPINT5_OFFSET                   0x9a8
-#define GC_USB_DIEPINT5_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ5_OFFSET                  0x9b0
-#define GC_USB_DIEPTSIZ5_DEFAULT                 0x0
-#define GC_USB_DIEPDMA5_OFFSET                   0x9b4
-#define GC_USB_DIEPDMA5_DEFAULT                  0x0
-#define GC_USB_DTXFSTS5_OFFSET                   0x9b8
-#define GC_USB_DTXFSTS5_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB5_OFFSET                  0x9bc
-#define GC_USB_DIEPDMAB5_DEFAULT                 0x0
-#define GC_USB_DIEPCTL6_OFFSET                   0x9c0
-#define GC_USB_DIEPCTL6_DEFAULT                  0x0
-#define GC_USB_DIEPINT6_OFFSET                   0x9c8
-#define GC_USB_DIEPINT6_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ6_OFFSET                  0x9d0
-#define GC_USB_DIEPTSIZ6_DEFAULT                 0x0
-#define GC_USB_DIEPDMA6_OFFSET                   0x9d4
-#define GC_USB_DIEPDMA6_DEFAULT                  0x0
-#define GC_USB_DTXFSTS6_OFFSET                   0x9d8
-#define GC_USB_DTXFSTS6_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB6_OFFSET                  0x9dc
-#define GC_USB_DIEPDMAB6_DEFAULT                 0x0
-#define GC_USB_DIEPCTL7_OFFSET                   0x9e0
-#define GC_USB_DIEPCTL7_DEFAULT                  0x0
-#define GC_USB_DIEPINT7_OFFSET                   0x9e8
-#define GC_USB_DIEPINT7_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ7_OFFSET                  0x9f0
-#define GC_USB_DIEPTSIZ7_DEFAULT                 0x0
-#define GC_USB_DIEPDMA7_OFFSET                   0x9f4
-#define GC_USB_DIEPDMA7_DEFAULT                  0x0
-#define GC_USB_DTXFSTS7_OFFSET                   0x9f8
-#define GC_USB_DTXFSTS7_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB7_OFFSET                  0x9fc
-#define GC_USB_DIEPDMAB7_DEFAULT                 0x0
-#define GC_USB_DIEPCTL8_OFFSET                   0xa00
-#define GC_USB_DIEPCTL8_DEFAULT                  0x0
-#define GC_USB_DIEPINT8_OFFSET                   0xa08
-#define GC_USB_DIEPINT8_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ8_OFFSET                  0xa10
-#define GC_USB_DIEPTSIZ8_DEFAULT                 0x0
-#define GC_USB_DIEPDMA8_OFFSET                   0xa14
-#define GC_USB_DIEPDMA8_DEFAULT                  0x0
-#define GC_USB_DTXFSTS8_OFFSET                   0xa18
-#define GC_USB_DTXFSTS8_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB8_OFFSET                  0xa1c
-#define GC_USB_DIEPDMAB8_DEFAULT                 0x0
-#define GC_USB_DIEPCTL9_OFFSET                   0xa20
-#define GC_USB_DIEPCTL9_DEFAULT                  0x0
-#define GC_USB_DIEPINT9_OFFSET                   0xa28
-#define GC_USB_DIEPINT9_DEFAULT                  0x0
-#define GC_USB_DIEPTSIZ9_OFFSET                  0xa30
-#define GC_USB_DIEPTSIZ9_DEFAULT                 0x0
-#define GC_USB_DIEPDMA9_OFFSET                   0xa34
-#define GC_USB_DIEPDMA9_DEFAULT                  0x0
-#define GC_USB_DTXFSTS9_OFFSET                   0xa38
-#define GC_USB_DTXFSTS9_DEFAULT                  0x0
-#define GC_USB_DIEPDMAB9_OFFSET                  0xa3c
-#define GC_USB_DIEPDMAB9_DEFAULT                 0x0
-#define GC_USB_DIEPCTL10_OFFSET                  0xa40
-#define GC_USB_DIEPCTL10_DEFAULT                 0x0
-#define GC_USB_DIEPINT10_OFFSET                  0xa48
-#define GC_USB_DIEPINT10_DEFAULT                 0x0
-#define GC_USB_DIEPTSIZ10_OFFSET                 0xa50
-#define GC_USB_DIEPTSIZ10_DEFAULT                0x0
-#define GC_USB_DIEPDMA10_OFFSET                  0xa54
-#define GC_USB_DIEPDMA10_DEFAULT                 0x0
-#define GC_USB_DTXFSTS10_OFFSET                  0xa58
-#define GC_USB_DTXFSTS10_DEFAULT                 0x0
-#define GC_USB_DIEPDMAB10_OFFSET                 0xa5c
-#define GC_USB_DIEPDMAB10_DEFAULT                0x0
-#define GC_USB_DIEPCTL11_OFFSET                  0xa60
-#define GC_USB_DIEPCTL11_DEFAULT                 0x0
-#define GC_USB_DIEPINT11_OFFSET                  0xa68
-#define GC_USB_DIEPINT11_DEFAULT                 0x0
-#define GC_USB_DIEPTSIZ11_OFFSET                 0xa70
-#define GC_USB_DIEPTSIZ11_DEFAULT                0x0
-#define GC_USB_DIEPDMA11_OFFSET                  0xa74
-#define GC_USB_DIEPDMA11_DEFAULT                 0x0
-#define GC_USB_DTXFSTS11_OFFSET                  0xa78
-#define GC_USB_DTXFSTS11_DEFAULT                 0x0
-#define GC_USB_DIEPDMAB11_OFFSET                 0xa7c
-#define GC_USB_DIEPDMAB11_DEFAULT                0x0
-#define GC_USB_DIEPCTL12_OFFSET                  0xa80
-#define GC_USB_DIEPCTL12_DEFAULT                 0x0
-#define GC_USB_DIEPINT12_OFFSET                  0xa88
-#define GC_USB_DIEPINT12_DEFAULT                 0x0
-#define GC_USB_DIEPTSIZ12_OFFSET                 0xa90
-#define GC_USB_DIEPTSIZ12_DEFAULT                0x0
-#define GC_USB_DIEPDMA12_OFFSET                  0xa94
-#define GC_USB_DIEPDMA12_DEFAULT                 0x0
-#define GC_USB_DTXFSTS12_OFFSET                  0xa98
-#define GC_USB_DTXFSTS12_DEFAULT                 0x0
-#define GC_USB_DIEPDMAB12_OFFSET                 0xa9c
-#define GC_USB_DIEPDMAB12_DEFAULT                0x0
-#define GC_USB_DIEPCTL13_OFFSET                  0xaa0
-#define GC_USB_DIEPCTL13_DEFAULT                 0x0
-#define GC_USB_DIEPINT13_OFFSET                  0xaa8
-#define GC_USB_DIEPINT13_DEFAULT                 0x0
-#define GC_USB_DIEPTSIZ13_OFFSET                 0xab0
-#define GC_USB_DIEPTSIZ13_DEFAULT                0x0
-#define GC_USB_DIEPDMA13_OFFSET                  0xab4
-#define GC_USB_DIEPDMA13_DEFAULT                 0x0
-#define GC_USB_DTXFSTS13_OFFSET                  0xab8
-#define GC_USB_DTXFSTS13_DEFAULT                 0x0
-#define GC_USB_DIEPDMAB13_OFFSET                 0xabc
-#define GC_USB_DIEPDMAB13_DEFAULT                0x0
-#define GC_USB_DIEPCTL14_OFFSET                  0xac0
-#define GC_USB_DIEPCTL14_DEFAULT                 0x0
-#define GC_USB_DIEPINT14_OFFSET                  0xac8
-#define GC_USB_DIEPINT14_DEFAULT                 0x0
-#define GC_USB_DIEPTSIZ14_OFFSET                 0xad0
-#define GC_USB_DIEPTSIZ14_DEFAULT                0x0
-#define GC_USB_DIEPDMA14_OFFSET                  0xad4
-#define GC_USB_DIEPDMA14_DEFAULT                 0x0
-#define GC_USB_DTXFSTS14_OFFSET                  0xad8
-#define GC_USB_DTXFSTS14_DEFAULT                 0x0
-#define GC_USB_DIEPDMAB14_OFFSET                 0xadc
-#define GC_USB_DIEPDMAB14_DEFAULT                0x0
-#define GC_USB_DIEPCTL15_OFFSET                  0xae0
-#define GC_USB_DIEPCTL15_DEFAULT                 0x0
-#define GC_USB_DIEPINT15_OFFSET                  0xae8
-#define GC_USB_DIEPINT15_DEFAULT                 0x0
-#define GC_USB_DIEPTSIZ15_OFFSET                 0xaf0
-#define GC_USB_DIEPTSIZ15_DEFAULT                0x0
-#define GC_USB_DIEPDMA15_OFFSET                  0xaf4
-#define GC_USB_DIEPDMA15_DEFAULT                 0x0
-#define GC_USB_DTXFSTS15_OFFSET                  0xaf8
-#define GC_USB_DTXFSTS15_DEFAULT                 0x0
-#define GC_USB_DIEPDMAB15_OFFSET                 0xafc
-#define GC_USB_DIEPDMAB15_DEFAULT                0x0
-#define GC_USB_DOEPCTL0_OFFSET                   0xb00
-#define GC_USB_DOEPCTL0_DEFAULT                  0x0
-#define GC_USB_DOEPINT0_OFFSET                   0xb08
-#define GC_USB_DOEPINT0_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ0_OFFSET                  0xb10
-#define GC_USB_DOEPTSIZ0_DEFAULT                 0x0
-#define GC_USB_DOEPDMA0_OFFSET                   0xb14
-#define GC_USB_DOEPDMA0_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB0_OFFSET                  0xb1c
-#define GC_USB_DOEPDMAB0_DEFAULT                 0x0
-#define GC_USB_DOEPCTL1_OFFSET                   0xb20
-#define GC_USB_DOEPCTL1_DEFAULT                  0x0
-#define GC_USB_DOEPINT1_OFFSET                   0xb28
-#define GC_USB_DOEPINT1_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ1_OFFSET                  0xb30
-#define GC_USB_DOEPTSIZ1_DEFAULT                 0x0
-#define GC_USB_DOEPDMA1_OFFSET                   0xb34
-#define GC_USB_DOEPDMA1_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB1_OFFSET                  0xb3c
-#define GC_USB_DOEPDMAB1_DEFAULT                 0x0
-#define GC_USB_DOEPCTL2_OFFSET                   0xb40
-#define GC_USB_DOEPCTL2_DEFAULT                  0x0
-#define GC_USB_DOEPINT2_OFFSET                   0xb48
-#define GC_USB_DOEPINT2_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ2_OFFSET                  0xb50
-#define GC_USB_DOEPTSIZ2_DEFAULT                 0x0
-#define GC_USB_DOEPDMA2_OFFSET                   0xb54
-#define GC_USB_DOEPDMA2_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB2_OFFSET                  0xb5c
-#define GC_USB_DOEPDMAB2_DEFAULT                 0x0
-#define GC_USB_DOEPCTL3_OFFSET                   0xb60
-#define GC_USB_DOEPCTL3_DEFAULT                  0x0
-#define GC_USB_DOEPINT3_OFFSET                   0xb68
-#define GC_USB_DOEPINT3_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ3_OFFSET                  0xb70
-#define GC_USB_DOEPTSIZ3_DEFAULT                 0x0
-#define GC_USB_DOEPDMA3_OFFSET                   0xb74
-#define GC_USB_DOEPDMA3_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB3_OFFSET                  0xb7c
-#define GC_USB_DOEPDMAB3_DEFAULT                 0x0
-#define GC_USB_DOEPCTL4_OFFSET                   0xb80
-#define GC_USB_DOEPCTL4_DEFAULT                  0x0
-#define GC_USB_DOEPINT4_OFFSET                   0xb88
-#define GC_USB_DOEPINT4_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ4_OFFSET                  0xb90
-#define GC_USB_DOEPTSIZ4_DEFAULT                 0x0
-#define GC_USB_DOEPDMA4_OFFSET                   0xb94
-#define GC_USB_DOEPDMA4_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB4_OFFSET                  0xb9c
-#define GC_USB_DOEPDMAB4_DEFAULT                 0x0
-#define GC_USB_DOEPCTL5_OFFSET                   0xba0
-#define GC_USB_DOEPCTL5_DEFAULT                  0x0
-#define GC_USB_DOEPINT5_OFFSET                   0xba8
-#define GC_USB_DOEPINT5_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ5_OFFSET                  0xbb0
-#define GC_USB_DOEPTSIZ5_DEFAULT                 0x0
-#define GC_USB_DOEPDMA5_OFFSET                   0xbb4
-#define GC_USB_DOEPDMA5_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB5_OFFSET                  0xbbc
-#define GC_USB_DOEPDMAB5_DEFAULT                 0x0
-#define GC_USB_DOEPCTL6_OFFSET                   0xbc0
-#define GC_USB_DOEPCTL6_DEFAULT                  0x0
-#define GC_USB_DOEPINT6_OFFSET                   0xbc8
-#define GC_USB_DOEPINT6_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ6_OFFSET                  0xbd0
-#define GC_USB_DOEPTSIZ6_DEFAULT                 0x0
-#define GC_USB_DOEPDMA6_OFFSET                   0xbd4
-#define GC_USB_DOEPDMA6_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB6_OFFSET                  0xbdc
-#define GC_USB_DOEPDMAB6_DEFAULT                 0x0
-#define GC_USB_DOEPCTL7_OFFSET                   0xbe0
-#define GC_USB_DOEPCTL7_DEFAULT                  0x0
-#define GC_USB_DOEPINT7_OFFSET                   0xbe8
-#define GC_USB_DOEPINT7_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ7_OFFSET                  0xbf0
-#define GC_USB_DOEPTSIZ7_DEFAULT                 0x0
-#define GC_USB_DOEPDMA7_OFFSET                   0xbf4
-#define GC_USB_DOEPDMA7_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB7_OFFSET                  0xbfc
-#define GC_USB_DOEPDMAB7_DEFAULT                 0x0
-#define GC_USB_DOEPCTL8_OFFSET                   0xc00
-#define GC_USB_DOEPCTL8_DEFAULT                  0x0
-#define GC_USB_DOEPINT8_OFFSET                   0xc08
-#define GC_USB_DOEPINT8_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ8_OFFSET                  0xc10
-#define GC_USB_DOEPTSIZ8_DEFAULT                 0x0
-#define GC_USB_DOEPDMA8_OFFSET                   0xc14
-#define GC_USB_DOEPDMA8_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB8_OFFSET                  0xc1c
-#define GC_USB_DOEPDMAB8_DEFAULT                 0x0
-#define GC_USB_DOEPCTL9_OFFSET                   0xc20
-#define GC_USB_DOEPCTL9_DEFAULT                  0x0
-#define GC_USB_DOEPINT9_OFFSET                   0xc28
-#define GC_USB_DOEPINT9_DEFAULT                  0x0
-#define GC_USB_DOEPTSIZ9_OFFSET                  0xc30
-#define GC_USB_DOEPTSIZ9_DEFAULT                 0x0
-#define GC_USB_DOEPDMA9_OFFSET                   0xc34
-#define GC_USB_DOEPDMA9_DEFAULT                  0x0
-#define GC_USB_DOEPDMAB9_OFFSET                  0xc3c
-#define GC_USB_DOEPDMAB9_DEFAULT                 0x0
-#define GC_USB_DOEPCTL10_OFFSET                  0xc40
-#define GC_USB_DOEPCTL10_DEFAULT                 0x0
-#define GC_USB_DOEPINT10_OFFSET                  0xc48
-#define GC_USB_DOEPINT10_DEFAULT                 0x0
-#define GC_USB_DOEPTSIZ10_OFFSET                 0xc50
-#define GC_USB_DOEPTSIZ10_DEFAULT                0x0
-#define GC_USB_DOEPDMA10_OFFSET                  0xc54
-#define GC_USB_DOEPDMA10_DEFAULT                 0x0
-#define GC_USB_DOEPDMAB10_OFFSET                 0xc5c
-#define GC_USB_DOEPDMAB10_DEFAULT                0x0
-#define GC_USB_DOEPCTL11_OFFSET                  0xc60
-#define GC_USB_DOEPCTL11_DEFAULT                 0x0
-#define GC_USB_DOEPINT11_OFFSET                  0xc68
-#define GC_USB_DOEPINT11_DEFAULT                 0x0
-#define GC_USB_DOEPTSIZ11_OFFSET                 0xc70
-#define GC_USB_DOEPTSIZ11_DEFAULT                0x0
-#define GC_USB_DOEPDMA11_OFFSET                  0xc74
-#define GC_USB_DOEPDMA11_DEFAULT                 0x0
-#define GC_USB_DOEPDMAB11_OFFSET                 0xc7c
-#define GC_USB_DOEPDMAB11_DEFAULT                0x0
-#define GC_USB_DOEPCTL12_OFFSET                  0xc80
-#define GC_USB_DOEPCTL12_DEFAULT                 0x0
-#define GC_USB_DOEPINT12_OFFSET                  0xc88
-#define GC_USB_DOEPINT12_DEFAULT                 0x0
-#define GC_USB_DOEPTSIZ12_OFFSET                 0xc90
-#define GC_USB_DOEPTSIZ12_DEFAULT                0x0
-#define GC_USB_DOEPDMA12_OFFSET                  0xc94
-#define GC_USB_DOEPDMA12_DEFAULT                 0x0
-#define GC_USB_DOEPDMAB12_OFFSET                 0xc9c
-#define GC_USB_DOEPDMAB12_DEFAULT                0x0
-#define GC_USB_DOEPCTL13_OFFSET                  0xca0
-#define GC_USB_DOEPCTL13_DEFAULT                 0x0
-#define GC_USB_DOEPINT13_OFFSET                  0xca8
-#define GC_USB_DOEPINT13_DEFAULT                 0x0
-#define GC_USB_DOEPTSIZ13_OFFSET                 0xcb0
-#define GC_USB_DOEPTSIZ13_DEFAULT                0x0
-#define GC_USB_DOEPDMA13_OFFSET                  0xcb4
-#define GC_USB_DOEPDMA13_DEFAULT                 0x0
-#define GC_USB_DOEPDMAB13_OFFSET                 0xcbc
-#define GC_USB_DOEPDMAB13_DEFAULT                0x0
-#define GC_USB_DOEPCTL14_OFFSET                  0xcc0
-#define GC_USB_DOEPCTL14_DEFAULT                 0x0
-#define GC_USB_DOEPINT14_OFFSET                  0xcc8
-#define GC_USB_DOEPINT14_DEFAULT                 0x0
-#define GC_USB_DOEPTSIZ14_OFFSET                 0xcd0
-#define GC_USB_DOEPTSIZ14_DEFAULT                0x0
-#define GC_USB_DOEPDMA14_OFFSET                  0xcd4
-#define GC_USB_DOEPDMA14_DEFAULT                 0x0
-#define GC_USB_DOEPDMAB14_OFFSET                 0xcdc
-#define GC_USB_DOEPDMAB14_DEFAULT                0x0
-#define GC_USB_DOEPCTL15_OFFSET                  0xce0
-#define GC_USB_DOEPCTL15_DEFAULT                 0x0
-#define GC_USB_DOEPINT15_OFFSET                  0xce8
-#define GC_USB_DOEPINT15_DEFAULT                 0x0
-#define GC_USB_DOEPTSIZ15_OFFSET                 0xcf0
-#define GC_USB_DOEPTSIZ15_DEFAULT                0x0
-#define GC_USB_DOEPDMA15_OFFSET                  0xcf4
-#define GC_USB_DOEPDMA15_DEFAULT                 0x0
-#define GC_USB_DOEPDMAB15_OFFSET                 0xcfc
-#define GC_USB_DOEPDMAB15_DEFAULT                0x0
-#define GC_USB_PCGCCTL_OFFSET                    0xe00
-#define GC_USB_PCGCCTL_DEFAULT                   0x0
-#define GC_USB_DFIFO_OFFSET                      0x20000
-#define GC_VOLT_VERSION_OFFSET                   0x0
-#define GC_VOLT_VERSION_DEFAULT                  0x1014125
-#define GC_VOLT_ANALOG_POWER_DOWN_B_OFFSET       0x4
-#define GC_VOLT_ANALOG_POWER_DOWN_B_DEFAULT      0x0
-#define GC_VOLT_ANALOG_CONTROL_OFFSET            0x8
-#define GC_VOLT_ANALOG_CONTROL_DEFAULT           0xb916
-#define GC_VOLT_CONFIG_OFFSET                    0xc
-#define GC_VOLT_CONFIG_DEFAULT                   0x0
-#define GC_VOLT_GLITCH_DET_CTR_STATE_OFFSET      0x10
-#define GC_VOLT_GLITCH_DET_CTR_STATE_DEFAULT     0x0
-#define GC_VOLT_ILLEGAL_VALS_CTR_STATE_OFFSET    0x14
-#define GC_VOLT_ILLEGAL_VALS_CTR_STATE_DEFAULT   0x0
-#define GC_WATCHDOG_WDOGLOAD_OFFSET              0x0
-#define GC_WATCHDOG_WDOGLOAD_DEFAULT             0xffffffff
-#define GC_WATCHDOG_WDOGVALUE_OFFSET             0x4
-#define GC_WATCHDOG_WDOGVALUE_DEFAULT            0xffffffff
-#define GC_WATCHDOG_WDOGCONTROL_OFFSET           0x8
-#define GC_WATCHDOG_WDOGCONTROL_DEFAULT          0x0
-#define GC_WATCHDOG_WDOGINTCLR_OFFSET            0xc
-#define GC_WATCHDOG_WDOGINTCLR_DEFAULT           0x0
-#define GC_WATCHDOG_WDOGRIS_OFFSET               0x10
-#define GC_WATCHDOG_WDOGRIS_DEFAULT              0x0
-#define GC_WATCHDOG_WDOGMIS_OFFSET               0x14
-#define GC_WATCHDOG_WDOGMIS_DEFAULT              0x0
-#define GC_WATCHDOG_WDOGLOCK_OFFSET              0xc00
-#define GC_WATCHDOG_WDOGLOCK_DEFAULT             0x0
-#define GC_WATCHDOG_WDOGITCR_OFFSET              0xf00
-#define GC_WATCHDOG_WDOGITCR_DEFAULT             0x0
-#define GC_WATCHDOG_WDOGITOP_OFFSET              0xf04
-#define GC_WATCHDOG_WDOGITOP_DEFAULT             0x0
-#define GC_WATCHDOG_WDOGPERIPHID4_OFFSET         0xfd0
-#define GC_WATCHDOG_WDOGPERIPHID4_DEFAULT        0x4
-#define GC_WATCHDOG_WDOGPERIPHID5_OFFSET         0xfd4
-#define GC_WATCHDOG_WDOGPERIPHID5_DEFAULT        0x0
-#define GC_WATCHDOG_WDOGPERIPHID6_OFFSET         0xfd8
-#define GC_WATCHDOG_WDOGPERIPHID6_DEFAULT        0x0
-#define GC_WATCHDOG_WDOGPERIPHID7_OFFSET         0xfdc
-#define GC_WATCHDOG_WDOGPERIPHID7_DEFAULT        0x0
-#define GC_WATCHDOG_WDOGPERIPHID0_OFFSET         0xfe0
-#define GC_WATCHDOG_WDOGPERIPHID0_DEFAULT        0x24
-#define GC_WATCHDOG_WDOGPERIPHID1_OFFSET         0xfe4
-#define GC_WATCHDOG_WDOGPERIPHID1_DEFAULT        0xb8
-#define GC_WATCHDOG_WDOGPERIPHID2_OFFSET         0xfe8
-#define GC_WATCHDOG_WDOGPERIPHID2_DEFAULT        0xb
-#define GC_WATCHDOG_WDOGPERIPHID3_OFFSET         0xfec
-#define GC_WATCHDOG_WDOGPERIPHID3_DEFAULT        0x0
-#define GC_WATCHDOG_WDOGPCELLID0_OFFSET          0xff0
-#define GC_WATCHDOG_WDOGPCELLID0_DEFAULT         0xd
-#define GC_WATCHDOG_WDOGPCELLID1_OFFSET          0xff4
-#define GC_WATCHDOG_WDOGPCELLID1_DEFAULT         0xf0
-#define GC_WATCHDOG_WDOGPCELLID2_OFFSET          0xff8
-#define GC_WATCHDOG_WDOGPCELLID2_DEFAULT         0x5
-#define GC_WATCHDOG_WDOGPCELLID3_OFFSET          0xffc
-#define GC_WATCHDOG_WDOGPCELLID3_DEFAULT         0xb1
-#define GC_XO_VERSION_OFFSET                     0x0
-#define GC_XO_VERSION_DEFAULT                    0x101424a
-#define GC_XO_CFG_WR_EN_OFFSET                   0x4
-#define GC_XO_CFG_WR_EN_DEFAULT                  0x1
-#define GC_XO_JTR_CTRL_EN_OFFSET                 0x8
-#define GC_XO_JTR_CTRL_EN_DEFAULT                0x1
-#define GC_XO_CLK_JTR_CTRL_OFFSET                0xc
-#define GC_XO_CLK_JTR_CTRL_DEFAULT               0x3
-#define GC_XO_CLK_JTR_RC_COARSE_ATE_TRIM_OFFSET  0x10
-#define GC_XO_CLK_JTR_RC_COARSE_ATE_TRIM_DEFAULT 0x0
-#define GC_XO_CLK_JTR_RC_FINE_ATE_TRIM_OFFSET    0x14
-#define GC_XO_CLK_JTR_RC_FINE_ATE_TRIM_DEFAULT   0x0
-#define GC_XO_CLK_JTR_CURRENT_OFFSET             0x18
-#define GC_XO_CLK_JTR_CURRENT_DEFAULT            0x0
-#define GC_XO_CLK_JTR_SYNC_CONTENTS_OFFSET       0x1c
-#define GC_XO_CLK_JTR_SYNC_CONTENTS_DEFAULT      0x0
-#define GC_XO_CLK_JTR_TRIM_CTRL_OFFSET           0x20
-#define GC_XO_CLK_JTR_TRIM_CTRL_DEFAULT          0x1e
-#define GC_XO_CLK_JTR_JITTERY_TRIM_EN_OFFSET     0x24
-#define GC_XO_CLK_JTR_JITTERY_TRIM_EN_DEFAULT    0x0
-#define GC_XO_CLK_JTR_JITTERY_TRIM_DIS_SIGNATURE_OFFSET 0x28
-#define GC_XO_CLK_JTR_JITTERY_TRIM_DIS_SIGNATURE_DEFAULT 0x0
-#define GC_XO_CLK_JTR_JITTERY_TRIM_RELOAD_PERIOD_OFFSET 0x2c
-#define GC_XO_CLK_JTR_JITTERY_TRIM_RELOAD_PERIOD_DEFAULT 0xff
-#define GC_XO_CLK_JTR_JITTERY_TRIM_RANDOM_SEED_EN_OFFSET 0x30
-#define GC_XO_CLK_JTR_JITTERY_TRIM_RANDOM_SEED_EN_DEFAULT 0x0
-#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK0_OFFSET  0x34
-#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK0_DEFAULT 0x0
-#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK1_OFFSET  0x38
-#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK1_DEFAULT 0x0
-#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK2_OFFSET  0x3c
-#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK2_DEFAULT 0x0
-#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK3_OFFSET  0x40
-#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK3_DEFAULT 0x0
-#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK4_OFFSET  0x44
-#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK4_DEFAULT 0x0
-#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK5_OFFSET  0x48
-#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK5_DEFAULT 0x0
-#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK6_OFFSET  0x4c
-#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK6_DEFAULT 0x0
-#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK7_OFFSET  0x50
-#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK7_DEFAULT 0x0
-#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK8_OFFSET  0x54
-#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK8_DEFAULT 0x0
-#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK9_OFFSET  0x58
-#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK9_DEFAULT 0x0
-#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK10_OFFSET 0x5c
-#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK10_DEFAULT 0x0
-#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK11_OFFSET 0x60
-#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK11_DEFAULT 0x0
-#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK12_OFFSET 0x64
-#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK12_DEFAULT 0x0
-#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK13_OFFSET 0x68
-#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK13_DEFAULT 0x0
-#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK14_OFFSET 0x6c
-#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK14_DEFAULT 0x0
-#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK15_OFFSET 0x70
-#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK15_DEFAULT 0x0
-#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_OFFSET     0x74
-#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_DEFAULT    0x0
-#define GC_XO_CLK_JTR_CALIB_NOP_SEEN_OFFSET      0x78
-#define GC_XO_CLK_JTR_CALIB_NOP_SEEN_DEFAULT     0x0
-#define GC_XO_CLK_JTR_SLOW_TRIM_CLK_CNT_OFFSET   0x7c
-#define GC_XO_CLK_JTR_SLOW_TRIM_CLK_CNT_DEFAULT  0x0
-#define GC_XO_CLK_JTR_FAST_TRIM_CLK_CNT_OFFSET   0x80
-#define GC_XO_CLK_JTR_FAST_TRIM_CLK_CNT_DEFAULT  0x0
-#define GC_XO_CLK_JTR_FAST_CALIB0_OFFSET         0x84
-#define GC_XO_CLK_JTR_FAST_CALIB0_DEFAULT        0x0
-#define GC_XO_CLK_JTR_FAST_CALIB1_OFFSET         0x88
-#define GC_XO_CLK_JTR_FAST_CALIB1_DEFAULT        0x0
-#define GC_XO_CLK_JTR_FAST_CALIB2_OFFSET         0x8c
-#define GC_XO_CLK_JTR_FAST_CALIB2_DEFAULT        0x0
-#define GC_XO_CLK_JTR_FAST_CALIB3_OFFSET         0x90
-#define GC_XO_CLK_JTR_FAST_CALIB3_DEFAULT        0x0
-#define GC_XO_CLK_JTR_FAST_CALIB4_OFFSET         0x94
-#define GC_XO_CLK_JTR_FAST_CALIB4_DEFAULT        0x0
-#define GC_XO_CLK_JTR_FAST_CALIB5_OFFSET         0x98
-#define GC_XO_CLK_JTR_FAST_CALIB5_DEFAULT        0x0
-#define GC_XO_CLK_JTR_FAST_CALIB6_OFFSET         0x9c
-#define GC_XO_CLK_JTR_FAST_CALIB6_DEFAULT        0x0
-#define GC_XO_CLK_JTR_FAST_CALIB7_OFFSET         0xa0
-#define GC_XO_CLK_JTR_FAST_CALIB7_DEFAULT        0x0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OFFSET    0xa4
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_DEFAULT   0x0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OFFSET    0xa8
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_DEFAULT   0x0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OFFSET    0xac
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_DEFAULT   0x0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OFFSET    0xb0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_DEFAULT   0x0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OFFSET    0xb4
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_DEFAULT   0x0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OFFSET    0xb8
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_DEFAULT   0x0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OFFSET    0xbc
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_DEFAULT   0x0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OFFSET    0xc0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_DEFAULT   0x0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OFFSET    0xc4
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_DEFAULT   0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB0_OFFSET         0xc8
-#define GC_XO_CLK_JTR_SLOW_CALIB0_DEFAULT        0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB1_OFFSET         0xcc
-#define GC_XO_CLK_JTR_SLOW_CALIB1_DEFAULT        0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB2_OFFSET         0xd0
-#define GC_XO_CLK_JTR_SLOW_CALIB2_DEFAULT        0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB3_OFFSET         0xd4
-#define GC_XO_CLK_JTR_SLOW_CALIB3_DEFAULT        0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB4_OFFSET         0xd8
-#define GC_XO_CLK_JTR_SLOW_CALIB4_DEFAULT        0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB5_OFFSET         0xdc
-#define GC_XO_CLK_JTR_SLOW_CALIB5_DEFAULT        0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB6_OFFSET         0xe0
-#define GC_XO_CLK_JTR_SLOW_CALIB6_DEFAULT        0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB7_OFFSET         0xe4
-#define GC_XO_CLK_JTR_SLOW_CALIB7_DEFAULT        0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OFFSET    0xe8
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_DEFAULT   0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OFFSET    0xec
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_DEFAULT   0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OFFSET    0xf0
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_DEFAULT   0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OFFSET    0xf4
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_DEFAULT   0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OFFSET    0xf8
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_DEFAULT   0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OFFSET    0xfc
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_DEFAULT   0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OFFSET    0x100
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_DEFAULT   0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OFFSET    0x104
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_DEFAULT   0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OFFSET    0x108
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_DEFAULT   0x0
-#define GC_XO_CLK_JTR_ENABLE_SW_TRIM_OFFSET      0x10c
-#define GC_XO_CLK_JTR_ENABLE_SW_TRIM_DEFAULT     0x0
-#define GC_XO_CLK_JTR_SW_TRIM_COUNTER_OFFSET     0x110
-#define GC_XO_CLK_JTR_SW_TRIM_COUNTER_DEFAULT    0x0
-#define GC_XO_CLK_TIMER_CTRL_OFFSET              0x114
-#define GC_XO_CLK_TIMER_CTRL_DEFAULT             0x3
-#define GC_XO_CLK_TIMER_RC_COARSE_ATE_TRIM_OFFSET 0x118
-#define GC_XO_CLK_TIMER_RC_COARSE_ATE_TRIM_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_RC_FINE_ATE_TRIM_OFFSET  0x11c
-#define GC_XO_CLK_TIMER_RC_FINE_ATE_TRIM_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_CURRENT_OFFSET           0x120
-#define GC_XO_CLK_TIMER_CURRENT_DEFAULT          0x0
-#define GC_XO_CLK_TIMER_SYNC_CONTENTS_OFFSET     0x124
-#define GC_XO_CLK_TIMER_SYNC_CONTENTS_DEFAULT    0x0
-#define GC_XO_CLK_TIMER_TRIM_CTRL_OFFSET         0x128
-#define GC_XO_CLK_TIMER_TRIM_CTRL_DEFAULT        0x1e
-#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_OFFSET   0x12c
-#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_DEFAULT  0x0
-#define GC_XO_CLK_TIMER_CALIB_NOP_SEEN_OFFSET    0x130
-#define GC_XO_CLK_TIMER_CALIB_NOP_SEEN_DEFAULT   0x0
-#define GC_XO_CLK_TIMER_SLOW_TRIM_CLK_CNT_OFFSET 0x134
-#define GC_XO_CLK_TIMER_SLOW_TRIM_CLK_CNT_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_FAST_TRIM_CLK_CNT_OFFSET 0x138
-#define GC_XO_CLK_TIMER_FAST_TRIM_CLK_CNT_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB0_OFFSET       0x13c
-#define GC_XO_CLK_TIMER_FAST_CALIB0_DEFAULT      0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB1_OFFSET       0x140
-#define GC_XO_CLK_TIMER_FAST_CALIB1_DEFAULT      0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB2_OFFSET       0x144
-#define GC_XO_CLK_TIMER_FAST_CALIB2_DEFAULT      0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB3_OFFSET       0x148
-#define GC_XO_CLK_TIMER_FAST_CALIB3_DEFAULT      0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB4_OFFSET       0x14c
-#define GC_XO_CLK_TIMER_FAST_CALIB4_DEFAULT      0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB5_OFFSET       0x150
-#define GC_XO_CLK_TIMER_FAST_CALIB5_DEFAULT      0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB6_OFFSET       0x154
-#define GC_XO_CLK_TIMER_FAST_CALIB6_DEFAULT      0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB7_OFFSET       0x158
-#define GC_XO_CLK_TIMER_FAST_CALIB7_DEFAULT      0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OFFSET  0x15c
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OFFSET  0x160
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OFFSET  0x164
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OFFSET  0x168
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OFFSET  0x16c
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OFFSET  0x170
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OFFSET  0x174
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OFFSET  0x178
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OFFSET  0x17c
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB0_OFFSET       0x180
-#define GC_XO_CLK_TIMER_SLOW_CALIB0_DEFAULT      0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB1_OFFSET       0x184
-#define GC_XO_CLK_TIMER_SLOW_CALIB1_DEFAULT      0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB2_OFFSET       0x188
-#define GC_XO_CLK_TIMER_SLOW_CALIB2_DEFAULT      0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB3_OFFSET       0x18c
-#define GC_XO_CLK_TIMER_SLOW_CALIB3_DEFAULT      0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB4_OFFSET       0x190
-#define GC_XO_CLK_TIMER_SLOW_CALIB4_DEFAULT      0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB5_OFFSET       0x194
-#define GC_XO_CLK_TIMER_SLOW_CALIB5_DEFAULT      0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB6_OFFSET       0x198
-#define GC_XO_CLK_TIMER_SLOW_CALIB6_DEFAULT      0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB7_OFFSET       0x19c
-#define GC_XO_CLK_TIMER_SLOW_CALIB7_DEFAULT      0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OFFSET  0x1a0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OFFSET  0x1a4
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OFFSET  0x1a8
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OFFSET  0x1ac
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OFFSET  0x1b0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OFFSET  0x1b4
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OFFSET  0x1b8
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OFFSET  0x1bc
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OFFSET  0x1c0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_ENABLE_SW_TRIM_OFFSET    0x1c4
-#define GC_XO_CLK_TIMER_ENABLE_SW_TRIM_DEFAULT   0x0
-#define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_OFFSET   0x1c8
-#define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_DEFAULT  0x0
-#define GC_XO_OSC_XTL_FREQ2X_OFFSET              0x1cc
-#define GC_XO_OSC_XTL_FREQ2X_DEFAULT             0x7
-#define GC_XO_OSC_XTL_FREQ2X_STAT_OFFSET         0x1d0
-#define GC_XO_OSC_XTL_FREQ2X_STAT_DEFAULT        0x6
-#define GC_XO_OSC_XTL_TRIMD_OFFSET               0x1d4
-#define GC_XO_OSC_XTL_TRIMD_DEFAULT              0x7f
-#define GC_XO_OSC_XTL_TRIMG_OFFSET               0x1d8
-#define GC_XO_OSC_XTL_TRIMG_DEFAULT              0x7f
-#define GC_XO_OSC_XTL_CTRL_OFFSET                0x1dc
-#define GC_XO_OSC_XTL_CTRL_DEFAULT               0x0
-#define GC_XO_OSC_XTL_RC_FLTR_OFFSET             0x1e0
-#define GC_XO_OSC_XTL_RC_FLTR_DEFAULT            0x15
-#define GC_XO_OSC_XTL_OVRD_OFFSET                0x1e4
-#define GC_XO_OSC_XTL_OVRD_DEFAULT               0x17
-#define GC_XO_OSC_XTL_OVRD_HOLDB_OFFSET          0x1e8
-#define GC_XO_OSC_XTL_OVRD_HOLDB_DEFAULT         0x1
-#define GC_XO_OSC_XTL_TRIM_OFFSET                0x1ec
-#define GC_XO_OSC_XTL_TRIM_DEFAULT               0x0
-#define GC_XO_OSC_XTL_TRIM_STAT_OFFSET           0x1f0
-#define GC_XO_OSC_XTL_TRIM_STAT_DEFAULT          0x0
-#define GC_XO_OSC_XTL_FSM_EN_OFFSET              0x1f4
-#define GC_XO_OSC_XTL_FSM_EN_DEFAULT             0x0
-#define GC_XO_OSC_XTL_FSM_EN_KEY                 0x60221413
-#define GC_XO_OSC_XTL_FSM_RESETB_OFFSET          0x1f8
-#define GC_XO_OSC_XTL_FSM_RESETB_DEFAULT         0x0
-#define GC_XO_OSC_XTL_FSM_OFFSET                 0x1fc
-#define GC_XO_OSC_XTL_FSM_DEFAULT                0x0
-#define GC_XO_OSC_XTL_FSM_CFG_OFFSET             0x200
-#define GC_XO_OSC_XTL_FSM_CFG_DEFAULT            0xd7488
-#define GC_XO_OSC_TEST_OFFSET                    0x204
-#define GC_XO_OSC_TEST_DEFAULT                   0x0
-#define GC_XO_TESTBUS_SEL_OFFSET                 0x208
-#define GC_XO_TESTBUS_SEL_DEFAULT                0x0
-#define GC_XO_CLK_JTR_TESTBUS_RD_OFFSET          0x20c
-#define GC_XO_CLK_JTR_TESTBUS_RD_DEFAULT         0x0
-#define GC_XO_CLK_TIMER_TESTBUS_RD_OFFSET        0x210
-#define GC_XO_CLK_TIMER_TESTBUS_RD_DEFAULT       0x0
-#define GC_XO_ANTEST_CTRL_OFFSET                 0x214
-#define GC_XO_ANTEST_CTRL_DEFAULT                0x0
-#define GC_XO_DXO_INT_ENABLE_OFFSET              0x218
-#define GC_XO_DXO_INT_ENABLE_DEFAULT             0x0
-#define GC_XO_DXO_INT_STATE_OFFSET               0x21c
-#define GC_XO_DXO_INT_STATE_DEFAULT              0x0
-#define GC_XO_DXO_INT_TEST_OFFSET                0x220
-#define GC_XO_DXO_INT_TEST_DEFAULT               0x0
-#define GC_M3_ITM_STIM0_OFFSET                   0x0
-#define GC_M3_ITM_STIM0_DEFAULT                  0x0
-#define GC_M3_ITM_STIM1_OFFSET                   0x4
-#define GC_M3_ITM_STIM1_DEFAULT                  0x0
-#define GC_M3_ITM_STIM2_OFFSET                   0x8
-#define GC_M3_ITM_STIM2_DEFAULT                  0x0
-#define GC_M3_ITM_STIM3_OFFSET                   0xc
-#define GC_M3_ITM_STIM3_DEFAULT                  0x0
-#define GC_M3_ITM_STIM4_OFFSET                   0x10
-#define GC_M3_ITM_STIM4_DEFAULT                  0x0
-#define GC_M3_ITM_STIM5_OFFSET                   0x14
-#define GC_M3_ITM_STIM5_DEFAULT                  0x0
-#define GC_M3_ITM_STIM6_OFFSET                   0x18
-#define GC_M3_ITM_STIM6_DEFAULT                  0x0
-#define GC_M3_ITM_STIM7_OFFSET                   0x1c
-#define GC_M3_ITM_STIM7_DEFAULT                  0x0
-#define GC_M3_ITM_STIM8_OFFSET                   0x20
-#define GC_M3_ITM_STIM8_DEFAULT                  0x0
-#define GC_M3_ITM_STIM9_OFFSET                   0x24
-#define GC_M3_ITM_STIM9_DEFAULT                  0x0
-#define GC_M3_ITM_STIM10_OFFSET                  0x28
-#define GC_M3_ITM_STIM10_DEFAULT                 0x0
-#define GC_M3_ITM_STIM11_OFFSET                  0x2c
-#define GC_M3_ITM_STIM11_DEFAULT                 0x0
-#define GC_M3_ITM_STIM12_OFFSET                  0x30
-#define GC_M3_ITM_STIM12_DEFAULT                 0x0
-#define GC_M3_ITM_STIM13_OFFSET                  0x34
-#define GC_M3_ITM_STIM13_DEFAULT                 0x0
-#define GC_M3_ITM_STIM14_OFFSET                  0x38
-#define GC_M3_ITM_STIM14_DEFAULT                 0x0
-#define GC_M3_ITM_STIM15_OFFSET                  0x3c
-#define GC_M3_ITM_STIM15_DEFAULT                 0x0
-#define GC_M3_ITM_STIM16_OFFSET                  0x40
-#define GC_M3_ITM_STIM16_DEFAULT                 0x0
-#define GC_M3_ITM_STIM17_OFFSET                  0x44
-#define GC_M3_ITM_STIM17_DEFAULT                 0x0
-#define GC_M3_ITM_STIM18_OFFSET                  0x48
-#define GC_M3_ITM_STIM18_DEFAULT                 0x0
-#define GC_M3_ITM_STIM19_OFFSET                  0x4c
-#define GC_M3_ITM_STIM19_DEFAULT                 0x0
-#define GC_M3_ITM_STIM20_OFFSET                  0x50
-#define GC_M3_ITM_STIM20_DEFAULT                 0x0
-#define GC_M3_ITM_STIM21_OFFSET                  0x54
-#define GC_M3_ITM_STIM21_DEFAULT                 0x0
-#define GC_M3_ITM_STIM22_OFFSET                  0x58
-#define GC_M3_ITM_STIM22_DEFAULT                 0x0
-#define GC_M3_ITM_STIM23_OFFSET                  0x5c
-#define GC_M3_ITM_STIM23_DEFAULT                 0x0
-#define GC_M3_ITM_STIM24_OFFSET                  0x60
-#define GC_M3_ITM_STIM24_DEFAULT                 0x0
-#define GC_M3_ITM_STIM25_OFFSET                  0x64
-#define GC_M3_ITM_STIM25_DEFAULT                 0x0
-#define GC_M3_ITM_STIM26_OFFSET                  0x68
-#define GC_M3_ITM_STIM26_DEFAULT                 0x0
-#define GC_M3_ITM_STIM27_OFFSET                  0x6c
-#define GC_M3_ITM_STIM27_DEFAULT                 0x0
-#define GC_M3_ITM_STIM28_OFFSET                  0x70
-#define GC_M3_ITM_STIM28_DEFAULT                 0x0
-#define GC_M3_ITM_STIM29_OFFSET                  0x74
-#define GC_M3_ITM_STIM29_DEFAULT                 0x0
-#define GC_M3_ITM_STIM30_OFFSET                  0x78
-#define GC_M3_ITM_STIM30_DEFAULT                 0x0
-#define GC_M3_ITM_STIM31_OFFSET                  0x7c
-#define GC_M3_ITM_STIM31_DEFAULT                 0x0
-#define GC_M3_ITM_TER_OFFSET                     0xe00
-#define GC_M3_ITM_TER_DEFAULT                    0x0
-#define GC_M3_ITM_TPR_OFFSET                     0xe40
-#define GC_M3_ITM_TPR_DEFAULT                    0x0
-#define GC_M3_ITM_TCR_OFFSET                     0xe80
-#define GC_M3_ITM_TCR_DEFAULT                    0x0
-#define GC_M3_ITM_INTWREG_OFFSET                 0xef8
-#define GC_M3_ITM_INTWREG_DEFAULT                0x0
-#define GC_M3_ITM_INTRREG_OFFSET                 0xefc
-#define GC_M3_ITM_INTRREG_DEFAULT                0x0
-#define GC_M3_ITM_INTMREG_OFFSET                 0xf00
-#define GC_M3_ITM_INTMREG_DEFAULT                0x0
-#define GC_M3_ITM_LOCKCREG_OFFSET                0xfb0
-#define GC_M3_ITM_LOCKCREG_DEFAULT               0x0
-#define GC_M3_ITM_LOCKSREG_OFFSET                0xfb4
-#define GC_M3_ITM_LOCKSREG_DEFAULT               0x0
-#define GC_M3_ITM_PID4_OFFSET                    0xfd0
-#define GC_M3_ITM_PID4_DEFAULT                   0x4
-#define GC_M3_ITM_PID5_OFFSET                    0xfd4
-#define GC_M3_ITM_PID5_DEFAULT                   0x0
-#define GC_M3_ITM_PID6_OFFSET                    0xfd8
-#define GC_M3_ITM_PID6_DEFAULT                   0x0
-#define GC_M3_ITM_PID7_OFFSET                    0xfdc
-#define GC_M3_ITM_PID7_DEFAULT                   0x0
-#define GC_M3_ITM_PID0_OFFSET                    0xfe0
-#define GC_M3_ITM_PID0_DEFAULT                   0x1
-#define GC_M3_ITM_PID1_OFFSET                    0xfe4
-#define GC_M3_ITM_PID1_DEFAULT                   0xb0
-#define GC_M3_ITM_PID2_OFFSET                    0xfe8
-#define GC_M3_ITM_PID2_DEFAULT                   0x1b
-#define GC_M3_ITM_PID3_OFFSET                    0xfec
-#define GC_M3_ITM_PID3_DEFAULT                   0x0
-#define GC_M3_ITM_CID0_OFFSET                    0xff0
-#define GC_M3_ITM_CID0_DEFAULT                   0xd
-#define GC_M3_ITM_CID1_OFFSET                    0xff4
-#define GC_M3_ITM_CID1_DEFAULT                   0xe0
-#define GC_M3_ITM_CID2_OFFSET                    0xff8
-#define GC_M3_ITM_CID2_DEFAULT                   0x5
-#define GC_M3_ITM_CID3_OFFSET                    0xffc
-#define GC_M3_ITM_CID3_DEFAULT                   0xb1
-#define GC_M3_DWT_CTRL_OFFSET                    0x1000
-#define GC_M3_DWT_CTRL_DEFAULT                   0x40000000
-#define GC_M3_DWT_CYCCNT_OFFSET                  0x1004
-#define GC_M3_DWT_CYCCNT_DEFAULT                 0x0
-#define GC_M3_DWT_CPICNT_OFFSET                  0x1008
-#define GC_M3_DWT_CPICNT_DEFAULT                 0x0
-#define GC_M3_DWT_EXCCNT_OFFSET                  0x100c
-#define GC_M3_DWT_EXCCNT_DEFAULT                 0x0
-#define GC_M3_DWT_SLEEPCNT_OFFSET                0x1010
-#define GC_M3_DWT_SLEEPCNT_DEFAULT               0x0
-#define GC_M3_DWT_LSUCNT_OFFSET                  0x1014
-#define GC_M3_DWT_LSUCNT_DEFAULT                 0x0
-#define GC_M3_DWT_FOLDCNT_OFFSET                 0x1018
-#define GC_M3_DWT_FOLDCNT_DEFAULT                0x0
-#define GC_M3_DWT_PCSR_OFFSET                    0x101c
-#define GC_M3_DWT_PCSR_DEFAULT                   0x0
-#define GC_M3_DWT_COMP0_OFFSET                   0x1020
-#define GC_M3_DWT_COMP0_DEFAULT                  0x0
-#define GC_M3_DWT_MASK0_OFFSET                   0x1024
-#define GC_M3_DWT_MASK0_DEFAULT                  0x0
-#define GC_M3_DWT_FUNCTION0_OFFSET               0x1028
-#define GC_M3_DWT_FUNCTION0_DEFAULT              0x0
-#define GC_M3_DWT_COMP1_OFFSET                   0x1030
-#define GC_M3_DWT_COMP1_DEFAULT                  0x0
-#define GC_M3_DWT_MASK1_OFFSET                   0x1034
-#define GC_M3_DWT_MASK1_DEFAULT                  0x0
-#define GC_M3_DWT_FUNCTION1_OFFSET               0x1038
-#define GC_M3_DWT_FUNCTION1_DEFAULT              0x0
-#define GC_M3_DWT_COMP2_OFFSET                   0x1040
-#define GC_M3_DWT_COMP2_DEFAULT                  0x0
-#define GC_M3_DWT_MASK2_OFFSET                   0x1044
-#define GC_M3_DWT_MASK2_DEFAULT                  0x0
-#define GC_M3_DWT_FUNCTION2_OFFSET               0x1048
-#define GC_M3_DWT_FUNCTION2_DEFAULT              0x0
-#define GC_M3_DWT_COMP3_OFFSET                   0x1050
-#define GC_M3_DWT_COMP3_DEFAULT                  0x0
-#define GC_M3_DWT_MASK3_OFFSET                   0x1054
-#define GC_M3_DWT_MASK3_DEFAULT                  0x0
-#define GC_M3_DWT_FUNCTION3_OFFSET               0x1058
-#define GC_M3_DWT_FUNCTION3_DEFAULT              0x0
-#define GC_M3_DWT_PID4_OFFSET                    0x1fd0
-#define GC_M3_DWT_PID4_DEFAULT                   0x4
-#define GC_M3_DWT_PID5_OFFSET                    0x1fd4
-#define GC_M3_DWT_PID5_DEFAULT                   0x0
-#define GC_M3_DWT_PID6_OFFSET                    0x1fd8
-#define GC_M3_DWT_PID6_DEFAULT                   0x0
-#define GC_M3_DWT_PID7_OFFSET                    0x1fdc
-#define GC_M3_DWT_PID7_DEFAULT                   0x0
-#define GC_M3_DWT_PID0_OFFSET                    0x1fe0
-#define GC_M3_DWT_PID0_DEFAULT                   0x2
-#define GC_M3_DWT_PID1_OFFSET                    0x1fe4
-#define GC_M3_DWT_PID1_DEFAULT                   0xb0
-#define GC_M3_DWT_PID2_OFFSET                    0x1fe8
-#define GC_M3_DWT_PID2_DEFAULT                   0x1b
-#define GC_M3_DWT_PID3_OFFSET                    0x1fec
-#define GC_M3_DWT_PID3_DEFAULT                   0x0
-#define GC_M3_DWT_CID0_OFFSET                    0x1ff0
-#define GC_M3_DWT_CID0_DEFAULT                   0xd
-#define GC_M3_DWT_CID1_OFFSET                    0x1ff4
-#define GC_M3_DWT_CID1_DEFAULT                   0xe0
-#define GC_M3_DWT_CID2_OFFSET                    0x1ff8
-#define GC_M3_DWT_CID2_DEFAULT                   0x5
-#define GC_M3_DWT_CID3_OFFSET                    0x1ffc
-#define GC_M3_DWT_CID3_DEFAULT                   0xb1
-#define GC_M3_FP_CTRL_OFFSET                     0x2000
-#define GC_M3_FP_CTRL_DEFAULT                    0x260
-#define GC_M3_FP_REMAP_OFFSET                    0x2004
-#define GC_M3_FP_REMAP_DEFAULT                   0x0
-#define GC_M3_FP_COMP0_OFFSET                    0x2008
-#define GC_M3_FP_COMP0_DEFAULT                   0x0
-#define GC_M3_FP_COMP1_OFFSET                    0x200c
-#define GC_M3_FP_COMP1_DEFAULT                   0x0
-#define GC_M3_FP_COMP2_OFFSET                    0x2010
-#define GC_M3_FP_COMP2_DEFAULT                   0x0
-#define GC_M3_FP_COMP3_OFFSET                    0x2014
-#define GC_M3_FP_COMP3_DEFAULT                   0x0
-#define GC_M3_FP_COMP4_OFFSET                    0x2018
-#define GC_M3_FP_COMP4_DEFAULT                   0x0
-#define GC_M3_FP_COMP5_OFFSET                    0x201c
-#define GC_M3_FP_COMP5_DEFAULT                   0x0
-#define GC_M3_FP_COMP6_OFFSET                    0x2020
-#define GC_M3_FP_COMP6_DEFAULT                   0x0
-#define GC_M3_FP_COMP7_OFFSET                    0x2024
-#define GC_M3_FP_COMP7_DEFAULT                   0x0
-#define GC_M3_FP_PID4_OFFSET                     0x2fd0
-#define GC_M3_FP_PID4_DEFAULT                    0x4
-#define GC_M3_FP_PID5_OFFSET                     0x2fd4
-#define GC_M3_FP_PID5_DEFAULT                    0x0
-#define GC_M3_FP_PID6_OFFSET                     0x2fd8
-#define GC_M3_FP_PID6_DEFAULT                    0x0
-#define GC_M3_FP_PID7_OFFSET                     0x2fdc
-#define GC_M3_FP_PID7_DEFAULT                    0x0
-#define GC_M3_FP_PID0_OFFSET                     0x2fe0
-#define GC_M3_FP_PID0_DEFAULT                    0x3
-#define GC_M3_FP_PID1_OFFSET                     0x2fe4
-#define GC_M3_FP_PID1_DEFAULT                    0xb0
-#define GC_M3_FP_PID2_OFFSET                     0x2fe8
-#define GC_M3_FP_PID2_DEFAULT                    0xb
-#define GC_M3_FP_PID3_OFFSET                     0x2fec
-#define GC_M3_FP_PID3_DEFAULT                    0x0
-#define GC_M3_FP_CID0_OFFSET                     0x2ff0
-#define GC_M3_FP_CID0_DEFAULT                    0xd
-#define GC_M3_FP_CID1_OFFSET                     0x2ff4
-#define GC_M3_FP_CID1_DEFAULT                    0xe0
-#define GC_M3_FP_CID2_OFFSET                     0x2ff8
-#define GC_M3_FP_CID2_DEFAULT                    0x5
-#define GC_M3_FP_CID3_OFFSET                     0x2ffc
-#define GC_M3_FP_CID3_DEFAULT                    0xb1
-#define GC_M3_ICTR_OFFSET                        0xe004
-#define GC_M3_ICTR_DEFAULT                       0x7
-#define GC_M3_SYST_CSR_OFFSET                    0xe010
-#define GC_M3_SYST_CSR_DEFAULT                   0x4
-#define GC_M3_SYST_RVR_OFFSET                    0xe014
-#define GC_M3_SYST_RVR_DEFAULT                   0x0
-#define GC_M3_SYST_CVR_OFFSET                    0xe018
-#define GC_M3_SYST_CVR_DEFAULT                   0x0
-#define GC_M3_SYST_CALIB_OFFSET                  0xe01c
-#define GC_M3_SYST_CALIB_DEFAULT                 0x3f79f
-#define GC_M3_NVIC_ISER0_OFFSET                  0xe100
-#define GC_M3_NVIC_ISER0_DEFAULT                 0x0
-#define GC_M3_NVIC_ISER1_OFFSET                  0xe104
-#define GC_M3_NVIC_ISER1_DEFAULT                 0x0
-#define GC_M3_NVIC_ISER2_OFFSET                  0xe108
-#define GC_M3_NVIC_ISER2_DEFAULT                 0x0
-#define GC_M3_NVIC_ISER3_OFFSET                  0xe10c
-#define GC_M3_NVIC_ISER3_DEFAULT                 0x0
-#define GC_M3_NVIC_ISER4_OFFSET                  0xe110
-#define GC_M3_NVIC_ISER4_DEFAULT                 0x0
-#define GC_M3_NVIC_ISER5_OFFSET                  0xe114
-#define GC_M3_NVIC_ISER5_DEFAULT                 0x0
-#define GC_M3_NVIC_ISER6_OFFSET                  0xe118
-#define GC_M3_NVIC_ISER6_DEFAULT                 0x0
-#define GC_M3_NVIC_ISER7_OFFSET                  0xe11c
-#define GC_M3_NVIC_ISER7_DEFAULT                 0x0
-#define GC_M3_NVIC_ICER0_OFFSET                  0xe180
-#define GC_M3_NVIC_ICER0_DEFAULT                 0x0
-#define GC_M3_NVIC_ICER1_OFFSET                  0xe184
-#define GC_M3_NVIC_ICER1_DEFAULT                 0x0
-#define GC_M3_NVIC_ICER2_OFFSET                  0xe188
-#define GC_M3_NVIC_ICER2_DEFAULT                 0x0
-#define GC_M3_NVIC_ICER3_OFFSET                  0xe18c
-#define GC_M3_NVIC_ICER3_DEFAULT                 0x0
-#define GC_M3_NVIC_ICER4_OFFSET                  0xe190
-#define GC_M3_NVIC_ICER4_DEFAULT                 0x0
-#define GC_M3_NVIC_ICER5_OFFSET                  0xe194
-#define GC_M3_NVIC_ICER5_DEFAULT                 0x0
-#define GC_M3_NVIC_ICER6_OFFSET                  0xe198
-#define GC_M3_NVIC_ICER6_DEFAULT                 0x0
-#define GC_M3_NVIC_ICER7_OFFSET                  0xe19c
-#define GC_M3_NVIC_ICER7_DEFAULT                 0x0
-#define GC_M3_NVIC_ISPR0_OFFSET                  0xe200
-#define GC_M3_NVIC_ISPR0_DEFAULT                 0x0
-#define GC_M3_NVIC_ISPR1_OFFSET                  0xe204
-#define GC_M3_NVIC_ISPR1_DEFAULT                 0x0
-#define GC_M3_NVIC_ISPR2_OFFSET                  0xe208
-#define GC_M3_NVIC_ISPR2_DEFAULT                 0x0
-#define GC_M3_NVIC_ISPR3_OFFSET                  0xe20c
-#define GC_M3_NVIC_ISPR3_DEFAULT                 0x0
-#define GC_M3_NVIC_ISPR4_OFFSET                  0xe210
-#define GC_M3_NVIC_ISPR4_DEFAULT                 0x0
-#define GC_M3_NVIC_ISPR5_OFFSET                  0xe214
-#define GC_M3_NVIC_ISPR5_DEFAULT                 0x0
-#define GC_M3_NVIC_ISPR6_OFFSET                  0xe218
-#define GC_M3_NVIC_ISPR6_DEFAULT                 0x0
-#define GC_M3_NVIC_ISPR7_OFFSET                  0xe21c
-#define GC_M3_NVIC_ISPR7_DEFAULT                 0x0
-#define GC_M3_NVIC_ICPR0_OFFSET                  0xe280
-#define GC_M3_NVIC_ICPR0_DEFAULT                 0x0
-#define GC_M3_NVIC_ICPR1_OFFSET                  0xe284
-#define GC_M3_NVIC_ICPR1_DEFAULT                 0x0
-#define GC_M3_NVIC_ICPR2_OFFSET                  0xe288
-#define GC_M3_NVIC_ICPR2_DEFAULT                 0x0
-#define GC_M3_NVIC_ICPR3_OFFSET                  0xe28c
-#define GC_M3_NVIC_ICPR3_DEFAULT                 0x0
-#define GC_M3_NVIC_ICPR4_OFFSET                  0xe290
-#define GC_M3_NVIC_ICPR4_DEFAULT                 0x0
-#define GC_M3_NVIC_ICPR5_OFFSET                  0xe294
-#define GC_M3_NVIC_ICPR5_DEFAULT                 0x0
-#define GC_M3_NVIC_ICPR6_OFFSET                  0xe298
-#define GC_M3_NVIC_ICPR6_DEFAULT                 0x0
-#define GC_M3_NVIC_ICPR7_OFFSET                  0xe29c
-#define GC_M3_NVIC_ICPR7_DEFAULT                 0x0
-#define GC_M3_NVIC_IABR0_OFFSET                  0xe300
-#define GC_M3_NVIC_IABR0_DEFAULT                 0x0
-#define GC_M3_NVIC_IABR1_OFFSET                  0xe304
-#define GC_M3_NVIC_IABR1_DEFAULT                 0x0
-#define GC_M3_NVIC_IABR2_OFFSET                  0xe308
-#define GC_M3_NVIC_IABR2_DEFAULT                 0x0
-#define GC_M3_NVIC_IABR3_OFFSET                  0xe30c
-#define GC_M3_NVIC_IABR3_DEFAULT                 0x0
-#define GC_M3_NVIC_IABR4_OFFSET                  0xe310
-#define GC_M3_NVIC_IABR4_DEFAULT                 0x0
-#define GC_M3_NVIC_IABR5_OFFSET                  0xe314
-#define GC_M3_NVIC_IABR5_DEFAULT                 0x0
-#define GC_M3_NVIC_IABR6_OFFSET                  0xe318
-#define GC_M3_NVIC_IABR6_DEFAULT                 0x0
-#define GC_M3_NVIC_IABR7_OFFSET                  0xe31c
-#define GC_M3_NVIC_IABR7_DEFAULT                 0x0
-#define GC_M3_NVIC_IPR0_OFFSET                   0xe400
-#define GC_M3_NVIC_IPR0_DEFAULT                  0x0
-#define GC_M3_NVIC_IPR1_OFFSET                   0xe404
-#define GC_M3_NVIC_IPR1_DEFAULT                  0x0
-#define GC_M3_NVIC_IPR2_OFFSET                   0xe408
-#define GC_M3_NVIC_IPR2_DEFAULT                  0x0
-#define GC_M3_NVIC_IPR3_OFFSET                   0xe40c
-#define GC_M3_NVIC_IPR3_DEFAULT                  0x0
-#define GC_M3_NVIC_IPR4_OFFSET                   0xe410
-#define GC_M3_NVIC_IPR4_DEFAULT                  0x0
-#define GC_M3_NVIC_IPR5_OFFSET                   0xe414
-#define GC_M3_NVIC_IPR5_DEFAULT                  0x0
-#define GC_M3_NVIC_IPR6_OFFSET                   0xe418
-#define GC_M3_NVIC_IPR6_DEFAULT                  0x0
-#define GC_M3_NVIC_IPR7_OFFSET                   0xe41c
-#define GC_M3_NVIC_IPR7_DEFAULT                  0x0
-#define GC_M3_CPUID_OFFSET                       0xed00
-#define GC_M3_CPUID_DEFAULT                      0x412fc231
-#define GC_M3_ICSR_OFFSET                        0xed04
-#define GC_M3_ICSR_DEFAULT                       0x0
-#define GC_M3_VTOR_OFFSET                        0xed08
-#define GC_M3_VTOR_DEFAULT                       0x0
-#define GC_M3_AIRCR_OFFSET                       0xed0c
-#define GC_M3_AIRCR_DEFAULT                      0x0
-#define GC_M3_SCR_OFFSET                         0xed10
-#define GC_M3_SCR_DEFAULT                        0x0
-#define GC_M3_CCR_OFFSET                         0xed14
-#define GC_M3_CCR_DEFAULT                        0x0
-#define GC_M3_SHPR1_OFFSET                       0xed18
-#define GC_M3_SHPR1_DEFAULT                      0x0
-#define GC_M3_SHPR2_OFFSET                       0xed1c
-#define GC_M3_SHPR2_DEFAULT                      0x0
-#define GC_M3_SHPR3_OFFSET                       0xed20
-#define GC_M3_SHPR3_DEFAULT                      0x0
-#define GC_M3_SHCSR_OFFSET                       0xed24
-#define GC_M3_SHCSR_DEFAULT                      0x0
-#define GC_M3_CFSR_OFFSET                        0xed28
-#define GC_M3_CFSR_DEFAULT                       0x0
-#define GC_M3_HFSR_OFFSET                        0xed2c
-#define GC_M3_HFSR_DEFAULT                       0x0
-#define GC_M3_DFSR_OFFSET                        0xed30
-#define GC_M3_DFSR_DEFAULT                       0x0
-#define GC_M3_MMFAR_OFFSET                       0xed34
-#define GC_M3_MMFAR_DEFAULT                      0x0
-#define GC_M3_BFAR_OFFSET                        0xed38
-#define GC_M3_BFAR_DEFAULT                       0x0
-#define GC_M3_AFSR_OFFSET                        0xed3c
-#define GC_M3_AFSR_DEFAULT                       0x0
-#define GC_M3_MPU_TYPE_OFFSET                    0xed90
-#define GC_M3_MPU_TYPE_DEFAULT                   0x800
-#define GC_M3_MPU_CTRL_OFFSET                    0xed94
-#define GC_M3_MPU_CTRL_DEFAULT                   0x0
-#define GC_M3_MPU_RNR_OFFSET                     0xed98
-#define GC_M3_MPU_RNR_DEFAULT                    0x0
-#define GC_M3_MPU_RBAR_OFFSET                    0xed9c
-#define GC_M3_MPU_RBAR_DEFAULT                   0x0
-#define GC_M3_MPU_RASR_OFFSET                    0xeda0
-#define GC_M3_MPU_RASR_DEFAULT                   0x0
-#define GC_M3_MPU_RBAR_A1_OFFSET                 0xeda4
-#define GC_M3_MPU_RBAR_A1_DEFAULT                0x0
-#define GC_M3_MPU_RASR_A1_OFFSET                 0xeda8
-#define GC_M3_MPU_RASR_A1_DEFAULT                0x0
-#define GC_M3_MPU_RBAR_A2_OFFSET                 0xedac
-#define GC_M3_MPU_RBAR_A2_DEFAULT                0x0
-#define GC_M3_MPU_RASR_A2_OFFSET                 0xedb0
-#define GC_M3_MPU_RASR_A2_DEFAULT                0x0
-#define GC_M3_MPU_RBAR_A3_OFFSET                 0xedb4
-#define GC_M3_MPU_RBAR_A3_DEFAULT                0x0
-#define GC_M3_MPU_RASR_A3_OFFSET                 0xedb8
-#define GC_M3_MPU_RASR_A3_DEFAULT                0x0
-#define GC_M3_DHCSR_OFFSET                       0xedf0
-#define GC_M3_DHCSR_DEFAULT                      0x0
-#define GC_M3_DCRSR_OFFSET                       0xedf4
-#define GC_M3_DCRSR_DEFAULT                      0x0
-#define GC_M3_DCRDR_OFFSET                       0xedf8
-#define GC_M3_DCRDR_DEFAULT                      0x0
-#define GC_M3_DEMCR_OFFSET                       0xedfc
-#define GC_M3_DEMCR_DEFAULT                      0x0
-#define GC_M3_TPIU_SSPSR_OFFSET                  0x40000
-#define GC_M3_TPIU_SSPSR_DEFAULT                 0x0
-#define GC_M3_TPIU_CSPSR_OFFSET                  0x40004
-#define GC_M3_TPIU_CSPSR_DEFAULT                 0x1
-#define GC_M3_TPIU_ACPR_OFFSET                   0x40010
-#define GC_M3_TPIU_ACPR_DEFAULT                  0x0
-#define GC_M3_TPIU_SPPR_OFFSET                   0x400f0
-#define GC_M3_TPIU_SPPR_DEFAULT                  0x1
-#define GC_M3_TPIU_FFSR_OFFSET                   0x40300
-#define GC_M3_TPIU_FFSR_DEFAULT                  0x8
-#define GC_M3_TPIU_FFCR_OFFSET                   0x40304
-#define GC_M3_TPIU_FFCR_DEFAULT                  0x0
-#define GC_M3_TPIU_FSCR_OFFSET                   0x40308
-#define GC_M3_TPIU_FSCR_DEFAULT                  0x0
-#define GC_M3_TRIGGER_OFFSET                     0x41ee8
-#define GC_M3_TRIGGER_DEFAULT                    0x0
-#define GC_M3_ITATBCTR2_OFFSET                   0x41ef0
-#define GC_M3_ITATBCTR2_DEFAULT                  0x0
-#define GC_M3_ITATBCTR0_OFFSET                   0x41ef8
-#define GC_M3_ITATBCTR0_DEFAULT                  0x0
-#define GC_M3_ITCTRL_OFFSET                      0x41f00
-#define GC_M3_ITCTRL_DEFAULT                     0x0
-#define GC_M3_CLAIMSET_OFFSET                    0x41fa0
-#define GC_M3_CLAIMSET_DEFAULT                   0x0
-#define GC_M3_CLAIMCLR_OFFSET                    0x41fa4
-#define GC_M3_CLAIMCLR_DEFAULT                   0x0
-#define GC_M3_DEVID_OFFSET                       0x41fc8
-#define GC_M3_DEVID_DEFAULT                      0xca0
-#define GC_M3_DEVTYPE_OFFSET                     0x41fcc
-#define GC_M3_DEVTYPE_DEFAULT                    0x11
-#define GC_M3_HASHER_LOAD_OFFSET                 0xaa008
-#define GC_M3_HASHER_LOAD_DEFAULT                0x0
-#define GC_M3_HASHER_START_OFFSET                0xaa010
-#define GC_M3_HASHER_START_DEFAULT               0x0
-#define GC_M3_HASHER_STOP_OFFSET                 0xaa018
-#define GC_M3_HASHER_STOP_DEFAULT                0x0
-#define GC_M3_HASHER_CHECK_OFFSET                0xaa020
-#define GC_M3_HASHER_CHECK_DEFAULT               0x0
-#define GC_M3_HASHER_VALUE_OFFSET                0xaa028
-#define GC_M3_HASHER_VALUE_DEFAULT               0x0
-#define GC_M3_ITM_STIM0_ADDR                     0xe0000000
-#define GC_M3_ITM_STIM1_ADDR                     0xe0000004
-#define GC_M3_ITM_STIM2_ADDR                     0xe0000008
-#define GC_M3_ITM_STIM3_ADDR                     0xe000000c
-#define GC_M3_ITM_STIM4_ADDR                     0xe0000010
-#define GC_M3_ITM_STIM5_ADDR                     0xe0000014
-#define GC_M3_ITM_STIM6_ADDR                     0xe0000018
-#define GC_M3_ITM_STIM7_ADDR                     0xe000001c
-#define GC_M3_ITM_STIM8_ADDR                     0xe0000020
-#define GC_M3_ITM_STIM9_ADDR                     0xe0000024
-#define GC_M3_ITM_STIM10_ADDR                    0xe0000028
-#define GC_M3_ITM_STIM11_ADDR                    0xe000002c
-#define GC_M3_ITM_STIM12_ADDR                    0xe0000030
-#define GC_M3_ITM_STIM13_ADDR                    0xe0000034
-#define GC_M3_ITM_STIM14_ADDR                    0xe0000038
-#define GC_M3_ITM_STIM15_ADDR                    0xe000003c
-#define GC_M3_ITM_STIM16_ADDR                    0xe0000040
-#define GC_M3_ITM_STIM17_ADDR                    0xe0000044
-#define GC_M3_ITM_STIM18_ADDR                    0xe0000048
-#define GC_M3_ITM_STIM19_ADDR                    0xe000004c
-#define GC_M3_ITM_STIM20_ADDR                    0xe0000050
-#define GC_M3_ITM_STIM21_ADDR                    0xe0000054
-#define GC_M3_ITM_STIM22_ADDR                    0xe0000058
-#define GC_M3_ITM_STIM23_ADDR                    0xe000005c
-#define GC_M3_ITM_STIM24_ADDR                    0xe0000060
-#define GC_M3_ITM_STIM25_ADDR                    0xe0000064
-#define GC_M3_ITM_STIM26_ADDR                    0xe0000068
-#define GC_M3_ITM_STIM27_ADDR                    0xe000006c
-#define GC_M3_ITM_STIM28_ADDR                    0xe0000070
-#define GC_M3_ITM_STIM29_ADDR                    0xe0000074
-#define GC_M3_ITM_STIM30_ADDR                    0xe0000078
-#define GC_M3_ITM_STIM31_ADDR                    0xe000007c
-#define GC_M3_ITM_TER_ADDR                       0xe0000e00
-#define GC_M3_ITM_TPR_ADDR                       0xe0000e40
-#define GC_M3_ITM_TCR_ADDR                       0xe0000e80
-#define GC_M3_ITM_INTWREG_ADDR                   0xe0000ef8
-#define GC_M3_ITM_INTRREG_ADDR                   0xe0000efc
-#define GC_M3_ITM_INTMREG_ADDR                   0xe0000f00
-#define GC_M3_ITM_LOCKCREG_ADDR                  0xe0000fb0
-#define GC_M3_ITM_LOCKSREG_ADDR                  0xe0000fb4
-#define GC_M3_ITM_PID4_ADDR                      0xe0000fd0
-#define GC_M3_ITM_PID5_ADDR                      0xe0000fd4
-#define GC_M3_ITM_PID6_ADDR                      0xe0000fd8
-#define GC_M3_ITM_PID7_ADDR                      0xe0000fdc
-#define GC_M3_ITM_PID0_ADDR                      0xe0000fe0
-#define GC_M3_ITM_PID1_ADDR                      0xe0000fe4
-#define GC_M3_ITM_PID2_ADDR                      0xe0000fe8
-#define GC_M3_ITM_PID3_ADDR                      0xe0000fec
-#define GC_M3_ITM_CID0_ADDR                      0xe0000ff0
-#define GC_M3_ITM_CID1_ADDR                      0xe0000ff4
-#define GC_M3_ITM_CID2_ADDR                      0xe0000ff8
-#define GC_M3_ITM_CID3_ADDR                      0xe0000ffc
-#define GC_M3_DWT_CTRL_ADDR                      0xe0001000
-#define GC_M3_DWT_CYCCNT_ADDR                    0xe0001004
-#define GC_M3_DWT_CPICNT_ADDR                    0xe0001008
-#define GC_M3_DWT_EXCCNT_ADDR                    0xe000100c
-#define GC_M3_DWT_SLEEPCNT_ADDR                  0xe0001010
-#define GC_M3_DWT_LSUCNT_ADDR                    0xe0001014
-#define GC_M3_DWT_FOLDCNT_ADDR                   0xe0001018
-#define GC_M3_DWT_PCSR_ADDR                      0xe000101c
-#define GC_M3_DWT_COMP0_ADDR                     0xe0001020
-#define GC_M3_DWT_MASK0_ADDR                     0xe0001024
-#define GC_M3_DWT_FUNCTION0_ADDR                 0xe0001028
-#define GC_M3_DWT_COMP1_ADDR                     0xe0001030
-#define GC_M3_DWT_MASK1_ADDR                     0xe0001034
-#define GC_M3_DWT_FUNCTION1_ADDR                 0xe0001038
-#define GC_M3_DWT_COMP2_ADDR                     0xe0001040
-#define GC_M3_DWT_MASK2_ADDR                     0xe0001044
-#define GC_M3_DWT_FUNCTION2_ADDR                 0xe0001048
-#define GC_M3_DWT_COMP3_ADDR                     0xe0001050
-#define GC_M3_DWT_MASK3_ADDR                     0xe0001054
-#define GC_M3_DWT_FUNCTION3_ADDR                 0xe0001058
-#define GC_M3_DWT_PID4_ADDR                      0xe0001fd0
-#define GC_M3_DWT_PID5_ADDR                      0xe0001fd4
-#define GC_M3_DWT_PID6_ADDR                      0xe0001fd8
-#define GC_M3_DWT_PID7_ADDR                      0xe0001fdc
-#define GC_M3_DWT_PID0_ADDR                      0xe0001fe0
-#define GC_M3_DWT_PID1_ADDR                      0xe0001fe4
-#define GC_M3_DWT_PID2_ADDR                      0xe0001fe8
-#define GC_M3_DWT_PID3_ADDR                      0xe0001fec
-#define GC_M3_DWT_CID0_ADDR                      0xe0001ff0
-#define GC_M3_DWT_CID1_ADDR                      0xe0001ff4
-#define GC_M3_DWT_CID2_ADDR                      0xe0001ff8
-#define GC_M3_DWT_CID3_ADDR                      0xe0001ffc
-#define GC_M3_FP_CTRL_ADDR                       0xe0002000
-#define GC_M3_FP_REMAP_ADDR                      0xe0002004
-#define GC_M3_FP_COMP0_ADDR                      0xe0002008
-#define GC_M3_FP_COMP1_ADDR                      0xe000200c
-#define GC_M3_FP_COMP2_ADDR                      0xe0002010
-#define GC_M3_FP_COMP3_ADDR                      0xe0002014
-#define GC_M3_FP_COMP4_ADDR                      0xe0002018
-#define GC_M3_FP_COMP5_ADDR                      0xe000201c
-#define GC_M3_FP_COMP6_ADDR                      0xe0002020
-#define GC_M3_FP_COMP7_ADDR                      0xe0002024
-#define GC_M3_FP_PID4_ADDR                       0xe0002fd0
-#define GC_M3_FP_PID5_ADDR                       0xe0002fd4
-#define GC_M3_FP_PID6_ADDR                       0xe0002fd8
-#define GC_M3_FP_PID7_ADDR                       0xe0002fdc
-#define GC_M3_FP_PID0_ADDR                       0xe0002fe0
-#define GC_M3_FP_PID1_ADDR                       0xe0002fe4
-#define GC_M3_FP_PID2_ADDR                       0xe0002fe8
-#define GC_M3_FP_PID3_ADDR                       0xe0002fec
-#define GC_M3_FP_CID0_ADDR                       0xe0002ff0
-#define GC_M3_FP_CID1_ADDR                       0xe0002ff4
-#define GC_M3_FP_CID2_ADDR                       0xe0002ff8
-#define GC_M3_FP_CID3_ADDR                       0xe0002ffc
-#define GC_M3_ICTR_ADDR                          0xe000e004
-#define GC_M3_SYST_CSR_ADDR                      0xe000e010
-#define GC_M3_SYST_RVR_ADDR                      0xe000e014
-#define GC_M3_SYST_CVR_ADDR                      0xe000e018
-#define GC_M3_SYST_CALIB_ADDR                    0xe000e01c
-#define GC_M3_NVIC_ISER0_ADDR                    0xe000e100
-#define GC_M3_NVIC_ISER1_ADDR                    0xe000e104
-#define GC_M3_NVIC_ISER2_ADDR                    0xe000e108
-#define GC_M3_NVIC_ISER3_ADDR                    0xe000e10c
-#define GC_M3_NVIC_ISER4_ADDR                    0xe000e110
-#define GC_M3_NVIC_ISER5_ADDR                    0xe000e114
-#define GC_M3_NVIC_ISER6_ADDR                    0xe000e118
-#define GC_M3_NVIC_ISER7_ADDR                    0xe000e11c
-#define GC_M3_NVIC_ICER0_ADDR                    0xe000e180
-#define GC_M3_NVIC_ICER1_ADDR                    0xe000e184
-#define GC_M3_NVIC_ICER2_ADDR                    0xe000e188
-#define GC_M3_NVIC_ICER3_ADDR                    0xe000e18c
-#define GC_M3_NVIC_ICER4_ADDR                    0xe000e190
-#define GC_M3_NVIC_ICER5_ADDR                    0xe000e194
-#define GC_M3_NVIC_ICER6_ADDR                    0xe000e198
-#define GC_M3_NVIC_ICER7_ADDR                    0xe000e19c
-#define GC_M3_NVIC_ISPR0_ADDR                    0xe000e200
-#define GC_M3_NVIC_ISPR1_ADDR                    0xe000e204
-#define GC_M3_NVIC_ISPR2_ADDR                    0xe000e208
-#define GC_M3_NVIC_ISPR3_ADDR                    0xe000e20c
-#define GC_M3_NVIC_ISPR4_ADDR                    0xe000e210
-#define GC_M3_NVIC_ISPR5_ADDR                    0xe000e214
-#define GC_M3_NVIC_ISPR6_ADDR                    0xe000e218
-#define GC_M3_NVIC_ISPR7_ADDR                    0xe000e21c
-#define GC_M3_NVIC_ICPR0_ADDR                    0xe000e280
-#define GC_M3_NVIC_ICPR1_ADDR                    0xe000e284
-#define GC_M3_NVIC_ICPR2_ADDR                    0xe000e288
-#define GC_M3_NVIC_ICPR3_ADDR                    0xe000e28c
-#define GC_M3_NVIC_ICPR4_ADDR                    0xe000e290
-#define GC_M3_NVIC_ICPR5_ADDR                    0xe000e294
-#define GC_M3_NVIC_ICPR6_ADDR                    0xe000e298
-#define GC_M3_NVIC_ICPR7_ADDR                    0xe000e29c
-#define GC_M3_NVIC_IABR0_ADDR                    0xe000e300
-#define GC_M3_NVIC_IABR1_ADDR                    0xe000e304
-#define GC_M3_NVIC_IABR2_ADDR                    0xe000e308
-#define GC_M3_NVIC_IABR3_ADDR                    0xe000e30c
-#define GC_M3_NVIC_IABR4_ADDR                    0xe000e310
-#define GC_M3_NVIC_IABR5_ADDR                    0xe000e314
-#define GC_M3_NVIC_IABR6_ADDR                    0xe000e318
-#define GC_M3_NVIC_IABR7_ADDR                    0xe000e31c
-#define GC_M3_NVIC_IPR0_ADDR                     0xe000e400
-#define GC_M3_NVIC_IPR1_ADDR                     0xe000e404
-#define GC_M3_NVIC_IPR2_ADDR                     0xe000e408
-#define GC_M3_NVIC_IPR3_ADDR                     0xe000e40c
-#define GC_M3_NVIC_IPR4_ADDR                     0xe000e410
-#define GC_M3_NVIC_IPR5_ADDR                     0xe000e414
-#define GC_M3_NVIC_IPR6_ADDR                     0xe000e418
-#define GC_M3_NVIC_IPR7_ADDR                     0xe000e41c
-#define GC_M3_CPUID_ADDR                         0xe000ed00
-#define GC_M3_ICSR_ADDR                          0xe000ed04
-#define GC_M3_VTOR_ADDR                          0xe000ed08
-#define GC_M3_AIRCR_ADDR                         0xe000ed0c
-#define GC_M3_SCR_ADDR                           0xe000ed10
-#define GC_M3_CCR_ADDR                           0xe000ed14
-#define GC_M3_SHPR1_ADDR                         0xe000ed18
-#define GC_M3_SHPR2_ADDR                         0xe000ed1c
-#define GC_M3_SHPR3_ADDR                         0xe000ed20
-#define GC_M3_SHCSR_ADDR                         0xe000ed24
-#define GC_M3_CFSR_ADDR                          0xe000ed28
-#define GC_M3_HFSR_ADDR                          0xe000ed2c
-#define GC_M3_DFSR_ADDR                          0xe000ed30
-#define GC_M3_MMFAR_ADDR                         0xe000ed34
-#define GC_M3_BFAR_ADDR                          0xe000ed38
-#define GC_M3_AFSR_ADDR                          0xe000ed3c
-#define GC_M3_MPU_TYPE_ADDR                      0xe000ed90
-#define GC_M3_MPU_CTRL_ADDR                      0xe000ed94
-#define GC_M3_MPU_RNR_ADDR                       0xe000ed98
-#define GC_M3_MPU_RBAR_ADDR                      0xe000ed9c
-#define GC_M3_MPU_RASR_ADDR                      0xe000eda0
-#define GC_M3_MPU_RBAR_A1_ADDR                   0xe000eda4
-#define GC_M3_MPU_RASR_A1_ADDR                   0xe000eda8
-#define GC_M3_MPU_RBAR_A2_ADDR                   0xe000edac
-#define GC_M3_MPU_RASR_A2_ADDR                   0xe000edb0
-#define GC_M3_MPU_RBAR_A3_ADDR                   0xe000edb4
-#define GC_M3_MPU_RASR_A3_ADDR                   0xe000edb8
-#define GC_M3_DHCSR_ADDR                         0xe000edf0
-#define GC_M3_DCRSR_ADDR                         0xe000edf4
-#define GC_M3_DCRDR_ADDR                         0xe000edf8
-#define GC_M3_DEMCR_ADDR                         0xe000edfc
-#define GC_M3_TPIU_SSPSR_ADDR                    0xe0040000
-#define GC_M3_TPIU_CSPSR_ADDR                    0xe0040004
-#define GC_M3_TPIU_ACPR_ADDR                     0xe0040010
-#define GC_M3_TPIU_SPPR_ADDR                     0xe00400f0
-#define GC_M3_TPIU_FFSR_ADDR                     0xe0040300
-#define GC_M3_TPIU_FFCR_ADDR                     0xe0040304
-#define GC_M3_TPIU_FSCR_ADDR                     0xe0040308
-#define GC_M3_TRIGGER_ADDR                       0xe0041ee8
-#define GC_M3_ITATBCTR2_ADDR                     0xe0041ef0
-#define GC_M3_ITATBCTR0_ADDR                     0xe0041ef8
-#define GC_M3_ITCTRL_ADDR                        0xe0041f00
-#define GC_M3_CLAIMSET_ADDR                      0xe0041fa0
-#define GC_M3_CLAIMCLR_ADDR                      0xe0041fa4
-#define GC_M3_DEVID_ADDR                         0xe0041fc8
-#define GC_M3_DEVTYPE_ADDR                       0xe0041fcc
-#define GC_M3_HASHER_LOAD_ADDR                   0xe00aa008
-#define GC_M3_HASHER_START_ADDR                  0xe00aa010
-#define GC_M3_HASHER_STOP_ADDR                   0xe00aa018
-#define GC_M3_HASHER_CHECK_ADDR                  0xe00aa020
-#define GC_M3_HASHER_VALUE_ADDR                  0xe00aa028
-#define GC_CAMO_VERSION_CHANGE_LSB               0x0
-#define GC_CAMO_VERSION_CHANGE_MASK              0xffffff
-#define GC_CAMO_VERSION_CHANGE_SIZE              0x18
-#define GC_CAMO_VERSION_CHANGE_DEFAULT           0x14125
-#define GC_CAMO_VERSION_CHANGE_OFFSET            0x8
-#define GC_CAMO_VERSION_REVISION_LSB             0x18
-#define GC_CAMO_VERSION_REVISION_MASK            0xff000000
-#define GC_CAMO_VERSION_REVISION_SIZE            0x8
-#define GC_CAMO_VERSION_REVISION_DEFAULT         0x1
-#define GC_CAMO_VERSION_REVISION_OFFSET          0x8
-#define GC_CRYPTO_VERSION_CHANGE_LSB             0x0
-#define GC_CRYPTO_VERSION_CHANGE_MASK            0xffffff
-#define GC_CRYPTO_VERSION_CHANGE_SIZE            0x18
-#define GC_CRYPTO_VERSION_CHANGE_DEFAULT         0x1424a
-#define GC_CRYPTO_VERSION_CHANGE_OFFSET          0x0
-#define GC_CRYPTO_VERSION_REVISION_LSB           0x18
-#define GC_CRYPTO_VERSION_REVISION_MASK          0xff000000
-#define GC_CRYPTO_VERSION_REVISION_SIZE          0x8
-#define GC_CRYPTO_VERSION_REVISION_DEFAULT       0x1
-#define GC_CRYPTO_VERSION_REVISION_OFFSET        0x0
-#define GC_CRYPTO_CONTROL_RESET_LSB              0x0
-#define GC_CRYPTO_CONTROL_RESET_MASK             0x1
-#define GC_CRYPTO_CONTROL_RESET_SIZE             0x1
-#define GC_CRYPTO_CONTROL_RESET_DEFAULT          0x0
-#define GC_CRYPTO_CONTROL_RESET_OFFSET           0x4
-#define GC_CRYPTO_CONTROL_BREAK_LSB              0x1
-#define GC_CRYPTO_CONTROL_BREAK_MASK             0x2
-#define GC_CRYPTO_CONTROL_BREAK_SIZE             0x1
-#define GC_CRYPTO_CONTROL_BREAK_DEFAULT          0x0
-#define GC_CRYPTO_CONTROL_BREAK_OFFSET           0x4
-#define GC_CRYPTO_CONTROL_RESUME_LSB             0x2
-#define GC_CRYPTO_CONTROL_RESUME_MASK            0x4
-#define GC_CRYPTO_CONTROL_RESUME_SIZE            0x1
-#define GC_CRYPTO_CONTROL_RESUME_DEFAULT         0x0
-#define GC_CRYPTO_CONTROL_RESUME_OFFSET          0x4
-#define GC_CRYPTO_PARITY_CFG_IMEM_SCRUB_EN_LSB   0x0
-#define GC_CRYPTO_PARITY_CFG_IMEM_SCRUB_EN_MASK  0x1
-#define GC_CRYPTO_PARITY_CFG_IMEM_SCRUB_EN_SIZE  0x1
-#define GC_CRYPTO_PARITY_CFG_IMEM_SCRUB_EN_DEFAULT 0x0
-#define GC_CRYPTO_PARITY_CFG_IMEM_SCRUB_EN_OFFSET 0x8
-#define GC_CRYPTO_PARITY_CFG_DMEM_SCRUB_EN_LSB   0x1
-#define GC_CRYPTO_PARITY_CFG_DMEM_SCRUB_EN_MASK  0x2
-#define GC_CRYPTO_PARITY_CFG_DMEM_SCRUB_EN_SIZE  0x1
-#define GC_CRYPTO_PARITY_CFG_DMEM_SCRUB_EN_DEFAULT 0x0
-#define GC_CRYPTO_PARITY_CFG_DMEM_SCRUB_EN_OFFSET 0x8
-#define GC_CRYPTO_PARITY_CFG_IMEM_INV_LSB        0x2
-#define GC_CRYPTO_PARITY_CFG_IMEM_INV_MASK       0x4
-#define GC_CRYPTO_PARITY_CFG_IMEM_INV_SIZE       0x1
-#define GC_CRYPTO_PARITY_CFG_IMEM_INV_DEFAULT    0x0
-#define GC_CRYPTO_PARITY_CFG_IMEM_INV_OFFSET     0x8
-#define GC_CRYPTO_PARITY_CFG_DMEM_INV_LSB        0x3
-#define GC_CRYPTO_PARITY_CFG_DMEM_INV_MASK       0x8
-#define GC_CRYPTO_PARITY_CFG_DMEM_INV_SIZE       0x1
-#define GC_CRYPTO_PARITY_CFG_DMEM_INV_DEFAULT    0x0
-#define GC_CRYPTO_PARITY_CFG_DMEM_INV_OFFSET     0x8
-#define GC_CRYPTO_PARITY_CFG_SCRUB_FREQ_LSB      0x4
-#define GC_CRYPTO_PARITY_CFG_SCRUB_FREQ_MASK     0x30
-#define GC_CRYPTO_PARITY_CFG_SCRUB_FREQ_SIZE     0x2
-#define GC_CRYPTO_PARITY_CFG_SCRUB_FREQ_DEFAULT  0x1
-#define GC_CRYPTO_PARITY_CFG_SCRUB_FREQ_OFFSET   0x8
-#define GC_CRYPTO_PARITY_CFG_DMEM_EN_LSB         0x6
-#define GC_CRYPTO_PARITY_CFG_DMEM_EN_MASK        0x40
-#define GC_CRYPTO_PARITY_CFG_DMEM_EN_SIZE        0x1
-#define GC_CRYPTO_PARITY_CFG_DMEM_EN_DEFAULT     0x0
-#define GC_CRYPTO_PARITY_CFG_DMEM_EN_OFFSET      0x8
-#define GC_CRYPTO_PARITY_CFG_IMEM_EN_LSB         0x7
-#define GC_CRYPTO_PARITY_CFG_IMEM_EN_MASK        0x80
-#define GC_CRYPTO_PARITY_CFG_IMEM_EN_SIZE        0x1
-#define GC_CRYPTO_PARITY_CFG_IMEM_EN_DEFAULT     0x0
-#define GC_CRYPTO_PARITY_CFG_IMEM_EN_OFFSET      0x8
-#define GC_CRYPTO_PARITY_CFG_DRF_EN_LSB          0x8
-#define GC_CRYPTO_PARITY_CFG_DRF_EN_MASK         0x100
-#define GC_CRYPTO_PARITY_CFG_DRF_EN_SIZE         0x1
-#define GC_CRYPTO_PARITY_CFG_DRF_EN_DEFAULT      0x0
-#define GC_CRYPTO_PARITY_CFG_DRF_EN_OFFSET       0x8
-#define GC_CRYPTO_IMEM_SCRUB_RANGE_HIGH_ADDR_LSB 0x0
-#define GC_CRYPTO_IMEM_SCRUB_RANGE_HIGH_ADDR_MASK 0x3ff
-#define GC_CRYPTO_IMEM_SCRUB_RANGE_HIGH_ADDR_SIZE 0xa
-#define GC_CRYPTO_IMEM_SCRUB_RANGE_HIGH_ADDR_DEFAULT 0x3ff
-#define GC_CRYPTO_IMEM_SCRUB_RANGE_HIGH_ADDR_OFFSET 0xc
-#define GC_CRYPTO_IMEM_SCRUB_RANGE_LOW_ADDR_LSB  0xa
-#define GC_CRYPTO_IMEM_SCRUB_RANGE_LOW_ADDR_MASK 0xffc00
-#define GC_CRYPTO_IMEM_SCRUB_RANGE_LOW_ADDR_SIZE 0xa
-#define GC_CRYPTO_IMEM_SCRUB_RANGE_LOW_ADDR_DEFAULT 0x0
-#define GC_CRYPTO_IMEM_SCRUB_RANGE_LOW_ADDR_OFFSET 0xc
-#define GC_CRYPTO_DMEM_SCRUB_RANGE_HIGH_ADDR_LSB 0x0
-#define GC_CRYPTO_DMEM_SCRUB_RANGE_HIGH_ADDR_MASK 0x7f
-#define GC_CRYPTO_DMEM_SCRUB_RANGE_HIGH_ADDR_SIZE 0x7
-#define GC_CRYPTO_DMEM_SCRUB_RANGE_HIGH_ADDR_DEFAULT 0x7f
-#define GC_CRYPTO_DMEM_SCRUB_RANGE_HIGH_ADDR_OFFSET 0x10
-#define GC_CRYPTO_DMEM_SCRUB_RANGE_LOW_ADDR_LSB  0x7
-#define GC_CRYPTO_DMEM_SCRUB_RANGE_LOW_ADDR_MASK 0x3f80
-#define GC_CRYPTO_DMEM_SCRUB_RANGE_LOW_ADDR_SIZE 0x7
-#define GC_CRYPTO_DMEM_SCRUB_RANGE_LOW_ADDR_DEFAULT 0x0
-#define GC_CRYPTO_DMEM_SCRUB_RANGE_LOW_ADDR_OFFSET 0x10
-#define GC_CRYPTO_INT_ENABLE_HOST_CMD_RECV_LSB   0x0
-#define GC_CRYPTO_INT_ENABLE_HOST_CMD_RECV_MASK  0x1
-#define GC_CRYPTO_INT_ENABLE_HOST_CMD_RECV_SIZE  0x1
-#define GC_CRYPTO_INT_ENABLE_HOST_CMD_RECV_DEFAULT 0x0
-#define GC_CRYPTO_INT_ENABLE_HOST_CMD_RECV_OFFSET 0x14
-#define GC_CRYPTO_INT_ENABLE_HOST_CMD_DONE_LSB   0x1
-#define GC_CRYPTO_INT_ENABLE_HOST_CMD_DONE_MASK  0x2
-#define GC_CRYPTO_INT_ENABLE_HOST_CMD_DONE_SIZE  0x1
-#define GC_CRYPTO_INT_ENABLE_HOST_CMD_DONE_DEFAULT 0x0
-#define GC_CRYPTO_INT_ENABLE_HOST_CMD_DONE_OFFSET 0x14
-#define GC_CRYPTO_INT_ENABLE_PC_STACK_OVERFLOW_LSB 0x2
-#define GC_CRYPTO_INT_ENABLE_PC_STACK_OVERFLOW_MASK 0x4
-#define GC_CRYPTO_INT_ENABLE_PC_STACK_OVERFLOW_SIZE 0x1
-#define GC_CRYPTO_INT_ENABLE_PC_STACK_OVERFLOW_DEFAULT 0x0
-#define GC_CRYPTO_INT_ENABLE_PC_STACK_OVERFLOW_OFFSET 0x14
-#define GC_CRYPTO_INT_ENABLE_LOOP_STACK_OVERFLOW_LSB 0x3
-#define GC_CRYPTO_INT_ENABLE_LOOP_STACK_OVERFLOW_MASK 0x8
-#define GC_CRYPTO_INT_ENABLE_LOOP_STACK_OVERFLOW_SIZE 0x1
-#define GC_CRYPTO_INT_ENABLE_LOOP_STACK_OVERFLOW_DEFAULT 0x0
-#define GC_CRYPTO_INT_ENABLE_LOOP_STACK_OVERFLOW_OFFSET 0x14
-#define GC_CRYPTO_INT_ENABLE_LOOP_STACK_UNDERFLOW_LSB 0x4
-#define GC_CRYPTO_INT_ENABLE_LOOP_STACK_UNDERFLOW_MASK 0x10
-#define GC_CRYPTO_INT_ENABLE_LOOP_STACK_UNDERFLOW_SIZE 0x1
-#define GC_CRYPTO_INT_ENABLE_LOOP_STACK_UNDERFLOW_DEFAULT 0x0
-#define GC_CRYPTO_INT_ENABLE_LOOP_STACK_UNDERFLOW_OFFSET 0x14
-#define GC_CRYPTO_INT_ENABLE_DMEM_PTRS_OVERFLOW_LSB 0x5
-#define GC_CRYPTO_INT_ENABLE_DMEM_PTRS_OVERFLOW_MASK 0x20
-#define GC_CRYPTO_INT_ENABLE_DMEM_PTRS_OVERFLOW_SIZE 0x1
-#define GC_CRYPTO_INT_ENABLE_DMEM_PTRS_OVERFLOW_DEFAULT 0x0
-#define GC_CRYPTO_INT_ENABLE_DMEM_PTRS_OVERFLOW_OFFSET 0x14
-#define GC_CRYPTO_INT_ENABLE_DRF_PTRS_OVERFLOW_LSB 0x6
-#define GC_CRYPTO_INT_ENABLE_DRF_PTRS_OVERFLOW_MASK 0x40
-#define GC_CRYPTO_INT_ENABLE_DRF_PTRS_OVERFLOW_SIZE 0x1
-#define GC_CRYPTO_INT_ENABLE_DRF_PTRS_OVERFLOW_DEFAULT 0x0
-#define GC_CRYPTO_INT_ENABLE_DRF_PTRS_OVERFLOW_OFFSET 0x14
-#define GC_CRYPTO_INT_ENABLE_BREAK_LSB           0x7
-#define GC_CRYPTO_INT_ENABLE_BREAK_MASK          0x80
-#define GC_CRYPTO_INT_ENABLE_BREAK_SIZE          0x1
-#define GC_CRYPTO_INT_ENABLE_BREAK_DEFAULT       0x0
-#define GC_CRYPTO_INT_ENABLE_BREAK_OFFSET        0x14
-#define GC_CRYPTO_INT_ENABLE_TRAP_LSB            0x8
-#define GC_CRYPTO_INT_ENABLE_TRAP_MASK           0x100
-#define GC_CRYPTO_INT_ENABLE_TRAP_SIZE           0x1
-#define GC_CRYPTO_INT_ENABLE_TRAP_DEFAULT        0x0
-#define GC_CRYPTO_INT_ENABLE_TRAP_OFFSET         0x14
-#define GC_CRYPTO_INT_ENABLE_DONE_WIPE_SECRETS_LSB 0x9
-#define GC_CRYPTO_INT_ENABLE_DONE_WIPE_SECRETS_MASK 0x200
-#define GC_CRYPTO_INT_ENABLE_DONE_WIPE_SECRETS_SIZE 0x1
-#define GC_CRYPTO_INT_ENABLE_DONE_WIPE_SECRETS_DEFAULT 0x0
-#define GC_CRYPTO_INT_ENABLE_DONE_WIPE_SECRETS_OFFSET 0x14
-#define GC_CRYPTO_INT_ENABLE_PGM_FAULT_LSB       0xa
-#define GC_CRYPTO_INT_ENABLE_PGM_FAULT_MASK      0x400
-#define GC_CRYPTO_INT_ENABLE_PGM_FAULT_SIZE      0x1
-#define GC_CRYPTO_INT_ENABLE_PGM_FAULT_DEFAULT   0x0
-#define GC_CRYPTO_INT_ENABLE_PGM_FAULT_OFFSET    0x14
-#define GC_CRYPTO_INT_ENABLE_MOD_OPERAND_OUT_OF_RANGE_LSB 0xb
-#define GC_CRYPTO_INT_ENABLE_MOD_OPERAND_OUT_OF_RANGE_MASK 0x800
-#define GC_CRYPTO_INT_ENABLE_MOD_OPERAND_OUT_OF_RANGE_SIZE 0x1
-#define GC_CRYPTO_INT_ENABLE_MOD_OPERAND_OUT_OF_RANGE_DEFAULT 0x0
-#define GC_CRYPTO_INT_ENABLE_MOD_OPERAND_OUT_OF_RANGE_OFFSET 0x14
-#define GC_CRYPTO_INT_STATE_HOST_CMD_RECV_LSB    0x0
-#define GC_CRYPTO_INT_STATE_HOST_CMD_RECV_MASK   0x1
-#define GC_CRYPTO_INT_STATE_HOST_CMD_RECV_SIZE   0x1
-#define GC_CRYPTO_INT_STATE_HOST_CMD_RECV_DEFAULT 0x0
-#define GC_CRYPTO_INT_STATE_HOST_CMD_RECV_OFFSET 0x18
-#define GC_CRYPTO_INT_STATE_HOST_CMD_DONE_LSB    0x1
-#define GC_CRYPTO_INT_STATE_HOST_CMD_DONE_MASK   0x2
-#define GC_CRYPTO_INT_STATE_HOST_CMD_DONE_SIZE   0x1
-#define GC_CRYPTO_INT_STATE_HOST_CMD_DONE_DEFAULT 0x0
-#define GC_CRYPTO_INT_STATE_HOST_CMD_DONE_OFFSET 0x18
-#define GC_CRYPTO_INT_STATE_PC_STACK_OVERFLOW_LSB 0x2
-#define GC_CRYPTO_INT_STATE_PC_STACK_OVERFLOW_MASK 0x4
-#define GC_CRYPTO_INT_STATE_PC_STACK_OVERFLOW_SIZE 0x1
-#define GC_CRYPTO_INT_STATE_PC_STACK_OVERFLOW_DEFAULT 0x0
-#define GC_CRYPTO_INT_STATE_PC_STACK_OVERFLOW_OFFSET 0x18
-#define GC_CRYPTO_INT_STATE_LOOP_STACK_OVERFLOW_LSB 0x3
-#define GC_CRYPTO_INT_STATE_LOOP_STACK_OVERFLOW_MASK 0x8
-#define GC_CRYPTO_INT_STATE_LOOP_STACK_OVERFLOW_SIZE 0x1
-#define GC_CRYPTO_INT_STATE_LOOP_STACK_OVERFLOW_DEFAULT 0x0
-#define GC_CRYPTO_INT_STATE_LOOP_STACK_OVERFLOW_OFFSET 0x18
-#define GC_CRYPTO_INT_STATE_LOOP_STACK_UNDERFLOW_LSB 0x4
-#define GC_CRYPTO_INT_STATE_LOOP_STACK_UNDERFLOW_MASK 0x10
-#define GC_CRYPTO_INT_STATE_LOOP_STACK_UNDERFLOW_SIZE 0x1
-#define GC_CRYPTO_INT_STATE_LOOP_STACK_UNDERFLOW_DEFAULT 0x0
-#define GC_CRYPTO_INT_STATE_LOOP_STACK_UNDERFLOW_OFFSET 0x18
-#define GC_CRYPTO_INT_STATE_DMEM_PTRS_OVERFLOW_LSB 0x5
-#define GC_CRYPTO_INT_STATE_DMEM_PTRS_OVERFLOW_MASK 0x20
-#define GC_CRYPTO_INT_STATE_DMEM_PTRS_OVERFLOW_SIZE 0x1
-#define GC_CRYPTO_INT_STATE_DMEM_PTRS_OVERFLOW_DEFAULT 0x0
-#define GC_CRYPTO_INT_STATE_DMEM_PTRS_OVERFLOW_OFFSET 0x18
-#define GC_CRYPTO_INT_STATE_DRF_PTRS_OVERFLOW_LSB 0x6
-#define GC_CRYPTO_INT_STATE_DRF_PTRS_OVERFLOW_MASK 0x40
-#define GC_CRYPTO_INT_STATE_DRF_PTRS_OVERFLOW_SIZE 0x1
-#define GC_CRYPTO_INT_STATE_DRF_PTRS_OVERFLOW_DEFAULT 0x0
-#define GC_CRYPTO_INT_STATE_DRF_PTRS_OVERFLOW_OFFSET 0x18
-#define GC_CRYPTO_INT_STATE_BREAK_LSB            0x7
-#define GC_CRYPTO_INT_STATE_BREAK_MASK           0x80
-#define GC_CRYPTO_INT_STATE_BREAK_SIZE           0x1
-#define GC_CRYPTO_INT_STATE_BREAK_DEFAULT        0x0
-#define GC_CRYPTO_INT_STATE_BREAK_OFFSET         0x18
-#define GC_CRYPTO_INT_STATE_TRAP_LSB             0x8
-#define GC_CRYPTO_INT_STATE_TRAP_MASK            0x100
-#define GC_CRYPTO_INT_STATE_TRAP_SIZE            0x1
-#define GC_CRYPTO_INT_STATE_TRAP_DEFAULT         0x0
-#define GC_CRYPTO_INT_STATE_TRAP_OFFSET          0x18
-#define GC_CRYPTO_INT_STATE_DONE_WIPE_SECRETS_LSB 0x9
-#define GC_CRYPTO_INT_STATE_DONE_WIPE_SECRETS_MASK 0x200
-#define GC_CRYPTO_INT_STATE_DONE_WIPE_SECRETS_SIZE 0x1
-#define GC_CRYPTO_INT_STATE_DONE_WIPE_SECRETS_DEFAULT 0x0
-#define GC_CRYPTO_INT_STATE_DONE_WIPE_SECRETS_OFFSET 0x18
-#define GC_CRYPTO_INT_STATE_PGM_FAULT_LSB        0xa
-#define GC_CRYPTO_INT_STATE_PGM_FAULT_MASK       0x400
-#define GC_CRYPTO_INT_STATE_PGM_FAULT_SIZE       0x1
-#define GC_CRYPTO_INT_STATE_PGM_FAULT_DEFAULT    0x0
-#define GC_CRYPTO_INT_STATE_PGM_FAULT_OFFSET     0x18
-#define GC_CRYPTO_INT_STATE_MOD_OPERAND_OUT_OF_RANGE_LSB 0xb
-#define GC_CRYPTO_INT_STATE_MOD_OPERAND_OUT_OF_RANGE_MASK 0x800
-#define GC_CRYPTO_INT_STATE_MOD_OPERAND_OUT_OF_RANGE_SIZE 0x1
-#define GC_CRYPTO_INT_STATE_MOD_OPERAND_OUT_OF_RANGE_DEFAULT 0x0
-#define GC_CRYPTO_INT_STATE_MOD_OPERAND_OUT_OF_RANGE_OFFSET 0x18
-#define GC_CRYPTO_INT_TEST_HOST_CMD_RECV_LSB     0x0
-#define GC_CRYPTO_INT_TEST_HOST_CMD_RECV_MASK    0x1
-#define GC_CRYPTO_INT_TEST_HOST_CMD_RECV_SIZE    0x1
-#define GC_CRYPTO_INT_TEST_HOST_CMD_RECV_DEFAULT 0x0
-#define GC_CRYPTO_INT_TEST_HOST_CMD_RECV_OFFSET  0x1c
-#define GC_CRYPTO_INT_TEST_HOST_CMD_DONE_LSB     0x1
-#define GC_CRYPTO_INT_TEST_HOST_CMD_DONE_MASK    0x2
-#define GC_CRYPTO_INT_TEST_HOST_CMD_DONE_SIZE    0x1
-#define GC_CRYPTO_INT_TEST_HOST_CMD_DONE_DEFAULT 0x0
-#define GC_CRYPTO_INT_TEST_HOST_CMD_DONE_OFFSET  0x1c
-#define GC_CRYPTO_INT_TEST_PC_STACK_OVERFLOW_LSB 0x2
-#define GC_CRYPTO_INT_TEST_PC_STACK_OVERFLOW_MASK 0x4
-#define GC_CRYPTO_INT_TEST_PC_STACK_OVERFLOW_SIZE 0x1
-#define GC_CRYPTO_INT_TEST_PC_STACK_OVERFLOW_DEFAULT 0x0
-#define GC_CRYPTO_INT_TEST_PC_STACK_OVERFLOW_OFFSET 0x1c
-#define GC_CRYPTO_INT_TEST_LOOP_STACK_OVERFLOW_LSB 0x3
-#define GC_CRYPTO_INT_TEST_LOOP_STACK_OVERFLOW_MASK 0x8
-#define GC_CRYPTO_INT_TEST_LOOP_STACK_OVERFLOW_SIZE 0x1
-#define GC_CRYPTO_INT_TEST_LOOP_STACK_OVERFLOW_DEFAULT 0x0
-#define GC_CRYPTO_INT_TEST_LOOP_STACK_OVERFLOW_OFFSET 0x1c
-#define GC_CRYPTO_INT_TEST_LOOP_STACK_UNDERFLOW_LSB 0x4
-#define GC_CRYPTO_INT_TEST_LOOP_STACK_UNDERFLOW_MASK 0x10
-#define GC_CRYPTO_INT_TEST_LOOP_STACK_UNDERFLOW_SIZE 0x1
-#define GC_CRYPTO_INT_TEST_LOOP_STACK_UNDERFLOW_DEFAULT 0x0
-#define GC_CRYPTO_INT_TEST_LOOP_STACK_UNDERFLOW_OFFSET 0x1c
-#define GC_CRYPTO_INT_TEST_DMEM_PTRS_OVERFLOW_LSB 0x5
-#define GC_CRYPTO_INT_TEST_DMEM_PTRS_OVERFLOW_MASK 0x20
-#define GC_CRYPTO_INT_TEST_DMEM_PTRS_OVERFLOW_SIZE 0x1
-#define GC_CRYPTO_INT_TEST_DMEM_PTRS_OVERFLOW_DEFAULT 0x0
-#define GC_CRYPTO_INT_TEST_DMEM_PTRS_OVERFLOW_OFFSET 0x1c
-#define GC_CRYPTO_INT_TEST_DRF_PTRS_OVERFLOW_LSB 0x6
-#define GC_CRYPTO_INT_TEST_DRF_PTRS_OVERFLOW_MASK 0x40
-#define GC_CRYPTO_INT_TEST_DRF_PTRS_OVERFLOW_SIZE 0x1
-#define GC_CRYPTO_INT_TEST_DRF_PTRS_OVERFLOW_DEFAULT 0x0
-#define GC_CRYPTO_INT_TEST_DRF_PTRS_OVERFLOW_OFFSET 0x1c
-#define GC_CRYPTO_INT_TEST_BREAK_LSB             0x7
-#define GC_CRYPTO_INT_TEST_BREAK_MASK            0x80
-#define GC_CRYPTO_INT_TEST_BREAK_SIZE            0x1
-#define GC_CRYPTO_INT_TEST_BREAK_DEFAULT         0x0
-#define GC_CRYPTO_INT_TEST_BREAK_OFFSET          0x1c
-#define GC_CRYPTO_INT_TEST_TRAP_LSB              0x8
-#define GC_CRYPTO_INT_TEST_TRAP_MASK             0x100
-#define GC_CRYPTO_INT_TEST_TRAP_SIZE             0x1
-#define GC_CRYPTO_INT_TEST_TRAP_DEFAULT          0x0
-#define GC_CRYPTO_INT_TEST_TRAP_OFFSET           0x1c
-#define GC_CRYPTO_INT_TEST_DONE_WIPE_SECRETS_LSB 0x9
-#define GC_CRYPTO_INT_TEST_DONE_WIPE_SECRETS_MASK 0x200
-#define GC_CRYPTO_INT_TEST_DONE_WIPE_SECRETS_SIZE 0x1
-#define GC_CRYPTO_INT_TEST_DONE_WIPE_SECRETS_DEFAULT 0x0
-#define GC_CRYPTO_INT_TEST_DONE_WIPE_SECRETS_OFFSET 0x1c
-#define GC_CRYPTO_INT_TEST_PGM_FAULT_LSB         0xa
-#define GC_CRYPTO_INT_TEST_PGM_FAULT_MASK        0x400
-#define GC_CRYPTO_INT_TEST_PGM_FAULT_SIZE        0x1
-#define GC_CRYPTO_INT_TEST_PGM_FAULT_DEFAULT     0x0
-#define GC_CRYPTO_INT_TEST_PGM_FAULT_OFFSET      0x1c
-#define GC_CRYPTO_INT_TEST_MOD_OPERAND_OUT_OF_RANGE_LSB 0xb
-#define GC_CRYPTO_INT_TEST_MOD_OPERAND_OUT_OF_RANGE_MASK 0x800
-#define GC_CRYPTO_INT_TEST_MOD_OPERAND_OUT_OF_RANGE_SIZE 0x1
-#define GC_CRYPTO_INT_TEST_MOD_OPERAND_OUT_OF_RANGE_DEFAULT 0x0
-#define GC_CRYPTO_INT_TEST_MOD_OPERAND_OUT_OF_RANGE_OFFSET 0x1c
-#define GC_CRYPTO_HOST_CMD_INSTR_LSB             0x0
-#define GC_CRYPTO_HOST_CMD_INSTR_MASK            0xffffffff
-#define GC_CRYPTO_HOST_CMD_INSTR_SIZE            0x20
-#define GC_CRYPTO_HOST_CMD_INSTR_DEFAULT         0xffffffff
-#define GC_CRYPTO_HOST_CMD_INSTR_OFFSET          0x20
-#define GC_CRYPTO_INSTR_PC_LSB                   0x0
-#define GC_CRYPTO_INSTR_PC_MASK                  0x3ff
-#define GC_CRYPTO_INSTR_PC_SIZE                  0xa
-#define GC_CRYPTO_INSTR_PC_DEFAULT               0x0
-#define GC_CRYPTO_INSTR_PC_OFFSET                0x24
-#define GC_CRYPTO_STATUS_STATE_LSB               0x0
-#define GC_CRYPTO_STATUS_STATE_MASK              0x3
-#define GC_CRYPTO_STATUS_STATE_SIZE              0x2
-#define GC_CRYPTO_STATUS_STATE_DEFAULT           0x0
-#define GC_CRYPTO_STATUS_STATE_OFFSET            0x28
-#define GC_CRYPTO_STATUS_L_LSB                   0x2
-#define GC_CRYPTO_STATUS_L_MASK                  0x4
-#define GC_CRYPTO_STATUS_L_SIZE                  0x1
-#define GC_CRYPTO_STATUS_L_DEFAULT               0x0
-#define GC_CRYPTO_STATUS_L_OFFSET                0x28
-#define GC_CRYPTO_STATUS_M_LSB                   0x3
-#define GC_CRYPTO_STATUS_M_MASK                  0x8
-#define GC_CRYPTO_STATUS_M_SIZE                  0x1
-#define GC_CRYPTO_STATUS_M_DEFAULT               0x0
-#define GC_CRYPTO_STATUS_M_OFFSET                0x28
-#define GC_CRYPTO_STATUS_Z_LSB                   0x4
-#define GC_CRYPTO_STATUS_Z_MASK                  0x10
-#define GC_CRYPTO_STATUS_Z_SIZE                  0x1
-#define GC_CRYPTO_STATUS_Z_DEFAULT               0x0
-#define GC_CRYPTO_STATUS_Z_OFFSET                0x28
-#define GC_CRYPTO_STATUS_C_LSB                   0x5
-#define GC_CRYPTO_STATUS_C_MASK                  0x20
-#define GC_CRYPTO_STATUS_C_SIZE                  0x1
-#define GC_CRYPTO_STATUS_C_DEFAULT               0x0
-#define GC_CRYPTO_STATUS_C_OFFSET                0x28
-#define GC_CRYPTO_AUX_CC_L_LSB                   0x0
-#define GC_CRYPTO_AUX_CC_L_MASK                  0x1
-#define GC_CRYPTO_AUX_CC_L_SIZE                  0x1
-#define GC_CRYPTO_AUX_CC_L_DEFAULT               0x0
-#define GC_CRYPTO_AUX_CC_L_OFFSET                0x2c
-#define GC_CRYPTO_AUX_CC_M_LSB                   0x1
-#define GC_CRYPTO_AUX_CC_M_MASK                  0x2
-#define GC_CRYPTO_AUX_CC_M_SIZE                  0x1
-#define GC_CRYPTO_AUX_CC_M_DEFAULT               0x0
-#define GC_CRYPTO_AUX_CC_M_OFFSET                0x2c
-#define GC_CRYPTO_AUX_CC_Z_LSB                   0x2
-#define GC_CRYPTO_AUX_CC_Z_MASK                  0x4
-#define GC_CRYPTO_AUX_CC_Z_SIZE                  0x1
-#define GC_CRYPTO_AUX_CC_Z_DEFAULT               0x0
-#define GC_CRYPTO_AUX_CC_Z_OFFSET                0x2c
-#define GC_CRYPTO_AUX_CC_C_LSB                   0x3
-#define GC_CRYPTO_AUX_CC_C_MASK                  0x8
-#define GC_CRYPTO_AUX_CC_C_SIZE                  0x1
-#define GC_CRYPTO_AUX_CC_C_DEFAULT               0x0
-#define GC_CRYPTO_AUX_CC_C_OFFSET                0x2c
-#define GC_CRYPTO_RAND_STALL_CTL_STALL_EN_LSB    0x0
-#define GC_CRYPTO_RAND_STALL_CTL_STALL_EN_MASK   0x1
-#define GC_CRYPTO_RAND_STALL_CTL_STALL_EN_SIZE   0x1
-#define GC_CRYPTO_RAND_STALL_CTL_STALL_EN_DEFAULT 0x1
-#define GC_CRYPTO_RAND_STALL_CTL_STALL_EN_OFFSET 0x30
-#define GC_CRYPTO_RAND_STALL_CTL_FREQ_LSB        0x1
-#define GC_CRYPTO_RAND_STALL_CTL_FREQ_MASK       0x6
-#define GC_CRYPTO_RAND_STALL_CTL_FREQ_SIZE       0x2
-#define GC_CRYPTO_RAND_STALL_CTL_FREQ_DEFAULT    0x2
-#define GC_CRYPTO_RAND_STALL_CTL_FREQ_OFFSET     0x30
-#define GC_CRYPTO_RAND256_SHIFT_EN_LSB           0x0
-#define GC_CRYPTO_RAND256_SHIFT_EN_MASK          0x1
-#define GC_CRYPTO_RAND256_SHIFT_EN_SIZE          0x1
-#define GC_CRYPTO_RAND256_SHIFT_EN_DEFAULT       0x1
-#define GC_CRYPTO_RAND256_SHIFT_EN_OFFSET        0x34
-#define GC_CRYPTO_PGM_LFSR_SIG_LSB               0x0
-#define GC_CRYPTO_PGM_LFSR_SIG_MASK              0xffffff
-#define GC_CRYPTO_PGM_LFSR_SIG_SIZE              0x18
-#define GC_CRYPTO_PGM_LFSR_SIG_DEFAULT           0x0
-#define GC_CRYPTO_PGM_LFSR_SIG_OFFSET            0x44
-#define GC_CRYPTO_DEBUG_BRKPT0_PC_LSB            0x0
-#define GC_CRYPTO_DEBUG_BRKPT0_PC_MASK           0x3ff
-#define GC_CRYPTO_DEBUG_BRKPT0_PC_SIZE           0xa
-#define GC_CRYPTO_DEBUG_BRKPT0_PC_DEFAULT        0x0
-#define GC_CRYPTO_DEBUG_BRKPT0_PC_OFFSET         0x48
-#define GC_CRYPTO_DEBUG_BRKPT0_EN_LSB            0x1f
-#define GC_CRYPTO_DEBUG_BRKPT0_EN_MASK           0x80000000
-#define GC_CRYPTO_DEBUG_BRKPT0_EN_SIZE           0x1
-#define GC_CRYPTO_DEBUG_BRKPT0_EN_DEFAULT        0x0
-#define GC_CRYPTO_DEBUG_BRKPT0_EN_OFFSET         0x48
-#define GC_CRYPTO_DEBUG_BRKPT1_PC_LSB            0x0
-#define GC_CRYPTO_DEBUG_BRKPT1_PC_MASK           0x3ff
-#define GC_CRYPTO_DEBUG_BRKPT1_PC_SIZE           0xa
-#define GC_CRYPTO_DEBUG_BRKPT1_PC_DEFAULT        0x0
-#define GC_CRYPTO_DEBUG_BRKPT1_PC_OFFSET         0x4c
-#define GC_CRYPTO_DEBUG_BRKPT1_EN_LSB            0x1f
-#define GC_CRYPTO_DEBUG_BRKPT1_EN_MASK           0x80000000
-#define GC_CRYPTO_DEBUG_BRKPT1_EN_SIZE           0x1
-#define GC_CRYPTO_DEBUG_BRKPT1_EN_DEFAULT        0x0
-#define GC_CRYPTO_DEBUG_BRKPT1_EN_OFFSET         0x4c
-#define GC_DMA_VERSION_CHANGE_LSB                0x0
-#define GC_DMA_VERSION_CHANGE_MASK               0xffffff
-#define GC_DMA_VERSION_CHANGE_SIZE               0x18
-#define GC_DMA_VERSION_CHANGE_DEFAULT            0x1424a
-#define GC_DMA_VERSION_CHANGE_OFFSET             0x0
-#define GC_DMA_VERSION_REVISION_LSB              0x18
-#define GC_DMA_VERSION_REVISION_MASK             0xff000000
-#define GC_DMA_VERSION_REVISION_SIZE             0x8
-#define GC_DMA_VERSION_REVISION_DEFAULT          0x1
-#define GC_DMA_VERSION_REVISION_OFFSET           0x0
-#define GC_DMA_INT_ENABLE_INTR_COMPLETE_CHAN_LSB 0x0
-#define GC_DMA_INT_ENABLE_INTR_COMPLETE_CHAN_MASK 0xff
-#define GC_DMA_INT_ENABLE_INTR_COMPLETE_CHAN_SIZE 0x8
-#define GC_DMA_INT_ENABLE_INTR_COMPLETE_CHAN_DEFAULT 0x0
-#define GC_DMA_INT_ENABLE_INTR_COMPLETE_CHAN_OFFSET 0x4
-#define GC_DMA_INT_ENABLE_INTR_PROG_CHAN_LSB     0x8
-#define GC_DMA_INT_ENABLE_INTR_PROG_CHAN_MASK    0xff00
-#define GC_DMA_INT_ENABLE_INTR_PROG_CHAN_SIZE    0x8
-#define GC_DMA_INT_ENABLE_INTR_PROG_CHAN_DEFAULT 0x0
-#define GC_DMA_INT_ENABLE_INTR_PROG_CHAN_OFFSET  0x4
-#define GC_DMA_INT_ENABLE_INTR_TIMEOUT_CHAN_LSB  0x10
-#define GC_DMA_INT_ENABLE_INTR_TIMEOUT_CHAN_MASK 0xff0000
-#define GC_DMA_INT_ENABLE_INTR_TIMEOUT_CHAN_SIZE 0x8
-#define GC_DMA_INT_ENABLE_INTR_TIMEOUT_CHAN_DEFAULT 0x0
-#define GC_DMA_INT_ENABLE_INTR_TIMEOUT_CHAN_OFFSET 0x4
-#define GC_DMA_INT_ENABLE_INTR_ERROR_CHAN_LSB    0x18
-#define GC_DMA_INT_ENABLE_INTR_ERROR_CHAN_MASK   0xff000000
-#define GC_DMA_INT_ENABLE_INTR_ERROR_CHAN_SIZE   0x8
-#define GC_DMA_INT_ENABLE_INTR_ERROR_CHAN_DEFAULT 0x0
-#define GC_DMA_INT_ENABLE_INTR_ERROR_CHAN_OFFSET 0x4
-#define GC_DMA_INT_STATE_INTR_COMPLETE_CHAN_LSB  0x0
-#define GC_DMA_INT_STATE_INTR_COMPLETE_CHAN_MASK 0xff
-#define GC_DMA_INT_STATE_INTR_COMPLETE_CHAN_SIZE 0x8
-#define GC_DMA_INT_STATE_INTR_COMPLETE_CHAN_DEFAULT 0x0
-#define GC_DMA_INT_STATE_INTR_COMPLETE_CHAN_OFFSET 0x8
-#define GC_DMA_INT_STATE_INTR_PROG_CHAN_LSB      0x8
-#define GC_DMA_INT_STATE_INTR_PROG_CHAN_MASK     0xff00
-#define GC_DMA_INT_STATE_INTR_PROG_CHAN_SIZE     0x8
-#define GC_DMA_INT_STATE_INTR_PROG_CHAN_DEFAULT  0x0
-#define GC_DMA_INT_STATE_INTR_PROG_CHAN_OFFSET   0x8
-#define GC_DMA_INT_STATE_INTR_TIMEOUT_CHAN_LSB   0x10
-#define GC_DMA_INT_STATE_INTR_TIMEOUT_CHAN_MASK  0xff0000
-#define GC_DMA_INT_STATE_INTR_TIMEOUT_CHAN_SIZE  0x8
-#define GC_DMA_INT_STATE_INTR_TIMEOUT_CHAN_DEFAULT 0x0
-#define GC_DMA_INT_STATE_INTR_TIMEOUT_CHAN_OFFSET 0x8
-#define GC_DMA_INT_STATE_INTR_ERROR_CHAN_LSB     0x18
-#define GC_DMA_INT_STATE_INTR_ERROR_CHAN_MASK    0xff000000
-#define GC_DMA_INT_STATE_INTR_ERROR_CHAN_SIZE    0x8
-#define GC_DMA_INT_STATE_INTR_ERROR_CHAN_DEFAULT 0x0
-#define GC_DMA_INT_STATE_INTR_ERROR_CHAN_OFFSET  0x8
-#define GC_DMA_INT_TEST_INTR_COMPLETE_CHAN_LSB   0x0
-#define GC_DMA_INT_TEST_INTR_COMPLETE_CHAN_MASK  0xff
-#define GC_DMA_INT_TEST_INTR_COMPLETE_CHAN_SIZE  0x8
-#define GC_DMA_INT_TEST_INTR_COMPLETE_CHAN_DEFAULT 0x0
-#define GC_DMA_INT_TEST_INTR_COMPLETE_CHAN_OFFSET 0xc
-#define GC_DMA_INT_TEST_INTR_PROG_CHAN_LSB       0x8
-#define GC_DMA_INT_TEST_INTR_PROG_CHAN_MASK      0xff00
-#define GC_DMA_INT_TEST_INTR_PROG_CHAN_SIZE      0x8
-#define GC_DMA_INT_TEST_INTR_PROG_CHAN_DEFAULT   0x0
-#define GC_DMA_INT_TEST_INTR_PROG_CHAN_OFFSET    0xc
-#define GC_DMA_INT_TEST_INTR_TIMEOUT_CHAN_LSB    0x10
-#define GC_DMA_INT_TEST_INTR_TIMEOUT_CHAN_MASK   0xff0000
-#define GC_DMA_INT_TEST_INTR_TIMEOUT_CHAN_SIZE   0x8
-#define GC_DMA_INT_TEST_INTR_TIMEOUT_CHAN_DEFAULT 0x0
-#define GC_DMA_INT_TEST_INTR_TIMEOUT_CHAN_OFFSET 0xc
-#define GC_DMA_INT_TEST_INTR_ERROR_CHAN_LSB      0x18
-#define GC_DMA_INT_TEST_INTR_ERROR_CHAN_MASK     0xff000000
-#define GC_DMA_INT_TEST_INTR_ERROR_CHAN_SIZE     0x8
-#define GC_DMA_INT_TEST_INTR_ERROR_CHAN_DEFAULT  0x0
-#define GC_DMA_INT_TEST_INTR_ERROR_CHAN_OFFSET   0xc
-#define GC_DMA_CTRL_CHAN0_CLR_ERROR_LSB          0x0
-#define GC_DMA_CTRL_CHAN0_CLR_ERROR_MASK         0x1
-#define GC_DMA_CTRL_CHAN0_CLR_ERROR_SIZE         0x1
-#define GC_DMA_CTRL_CHAN0_CLR_ERROR_DEFAULT      0x0
-#define GC_DMA_CTRL_CHAN0_CLR_ERROR_OFFSET       0x108
-#define GC_DMA_CTRL_CHAN0_BYTE_NONWORD_MODE_LSB  0x1
-#define GC_DMA_CTRL_CHAN0_BYTE_NONWORD_MODE_MASK 0x2
-#define GC_DMA_CTRL_CHAN0_BYTE_NONWORD_MODE_SIZE 0x1
-#define GC_DMA_CTRL_CHAN0_BYTE_NONWORD_MODE_DEFAULT 0x1
-#define GC_DMA_CTRL_CHAN0_BYTE_NONWORD_MODE_OFFSET 0x108
-#define GC_DMA_CTRL_CHAN0_WRAP_MODE_LSB          0x2
-#define GC_DMA_CTRL_CHAN0_WRAP_MODE_MASK         0x4
-#define GC_DMA_CTRL_CHAN0_WRAP_MODE_SIZE         0x1
-#define GC_DMA_CTRL_CHAN0_WRAP_MODE_DEFAULT      0x0
-#define GC_DMA_CTRL_CHAN0_WRAP_MODE_OFFSET       0x108
-#define GC_DMA_CTRL_CHAN0_SRC_FIFO_MODE_LSB      0x3
-#define GC_DMA_CTRL_CHAN0_SRC_FIFO_MODE_MASK     0x8
-#define GC_DMA_CTRL_CHAN0_SRC_FIFO_MODE_SIZE     0x1
-#define GC_DMA_CTRL_CHAN0_SRC_FIFO_MODE_DEFAULT  0x1
-#define GC_DMA_CTRL_CHAN0_SRC_FIFO_MODE_OFFSET   0x108
-#define GC_DMA_CTRL_CHAN0_DST_FIFO_MODE_LSB      0x4
-#define GC_DMA_CTRL_CHAN0_DST_FIFO_MODE_MASK     0x10
-#define GC_DMA_CTRL_CHAN0_DST_FIFO_MODE_SIZE     0x1
-#define GC_DMA_CTRL_CHAN0_DST_FIFO_MODE_DEFAULT  0x0
-#define GC_DMA_CTRL_CHAN0_DST_FIFO_MODE_OFFSET   0x108
-#define GC_DMA_CTRL_CHAN0_NCHK_EMPTY_LSB         0x5
-#define GC_DMA_CTRL_CHAN0_NCHK_EMPTY_MASK        0x20
-#define GC_DMA_CTRL_CHAN0_NCHK_EMPTY_SIZE        0x1
-#define GC_DMA_CTRL_CHAN0_NCHK_EMPTY_DEFAULT     0x0
-#define GC_DMA_CTRL_CHAN0_NCHK_EMPTY_OFFSET      0x108
-#define GC_DMA_CTRL_CHAN0_NCHK_FULL_LSB          0x6
-#define GC_DMA_CTRL_CHAN0_NCHK_FULL_MASK         0x40
-#define GC_DMA_CTRL_CHAN0_NCHK_FULL_SIZE         0x1
-#define GC_DMA_CTRL_CHAN0_NCHK_FULL_DEFAULT      0x0
-#define GC_DMA_CTRL_CHAN0_NCHK_FULL_OFFSET       0x108
-#define GC_DMA_CTRL_CHAN0_SRC_EMPTY_VECTOR_BIT_LSB 0x7
-#define GC_DMA_CTRL_CHAN0_SRC_EMPTY_VECTOR_BIT_MASK 0x380
-#define GC_DMA_CTRL_CHAN0_SRC_EMPTY_VECTOR_BIT_SIZE 0x3
-#define GC_DMA_CTRL_CHAN0_SRC_EMPTY_VECTOR_BIT_DEFAULT 0x0
-#define GC_DMA_CTRL_CHAN0_SRC_EMPTY_VECTOR_BIT_OFFSET 0x108
-#define GC_DMA_CTRL_CHAN0_DST_FULL_VECTOR_BIT_LSB 0xa
-#define GC_DMA_CTRL_CHAN0_DST_FULL_VECTOR_BIT_MASK 0x1c00
-#define GC_DMA_CTRL_CHAN0_DST_FULL_VECTOR_BIT_SIZE 0x3
-#define GC_DMA_CTRL_CHAN0_DST_FULL_VECTOR_BIT_DEFAULT 0x0
-#define GC_DMA_CTRL_CHAN0_DST_FULL_VECTOR_BIT_OFFSET 0x108
-#define GC_DMA_FSM_STATE_CHAN0_IDLE_LSB          0x0
-#define GC_DMA_FSM_STATE_CHAN0_IDLE_MASK         0x1
-#define GC_DMA_FSM_STATE_CHAN0_IDLE_SIZE         0x1
-#define GC_DMA_FSM_STATE_CHAN0_IDLE_DEFAULT      0x1
-#define GC_DMA_FSM_STATE_CHAN0_IDLE_OFFSET       0x128
-#define GC_DMA_FSM_STATE_CHAN0_BID_READ_LSB      0x1
-#define GC_DMA_FSM_STATE_CHAN0_BID_READ_MASK     0x2
-#define GC_DMA_FSM_STATE_CHAN0_BID_READ_SIZE     0x1
-#define GC_DMA_FSM_STATE_CHAN0_BID_READ_DEFAULT  0x0
-#define GC_DMA_FSM_STATE_CHAN0_BID_READ_OFFSET   0x128
-#define GC_DMA_FSM_STATE_CHAN0_BID_WRITE_LSB     0x2
-#define GC_DMA_FSM_STATE_CHAN0_BID_WRITE_MASK    0x4
-#define GC_DMA_FSM_STATE_CHAN0_BID_WRITE_SIZE    0x1
-#define GC_DMA_FSM_STATE_CHAN0_BID_WRITE_DEFAULT 0x0
-#define GC_DMA_FSM_STATE_CHAN0_BID_WRITE_OFFSET  0x128
-#define GC_DMA_FSM_STATE_CHAN0_CHECK_EMPTY_LSB   0x3
-#define GC_DMA_FSM_STATE_CHAN0_CHECK_EMPTY_MASK  0x8
-#define GC_DMA_FSM_STATE_CHAN0_CHECK_EMPTY_SIZE  0x1
-#define GC_DMA_FSM_STATE_CHAN0_CHECK_EMPTY_DEFAULT 0x0
-#define GC_DMA_FSM_STATE_CHAN0_CHECK_EMPTY_OFFSET 0x128
-#define GC_DMA_FSM_STATE_CHAN0_CHECK_FULL_LSB    0x4
-#define GC_DMA_FSM_STATE_CHAN0_CHECK_FULL_MASK   0x10
-#define GC_DMA_FSM_STATE_CHAN0_CHECK_FULL_SIZE   0x1
-#define GC_DMA_FSM_STATE_CHAN0_CHECK_FULL_DEFAULT 0x0
-#define GC_DMA_FSM_STATE_CHAN0_CHECK_FULL_OFFSET 0x128
-#define GC_DMA_FSM_STATE_CHAN0_READ_LSB          0x5
-#define GC_DMA_FSM_STATE_CHAN0_READ_MASK         0x20
-#define GC_DMA_FSM_STATE_CHAN0_READ_SIZE         0x1
-#define GC_DMA_FSM_STATE_CHAN0_READ_DEFAULT      0x0
-#define GC_DMA_FSM_STATE_CHAN0_READ_OFFSET       0x128
-#define GC_DMA_FSM_STATE_CHAN0_WRITE_LSB         0x6
-#define GC_DMA_FSM_STATE_CHAN0_WRITE_MASK        0x40
-#define GC_DMA_FSM_STATE_CHAN0_WRITE_SIZE        0x1
-#define GC_DMA_FSM_STATE_CHAN0_WRITE_DEFAULT     0x0
-#define GC_DMA_FSM_STATE_CHAN0_WRITE_OFFSET      0x128
-#define GC_DMA_FSM_STATE_CHAN0_ERROR_LSB         0x7
-#define GC_DMA_FSM_STATE_CHAN0_ERROR_MASK        0x80
-#define GC_DMA_FSM_STATE_CHAN0_ERROR_SIZE        0x1
-#define GC_DMA_FSM_STATE_CHAN0_ERROR_DEFAULT     0x0
-#define GC_DMA_FSM_STATE_CHAN0_ERROR_OFFSET      0x128
-#define GC_DMA_FSM_STATE_CHAN0_PAUSE_LSB         0x8
-#define GC_DMA_FSM_STATE_CHAN0_PAUSE_MASK        0x100
-#define GC_DMA_FSM_STATE_CHAN0_PAUSE_SIZE        0x1
-#define GC_DMA_FSM_STATE_CHAN0_PAUSE_DEFAULT     0x0
-#define GC_DMA_FSM_STATE_CHAN0_PAUSE_OFFSET      0x128
-#define GC_DMA_CTRL_CHAN1_CLR_ERROR_LSB          0x0
-#define GC_DMA_CTRL_CHAN1_CLR_ERROR_MASK         0x1
-#define GC_DMA_CTRL_CHAN1_CLR_ERROR_SIZE         0x1
-#define GC_DMA_CTRL_CHAN1_CLR_ERROR_DEFAULT      0x0
-#define GC_DMA_CTRL_CHAN1_CLR_ERROR_OFFSET       0x208
-#define GC_DMA_CTRL_CHAN1_BYTE_NONWORD_MODE_LSB  0x1
-#define GC_DMA_CTRL_CHAN1_BYTE_NONWORD_MODE_MASK 0x2
-#define GC_DMA_CTRL_CHAN1_BYTE_NONWORD_MODE_SIZE 0x1
-#define GC_DMA_CTRL_CHAN1_BYTE_NONWORD_MODE_DEFAULT 0x1
-#define GC_DMA_CTRL_CHAN1_BYTE_NONWORD_MODE_OFFSET 0x208
-#define GC_DMA_CTRL_CHAN1_WRAP_MODE_LSB          0x2
-#define GC_DMA_CTRL_CHAN1_WRAP_MODE_MASK         0x4
-#define GC_DMA_CTRL_CHAN1_WRAP_MODE_SIZE         0x1
-#define GC_DMA_CTRL_CHAN1_WRAP_MODE_DEFAULT      0x0
-#define GC_DMA_CTRL_CHAN1_WRAP_MODE_OFFSET       0x208
-#define GC_DMA_CTRL_CHAN1_SRC_FIFO_MODE_LSB      0x3
-#define GC_DMA_CTRL_CHAN1_SRC_FIFO_MODE_MASK     0x8
-#define GC_DMA_CTRL_CHAN1_SRC_FIFO_MODE_SIZE     0x1
-#define GC_DMA_CTRL_CHAN1_SRC_FIFO_MODE_DEFAULT  0x1
-#define GC_DMA_CTRL_CHAN1_SRC_FIFO_MODE_OFFSET   0x208
-#define GC_DMA_CTRL_CHAN1_DST_FIFO_MODE_LSB      0x4
-#define GC_DMA_CTRL_CHAN1_DST_FIFO_MODE_MASK     0x10
-#define GC_DMA_CTRL_CHAN1_DST_FIFO_MODE_SIZE     0x1
-#define GC_DMA_CTRL_CHAN1_DST_FIFO_MODE_DEFAULT  0x0
-#define GC_DMA_CTRL_CHAN1_DST_FIFO_MODE_OFFSET   0x208
-#define GC_DMA_CTRL_CHAN1_NCHK_EMPTY_LSB         0x5
-#define GC_DMA_CTRL_CHAN1_NCHK_EMPTY_MASK        0x20
-#define GC_DMA_CTRL_CHAN1_NCHK_EMPTY_SIZE        0x1
-#define GC_DMA_CTRL_CHAN1_NCHK_EMPTY_DEFAULT     0x0
-#define GC_DMA_CTRL_CHAN1_NCHK_EMPTY_OFFSET      0x208
-#define GC_DMA_CTRL_CHAN1_NCHK_FULL_LSB          0x6
-#define GC_DMA_CTRL_CHAN1_NCHK_FULL_MASK         0x40
-#define GC_DMA_CTRL_CHAN1_NCHK_FULL_SIZE         0x1
-#define GC_DMA_CTRL_CHAN1_NCHK_FULL_DEFAULT      0x0
-#define GC_DMA_CTRL_CHAN1_NCHK_FULL_OFFSET       0x208
-#define GC_DMA_CTRL_CHAN1_SRC_EMPTY_VECTOR_BIT_LSB 0x7
-#define GC_DMA_CTRL_CHAN1_SRC_EMPTY_VECTOR_BIT_MASK 0x380
-#define GC_DMA_CTRL_CHAN1_SRC_EMPTY_VECTOR_BIT_SIZE 0x3
-#define GC_DMA_CTRL_CHAN1_SRC_EMPTY_VECTOR_BIT_DEFAULT 0x0
-#define GC_DMA_CTRL_CHAN1_SRC_EMPTY_VECTOR_BIT_OFFSET 0x208
-#define GC_DMA_CTRL_CHAN1_DST_FULL_VECTOR_BIT_LSB 0xa
-#define GC_DMA_CTRL_CHAN1_DST_FULL_VECTOR_BIT_MASK 0x1c00
-#define GC_DMA_CTRL_CHAN1_DST_FULL_VECTOR_BIT_SIZE 0x3
-#define GC_DMA_CTRL_CHAN1_DST_FULL_VECTOR_BIT_DEFAULT 0x0
-#define GC_DMA_CTRL_CHAN1_DST_FULL_VECTOR_BIT_OFFSET 0x208
-#define GC_DMA_FSM_STATE_CHAN1_IDLE_LSB          0x0
-#define GC_DMA_FSM_STATE_CHAN1_IDLE_MASK         0x1
-#define GC_DMA_FSM_STATE_CHAN1_IDLE_SIZE         0x1
-#define GC_DMA_FSM_STATE_CHAN1_IDLE_DEFAULT      0x1
-#define GC_DMA_FSM_STATE_CHAN1_IDLE_OFFSET       0x228
-#define GC_DMA_FSM_STATE_CHAN1_BID_READ_LSB      0x1
-#define GC_DMA_FSM_STATE_CHAN1_BID_READ_MASK     0x2
-#define GC_DMA_FSM_STATE_CHAN1_BID_READ_SIZE     0x1
-#define GC_DMA_FSM_STATE_CHAN1_BID_READ_DEFAULT  0x0
-#define GC_DMA_FSM_STATE_CHAN1_BID_READ_OFFSET   0x228
-#define GC_DMA_FSM_STATE_CHAN1_BID_WRITE_LSB     0x2
-#define GC_DMA_FSM_STATE_CHAN1_BID_WRITE_MASK    0x4
-#define GC_DMA_FSM_STATE_CHAN1_BID_WRITE_SIZE    0x1
-#define GC_DMA_FSM_STATE_CHAN1_BID_WRITE_DEFAULT 0x0
-#define GC_DMA_FSM_STATE_CHAN1_BID_WRITE_OFFSET  0x228
-#define GC_DMA_FSM_STATE_CHAN1_CHECK_EMPTY_LSB   0x3
-#define GC_DMA_FSM_STATE_CHAN1_CHECK_EMPTY_MASK  0x8
-#define GC_DMA_FSM_STATE_CHAN1_CHECK_EMPTY_SIZE  0x1
-#define GC_DMA_FSM_STATE_CHAN1_CHECK_EMPTY_DEFAULT 0x0
-#define GC_DMA_FSM_STATE_CHAN1_CHECK_EMPTY_OFFSET 0x228
-#define GC_DMA_FSM_STATE_CHAN1_CHECK_FULL_LSB    0x4
-#define GC_DMA_FSM_STATE_CHAN1_CHECK_FULL_MASK   0x10
-#define GC_DMA_FSM_STATE_CHAN1_CHECK_FULL_SIZE   0x1
-#define GC_DMA_FSM_STATE_CHAN1_CHECK_FULL_DEFAULT 0x0
-#define GC_DMA_FSM_STATE_CHAN1_CHECK_FULL_OFFSET 0x228
-#define GC_DMA_FSM_STATE_CHAN1_READ_LSB          0x5
-#define GC_DMA_FSM_STATE_CHAN1_READ_MASK         0x20
-#define GC_DMA_FSM_STATE_CHAN1_READ_SIZE         0x1
-#define GC_DMA_FSM_STATE_CHAN1_READ_DEFAULT      0x0
-#define GC_DMA_FSM_STATE_CHAN1_READ_OFFSET       0x228
-#define GC_DMA_FSM_STATE_CHAN1_WRITE_LSB         0x6
-#define GC_DMA_FSM_STATE_CHAN1_WRITE_MASK        0x40
-#define GC_DMA_FSM_STATE_CHAN1_WRITE_SIZE        0x1
-#define GC_DMA_FSM_STATE_CHAN1_WRITE_DEFAULT     0x0
-#define GC_DMA_FSM_STATE_CHAN1_WRITE_OFFSET      0x228
-#define GC_DMA_FSM_STATE_CHAN1_ERROR_LSB         0x7
-#define GC_DMA_FSM_STATE_CHAN1_ERROR_MASK        0x80
-#define GC_DMA_FSM_STATE_CHAN1_ERROR_SIZE        0x1
-#define GC_DMA_FSM_STATE_CHAN1_ERROR_DEFAULT     0x0
-#define GC_DMA_FSM_STATE_CHAN1_ERROR_OFFSET      0x228
-#define GC_DMA_FSM_STATE_CHAN1_PAUSE_LSB         0x8
-#define GC_DMA_FSM_STATE_CHAN1_PAUSE_MASK        0x100
-#define GC_DMA_FSM_STATE_CHAN1_PAUSE_SIZE        0x1
-#define GC_DMA_FSM_STATE_CHAN1_PAUSE_DEFAULT     0x0
-#define GC_DMA_FSM_STATE_CHAN1_PAUSE_OFFSET      0x228
-#define GC_DMA_CTRL_CHAN2_CLR_ERROR_LSB          0x0
-#define GC_DMA_CTRL_CHAN2_CLR_ERROR_MASK         0x1
-#define GC_DMA_CTRL_CHAN2_CLR_ERROR_SIZE         0x1
-#define GC_DMA_CTRL_CHAN2_CLR_ERROR_DEFAULT      0x0
-#define GC_DMA_CTRL_CHAN2_CLR_ERROR_OFFSET       0x308
-#define GC_DMA_CTRL_CHAN2_BYTE_NONWORD_MODE_LSB  0x1
-#define GC_DMA_CTRL_CHAN2_BYTE_NONWORD_MODE_MASK 0x2
-#define GC_DMA_CTRL_CHAN2_BYTE_NONWORD_MODE_SIZE 0x1
-#define GC_DMA_CTRL_CHAN2_BYTE_NONWORD_MODE_DEFAULT 0x1
-#define GC_DMA_CTRL_CHAN2_BYTE_NONWORD_MODE_OFFSET 0x308
-#define GC_DMA_CTRL_CHAN2_WRAP_MODE_LSB          0x2
-#define GC_DMA_CTRL_CHAN2_WRAP_MODE_MASK         0x4
-#define GC_DMA_CTRL_CHAN2_WRAP_MODE_SIZE         0x1
-#define GC_DMA_CTRL_CHAN2_WRAP_MODE_DEFAULT      0x0
-#define GC_DMA_CTRL_CHAN2_WRAP_MODE_OFFSET       0x308
-#define GC_DMA_CTRL_CHAN2_SRC_FIFO_MODE_LSB      0x3
-#define GC_DMA_CTRL_CHAN2_SRC_FIFO_MODE_MASK     0x8
-#define GC_DMA_CTRL_CHAN2_SRC_FIFO_MODE_SIZE     0x1
-#define GC_DMA_CTRL_CHAN2_SRC_FIFO_MODE_DEFAULT  0x1
-#define GC_DMA_CTRL_CHAN2_SRC_FIFO_MODE_OFFSET   0x308
-#define GC_DMA_CTRL_CHAN2_DST_FIFO_MODE_LSB      0x4
-#define GC_DMA_CTRL_CHAN2_DST_FIFO_MODE_MASK     0x10
-#define GC_DMA_CTRL_CHAN2_DST_FIFO_MODE_SIZE     0x1
-#define GC_DMA_CTRL_CHAN2_DST_FIFO_MODE_DEFAULT  0x0
-#define GC_DMA_CTRL_CHAN2_DST_FIFO_MODE_OFFSET   0x308
-#define GC_DMA_CTRL_CHAN2_NCHK_EMPTY_LSB         0x5
-#define GC_DMA_CTRL_CHAN2_NCHK_EMPTY_MASK        0x20
-#define GC_DMA_CTRL_CHAN2_NCHK_EMPTY_SIZE        0x1
-#define GC_DMA_CTRL_CHAN2_NCHK_EMPTY_DEFAULT     0x0
-#define GC_DMA_CTRL_CHAN2_NCHK_EMPTY_OFFSET      0x308
-#define GC_DMA_CTRL_CHAN2_NCHK_FULL_LSB          0x6
-#define GC_DMA_CTRL_CHAN2_NCHK_FULL_MASK         0x40
-#define GC_DMA_CTRL_CHAN2_NCHK_FULL_SIZE         0x1
-#define GC_DMA_CTRL_CHAN2_NCHK_FULL_DEFAULT      0x0
-#define GC_DMA_CTRL_CHAN2_NCHK_FULL_OFFSET       0x308
-#define GC_DMA_CTRL_CHAN2_SRC_EMPTY_VECTOR_BIT_LSB 0x7
-#define GC_DMA_CTRL_CHAN2_SRC_EMPTY_VECTOR_BIT_MASK 0x380
-#define GC_DMA_CTRL_CHAN2_SRC_EMPTY_VECTOR_BIT_SIZE 0x3
-#define GC_DMA_CTRL_CHAN2_SRC_EMPTY_VECTOR_BIT_DEFAULT 0x0
-#define GC_DMA_CTRL_CHAN2_SRC_EMPTY_VECTOR_BIT_OFFSET 0x308
-#define GC_DMA_CTRL_CHAN2_DST_FULL_VECTOR_BIT_LSB 0xa
-#define GC_DMA_CTRL_CHAN2_DST_FULL_VECTOR_BIT_MASK 0x1c00
-#define GC_DMA_CTRL_CHAN2_DST_FULL_VECTOR_BIT_SIZE 0x3
-#define GC_DMA_CTRL_CHAN2_DST_FULL_VECTOR_BIT_DEFAULT 0x0
-#define GC_DMA_CTRL_CHAN2_DST_FULL_VECTOR_BIT_OFFSET 0x308
-#define GC_DMA_FSM_STATE_CHAN2_IDLE_LSB          0x0
-#define GC_DMA_FSM_STATE_CHAN2_IDLE_MASK         0x1
-#define GC_DMA_FSM_STATE_CHAN2_IDLE_SIZE         0x1
-#define GC_DMA_FSM_STATE_CHAN2_IDLE_DEFAULT      0x1
-#define GC_DMA_FSM_STATE_CHAN2_IDLE_OFFSET       0x328
-#define GC_DMA_FSM_STATE_CHAN2_BID_READ_LSB      0x1
-#define GC_DMA_FSM_STATE_CHAN2_BID_READ_MASK     0x2
-#define GC_DMA_FSM_STATE_CHAN2_BID_READ_SIZE     0x1
-#define GC_DMA_FSM_STATE_CHAN2_BID_READ_DEFAULT  0x0
-#define GC_DMA_FSM_STATE_CHAN2_BID_READ_OFFSET   0x328
-#define GC_DMA_FSM_STATE_CHAN2_BID_WRITE_LSB     0x2
-#define GC_DMA_FSM_STATE_CHAN2_BID_WRITE_MASK    0x4
-#define GC_DMA_FSM_STATE_CHAN2_BID_WRITE_SIZE    0x1
-#define GC_DMA_FSM_STATE_CHAN2_BID_WRITE_DEFAULT 0x0
-#define GC_DMA_FSM_STATE_CHAN2_BID_WRITE_OFFSET  0x328
-#define GC_DMA_FSM_STATE_CHAN2_CHECK_EMPTY_LSB   0x3
-#define GC_DMA_FSM_STATE_CHAN2_CHECK_EMPTY_MASK  0x8
-#define GC_DMA_FSM_STATE_CHAN2_CHECK_EMPTY_SIZE  0x1
-#define GC_DMA_FSM_STATE_CHAN2_CHECK_EMPTY_DEFAULT 0x0
-#define GC_DMA_FSM_STATE_CHAN2_CHECK_EMPTY_OFFSET 0x328
-#define GC_DMA_FSM_STATE_CHAN2_CHECK_FULL_LSB    0x4
-#define GC_DMA_FSM_STATE_CHAN2_CHECK_FULL_MASK   0x10
-#define GC_DMA_FSM_STATE_CHAN2_CHECK_FULL_SIZE   0x1
-#define GC_DMA_FSM_STATE_CHAN2_CHECK_FULL_DEFAULT 0x0
-#define GC_DMA_FSM_STATE_CHAN2_CHECK_FULL_OFFSET 0x328
-#define GC_DMA_FSM_STATE_CHAN2_READ_LSB          0x5
-#define GC_DMA_FSM_STATE_CHAN2_READ_MASK         0x20
-#define GC_DMA_FSM_STATE_CHAN2_READ_SIZE         0x1
-#define GC_DMA_FSM_STATE_CHAN2_READ_DEFAULT      0x0
-#define GC_DMA_FSM_STATE_CHAN2_READ_OFFSET       0x328
-#define GC_DMA_FSM_STATE_CHAN2_WRITE_LSB         0x6
-#define GC_DMA_FSM_STATE_CHAN2_WRITE_MASK        0x40
-#define GC_DMA_FSM_STATE_CHAN2_WRITE_SIZE        0x1
-#define GC_DMA_FSM_STATE_CHAN2_WRITE_DEFAULT     0x0
-#define GC_DMA_FSM_STATE_CHAN2_WRITE_OFFSET      0x328
-#define GC_DMA_FSM_STATE_CHAN2_ERROR_LSB         0x7
-#define GC_DMA_FSM_STATE_CHAN2_ERROR_MASK        0x80
-#define GC_DMA_FSM_STATE_CHAN2_ERROR_SIZE        0x1
-#define GC_DMA_FSM_STATE_CHAN2_ERROR_DEFAULT     0x0
-#define GC_DMA_FSM_STATE_CHAN2_ERROR_OFFSET      0x328
-#define GC_DMA_FSM_STATE_CHAN2_PAUSE_LSB         0x8
-#define GC_DMA_FSM_STATE_CHAN2_PAUSE_MASK        0x100
-#define GC_DMA_FSM_STATE_CHAN2_PAUSE_SIZE        0x1
-#define GC_DMA_FSM_STATE_CHAN2_PAUSE_DEFAULT     0x0
-#define GC_DMA_FSM_STATE_CHAN2_PAUSE_OFFSET      0x328
-#define GC_DMA_CTRL_CHAN3_CLR_ERROR_LSB          0x0
-#define GC_DMA_CTRL_CHAN3_CLR_ERROR_MASK         0x1
-#define GC_DMA_CTRL_CHAN3_CLR_ERROR_SIZE         0x1
-#define GC_DMA_CTRL_CHAN3_CLR_ERROR_DEFAULT      0x0
-#define GC_DMA_CTRL_CHAN3_CLR_ERROR_OFFSET       0x408
-#define GC_DMA_CTRL_CHAN3_BYTE_NONWORD_MODE_LSB  0x1
-#define GC_DMA_CTRL_CHAN3_BYTE_NONWORD_MODE_MASK 0x2
-#define GC_DMA_CTRL_CHAN3_BYTE_NONWORD_MODE_SIZE 0x1
-#define GC_DMA_CTRL_CHAN3_BYTE_NONWORD_MODE_DEFAULT 0x1
-#define GC_DMA_CTRL_CHAN3_BYTE_NONWORD_MODE_OFFSET 0x408
-#define GC_DMA_CTRL_CHAN3_WRAP_MODE_LSB          0x2
-#define GC_DMA_CTRL_CHAN3_WRAP_MODE_MASK         0x4
-#define GC_DMA_CTRL_CHAN3_WRAP_MODE_SIZE         0x1
-#define GC_DMA_CTRL_CHAN3_WRAP_MODE_DEFAULT      0x0
-#define GC_DMA_CTRL_CHAN3_WRAP_MODE_OFFSET       0x408
-#define GC_DMA_CTRL_CHAN3_SRC_FIFO_MODE_LSB      0x3
-#define GC_DMA_CTRL_CHAN3_SRC_FIFO_MODE_MASK     0x8
-#define GC_DMA_CTRL_CHAN3_SRC_FIFO_MODE_SIZE     0x1
-#define GC_DMA_CTRL_CHAN3_SRC_FIFO_MODE_DEFAULT  0x1
-#define GC_DMA_CTRL_CHAN3_SRC_FIFO_MODE_OFFSET   0x408
-#define GC_DMA_CTRL_CHAN3_DST_FIFO_MODE_LSB      0x4
-#define GC_DMA_CTRL_CHAN3_DST_FIFO_MODE_MASK     0x10
-#define GC_DMA_CTRL_CHAN3_DST_FIFO_MODE_SIZE     0x1
-#define GC_DMA_CTRL_CHAN3_DST_FIFO_MODE_DEFAULT  0x0
-#define GC_DMA_CTRL_CHAN3_DST_FIFO_MODE_OFFSET   0x408
-#define GC_DMA_CTRL_CHAN3_NCHK_EMPTY_LSB         0x5
-#define GC_DMA_CTRL_CHAN3_NCHK_EMPTY_MASK        0x20
-#define GC_DMA_CTRL_CHAN3_NCHK_EMPTY_SIZE        0x1
-#define GC_DMA_CTRL_CHAN3_NCHK_EMPTY_DEFAULT     0x0
-#define GC_DMA_CTRL_CHAN3_NCHK_EMPTY_OFFSET      0x408
-#define GC_DMA_CTRL_CHAN3_NCHK_FULL_LSB          0x6
-#define GC_DMA_CTRL_CHAN3_NCHK_FULL_MASK         0x40
-#define GC_DMA_CTRL_CHAN3_NCHK_FULL_SIZE         0x1
-#define GC_DMA_CTRL_CHAN3_NCHK_FULL_DEFAULT      0x0
-#define GC_DMA_CTRL_CHAN3_NCHK_FULL_OFFSET       0x408
-#define GC_DMA_CTRL_CHAN3_SRC_EMPTY_VECTOR_BIT_LSB 0x7
-#define GC_DMA_CTRL_CHAN3_SRC_EMPTY_VECTOR_BIT_MASK 0x380
-#define GC_DMA_CTRL_CHAN3_SRC_EMPTY_VECTOR_BIT_SIZE 0x3
-#define GC_DMA_CTRL_CHAN3_SRC_EMPTY_VECTOR_BIT_DEFAULT 0x0
-#define GC_DMA_CTRL_CHAN3_SRC_EMPTY_VECTOR_BIT_OFFSET 0x408
-#define GC_DMA_CTRL_CHAN3_DST_FULL_VECTOR_BIT_LSB 0xa
-#define GC_DMA_CTRL_CHAN3_DST_FULL_VECTOR_BIT_MASK 0x1c00
-#define GC_DMA_CTRL_CHAN3_DST_FULL_VECTOR_BIT_SIZE 0x3
-#define GC_DMA_CTRL_CHAN3_DST_FULL_VECTOR_BIT_DEFAULT 0x0
-#define GC_DMA_CTRL_CHAN3_DST_FULL_VECTOR_BIT_OFFSET 0x408
-#define GC_DMA_FSM_STATE_CHAN3_IDLE_LSB          0x0
-#define GC_DMA_FSM_STATE_CHAN3_IDLE_MASK         0x1
-#define GC_DMA_FSM_STATE_CHAN3_IDLE_SIZE         0x1
-#define GC_DMA_FSM_STATE_CHAN3_IDLE_DEFAULT      0x1
-#define GC_DMA_FSM_STATE_CHAN3_IDLE_OFFSET       0x428
-#define GC_DMA_FSM_STATE_CHAN3_BID_READ_LSB      0x1
-#define GC_DMA_FSM_STATE_CHAN3_BID_READ_MASK     0x2
-#define GC_DMA_FSM_STATE_CHAN3_BID_READ_SIZE     0x1
-#define GC_DMA_FSM_STATE_CHAN3_BID_READ_DEFAULT  0x0
-#define GC_DMA_FSM_STATE_CHAN3_BID_READ_OFFSET   0x428
-#define GC_DMA_FSM_STATE_CHAN3_BID_WRITE_LSB     0x2
-#define GC_DMA_FSM_STATE_CHAN3_BID_WRITE_MASK    0x4
-#define GC_DMA_FSM_STATE_CHAN3_BID_WRITE_SIZE    0x1
-#define GC_DMA_FSM_STATE_CHAN3_BID_WRITE_DEFAULT 0x0
-#define GC_DMA_FSM_STATE_CHAN3_BID_WRITE_OFFSET  0x428
-#define GC_DMA_FSM_STATE_CHAN3_CHECK_EMPTY_LSB   0x3
-#define GC_DMA_FSM_STATE_CHAN3_CHECK_EMPTY_MASK  0x8
-#define GC_DMA_FSM_STATE_CHAN3_CHECK_EMPTY_SIZE  0x1
-#define GC_DMA_FSM_STATE_CHAN3_CHECK_EMPTY_DEFAULT 0x0
-#define GC_DMA_FSM_STATE_CHAN3_CHECK_EMPTY_OFFSET 0x428
-#define GC_DMA_FSM_STATE_CHAN3_CHECK_FULL_LSB    0x4
-#define GC_DMA_FSM_STATE_CHAN3_CHECK_FULL_MASK   0x10
-#define GC_DMA_FSM_STATE_CHAN3_CHECK_FULL_SIZE   0x1
-#define GC_DMA_FSM_STATE_CHAN3_CHECK_FULL_DEFAULT 0x0
-#define GC_DMA_FSM_STATE_CHAN3_CHECK_FULL_OFFSET 0x428
-#define GC_DMA_FSM_STATE_CHAN3_READ_LSB          0x5
-#define GC_DMA_FSM_STATE_CHAN3_READ_MASK         0x20
-#define GC_DMA_FSM_STATE_CHAN3_READ_SIZE         0x1
-#define GC_DMA_FSM_STATE_CHAN3_READ_DEFAULT      0x0
-#define GC_DMA_FSM_STATE_CHAN3_READ_OFFSET       0x428
-#define GC_DMA_FSM_STATE_CHAN3_WRITE_LSB         0x6
-#define GC_DMA_FSM_STATE_CHAN3_WRITE_MASK        0x40
-#define GC_DMA_FSM_STATE_CHAN3_WRITE_SIZE        0x1
-#define GC_DMA_FSM_STATE_CHAN3_WRITE_DEFAULT     0x0
-#define GC_DMA_FSM_STATE_CHAN3_WRITE_OFFSET      0x428
-#define GC_DMA_FSM_STATE_CHAN3_ERROR_LSB         0x7
-#define GC_DMA_FSM_STATE_CHAN3_ERROR_MASK        0x80
-#define GC_DMA_FSM_STATE_CHAN3_ERROR_SIZE        0x1
-#define GC_DMA_FSM_STATE_CHAN3_ERROR_DEFAULT     0x0
-#define GC_DMA_FSM_STATE_CHAN3_ERROR_OFFSET      0x428
-#define GC_DMA_FSM_STATE_CHAN3_PAUSE_LSB         0x8
-#define GC_DMA_FSM_STATE_CHAN3_PAUSE_MASK        0x100
-#define GC_DMA_FSM_STATE_CHAN3_PAUSE_SIZE        0x1
-#define GC_DMA_FSM_STATE_CHAN3_PAUSE_DEFAULT     0x0
-#define GC_DMA_FSM_STATE_CHAN3_PAUSE_OFFSET      0x428
-#define GC_DMA_CTRL_CHAN4_CLR_ERROR_LSB          0x0
-#define GC_DMA_CTRL_CHAN4_CLR_ERROR_MASK         0x1
-#define GC_DMA_CTRL_CHAN4_CLR_ERROR_SIZE         0x1
-#define GC_DMA_CTRL_CHAN4_CLR_ERROR_DEFAULT      0x0
-#define GC_DMA_CTRL_CHAN4_CLR_ERROR_OFFSET       0x508
-#define GC_DMA_CTRL_CHAN4_BYTE_NONWORD_MODE_LSB  0x1
-#define GC_DMA_CTRL_CHAN4_BYTE_NONWORD_MODE_MASK 0x2
-#define GC_DMA_CTRL_CHAN4_BYTE_NONWORD_MODE_SIZE 0x1
-#define GC_DMA_CTRL_CHAN4_BYTE_NONWORD_MODE_DEFAULT 0x1
-#define GC_DMA_CTRL_CHAN4_BYTE_NONWORD_MODE_OFFSET 0x508
-#define GC_DMA_CTRL_CHAN4_WRAP_MODE_LSB          0x2
-#define GC_DMA_CTRL_CHAN4_WRAP_MODE_MASK         0x4
-#define GC_DMA_CTRL_CHAN4_WRAP_MODE_SIZE         0x1
-#define GC_DMA_CTRL_CHAN4_WRAP_MODE_DEFAULT      0x0
-#define GC_DMA_CTRL_CHAN4_WRAP_MODE_OFFSET       0x508
-#define GC_DMA_CTRL_CHAN4_SRC_FIFO_MODE_LSB      0x3
-#define GC_DMA_CTRL_CHAN4_SRC_FIFO_MODE_MASK     0x8
-#define GC_DMA_CTRL_CHAN4_SRC_FIFO_MODE_SIZE     0x1
-#define GC_DMA_CTRL_CHAN4_SRC_FIFO_MODE_DEFAULT  0x1
-#define GC_DMA_CTRL_CHAN4_SRC_FIFO_MODE_OFFSET   0x508
-#define GC_DMA_CTRL_CHAN4_DST_FIFO_MODE_LSB      0x4
-#define GC_DMA_CTRL_CHAN4_DST_FIFO_MODE_MASK     0x10
-#define GC_DMA_CTRL_CHAN4_DST_FIFO_MODE_SIZE     0x1
-#define GC_DMA_CTRL_CHAN4_DST_FIFO_MODE_DEFAULT  0x0
-#define GC_DMA_CTRL_CHAN4_DST_FIFO_MODE_OFFSET   0x508
-#define GC_DMA_CTRL_CHAN4_NCHK_EMPTY_LSB         0x5
-#define GC_DMA_CTRL_CHAN4_NCHK_EMPTY_MASK        0x20
-#define GC_DMA_CTRL_CHAN4_NCHK_EMPTY_SIZE        0x1
-#define GC_DMA_CTRL_CHAN4_NCHK_EMPTY_DEFAULT     0x0
-#define GC_DMA_CTRL_CHAN4_NCHK_EMPTY_OFFSET      0x508
-#define GC_DMA_CTRL_CHAN4_NCHK_FULL_LSB          0x6
-#define GC_DMA_CTRL_CHAN4_NCHK_FULL_MASK         0x40
-#define GC_DMA_CTRL_CHAN4_NCHK_FULL_SIZE         0x1
-#define GC_DMA_CTRL_CHAN4_NCHK_FULL_DEFAULT      0x0
-#define GC_DMA_CTRL_CHAN4_NCHK_FULL_OFFSET       0x508
-#define GC_DMA_CTRL_CHAN4_SRC_EMPTY_VECTOR_BIT_LSB 0x7
-#define GC_DMA_CTRL_CHAN4_SRC_EMPTY_VECTOR_BIT_MASK 0x380
-#define GC_DMA_CTRL_CHAN4_SRC_EMPTY_VECTOR_BIT_SIZE 0x3
-#define GC_DMA_CTRL_CHAN4_SRC_EMPTY_VECTOR_BIT_DEFAULT 0x0
-#define GC_DMA_CTRL_CHAN4_SRC_EMPTY_VECTOR_BIT_OFFSET 0x508
-#define GC_DMA_CTRL_CHAN4_DST_FULL_VECTOR_BIT_LSB 0xa
-#define GC_DMA_CTRL_CHAN4_DST_FULL_VECTOR_BIT_MASK 0x1c00
-#define GC_DMA_CTRL_CHAN4_DST_FULL_VECTOR_BIT_SIZE 0x3
-#define GC_DMA_CTRL_CHAN4_DST_FULL_VECTOR_BIT_DEFAULT 0x0
-#define GC_DMA_CTRL_CHAN4_DST_FULL_VECTOR_BIT_OFFSET 0x508
-#define GC_DMA_FSM_STATE_CHAN4_IDLE_LSB          0x0
-#define GC_DMA_FSM_STATE_CHAN4_IDLE_MASK         0x1
-#define GC_DMA_FSM_STATE_CHAN4_IDLE_SIZE         0x1
-#define GC_DMA_FSM_STATE_CHAN4_IDLE_DEFAULT      0x1
-#define GC_DMA_FSM_STATE_CHAN4_IDLE_OFFSET       0x528
-#define GC_DMA_FSM_STATE_CHAN4_BID_READ_LSB      0x1
-#define GC_DMA_FSM_STATE_CHAN4_BID_READ_MASK     0x2
-#define GC_DMA_FSM_STATE_CHAN4_BID_READ_SIZE     0x1
-#define GC_DMA_FSM_STATE_CHAN4_BID_READ_DEFAULT  0x0
-#define GC_DMA_FSM_STATE_CHAN4_BID_READ_OFFSET   0x528
-#define GC_DMA_FSM_STATE_CHAN4_BID_WRITE_LSB     0x2
-#define GC_DMA_FSM_STATE_CHAN4_BID_WRITE_MASK    0x4
-#define GC_DMA_FSM_STATE_CHAN4_BID_WRITE_SIZE    0x1
-#define GC_DMA_FSM_STATE_CHAN4_BID_WRITE_DEFAULT 0x0
-#define GC_DMA_FSM_STATE_CHAN4_BID_WRITE_OFFSET  0x528
-#define GC_DMA_FSM_STATE_CHAN4_CHECK_EMPTY_LSB   0x3
-#define GC_DMA_FSM_STATE_CHAN4_CHECK_EMPTY_MASK  0x8
-#define GC_DMA_FSM_STATE_CHAN4_CHECK_EMPTY_SIZE  0x1
-#define GC_DMA_FSM_STATE_CHAN4_CHECK_EMPTY_DEFAULT 0x0
-#define GC_DMA_FSM_STATE_CHAN4_CHECK_EMPTY_OFFSET 0x528
-#define GC_DMA_FSM_STATE_CHAN4_CHECK_FULL_LSB    0x4
-#define GC_DMA_FSM_STATE_CHAN4_CHECK_FULL_MASK   0x10
-#define GC_DMA_FSM_STATE_CHAN4_CHECK_FULL_SIZE   0x1
-#define GC_DMA_FSM_STATE_CHAN4_CHECK_FULL_DEFAULT 0x0
-#define GC_DMA_FSM_STATE_CHAN4_CHECK_FULL_OFFSET 0x528
-#define GC_DMA_FSM_STATE_CHAN4_READ_LSB          0x5
-#define GC_DMA_FSM_STATE_CHAN4_READ_MASK         0x20
-#define GC_DMA_FSM_STATE_CHAN4_READ_SIZE         0x1
-#define GC_DMA_FSM_STATE_CHAN4_READ_DEFAULT      0x0
-#define GC_DMA_FSM_STATE_CHAN4_READ_OFFSET       0x528
-#define GC_DMA_FSM_STATE_CHAN4_WRITE_LSB         0x6
-#define GC_DMA_FSM_STATE_CHAN4_WRITE_MASK        0x40
-#define GC_DMA_FSM_STATE_CHAN4_WRITE_SIZE        0x1
-#define GC_DMA_FSM_STATE_CHAN4_WRITE_DEFAULT     0x0
-#define GC_DMA_FSM_STATE_CHAN4_WRITE_OFFSET      0x528
-#define GC_DMA_FSM_STATE_CHAN4_ERROR_LSB         0x7
-#define GC_DMA_FSM_STATE_CHAN4_ERROR_MASK        0x80
-#define GC_DMA_FSM_STATE_CHAN4_ERROR_SIZE        0x1
-#define GC_DMA_FSM_STATE_CHAN4_ERROR_DEFAULT     0x0
-#define GC_DMA_FSM_STATE_CHAN4_ERROR_OFFSET      0x528
-#define GC_DMA_FSM_STATE_CHAN4_PAUSE_LSB         0x8
-#define GC_DMA_FSM_STATE_CHAN4_PAUSE_MASK        0x100
-#define GC_DMA_FSM_STATE_CHAN4_PAUSE_SIZE        0x1
-#define GC_DMA_FSM_STATE_CHAN4_PAUSE_DEFAULT     0x0
-#define GC_DMA_FSM_STATE_CHAN4_PAUSE_OFFSET      0x528
-#define GC_DMA_CTRL_CHAN5_CLR_ERROR_LSB          0x0
-#define GC_DMA_CTRL_CHAN5_CLR_ERROR_MASK         0x1
-#define GC_DMA_CTRL_CHAN5_CLR_ERROR_SIZE         0x1
-#define GC_DMA_CTRL_CHAN5_CLR_ERROR_DEFAULT      0x0
-#define GC_DMA_CTRL_CHAN5_CLR_ERROR_OFFSET       0x608
-#define GC_DMA_CTRL_CHAN5_BYTE_NONWORD_MODE_LSB  0x1
-#define GC_DMA_CTRL_CHAN5_BYTE_NONWORD_MODE_MASK 0x2
-#define GC_DMA_CTRL_CHAN5_BYTE_NONWORD_MODE_SIZE 0x1
-#define GC_DMA_CTRL_CHAN5_BYTE_NONWORD_MODE_DEFAULT 0x1
-#define GC_DMA_CTRL_CHAN5_BYTE_NONWORD_MODE_OFFSET 0x608
-#define GC_DMA_CTRL_CHAN5_WRAP_MODE_LSB          0x2
-#define GC_DMA_CTRL_CHAN5_WRAP_MODE_MASK         0x4
-#define GC_DMA_CTRL_CHAN5_WRAP_MODE_SIZE         0x1
-#define GC_DMA_CTRL_CHAN5_WRAP_MODE_DEFAULT      0x0
-#define GC_DMA_CTRL_CHAN5_WRAP_MODE_OFFSET       0x608
-#define GC_DMA_CTRL_CHAN5_SRC_FIFO_MODE_LSB      0x3
-#define GC_DMA_CTRL_CHAN5_SRC_FIFO_MODE_MASK     0x8
-#define GC_DMA_CTRL_CHAN5_SRC_FIFO_MODE_SIZE     0x1
-#define GC_DMA_CTRL_CHAN5_SRC_FIFO_MODE_DEFAULT  0x1
-#define GC_DMA_CTRL_CHAN5_SRC_FIFO_MODE_OFFSET   0x608
-#define GC_DMA_CTRL_CHAN5_DST_FIFO_MODE_LSB      0x4
-#define GC_DMA_CTRL_CHAN5_DST_FIFO_MODE_MASK     0x10
-#define GC_DMA_CTRL_CHAN5_DST_FIFO_MODE_SIZE     0x1
-#define GC_DMA_CTRL_CHAN5_DST_FIFO_MODE_DEFAULT  0x0
-#define GC_DMA_CTRL_CHAN5_DST_FIFO_MODE_OFFSET   0x608
-#define GC_DMA_CTRL_CHAN5_NCHK_EMPTY_LSB         0x5
-#define GC_DMA_CTRL_CHAN5_NCHK_EMPTY_MASK        0x20
-#define GC_DMA_CTRL_CHAN5_NCHK_EMPTY_SIZE        0x1
-#define GC_DMA_CTRL_CHAN5_NCHK_EMPTY_DEFAULT     0x0
-#define GC_DMA_CTRL_CHAN5_NCHK_EMPTY_OFFSET      0x608
-#define GC_DMA_CTRL_CHAN5_NCHK_FULL_LSB          0x6
-#define GC_DMA_CTRL_CHAN5_NCHK_FULL_MASK         0x40
-#define GC_DMA_CTRL_CHAN5_NCHK_FULL_SIZE         0x1
-#define GC_DMA_CTRL_CHAN5_NCHK_FULL_DEFAULT      0x0
-#define GC_DMA_CTRL_CHAN5_NCHK_FULL_OFFSET       0x608
-#define GC_DMA_CTRL_CHAN5_SRC_EMPTY_VECTOR_BIT_LSB 0x7
-#define GC_DMA_CTRL_CHAN5_SRC_EMPTY_VECTOR_BIT_MASK 0x380
-#define GC_DMA_CTRL_CHAN5_SRC_EMPTY_VECTOR_BIT_SIZE 0x3
-#define GC_DMA_CTRL_CHAN5_SRC_EMPTY_VECTOR_BIT_DEFAULT 0x0
-#define GC_DMA_CTRL_CHAN5_SRC_EMPTY_VECTOR_BIT_OFFSET 0x608
-#define GC_DMA_CTRL_CHAN5_DST_FULL_VECTOR_BIT_LSB 0xa
-#define GC_DMA_CTRL_CHAN5_DST_FULL_VECTOR_BIT_MASK 0x1c00
-#define GC_DMA_CTRL_CHAN5_DST_FULL_VECTOR_BIT_SIZE 0x3
-#define GC_DMA_CTRL_CHAN5_DST_FULL_VECTOR_BIT_DEFAULT 0x0
-#define GC_DMA_CTRL_CHAN5_DST_FULL_VECTOR_BIT_OFFSET 0x608
-#define GC_DMA_FSM_STATE_CHAN5_IDLE_LSB          0x0
-#define GC_DMA_FSM_STATE_CHAN5_IDLE_MASK         0x1
-#define GC_DMA_FSM_STATE_CHAN5_IDLE_SIZE         0x1
-#define GC_DMA_FSM_STATE_CHAN5_IDLE_DEFAULT      0x1
-#define GC_DMA_FSM_STATE_CHAN5_IDLE_OFFSET       0x628
-#define GC_DMA_FSM_STATE_CHAN5_BID_READ_LSB      0x1
-#define GC_DMA_FSM_STATE_CHAN5_BID_READ_MASK     0x2
-#define GC_DMA_FSM_STATE_CHAN5_BID_READ_SIZE     0x1
-#define GC_DMA_FSM_STATE_CHAN5_BID_READ_DEFAULT  0x0
-#define GC_DMA_FSM_STATE_CHAN5_BID_READ_OFFSET   0x628
-#define GC_DMA_FSM_STATE_CHAN5_BID_WRITE_LSB     0x2
-#define GC_DMA_FSM_STATE_CHAN5_BID_WRITE_MASK    0x4
-#define GC_DMA_FSM_STATE_CHAN5_BID_WRITE_SIZE    0x1
-#define GC_DMA_FSM_STATE_CHAN5_BID_WRITE_DEFAULT 0x0
-#define GC_DMA_FSM_STATE_CHAN5_BID_WRITE_OFFSET  0x628
-#define GC_DMA_FSM_STATE_CHAN5_CHECK_EMPTY_LSB   0x3
-#define GC_DMA_FSM_STATE_CHAN5_CHECK_EMPTY_MASK  0x8
-#define GC_DMA_FSM_STATE_CHAN5_CHECK_EMPTY_SIZE  0x1
-#define GC_DMA_FSM_STATE_CHAN5_CHECK_EMPTY_DEFAULT 0x0
-#define GC_DMA_FSM_STATE_CHAN5_CHECK_EMPTY_OFFSET 0x628
-#define GC_DMA_FSM_STATE_CHAN5_CHECK_FULL_LSB    0x4
-#define GC_DMA_FSM_STATE_CHAN5_CHECK_FULL_MASK   0x10
-#define GC_DMA_FSM_STATE_CHAN5_CHECK_FULL_SIZE   0x1
-#define GC_DMA_FSM_STATE_CHAN5_CHECK_FULL_DEFAULT 0x0
-#define GC_DMA_FSM_STATE_CHAN5_CHECK_FULL_OFFSET 0x628
-#define GC_DMA_FSM_STATE_CHAN5_READ_LSB          0x5
-#define GC_DMA_FSM_STATE_CHAN5_READ_MASK         0x20
-#define GC_DMA_FSM_STATE_CHAN5_READ_SIZE         0x1
-#define GC_DMA_FSM_STATE_CHAN5_READ_DEFAULT      0x0
-#define GC_DMA_FSM_STATE_CHAN5_READ_OFFSET       0x628
-#define GC_DMA_FSM_STATE_CHAN5_WRITE_LSB         0x6
-#define GC_DMA_FSM_STATE_CHAN5_WRITE_MASK        0x40
-#define GC_DMA_FSM_STATE_CHAN5_WRITE_SIZE        0x1
-#define GC_DMA_FSM_STATE_CHAN5_WRITE_DEFAULT     0x0
-#define GC_DMA_FSM_STATE_CHAN5_WRITE_OFFSET      0x628
-#define GC_DMA_FSM_STATE_CHAN5_ERROR_LSB         0x7
-#define GC_DMA_FSM_STATE_CHAN5_ERROR_MASK        0x80
-#define GC_DMA_FSM_STATE_CHAN5_ERROR_SIZE        0x1
-#define GC_DMA_FSM_STATE_CHAN5_ERROR_DEFAULT     0x0
-#define GC_DMA_FSM_STATE_CHAN5_ERROR_OFFSET      0x628
-#define GC_DMA_FSM_STATE_CHAN5_PAUSE_LSB         0x8
-#define GC_DMA_FSM_STATE_CHAN5_PAUSE_MASK        0x100
-#define GC_DMA_FSM_STATE_CHAN5_PAUSE_SIZE        0x1
-#define GC_DMA_FSM_STATE_CHAN5_PAUSE_DEFAULT     0x0
-#define GC_DMA_FSM_STATE_CHAN5_PAUSE_OFFSET      0x628
-#define GC_DMA_CTRL_CHAN6_CLR_ERROR_LSB          0x0
-#define GC_DMA_CTRL_CHAN6_CLR_ERROR_MASK         0x1
-#define GC_DMA_CTRL_CHAN6_CLR_ERROR_SIZE         0x1
-#define GC_DMA_CTRL_CHAN6_CLR_ERROR_DEFAULT      0x0
-#define GC_DMA_CTRL_CHAN6_CLR_ERROR_OFFSET       0x708
-#define GC_DMA_CTRL_CHAN6_BYTE_NONWORD_MODE_LSB  0x1
-#define GC_DMA_CTRL_CHAN6_BYTE_NONWORD_MODE_MASK 0x2
-#define GC_DMA_CTRL_CHAN6_BYTE_NONWORD_MODE_SIZE 0x1
-#define GC_DMA_CTRL_CHAN6_BYTE_NONWORD_MODE_DEFAULT 0x1
-#define GC_DMA_CTRL_CHAN6_BYTE_NONWORD_MODE_OFFSET 0x708
-#define GC_DMA_CTRL_CHAN6_WRAP_MODE_LSB          0x2
-#define GC_DMA_CTRL_CHAN6_WRAP_MODE_MASK         0x4
-#define GC_DMA_CTRL_CHAN6_WRAP_MODE_SIZE         0x1
-#define GC_DMA_CTRL_CHAN6_WRAP_MODE_DEFAULT      0x0
-#define GC_DMA_CTRL_CHAN6_WRAP_MODE_OFFSET       0x708
-#define GC_DMA_CTRL_CHAN6_SRC_FIFO_MODE_LSB      0x3
-#define GC_DMA_CTRL_CHAN6_SRC_FIFO_MODE_MASK     0x8
-#define GC_DMA_CTRL_CHAN6_SRC_FIFO_MODE_SIZE     0x1
-#define GC_DMA_CTRL_CHAN6_SRC_FIFO_MODE_DEFAULT  0x1
-#define GC_DMA_CTRL_CHAN6_SRC_FIFO_MODE_OFFSET   0x708
-#define GC_DMA_CTRL_CHAN6_DST_FIFO_MODE_LSB      0x4
-#define GC_DMA_CTRL_CHAN6_DST_FIFO_MODE_MASK     0x10
-#define GC_DMA_CTRL_CHAN6_DST_FIFO_MODE_SIZE     0x1
-#define GC_DMA_CTRL_CHAN6_DST_FIFO_MODE_DEFAULT  0x0
-#define GC_DMA_CTRL_CHAN6_DST_FIFO_MODE_OFFSET   0x708
-#define GC_DMA_CTRL_CHAN6_NCHK_EMPTY_LSB         0x5
-#define GC_DMA_CTRL_CHAN6_NCHK_EMPTY_MASK        0x20
-#define GC_DMA_CTRL_CHAN6_NCHK_EMPTY_SIZE        0x1
-#define GC_DMA_CTRL_CHAN6_NCHK_EMPTY_DEFAULT     0x0
-#define GC_DMA_CTRL_CHAN6_NCHK_EMPTY_OFFSET      0x708
-#define GC_DMA_CTRL_CHAN6_NCHK_FULL_LSB          0x6
-#define GC_DMA_CTRL_CHAN6_NCHK_FULL_MASK         0x40
-#define GC_DMA_CTRL_CHAN6_NCHK_FULL_SIZE         0x1
-#define GC_DMA_CTRL_CHAN6_NCHK_FULL_DEFAULT      0x0
-#define GC_DMA_CTRL_CHAN6_NCHK_FULL_OFFSET       0x708
-#define GC_DMA_CTRL_CHAN6_SRC_EMPTY_VECTOR_BIT_LSB 0x7
-#define GC_DMA_CTRL_CHAN6_SRC_EMPTY_VECTOR_BIT_MASK 0x380
-#define GC_DMA_CTRL_CHAN6_SRC_EMPTY_VECTOR_BIT_SIZE 0x3
-#define GC_DMA_CTRL_CHAN6_SRC_EMPTY_VECTOR_BIT_DEFAULT 0x0
-#define GC_DMA_CTRL_CHAN6_SRC_EMPTY_VECTOR_BIT_OFFSET 0x708
-#define GC_DMA_CTRL_CHAN6_DST_FULL_VECTOR_BIT_LSB 0xa
-#define GC_DMA_CTRL_CHAN6_DST_FULL_VECTOR_BIT_MASK 0x1c00
-#define GC_DMA_CTRL_CHAN6_DST_FULL_VECTOR_BIT_SIZE 0x3
-#define GC_DMA_CTRL_CHAN6_DST_FULL_VECTOR_BIT_DEFAULT 0x0
-#define GC_DMA_CTRL_CHAN6_DST_FULL_VECTOR_BIT_OFFSET 0x708
-#define GC_DMA_FSM_STATE_CHAN6_IDLE_LSB          0x0
-#define GC_DMA_FSM_STATE_CHAN6_IDLE_MASK         0x1
-#define GC_DMA_FSM_STATE_CHAN6_IDLE_SIZE         0x1
-#define GC_DMA_FSM_STATE_CHAN6_IDLE_DEFAULT      0x1
-#define GC_DMA_FSM_STATE_CHAN6_IDLE_OFFSET       0x728
-#define GC_DMA_FSM_STATE_CHAN6_BID_READ_LSB      0x1
-#define GC_DMA_FSM_STATE_CHAN6_BID_READ_MASK     0x2
-#define GC_DMA_FSM_STATE_CHAN6_BID_READ_SIZE     0x1
-#define GC_DMA_FSM_STATE_CHAN6_BID_READ_DEFAULT  0x0
-#define GC_DMA_FSM_STATE_CHAN6_BID_READ_OFFSET   0x728
-#define GC_DMA_FSM_STATE_CHAN6_BID_WRITE_LSB     0x2
-#define GC_DMA_FSM_STATE_CHAN6_BID_WRITE_MASK    0x4
-#define GC_DMA_FSM_STATE_CHAN6_BID_WRITE_SIZE    0x1
-#define GC_DMA_FSM_STATE_CHAN6_BID_WRITE_DEFAULT 0x0
-#define GC_DMA_FSM_STATE_CHAN6_BID_WRITE_OFFSET  0x728
-#define GC_DMA_FSM_STATE_CHAN6_CHECK_EMPTY_LSB   0x3
-#define GC_DMA_FSM_STATE_CHAN6_CHECK_EMPTY_MASK  0x8
-#define GC_DMA_FSM_STATE_CHAN6_CHECK_EMPTY_SIZE  0x1
-#define GC_DMA_FSM_STATE_CHAN6_CHECK_EMPTY_DEFAULT 0x0
-#define GC_DMA_FSM_STATE_CHAN6_CHECK_EMPTY_OFFSET 0x728
-#define GC_DMA_FSM_STATE_CHAN6_CHECK_FULL_LSB    0x4
-#define GC_DMA_FSM_STATE_CHAN6_CHECK_FULL_MASK   0x10
-#define GC_DMA_FSM_STATE_CHAN6_CHECK_FULL_SIZE   0x1
-#define GC_DMA_FSM_STATE_CHAN6_CHECK_FULL_DEFAULT 0x0
-#define GC_DMA_FSM_STATE_CHAN6_CHECK_FULL_OFFSET 0x728
-#define GC_DMA_FSM_STATE_CHAN6_READ_LSB          0x5
-#define GC_DMA_FSM_STATE_CHAN6_READ_MASK         0x20
-#define GC_DMA_FSM_STATE_CHAN6_READ_SIZE         0x1
-#define GC_DMA_FSM_STATE_CHAN6_READ_DEFAULT      0x0
-#define GC_DMA_FSM_STATE_CHAN6_READ_OFFSET       0x728
-#define GC_DMA_FSM_STATE_CHAN6_WRITE_LSB         0x6
-#define GC_DMA_FSM_STATE_CHAN6_WRITE_MASK        0x40
-#define GC_DMA_FSM_STATE_CHAN6_WRITE_SIZE        0x1
-#define GC_DMA_FSM_STATE_CHAN6_WRITE_DEFAULT     0x0
-#define GC_DMA_FSM_STATE_CHAN6_WRITE_OFFSET      0x728
-#define GC_DMA_FSM_STATE_CHAN6_ERROR_LSB         0x7
-#define GC_DMA_FSM_STATE_CHAN6_ERROR_MASK        0x80
-#define GC_DMA_FSM_STATE_CHAN6_ERROR_SIZE        0x1
-#define GC_DMA_FSM_STATE_CHAN6_ERROR_DEFAULT     0x0
-#define GC_DMA_FSM_STATE_CHAN6_ERROR_OFFSET      0x728
-#define GC_DMA_FSM_STATE_CHAN6_PAUSE_LSB         0x8
-#define GC_DMA_FSM_STATE_CHAN6_PAUSE_MASK        0x100
-#define GC_DMA_FSM_STATE_CHAN6_PAUSE_SIZE        0x1
-#define GC_DMA_FSM_STATE_CHAN6_PAUSE_DEFAULT     0x0
-#define GC_DMA_FSM_STATE_CHAN6_PAUSE_OFFSET      0x728
-#define GC_DMA_CTRL_CHAN7_CLR_ERROR_LSB          0x0
-#define GC_DMA_CTRL_CHAN7_CLR_ERROR_MASK         0x1
-#define GC_DMA_CTRL_CHAN7_CLR_ERROR_SIZE         0x1
-#define GC_DMA_CTRL_CHAN7_CLR_ERROR_DEFAULT      0x0
-#define GC_DMA_CTRL_CHAN7_CLR_ERROR_OFFSET       0x808
-#define GC_DMA_CTRL_CHAN7_BYTE_NONWORD_MODE_LSB  0x1
-#define GC_DMA_CTRL_CHAN7_BYTE_NONWORD_MODE_MASK 0x2
-#define GC_DMA_CTRL_CHAN7_BYTE_NONWORD_MODE_SIZE 0x1
-#define GC_DMA_CTRL_CHAN7_BYTE_NONWORD_MODE_DEFAULT 0x1
-#define GC_DMA_CTRL_CHAN7_BYTE_NONWORD_MODE_OFFSET 0x808
-#define GC_DMA_CTRL_CHAN7_WRAP_MODE_LSB          0x2
-#define GC_DMA_CTRL_CHAN7_WRAP_MODE_MASK         0x4
-#define GC_DMA_CTRL_CHAN7_WRAP_MODE_SIZE         0x1
-#define GC_DMA_CTRL_CHAN7_WRAP_MODE_DEFAULT      0x0
-#define GC_DMA_CTRL_CHAN7_WRAP_MODE_OFFSET       0x808
-#define GC_DMA_CTRL_CHAN7_SRC_FIFO_MODE_LSB      0x3
-#define GC_DMA_CTRL_CHAN7_SRC_FIFO_MODE_MASK     0x8
-#define GC_DMA_CTRL_CHAN7_SRC_FIFO_MODE_SIZE     0x1
-#define GC_DMA_CTRL_CHAN7_SRC_FIFO_MODE_DEFAULT  0x1
-#define GC_DMA_CTRL_CHAN7_SRC_FIFO_MODE_OFFSET   0x808
-#define GC_DMA_CTRL_CHAN7_DST_FIFO_MODE_LSB      0x4
-#define GC_DMA_CTRL_CHAN7_DST_FIFO_MODE_MASK     0x10
-#define GC_DMA_CTRL_CHAN7_DST_FIFO_MODE_SIZE     0x1
-#define GC_DMA_CTRL_CHAN7_DST_FIFO_MODE_DEFAULT  0x0
-#define GC_DMA_CTRL_CHAN7_DST_FIFO_MODE_OFFSET   0x808
-#define GC_DMA_CTRL_CHAN7_NCHK_EMPTY_LSB         0x5
-#define GC_DMA_CTRL_CHAN7_NCHK_EMPTY_MASK        0x20
-#define GC_DMA_CTRL_CHAN7_NCHK_EMPTY_SIZE        0x1
-#define GC_DMA_CTRL_CHAN7_NCHK_EMPTY_DEFAULT     0x0
-#define GC_DMA_CTRL_CHAN7_NCHK_EMPTY_OFFSET      0x808
-#define GC_DMA_CTRL_CHAN7_NCHK_FULL_LSB          0x6
-#define GC_DMA_CTRL_CHAN7_NCHK_FULL_MASK         0x40
-#define GC_DMA_CTRL_CHAN7_NCHK_FULL_SIZE         0x1
-#define GC_DMA_CTRL_CHAN7_NCHK_FULL_DEFAULT      0x0
-#define GC_DMA_CTRL_CHAN7_NCHK_FULL_OFFSET       0x808
-#define GC_DMA_CTRL_CHAN7_SRC_EMPTY_VECTOR_BIT_LSB 0x7
-#define GC_DMA_CTRL_CHAN7_SRC_EMPTY_VECTOR_BIT_MASK 0x380
-#define GC_DMA_CTRL_CHAN7_SRC_EMPTY_VECTOR_BIT_SIZE 0x3
-#define GC_DMA_CTRL_CHAN7_SRC_EMPTY_VECTOR_BIT_DEFAULT 0x0
-#define GC_DMA_CTRL_CHAN7_SRC_EMPTY_VECTOR_BIT_OFFSET 0x808
-#define GC_DMA_CTRL_CHAN7_DST_FULL_VECTOR_BIT_LSB 0xa
-#define GC_DMA_CTRL_CHAN7_DST_FULL_VECTOR_BIT_MASK 0x1c00
-#define GC_DMA_CTRL_CHAN7_DST_FULL_VECTOR_BIT_SIZE 0x3
-#define GC_DMA_CTRL_CHAN7_DST_FULL_VECTOR_BIT_DEFAULT 0x0
-#define GC_DMA_CTRL_CHAN7_DST_FULL_VECTOR_BIT_OFFSET 0x808
-#define GC_DMA_FSM_STATE_CHAN7_IDLE_LSB          0x0
-#define GC_DMA_FSM_STATE_CHAN7_IDLE_MASK         0x1
-#define GC_DMA_FSM_STATE_CHAN7_IDLE_SIZE         0x1
-#define GC_DMA_FSM_STATE_CHAN7_IDLE_DEFAULT      0x1
-#define GC_DMA_FSM_STATE_CHAN7_IDLE_OFFSET       0x828
-#define GC_DMA_FSM_STATE_CHAN7_BID_READ_LSB      0x1
-#define GC_DMA_FSM_STATE_CHAN7_BID_READ_MASK     0x2
-#define GC_DMA_FSM_STATE_CHAN7_BID_READ_SIZE     0x1
-#define GC_DMA_FSM_STATE_CHAN7_BID_READ_DEFAULT  0x0
-#define GC_DMA_FSM_STATE_CHAN7_BID_READ_OFFSET   0x828
-#define GC_DMA_FSM_STATE_CHAN7_BID_WRITE_LSB     0x2
-#define GC_DMA_FSM_STATE_CHAN7_BID_WRITE_MASK    0x4
-#define GC_DMA_FSM_STATE_CHAN7_BID_WRITE_SIZE    0x1
-#define GC_DMA_FSM_STATE_CHAN7_BID_WRITE_DEFAULT 0x0
-#define GC_DMA_FSM_STATE_CHAN7_BID_WRITE_OFFSET  0x828
-#define GC_DMA_FSM_STATE_CHAN7_CHECK_EMPTY_LSB   0x3
-#define GC_DMA_FSM_STATE_CHAN7_CHECK_EMPTY_MASK  0x8
-#define GC_DMA_FSM_STATE_CHAN7_CHECK_EMPTY_SIZE  0x1
-#define GC_DMA_FSM_STATE_CHAN7_CHECK_EMPTY_DEFAULT 0x0
-#define GC_DMA_FSM_STATE_CHAN7_CHECK_EMPTY_OFFSET 0x828
-#define GC_DMA_FSM_STATE_CHAN7_CHECK_FULL_LSB    0x4
-#define GC_DMA_FSM_STATE_CHAN7_CHECK_FULL_MASK   0x10
-#define GC_DMA_FSM_STATE_CHAN7_CHECK_FULL_SIZE   0x1
-#define GC_DMA_FSM_STATE_CHAN7_CHECK_FULL_DEFAULT 0x0
-#define GC_DMA_FSM_STATE_CHAN7_CHECK_FULL_OFFSET 0x828
-#define GC_DMA_FSM_STATE_CHAN7_READ_LSB          0x5
-#define GC_DMA_FSM_STATE_CHAN7_READ_MASK         0x20
-#define GC_DMA_FSM_STATE_CHAN7_READ_SIZE         0x1
-#define GC_DMA_FSM_STATE_CHAN7_READ_DEFAULT      0x0
-#define GC_DMA_FSM_STATE_CHAN7_READ_OFFSET       0x828
-#define GC_DMA_FSM_STATE_CHAN7_WRITE_LSB         0x6
-#define GC_DMA_FSM_STATE_CHAN7_WRITE_MASK        0x40
-#define GC_DMA_FSM_STATE_CHAN7_WRITE_SIZE        0x1
-#define GC_DMA_FSM_STATE_CHAN7_WRITE_DEFAULT     0x0
-#define GC_DMA_FSM_STATE_CHAN7_WRITE_OFFSET      0x828
-#define GC_DMA_FSM_STATE_CHAN7_ERROR_LSB         0x7
-#define GC_DMA_FSM_STATE_CHAN7_ERROR_MASK        0x80
-#define GC_DMA_FSM_STATE_CHAN7_ERROR_SIZE        0x1
-#define GC_DMA_FSM_STATE_CHAN7_ERROR_DEFAULT     0x0
-#define GC_DMA_FSM_STATE_CHAN7_ERROR_OFFSET      0x828
-#define GC_DMA_FSM_STATE_CHAN7_PAUSE_LSB         0x8
-#define GC_DMA_FSM_STATE_CHAN7_PAUSE_MASK        0x100
-#define GC_DMA_FSM_STATE_CHAN7_PAUSE_SIZE        0x1
-#define GC_DMA_FSM_STATE_CHAN7_PAUSE_DEFAULT     0x0
-#define GC_DMA_FSM_STATE_CHAN7_PAUSE_OFFSET      0x828
-#define GC_FLASH_FSH_TRANS_OFFSET_LSB            0x0
-#define GC_FLASH_FSH_TRANS_OFFSET_MASK           0xffff
-#define GC_FLASH_FSH_TRANS_OFFSET_SIZE           0x10
-#define GC_FLASH_FSH_TRANS_OFFSET_DEFAULT        0x0
-#define GC_FLASH_FSH_TRANS_OFFSET_OFFSET         0x8
-#define GC_FLASH_FSH_TRANS_MAINB_LSB             0x10
-#define GC_FLASH_FSH_TRANS_MAINB_MASK            0x10000
-#define GC_FLASH_FSH_TRANS_MAINB_SIZE            0x1
-#define GC_FLASH_FSH_TRANS_MAINB_DEFAULT         0x0
-#define GC_FLASH_FSH_TRANS_MAINB_OFFSET          0x8
-#define GC_FLASH_FSH_TRANS_SIZE_LSB              0x11
-#define GC_FLASH_FSH_TRANS_SIZE_MASK             0x3e0000
-#define GC_FLASH_FSH_TRANS_SIZE_SIZE             0x5
-#define GC_FLASH_FSH_TRANS_SIZE_DEFAULT          0x0
-#define GC_FLASH_FSH_TRANS_SIZE_OFFSET           0x8
-#define GC_FLASH_FSH_PROTECT_INFO1_ERASE_LSB     0x0
-#define GC_FLASH_FSH_PROTECT_INFO1_ERASE_MASK    0x1
-#define GC_FLASH_FSH_PROTECT_INFO1_ERASE_SIZE    0x1
-#define GC_FLASH_FSH_PROTECT_INFO1_ERASE_DEFAULT 0x0
-#define GC_FLASH_FSH_PROTECT_INFO1_ERASE_OFFSET  0xc
-#define GC_FLASH_FSH_PROTECT_INFO1_PROG_REGION0_LSB 0x1
-#define GC_FLASH_FSH_PROTECT_INFO1_PROG_REGION0_MASK 0x2
-#define GC_FLASH_FSH_PROTECT_INFO1_PROG_REGION0_SIZE 0x1
-#define GC_FLASH_FSH_PROTECT_INFO1_PROG_REGION0_DEFAULT 0x0
-#define GC_FLASH_FSH_PROTECT_INFO1_PROG_REGION0_OFFSET 0xc
-#define GC_FLASH_FSH_PROTECT_INFO1_PROG_REGION1_LSB 0x2
-#define GC_FLASH_FSH_PROTECT_INFO1_PROG_REGION1_MASK 0x4
-#define GC_FLASH_FSH_PROTECT_INFO1_PROG_REGION1_SIZE 0x1
-#define GC_FLASH_FSH_PROTECT_INFO1_PROG_REGION1_DEFAULT 0x0
-#define GC_FLASH_FSH_PROTECT_INFO1_PROG_REGION1_OFFSET 0xc
-#define GC_FLASH_FSH_PROTECT_INFO1_PROG_REGION2_LSB 0x3
-#define GC_FLASH_FSH_PROTECT_INFO1_PROG_REGION2_MASK 0x8
-#define GC_FLASH_FSH_PROTECT_INFO1_PROG_REGION2_SIZE 0x1
-#define GC_FLASH_FSH_PROTECT_INFO1_PROG_REGION2_DEFAULT 0x0
-#define GC_FLASH_FSH_PROTECT_INFO1_PROG_REGION2_OFFSET 0xc
-#define GC_FLASH_FSH_PROTECT_INFO1_PROG_REGION3_LSB 0x4
-#define GC_FLASH_FSH_PROTECT_INFO1_PROG_REGION3_MASK 0x10
-#define GC_FLASH_FSH_PROTECT_INFO1_PROG_REGION3_SIZE 0x1
-#define GC_FLASH_FSH_PROTECT_INFO1_PROG_REGION3_DEFAULT 0x0
-#define GC_FLASH_FSH_PROTECT_INFO1_PROG_REGION3_OFFSET 0xc
-#define GC_FLASH_FSH_PROTECT_INFO1_READ_REGION0_LSB 0x5
-#define GC_FLASH_FSH_PROTECT_INFO1_READ_REGION0_MASK 0x20
-#define GC_FLASH_FSH_PROTECT_INFO1_READ_REGION0_SIZE 0x1
-#define GC_FLASH_FSH_PROTECT_INFO1_READ_REGION0_DEFAULT 0x0
-#define GC_FLASH_FSH_PROTECT_INFO1_READ_REGION0_OFFSET 0xc
-#define GC_FLASH_FSH_PROTECT_INFO1_READ_REGION1_LSB 0x6
-#define GC_FLASH_FSH_PROTECT_INFO1_READ_REGION1_MASK 0x40
-#define GC_FLASH_FSH_PROTECT_INFO1_READ_REGION1_SIZE 0x1
-#define GC_FLASH_FSH_PROTECT_INFO1_READ_REGION1_DEFAULT 0x0
-#define GC_FLASH_FSH_PROTECT_INFO1_READ_REGION1_OFFSET 0xc
-#define GC_FLASH_FSH_PROTECT_INFO1_READ_REGION2_LSB 0x7
-#define GC_FLASH_FSH_PROTECT_INFO1_READ_REGION2_MASK 0x80
-#define GC_FLASH_FSH_PROTECT_INFO1_READ_REGION2_SIZE 0x1
-#define GC_FLASH_FSH_PROTECT_INFO1_READ_REGION2_DEFAULT 0x0
-#define GC_FLASH_FSH_PROTECT_INFO1_READ_REGION2_OFFSET 0xc
-#define GC_FLASH_FSH_PROTECT_INFO1_READ_REGION3_LSB 0x8
-#define GC_FLASH_FSH_PROTECT_INFO1_READ_REGION3_MASK 0x100
-#define GC_FLASH_FSH_PROTECT_INFO1_READ_REGION3_SIZE 0x1
-#define GC_FLASH_FSH_PROTECT_INFO1_READ_REGION3_DEFAULT 0x0
-#define GC_FLASH_FSH_PROTECT_INFO1_READ_REGION3_OFFSET 0xc
-#define GC_FLASH_FSH_ICTRL_EDONE_LSB             0x0
-#define GC_FLASH_FSH_ICTRL_EDONE_MASK            0x1
-#define GC_FLASH_FSH_ICTRL_EDONE_SIZE            0x1
-#define GC_FLASH_FSH_ICTRL_EDONE_DEFAULT         0x0
-#define GC_FLASH_FSH_ICTRL_EDONE_OFFSET          0x14
-#define GC_FLASH_FSH_ICTRL_PDONE_LSB             0x1
-#define GC_FLASH_FSH_ICTRL_PDONE_MASK            0x2
-#define GC_FLASH_FSH_ICTRL_PDONE_SIZE            0x1
-#define GC_FLASH_FSH_ICTRL_PDONE_DEFAULT         0x0
-#define GC_FLASH_FSH_ICTRL_PDONE_OFFSET          0x14
-#define GC_FLASH_FSH_ISTATE_EDONE_LSB            0x0
-#define GC_FLASH_FSH_ISTATE_EDONE_MASK           0x1
-#define GC_FLASH_FSH_ISTATE_EDONE_SIZE           0x1
-#define GC_FLASH_FSH_ISTATE_EDONE_DEFAULT        0x0
-#define GC_FLASH_FSH_ISTATE_EDONE_OFFSET         0x18
-#define GC_FLASH_FSH_ISTATE_PDONE_LSB            0x1
-#define GC_FLASH_FSH_ISTATE_PDONE_MASK           0x2
-#define GC_FLASH_FSH_ISTATE_PDONE_SIZE           0x1
-#define GC_FLASH_FSH_ISTATE_PDONE_DEFAULT        0x0
-#define GC_FLASH_FSH_ISTATE_PDONE_OFFSET         0x18
-#define GC_FLASH_FSH_OVRD_SIGVAL_IFREN_LSB       0x0
-#define GC_FLASH_FSH_OVRD_SIGVAL_IFREN_MASK      0x1
-#define GC_FLASH_FSH_OVRD_SIGVAL_IFREN_SIZE      0x1
-#define GC_FLASH_FSH_OVRD_SIGVAL_IFREN_DEFAULT   0x0
-#define GC_FLASH_FSH_OVRD_SIGVAL_IFREN_OFFSET    0x2c
-#define GC_FLASH_FSH_OVRD_SIGVAL_IFREN1_LSB      0x1
-#define GC_FLASH_FSH_OVRD_SIGVAL_IFREN1_MASK     0x2
-#define GC_FLASH_FSH_OVRD_SIGVAL_IFREN1_SIZE     0x1
-#define GC_FLASH_FSH_OVRD_SIGVAL_IFREN1_DEFAULT  0x0
-#define GC_FLASH_FSH_OVRD_SIGVAL_IFREN1_OFFSET   0x2c
-#define GC_FLASH_FSH_OVRD_SIGVAL_REDEN_LSB       0x2
-#define GC_FLASH_FSH_OVRD_SIGVAL_REDEN_MASK      0x4
-#define GC_FLASH_FSH_OVRD_SIGVAL_REDEN_SIZE      0x1
-#define GC_FLASH_FSH_OVRD_SIGVAL_REDEN_DEFAULT   0x0
-#define GC_FLASH_FSH_OVRD_SIGVAL_REDEN_OFFSET    0x2c
-#define GC_FLASH_FSH_OVRD_SIGVAL_TMR_LSB         0x3
-#define GC_FLASH_FSH_OVRD_SIGVAL_TMR_MASK        0x8
-#define GC_FLASH_FSH_OVRD_SIGVAL_TMR_SIZE        0x1
-#define GC_FLASH_FSH_OVRD_SIGVAL_TMR_DEFAULT     0x0
-#define GC_FLASH_FSH_OVRD_SIGVAL_TMR_OFFSET      0x2c
-#define GC_FLASH_FSH_OVRD_SIGVAL_XE_LSB          0x4
-#define GC_FLASH_FSH_OVRD_SIGVAL_XE_MASK         0x10
-#define GC_FLASH_FSH_OVRD_SIGVAL_XE_SIZE         0x1
-#define GC_FLASH_FSH_OVRD_SIGVAL_XE_DEFAULT      0x0
-#define GC_FLASH_FSH_OVRD_SIGVAL_XE_OFFSET       0x2c
-#define GC_FLASH_FSH_OVRD_SIGVAL_YE_LSB          0x5
-#define GC_FLASH_FSH_OVRD_SIGVAL_YE_MASK         0x20
-#define GC_FLASH_FSH_OVRD_SIGVAL_YE_SIZE         0x1
-#define GC_FLASH_FSH_OVRD_SIGVAL_YE_DEFAULT      0x0
-#define GC_FLASH_FSH_OVRD_SIGVAL_YE_OFFSET       0x2c
-#define GC_FLASH_FSH_OVRD_SIGVAL_SE_LSB          0x6
-#define GC_FLASH_FSH_OVRD_SIGVAL_SE_MASK         0x40
-#define GC_FLASH_FSH_OVRD_SIGVAL_SE_SIZE         0x1
-#define GC_FLASH_FSH_OVRD_SIGVAL_SE_DEFAULT      0x0
-#define GC_FLASH_FSH_OVRD_SIGVAL_SE_OFFSET       0x2c
-#define GC_FLASH_FSH_OVRD_SIGVAL_ERASE_LSB       0x7
-#define GC_FLASH_FSH_OVRD_SIGVAL_ERASE_MASK      0x80
-#define GC_FLASH_FSH_OVRD_SIGVAL_ERASE_SIZE      0x1
-#define GC_FLASH_FSH_OVRD_SIGVAL_ERASE_DEFAULT   0x0
-#define GC_FLASH_FSH_OVRD_SIGVAL_ERASE_OFFSET    0x2c
-#define GC_FLASH_FSH_OVRD_SIGVAL_PROG_LSB        0x8
-#define GC_FLASH_FSH_OVRD_SIGVAL_PROG_MASK       0x100
-#define GC_FLASH_FSH_OVRD_SIGVAL_PROG_SIZE       0x1
-#define GC_FLASH_FSH_OVRD_SIGVAL_PROG_DEFAULT    0x0
-#define GC_FLASH_FSH_OVRD_SIGVAL_PROG_OFFSET     0x2c
-#define GC_FLASH_FSH_OVRD_SIGVAL_MAS1_LSB        0x9
-#define GC_FLASH_FSH_OVRD_SIGVAL_MAS1_MASK       0x200
-#define GC_FLASH_FSH_OVRD_SIGVAL_MAS1_SIZE       0x1
-#define GC_FLASH_FSH_OVRD_SIGVAL_MAS1_DEFAULT    0x0
-#define GC_FLASH_FSH_OVRD_SIGVAL_MAS1_OFFSET     0x2c
-#define GC_FLASH_FSH_OVRD_SIGVAL_NVSTR_LSB       0xa
-#define GC_FLASH_FSH_OVRD_SIGVAL_NVSTR_MASK      0x400
-#define GC_FLASH_FSH_OVRD_SIGVAL_NVSTR_SIZE      0x1
-#define GC_FLASH_FSH_OVRD_SIGVAL_NVSTR_DEFAULT   0x0
-#define GC_FLASH_FSH_OVRD_SIGVAL_NVSTR_OFFSET    0x2c
-#define GC_FLASH_FSH_OVRD_SIGVAL_PV_LSB          0xb
-#define GC_FLASH_FSH_OVRD_SIGVAL_PV_MASK         0x800
-#define GC_FLASH_FSH_OVRD_SIGVAL_PV_SIZE         0x1
-#define GC_FLASH_FSH_OVRD_SIGVAL_PV_DEFAULT      0x0
-#define GC_FLASH_FSH_OVRD_SIGVAL_PV_OFFSET       0x2c
-#define GC_FLASH_FSH_OVRD_SIGVAL_EV_LSB          0xc
-#define GC_FLASH_FSH_OVRD_SIGVAL_EV_MASK         0x1000
-#define GC_FLASH_FSH_OVRD_SIGVAL_EV_SIZE         0x1
-#define GC_FLASH_FSH_OVRD_SIGVAL_EV_DEFAULT      0x0
-#define GC_FLASH_FSH_OVRD_SIGVAL_EV_OFFSET       0x2c
-#define GC_FLASH_FSH_OVRD_SIGEN_IFREN_LSB        0x0
-#define GC_FLASH_FSH_OVRD_SIGEN_IFREN_MASK       0x1
-#define GC_FLASH_FSH_OVRD_SIGEN_IFREN_SIZE       0x1
-#define GC_FLASH_FSH_OVRD_SIGEN_IFREN_DEFAULT    0x0
-#define GC_FLASH_FSH_OVRD_SIGEN_IFREN_OFFSET     0x30
-#define GC_FLASH_FSH_OVRD_SIGEN_IFREN1_LSB       0x1
-#define GC_FLASH_FSH_OVRD_SIGEN_IFREN1_MASK      0x2
-#define GC_FLASH_FSH_OVRD_SIGEN_IFREN1_SIZE      0x1
-#define GC_FLASH_FSH_OVRD_SIGEN_IFREN1_DEFAULT   0x0
-#define GC_FLASH_FSH_OVRD_SIGEN_IFREN1_OFFSET    0x30
-#define GC_FLASH_FSH_OVRD_SIGEN_REDEN_LSB        0x2
-#define GC_FLASH_FSH_OVRD_SIGEN_REDEN_MASK       0x4
-#define GC_FLASH_FSH_OVRD_SIGEN_REDEN_SIZE       0x1
-#define GC_FLASH_FSH_OVRD_SIGEN_REDEN_DEFAULT    0x0
-#define GC_FLASH_FSH_OVRD_SIGEN_REDEN_OFFSET     0x30
-#define GC_FLASH_FSH_OVRD_SIGEN_TMR_LSB          0x3
-#define GC_FLASH_FSH_OVRD_SIGEN_TMR_MASK         0x8
-#define GC_FLASH_FSH_OVRD_SIGEN_TMR_SIZE         0x1
-#define GC_FLASH_FSH_OVRD_SIGEN_TMR_DEFAULT      0x0
-#define GC_FLASH_FSH_OVRD_SIGEN_TMR_OFFSET       0x30
-#define GC_FLASH_FSH_OVRD_SIGEN_XE_LSB           0x4
-#define GC_FLASH_FSH_OVRD_SIGEN_XE_MASK          0x10
-#define GC_FLASH_FSH_OVRD_SIGEN_XE_SIZE          0x1
-#define GC_FLASH_FSH_OVRD_SIGEN_XE_DEFAULT       0x0
-#define GC_FLASH_FSH_OVRD_SIGEN_XE_OFFSET        0x30
-#define GC_FLASH_FSH_OVRD_SIGEN_YE_LSB           0x5
-#define GC_FLASH_FSH_OVRD_SIGEN_YE_MASK          0x20
-#define GC_FLASH_FSH_OVRD_SIGEN_YE_SIZE          0x1
-#define GC_FLASH_FSH_OVRD_SIGEN_YE_DEFAULT       0x0
-#define GC_FLASH_FSH_OVRD_SIGEN_YE_OFFSET        0x30
-#define GC_FLASH_FSH_OVRD_SIGEN_SE_LSB           0x6
-#define GC_FLASH_FSH_OVRD_SIGEN_SE_MASK          0x40
-#define GC_FLASH_FSH_OVRD_SIGEN_SE_SIZE          0x1
-#define GC_FLASH_FSH_OVRD_SIGEN_SE_DEFAULT       0x0
-#define GC_FLASH_FSH_OVRD_SIGEN_SE_OFFSET        0x30
-#define GC_FLASH_FSH_OVRD_SIGEN_ERASE_LSB        0x7
-#define GC_FLASH_FSH_OVRD_SIGEN_ERASE_MASK       0x80
-#define GC_FLASH_FSH_OVRD_SIGEN_ERASE_SIZE       0x1
-#define GC_FLASH_FSH_OVRD_SIGEN_ERASE_DEFAULT    0x0
-#define GC_FLASH_FSH_OVRD_SIGEN_ERASE_OFFSET     0x30
-#define GC_FLASH_FSH_OVRD_SIGEN_PROG_LSB         0x8
-#define GC_FLASH_FSH_OVRD_SIGEN_PROG_MASK        0x100
-#define GC_FLASH_FSH_OVRD_SIGEN_PROG_SIZE        0x1
-#define GC_FLASH_FSH_OVRD_SIGEN_PROG_DEFAULT     0x0
-#define GC_FLASH_FSH_OVRD_SIGEN_PROG_OFFSET      0x30
-#define GC_FLASH_FSH_OVRD_SIGEN_MAS1_LSB         0x9
-#define GC_FLASH_FSH_OVRD_SIGEN_MAS1_MASK        0x200
-#define GC_FLASH_FSH_OVRD_SIGEN_MAS1_SIZE        0x1
-#define GC_FLASH_FSH_OVRD_SIGEN_MAS1_DEFAULT     0x0
-#define GC_FLASH_FSH_OVRD_SIGEN_MAS1_OFFSET      0x30
-#define GC_FLASH_FSH_OVRD_SIGEN_NVSTR_LSB        0xa
-#define GC_FLASH_FSH_OVRD_SIGEN_NVSTR_MASK       0x400
-#define GC_FLASH_FSH_OVRD_SIGEN_NVSTR_SIZE       0x1
-#define GC_FLASH_FSH_OVRD_SIGEN_NVSTR_DEFAULT    0x0
-#define GC_FLASH_FSH_OVRD_SIGEN_NVSTR_OFFSET     0x30
-#define GC_FLASH_FSH_OVRD_SIGEN_PV_LSB           0xb
-#define GC_FLASH_FSH_OVRD_SIGEN_PV_MASK          0x800
-#define GC_FLASH_FSH_OVRD_SIGEN_PV_SIZE          0x1
-#define GC_FLASH_FSH_OVRD_SIGEN_PV_DEFAULT       0x0
-#define GC_FLASH_FSH_OVRD_SIGEN_PV_OFFSET        0x30
-#define GC_FLASH_FSH_OVRD_SIGEN_EV_LSB           0xc
-#define GC_FLASH_FSH_OVRD_SIGEN_EV_MASK          0x1000
-#define GC_FLASH_FSH_OVRD_SIGEN_EV_SIZE          0x1
-#define GC_FLASH_FSH_OVRD_SIGEN_EV_DEFAULT       0x0
-#define GC_FLASH_FSH_OVRD_SIGEN_EV_OFFSET        0x30
-#define GC_FLASH_FSH_OVRD_SIGEN_DIN_LSB          0xd
-#define GC_FLASH_FSH_OVRD_SIGEN_DIN_MASK         0x2000
-#define GC_FLASH_FSH_OVRD_SIGEN_DIN_SIZE         0x1
-#define GC_FLASH_FSH_OVRD_SIGEN_DIN_DEFAULT      0x0
-#define GC_FLASH_FSH_OVRD_SIGEN_DIN_OFFSET       0x30
-#define GC_FLASH_FSH_OVRD_SIGEN_OFFSET_LSB       0xe
-#define GC_FLASH_FSH_OVRD_SIGEN_OFFSET_MASK      0x4000
-#define GC_FLASH_FSH_OVRD_SIGEN_OFFSET_SIZE      0x1
-#define GC_FLASH_FSH_OVRD_SIGEN_OFFSET_DEFAULT   0x0
-#define GC_FLASH_FSH_OVRD_SIGEN_OFFSET_OFFSET    0x30
-#define GC_FLASH_FSH_OVRD_SIGEN_DOUT_LSB         0xf
-#define GC_FLASH_FSH_OVRD_SIGEN_DOUT_MASK        0x8000
-#define GC_FLASH_FSH_OVRD_SIGEN_DOUT_SIZE        0x1
-#define GC_FLASH_FSH_OVRD_SIGEN_DOUT_DEFAULT     0x0
-#define GC_FLASH_FSH_OVRD_SIGEN_DOUT_OFFSET      0x30
-#define GC_FLASH_FSH_OVRD_SIGEN_TC_LSB           0x10
-#define GC_FLASH_FSH_OVRD_SIGEN_TC_MASK          0x10000
-#define GC_FLASH_FSH_OVRD_SIGEN_TC_SIZE          0x1
-#define GC_FLASH_FSH_OVRD_SIGEN_TC_DEFAULT       0x0
-#define GC_FLASH_FSH_OVRD_SIGEN_TC_OFFSET        0x30
-#define GC_FLASH_FSH_REDUN0_EN_LSB               0x0
-#define GC_FLASH_FSH_REDUN0_EN_MASK              0x1
-#define GC_FLASH_FSH_REDUN0_EN_SIZE              0x1
-#define GC_FLASH_FSH_REDUN0_EN_DEFAULT           0x0
-#define GC_FLASH_FSH_REDUN0_EN_OFFSET            0xcc
-#define GC_FLASH_FSH_REDUN0_REMAP_LSB            0x1
-#define GC_FLASH_FSH_REDUN0_REMAP_MASK           0xfe
-#define GC_FLASH_FSH_REDUN0_REMAP_SIZE           0x7
-#define GC_FLASH_FSH_REDUN0_REMAP_DEFAULT        0x0
-#define GC_FLASH_FSH_REDUN0_REMAP_OFFSET         0xcc
-#define GC_FLASH_FSH_REDUN1_EN_LSB               0x0
-#define GC_FLASH_FSH_REDUN1_EN_MASK              0x1
-#define GC_FLASH_FSH_REDUN1_EN_SIZE              0x1
-#define GC_FLASH_FSH_REDUN1_EN_DEFAULT           0x0
-#define GC_FLASH_FSH_REDUN1_EN_OFFSET            0xd0
-#define GC_FLASH_FSH_REDUN1_REMAP_LSB            0x1
-#define GC_FLASH_FSH_REDUN1_REMAP_MASK           0xfe
-#define GC_FLASH_FSH_REDUN1_REMAP_SIZE           0x7
-#define GC_FLASH_FSH_REDUN1_REMAP_DEFAULT        0x0
-#define GC_FLASH_FSH_REDUN1_REMAP_OFFSET         0xd0
-#define GC_FLASH_FSH_DBG_STATE_LSB               0x0
-#define GC_FLASH_FSH_DBG_STATE_MASK              0xf
-#define GC_FLASH_FSH_DBG_STATE_SIZE              0x4
-#define GC_FLASH_FSH_DBG_STATE_DEFAULT           0x0
-#define GC_FLASH_FSH_DBG_STATE_OFFSET            0x17c
-#define GC_FLASH_FSH_ITOP_PDONEINT_LSB           0x0
-#define GC_FLASH_FSH_ITOP_PDONEINT_MASK          0x1
-#define GC_FLASH_FSH_ITOP_PDONEINT_SIZE          0x1
-#define GC_FLASH_FSH_ITOP_PDONEINT_DEFAULT       0x0
-#define GC_FLASH_FSH_ITOP_PDONEINT_OFFSET        0xf04
-#define GC_FLASH_FSH_ITOP_EDONEINT_LSB           0x1
-#define GC_FLASH_FSH_ITOP_EDONEINT_MASK          0x2
-#define GC_FLASH_FSH_ITOP_EDONEINT_SIZE          0x1
-#define GC_FLASH_FSH_ITOP_EDONEINT_DEFAULT       0x0
-#define GC_FLASH_FSH_ITOP_EDONEINT_OFFSET        0xf04
-#define GC_FUSE_STATUS_VALID_LSB                 0x0
-#define GC_FUSE_STATUS_VALID_MASK                0x1
-#define GC_FUSE_STATUS_VALID_SIZE                0x1
-#define GC_FUSE_STATUS_VALID_DEFAULT             0x0
-#define GC_FUSE_STATUS_VALID_OFFSET              0x0
-#define GC_FUSE_STATUS_DEFAULTS_VALID_LSB        0x1
-#define GC_FUSE_STATUS_DEFAULTS_VALID_MASK       0x2
-#define GC_FUSE_STATUS_DEFAULTS_VALID_SIZE       0x1
-#define GC_FUSE_STATUS_DEFAULTS_VALID_DEFAULT    0x0
-#define GC_FUSE_STATUS_DEFAULTS_VALID_OFFSET     0x0
-#define GC_FUSE_STATUS_READ_DONE_LSB             0x2
-#define GC_FUSE_STATUS_READ_DONE_MASK            0x4
-#define GC_FUSE_STATUS_READ_DONE_SIZE            0x1
-#define GC_FUSE_STATUS_READ_DONE_DEFAULT         0x0
-#define GC_FUSE_STATUS_READ_DONE_OFFSET          0x0
-#define GC_FUSE_STATUS_READ_DONE_ERR_LSB         0x3
-#define GC_FUSE_STATUS_READ_DONE_ERR_MASK        0x8
-#define GC_FUSE_STATUS_READ_DONE_ERR_SIZE        0x1
-#define GC_FUSE_STATUS_READ_DONE_ERR_DEFAULT     0x0
-#define GC_FUSE_STATUS_READ_DONE_ERR_OFFSET      0x0
-#define GC_FUSE_STATUS_PROG_VERIFY_DONE_LSB      0x4
-#define GC_FUSE_STATUS_PROG_VERIFY_DONE_MASK     0x10
-#define GC_FUSE_STATUS_PROG_VERIFY_DONE_SIZE     0x1
-#define GC_FUSE_STATUS_PROG_VERIFY_DONE_DEFAULT  0x0
-#define GC_FUSE_STATUS_PROG_VERIFY_DONE_OFFSET   0x0
-#define GC_FUSE_STATUS_PROG_VERIFY_DONE_ERR_LSB  0x5
-#define GC_FUSE_STATUS_PROG_VERIFY_DONE_ERR_MASK 0x20
-#define GC_FUSE_STATUS_PROG_VERIFY_DONE_ERR_SIZE 0x1
-#define GC_FUSE_STATUS_PROG_VERIFY_DONE_ERR_DEFAULT 0x0
-#define GC_FUSE_STATUS_PROG_VERIFY_DONE_ERR_OFFSET 0x0
-#define GC_FUSE_STATUS_OVERRIDE_DONE_LSB         0x6
-#define GC_FUSE_STATUS_OVERRIDE_DONE_MASK        0x40
-#define GC_FUSE_STATUS_OVERRIDE_DONE_SIZE        0x1
-#define GC_FUSE_STATUS_OVERRIDE_DONE_DEFAULT     0x0
-#define GC_FUSE_STATUS_OVERRIDE_DONE_OFFSET      0x0
-#define GC_FUSE_STATUS_BUSY_LSB                  0x7
-#define GC_FUSE_STATUS_BUSY_MASK                 0x80
-#define GC_FUSE_STATUS_BUSY_SIZE                 0x1
-#define GC_FUSE_STATUS_BUSY_DEFAULT              0x0
-#define GC_FUSE_STATUS_BUSY_OFFSET               0x0
-#define GC_FUSE_FPGA_MODEL_CTRL_ERASE_LSB        0x0
-#define GC_FUSE_FPGA_MODEL_CTRL_ERASE_MASK       0x1
-#define GC_FUSE_FPGA_MODEL_CTRL_ERASE_SIZE       0x1
-#define GC_FUSE_FPGA_MODEL_CTRL_ERASE_DEFAULT    0x0
-#define GC_FUSE_FPGA_MODEL_CTRL_ERASE_OFFSET     0x10
-#define GC_FUSE_ANTEST_EN_SW0_LSB                0x0
-#define GC_FUSE_ANTEST_EN_SW0_MASK               0x1
-#define GC_FUSE_ANTEST_EN_SW0_SIZE               0x1
-#define GC_FUSE_ANTEST_EN_SW0_DEFAULT            0x0
-#define GC_FUSE_ANTEST_EN_SW0_OFFSET             0x28
-#define GC_FUSE_ANTEST_EN_SW1_LSB                0x1
-#define GC_FUSE_ANTEST_EN_SW1_MASK               0x2
-#define GC_FUSE_ANTEST_EN_SW1_SIZE               0x1
-#define GC_FUSE_ANTEST_EN_SW1_DEFAULT            0x0
-#define GC_FUSE_ANTEST_EN_SW1_OFFSET             0x28
-#define GC_FUSE_ANTEST_EN_SW2_LSB                0x2
-#define GC_FUSE_ANTEST_EN_SW2_MASK               0x4
-#define GC_FUSE_ANTEST_EN_SW2_SIZE               0x1
-#define GC_FUSE_ANTEST_EN_SW2_DEFAULT            0x0
-#define GC_FUSE_ANTEST_EN_SW2_OFFSET             0x28
-#define GC_FUSE_ANTEST_EN_SW3_LSB                0x3
-#define GC_FUSE_ANTEST_EN_SW3_MASK               0x8
-#define GC_FUSE_ANTEST_EN_SW3_SIZE               0x1
-#define GC_FUSE_ANTEST_EN_SW3_DEFAULT            0x0
-#define GC_FUSE_ANTEST_EN_SW3_OFFSET             0x28
-#define GC_FUSE_VERSION_CHANGE_LSB               0x0
-#define GC_FUSE_VERSION_CHANGE_MASK              0xffffff
-#define GC_FUSE_VERSION_CHANGE_SIZE              0x18
-#define GC_FUSE_VERSION_CHANGE_DEFAULT           0x14125
-#define GC_FUSE_VERSION_CHANGE_OFFSET            0x2c
-#define GC_FUSE_VERSION_REVISION_LSB             0x18
-#define GC_FUSE_VERSION_REVISION_MASK            0xff000000
-#define GC_FUSE_VERSION_REVISION_SIZE            0x8
-#define GC_FUSE_VERSION_REVISION_DEFAULT         0x1
-#define GC_FUSE_VERSION_REVISION_OFFSET          0x2c
-#define GC_FUSE_BNK0_INTG_CHKSUM_VAL_LSB         0x0
-#define GC_FUSE_BNK0_INTG_CHKSUM_VAL_MASK        0xffffff
-#define GC_FUSE_BNK0_INTG_CHKSUM_VAL_SIZE        0x18
-#define GC_FUSE_BNK0_INTG_CHKSUM_VAL_DEFAULT     0x0
-#define GC_FUSE_BNK0_INTG_CHKSUM_VAL_OFFSET      0x30
-#define GC_FUSE_BNK0_INTG_LOCK_VAL_LSB           0x0
-#define GC_FUSE_BNK0_INTG_LOCK_VAL_MASK          0x7
-#define GC_FUSE_BNK0_INTG_LOCK_VAL_SIZE          0x3
-#define GC_FUSE_BNK0_INTG_LOCK_VAL_DEFAULT       0x0
-#define GC_FUSE_BNK0_INTG_LOCK_VAL_OFFSET        0x34
-#define GC_FUSE_DS_GRP0_VAL_LSB                  0x0
-#define GC_FUSE_DS_GRP0_VAL_MASK                 0x1ff
-#define GC_FUSE_DS_GRP0_VAL_SIZE                 0x9
-#define GC_FUSE_DS_GRP0_VAL_DEFAULT              0x0
-#define GC_FUSE_DS_GRP0_VAL_OFFSET               0x38
-#define GC_FUSE_DS_GRP1_VAL_LSB                  0x0
-#define GC_FUSE_DS_GRP1_VAL_MASK                 0x1ff
-#define GC_FUSE_DS_GRP1_VAL_SIZE                 0x9
-#define GC_FUSE_DS_GRP1_VAL_DEFAULT              0x0
-#define GC_FUSE_DS_GRP1_VAL_OFFSET               0x3c
-#define GC_FUSE_DS_GRP2_VAL_LSB                  0x0
-#define GC_FUSE_DS_GRP2_VAL_MASK                 0x1ff
-#define GC_FUSE_DS_GRP2_VAL_SIZE                 0x9
-#define GC_FUSE_DS_GRP2_VAL_DEFAULT              0x0
-#define GC_FUSE_DS_GRP2_VAL_OFFSET               0x40
-#define GC_FUSE_DEV_ID0_VAL_LSB                  0x0
-#define GC_FUSE_DEV_ID0_VAL_MASK                 0xffffffff
-#define GC_FUSE_DEV_ID0_VAL_SIZE                 0x20
-#define GC_FUSE_DEV_ID0_VAL_DEFAULT              0x0
-#define GC_FUSE_DEV_ID0_VAL_OFFSET               0x44
-#define GC_FUSE_DEV_ID1_VAL_LSB                  0x0
-#define GC_FUSE_DEV_ID1_VAL_MASK                 0xffffffff
-#define GC_FUSE_DEV_ID1_VAL_SIZE                 0x20
-#define GC_FUSE_DEV_ID1_VAL_DEFAULT              0x0
-#define GC_FUSE_DEV_ID1_VAL_OFFSET               0x48
-#define GC_FUSE_BNK1_INTG_CHKSUM_VAL_LSB         0x0
-#define GC_FUSE_BNK1_INTG_CHKSUM_VAL_MASK        0xffffff
-#define GC_FUSE_BNK1_INTG_CHKSUM_VAL_SIZE        0x18
-#define GC_FUSE_BNK1_INTG_CHKSUM_VAL_DEFAULT     0x0
-#define GC_FUSE_BNK1_INTG_CHKSUM_VAL_OFFSET      0x4c
-#define GC_FUSE_BNK1_INTG_LOCK_VAL_LSB           0x0
-#define GC_FUSE_BNK1_INTG_LOCK_VAL_MASK          0x7
-#define GC_FUSE_BNK1_INTG_LOCK_VAL_SIZE          0x3
-#define GC_FUSE_BNK1_INTG_LOCK_VAL_DEFAULT       0x0
-#define GC_FUSE_BNK1_INTG_LOCK_VAL_OFFSET        0x50
-#define GC_FUSE_LB0_POST_OVRD_VAL_LSB            0x0
-#define GC_FUSE_LB0_POST_OVRD_VAL_MASK           0x7
-#define GC_FUSE_LB0_POST_OVRD_VAL_SIZE           0x3
-#define GC_FUSE_LB0_POST_OVRD_VAL_DEFAULT        0x0
-#define GC_FUSE_LB0_POST_OVRD_VAL_OFFSET         0x54
-#define GC_FUSE_LB0_POST_PATCNT_VAL_LSB          0x0
-#define GC_FUSE_LB0_POST_PATCNT_VAL_MASK         0x3
-#define GC_FUSE_LB0_POST_PATCNT_VAL_SIZE         0x2
-#define GC_FUSE_LB0_POST_PATCNT_VAL_DEFAULT      0x0
-#define GC_FUSE_LB0_POST_PATCNT_VAL_OFFSET       0x58
-#define GC_FUSE_LB0_POST_WARMUP_OVRD_VAL_LSB     0x0
-#define GC_FUSE_LB0_POST_WARMUP_OVRD_VAL_MASK    0x7
-#define GC_FUSE_LB0_POST_WARMUP_OVRD_VAL_SIZE    0x3
-#define GC_FUSE_LB0_POST_WARMUP_OVRD_VAL_DEFAULT 0x0
-#define GC_FUSE_LB0_POST_WARMUP_OVRD_VAL_OFFSET  0x5c
-#define GC_FUSE_LB0_POST_WARMUP_CNT_VAL_LSB      0x0
-#define GC_FUSE_LB0_POST_WARMUP_CNT_VAL_MASK     0x3
-#define GC_FUSE_LB0_POST_WARMUP_CNT_VAL_SIZE     0x2
-#define GC_FUSE_LB0_POST_WARMUP_CNT_VAL_DEFAULT  0x0
-#define GC_FUSE_LB0_POST_WARMUP_CNT_VAL_OFFSET   0x60
-#define GC_FUSE_LB1_POST_OVRD_VAL_LSB            0x0
-#define GC_FUSE_LB1_POST_OVRD_VAL_MASK           0x7
-#define GC_FUSE_LB1_POST_OVRD_VAL_SIZE           0x3
-#define GC_FUSE_LB1_POST_OVRD_VAL_DEFAULT        0x0
-#define GC_FUSE_LB1_POST_OVRD_VAL_OFFSET         0x64
-#define GC_FUSE_LB1_POST_PATCNT_VAL_LSB          0x0
-#define GC_FUSE_LB1_POST_PATCNT_VAL_MASK         0x3
-#define GC_FUSE_LB1_POST_PATCNT_VAL_SIZE         0x2
-#define GC_FUSE_LB1_POST_PATCNT_VAL_DEFAULT      0x0
-#define GC_FUSE_LB1_POST_PATCNT_VAL_OFFSET       0x68
-#define GC_FUSE_LB1_POST_WARMUP_OVRD_VAL_LSB     0x0
-#define GC_FUSE_LB1_POST_WARMUP_OVRD_VAL_MASK    0x7
-#define GC_FUSE_LB1_POST_WARMUP_OVRD_VAL_SIZE    0x3
-#define GC_FUSE_LB1_POST_WARMUP_OVRD_VAL_DEFAULT 0x0
-#define GC_FUSE_LB1_POST_WARMUP_OVRD_VAL_OFFSET  0x6c
-#define GC_FUSE_LB1_POST_WARMUP_CNT_VAL_LSB      0x0
-#define GC_FUSE_LB1_POST_WARMUP_CNT_VAL_MASK     0x3
-#define GC_FUSE_LB1_POST_WARMUP_CNT_VAL_SIZE     0x2
-#define GC_FUSE_LB1_POST_WARMUP_CNT_VAL_DEFAULT  0x0
-#define GC_FUSE_LB1_POST_WARMUP_CNT_VAL_OFFSET   0x70
-#define GC_FUSE_LB2_POST_OVRD_VAL_LSB            0x0
-#define GC_FUSE_LB2_POST_OVRD_VAL_MASK           0x7
-#define GC_FUSE_LB2_POST_OVRD_VAL_SIZE           0x3
-#define GC_FUSE_LB2_POST_OVRD_VAL_DEFAULT        0x0
-#define GC_FUSE_LB2_POST_OVRD_VAL_OFFSET         0x74
-#define GC_FUSE_LB2_POST_PATCNT_VAL_LSB          0x0
-#define GC_FUSE_LB2_POST_PATCNT_VAL_MASK         0x3
-#define GC_FUSE_LB2_POST_PATCNT_VAL_SIZE         0x2
-#define GC_FUSE_LB2_POST_PATCNT_VAL_DEFAULT      0x0
-#define GC_FUSE_LB2_POST_PATCNT_VAL_OFFSET       0x78
-#define GC_FUSE_LB2_POST_WARMUP_OVRD_VAL_LSB     0x0
-#define GC_FUSE_LB2_POST_WARMUP_OVRD_VAL_MASK    0x7
-#define GC_FUSE_LB2_POST_WARMUP_OVRD_VAL_SIZE    0x3
-#define GC_FUSE_LB2_POST_WARMUP_OVRD_VAL_DEFAULT 0x0
-#define GC_FUSE_LB2_POST_WARMUP_OVRD_VAL_OFFSET  0x7c
-#define GC_FUSE_LB2_POST_WARMUP_CNT_VAL_LSB      0x0
-#define GC_FUSE_LB2_POST_WARMUP_CNT_VAL_MASK     0x3
-#define GC_FUSE_LB2_POST_WARMUP_CNT_VAL_SIZE     0x2
-#define GC_FUSE_LB2_POST_WARMUP_CNT_VAL_DEFAULT  0x0
-#define GC_FUSE_LB2_POST_WARMUP_CNT_VAL_OFFSET   0x80
-#define GC_FUSE_LB3_POST_OVRD_VAL_LSB            0x0
-#define GC_FUSE_LB3_POST_OVRD_VAL_MASK           0x7
-#define GC_FUSE_LB3_POST_OVRD_VAL_SIZE           0x3
-#define GC_FUSE_LB3_POST_OVRD_VAL_DEFAULT        0x0
-#define GC_FUSE_LB3_POST_OVRD_VAL_OFFSET         0x84
-#define GC_FUSE_LB3_POST_PATCNT_VAL_LSB          0x0
-#define GC_FUSE_LB3_POST_PATCNT_VAL_MASK         0x3
-#define GC_FUSE_LB3_POST_PATCNT_VAL_SIZE         0x2
-#define GC_FUSE_LB3_POST_PATCNT_VAL_DEFAULT      0x0
-#define GC_FUSE_LB3_POST_PATCNT_VAL_OFFSET       0x88
-#define GC_FUSE_LB3_POST_WARMUP_OVRD_VAL_LSB     0x0
-#define GC_FUSE_LB3_POST_WARMUP_OVRD_VAL_MASK    0x7
-#define GC_FUSE_LB3_POST_WARMUP_OVRD_VAL_SIZE    0x3
-#define GC_FUSE_LB3_POST_WARMUP_OVRD_VAL_DEFAULT 0x0
-#define GC_FUSE_LB3_POST_WARMUP_OVRD_VAL_OFFSET  0x8c
-#define GC_FUSE_LB3_POST_WARMUP_CNT_VAL_LSB      0x0
-#define GC_FUSE_LB3_POST_WARMUP_CNT_VAL_MASK     0x3
-#define GC_FUSE_LB3_POST_WARMUP_CNT_VAL_SIZE     0x2
-#define GC_FUSE_LB3_POST_WARMUP_CNT_VAL_DEFAULT  0x0
-#define GC_FUSE_LB3_POST_WARMUP_CNT_VAL_OFFSET   0x90
-#define GC_FUSE_LB4_POST_OVRD_VAL_LSB            0x0
-#define GC_FUSE_LB4_POST_OVRD_VAL_MASK           0x7
-#define GC_FUSE_LB4_POST_OVRD_VAL_SIZE           0x3
-#define GC_FUSE_LB4_POST_OVRD_VAL_DEFAULT        0x0
-#define GC_FUSE_LB4_POST_OVRD_VAL_OFFSET         0x94
-#define GC_FUSE_LB4_POST_PATCNT_VAL_LSB          0x0
-#define GC_FUSE_LB4_POST_PATCNT_VAL_MASK         0x3
-#define GC_FUSE_LB4_POST_PATCNT_VAL_SIZE         0x2
-#define GC_FUSE_LB4_POST_PATCNT_VAL_DEFAULT      0x0
-#define GC_FUSE_LB4_POST_PATCNT_VAL_OFFSET       0x98
-#define GC_FUSE_LB4_POST_WARMUP_OVRD_VAL_LSB     0x0
-#define GC_FUSE_LB4_POST_WARMUP_OVRD_VAL_MASK    0x7
-#define GC_FUSE_LB4_POST_WARMUP_OVRD_VAL_SIZE    0x3
-#define GC_FUSE_LB4_POST_WARMUP_OVRD_VAL_DEFAULT 0x0
-#define GC_FUSE_LB4_POST_WARMUP_OVRD_VAL_OFFSET  0x9c
-#define GC_FUSE_LB4_POST_WARMUP_CNT_VAL_LSB      0x0
-#define GC_FUSE_LB4_POST_WARMUP_CNT_VAL_MASK     0x3
-#define GC_FUSE_LB4_POST_WARMUP_CNT_VAL_SIZE     0x2
-#define GC_FUSE_LB4_POST_WARMUP_CNT_VAL_DEFAULT  0x0
-#define GC_FUSE_LB4_POST_WARMUP_CNT_VAL_OFFSET   0xa0
-#define GC_FUSE_MBIST_POST_SEQ_VAL_LSB           0x0
-#define GC_FUSE_MBIST_POST_SEQ_VAL_MASK          0x1ffffff
-#define GC_FUSE_MBIST_POST_SEQ_VAL_SIZE          0x19
-#define GC_FUSE_MBIST_POST_SEQ_VAL_DEFAULT       0x0
-#define GC_FUSE_MBIST_POST_SEQ_VAL_OFFSET        0xa4
-#define GC_FUSE_LBIST_POST_SEQ_VAL_LSB           0x0
-#define GC_FUSE_LBIST_POST_SEQ_VAL_MASK          0x1ffffff
-#define GC_FUSE_LBIST_POST_SEQ_VAL_SIZE          0x19
-#define GC_FUSE_LBIST_POST_SEQ_VAL_DEFAULT       0x0
-#define GC_FUSE_LBIST_POST_SEQ_VAL_OFFSET        0xa8
-#define GC_FUSE_LBIST_VIA_TAP_DIS_VAL_LSB        0x0
-#define GC_FUSE_LBIST_VIA_TAP_DIS_VAL_MASK       0x7
-#define GC_FUSE_LBIST_VIA_TAP_DIS_VAL_SIZE       0x3
-#define GC_FUSE_LBIST_VIA_TAP_DIS_VAL_DEFAULT    0x0
-#define GC_FUSE_LBIST_VIA_TAP_DIS_VAL_OFFSET     0xac
-#define GC_FUSE_MBIST_VIA_TAP_DIS_VAL_LSB        0x0
-#define GC_FUSE_MBIST_VIA_TAP_DIS_VAL_MASK       0x7
-#define GC_FUSE_MBIST_VIA_TAP_DIS_VAL_SIZE       0x3
-#define GC_FUSE_MBIST_VIA_TAP_DIS_VAL_DEFAULT    0x0
-#define GC_FUSE_MBIST_VIA_TAP_DIS_VAL_OFFSET     0xb0
-#define GC_FUSE_TAP_DISABLE_VAL_LSB              0x0
-#define GC_FUSE_TAP_DISABLE_VAL_MASK             0x7
-#define GC_FUSE_TAP_DISABLE_VAL_SIZE             0x3
-#define GC_FUSE_TAP_DISABLE_VAL_DEFAULT          0x0
-#define GC_FUSE_TAP_DISABLE_VAL_OFFSET           0xb4
-#define GC_FUSE_RNGBIST_AR_EN_VAL_LSB            0x0
-#define GC_FUSE_RNGBIST_AR_EN_VAL_MASK           0x7
-#define GC_FUSE_RNGBIST_AR_EN_VAL_SIZE           0x3
-#define GC_FUSE_RNGBIST_AR_EN_VAL_DEFAULT        0x0
-#define GC_FUSE_RNGBIST_AR_EN_VAL_OFFSET         0xb8
-#define GC_FUSE_TESTMODE_KEYS_EN_VAL_LSB         0x0
-#define GC_FUSE_TESTMODE_KEYS_EN_VAL_MASK        0x7
-#define GC_FUSE_TESTMODE_KEYS_EN_VAL_SIZE        0x3
-#define GC_FUSE_TESTMODE_KEYS_EN_VAL_DEFAULT     0x0
-#define GC_FUSE_TESTMODE_KEYS_EN_VAL_OFFSET      0xbc
-#define GC_FUSE_PKG_ID_VAL_LSB                   0x0
-#define GC_FUSE_PKG_ID_VAL_MASK                  0x7
-#define GC_FUSE_PKG_ID_VAL_SIZE                  0x3
-#define GC_FUSE_PKG_ID_VAL_DEFAULT               0x0
-#define GC_FUSE_PKG_ID_VAL_OFFSET                0xc0
-#define GC_FUSE_BIN_ID_VAL_LSB                   0x0
-#define GC_FUSE_BIN_ID_VAL_MASK                  0x7
-#define GC_FUSE_BIN_ID_VAL_SIZE                  0x3
-#define GC_FUSE_BIN_ID_VAL_DEFAULT               0x0
-#define GC_FUSE_BIN_ID_VAL_OFFSET                0xc4
-#define GC_FUSE_RC_JTR_OSC48_CC_TRIM_VAL_LSB     0x0
-#define GC_FUSE_RC_JTR_OSC48_CC_TRIM_VAL_MASK    0xff
-#define GC_FUSE_RC_JTR_OSC48_CC_TRIM_VAL_SIZE    0x8
-#define GC_FUSE_RC_JTR_OSC48_CC_TRIM_VAL_DEFAULT 0x0
-#define GC_FUSE_RC_JTR_OSC48_CC_TRIM_VAL_OFFSET  0xc8
-#define GC_FUSE_RC_JTR_OSC48_CC_EN_VAL_LSB       0x0
-#define GC_FUSE_RC_JTR_OSC48_CC_EN_VAL_MASK      0x7
-#define GC_FUSE_RC_JTR_OSC48_CC_EN_VAL_SIZE      0x3
-#define GC_FUSE_RC_JTR_OSC48_CC_EN_VAL_DEFAULT   0x0
-#define GC_FUSE_RC_JTR_OSC48_CC_EN_VAL_OFFSET    0xcc
-#define GC_FUSE_RC_JTR_OSC60_CC_TRIM_VAL_LSB     0x0
-#define GC_FUSE_RC_JTR_OSC60_CC_TRIM_VAL_MASK    0xff
-#define GC_FUSE_RC_JTR_OSC60_CC_TRIM_VAL_SIZE    0x8
-#define GC_FUSE_RC_JTR_OSC60_CC_TRIM_VAL_DEFAULT 0x0
-#define GC_FUSE_RC_JTR_OSC60_CC_TRIM_VAL_OFFSET  0xd0
-#define GC_FUSE_RC_JTR_OSC60_CC_EN_VAL_LSB       0x0
-#define GC_FUSE_RC_JTR_OSC60_CC_EN_VAL_MASK      0x7
-#define GC_FUSE_RC_JTR_OSC60_CC_EN_VAL_SIZE      0x3
-#define GC_FUSE_RC_JTR_OSC60_CC_EN_VAL_DEFAULT   0x0
-#define GC_FUSE_RC_JTR_OSC60_CC_EN_VAL_OFFSET    0xd4
-#define GC_FUSE_RC_TIMER_OSC48_CC_TRIM_VAL_LSB   0x0
-#define GC_FUSE_RC_TIMER_OSC48_CC_TRIM_VAL_MASK  0xff
-#define GC_FUSE_RC_TIMER_OSC48_CC_TRIM_VAL_SIZE  0x8
-#define GC_FUSE_RC_TIMER_OSC48_CC_TRIM_VAL_DEFAULT 0x0
-#define GC_FUSE_RC_TIMER_OSC48_CC_TRIM_VAL_OFFSET 0xd8
-#define GC_FUSE_RC_TIMER_OSC48_CC_EN_VAL_LSB     0x0
-#define GC_FUSE_RC_TIMER_OSC48_CC_EN_VAL_MASK    0x7
-#define GC_FUSE_RC_TIMER_OSC48_CC_EN_VAL_SIZE    0x3
-#define GC_FUSE_RC_TIMER_OSC48_CC_EN_VAL_DEFAULT 0x0
-#define GC_FUSE_RC_TIMER_OSC48_CC_EN_VAL_OFFSET  0xdc
-#define GC_FUSE_RC_TIMER_OSC48_FC_TRIM_VAL_LSB   0x0
-#define GC_FUSE_RC_TIMER_OSC48_FC_TRIM_VAL_MASK  0x1f
-#define GC_FUSE_RC_TIMER_OSC48_FC_TRIM_VAL_SIZE  0x5
-#define GC_FUSE_RC_TIMER_OSC48_FC_TRIM_VAL_DEFAULT 0x0
-#define GC_FUSE_RC_TIMER_OSC48_FC_TRIM_VAL_OFFSET 0xe0
-#define GC_FUSE_RC_TIMER_OSC48_FC_EN_VAL_LSB     0x0
-#define GC_FUSE_RC_TIMER_OSC48_FC_EN_VAL_MASK    0x7
-#define GC_FUSE_RC_TIMER_OSC48_FC_EN_VAL_SIZE    0x3
-#define GC_FUSE_RC_TIMER_OSC48_FC_EN_VAL_DEFAULT 0x0
-#define GC_FUSE_RC_TIMER_OSC48_FC_EN_VAL_OFFSET  0xe4
-#define GC_FUSE_RC_RTC_OSC256K_CC_TRIM_VAL_LSB   0x0
-#define GC_FUSE_RC_RTC_OSC256K_CC_TRIM_VAL_MASK  0xff
-#define GC_FUSE_RC_RTC_OSC256K_CC_TRIM_VAL_SIZE  0x8
-#define GC_FUSE_RC_RTC_OSC256K_CC_TRIM_VAL_DEFAULT 0x0
-#define GC_FUSE_RC_RTC_OSC256K_CC_TRIM_VAL_OFFSET 0xe8
-#define GC_FUSE_RC_RTC_OSC256K_CC_EN_VAL_LSB     0x0
-#define GC_FUSE_RC_RTC_OSC256K_CC_EN_VAL_MASK    0x7
-#define GC_FUSE_RC_RTC_OSC256K_CC_EN_VAL_SIZE    0x3
-#define GC_FUSE_RC_RTC_OSC256K_CC_EN_VAL_DEFAULT 0x0
-#define GC_FUSE_RC_RTC_OSC256K_CC_EN_VAL_OFFSET  0xec
-#define GC_FUSE_SEL_VREG_REG_EN_VAL_LSB          0x0
-#define GC_FUSE_SEL_VREG_REG_EN_VAL_MASK         0x7
-#define GC_FUSE_SEL_VREG_REG_EN_VAL_SIZE         0x3
-#define GC_FUSE_SEL_VREG_REG_EN_VAL_DEFAULT      0x0
-#define GC_FUSE_SEL_VREG_REG_EN_VAL_OFFSET       0xf0
-#define GC_FUSE_SEL_VREF_REG_VAL_LSB             0x0
-#define GC_FUSE_SEL_VREF_REG_VAL_MASK            0xf
-#define GC_FUSE_SEL_VREF_REG_VAL_SIZE            0x4
-#define GC_FUSE_SEL_VREF_REG_VAL_DEFAULT         0x0
-#define GC_FUSE_SEL_VREF_REG_VAL_OFFSET          0xf4
-#define GC_FUSE_SEL_VREF_BATMON_EN_VAL_LSB       0x0
-#define GC_FUSE_SEL_VREF_BATMON_EN_VAL_MASK      0x7
-#define GC_FUSE_SEL_VREF_BATMON_EN_VAL_SIZE      0x3
-#define GC_FUSE_SEL_VREF_BATMON_EN_VAL_DEFAULT   0x0
-#define GC_FUSE_SEL_VREF_BATMON_EN_VAL_OFFSET    0xf8
-#define GC_FUSE_SEL_VREF_BATMON_VAL_LSB          0x0
-#define GC_FUSE_SEL_VREF_BATMON_VAL_MASK         0x7
-#define GC_FUSE_SEL_VREF_BATMON_VAL_SIZE         0x3
-#define GC_FUSE_SEL_VREF_BATMON_VAL_DEFAULT      0x0
-#define GC_FUSE_SEL_VREF_BATMON_VAL_OFFSET       0xfc
-#define GC_FUSE_X_OSC_LDO_CTRL_EN_VAL_LSB        0x0
-#define GC_FUSE_X_OSC_LDO_CTRL_EN_VAL_MASK       0x7
-#define GC_FUSE_X_OSC_LDO_CTRL_EN_VAL_SIZE       0x3
-#define GC_FUSE_X_OSC_LDO_CTRL_EN_VAL_DEFAULT    0x0
-#define GC_FUSE_X_OSC_LDO_CTRL_EN_VAL_OFFSET     0x100
-#define GC_FUSE_X_OSC_LDO_CTRL_VAL_LSB           0x0
-#define GC_FUSE_X_OSC_LDO_CTRL_VAL_MASK          0xf
-#define GC_FUSE_X_OSC_LDO_CTRL_VAL_SIZE          0x4
-#define GC_FUSE_X_OSC_LDO_CTRL_VAL_DEFAULT       0x0
-#define GC_FUSE_X_OSC_LDO_CTRL_VAL_OFFSET        0x104
-#define GC_FUSE_TEMP_OFFSET_CAL_VAL_LSB          0x0
-#define GC_FUSE_TEMP_OFFSET_CAL_VAL_MASK         0xfff
-#define GC_FUSE_TEMP_OFFSET_CAL_VAL_SIZE         0xc
-#define GC_FUSE_TEMP_OFFSET_CAL_VAL_DEFAULT      0x0
-#define GC_FUSE_TEMP_OFFSET_CAL_VAL_OFFSET       0x108
-#define GC_FUSE_TRNG_LDO_CTRL_EN_VAL_LSB         0x0
-#define GC_FUSE_TRNG_LDO_CTRL_EN_VAL_MASK        0x7
-#define GC_FUSE_TRNG_LDO_CTRL_EN_VAL_SIZE        0x3
-#define GC_FUSE_TRNG_LDO_CTRL_EN_VAL_DEFAULT     0x0
-#define GC_FUSE_TRNG_LDO_CTRL_EN_VAL_OFFSET      0x10c
-#define GC_FUSE_TRNG_LDO_CTRL_VAL_LSB            0x0
-#define GC_FUSE_TRNG_LDO_CTRL_VAL_MASK           0x1f
-#define GC_FUSE_TRNG_LDO_CTRL_VAL_SIZE           0x5
-#define GC_FUSE_TRNG_LDO_CTRL_VAL_DEFAULT        0x0
-#define GC_FUSE_TRNG_LDO_CTRL_VAL_OFFSET         0x110
-#define GC_FUSE_TRNG_ANALOG_CTRL_EN_VAL_LSB      0x0
-#define GC_FUSE_TRNG_ANALOG_CTRL_EN_VAL_MASK     0x7
-#define GC_FUSE_TRNG_ANALOG_CTRL_EN_VAL_SIZE     0x3
-#define GC_FUSE_TRNG_ANALOG_CTRL_EN_VAL_DEFAULT  0x0
-#define GC_FUSE_TRNG_ANALOG_CTRL_EN_VAL_OFFSET   0x114
-#define GC_FUSE_TRNG_ANALOG_CTRL_VAL_LSB         0x0
-#define GC_FUSE_TRNG_ANALOG_CTRL_VAL_MASK        0xf
-#define GC_FUSE_TRNG_ANALOG_CTRL_VAL_SIZE        0x4
-#define GC_FUSE_TRNG_ANALOG_CTRL_VAL_DEFAULT     0x0
-#define GC_FUSE_TRNG_ANALOG_CTRL_VAL_OFFSET      0x118
-#define GC_FUSE_EXT_XTAL_PDB_VAL_LSB             0x0
-#define GC_FUSE_EXT_XTAL_PDB_VAL_MASK            0x3
-#define GC_FUSE_EXT_XTAL_PDB_VAL_SIZE            0x2
-#define GC_FUSE_EXT_XTAL_PDB_VAL_DEFAULT         0x0
-#define GC_FUSE_EXT_XTAL_PDB_VAL_OFFSET          0x11c
-#define GC_FUSE_DIS_EXT_XTAL_CLK_TREE_VAL_LSB    0x0
-#define GC_FUSE_DIS_EXT_XTAL_CLK_TREE_VAL_MASK   0x7
-#define GC_FUSE_DIS_EXT_XTAL_CLK_TREE_VAL_SIZE   0x3
-#define GC_FUSE_DIS_EXT_XTAL_CLK_TREE_VAL_DEFAULT 0x0
-#define GC_FUSE_DIS_EXT_XTAL_CLK_TREE_VAL_OFFSET 0x120
-#define GC_FUSE_OBFUSCATION_EN_VAL_LSB           0x0
-#define GC_FUSE_OBFUSCATION_EN_VAL_MASK          0x7
-#define GC_FUSE_OBFUSCATION_EN_VAL_SIZE          0x3
-#define GC_FUSE_OBFUSCATION_EN_VAL_DEFAULT       0x0
-#define GC_FUSE_OBFUSCATION_EN_VAL_OFFSET        0x124
-#define GC_FUSE_HIK_CREATE_LOCK_VAL_LSB          0x0
-#define GC_FUSE_HIK_CREATE_LOCK_VAL_MASK         0x7
-#define GC_FUSE_HIK_CREATE_LOCK_VAL_SIZE         0x3
-#define GC_FUSE_HIK_CREATE_LOCK_VAL_DEFAULT      0x0
-#define GC_FUSE_HIK_CREATE_LOCK_VAL_OFFSET       0x128
-#define GC_FUSE_BNK2_INTG_CHKSUM_VAL_LSB         0x0
-#define GC_FUSE_BNK2_INTG_CHKSUM_VAL_MASK        0xffffff
-#define GC_FUSE_BNK2_INTG_CHKSUM_VAL_SIZE        0x18
-#define GC_FUSE_BNK2_INTG_CHKSUM_VAL_DEFAULT     0x0
-#define GC_FUSE_BNK2_INTG_CHKSUM_VAL_OFFSET      0x12c
-#define GC_FUSE_BNK2_INTG_LOCK_VAL_LSB           0x0
-#define GC_FUSE_BNK2_INTG_LOCK_VAL_MASK          0x7
-#define GC_FUSE_BNK2_INTG_LOCK_VAL_SIZE          0x3
-#define GC_FUSE_BNK2_INTG_LOCK_VAL_DEFAULT       0x0
-#define GC_FUSE_BNK2_INTG_LOCK_VAL_OFFSET        0x130
-#define GC_FUSE_TESTMODE_OTPW_DIS_VAL_LSB        0x0
-#define GC_FUSE_TESTMODE_OTPW_DIS_VAL_MASK       0x7
-#define GC_FUSE_TESTMODE_OTPW_DIS_VAL_SIZE       0x3
-#define GC_FUSE_TESTMODE_OTPW_DIS_VAL_DEFAULT    0x0
-#define GC_FUSE_TESTMODE_OTPW_DIS_VAL_OFFSET     0x134
-#define GC_FUSE_HKEY_WDOG_TIMER_EN_VAL_LSB       0x0
-#define GC_FUSE_HKEY_WDOG_TIMER_EN_VAL_MASK      0x7
-#define GC_FUSE_HKEY_WDOG_TIMER_EN_VAL_SIZE      0x3
-#define GC_FUSE_HKEY_WDOG_TIMER_EN_VAL_DEFAULT   0x0
-#define GC_FUSE_HKEY_WDOG_TIMER_EN_VAL_OFFSET    0x138
-#define GC_FUSE_FLASH_PERSO_PAGE_LOCK_VAL_LSB    0x0
-#define GC_FUSE_FLASH_PERSO_PAGE_LOCK_VAL_MASK   0x7
-#define GC_FUSE_FLASH_PERSO_PAGE_LOCK_VAL_SIZE   0x3
-#define GC_FUSE_FLASH_PERSO_PAGE_LOCK_VAL_DEFAULT 0x0
-#define GC_FUSE_FLASH_PERSO_PAGE_LOCK_VAL_OFFSET 0x13c
-#define GC_FUSE_ALERT_RSP_CFG_VAL_LSB            0x0
-#define GC_FUSE_ALERT_RSP_CFG_VAL_MASK           0xff
-#define GC_FUSE_ALERT_RSP_CFG_VAL_SIZE           0x8
-#define GC_FUSE_ALERT_RSP_CFG_VAL_DEFAULT        0x0
-#define GC_FUSE_ALERT_RSP_CFG_VAL_OFFSET         0x140
-#define GC_FUSE_BNK3_INTG_CHKSUM_VAL_LSB         0x0
-#define GC_FUSE_BNK3_INTG_CHKSUM_VAL_MASK        0xffffff
-#define GC_FUSE_BNK3_INTG_CHKSUM_VAL_SIZE        0x18
-#define GC_FUSE_BNK3_INTG_CHKSUM_VAL_DEFAULT     0x0
-#define GC_FUSE_BNK3_INTG_CHKSUM_VAL_OFFSET      0x144
-#define GC_FUSE_BNK3_INTG_LOCK_VAL_LSB           0x0
-#define GC_FUSE_BNK3_INTG_LOCK_VAL_MASK          0x7
-#define GC_FUSE_BNK3_INTG_LOCK_VAL_SIZE          0x3
-#define GC_FUSE_BNK3_INTG_LOCK_VAL_DEFAULT       0x0
-#define GC_FUSE_BNK3_INTG_LOCK_VAL_OFFSET        0x148
-#define GC_FUSE_FW_DEFINED_DATA_BLK0_VAL_LSB     0x0
-#define GC_FUSE_FW_DEFINED_DATA_BLK0_VAL_MASK    0xff
-#define GC_FUSE_FW_DEFINED_DATA_BLK0_VAL_SIZE    0x8
-#define GC_FUSE_FW_DEFINED_DATA_BLK0_VAL_DEFAULT 0x0
-#define GC_FUSE_FW_DEFINED_DATA_BLK0_VAL_OFFSET  0x14c
-#define GC_FUSE_FW_DEFINED_BROM_ERR_RESPONSE_VAL_LSB 0x0
-#define GC_FUSE_FW_DEFINED_BROM_ERR_RESPONSE_VAL_MASK 0xffff
-#define GC_FUSE_FW_DEFINED_BROM_ERR_RESPONSE_VAL_SIZE 0x10
-#define GC_FUSE_FW_DEFINED_BROM_ERR_RESPONSE_VAL_DEFAULT 0x0
-#define GC_FUSE_FW_DEFINED_BROM_ERR_RESPONSE_VAL_OFFSET 0x150
-#define GC_FUSE_FW_DEFINED_BROM_APPLYSEC_VAL_LSB 0x0
-#define GC_FUSE_FW_DEFINED_BROM_APPLYSEC_VAL_MASK 0xfff
-#define GC_FUSE_FW_DEFINED_BROM_APPLYSEC_VAL_SIZE 0xc
-#define GC_FUSE_FW_DEFINED_BROM_APPLYSEC_VAL_DEFAULT 0x0
-#define GC_FUSE_FW_DEFINED_BROM_APPLYSEC_VAL_OFFSET 0x154
-#define GC_FUSE_FW_DEFINED_BROM_CONFIG0_VAL_LSB  0x0
-#define GC_FUSE_FW_DEFINED_BROM_CONFIG0_VAL_MASK 0xff
-#define GC_FUSE_FW_DEFINED_BROM_CONFIG0_VAL_SIZE 0x8
-#define GC_FUSE_FW_DEFINED_BROM_CONFIG0_VAL_DEFAULT 0x0
-#define GC_FUSE_FW_DEFINED_BROM_CONFIG0_VAL_OFFSET 0x158
-#define GC_FUSE_FW_DEFINED_BROM_CONFIG1_VAL_LSB  0x0
-#define GC_FUSE_FW_DEFINED_BROM_CONFIG1_VAL_MASK 0xff
-#define GC_FUSE_FW_DEFINED_BROM_CONFIG1_VAL_SIZE 0x8
-#define GC_FUSE_FW_DEFINED_BROM_CONFIG1_VAL_DEFAULT 0x0
-#define GC_FUSE_FW_DEFINED_BROM_CONFIG1_VAL_OFFSET 0x15c
-#define GC_FUSE_RBOX_MODE_DBG_OVRD_DIS_VAL_LSB   0x0
-#define GC_FUSE_RBOX_MODE_DBG_OVRD_DIS_VAL_MASK  0x1
-#define GC_FUSE_RBOX_MODE_DBG_OVRD_DIS_VAL_SIZE  0x1
-#define GC_FUSE_RBOX_MODE_DBG_OVRD_DIS_VAL_DEFAULT 0x0
-#define GC_FUSE_RBOX_MODE_DBG_OVRD_DIS_VAL_OFFSET 0x160
-#define GC_FUSE_RBOX_MODE_OUTPUT_OVRD_DIS_VAL_LSB 0x0
-#define GC_FUSE_RBOX_MODE_OUTPUT_OVRD_DIS_VAL_MASK 0x7f
-#define GC_FUSE_RBOX_MODE_OUTPUT_OVRD_DIS_VAL_SIZE 0x7
-#define GC_FUSE_RBOX_MODE_OUTPUT_OVRD_DIS_VAL_DEFAULT 0x0
-#define GC_FUSE_RBOX_MODE_OUTPUT_OVRD_DIS_VAL_OFFSET 0x164
-#define GC_FUSE_RBOX_CLK10HZ_COUNT_VAL_LSB       0x0
-#define GC_FUSE_RBOX_CLK10HZ_COUNT_VAL_MASK      0xffff
-#define GC_FUSE_RBOX_CLK10HZ_COUNT_VAL_SIZE      0x10
-#define GC_FUSE_RBOX_CLK10HZ_COUNT_VAL_DEFAULT   0x0
-#define GC_FUSE_RBOX_CLK10HZ_COUNT_VAL_OFFSET    0x168
-#define GC_FUSE_RBOX_SHORT_DELAY_COUNT_VAL_LSB   0x0
-#define GC_FUSE_RBOX_SHORT_DELAY_COUNT_VAL_MASK  0xffff
-#define GC_FUSE_RBOX_SHORT_DELAY_COUNT_VAL_SIZE  0x10
-#define GC_FUSE_RBOX_SHORT_DELAY_COUNT_VAL_DEFAULT 0x0
-#define GC_FUSE_RBOX_SHORT_DELAY_COUNT_VAL_OFFSET 0x16c
-#define GC_FUSE_RBOX_LONG_DELAY_COUNT_VAL_LSB    0x0
-#define GC_FUSE_RBOX_LONG_DELAY_COUNT_VAL_MASK   0xff
-#define GC_FUSE_RBOX_LONG_DELAY_COUNT_VAL_SIZE   0x8
-#define GC_FUSE_RBOX_LONG_DELAY_COUNT_VAL_DEFAULT 0x0
-#define GC_FUSE_RBOX_LONG_DELAY_COUNT_VAL_OFFSET 0x170
-#define GC_FUSE_RBOX_DEBOUNCE_PERIOD_VAL_LSB     0x0
-#define GC_FUSE_RBOX_DEBOUNCE_PERIOD_VAL_MASK    0xffff
-#define GC_FUSE_RBOX_DEBOUNCE_PERIOD_VAL_SIZE    0x10
-#define GC_FUSE_RBOX_DEBOUNCE_PERIOD_VAL_DEFAULT 0x0
-#define GC_FUSE_RBOX_DEBOUNCE_PERIOD_VAL_OFFSET  0x174
-#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_PWRB_VAL_LSB 0x0
-#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_PWRB_VAL_MASK 0x1
-#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_PWRB_VAL_SIZE 0x1
-#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_PWRB_VAL_DEFAULT 0x0
-#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_PWRB_VAL_OFFSET 0x178
-#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY0_VAL_LSB 0x0
-#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY0_VAL_MASK 0x1
-#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY0_VAL_SIZE 0x1
-#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY0_VAL_DEFAULT 0x0
-#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY0_VAL_OFFSET 0x17c
-#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY1_VAL_LSB 0x0
-#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY1_VAL_MASK 0x1
-#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY1_VAL_SIZE 0x1
-#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY1_VAL_DEFAULT 0x0
-#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY1_VAL_OFFSET 0x180
-#define GC_FUSE_RBOX_KEY_COMBO0_VAL_VAL_LSB      0x0
-#define GC_FUSE_RBOX_KEY_COMBO0_VAL_VAL_MASK     0xff
-#define GC_FUSE_RBOX_KEY_COMBO0_VAL_VAL_SIZE     0x8
-#define GC_FUSE_RBOX_KEY_COMBO0_VAL_VAL_DEFAULT  0x0
-#define GC_FUSE_RBOX_KEY_COMBO0_VAL_VAL_OFFSET   0x184
-#define GC_FUSE_RBOX_KEY_COMBO1_VAL_VAL_LSB      0x0
-#define GC_FUSE_RBOX_KEY_COMBO1_VAL_VAL_MASK     0xff
-#define GC_FUSE_RBOX_KEY_COMBO1_VAL_VAL_SIZE     0x8
-#define GC_FUSE_RBOX_KEY_COMBO1_VAL_VAL_DEFAULT  0x0
-#define GC_FUSE_RBOX_KEY_COMBO1_VAL_VAL_OFFSET   0x188
-#define GC_FUSE_RBOX_KEY_COMBO2_VAL_VAL_LSB      0x0
-#define GC_FUSE_RBOX_KEY_COMBO2_VAL_VAL_MASK     0xff
-#define GC_FUSE_RBOX_KEY_COMBO2_VAL_VAL_SIZE     0x8
-#define GC_FUSE_RBOX_KEY_COMBO2_VAL_VAL_DEFAULT  0x0
-#define GC_FUSE_RBOX_KEY_COMBO2_VAL_VAL_OFFSET   0x18c
-#define GC_FUSE_RBOX_KEY_COMBO0_HOLD_VAL_LSB     0x0
-#define GC_FUSE_RBOX_KEY_COMBO0_HOLD_VAL_MASK    0xff
-#define GC_FUSE_RBOX_KEY_COMBO0_HOLD_VAL_SIZE    0x8
-#define GC_FUSE_RBOX_KEY_COMBO0_HOLD_VAL_DEFAULT 0x0
-#define GC_FUSE_RBOX_KEY_COMBO0_HOLD_VAL_OFFSET  0x190
-#define GC_FUSE_RBOX_KEY_COMBO1_HOLD_VAL_LSB     0x0
-#define GC_FUSE_RBOX_KEY_COMBO1_HOLD_VAL_MASK    0xff
-#define GC_FUSE_RBOX_KEY_COMBO1_HOLD_VAL_SIZE    0x8
-#define GC_FUSE_RBOX_KEY_COMBO1_HOLD_VAL_DEFAULT 0x0
-#define GC_FUSE_RBOX_KEY_COMBO1_HOLD_VAL_OFFSET  0x194
-#define GC_FUSE_RBOX_KEY_COMBO2_HOLD_VAL_LSB     0x0
-#define GC_FUSE_RBOX_KEY_COMBO2_HOLD_VAL_MASK    0xff
-#define GC_FUSE_RBOX_KEY_COMBO2_HOLD_VAL_SIZE    0x8
-#define GC_FUSE_RBOX_KEY_COMBO2_HOLD_VAL_DEFAULT 0x0
-#define GC_FUSE_RBOX_KEY_COMBO2_HOLD_VAL_OFFSET  0x198
-#define GC_FUSE_RBOX_BLOCK_KEY0_SEL_VAL_LSB      0x0
-#define GC_FUSE_RBOX_BLOCK_KEY0_SEL_VAL_MASK     0x1
-#define GC_FUSE_RBOX_BLOCK_KEY0_SEL_VAL_SIZE     0x1
-#define GC_FUSE_RBOX_BLOCK_KEY0_SEL_VAL_DEFAULT  0x0
-#define GC_FUSE_RBOX_BLOCK_KEY0_SEL_VAL_OFFSET   0x19c
-#define GC_FUSE_RBOX_BLOCK_KEY1_SEL_VAL_LSB      0x0
-#define GC_FUSE_RBOX_BLOCK_KEY1_SEL_VAL_MASK     0x1
-#define GC_FUSE_RBOX_BLOCK_KEY1_SEL_VAL_SIZE     0x1
-#define GC_FUSE_RBOX_BLOCK_KEY1_SEL_VAL_DEFAULT  0x0
-#define GC_FUSE_RBOX_BLOCK_KEY1_SEL_VAL_OFFSET   0x1a0
-#define GC_FUSE_RBOX_BLOCK_KEY0_VAL_VAL_LSB      0x0
-#define GC_FUSE_RBOX_BLOCK_KEY0_VAL_VAL_MASK     0x1
-#define GC_FUSE_RBOX_BLOCK_KEY0_VAL_VAL_SIZE     0x1
-#define GC_FUSE_RBOX_BLOCK_KEY0_VAL_VAL_DEFAULT  0x0
-#define GC_FUSE_RBOX_BLOCK_KEY0_VAL_VAL_OFFSET   0x1a4
-#define GC_FUSE_RBOX_BLOCK_KEY1_VAL_VAL_LSB      0x0
-#define GC_FUSE_RBOX_BLOCK_KEY1_VAL_VAL_MASK     0x1
-#define GC_FUSE_RBOX_BLOCK_KEY1_VAL_VAL_SIZE     0x1
-#define GC_FUSE_RBOX_BLOCK_KEY1_VAL_VAL_DEFAULT  0x0
-#define GC_FUSE_RBOX_BLOCK_KEY1_VAL_VAL_OFFSET   0x1a8
-#define GC_FUSE_RBOX_POL_AC_PRESENT_VAL_LSB      0x0
-#define GC_FUSE_RBOX_POL_AC_PRESENT_VAL_MASK     0x1
-#define GC_FUSE_RBOX_POL_AC_PRESENT_VAL_SIZE     0x1
-#define GC_FUSE_RBOX_POL_AC_PRESENT_VAL_DEFAULT  0x0
-#define GC_FUSE_RBOX_POL_AC_PRESENT_VAL_OFFSET   0x1ac
-#define GC_FUSE_RBOX_POL_PWRB_IN_VAL_LSB         0x0
-#define GC_FUSE_RBOX_POL_PWRB_IN_VAL_MASK        0x1
-#define GC_FUSE_RBOX_POL_PWRB_IN_VAL_SIZE        0x1
-#define GC_FUSE_RBOX_POL_PWRB_IN_VAL_DEFAULT     0x0
-#define GC_FUSE_RBOX_POL_PWRB_IN_VAL_OFFSET      0x1b0
-#define GC_FUSE_RBOX_POL_PWRB_OUT_VAL_LSB        0x0
-#define GC_FUSE_RBOX_POL_PWRB_OUT_VAL_MASK       0x1
-#define GC_FUSE_RBOX_POL_PWRB_OUT_VAL_SIZE       0x1
-#define GC_FUSE_RBOX_POL_PWRB_OUT_VAL_DEFAULT    0x0
-#define GC_FUSE_RBOX_POL_PWRB_OUT_VAL_OFFSET     0x1b4
-#define GC_FUSE_RBOX_POL_KEY0_IN_VAL_LSB         0x0
-#define GC_FUSE_RBOX_POL_KEY0_IN_VAL_MASK        0x1
-#define GC_FUSE_RBOX_POL_KEY0_IN_VAL_SIZE        0x1
-#define GC_FUSE_RBOX_POL_KEY0_IN_VAL_DEFAULT     0x0
-#define GC_FUSE_RBOX_POL_KEY0_IN_VAL_OFFSET      0x1b8
-#define GC_FUSE_RBOX_POL_KEY0_OUT_VAL_LSB        0x0
-#define GC_FUSE_RBOX_POL_KEY0_OUT_VAL_MASK       0x1
-#define GC_FUSE_RBOX_POL_KEY0_OUT_VAL_SIZE       0x1
-#define GC_FUSE_RBOX_POL_KEY0_OUT_VAL_DEFAULT    0x0
-#define GC_FUSE_RBOX_POL_KEY0_OUT_VAL_OFFSET     0x1bc
-#define GC_FUSE_RBOX_POL_KEY1_IN_VAL_LSB         0x0
-#define GC_FUSE_RBOX_POL_KEY1_IN_VAL_MASK        0x1
-#define GC_FUSE_RBOX_POL_KEY1_IN_VAL_SIZE        0x1
-#define GC_FUSE_RBOX_POL_KEY1_IN_VAL_DEFAULT     0x0
-#define GC_FUSE_RBOX_POL_KEY1_IN_VAL_OFFSET      0x1c0
-#define GC_FUSE_RBOX_POL_KEY1_OUT_VAL_LSB        0x0
-#define GC_FUSE_RBOX_POL_KEY1_OUT_VAL_MASK       0x1
-#define GC_FUSE_RBOX_POL_KEY1_OUT_VAL_SIZE       0x1
-#define GC_FUSE_RBOX_POL_KEY1_OUT_VAL_DEFAULT    0x0
-#define GC_FUSE_RBOX_POL_KEY1_OUT_VAL_OFFSET     0x1c4
-#define GC_FUSE_RBOX_POL_EC_RST_VAL_LSB          0x0
-#define GC_FUSE_RBOX_POL_EC_RST_VAL_MASK         0x1
-#define GC_FUSE_RBOX_POL_EC_RST_VAL_SIZE         0x1
-#define GC_FUSE_RBOX_POL_EC_RST_VAL_DEFAULT      0x0
-#define GC_FUSE_RBOX_POL_EC_RST_VAL_OFFSET       0x1c8
-#define GC_FUSE_RBOX_POL_BATT_DISABLE_VAL_LSB    0x0
-#define GC_FUSE_RBOX_POL_BATT_DISABLE_VAL_MASK   0x1
-#define GC_FUSE_RBOX_POL_BATT_DISABLE_VAL_SIZE   0x1
-#define GC_FUSE_RBOX_POL_BATT_DISABLE_VAL_DEFAULT 0x0
-#define GC_FUSE_RBOX_POL_BATT_DISABLE_VAL_OFFSET 0x1cc
-#define GC_FUSE_RBOX_TERM_AC_PRESENT_VAL_LSB     0x0
-#define GC_FUSE_RBOX_TERM_AC_PRESENT_VAL_MASK    0x3
-#define GC_FUSE_RBOX_TERM_AC_PRESENT_VAL_SIZE    0x2
-#define GC_FUSE_RBOX_TERM_AC_PRESENT_VAL_DEFAULT 0x0
-#define GC_FUSE_RBOX_TERM_AC_PRESENT_VAL_OFFSET  0x1d0
-#define GC_FUSE_RBOX_TERM_ENTERING_RW_VAL_LSB    0x0
-#define GC_FUSE_RBOX_TERM_ENTERING_RW_VAL_MASK   0x3
-#define GC_FUSE_RBOX_TERM_ENTERING_RW_VAL_SIZE   0x2
-#define GC_FUSE_RBOX_TERM_ENTERING_RW_VAL_DEFAULT 0x0
-#define GC_FUSE_RBOX_TERM_ENTERING_RW_VAL_OFFSET 0x1d4
-#define GC_FUSE_RBOX_TERM_PWRB_IN_VAL_LSB        0x0
-#define GC_FUSE_RBOX_TERM_PWRB_IN_VAL_MASK       0x3
-#define GC_FUSE_RBOX_TERM_PWRB_IN_VAL_SIZE       0x2
-#define GC_FUSE_RBOX_TERM_PWRB_IN_VAL_DEFAULT    0x0
-#define GC_FUSE_RBOX_TERM_PWRB_IN_VAL_OFFSET     0x1d8
-#define GC_FUSE_RBOX_TERM_PWRB_OUT_VAL_LSB       0x0
-#define GC_FUSE_RBOX_TERM_PWRB_OUT_VAL_MASK      0x3
-#define GC_FUSE_RBOX_TERM_PWRB_OUT_VAL_SIZE      0x2
-#define GC_FUSE_RBOX_TERM_PWRB_OUT_VAL_DEFAULT   0x0
-#define GC_FUSE_RBOX_TERM_PWRB_OUT_VAL_OFFSET    0x1dc
-#define GC_FUSE_RBOX_TERM_KEY0_IN_VAL_LSB        0x0
-#define GC_FUSE_RBOX_TERM_KEY0_IN_VAL_MASK       0x3
-#define GC_FUSE_RBOX_TERM_KEY0_IN_VAL_SIZE       0x2
-#define GC_FUSE_RBOX_TERM_KEY0_IN_VAL_DEFAULT    0x0
-#define GC_FUSE_RBOX_TERM_KEY0_IN_VAL_OFFSET     0x1e0
-#define GC_FUSE_RBOX_TERM_KEY0_OUT_VAL_LSB       0x0
-#define GC_FUSE_RBOX_TERM_KEY0_OUT_VAL_MASK      0x3
-#define GC_FUSE_RBOX_TERM_KEY0_OUT_VAL_SIZE      0x2
-#define GC_FUSE_RBOX_TERM_KEY0_OUT_VAL_DEFAULT   0x0
-#define GC_FUSE_RBOX_TERM_KEY0_OUT_VAL_OFFSET    0x1e4
-#define GC_FUSE_RBOX_TERM_KEY1_IN_VAL_LSB        0x0
-#define GC_FUSE_RBOX_TERM_KEY1_IN_VAL_MASK       0x3
-#define GC_FUSE_RBOX_TERM_KEY1_IN_VAL_SIZE       0x2
-#define GC_FUSE_RBOX_TERM_KEY1_IN_VAL_DEFAULT    0x0
-#define GC_FUSE_RBOX_TERM_KEY1_IN_VAL_OFFSET     0x1e8
-#define GC_FUSE_RBOX_TERM_KEY1_OUT_VAL_LSB       0x0
-#define GC_FUSE_RBOX_TERM_KEY1_OUT_VAL_MASK      0x3
-#define GC_FUSE_RBOX_TERM_KEY1_OUT_VAL_SIZE      0x2
-#define GC_FUSE_RBOX_TERM_KEY1_OUT_VAL_DEFAULT   0x0
-#define GC_FUSE_RBOX_TERM_KEY1_OUT_VAL_OFFSET    0x1ec
-#define GC_FUSE_RBOX_DRIVE_PWRB_OUT_VAL_LSB      0x0
-#define GC_FUSE_RBOX_DRIVE_PWRB_OUT_VAL_MASK     0x3
-#define GC_FUSE_RBOX_DRIVE_PWRB_OUT_VAL_SIZE     0x2
-#define GC_FUSE_RBOX_DRIVE_PWRB_OUT_VAL_DEFAULT  0x0
-#define GC_FUSE_RBOX_DRIVE_PWRB_OUT_VAL_OFFSET   0x1f0
-#define GC_FUSE_RBOX_DRIVE_KEY0_OUT_VAL_LSB      0x0
-#define GC_FUSE_RBOX_DRIVE_KEY0_OUT_VAL_MASK     0x3
-#define GC_FUSE_RBOX_DRIVE_KEY0_OUT_VAL_SIZE     0x2
-#define GC_FUSE_RBOX_DRIVE_KEY0_OUT_VAL_DEFAULT  0x0
-#define GC_FUSE_RBOX_DRIVE_KEY0_OUT_VAL_OFFSET   0x1f4
-#define GC_FUSE_RBOX_DRIVE_KEY1_OUT_VAL_LSB      0x0
-#define GC_FUSE_RBOX_DRIVE_KEY1_OUT_VAL_MASK     0x3
-#define GC_FUSE_RBOX_DRIVE_KEY1_OUT_VAL_SIZE     0x2
-#define GC_FUSE_RBOX_DRIVE_KEY1_OUT_VAL_DEFAULT  0x0
-#define GC_FUSE_RBOX_DRIVE_KEY1_OUT_VAL_OFFSET   0x1f8
-#define GC_FUSE_RBOX_DRIVE_EC_RST_VAL_LSB        0x0
-#define GC_FUSE_RBOX_DRIVE_EC_RST_VAL_MASK       0x3
-#define GC_FUSE_RBOX_DRIVE_EC_RST_VAL_SIZE       0x2
-#define GC_FUSE_RBOX_DRIVE_EC_RST_VAL_DEFAULT    0x0
-#define GC_FUSE_RBOX_DRIVE_EC_RST_VAL_OFFSET     0x1fc
-#define GC_FUSE_RBOX_DRIVE_BATT_DISABLE_VAL_LSB  0x0
-#define GC_FUSE_RBOX_DRIVE_BATT_DISABLE_VAL_MASK 0x3
-#define GC_FUSE_RBOX_DRIVE_BATT_DISABLE_VAL_SIZE 0x2
-#define GC_FUSE_RBOX_DRIVE_BATT_DISABLE_VAL_DEFAULT 0x0
-#define GC_FUSE_RBOX_DRIVE_BATT_DISABLE_VAL_OFFSET 0x200
-#define GC_FUSE_BNK4_INTG_CHKSUM_VAL_LSB         0x0
-#define GC_FUSE_BNK4_INTG_CHKSUM_VAL_MASK        0xffffff
-#define GC_FUSE_BNK4_INTG_CHKSUM_VAL_SIZE        0x18
-#define GC_FUSE_BNK4_INTG_CHKSUM_VAL_DEFAULT     0x0
-#define GC_FUSE_BNK4_INTG_CHKSUM_VAL_OFFSET      0x204
-#define GC_FUSE_BNK4_INTG_LOCK_VAL_LSB           0x0
-#define GC_FUSE_BNK4_INTG_LOCK_VAL_MASK          0x7
-#define GC_FUSE_BNK4_INTG_LOCK_VAL_SIZE          0x3
-#define GC_FUSE_BNK4_INTG_LOCK_VAL_DEFAULT       0x0
-#define GC_FUSE_BNK4_INTG_LOCK_VAL_OFFSET        0x208
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK0_VAL_LSB 0x0
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK0_VAL_MASK 0xff
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK0_VAL_SIZE 0x8
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK0_VAL_DEFAULT 0x0
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK0_VAL_OFFSET 0x20c
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK1_VAL_LSB 0x0
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK1_VAL_MASK 0xff
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK1_VAL_SIZE 0x8
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK1_VAL_DEFAULT 0x0
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK1_VAL_OFFSET 0x210
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK2_VAL_LSB 0x0
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK2_VAL_MASK 0xff
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK2_VAL_SIZE 0x8
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK2_VAL_DEFAULT 0x0
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK2_VAL_OFFSET 0x214
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK3_VAL_LSB 0x0
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK3_VAL_MASK 0xff
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK3_VAL_SIZE 0x8
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK3_VAL_DEFAULT 0x0
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK3_VAL_OFFSET 0x218
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK4_VAL_LSB 0x0
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK4_VAL_MASK 0xff
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK4_VAL_SIZE 0x8
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK4_VAL_DEFAULT 0x0
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK4_VAL_OFFSET 0x21c
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK5_VAL_LSB 0x0
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK5_VAL_MASK 0xff
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK5_VAL_SIZE 0x8
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK5_VAL_DEFAULT 0x0
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK5_VAL_OFFSET 0x220
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK6_VAL_LSB 0x0
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK6_VAL_MASK 0x1f
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK6_VAL_SIZE 0x5
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK6_VAL_DEFAULT 0x0
-#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK6_VAL_OFFSET 0x224
-#define GC_FUSE_PROG_BNK0_INTG_CHKSUM_VAL_LSB    0x0
-#define GC_FUSE_PROG_BNK0_INTG_CHKSUM_VAL_MASK   0xffffff
-#define GC_FUSE_PROG_BNK0_INTG_CHKSUM_VAL_SIZE   0x18
-#define GC_FUSE_PROG_BNK0_INTG_CHKSUM_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_BNK0_INTG_CHKSUM_VAL_OFFSET 0x228
-#define GC_FUSE_PROG_BNK0_INTG_LOCK_VAL_LSB      0x0
-#define GC_FUSE_PROG_BNK0_INTG_LOCK_VAL_MASK     0x7
-#define GC_FUSE_PROG_BNK0_INTG_LOCK_VAL_SIZE     0x3
-#define GC_FUSE_PROG_BNK0_INTG_LOCK_VAL_DEFAULT  0x0
-#define GC_FUSE_PROG_BNK0_INTG_LOCK_VAL_OFFSET   0x22c
-#define GC_FUSE_PROG_DS_GRP0_VAL_LSB             0x0
-#define GC_FUSE_PROG_DS_GRP0_VAL_MASK            0x1ff
-#define GC_FUSE_PROG_DS_GRP0_VAL_SIZE            0x9
-#define GC_FUSE_PROG_DS_GRP0_VAL_DEFAULT         0x0
-#define GC_FUSE_PROG_DS_GRP0_VAL_OFFSET          0x230
-#define GC_FUSE_PROG_DS_GRP1_VAL_LSB             0x0
-#define GC_FUSE_PROG_DS_GRP1_VAL_MASK            0x1ff
-#define GC_FUSE_PROG_DS_GRP1_VAL_SIZE            0x9
-#define GC_FUSE_PROG_DS_GRP1_VAL_DEFAULT         0x0
-#define GC_FUSE_PROG_DS_GRP1_VAL_OFFSET          0x234
-#define GC_FUSE_PROG_DS_GRP2_VAL_LSB             0x0
-#define GC_FUSE_PROG_DS_GRP2_VAL_MASK            0x1ff
-#define GC_FUSE_PROG_DS_GRP2_VAL_SIZE            0x9
-#define GC_FUSE_PROG_DS_GRP2_VAL_DEFAULT         0x0
-#define GC_FUSE_PROG_DS_GRP2_VAL_OFFSET          0x238
-#define GC_FUSE_PROG_DEV_ID0_VAL_LSB             0x0
-#define GC_FUSE_PROG_DEV_ID0_VAL_MASK            0xffffffff
-#define GC_FUSE_PROG_DEV_ID0_VAL_SIZE            0x20
-#define GC_FUSE_PROG_DEV_ID0_VAL_DEFAULT         0x0
-#define GC_FUSE_PROG_DEV_ID0_VAL_OFFSET          0x23c
-#define GC_FUSE_PROG_DEV_ID1_VAL_LSB             0x0
-#define GC_FUSE_PROG_DEV_ID1_VAL_MASK            0xffffffff
-#define GC_FUSE_PROG_DEV_ID1_VAL_SIZE            0x20
-#define GC_FUSE_PROG_DEV_ID1_VAL_DEFAULT         0x0
-#define GC_FUSE_PROG_DEV_ID1_VAL_OFFSET          0x240
-#define GC_FUSE_PROG_BNK1_INTG_CHKSUM_VAL_LSB    0x0
-#define GC_FUSE_PROG_BNK1_INTG_CHKSUM_VAL_MASK   0xffffff
-#define GC_FUSE_PROG_BNK1_INTG_CHKSUM_VAL_SIZE   0x18
-#define GC_FUSE_PROG_BNK1_INTG_CHKSUM_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_BNK1_INTG_CHKSUM_VAL_OFFSET 0x244
-#define GC_FUSE_PROG_BNK1_INTG_LOCK_VAL_LSB      0x0
-#define GC_FUSE_PROG_BNK1_INTG_LOCK_VAL_MASK     0x7
-#define GC_FUSE_PROG_BNK1_INTG_LOCK_VAL_SIZE     0x3
-#define GC_FUSE_PROG_BNK1_INTG_LOCK_VAL_DEFAULT  0x0
-#define GC_FUSE_PROG_BNK1_INTG_LOCK_VAL_OFFSET   0x248
-#define GC_FUSE_PROG_LB0_POST_OVRD_VAL_LSB       0x0
-#define GC_FUSE_PROG_LB0_POST_OVRD_VAL_MASK      0x7
-#define GC_FUSE_PROG_LB0_POST_OVRD_VAL_SIZE      0x3
-#define GC_FUSE_PROG_LB0_POST_OVRD_VAL_DEFAULT   0x0
-#define GC_FUSE_PROG_LB0_POST_OVRD_VAL_OFFSET    0x24c
-#define GC_FUSE_PROG_LB0_POST_PATCNT_VAL_LSB     0x0
-#define GC_FUSE_PROG_LB0_POST_PATCNT_VAL_MASK    0x3
-#define GC_FUSE_PROG_LB0_POST_PATCNT_VAL_SIZE    0x2
-#define GC_FUSE_PROG_LB0_POST_PATCNT_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_LB0_POST_PATCNT_VAL_OFFSET  0x250
-#define GC_FUSE_PROG_LB0_POST_WARMUP_OVRD_VAL_LSB 0x0
-#define GC_FUSE_PROG_LB0_POST_WARMUP_OVRD_VAL_MASK 0x7
-#define GC_FUSE_PROG_LB0_POST_WARMUP_OVRD_VAL_SIZE 0x3
-#define GC_FUSE_PROG_LB0_POST_WARMUP_OVRD_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_LB0_POST_WARMUP_OVRD_VAL_OFFSET 0x254
-#define GC_FUSE_PROG_LB0_POST_WARMUP_CNT_VAL_LSB 0x0
-#define GC_FUSE_PROG_LB0_POST_WARMUP_CNT_VAL_MASK 0x3
-#define GC_FUSE_PROG_LB0_POST_WARMUP_CNT_VAL_SIZE 0x2
-#define GC_FUSE_PROG_LB0_POST_WARMUP_CNT_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_LB0_POST_WARMUP_CNT_VAL_OFFSET 0x258
-#define GC_FUSE_PROG_LB1_POST_OVRD_VAL_LSB       0x0
-#define GC_FUSE_PROG_LB1_POST_OVRD_VAL_MASK      0x7
-#define GC_FUSE_PROG_LB1_POST_OVRD_VAL_SIZE      0x3
-#define GC_FUSE_PROG_LB1_POST_OVRD_VAL_DEFAULT   0x0
-#define GC_FUSE_PROG_LB1_POST_OVRD_VAL_OFFSET    0x25c
-#define GC_FUSE_PROG_LB1_POST_PATCNT_VAL_LSB     0x0
-#define GC_FUSE_PROG_LB1_POST_PATCNT_VAL_MASK    0x3
-#define GC_FUSE_PROG_LB1_POST_PATCNT_VAL_SIZE    0x2
-#define GC_FUSE_PROG_LB1_POST_PATCNT_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_LB1_POST_PATCNT_VAL_OFFSET  0x260
-#define GC_FUSE_PROG_LB1_POST_WARMUP_OVRD_VAL_LSB 0x0
-#define GC_FUSE_PROG_LB1_POST_WARMUP_OVRD_VAL_MASK 0x7
-#define GC_FUSE_PROG_LB1_POST_WARMUP_OVRD_VAL_SIZE 0x3
-#define GC_FUSE_PROG_LB1_POST_WARMUP_OVRD_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_LB1_POST_WARMUP_OVRD_VAL_OFFSET 0x264
-#define GC_FUSE_PROG_LB1_POST_WARMUP_CNT_VAL_LSB 0x0
-#define GC_FUSE_PROG_LB1_POST_WARMUP_CNT_VAL_MASK 0x3
-#define GC_FUSE_PROG_LB1_POST_WARMUP_CNT_VAL_SIZE 0x2
-#define GC_FUSE_PROG_LB1_POST_WARMUP_CNT_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_LB1_POST_WARMUP_CNT_VAL_OFFSET 0x268
-#define GC_FUSE_PROG_LB2_POST_OVRD_VAL_LSB       0x0
-#define GC_FUSE_PROG_LB2_POST_OVRD_VAL_MASK      0x7
-#define GC_FUSE_PROG_LB2_POST_OVRD_VAL_SIZE      0x3
-#define GC_FUSE_PROG_LB2_POST_OVRD_VAL_DEFAULT   0x0
-#define GC_FUSE_PROG_LB2_POST_OVRD_VAL_OFFSET    0x26c
-#define GC_FUSE_PROG_LB2_POST_PATCNT_VAL_LSB     0x0
-#define GC_FUSE_PROG_LB2_POST_PATCNT_VAL_MASK    0x3
-#define GC_FUSE_PROG_LB2_POST_PATCNT_VAL_SIZE    0x2
-#define GC_FUSE_PROG_LB2_POST_PATCNT_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_LB2_POST_PATCNT_VAL_OFFSET  0x270
-#define GC_FUSE_PROG_LB2_POST_WARMUP_OVRD_VAL_LSB 0x0
-#define GC_FUSE_PROG_LB2_POST_WARMUP_OVRD_VAL_MASK 0x7
-#define GC_FUSE_PROG_LB2_POST_WARMUP_OVRD_VAL_SIZE 0x3
-#define GC_FUSE_PROG_LB2_POST_WARMUP_OVRD_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_LB2_POST_WARMUP_OVRD_VAL_OFFSET 0x274
-#define GC_FUSE_PROG_LB2_POST_WARMUP_CNT_VAL_LSB 0x0
-#define GC_FUSE_PROG_LB2_POST_WARMUP_CNT_VAL_MASK 0x3
-#define GC_FUSE_PROG_LB2_POST_WARMUP_CNT_VAL_SIZE 0x2
-#define GC_FUSE_PROG_LB2_POST_WARMUP_CNT_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_LB2_POST_WARMUP_CNT_VAL_OFFSET 0x278
-#define GC_FUSE_PROG_LB3_POST_OVRD_VAL_LSB       0x0
-#define GC_FUSE_PROG_LB3_POST_OVRD_VAL_MASK      0x7
-#define GC_FUSE_PROG_LB3_POST_OVRD_VAL_SIZE      0x3
-#define GC_FUSE_PROG_LB3_POST_OVRD_VAL_DEFAULT   0x0
-#define GC_FUSE_PROG_LB3_POST_OVRD_VAL_OFFSET    0x27c
-#define GC_FUSE_PROG_LB3_POST_PATCNT_VAL_LSB     0x0
-#define GC_FUSE_PROG_LB3_POST_PATCNT_VAL_MASK    0x3
-#define GC_FUSE_PROG_LB3_POST_PATCNT_VAL_SIZE    0x2
-#define GC_FUSE_PROG_LB3_POST_PATCNT_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_LB3_POST_PATCNT_VAL_OFFSET  0x280
-#define GC_FUSE_PROG_LB3_POST_WARMUP_OVRD_VAL_LSB 0x0
-#define GC_FUSE_PROG_LB3_POST_WARMUP_OVRD_VAL_MASK 0x7
-#define GC_FUSE_PROG_LB3_POST_WARMUP_OVRD_VAL_SIZE 0x3
-#define GC_FUSE_PROG_LB3_POST_WARMUP_OVRD_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_LB3_POST_WARMUP_OVRD_VAL_OFFSET 0x284
-#define GC_FUSE_PROG_LB3_POST_WARMUP_CNT_VAL_LSB 0x0
-#define GC_FUSE_PROG_LB3_POST_WARMUP_CNT_VAL_MASK 0x3
-#define GC_FUSE_PROG_LB3_POST_WARMUP_CNT_VAL_SIZE 0x2
-#define GC_FUSE_PROG_LB3_POST_WARMUP_CNT_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_LB3_POST_WARMUP_CNT_VAL_OFFSET 0x288
-#define GC_FUSE_PROG_LB4_POST_OVRD_VAL_LSB       0x0
-#define GC_FUSE_PROG_LB4_POST_OVRD_VAL_MASK      0x7
-#define GC_FUSE_PROG_LB4_POST_OVRD_VAL_SIZE      0x3
-#define GC_FUSE_PROG_LB4_POST_OVRD_VAL_DEFAULT   0x0
-#define GC_FUSE_PROG_LB4_POST_OVRD_VAL_OFFSET    0x28c
-#define GC_FUSE_PROG_LB4_POST_PATCNT_VAL_LSB     0x0
-#define GC_FUSE_PROG_LB4_POST_PATCNT_VAL_MASK    0x3
-#define GC_FUSE_PROG_LB4_POST_PATCNT_VAL_SIZE    0x2
-#define GC_FUSE_PROG_LB4_POST_PATCNT_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_LB4_POST_PATCNT_VAL_OFFSET  0x290
-#define GC_FUSE_PROG_LB4_POST_WARMUP_OVRD_VAL_LSB 0x0
-#define GC_FUSE_PROG_LB4_POST_WARMUP_OVRD_VAL_MASK 0x7
-#define GC_FUSE_PROG_LB4_POST_WARMUP_OVRD_VAL_SIZE 0x3
-#define GC_FUSE_PROG_LB4_POST_WARMUP_OVRD_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_LB4_POST_WARMUP_OVRD_VAL_OFFSET 0x294
-#define GC_FUSE_PROG_LB4_POST_WARMUP_CNT_VAL_LSB 0x0
-#define GC_FUSE_PROG_LB4_POST_WARMUP_CNT_VAL_MASK 0x3
-#define GC_FUSE_PROG_LB4_POST_WARMUP_CNT_VAL_SIZE 0x2
-#define GC_FUSE_PROG_LB4_POST_WARMUP_CNT_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_LB4_POST_WARMUP_CNT_VAL_OFFSET 0x298
-#define GC_FUSE_PROG_MBIST_POST_SEQ_VAL_LSB      0x0
-#define GC_FUSE_PROG_MBIST_POST_SEQ_VAL_MASK     0x1ffffff
-#define GC_FUSE_PROG_MBIST_POST_SEQ_VAL_SIZE     0x19
-#define GC_FUSE_PROG_MBIST_POST_SEQ_VAL_DEFAULT  0x0
-#define GC_FUSE_PROG_MBIST_POST_SEQ_VAL_OFFSET   0x29c
-#define GC_FUSE_PROG_LBIST_POST_SEQ_VAL_LSB      0x0
-#define GC_FUSE_PROG_LBIST_POST_SEQ_VAL_MASK     0x1ffffff
-#define GC_FUSE_PROG_LBIST_POST_SEQ_VAL_SIZE     0x19
-#define GC_FUSE_PROG_LBIST_POST_SEQ_VAL_DEFAULT  0x0
-#define GC_FUSE_PROG_LBIST_POST_SEQ_VAL_OFFSET   0x2a0
-#define GC_FUSE_PROG_LBIST_VIA_TAP_DIS_VAL_LSB   0x0
-#define GC_FUSE_PROG_LBIST_VIA_TAP_DIS_VAL_MASK  0x7
-#define GC_FUSE_PROG_LBIST_VIA_TAP_DIS_VAL_SIZE  0x3
-#define GC_FUSE_PROG_LBIST_VIA_TAP_DIS_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_LBIST_VIA_TAP_DIS_VAL_OFFSET 0x2a4
-#define GC_FUSE_PROG_MBIST_VIA_TAP_DIS_VAL_LSB   0x0
-#define GC_FUSE_PROG_MBIST_VIA_TAP_DIS_VAL_MASK  0x7
-#define GC_FUSE_PROG_MBIST_VIA_TAP_DIS_VAL_SIZE  0x3
-#define GC_FUSE_PROG_MBIST_VIA_TAP_DIS_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_MBIST_VIA_TAP_DIS_VAL_OFFSET 0x2a8
-#define GC_FUSE_PROG_MBIST_BOOTROM_MISR_EN_VAL_LSB 0x0
-#define GC_FUSE_PROG_MBIST_BOOTROM_MISR_EN_VAL_MASK 0x7
-#define GC_FUSE_PROG_MBIST_BOOTROM_MISR_EN_VAL_SIZE 0x3
-#define GC_FUSE_PROG_MBIST_BOOTROM_MISR_EN_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_MBIST_BOOTROM_MISR_EN_VAL_OFFSET 0x2ac
-#define GC_FUSE_PROG_MBIST_BOOTROM_MISR_VAL_LSB  0x0
-#define GC_FUSE_PROG_MBIST_BOOTROM_MISR_VAL_MASK 0xffffffff
-#define GC_FUSE_PROG_MBIST_BOOTROM_MISR_VAL_SIZE 0x20
-#define GC_FUSE_PROG_MBIST_BOOTROM_MISR_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_MBIST_BOOTROM_MISR_VAL_OFFSET 0x2b0
-#define GC_FUSE_PROG_TAP_DISABLE_VAL_LSB         0x0
-#define GC_FUSE_PROG_TAP_DISABLE_VAL_MASK        0x7
-#define GC_FUSE_PROG_TAP_DISABLE_VAL_SIZE        0x3
-#define GC_FUSE_PROG_TAP_DISABLE_VAL_DEFAULT     0x0
-#define GC_FUSE_PROG_TAP_DISABLE_VAL_OFFSET      0x2b4
-#define GC_FUSE_PROG_RNGBIST_AR_EN_VAL_LSB       0x0
-#define GC_FUSE_PROG_RNGBIST_AR_EN_VAL_MASK      0x7
-#define GC_FUSE_PROG_RNGBIST_AR_EN_VAL_SIZE      0x3
-#define GC_FUSE_PROG_RNGBIST_AR_EN_VAL_DEFAULT   0x0
-#define GC_FUSE_PROG_RNGBIST_AR_EN_VAL_OFFSET    0x2b8
-#define GC_FUSE_PROG_TESTMODE_KEYS_EN_VAL_LSB    0x0
-#define GC_FUSE_PROG_TESTMODE_KEYS_EN_VAL_MASK   0x7
-#define GC_FUSE_PROG_TESTMODE_KEYS_EN_VAL_SIZE   0x3
-#define GC_FUSE_PROG_TESTMODE_KEYS_EN_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_TESTMODE_KEYS_EN_VAL_OFFSET 0x2bc
-#define GC_FUSE_PROG_PKG_ID_VAL_LSB              0x0
-#define GC_FUSE_PROG_PKG_ID_VAL_MASK             0x7
-#define GC_FUSE_PROG_PKG_ID_VAL_SIZE             0x3
-#define GC_FUSE_PROG_PKG_ID_VAL_DEFAULT          0x0
-#define GC_FUSE_PROG_PKG_ID_VAL_OFFSET           0x2c0
-#define GC_FUSE_PROG_BIN_ID_VAL_LSB              0x0
-#define GC_FUSE_PROG_BIN_ID_VAL_MASK             0x7
-#define GC_FUSE_PROG_BIN_ID_VAL_SIZE             0x3
-#define GC_FUSE_PROG_BIN_ID_VAL_DEFAULT          0x0
-#define GC_FUSE_PROG_BIN_ID_VAL_OFFSET           0x2c4
-#define GC_FUSE_PROG_RC_JTR_OSC48_CC_TRIM_VAL_LSB 0x0
-#define GC_FUSE_PROG_RC_JTR_OSC48_CC_TRIM_VAL_MASK 0xff
-#define GC_FUSE_PROG_RC_JTR_OSC48_CC_TRIM_VAL_SIZE 0x8
-#define GC_FUSE_PROG_RC_JTR_OSC48_CC_TRIM_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RC_JTR_OSC48_CC_TRIM_VAL_OFFSET 0x2c8
-#define GC_FUSE_PROG_RC_JTR_OSC48_CC_EN_VAL_LSB  0x0
-#define GC_FUSE_PROG_RC_JTR_OSC48_CC_EN_VAL_MASK 0x7
-#define GC_FUSE_PROG_RC_JTR_OSC48_CC_EN_VAL_SIZE 0x3
-#define GC_FUSE_PROG_RC_JTR_OSC48_CC_EN_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RC_JTR_OSC48_CC_EN_VAL_OFFSET 0x2cc
-#define GC_FUSE_PROG_RC_JTR_OSC60_CC_TRIM_VAL_LSB 0x0
-#define GC_FUSE_PROG_RC_JTR_OSC60_CC_TRIM_VAL_MASK 0xff
-#define GC_FUSE_PROG_RC_JTR_OSC60_CC_TRIM_VAL_SIZE 0x8
-#define GC_FUSE_PROG_RC_JTR_OSC60_CC_TRIM_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RC_JTR_OSC60_CC_TRIM_VAL_OFFSET 0x2d0
-#define GC_FUSE_PROG_RC_JTR_OSC60_CC_EN_VAL_LSB  0x0
-#define GC_FUSE_PROG_RC_JTR_OSC60_CC_EN_VAL_MASK 0x7
-#define GC_FUSE_PROG_RC_JTR_OSC60_CC_EN_VAL_SIZE 0x3
-#define GC_FUSE_PROG_RC_JTR_OSC60_CC_EN_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RC_JTR_OSC60_CC_EN_VAL_OFFSET 0x2d4
-#define GC_FUSE_PROG_RC_TIMER_OSC48_CC_TRIM_VAL_LSB 0x0
-#define GC_FUSE_PROG_RC_TIMER_OSC48_CC_TRIM_VAL_MASK 0xff
-#define GC_FUSE_PROG_RC_TIMER_OSC48_CC_TRIM_VAL_SIZE 0x8
-#define GC_FUSE_PROG_RC_TIMER_OSC48_CC_TRIM_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RC_TIMER_OSC48_CC_TRIM_VAL_OFFSET 0x2d8
-#define GC_FUSE_PROG_RC_TIMER_OSC48_CC_EN_VAL_LSB 0x0
-#define GC_FUSE_PROG_RC_TIMER_OSC48_CC_EN_VAL_MASK 0x7
-#define GC_FUSE_PROG_RC_TIMER_OSC48_CC_EN_VAL_SIZE 0x3
-#define GC_FUSE_PROG_RC_TIMER_OSC48_CC_EN_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RC_TIMER_OSC48_CC_EN_VAL_OFFSET 0x2dc
-#define GC_FUSE_PROG_RC_TIMER_OSC48_FC_TRIM_VAL_LSB 0x0
-#define GC_FUSE_PROG_RC_TIMER_OSC48_FC_TRIM_VAL_MASK 0x1f
-#define GC_FUSE_PROG_RC_TIMER_OSC48_FC_TRIM_VAL_SIZE 0x5
-#define GC_FUSE_PROG_RC_TIMER_OSC48_FC_TRIM_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RC_TIMER_OSC48_FC_TRIM_VAL_OFFSET 0x2e0
-#define GC_FUSE_PROG_RC_TIMER_OSC48_FC_EN_VAL_LSB 0x0
-#define GC_FUSE_PROG_RC_TIMER_OSC48_FC_EN_VAL_MASK 0x7
-#define GC_FUSE_PROG_RC_TIMER_OSC48_FC_EN_VAL_SIZE 0x3
-#define GC_FUSE_PROG_RC_TIMER_OSC48_FC_EN_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RC_TIMER_OSC48_FC_EN_VAL_OFFSET 0x2e4
-#define GC_FUSE_PROG_RC_RTC_OSC256K_CC_TRIM_VAL_LSB 0x0
-#define GC_FUSE_PROG_RC_RTC_OSC256K_CC_TRIM_VAL_MASK 0xff
-#define GC_FUSE_PROG_RC_RTC_OSC256K_CC_TRIM_VAL_SIZE 0x8
-#define GC_FUSE_PROG_RC_RTC_OSC256K_CC_TRIM_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RC_RTC_OSC256K_CC_TRIM_VAL_OFFSET 0x2e8
-#define GC_FUSE_PROG_RC_RTC_OSC256K_CC_EN_VAL_LSB 0x0
-#define GC_FUSE_PROG_RC_RTC_OSC256K_CC_EN_VAL_MASK 0x7
-#define GC_FUSE_PROG_RC_RTC_OSC256K_CC_EN_VAL_SIZE 0x3
-#define GC_FUSE_PROG_RC_RTC_OSC256K_CC_EN_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RC_RTC_OSC256K_CC_EN_VAL_OFFSET 0x2ec
-#define GC_FUSE_PROG_SEL_VREG_REG_EN_VAL_LSB     0x0
-#define GC_FUSE_PROG_SEL_VREG_REG_EN_VAL_MASK    0x7
-#define GC_FUSE_PROG_SEL_VREG_REG_EN_VAL_SIZE    0x3
-#define GC_FUSE_PROG_SEL_VREG_REG_EN_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_SEL_VREG_REG_EN_VAL_OFFSET  0x2f0
-#define GC_FUSE_PROG_SEL_VREF_REG_VAL_LSB        0x0
-#define GC_FUSE_PROG_SEL_VREF_REG_VAL_MASK       0xf
-#define GC_FUSE_PROG_SEL_VREF_REG_VAL_SIZE       0x4
-#define GC_FUSE_PROG_SEL_VREF_REG_VAL_DEFAULT    0x0
-#define GC_FUSE_PROG_SEL_VREF_REG_VAL_OFFSET     0x2f4
-#define GC_FUSE_PROG_SEL_VREF_BATMON_EN_VAL_LSB  0x0
-#define GC_FUSE_PROG_SEL_VREF_BATMON_EN_VAL_MASK 0x7
-#define GC_FUSE_PROG_SEL_VREF_BATMON_EN_VAL_SIZE 0x3
-#define GC_FUSE_PROG_SEL_VREF_BATMON_EN_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_SEL_VREF_BATMON_EN_VAL_OFFSET 0x2f8
-#define GC_FUSE_PROG_SEL_VREF_BATMON_VAL_LSB     0x0
-#define GC_FUSE_PROG_SEL_VREF_BATMON_VAL_MASK    0x7
-#define GC_FUSE_PROG_SEL_VREF_BATMON_VAL_SIZE    0x3
-#define GC_FUSE_PROG_SEL_VREF_BATMON_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_SEL_VREF_BATMON_VAL_OFFSET  0x2fc
-#define GC_FUSE_PROG_X_OSC_LDO_CTRL_EN_VAL_LSB   0x0
-#define GC_FUSE_PROG_X_OSC_LDO_CTRL_EN_VAL_MASK  0x7
-#define GC_FUSE_PROG_X_OSC_LDO_CTRL_EN_VAL_SIZE  0x3
-#define GC_FUSE_PROG_X_OSC_LDO_CTRL_EN_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_X_OSC_LDO_CTRL_EN_VAL_OFFSET 0x300
-#define GC_FUSE_PROG_X_OSC_LDO_CTRL_VAL_LSB      0x0
-#define GC_FUSE_PROG_X_OSC_LDO_CTRL_VAL_MASK     0xf
-#define GC_FUSE_PROG_X_OSC_LDO_CTRL_VAL_SIZE     0x4
-#define GC_FUSE_PROG_X_OSC_LDO_CTRL_VAL_DEFAULT  0x0
-#define GC_FUSE_PROG_X_OSC_LDO_CTRL_VAL_OFFSET   0x304
-#define GC_FUSE_PROG_TEMP_OFFSET_CAL_VAL_LSB     0x0
-#define GC_FUSE_PROG_TEMP_OFFSET_CAL_VAL_MASK    0xfff
-#define GC_FUSE_PROG_TEMP_OFFSET_CAL_VAL_SIZE    0xc
-#define GC_FUSE_PROG_TEMP_OFFSET_CAL_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_TEMP_OFFSET_CAL_VAL_OFFSET  0x308
-#define GC_FUSE_PROG_TRNG_LDO_CTRL_EN_VAL_LSB    0x0
-#define GC_FUSE_PROG_TRNG_LDO_CTRL_EN_VAL_MASK   0x7
-#define GC_FUSE_PROG_TRNG_LDO_CTRL_EN_VAL_SIZE   0x3
-#define GC_FUSE_PROG_TRNG_LDO_CTRL_EN_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_TRNG_LDO_CTRL_EN_VAL_OFFSET 0x30c
-#define GC_FUSE_PROG_TRNG_LDO_CTRL_VAL_LSB       0x0
-#define GC_FUSE_PROG_TRNG_LDO_CTRL_VAL_MASK      0x1f
-#define GC_FUSE_PROG_TRNG_LDO_CTRL_VAL_SIZE      0x5
-#define GC_FUSE_PROG_TRNG_LDO_CTRL_VAL_DEFAULT   0x0
-#define GC_FUSE_PROG_TRNG_LDO_CTRL_VAL_OFFSET    0x310
-#define GC_FUSE_PROG_TRNG_ANALOG_CTRL_EN_VAL_LSB 0x0
-#define GC_FUSE_PROG_TRNG_ANALOG_CTRL_EN_VAL_MASK 0x7
-#define GC_FUSE_PROG_TRNG_ANALOG_CTRL_EN_VAL_SIZE 0x3
-#define GC_FUSE_PROG_TRNG_ANALOG_CTRL_EN_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_TRNG_ANALOG_CTRL_EN_VAL_OFFSET 0x314
-#define GC_FUSE_PROG_TRNG_ANALOG_CTRL_VAL_LSB    0x0
-#define GC_FUSE_PROG_TRNG_ANALOG_CTRL_VAL_MASK   0xf
-#define GC_FUSE_PROG_TRNG_ANALOG_CTRL_VAL_SIZE   0x4
-#define GC_FUSE_PROG_TRNG_ANALOG_CTRL_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_TRNG_ANALOG_CTRL_VAL_OFFSET 0x318
-#define GC_FUSE_PROG_EXT_XTAL_PDB_VAL_LSB        0x0
-#define GC_FUSE_PROG_EXT_XTAL_PDB_VAL_MASK       0x3
-#define GC_FUSE_PROG_EXT_XTAL_PDB_VAL_SIZE       0x2
-#define GC_FUSE_PROG_EXT_XTAL_PDB_VAL_DEFAULT    0x0
-#define GC_FUSE_PROG_EXT_XTAL_PDB_VAL_OFFSET     0x31c
-#define GC_FUSE_PROG_DIS_EXT_XTAL_CLK_TREE_VAL_LSB 0x0
-#define GC_FUSE_PROG_DIS_EXT_XTAL_CLK_TREE_VAL_MASK 0x7
-#define GC_FUSE_PROG_DIS_EXT_XTAL_CLK_TREE_VAL_SIZE 0x3
-#define GC_FUSE_PROG_DIS_EXT_XTAL_CLK_TREE_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_DIS_EXT_XTAL_CLK_TREE_VAL_OFFSET 0x320
-#define GC_FUSE_PROG_OBFUSCATION_EN_VAL_LSB      0x0
-#define GC_FUSE_PROG_OBFUSCATION_EN_VAL_MASK     0x7
-#define GC_FUSE_PROG_OBFUSCATION_EN_VAL_SIZE     0x3
-#define GC_FUSE_PROG_OBFUSCATION_EN_VAL_DEFAULT  0x0
-#define GC_FUSE_PROG_OBFUSCATION_EN_VAL_OFFSET   0x324
-#define GC_FUSE_PROG_OBS0_VAL_LSB                0x0
-#define GC_FUSE_PROG_OBS0_VAL_MASK               0xffffffff
-#define GC_FUSE_PROG_OBS0_VAL_SIZE               0x20
-#define GC_FUSE_PROG_OBS0_VAL_DEFAULT            0x0
-#define GC_FUSE_PROG_OBS0_VAL_OFFSET             0x328
-#define GC_FUSE_PROG_OBS1_VAL_LSB                0x0
-#define GC_FUSE_PROG_OBS1_VAL_MASK               0xffffffff
-#define GC_FUSE_PROG_OBS1_VAL_SIZE               0x20
-#define GC_FUSE_PROG_OBS1_VAL_DEFAULT            0x0
-#define GC_FUSE_PROG_OBS1_VAL_OFFSET             0x32c
-#define GC_FUSE_PROG_OBS2_VAL_LSB                0x0
-#define GC_FUSE_PROG_OBS2_VAL_MASK               0xffffffff
-#define GC_FUSE_PROG_OBS2_VAL_SIZE               0x20
-#define GC_FUSE_PROG_OBS2_VAL_DEFAULT            0x0
-#define GC_FUSE_PROG_OBS2_VAL_OFFSET             0x330
-#define GC_FUSE_PROG_OBS3_VAL_LSB                0x0
-#define GC_FUSE_PROG_OBS3_VAL_MASK               0xffffffff
-#define GC_FUSE_PROG_OBS3_VAL_SIZE               0x20
-#define GC_FUSE_PROG_OBS3_VAL_DEFAULT            0x0
-#define GC_FUSE_PROG_OBS3_VAL_OFFSET             0x334
-#define GC_FUSE_PROG_OBS4_VAL_LSB                0x0
-#define GC_FUSE_PROG_OBS4_VAL_MASK               0xffffffff
-#define GC_FUSE_PROG_OBS4_VAL_SIZE               0x20
-#define GC_FUSE_PROG_OBS4_VAL_DEFAULT            0x0
-#define GC_FUSE_PROG_OBS4_VAL_OFFSET             0x338
-#define GC_FUSE_PROG_OBS5_VAL_LSB                0x0
-#define GC_FUSE_PROG_OBS5_VAL_MASK               0xffffffff
-#define GC_FUSE_PROG_OBS5_VAL_SIZE               0x20
-#define GC_FUSE_PROG_OBS5_VAL_DEFAULT            0x0
-#define GC_FUSE_PROG_OBS5_VAL_OFFSET             0x33c
-#define GC_FUSE_PROG_OBS6_VAL_LSB                0x0
-#define GC_FUSE_PROG_OBS6_VAL_MASK               0xffffffff
-#define GC_FUSE_PROG_OBS6_VAL_SIZE               0x20
-#define GC_FUSE_PROG_OBS6_VAL_DEFAULT            0x0
-#define GC_FUSE_PROG_OBS6_VAL_OFFSET             0x340
-#define GC_FUSE_PROG_OBS7_VAL_LSB                0x0
-#define GC_FUSE_PROG_OBS7_VAL_MASK               0xffffffff
-#define GC_FUSE_PROG_OBS7_VAL_SIZE               0x20
-#define GC_FUSE_PROG_OBS7_VAL_DEFAULT            0x0
-#define GC_FUSE_PROG_OBS7_VAL_OFFSET             0x344
-#define GC_FUSE_PROG_HIK_CREATE_LOCK_VAL_LSB     0x0
-#define GC_FUSE_PROG_HIK_CREATE_LOCK_VAL_MASK    0x7
-#define GC_FUSE_PROG_HIK_CREATE_LOCK_VAL_SIZE    0x3
-#define GC_FUSE_PROG_HIK_CREATE_LOCK_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_HIK_CREATE_LOCK_VAL_OFFSET  0x348
-#define GC_FUSE_PROG_BNK2_INTG_CHKSUM_VAL_LSB    0x0
-#define GC_FUSE_PROG_BNK2_INTG_CHKSUM_VAL_MASK   0xffffff
-#define GC_FUSE_PROG_BNK2_INTG_CHKSUM_VAL_SIZE   0x18
-#define GC_FUSE_PROG_BNK2_INTG_CHKSUM_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_BNK2_INTG_CHKSUM_VAL_OFFSET 0x34c
-#define GC_FUSE_PROG_BNK2_INTG_LOCK_VAL_LSB      0x0
-#define GC_FUSE_PROG_BNK2_INTG_LOCK_VAL_MASK     0x7
-#define GC_FUSE_PROG_BNK2_INTG_LOCK_VAL_SIZE     0x3
-#define GC_FUSE_PROG_BNK2_INTG_LOCK_VAL_DEFAULT  0x0
-#define GC_FUSE_PROG_BNK2_INTG_LOCK_VAL_OFFSET   0x350
-#define GC_FUSE_PROG_TESTMODE_OTPW_DIS_VAL_LSB   0x0
-#define GC_FUSE_PROG_TESTMODE_OTPW_DIS_VAL_MASK  0x7
-#define GC_FUSE_PROG_TESTMODE_OTPW_DIS_VAL_SIZE  0x3
-#define GC_FUSE_PROG_TESTMODE_OTPW_DIS_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_TESTMODE_OTPW_DIS_VAL_OFFSET 0x354
-#define GC_FUSE_PROG_HKEY_WDOG_TIMER_EN_VAL_LSB  0x0
-#define GC_FUSE_PROG_HKEY_WDOG_TIMER_EN_VAL_MASK 0x7
-#define GC_FUSE_PROG_HKEY_WDOG_TIMER_EN_VAL_SIZE 0x3
-#define GC_FUSE_PROG_HKEY_WDOG_TIMER_EN_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_HKEY_WDOG_TIMER_EN_VAL_OFFSET 0x358
-#define GC_FUSE_PROG_FLASH_PERSO_PAGE_LOCK_VAL_LSB 0x0
-#define GC_FUSE_PROG_FLASH_PERSO_PAGE_LOCK_VAL_MASK 0x7
-#define GC_FUSE_PROG_FLASH_PERSO_PAGE_LOCK_VAL_SIZE 0x3
-#define GC_FUSE_PROG_FLASH_PERSO_PAGE_LOCK_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_FLASH_PERSO_PAGE_LOCK_VAL_OFFSET 0x35c
-#define GC_FUSE_PROG_ALERT_RSP_CFG_VAL_LSB       0x0
-#define GC_FUSE_PROG_ALERT_RSP_CFG_VAL_MASK      0xff
-#define GC_FUSE_PROG_ALERT_RSP_CFG_VAL_SIZE      0x8
-#define GC_FUSE_PROG_ALERT_RSP_CFG_VAL_DEFAULT   0x0
-#define GC_FUSE_PROG_ALERT_RSP_CFG_VAL_OFFSET    0x360
-#define GC_FUSE_PROG_BNK3_INTG_CHKSUM_VAL_LSB    0x0
-#define GC_FUSE_PROG_BNK3_INTG_CHKSUM_VAL_MASK   0xffffff
-#define GC_FUSE_PROG_BNK3_INTG_CHKSUM_VAL_SIZE   0x18
-#define GC_FUSE_PROG_BNK3_INTG_CHKSUM_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_BNK3_INTG_CHKSUM_VAL_OFFSET 0x364
-#define GC_FUSE_PROG_BNK3_INTG_LOCK_VAL_LSB      0x0
-#define GC_FUSE_PROG_BNK3_INTG_LOCK_VAL_MASK     0x7
-#define GC_FUSE_PROG_BNK3_INTG_LOCK_VAL_SIZE     0x3
-#define GC_FUSE_PROG_BNK3_INTG_LOCK_VAL_DEFAULT  0x0
-#define GC_FUSE_PROG_BNK3_INTG_LOCK_VAL_OFFSET   0x368
-#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK0_VAL_LSB 0x0
-#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK0_VAL_MASK 0xff
-#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK0_VAL_SIZE 0x8
-#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK0_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK0_VAL_OFFSET 0x36c
-#define GC_FUSE_PROG_FW_DEFINED_BROM_ERR_RESPONSE_VAL_LSB 0x0
-#define GC_FUSE_PROG_FW_DEFINED_BROM_ERR_RESPONSE_VAL_MASK 0xffff
-#define GC_FUSE_PROG_FW_DEFINED_BROM_ERR_RESPONSE_VAL_SIZE 0x10
-#define GC_FUSE_PROG_FW_DEFINED_BROM_ERR_RESPONSE_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_FW_DEFINED_BROM_ERR_RESPONSE_VAL_OFFSET 0x370
-#define GC_FUSE_PROG_FW_DEFINED_BROM_APPLYSEC_VAL_LSB 0x0
-#define GC_FUSE_PROG_FW_DEFINED_BROM_APPLYSEC_VAL_MASK 0xfff
-#define GC_FUSE_PROG_FW_DEFINED_BROM_APPLYSEC_VAL_SIZE 0xc
-#define GC_FUSE_PROG_FW_DEFINED_BROM_APPLYSEC_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_FW_DEFINED_BROM_APPLYSEC_VAL_OFFSET 0x374
-#define GC_FUSE_PROG_FW_DEFINED_BROM_CONFIG0_VAL_LSB 0x0
-#define GC_FUSE_PROG_FW_DEFINED_BROM_CONFIG0_VAL_MASK 0xff
-#define GC_FUSE_PROG_FW_DEFINED_BROM_CONFIG0_VAL_SIZE 0x8
-#define GC_FUSE_PROG_FW_DEFINED_BROM_CONFIG0_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_FW_DEFINED_BROM_CONFIG0_VAL_OFFSET 0x378
-#define GC_FUSE_PROG_FW_DEFINED_BROM_CONFIG1_VAL_LSB 0x0
-#define GC_FUSE_PROG_FW_DEFINED_BROM_CONFIG1_VAL_MASK 0xff
-#define GC_FUSE_PROG_FW_DEFINED_BROM_CONFIG1_VAL_SIZE 0x8
-#define GC_FUSE_PROG_FW_DEFINED_BROM_CONFIG1_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_FW_DEFINED_BROM_CONFIG1_VAL_OFFSET 0x37c
-#define GC_FUSE_PROG_RBOX_MODE_DBG_OVRD_DIS_VAL_LSB 0x0
-#define GC_FUSE_PROG_RBOX_MODE_DBG_OVRD_DIS_VAL_MASK 0x1
-#define GC_FUSE_PROG_RBOX_MODE_DBG_OVRD_DIS_VAL_SIZE 0x1
-#define GC_FUSE_PROG_RBOX_MODE_DBG_OVRD_DIS_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_MODE_DBG_OVRD_DIS_VAL_OFFSET 0x380
-#define GC_FUSE_PROG_RBOX_MODE_OUTPUT_OVRD_DIS_VAL_LSB 0x0
-#define GC_FUSE_PROG_RBOX_MODE_OUTPUT_OVRD_DIS_VAL_MASK 0x7f
-#define GC_FUSE_PROG_RBOX_MODE_OUTPUT_OVRD_DIS_VAL_SIZE 0x7
-#define GC_FUSE_PROG_RBOX_MODE_OUTPUT_OVRD_DIS_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_MODE_OUTPUT_OVRD_DIS_VAL_OFFSET 0x384
-#define GC_FUSE_PROG_RBOX_CLK10HZ_COUNT_VAL_LSB  0x0
-#define GC_FUSE_PROG_RBOX_CLK10HZ_COUNT_VAL_MASK 0xffff
-#define GC_FUSE_PROG_RBOX_CLK10HZ_COUNT_VAL_SIZE 0x10
-#define GC_FUSE_PROG_RBOX_CLK10HZ_COUNT_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_CLK10HZ_COUNT_VAL_OFFSET 0x388
-#define GC_FUSE_PROG_RBOX_SHORT_DELAY_COUNT_VAL_LSB 0x0
-#define GC_FUSE_PROG_RBOX_SHORT_DELAY_COUNT_VAL_MASK 0xffff
-#define GC_FUSE_PROG_RBOX_SHORT_DELAY_COUNT_VAL_SIZE 0x10
-#define GC_FUSE_PROG_RBOX_SHORT_DELAY_COUNT_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_SHORT_DELAY_COUNT_VAL_OFFSET 0x38c
-#define GC_FUSE_PROG_RBOX_LONG_DELAY_COUNT_VAL_LSB 0x0
-#define GC_FUSE_PROG_RBOX_LONG_DELAY_COUNT_VAL_MASK 0xff
-#define GC_FUSE_PROG_RBOX_LONG_DELAY_COUNT_VAL_SIZE 0x8
-#define GC_FUSE_PROG_RBOX_LONG_DELAY_COUNT_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_LONG_DELAY_COUNT_VAL_OFFSET 0x390
-#define GC_FUSE_PROG_RBOX_DEBOUNCE_PERIOD_VAL_LSB 0x0
-#define GC_FUSE_PROG_RBOX_DEBOUNCE_PERIOD_VAL_MASK 0xffff
-#define GC_FUSE_PROG_RBOX_DEBOUNCE_PERIOD_VAL_SIZE 0x10
-#define GC_FUSE_PROG_RBOX_DEBOUNCE_PERIOD_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_DEBOUNCE_PERIOD_VAL_OFFSET 0x394
-#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_PWRB_VAL_LSB 0x0
-#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_PWRB_VAL_MASK 0x1
-#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_PWRB_VAL_SIZE 0x1
-#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_PWRB_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_PWRB_VAL_OFFSET 0x398
-#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY0_VAL_LSB 0x0
-#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY0_VAL_MASK 0x1
-#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY0_VAL_SIZE 0x1
-#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY0_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY0_VAL_OFFSET 0x39c
-#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY1_VAL_LSB 0x0
-#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY1_VAL_MASK 0x1
-#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY1_VAL_SIZE 0x1
-#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY1_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY1_VAL_OFFSET 0x3a0
-#define GC_FUSE_PROG_RBOX_KEY_COMBO0_VAL_VAL_LSB 0x0
-#define GC_FUSE_PROG_RBOX_KEY_COMBO0_VAL_VAL_MASK 0xff
-#define GC_FUSE_PROG_RBOX_KEY_COMBO0_VAL_VAL_SIZE 0x8
-#define GC_FUSE_PROG_RBOX_KEY_COMBO0_VAL_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_KEY_COMBO0_VAL_VAL_OFFSET 0x3a4
-#define GC_FUSE_PROG_RBOX_KEY_COMBO1_VAL_VAL_LSB 0x0
-#define GC_FUSE_PROG_RBOX_KEY_COMBO1_VAL_VAL_MASK 0xff
-#define GC_FUSE_PROG_RBOX_KEY_COMBO1_VAL_VAL_SIZE 0x8
-#define GC_FUSE_PROG_RBOX_KEY_COMBO1_VAL_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_KEY_COMBO1_VAL_VAL_OFFSET 0x3a8
-#define GC_FUSE_PROG_RBOX_KEY_COMBO2_VAL_VAL_LSB 0x0
-#define GC_FUSE_PROG_RBOX_KEY_COMBO2_VAL_VAL_MASK 0xff
-#define GC_FUSE_PROG_RBOX_KEY_COMBO2_VAL_VAL_SIZE 0x8
-#define GC_FUSE_PROG_RBOX_KEY_COMBO2_VAL_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_KEY_COMBO2_VAL_VAL_OFFSET 0x3ac
-#define GC_FUSE_PROG_RBOX_KEY_COMBO0_HOLD_VAL_LSB 0x0
-#define GC_FUSE_PROG_RBOX_KEY_COMBO0_HOLD_VAL_MASK 0xff
-#define GC_FUSE_PROG_RBOX_KEY_COMBO0_HOLD_VAL_SIZE 0x8
-#define GC_FUSE_PROG_RBOX_KEY_COMBO0_HOLD_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_KEY_COMBO0_HOLD_VAL_OFFSET 0x3b0
-#define GC_FUSE_PROG_RBOX_KEY_COMBO1_HOLD_VAL_LSB 0x0
-#define GC_FUSE_PROG_RBOX_KEY_COMBO1_HOLD_VAL_MASK 0xff
-#define GC_FUSE_PROG_RBOX_KEY_COMBO1_HOLD_VAL_SIZE 0x8
-#define GC_FUSE_PROG_RBOX_KEY_COMBO1_HOLD_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_KEY_COMBO1_HOLD_VAL_OFFSET 0x3b4
-#define GC_FUSE_PROG_RBOX_KEY_COMBO2_HOLD_VAL_LSB 0x0
-#define GC_FUSE_PROG_RBOX_KEY_COMBO2_HOLD_VAL_MASK 0xff
-#define GC_FUSE_PROG_RBOX_KEY_COMBO2_HOLD_VAL_SIZE 0x8
-#define GC_FUSE_PROG_RBOX_KEY_COMBO2_HOLD_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_KEY_COMBO2_HOLD_VAL_OFFSET 0x3b8
-#define GC_FUSE_PROG_RBOX_BLOCK_KEY0_SEL_VAL_LSB 0x0
-#define GC_FUSE_PROG_RBOX_BLOCK_KEY0_SEL_VAL_MASK 0x1
-#define GC_FUSE_PROG_RBOX_BLOCK_KEY0_SEL_VAL_SIZE 0x1
-#define GC_FUSE_PROG_RBOX_BLOCK_KEY0_SEL_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_BLOCK_KEY0_SEL_VAL_OFFSET 0x3bc
-#define GC_FUSE_PROG_RBOX_BLOCK_KEY1_SEL_VAL_LSB 0x0
-#define GC_FUSE_PROG_RBOX_BLOCK_KEY1_SEL_VAL_MASK 0x1
-#define GC_FUSE_PROG_RBOX_BLOCK_KEY1_SEL_VAL_SIZE 0x1
-#define GC_FUSE_PROG_RBOX_BLOCK_KEY1_SEL_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_BLOCK_KEY1_SEL_VAL_OFFSET 0x3c0
-#define GC_FUSE_PROG_RBOX_BLOCK_KEY0_VAL_VAL_LSB 0x0
-#define GC_FUSE_PROG_RBOX_BLOCK_KEY0_VAL_VAL_MASK 0x1
-#define GC_FUSE_PROG_RBOX_BLOCK_KEY0_VAL_VAL_SIZE 0x1
-#define GC_FUSE_PROG_RBOX_BLOCK_KEY0_VAL_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_BLOCK_KEY0_VAL_VAL_OFFSET 0x3c4
-#define GC_FUSE_PROG_RBOX_BLOCK_KEY1_VAL_VAL_LSB 0x0
-#define GC_FUSE_PROG_RBOX_BLOCK_KEY1_VAL_VAL_MASK 0x1
-#define GC_FUSE_PROG_RBOX_BLOCK_KEY1_VAL_VAL_SIZE 0x1
-#define GC_FUSE_PROG_RBOX_BLOCK_KEY1_VAL_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_BLOCK_KEY1_VAL_VAL_OFFSET 0x3c8
-#define GC_FUSE_PROG_RBOX_POL_AC_PRESENT_VAL_LSB 0x0
-#define GC_FUSE_PROG_RBOX_POL_AC_PRESENT_VAL_MASK 0x1
-#define GC_FUSE_PROG_RBOX_POL_AC_PRESENT_VAL_SIZE 0x1
-#define GC_FUSE_PROG_RBOX_POL_AC_PRESENT_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_POL_AC_PRESENT_VAL_OFFSET 0x3cc
-#define GC_FUSE_PROG_RBOX_POL_PWRB_IN_VAL_LSB    0x0
-#define GC_FUSE_PROG_RBOX_POL_PWRB_IN_VAL_MASK   0x1
-#define GC_FUSE_PROG_RBOX_POL_PWRB_IN_VAL_SIZE   0x1
-#define GC_FUSE_PROG_RBOX_POL_PWRB_IN_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_POL_PWRB_IN_VAL_OFFSET 0x3d0
-#define GC_FUSE_PROG_RBOX_POL_PWRB_OUT_VAL_LSB   0x0
-#define GC_FUSE_PROG_RBOX_POL_PWRB_OUT_VAL_MASK  0x1
-#define GC_FUSE_PROG_RBOX_POL_PWRB_OUT_VAL_SIZE  0x1
-#define GC_FUSE_PROG_RBOX_POL_PWRB_OUT_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_POL_PWRB_OUT_VAL_OFFSET 0x3d4
-#define GC_FUSE_PROG_RBOX_POL_KEY0_IN_VAL_LSB    0x0
-#define GC_FUSE_PROG_RBOX_POL_KEY0_IN_VAL_MASK   0x1
-#define GC_FUSE_PROG_RBOX_POL_KEY0_IN_VAL_SIZE   0x1
-#define GC_FUSE_PROG_RBOX_POL_KEY0_IN_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_POL_KEY0_IN_VAL_OFFSET 0x3d8
-#define GC_FUSE_PROG_RBOX_POL_KEY0_OUT_VAL_LSB   0x0
-#define GC_FUSE_PROG_RBOX_POL_KEY0_OUT_VAL_MASK  0x1
-#define GC_FUSE_PROG_RBOX_POL_KEY0_OUT_VAL_SIZE  0x1
-#define GC_FUSE_PROG_RBOX_POL_KEY0_OUT_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_POL_KEY0_OUT_VAL_OFFSET 0x3dc
-#define GC_FUSE_PROG_RBOX_POL_KEY1_IN_VAL_LSB    0x0
-#define GC_FUSE_PROG_RBOX_POL_KEY1_IN_VAL_MASK   0x1
-#define GC_FUSE_PROG_RBOX_POL_KEY1_IN_VAL_SIZE   0x1
-#define GC_FUSE_PROG_RBOX_POL_KEY1_IN_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_POL_KEY1_IN_VAL_OFFSET 0x3e0
-#define GC_FUSE_PROG_RBOX_POL_KEY1_OUT_VAL_LSB   0x0
-#define GC_FUSE_PROG_RBOX_POL_KEY1_OUT_VAL_MASK  0x1
-#define GC_FUSE_PROG_RBOX_POL_KEY1_OUT_VAL_SIZE  0x1
-#define GC_FUSE_PROG_RBOX_POL_KEY1_OUT_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_POL_KEY1_OUT_VAL_OFFSET 0x3e4
-#define GC_FUSE_PROG_RBOX_POL_EC_RST_VAL_LSB     0x0
-#define GC_FUSE_PROG_RBOX_POL_EC_RST_VAL_MASK    0x1
-#define GC_FUSE_PROG_RBOX_POL_EC_RST_VAL_SIZE    0x1
-#define GC_FUSE_PROG_RBOX_POL_EC_RST_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_POL_EC_RST_VAL_OFFSET  0x3e8
-#define GC_FUSE_PROG_RBOX_POL_BATT_DISABLE_VAL_LSB 0x0
-#define GC_FUSE_PROG_RBOX_POL_BATT_DISABLE_VAL_MASK 0x1
-#define GC_FUSE_PROG_RBOX_POL_BATT_DISABLE_VAL_SIZE 0x1
-#define GC_FUSE_PROG_RBOX_POL_BATT_DISABLE_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_POL_BATT_DISABLE_VAL_OFFSET 0x3ec
-#define GC_FUSE_PROG_RBOX_TERM_AC_PRESENT_VAL_LSB 0x0
-#define GC_FUSE_PROG_RBOX_TERM_AC_PRESENT_VAL_MASK 0x3
-#define GC_FUSE_PROG_RBOX_TERM_AC_PRESENT_VAL_SIZE 0x2
-#define GC_FUSE_PROG_RBOX_TERM_AC_PRESENT_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_TERM_AC_PRESENT_VAL_OFFSET 0x3f0
-#define GC_FUSE_PROG_RBOX_TERM_ENTERING_RW_VAL_LSB 0x0
-#define GC_FUSE_PROG_RBOX_TERM_ENTERING_RW_VAL_MASK 0x3
-#define GC_FUSE_PROG_RBOX_TERM_ENTERING_RW_VAL_SIZE 0x2
-#define GC_FUSE_PROG_RBOX_TERM_ENTERING_RW_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_TERM_ENTERING_RW_VAL_OFFSET 0x3f4
-#define GC_FUSE_PROG_RBOX_TERM_PWRB_IN_VAL_LSB   0x0
-#define GC_FUSE_PROG_RBOX_TERM_PWRB_IN_VAL_MASK  0x3
-#define GC_FUSE_PROG_RBOX_TERM_PWRB_IN_VAL_SIZE  0x2
-#define GC_FUSE_PROG_RBOX_TERM_PWRB_IN_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_TERM_PWRB_IN_VAL_OFFSET 0x3f8
-#define GC_FUSE_PROG_RBOX_TERM_PWRB_OUT_VAL_LSB  0x0
-#define GC_FUSE_PROG_RBOX_TERM_PWRB_OUT_VAL_MASK 0x3
-#define GC_FUSE_PROG_RBOX_TERM_PWRB_OUT_VAL_SIZE 0x2
-#define GC_FUSE_PROG_RBOX_TERM_PWRB_OUT_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_TERM_PWRB_OUT_VAL_OFFSET 0x3fc
-#define GC_FUSE_PROG_RBOX_TERM_KEY0_IN_VAL_LSB   0x0
-#define GC_FUSE_PROG_RBOX_TERM_KEY0_IN_VAL_MASK  0x3
-#define GC_FUSE_PROG_RBOX_TERM_KEY0_IN_VAL_SIZE  0x2
-#define GC_FUSE_PROG_RBOX_TERM_KEY0_IN_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_TERM_KEY0_IN_VAL_OFFSET 0x400
-#define GC_FUSE_PROG_RBOX_TERM_KEY0_OUT_VAL_LSB  0x0
-#define GC_FUSE_PROG_RBOX_TERM_KEY0_OUT_VAL_MASK 0x3
-#define GC_FUSE_PROG_RBOX_TERM_KEY0_OUT_VAL_SIZE 0x2
-#define GC_FUSE_PROG_RBOX_TERM_KEY0_OUT_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_TERM_KEY0_OUT_VAL_OFFSET 0x404
-#define GC_FUSE_PROG_RBOX_TERM_KEY1_IN_VAL_LSB   0x0
-#define GC_FUSE_PROG_RBOX_TERM_KEY1_IN_VAL_MASK  0x3
-#define GC_FUSE_PROG_RBOX_TERM_KEY1_IN_VAL_SIZE  0x2
-#define GC_FUSE_PROG_RBOX_TERM_KEY1_IN_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_TERM_KEY1_IN_VAL_OFFSET 0x408
-#define GC_FUSE_PROG_RBOX_TERM_KEY1_OUT_VAL_LSB  0x0
-#define GC_FUSE_PROG_RBOX_TERM_KEY1_OUT_VAL_MASK 0x3
-#define GC_FUSE_PROG_RBOX_TERM_KEY1_OUT_VAL_SIZE 0x2
-#define GC_FUSE_PROG_RBOX_TERM_KEY1_OUT_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_TERM_KEY1_OUT_VAL_OFFSET 0x40c
-#define GC_FUSE_PROG_RBOX_DRIVE_PWRB_OUT_VAL_LSB 0x0
-#define GC_FUSE_PROG_RBOX_DRIVE_PWRB_OUT_VAL_MASK 0x3
-#define GC_FUSE_PROG_RBOX_DRIVE_PWRB_OUT_VAL_SIZE 0x2
-#define GC_FUSE_PROG_RBOX_DRIVE_PWRB_OUT_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_DRIVE_PWRB_OUT_VAL_OFFSET 0x410
-#define GC_FUSE_PROG_RBOX_DRIVE_KEY0_OUT_VAL_LSB 0x0
-#define GC_FUSE_PROG_RBOX_DRIVE_KEY0_OUT_VAL_MASK 0x3
-#define GC_FUSE_PROG_RBOX_DRIVE_KEY0_OUT_VAL_SIZE 0x2
-#define GC_FUSE_PROG_RBOX_DRIVE_KEY0_OUT_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_DRIVE_KEY0_OUT_VAL_OFFSET 0x414
-#define GC_FUSE_PROG_RBOX_DRIVE_KEY1_OUT_VAL_LSB 0x0
-#define GC_FUSE_PROG_RBOX_DRIVE_KEY1_OUT_VAL_MASK 0x3
-#define GC_FUSE_PROG_RBOX_DRIVE_KEY1_OUT_VAL_SIZE 0x2
-#define GC_FUSE_PROG_RBOX_DRIVE_KEY1_OUT_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_DRIVE_KEY1_OUT_VAL_OFFSET 0x418
-#define GC_FUSE_PROG_RBOX_DRIVE_EC_RST_VAL_LSB   0x0
-#define GC_FUSE_PROG_RBOX_DRIVE_EC_RST_VAL_MASK  0x3
-#define GC_FUSE_PROG_RBOX_DRIVE_EC_RST_VAL_SIZE  0x2
-#define GC_FUSE_PROG_RBOX_DRIVE_EC_RST_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_DRIVE_EC_RST_VAL_OFFSET 0x41c
-#define GC_FUSE_PROG_RBOX_DRIVE_BATT_DISABLE_VAL_LSB 0x0
-#define GC_FUSE_PROG_RBOX_DRIVE_BATT_DISABLE_VAL_MASK 0x3
-#define GC_FUSE_PROG_RBOX_DRIVE_BATT_DISABLE_VAL_SIZE 0x2
-#define GC_FUSE_PROG_RBOX_DRIVE_BATT_DISABLE_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_RBOX_DRIVE_BATT_DISABLE_VAL_OFFSET 0x420
-#define GC_FUSE_PROG_BNK4_INTG_CHKSUM_VAL_LSB    0x0
-#define GC_FUSE_PROG_BNK4_INTG_CHKSUM_VAL_MASK   0xffffff
-#define GC_FUSE_PROG_BNK4_INTG_CHKSUM_VAL_SIZE   0x18
-#define GC_FUSE_PROG_BNK4_INTG_CHKSUM_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_BNK4_INTG_CHKSUM_VAL_OFFSET 0x424
-#define GC_FUSE_PROG_BNK4_INTG_LOCK_VAL_LSB      0x0
-#define GC_FUSE_PROG_BNK4_INTG_LOCK_VAL_MASK     0x7
-#define GC_FUSE_PROG_BNK4_INTG_LOCK_VAL_SIZE     0x3
-#define GC_FUSE_PROG_BNK4_INTG_LOCK_VAL_DEFAULT  0x0
-#define GC_FUSE_PROG_BNK4_INTG_LOCK_VAL_OFFSET   0x428
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK0_VAL_LSB 0x0
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK0_VAL_MASK 0xff
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK0_VAL_SIZE 0x8
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK0_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK0_VAL_OFFSET 0x42c
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK1_VAL_LSB 0x0
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK1_VAL_MASK 0xff
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK1_VAL_SIZE 0x8
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK1_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK1_VAL_OFFSET 0x430
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK2_VAL_LSB 0x0
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK2_VAL_MASK 0xff
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK2_VAL_SIZE 0x8
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK2_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK2_VAL_OFFSET 0x434
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK3_VAL_LSB 0x0
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK3_VAL_MASK 0xff
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK3_VAL_SIZE 0x8
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK3_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK3_VAL_OFFSET 0x438
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK4_VAL_LSB 0x0
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK4_VAL_MASK 0xff
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK4_VAL_SIZE 0x8
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK4_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK4_VAL_OFFSET 0x43c
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK5_VAL_LSB 0x0
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK5_VAL_MASK 0xff
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK5_VAL_SIZE 0x8
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK5_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK5_VAL_OFFSET 0x440
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK6_VAL_LSB 0x0
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK6_VAL_MASK 0x1f
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK6_VAL_SIZE 0x5
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK6_VAL_DEFAULT 0x0
-#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK6_VAL_OFFSET 0x444
-#define GC_GLOBALSEC_CPU0_D_REGION0_CTRL_EN_LSB  0x0
-#define GC_GLOBALSEC_CPU0_D_REGION0_CTRL_EN_MASK 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION0_CTRL_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION0_CTRL_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION0_CTRL_EN_OFFSET 0x0
-#define GC_GLOBALSEC_CPU0_D_REGION0_CTRL_RD_EN_LSB 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION0_CTRL_RD_EN_MASK 0x2
-#define GC_GLOBALSEC_CPU0_D_REGION0_CTRL_RD_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION0_CTRL_RD_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION0_CTRL_RD_EN_OFFSET 0x0
-#define GC_GLOBALSEC_CPU0_D_REGION0_CTRL_WR_EN_LSB 0x2
-#define GC_GLOBALSEC_CPU0_D_REGION0_CTRL_WR_EN_MASK 0x4
-#define GC_GLOBALSEC_CPU0_D_REGION0_CTRL_WR_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION0_CTRL_WR_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION0_CTRL_WR_EN_OFFSET 0x0
-#define GC_GLOBALSEC_CPU0_D_REGION1_CTRL_EN_LSB  0x0
-#define GC_GLOBALSEC_CPU0_D_REGION1_CTRL_EN_MASK 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION1_CTRL_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION1_CTRL_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION1_CTRL_EN_OFFSET 0x4
-#define GC_GLOBALSEC_CPU0_D_REGION1_CTRL_RD_EN_LSB 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION1_CTRL_RD_EN_MASK 0x2
-#define GC_GLOBALSEC_CPU0_D_REGION1_CTRL_RD_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION1_CTRL_RD_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION1_CTRL_RD_EN_OFFSET 0x4
-#define GC_GLOBALSEC_CPU0_D_REGION1_CTRL_WR_EN_LSB 0x2
-#define GC_GLOBALSEC_CPU0_D_REGION1_CTRL_WR_EN_MASK 0x4
-#define GC_GLOBALSEC_CPU0_D_REGION1_CTRL_WR_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION1_CTRL_WR_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION1_CTRL_WR_EN_OFFSET 0x4
-#define GC_GLOBALSEC_CPU0_D_REGION2_CTRL_EN_LSB  0x0
-#define GC_GLOBALSEC_CPU0_D_REGION2_CTRL_EN_MASK 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION2_CTRL_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION2_CTRL_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION2_CTRL_EN_OFFSET 0x8
-#define GC_GLOBALSEC_CPU0_D_REGION2_CTRL_RD_EN_LSB 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION2_CTRL_RD_EN_MASK 0x2
-#define GC_GLOBALSEC_CPU0_D_REGION2_CTRL_RD_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION2_CTRL_RD_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION2_CTRL_RD_EN_OFFSET 0x8
-#define GC_GLOBALSEC_CPU0_D_REGION2_CTRL_WR_EN_LSB 0x2
-#define GC_GLOBALSEC_CPU0_D_REGION2_CTRL_WR_EN_MASK 0x4
-#define GC_GLOBALSEC_CPU0_D_REGION2_CTRL_WR_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION2_CTRL_WR_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION2_CTRL_WR_EN_OFFSET 0x8
-#define GC_GLOBALSEC_CPU0_D_REGION3_CTRL_EN_LSB  0x0
-#define GC_GLOBALSEC_CPU0_D_REGION3_CTRL_EN_MASK 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION3_CTRL_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION3_CTRL_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION3_CTRL_EN_OFFSET 0xc
-#define GC_GLOBALSEC_CPU0_D_REGION3_CTRL_RD_EN_LSB 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION3_CTRL_RD_EN_MASK 0x2
-#define GC_GLOBALSEC_CPU0_D_REGION3_CTRL_RD_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION3_CTRL_RD_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION3_CTRL_RD_EN_OFFSET 0xc
-#define GC_GLOBALSEC_CPU0_D_REGION3_CTRL_WR_EN_LSB 0x2
-#define GC_GLOBALSEC_CPU0_D_REGION3_CTRL_WR_EN_MASK 0x4
-#define GC_GLOBALSEC_CPU0_D_REGION3_CTRL_WR_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION3_CTRL_WR_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION3_CTRL_WR_EN_OFFSET 0xc
-#define GC_GLOBALSEC_CPU0_D_REGION4_CTRL_EN_LSB  0x0
-#define GC_GLOBALSEC_CPU0_D_REGION4_CTRL_EN_MASK 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION4_CTRL_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION4_CTRL_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION4_CTRL_EN_OFFSET 0x10
-#define GC_GLOBALSEC_CPU0_D_REGION4_CTRL_RD_EN_LSB 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION4_CTRL_RD_EN_MASK 0x2
-#define GC_GLOBALSEC_CPU0_D_REGION4_CTRL_RD_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION4_CTRL_RD_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION4_CTRL_RD_EN_OFFSET 0x10
-#define GC_GLOBALSEC_CPU0_D_REGION4_CTRL_WR_EN_LSB 0x2
-#define GC_GLOBALSEC_CPU0_D_REGION4_CTRL_WR_EN_MASK 0x4
-#define GC_GLOBALSEC_CPU0_D_REGION4_CTRL_WR_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION4_CTRL_WR_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION4_CTRL_WR_EN_OFFSET 0x10
-#define GC_GLOBALSEC_CPU0_D_REGION5_CTRL_EN_LSB  0x0
-#define GC_GLOBALSEC_CPU0_D_REGION5_CTRL_EN_MASK 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION5_CTRL_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION5_CTRL_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION5_CTRL_EN_OFFSET 0x14
-#define GC_GLOBALSEC_CPU0_D_REGION5_CTRL_RD_EN_LSB 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION5_CTRL_RD_EN_MASK 0x2
-#define GC_GLOBALSEC_CPU0_D_REGION5_CTRL_RD_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION5_CTRL_RD_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION5_CTRL_RD_EN_OFFSET 0x14
-#define GC_GLOBALSEC_CPU0_D_REGION5_CTRL_WR_EN_LSB 0x2
-#define GC_GLOBALSEC_CPU0_D_REGION5_CTRL_WR_EN_MASK 0x4
-#define GC_GLOBALSEC_CPU0_D_REGION5_CTRL_WR_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION5_CTRL_WR_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION5_CTRL_WR_EN_OFFSET 0x14
-#define GC_GLOBALSEC_CPU0_D_REGION6_CTRL_EN_LSB  0x0
-#define GC_GLOBALSEC_CPU0_D_REGION6_CTRL_EN_MASK 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION6_CTRL_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION6_CTRL_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION6_CTRL_EN_OFFSET 0x18
-#define GC_GLOBALSEC_CPU0_D_REGION6_CTRL_RD_EN_LSB 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION6_CTRL_RD_EN_MASK 0x2
-#define GC_GLOBALSEC_CPU0_D_REGION6_CTRL_RD_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION6_CTRL_RD_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION6_CTRL_RD_EN_OFFSET 0x18
-#define GC_GLOBALSEC_CPU0_D_REGION6_CTRL_WR_EN_LSB 0x2
-#define GC_GLOBALSEC_CPU0_D_REGION6_CTRL_WR_EN_MASK 0x4
-#define GC_GLOBALSEC_CPU0_D_REGION6_CTRL_WR_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION6_CTRL_WR_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION6_CTRL_WR_EN_OFFSET 0x18
-#define GC_GLOBALSEC_CPU0_D_REGION7_CTRL_EN_LSB  0x0
-#define GC_GLOBALSEC_CPU0_D_REGION7_CTRL_EN_MASK 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION7_CTRL_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION7_CTRL_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION7_CTRL_EN_OFFSET 0x1c
-#define GC_GLOBALSEC_CPU0_D_REGION7_CTRL_RD_EN_LSB 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION7_CTRL_RD_EN_MASK 0x2
-#define GC_GLOBALSEC_CPU0_D_REGION7_CTRL_RD_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION7_CTRL_RD_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION7_CTRL_RD_EN_OFFSET 0x1c
-#define GC_GLOBALSEC_CPU0_D_REGION7_CTRL_WR_EN_LSB 0x2
-#define GC_GLOBALSEC_CPU0_D_REGION7_CTRL_WR_EN_MASK 0x4
-#define GC_GLOBALSEC_CPU0_D_REGION7_CTRL_WR_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION7_CTRL_WR_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_CPU0_D_REGION7_CTRL_WR_EN_OFFSET 0x1c
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_CTRL_EN_LSB 0x0
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_CTRL_EN_MASK 0x1
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_CTRL_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_CTRL_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_CTRL_EN_OFFSET 0x40
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_CTRL_RD_EN_LSB 0x1
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_CTRL_RD_EN_MASK 0x2
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_CTRL_RD_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_CTRL_RD_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_CTRL_RD_EN_OFFSET 0x40
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_CTRL_WR_EN_LSB 0x2
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_CTRL_WR_EN_MASK 0x4
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_CTRL_WR_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_CTRL_WR_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_CTRL_WR_EN_OFFSET 0x40
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_CTRL_EN_LSB 0x0
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_CTRL_EN_MASK 0x1
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_CTRL_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_CTRL_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_CTRL_EN_OFFSET 0x44
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_CTRL_RD_EN_LSB 0x1
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_CTRL_RD_EN_MASK 0x2
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_CTRL_RD_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_CTRL_RD_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_CTRL_RD_EN_OFFSET 0x44
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_CTRL_WR_EN_LSB 0x2
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_CTRL_WR_EN_MASK 0x4
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_CTRL_WR_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_CTRL_WR_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_CTRL_WR_EN_OFFSET 0x44
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_CTRL_EN_LSB 0x0
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_CTRL_EN_MASK 0x1
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_CTRL_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_CTRL_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_CTRL_EN_OFFSET 0x48
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_CTRL_RD_EN_LSB 0x1
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_CTRL_RD_EN_MASK 0x2
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_CTRL_RD_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_CTRL_RD_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_CTRL_RD_EN_OFFSET 0x48
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_CTRL_WR_EN_LSB 0x2
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_CTRL_WR_EN_MASK 0x4
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_CTRL_WR_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_CTRL_WR_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_CTRL_WR_EN_OFFSET 0x48
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_CTRL_EN_LSB 0x0
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_CTRL_EN_MASK 0x1
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_CTRL_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_CTRL_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_CTRL_EN_OFFSET 0x4c
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_CTRL_RD_EN_LSB 0x1
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_CTRL_RD_EN_MASK 0x2
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_CTRL_RD_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_CTRL_RD_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_CTRL_RD_EN_OFFSET 0x4c
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_CTRL_WR_EN_LSB 0x2
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_CTRL_WR_EN_MASK 0x4
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_CTRL_WR_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_CTRL_WR_EN_DEFAULT 0x1
-#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_CTRL_WR_EN_OFFSET 0x4c
-#define GC_GLOBALSEC_CPU0_I_REGION0_CTRL_EN_LSB  0x0
-#define GC_GLOBALSEC_CPU0_I_REGION0_CTRL_EN_MASK 0x1
-#define GC_GLOBALSEC_CPU0_I_REGION0_CTRL_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_I_REGION0_CTRL_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_REGION0_CTRL_EN_OFFSET 0x60
-#define GC_GLOBALSEC_CPU0_I_REGION0_CTRL_RD_EN_LSB 0x1
-#define GC_GLOBALSEC_CPU0_I_REGION0_CTRL_RD_EN_MASK 0x2
-#define GC_GLOBALSEC_CPU0_I_REGION0_CTRL_RD_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_I_REGION0_CTRL_RD_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_REGION0_CTRL_RD_EN_OFFSET 0x60
-#define GC_GLOBALSEC_CPU0_I_REGION0_CTRL_WR_EN_LSB 0x2
-#define GC_GLOBALSEC_CPU0_I_REGION0_CTRL_WR_EN_MASK 0x4
-#define GC_GLOBALSEC_CPU0_I_REGION0_CTRL_WR_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_I_REGION0_CTRL_WR_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_REGION0_CTRL_WR_EN_OFFSET 0x60
-#define GC_GLOBALSEC_CPU0_I_REGION1_CTRL_EN_LSB  0x0
-#define GC_GLOBALSEC_CPU0_I_REGION1_CTRL_EN_MASK 0x1
-#define GC_GLOBALSEC_CPU0_I_REGION1_CTRL_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_I_REGION1_CTRL_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_REGION1_CTRL_EN_OFFSET 0x64
-#define GC_GLOBALSEC_CPU0_I_REGION1_CTRL_RD_EN_LSB 0x1
-#define GC_GLOBALSEC_CPU0_I_REGION1_CTRL_RD_EN_MASK 0x2
-#define GC_GLOBALSEC_CPU0_I_REGION1_CTRL_RD_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_I_REGION1_CTRL_RD_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_REGION1_CTRL_RD_EN_OFFSET 0x64
-#define GC_GLOBALSEC_CPU0_I_REGION1_CTRL_WR_EN_LSB 0x2
-#define GC_GLOBALSEC_CPU0_I_REGION1_CTRL_WR_EN_MASK 0x4
-#define GC_GLOBALSEC_CPU0_I_REGION1_CTRL_WR_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_I_REGION1_CTRL_WR_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_REGION1_CTRL_WR_EN_OFFSET 0x64
-#define GC_GLOBALSEC_CPU0_I_REGION2_CTRL_EN_LSB  0x0
-#define GC_GLOBALSEC_CPU0_I_REGION2_CTRL_EN_MASK 0x1
-#define GC_GLOBALSEC_CPU0_I_REGION2_CTRL_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_I_REGION2_CTRL_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_REGION2_CTRL_EN_OFFSET 0x68
-#define GC_GLOBALSEC_CPU0_I_REGION2_CTRL_RD_EN_LSB 0x1
-#define GC_GLOBALSEC_CPU0_I_REGION2_CTRL_RD_EN_MASK 0x2
-#define GC_GLOBALSEC_CPU0_I_REGION2_CTRL_RD_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_I_REGION2_CTRL_RD_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_REGION2_CTRL_RD_EN_OFFSET 0x68
-#define GC_GLOBALSEC_CPU0_I_REGION2_CTRL_WR_EN_LSB 0x2
-#define GC_GLOBALSEC_CPU0_I_REGION2_CTRL_WR_EN_MASK 0x4
-#define GC_GLOBALSEC_CPU0_I_REGION2_CTRL_WR_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_I_REGION2_CTRL_WR_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_REGION2_CTRL_WR_EN_OFFSET 0x68
-#define GC_GLOBALSEC_CPU0_I_REGION3_CTRL_EN_LSB  0x0
-#define GC_GLOBALSEC_CPU0_I_REGION3_CTRL_EN_MASK 0x1
-#define GC_GLOBALSEC_CPU0_I_REGION3_CTRL_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_I_REGION3_CTRL_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_REGION3_CTRL_EN_OFFSET 0x6c
-#define GC_GLOBALSEC_CPU0_I_REGION3_CTRL_RD_EN_LSB 0x1
-#define GC_GLOBALSEC_CPU0_I_REGION3_CTRL_RD_EN_MASK 0x2
-#define GC_GLOBALSEC_CPU0_I_REGION3_CTRL_RD_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_I_REGION3_CTRL_RD_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_REGION3_CTRL_RD_EN_OFFSET 0x6c
-#define GC_GLOBALSEC_CPU0_I_REGION3_CTRL_WR_EN_LSB 0x2
-#define GC_GLOBALSEC_CPU0_I_REGION3_CTRL_WR_EN_MASK 0x4
-#define GC_GLOBALSEC_CPU0_I_REGION3_CTRL_WR_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_I_REGION3_CTRL_WR_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_REGION3_CTRL_WR_EN_OFFSET 0x6c
-#define GC_GLOBALSEC_CPU0_I_REGION4_CTRL_EN_LSB  0x0
-#define GC_GLOBALSEC_CPU0_I_REGION4_CTRL_EN_MASK 0x1
-#define GC_GLOBALSEC_CPU0_I_REGION4_CTRL_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_I_REGION4_CTRL_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_REGION4_CTRL_EN_OFFSET 0x70
-#define GC_GLOBALSEC_CPU0_I_REGION4_CTRL_RD_EN_LSB 0x1
-#define GC_GLOBALSEC_CPU0_I_REGION4_CTRL_RD_EN_MASK 0x2
-#define GC_GLOBALSEC_CPU0_I_REGION4_CTRL_RD_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_I_REGION4_CTRL_RD_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_REGION4_CTRL_RD_EN_OFFSET 0x70
-#define GC_GLOBALSEC_CPU0_I_REGION4_CTRL_WR_EN_LSB 0x2
-#define GC_GLOBALSEC_CPU0_I_REGION4_CTRL_WR_EN_MASK 0x4
-#define GC_GLOBALSEC_CPU0_I_REGION4_CTRL_WR_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_I_REGION4_CTRL_WR_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_REGION4_CTRL_WR_EN_OFFSET 0x70
-#define GC_GLOBALSEC_CPU0_I_REGION5_CTRL_EN_LSB  0x0
-#define GC_GLOBALSEC_CPU0_I_REGION5_CTRL_EN_MASK 0x1
-#define GC_GLOBALSEC_CPU0_I_REGION5_CTRL_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_I_REGION5_CTRL_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_REGION5_CTRL_EN_OFFSET 0x74
-#define GC_GLOBALSEC_CPU0_I_REGION5_CTRL_RD_EN_LSB 0x1
-#define GC_GLOBALSEC_CPU0_I_REGION5_CTRL_RD_EN_MASK 0x2
-#define GC_GLOBALSEC_CPU0_I_REGION5_CTRL_RD_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_I_REGION5_CTRL_RD_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_REGION5_CTRL_RD_EN_OFFSET 0x74
-#define GC_GLOBALSEC_CPU0_I_REGION5_CTRL_WR_EN_LSB 0x2
-#define GC_GLOBALSEC_CPU0_I_REGION5_CTRL_WR_EN_MASK 0x4
-#define GC_GLOBALSEC_CPU0_I_REGION5_CTRL_WR_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_I_REGION5_CTRL_WR_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_REGION5_CTRL_WR_EN_OFFSET 0x74
-#define GC_GLOBALSEC_CPU0_I_REGION6_CTRL_EN_LSB  0x0
-#define GC_GLOBALSEC_CPU0_I_REGION6_CTRL_EN_MASK 0x1
-#define GC_GLOBALSEC_CPU0_I_REGION6_CTRL_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_I_REGION6_CTRL_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_REGION6_CTRL_EN_OFFSET 0x78
-#define GC_GLOBALSEC_CPU0_I_REGION6_CTRL_RD_EN_LSB 0x1
-#define GC_GLOBALSEC_CPU0_I_REGION6_CTRL_RD_EN_MASK 0x2
-#define GC_GLOBALSEC_CPU0_I_REGION6_CTRL_RD_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_I_REGION6_CTRL_RD_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_REGION6_CTRL_RD_EN_OFFSET 0x78
-#define GC_GLOBALSEC_CPU0_I_REGION6_CTRL_WR_EN_LSB 0x2
-#define GC_GLOBALSEC_CPU0_I_REGION6_CTRL_WR_EN_MASK 0x4
-#define GC_GLOBALSEC_CPU0_I_REGION6_CTRL_WR_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_I_REGION6_CTRL_WR_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_REGION6_CTRL_WR_EN_OFFSET 0x78
-#define GC_GLOBALSEC_CPU0_I_REGION7_CTRL_EN_LSB  0x0
-#define GC_GLOBALSEC_CPU0_I_REGION7_CTRL_EN_MASK 0x1
-#define GC_GLOBALSEC_CPU0_I_REGION7_CTRL_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_I_REGION7_CTRL_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_REGION7_CTRL_EN_OFFSET 0x7c
-#define GC_GLOBALSEC_CPU0_I_REGION7_CTRL_RD_EN_LSB 0x1
-#define GC_GLOBALSEC_CPU0_I_REGION7_CTRL_RD_EN_MASK 0x2
-#define GC_GLOBALSEC_CPU0_I_REGION7_CTRL_RD_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_I_REGION7_CTRL_RD_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_REGION7_CTRL_RD_EN_OFFSET 0x7c
-#define GC_GLOBALSEC_CPU0_I_REGION7_CTRL_WR_EN_LSB 0x2
-#define GC_GLOBALSEC_CPU0_I_REGION7_CTRL_WR_EN_MASK 0x4
-#define GC_GLOBALSEC_CPU0_I_REGION7_CTRL_WR_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_I_REGION7_CTRL_WR_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_REGION7_CTRL_WR_EN_OFFSET 0x7c
-#define GC_GLOBALSEC_DDMA0_REGION0_CTRL_EN_LSB   0x0
-#define GC_GLOBALSEC_DDMA0_REGION0_CTRL_EN_MASK  0x1
-#define GC_GLOBALSEC_DDMA0_REGION0_CTRL_EN_SIZE  0x1
-#define GC_GLOBALSEC_DDMA0_REGION0_CTRL_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_DDMA0_REGION0_CTRL_EN_OFFSET 0x80
-#define GC_GLOBALSEC_DDMA0_REGION0_CTRL_RD_EN_LSB 0x1
-#define GC_GLOBALSEC_DDMA0_REGION0_CTRL_RD_EN_MASK 0x2
-#define GC_GLOBALSEC_DDMA0_REGION0_CTRL_RD_EN_SIZE 0x1
-#define GC_GLOBALSEC_DDMA0_REGION0_CTRL_RD_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_DDMA0_REGION0_CTRL_RD_EN_OFFSET 0x80
-#define GC_GLOBALSEC_DDMA0_REGION0_CTRL_WR_EN_LSB 0x2
-#define GC_GLOBALSEC_DDMA0_REGION0_CTRL_WR_EN_MASK 0x4
-#define GC_GLOBALSEC_DDMA0_REGION0_CTRL_WR_EN_SIZE 0x1
-#define GC_GLOBALSEC_DDMA0_REGION0_CTRL_WR_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_DDMA0_REGION0_CTRL_WR_EN_OFFSET 0x80
-#define GC_GLOBALSEC_DDMA0_REGION1_CTRL_EN_LSB   0x0
-#define GC_GLOBALSEC_DDMA0_REGION1_CTRL_EN_MASK  0x1
-#define GC_GLOBALSEC_DDMA0_REGION1_CTRL_EN_SIZE  0x1
-#define GC_GLOBALSEC_DDMA0_REGION1_CTRL_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_DDMA0_REGION1_CTRL_EN_OFFSET 0x84
-#define GC_GLOBALSEC_DDMA0_REGION1_CTRL_RD_EN_LSB 0x1
-#define GC_GLOBALSEC_DDMA0_REGION1_CTRL_RD_EN_MASK 0x2
-#define GC_GLOBALSEC_DDMA0_REGION1_CTRL_RD_EN_SIZE 0x1
-#define GC_GLOBALSEC_DDMA0_REGION1_CTRL_RD_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_DDMA0_REGION1_CTRL_RD_EN_OFFSET 0x84
-#define GC_GLOBALSEC_DDMA0_REGION1_CTRL_WR_EN_LSB 0x2
-#define GC_GLOBALSEC_DDMA0_REGION1_CTRL_WR_EN_MASK 0x4
-#define GC_GLOBALSEC_DDMA0_REGION1_CTRL_WR_EN_SIZE 0x1
-#define GC_GLOBALSEC_DDMA0_REGION1_CTRL_WR_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_DDMA0_REGION1_CTRL_WR_EN_OFFSET 0x84
-#define GC_GLOBALSEC_DDMA0_REGION2_CTRL_EN_LSB   0x0
-#define GC_GLOBALSEC_DDMA0_REGION2_CTRL_EN_MASK  0x1
-#define GC_GLOBALSEC_DDMA0_REGION2_CTRL_EN_SIZE  0x1
-#define GC_GLOBALSEC_DDMA0_REGION2_CTRL_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_DDMA0_REGION2_CTRL_EN_OFFSET 0x88
-#define GC_GLOBALSEC_DDMA0_REGION2_CTRL_RD_EN_LSB 0x1
-#define GC_GLOBALSEC_DDMA0_REGION2_CTRL_RD_EN_MASK 0x2
-#define GC_GLOBALSEC_DDMA0_REGION2_CTRL_RD_EN_SIZE 0x1
-#define GC_GLOBALSEC_DDMA0_REGION2_CTRL_RD_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_DDMA0_REGION2_CTRL_RD_EN_OFFSET 0x88
-#define GC_GLOBALSEC_DDMA0_REGION2_CTRL_WR_EN_LSB 0x2
-#define GC_GLOBALSEC_DDMA0_REGION2_CTRL_WR_EN_MASK 0x4
-#define GC_GLOBALSEC_DDMA0_REGION2_CTRL_WR_EN_SIZE 0x1
-#define GC_GLOBALSEC_DDMA0_REGION2_CTRL_WR_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_DDMA0_REGION2_CTRL_WR_EN_OFFSET 0x88
-#define GC_GLOBALSEC_DDMA0_REGION3_CTRL_EN_LSB   0x0
-#define GC_GLOBALSEC_DDMA0_REGION3_CTRL_EN_MASK  0x1
-#define GC_GLOBALSEC_DDMA0_REGION3_CTRL_EN_SIZE  0x1
-#define GC_GLOBALSEC_DDMA0_REGION3_CTRL_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_DDMA0_REGION3_CTRL_EN_OFFSET 0x8c
-#define GC_GLOBALSEC_DDMA0_REGION3_CTRL_RD_EN_LSB 0x1
-#define GC_GLOBALSEC_DDMA0_REGION3_CTRL_RD_EN_MASK 0x2
-#define GC_GLOBALSEC_DDMA0_REGION3_CTRL_RD_EN_SIZE 0x1
-#define GC_GLOBALSEC_DDMA0_REGION3_CTRL_RD_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_DDMA0_REGION3_CTRL_RD_EN_OFFSET 0x8c
-#define GC_GLOBALSEC_DDMA0_REGION3_CTRL_WR_EN_LSB 0x2
-#define GC_GLOBALSEC_DDMA0_REGION3_CTRL_WR_EN_MASK 0x4
-#define GC_GLOBALSEC_DDMA0_REGION3_CTRL_WR_EN_SIZE 0x1
-#define GC_GLOBALSEC_DDMA0_REGION3_CTRL_WR_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_DDMA0_REGION3_CTRL_WR_EN_OFFSET 0x8c
-#define GC_GLOBALSEC_DSPS0_REGION0_CTRL_EN_LSB   0x0
-#define GC_GLOBALSEC_DSPS0_REGION0_CTRL_EN_MASK  0x1
-#define GC_GLOBALSEC_DSPS0_REGION0_CTRL_EN_SIZE  0x1
-#define GC_GLOBALSEC_DSPS0_REGION0_CTRL_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_DSPS0_REGION0_CTRL_EN_OFFSET 0xa0
-#define GC_GLOBALSEC_DSPS0_REGION0_CTRL_RD_EN_LSB 0x1
-#define GC_GLOBALSEC_DSPS0_REGION0_CTRL_RD_EN_MASK 0x2
-#define GC_GLOBALSEC_DSPS0_REGION0_CTRL_RD_EN_SIZE 0x1
-#define GC_GLOBALSEC_DSPS0_REGION0_CTRL_RD_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_DSPS0_REGION0_CTRL_RD_EN_OFFSET 0xa0
-#define GC_GLOBALSEC_DSPS0_REGION0_CTRL_WR_EN_LSB 0x2
-#define GC_GLOBALSEC_DSPS0_REGION0_CTRL_WR_EN_MASK 0x4
-#define GC_GLOBALSEC_DSPS0_REGION0_CTRL_WR_EN_SIZE 0x1
-#define GC_GLOBALSEC_DSPS0_REGION0_CTRL_WR_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_DSPS0_REGION0_CTRL_WR_EN_OFFSET 0xa0
-#define GC_GLOBALSEC_DSPS0_REGION1_CTRL_EN_LSB   0x0
-#define GC_GLOBALSEC_DSPS0_REGION1_CTRL_EN_MASK  0x1
-#define GC_GLOBALSEC_DSPS0_REGION1_CTRL_EN_SIZE  0x1
-#define GC_GLOBALSEC_DSPS0_REGION1_CTRL_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_DSPS0_REGION1_CTRL_EN_OFFSET 0xa4
-#define GC_GLOBALSEC_DSPS0_REGION1_CTRL_RD_EN_LSB 0x1
-#define GC_GLOBALSEC_DSPS0_REGION1_CTRL_RD_EN_MASK 0x2
-#define GC_GLOBALSEC_DSPS0_REGION1_CTRL_RD_EN_SIZE 0x1
-#define GC_GLOBALSEC_DSPS0_REGION1_CTRL_RD_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_DSPS0_REGION1_CTRL_RD_EN_OFFSET 0xa4
-#define GC_GLOBALSEC_DSPS0_REGION1_CTRL_WR_EN_LSB 0x2
-#define GC_GLOBALSEC_DSPS0_REGION1_CTRL_WR_EN_MASK 0x4
-#define GC_GLOBALSEC_DSPS0_REGION1_CTRL_WR_EN_SIZE 0x1
-#define GC_GLOBALSEC_DSPS0_REGION1_CTRL_WR_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_DSPS0_REGION1_CTRL_WR_EN_OFFSET 0xa4
-#define GC_GLOBALSEC_DSPS0_REGION2_CTRL_EN_LSB   0x0
-#define GC_GLOBALSEC_DSPS0_REGION2_CTRL_EN_MASK  0x1
-#define GC_GLOBALSEC_DSPS0_REGION2_CTRL_EN_SIZE  0x1
-#define GC_GLOBALSEC_DSPS0_REGION2_CTRL_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_DSPS0_REGION2_CTRL_EN_OFFSET 0xa8
-#define GC_GLOBALSEC_DSPS0_REGION2_CTRL_RD_EN_LSB 0x1
-#define GC_GLOBALSEC_DSPS0_REGION2_CTRL_RD_EN_MASK 0x2
-#define GC_GLOBALSEC_DSPS0_REGION2_CTRL_RD_EN_SIZE 0x1
-#define GC_GLOBALSEC_DSPS0_REGION2_CTRL_RD_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_DSPS0_REGION2_CTRL_RD_EN_OFFSET 0xa8
-#define GC_GLOBALSEC_DSPS0_REGION2_CTRL_WR_EN_LSB 0x2
-#define GC_GLOBALSEC_DSPS0_REGION2_CTRL_WR_EN_MASK 0x4
-#define GC_GLOBALSEC_DSPS0_REGION2_CTRL_WR_EN_SIZE 0x1
-#define GC_GLOBALSEC_DSPS0_REGION2_CTRL_WR_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_DSPS0_REGION2_CTRL_WR_EN_OFFSET 0xa8
-#define GC_GLOBALSEC_DSPS0_REGION3_CTRL_EN_LSB   0x0
-#define GC_GLOBALSEC_DSPS0_REGION3_CTRL_EN_MASK  0x1
-#define GC_GLOBALSEC_DSPS0_REGION3_CTRL_EN_SIZE  0x1
-#define GC_GLOBALSEC_DSPS0_REGION3_CTRL_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_DSPS0_REGION3_CTRL_EN_OFFSET 0xac
-#define GC_GLOBALSEC_DSPS0_REGION3_CTRL_RD_EN_LSB 0x1
-#define GC_GLOBALSEC_DSPS0_REGION3_CTRL_RD_EN_MASK 0x2
-#define GC_GLOBALSEC_DSPS0_REGION3_CTRL_RD_EN_SIZE 0x1
-#define GC_GLOBALSEC_DSPS0_REGION3_CTRL_RD_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_DSPS0_REGION3_CTRL_RD_EN_OFFSET 0xac
-#define GC_GLOBALSEC_DSPS0_REGION3_CTRL_WR_EN_LSB 0x2
-#define GC_GLOBALSEC_DSPS0_REGION3_CTRL_WR_EN_MASK 0x4
-#define GC_GLOBALSEC_DSPS0_REGION3_CTRL_WR_EN_SIZE 0x1
-#define GC_GLOBALSEC_DSPS0_REGION3_CTRL_WR_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_DSPS0_REGION3_CTRL_WR_EN_OFFSET 0xac
-#define GC_GLOBALSEC_DUSB0_REGION0_CTRL_EN_LSB   0x0
-#define GC_GLOBALSEC_DUSB0_REGION0_CTRL_EN_MASK  0x1
-#define GC_GLOBALSEC_DUSB0_REGION0_CTRL_EN_SIZE  0x1
-#define GC_GLOBALSEC_DUSB0_REGION0_CTRL_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_DUSB0_REGION0_CTRL_EN_OFFSET 0xc0
-#define GC_GLOBALSEC_DUSB0_REGION0_CTRL_RD_EN_LSB 0x1
-#define GC_GLOBALSEC_DUSB0_REGION0_CTRL_RD_EN_MASK 0x2
-#define GC_GLOBALSEC_DUSB0_REGION0_CTRL_RD_EN_SIZE 0x1
-#define GC_GLOBALSEC_DUSB0_REGION0_CTRL_RD_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_DUSB0_REGION0_CTRL_RD_EN_OFFSET 0xc0
-#define GC_GLOBALSEC_DUSB0_REGION0_CTRL_WR_EN_LSB 0x2
-#define GC_GLOBALSEC_DUSB0_REGION0_CTRL_WR_EN_MASK 0x4
-#define GC_GLOBALSEC_DUSB0_REGION0_CTRL_WR_EN_SIZE 0x1
-#define GC_GLOBALSEC_DUSB0_REGION0_CTRL_WR_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_DUSB0_REGION0_CTRL_WR_EN_OFFSET 0xc0
-#define GC_GLOBALSEC_DUSB0_REGION1_CTRL_EN_LSB   0x0
-#define GC_GLOBALSEC_DUSB0_REGION1_CTRL_EN_MASK  0x1
-#define GC_GLOBALSEC_DUSB0_REGION1_CTRL_EN_SIZE  0x1
-#define GC_GLOBALSEC_DUSB0_REGION1_CTRL_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_DUSB0_REGION1_CTRL_EN_OFFSET 0xc4
-#define GC_GLOBALSEC_DUSB0_REGION1_CTRL_RD_EN_LSB 0x1
-#define GC_GLOBALSEC_DUSB0_REGION1_CTRL_RD_EN_MASK 0x2
-#define GC_GLOBALSEC_DUSB0_REGION1_CTRL_RD_EN_SIZE 0x1
-#define GC_GLOBALSEC_DUSB0_REGION1_CTRL_RD_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_DUSB0_REGION1_CTRL_RD_EN_OFFSET 0xc4
-#define GC_GLOBALSEC_DUSB0_REGION1_CTRL_WR_EN_LSB 0x2
-#define GC_GLOBALSEC_DUSB0_REGION1_CTRL_WR_EN_MASK 0x4
-#define GC_GLOBALSEC_DUSB0_REGION1_CTRL_WR_EN_SIZE 0x1
-#define GC_GLOBALSEC_DUSB0_REGION1_CTRL_WR_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_DUSB0_REGION1_CTRL_WR_EN_OFFSET 0xc4
-#define GC_GLOBALSEC_DUSB0_REGION2_CTRL_EN_LSB   0x0
-#define GC_GLOBALSEC_DUSB0_REGION2_CTRL_EN_MASK  0x1
-#define GC_GLOBALSEC_DUSB0_REGION2_CTRL_EN_SIZE  0x1
-#define GC_GLOBALSEC_DUSB0_REGION2_CTRL_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_DUSB0_REGION2_CTRL_EN_OFFSET 0xc8
-#define GC_GLOBALSEC_DUSB0_REGION2_CTRL_RD_EN_LSB 0x1
-#define GC_GLOBALSEC_DUSB0_REGION2_CTRL_RD_EN_MASK 0x2
-#define GC_GLOBALSEC_DUSB0_REGION2_CTRL_RD_EN_SIZE 0x1
-#define GC_GLOBALSEC_DUSB0_REGION2_CTRL_RD_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_DUSB0_REGION2_CTRL_RD_EN_OFFSET 0xc8
-#define GC_GLOBALSEC_DUSB0_REGION2_CTRL_WR_EN_LSB 0x2
-#define GC_GLOBALSEC_DUSB0_REGION2_CTRL_WR_EN_MASK 0x4
-#define GC_GLOBALSEC_DUSB0_REGION2_CTRL_WR_EN_SIZE 0x1
-#define GC_GLOBALSEC_DUSB0_REGION2_CTRL_WR_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_DUSB0_REGION2_CTRL_WR_EN_OFFSET 0xc8
-#define GC_GLOBALSEC_DUSB0_REGION3_CTRL_EN_LSB   0x0
-#define GC_GLOBALSEC_DUSB0_REGION3_CTRL_EN_MASK  0x1
-#define GC_GLOBALSEC_DUSB0_REGION3_CTRL_EN_SIZE  0x1
-#define GC_GLOBALSEC_DUSB0_REGION3_CTRL_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_DUSB0_REGION3_CTRL_EN_OFFSET 0xcc
-#define GC_GLOBALSEC_DUSB0_REGION3_CTRL_RD_EN_LSB 0x1
-#define GC_GLOBALSEC_DUSB0_REGION3_CTRL_RD_EN_MASK 0x2
-#define GC_GLOBALSEC_DUSB0_REGION3_CTRL_RD_EN_SIZE 0x1
-#define GC_GLOBALSEC_DUSB0_REGION3_CTRL_RD_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_DUSB0_REGION3_CTRL_RD_EN_OFFSET 0xcc
-#define GC_GLOBALSEC_DUSB0_REGION3_CTRL_WR_EN_LSB 0x2
-#define GC_GLOBALSEC_DUSB0_REGION3_CTRL_WR_EN_MASK 0x4
-#define GC_GLOBALSEC_DUSB0_REGION3_CTRL_WR_EN_SIZE 0x1
-#define GC_GLOBALSEC_DUSB0_REGION3_CTRL_WR_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_DUSB0_REGION3_CTRL_WR_EN_OFFSET 0xcc
-#define GC_GLOBALSEC_FLASH_REGION0_CTRL_EN_LSB   0x0
-#define GC_GLOBALSEC_FLASH_REGION0_CTRL_EN_MASK  0x1
-#define GC_GLOBALSEC_FLASH_REGION0_CTRL_EN_SIZE  0x1
-#define GC_GLOBALSEC_FLASH_REGION0_CTRL_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_FLASH_REGION0_CTRL_EN_OFFSET 0xe0
-#define GC_GLOBALSEC_FLASH_REGION0_CTRL_RD_EN_LSB 0x1
-#define GC_GLOBALSEC_FLASH_REGION0_CTRL_RD_EN_MASK 0x2
-#define GC_GLOBALSEC_FLASH_REGION0_CTRL_RD_EN_SIZE 0x1
-#define GC_GLOBALSEC_FLASH_REGION0_CTRL_RD_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_FLASH_REGION0_CTRL_RD_EN_OFFSET 0xe0
-#define GC_GLOBALSEC_FLASH_REGION0_CTRL_WR_EN_LSB 0x2
-#define GC_GLOBALSEC_FLASH_REGION0_CTRL_WR_EN_MASK 0x4
-#define GC_GLOBALSEC_FLASH_REGION0_CTRL_WR_EN_SIZE 0x1
-#define GC_GLOBALSEC_FLASH_REGION0_CTRL_WR_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_FLASH_REGION0_CTRL_WR_EN_OFFSET 0xe0
-#define GC_GLOBALSEC_FLASH_REGION1_CTRL_EN_LSB   0x0
-#define GC_GLOBALSEC_FLASH_REGION1_CTRL_EN_MASK  0x1
-#define GC_GLOBALSEC_FLASH_REGION1_CTRL_EN_SIZE  0x1
-#define GC_GLOBALSEC_FLASH_REGION1_CTRL_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_FLASH_REGION1_CTRL_EN_OFFSET 0xe4
-#define GC_GLOBALSEC_FLASH_REGION1_CTRL_RD_EN_LSB 0x1
-#define GC_GLOBALSEC_FLASH_REGION1_CTRL_RD_EN_MASK 0x2
-#define GC_GLOBALSEC_FLASH_REGION1_CTRL_RD_EN_SIZE 0x1
-#define GC_GLOBALSEC_FLASH_REGION1_CTRL_RD_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_FLASH_REGION1_CTRL_RD_EN_OFFSET 0xe4
-#define GC_GLOBALSEC_FLASH_REGION1_CTRL_WR_EN_LSB 0x2
-#define GC_GLOBALSEC_FLASH_REGION1_CTRL_WR_EN_MASK 0x4
-#define GC_GLOBALSEC_FLASH_REGION1_CTRL_WR_EN_SIZE 0x1
-#define GC_GLOBALSEC_FLASH_REGION1_CTRL_WR_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_FLASH_REGION1_CTRL_WR_EN_OFFSET 0xe4
-#define GC_GLOBALSEC_FLASH_REGION2_CTRL_EN_LSB   0x0
-#define GC_GLOBALSEC_FLASH_REGION2_CTRL_EN_MASK  0x1
-#define GC_GLOBALSEC_FLASH_REGION2_CTRL_EN_SIZE  0x1
-#define GC_GLOBALSEC_FLASH_REGION2_CTRL_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_FLASH_REGION2_CTRL_EN_OFFSET 0xe8
-#define GC_GLOBALSEC_FLASH_REGION2_CTRL_RD_EN_LSB 0x1
-#define GC_GLOBALSEC_FLASH_REGION2_CTRL_RD_EN_MASK 0x2
-#define GC_GLOBALSEC_FLASH_REGION2_CTRL_RD_EN_SIZE 0x1
-#define GC_GLOBALSEC_FLASH_REGION2_CTRL_RD_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_FLASH_REGION2_CTRL_RD_EN_OFFSET 0xe8
-#define GC_GLOBALSEC_FLASH_REGION2_CTRL_WR_EN_LSB 0x2
-#define GC_GLOBALSEC_FLASH_REGION2_CTRL_WR_EN_MASK 0x4
-#define GC_GLOBALSEC_FLASH_REGION2_CTRL_WR_EN_SIZE 0x1
-#define GC_GLOBALSEC_FLASH_REGION2_CTRL_WR_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_FLASH_REGION2_CTRL_WR_EN_OFFSET 0xe8
-#define GC_GLOBALSEC_FLASH_REGION3_CTRL_EN_LSB   0x0
-#define GC_GLOBALSEC_FLASH_REGION3_CTRL_EN_MASK  0x1
-#define GC_GLOBALSEC_FLASH_REGION3_CTRL_EN_SIZE  0x1
-#define GC_GLOBALSEC_FLASH_REGION3_CTRL_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_FLASH_REGION3_CTRL_EN_OFFSET 0xec
-#define GC_GLOBALSEC_FLASH_REGION3_CTRL_RD_EN_LSB 0x1
-#define GC_GLOBALSEC_FLASH_REGION3_CTRL_RD_EN_MASK 0x2
-#define GC_GLOBALSEC_FLASH_REGION3_CTRL_RD_EN_SIZE 0x1
-#define GC_GLOBALSEC_FLASH_REGION3_CTRL_RD_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_FLASH_REGION3_CTRL_RD_EN_OFFSET 0xec
-#define GC_GLOBALSEC_FLASH_REGION3_CTRL_WR_EN_LSB 0x2
-#define GC_GLOBALSEC_FLASH_REGION3_CTRL_WR_EN_MASK 0x4
-#define GC_GLOBALSEC_FLASH_REGION3_CTRL_WR_EN_SIZE 0x1
-#define GC_GLOBALSEC_FLASH_REGION3_CTRL_WR_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_FLASH_REGION3_CTRL_WR_EN_OFFSET 0xec
-#define GC_GLOBALSEC_FLASH_REGION4_CTRL_EN_LSB   0x0
-#define GC_GLOBALSEC_FLASH_REGION4_CTRL_EN_MASK  0x1
-#define GC_GLOBALSEC_FLASH_REGION4_CTRL_EN_SIZE  0x1
-#define GC_GLOBALSEC_FLASH_REGION4_CTRL_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_FLASH_REGION4_CTRL_EN_OFFSET 0xf0
-#define GC_GLOBALSEC_FLASH_REGION4_CTRL_RD_EN_LSB 0x1
-#define GC_GLOBALSEC_FLASH_REGION4_CTRL_RD_EN_MASK 0x2
-#define GC_GLOBALSEC_FLASH_REGION4_CTRL_RD_EN_SIZE 0x1
-#define GC_GLOBALSEC_FLASH_REGION4_CTRL_RD_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_FLASH_REGION4_CTRL_RD_EN_OFFSET 0xf0
-#define GC_GLOBALSEC_FLASH_REGION4_CTRL_WR_EN_LSB 0x2
-#define GC_GLOBALSEC_FLASH_REGION4_CTRL_WR_EN_MASK 0x4
-#define GC_GLOBALSEC_FLASH_REGION4_CTRL_WR_EN_SIZE 0x1
-#define GC_GLOBALSEC_FLASH_REGION4_CTRL_WR_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_FLASH_REGION4_CTRL_WR_EN_OFFSET 0xf0
-#define GC_GLOBALSEC_FLASH_REGION5_CTRL_EN_LSB   0x0
-#define GC_GLOBALSEC_FLASH_REGION5_CTRL_EN_MASK  0x1
-#define GC_GLOBALSEC_FLASH_REGION5_CTRL_EN_SIZE  0x1
-#define GC_GLOBALSEC_FLASH_REGION5_CTRL_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_FLASH_REGION5_CTRL_EN_OFFSET 0xf4
-#define GC_GLOBALSEC_FLASH_REGION5_CTRL_RD_EN_LSB 0x1
-#define GC_GLOBALSEC_FLASH_REGION5_CTRL_RD_EN_MASK 0x2
-#define GC_GLOBALSEC_FLASH_REGION5_CTRL_RD_EN_SIZE 0x1
-#define GC_GLOBALSEC_FLASH_REGION5_CTRL_RD_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_FLASH_REGION5_CTRL_RD_EN_OFFSET 0xf4
-#define GC_GLOBALSEC_FLASH_REGION5_CTRL_WR_EN_LSB 0x2
-#define GC_GLOBALSEC_FLASH_REGION5_CTRL_WR_EN_MASK 0x4
-#define GC_GLOBALSEC_FLASH_REGION5_CTRL_WR_EN_SIZE 0x1
-#define GC_GLOBALSEC_FLASH_REGION5_CTRL_WR_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_FLASH_REGION5_CTRL_WR_EN_OFFSET 0xf4
-#define GC_GLOBALSEC_FLASH_REGION6_CTRL_EN_LSB   0x0
-#define GC_GLOBALSEC_FLASH_REGION6_CTRL_EN_MASK  0x1
-#define GC_GLOBALSEC_FLASH_REGION6_CTRL_EN_SIZE  0x1
-#define GC_GLOBALSEC_FLASH_REGION6_CTRL_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_FLASH_REGION6_CTRL_EN_OFFSET 0xf8
-#define GC_GLOBALSEC_FLASH_REGION6_CTRL_RD_EN_LSB 0x1
-#define GC_GLOBALSEC_FLASH_REGION6_CTRL_RD_EN_MASK 0x2
-#define GC_GLOBALSEC_FLASH_REGION6_CTRL_RD_EN_SIZE 0x1
-#define GC_GLOBALSEC_FLASH_REGION6_CTRL_RD_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_FLASH_REGION6_CTRL_RD_EN_OFFSET 0xf8
-#define GC_GLOBALSEC_FLASH_REGION6_CTRL_WR_EN_LSB 0x2
-#define GC_GLOBALSEC_FLASH_REGION6_CTRL_WR_EN_MASK 0x4
-#define GC_GLOBALSEC_FLASH_REGION6_CTRL_WR_EN_SIZE 0x1
-#define GC_GLOBALSEC_FLASH_REGION6_CTRL_WR_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_FLASH_REGION6_CTRL_WR_EN_OFFSET 0xf8
-#define GC_GLOBALSEC_FLASH_REGION7_CTRL_EN_LSB   0x0
-#define GC_GLOBALSEC_FLASH_REGION7_CTRL_EN_MASK  0x1
-#define GC_GLOBALSEC_FLASH_REGION7_CTRL_EN_SIZE  0x1
-#define GC_GLOBALSEC_FLASH_REGION7_CTRL_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_FLASH_REGION7_CTRL_EN_OFFSET 0xfc
-#define GC_GLOBALSEC_FLASH_REGION7_CTRL_RD_EN_LSB 0x1
-#define GC_GLOBALSEC_FLASH_REGION7_CTRL_RD_EN_MASK 0x2
-#define GC_GLOBALSEC_FLASH_REGION7_CTRL_RD_EN_SIZE 0x1
-#define GC_GLOBALSEC_FLASH_REGION7_CTRL_RD_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_FLASH_REGION7_CTRL_RD_EN_OFFSET 0xfc
-#define GC_GLOBALSEC_FLASH_REGION7_CTRL_WR_EN_LSB 0x2
-#define GC_GLOBALSEC_FLASH_REGION7_CTRL_WR_EN_MASK 0x4
-#define GC_GLOBALSEC_FLASH_REGION7_CTRL_WR_EN_SIZE 0x1
-#define GC_GLOBALSEC_FLASH_REGION7_CTRL_WR_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_FLASH_REGION7_CTRL_WR_EN_OFFSET 0xfc
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_EN_LSB 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_EN_MASK 0x1
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_EN_OFFSET 0x270
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_RD_EN_LSB 0x1
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_RD_EN_MASK 0x2
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_RD_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_RD_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_RD_EN_OFFSET 0x270
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_WR_EN_LSB 0x2
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_WR_EN_MASK 0x4
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_WR_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_WR_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_WR_EN_OFFSET 0x270
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_EN_LSB 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_EN_MASK 0x1
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_EN_OFFSET 0x27c
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_RD_EN_LSB 0x1
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_RD_EN_MASK 0x2
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_RD_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_RD_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_RD_EN_OFFSET 0x27c
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_WR_EN_LSB 0x2
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_WR_EN_MASK 0x4
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_WR_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_WR_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_WR_EN_OFFSET 0x27c
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_EN_LSB 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_EN_MASK 0x1
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_EN_OFFSET 0x288
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_RD_EN_LSB 0x1
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_RD_EN_MASK 0x2
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_RD_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_RD_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_RD_EN_OFFSET 0x288
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_WR_EN_LSB 0x2
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_WR_EN_MASK 0x4
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_WR_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_WR_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_WR_EN_OFFSET 0x288
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_EN_LSB 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_EN_MASK 0x1
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_EN_OFFSET 0x294
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_RD_EN_LSB 0x1
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_RD_EN_MASK 0x2
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_RD_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_RD_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_RD_EN_OFFSET 0x294
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_WR_EN_LSB 0x2
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_WR_EN_MASK 0x4
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_WR_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_WR_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_WR_EN_OFFSET 0x294
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_EN_LSB 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_EN_MASK 0x1
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_EN_OFFSET 0x2a0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_RD_EN_LSB 0x1
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_RD_EN_MASK 0x2
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_RD_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_RD_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_RD_EN_OFFSET 0x2a0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_WR_EN_LSB 0x2
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_WR_EN_MASK 0x4
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_WR_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_WR_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_WR_EN_OFFSET 0x2a0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_EN_LSB 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_EN_MASK 0x1
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_EN_OFFSET 0x2ac
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_RD_EN_LSB 0x1
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_RD_EN_MASK 0x2
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_RD_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_RD_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_RD_EN_OFFSET 0x2ac
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_WR_EN_LSB 0x2
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_WR_EN_MASK 0x4
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_WR_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_WR_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_WR_EN_OFFSET 0x2ac
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_EN_LSB 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_EN_MASK 0x1
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_EN_OFFSET 0x2b8
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_RD_EN_LSB 0x1
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_RD_EN_MASK 0x2
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_RD_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_RD_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_RD_EN_OFFSET 0x2b8
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_WR_EN_LSB 0x2
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_WR_EN_MASK 0x4
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_WR_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_WR_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_WR_EN_OFFSET 0x2b8
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_EN_LSB 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_EN_MASK 0x1
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_EN_OFFSET 0x2c4
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_RD_EN_LSB 0x1
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_RD_EN_MASK 0x2
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_RD_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_RD_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_RD_EN_OFFSET 0x2c4
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_WR_EN_LSB 0x2
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_WR_EN_MASK 0x4
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_WR_EN_SIZE 0x1
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_WR_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_WR_EN_OFFSET 0x2c4
-#define GC_GLOBALSEC_SB_COMP_STATUS_SB_BL_SIG_MATCH_LSB 0x0
-#define GC_GLOBALSEC_SB_COMP_STATUS_SB_BL_SIG_MATCH_MASK 0x1
-#define GC_GLOBALSEC_SB_COMP_STATUS_SB_BL_SIG_MATCH_SIZE 0x1
-#define GC_GLOBALSEC_SB_COMP_STATUS_SB_BL_SIG_MATCH_DEFAULT 0x0
-#define GC_GLOBALSEC_SB_COMP_STATUS_SB_BL_SIG_MATCH_OFFSET 0x1000
-#define GC_GLOBALSEC_INT_ERR_FLAGS_DEV_ST_DEC_ERR_LSB 0x18
-#define GC_GLOBALSEC_INT_ERR_FLAGS_DEV_ST_DEC_ERR_MASK 0x1000000
-#define GC_GLOBALSEC_INT_ERR_FLAGS_DEV_ST_DEC_ERR_SIZE 0x1
-#define GC_GLOBALSEC_INT_ERR_FLAGS_DEV_ST_DEC_ERR_DEFAULT 0x0
-#define GC_GLOBALSEC_INT_ERR_FLAGS_DEV_ST_DEC_ERR_OFFSET 0x1028
-#define GC_GLOBALSEC_ALERT_INTR_STS0_CAMO0_BREACH_ALERT_LSB 0x0
-#define GC_GLOBALSEC_ALERT_INTR_STS0_CAMO0_BREACH_ALERT_MASK 0x1
-#define GC_GLOBALSEC_ALERT_INTR_STS0_CAMO0_BREACH_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_INTR_STS0_CAMO0_BREACH_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_INTR_STS0_CAMO0_BREACH_ALERT_OFFSET 0x4004
-#define GC_GLOBALSEC_ALERT_INTR_STS0_CRYPTO0_DMEM_PARITY_ALERT_LSB 0x1
-#define GC_GLOBALSEC_ALERT_INTR_STS0_CRYPTO0_DMEM_PARITY_ALERT_MASK 0x2
-#define GC_GLOBALSEC_ALERT_INTR_STS0_CRYPTO0_DMEM_PARITY_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_INTR_STS0_CRYPTO0_DMEM_PARITY_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_INTR_STS0_CRYPTO0_DMEM_PARITY_ALERT_OFFSET 0x4004
-#define GC_GLOBALSEC_ALERT_INTR_STS0_CRYPTO0_DRF_PARITY_ALERT_LSB 0x2
-#define GC_GLOBALSEC_ALERT_INTR_STS0_CRYPTO0_DRF_PARITY_ALERT_MASK 0x4
-#define GC_GLOBALSEC_ALERT_INTR_STS0_CRYPTO0_DRF_PARITY_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_INTR_STS0_CRYPTO0_DRF_PARITY_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_INTR_STS0_CRYPTO0_DRF_PARITY_ALERT_OFFSET 0x4004
-#define GC_GLOBALSEC_ALERT_INTR_STS0_CRYPTO0_IMEM_PARITY_ALERT_LSB 0x3
-#define GC_GLOBALSEC_ALERT_INTR_STS0_CRYPTO0_IMEM_PARITY_ALERT_MASK 0x8
-#define GC_GLOBALSEC_ALERT_INTR_STS0_CRYPTO0_IMEM_PARITY_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_INTR_STS0_CRYPTO0_IMEM_PARITY_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_INTR_STS0_CRYPTO0_IMEM_PARITY_ALERT_OFFSET 0x4004
-#define GC_GLOBALSEC_ALERT_INTR_STS0_CRYPTO0_PGM_FAULT_ALERT_LSB 0x4
-#define GC_GLOBALSEC_ALERT_INTR_STS0_CRYPTO0_PGM_FAULT_ALERT_MASK 0x10
-#define GC_GLOBALSEC_ALERT_INTR_STS0_CRYPTO0_PGM_FAULT_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_INTR_STS0_CRYPTO0_PGM_FAULT_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_INTR_STS0_CRYPTO0_PGM_FAULT_ALERT_OFFSET 0x4004
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_LSB 0x5
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_MASK 0x20
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_OFFSET 0x4004
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_LSB 0x6
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_MASK 0x40
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4004
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_LSB 0x7
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_MASK 0x80
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_OFFSET 0x4004
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_LSB 0x8
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_MASK 0x100
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4004
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_LSB 0x9
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_MASK 0x200
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_OFFSET 0x4004
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_LSB 0xa
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_MASK 0x400
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4004
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_LSB 0xb
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_MASK 0x800
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_OFFSET 0x4004
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_LSB 0xc
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_MASK 0x1000
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4004
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_LSB 0xd
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_MASK 0x2000
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_OFFSET 0x4004
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_LSB 0xe
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_MASK 0x4000
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4004
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_LSB 0xf
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_MASK 0x8000
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_OFFSET 0x4004
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_LSB 0x10
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_MASK 0x10000
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_INTR_STS0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4004
-#define GC_GLOBALSEC_ALERT_INTR_STS0_FUSE0_FUSE_DEFAULTS_ALERT_LSB 0x11
-#define GC_GLOBALSEC_ALERT_INTR_STS0_FUSE0_FUSE_DEFAULTS_ALERT_MASK 0x20000
-#define GC_GLOBALSEC_ALERT_INTR_STS0_FUSE0_FUSE_DEFAULTS_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_INTR_STS0_FUSE0_FUSE_DEFAULTS_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_INTR_STS0_FUSE0_FUSE_DEFAULTS_ALERT_OFFSET 0x4004
-#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_DIFF_FAIL_ALERT_LSB 0x12
-#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_DIFF_FAIL_ALERT_MASK 0x40000
-#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_DIFF_FAIL_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_DIFF_FAIL_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_DIFF_FAIL_ALERT_OFFSET 0x4004
-#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW0_ALERT_LSB 0x13
-#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW0_ALERT_MASK 0x80000
-#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW0_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW0_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW0_ALERT_OFFSET 0x4004
-#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW1_ALERT_LSB 0x14
-#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW1_ALERT_MASK 0x100000
-#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW1_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW1_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW1_ALERT_OFFSET 0x4004
-#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW2_ALERT_LSB 0x15
-#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW2_ALERT_MASK 0x200000
-#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW2_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW2_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW2_ALERT_OFFSET 0x4004
-#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW3_ALERT_LSB 0x16
-#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW3_ALERT_MASK 0x400000
-#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW3_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW3_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_FW3_ALERT_OFFSET 0x4004
-#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_LSB 0x17
-#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_MASK 0x800000
-#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_OFFSET 0x4004
-#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_LSB 0x18
-#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_MASK 0x1000000
-#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_OFFSET 0x4004
-#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_LSB 0x19
-#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_MASK 0x2000000
-#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_INTR_STS0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_OFFSET 0x4004
-#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_LSB 0x1a
-#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_MASK 0x4000000
-#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_OFFSET 0x4004
-#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_AES_HKEY_ALERT_LSB 0x1b
-#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_AES_HKEY_ALERT_MASK 0x8000000
-#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_AES_HKEY_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_AES_HKEY_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_AES_HKEY_ALERT_OFFSET 0x4004
-#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_CERT_LOOKUP_ALERT_LSB 0x1c
-#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_CERT_LOOKUP_ALERT_MASK 0x10000000
-#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_CERT_LOOKUP_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_CERT_LOOKUP_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_CERT_LOOKUP_ALERT_OFFSET 0x4004
-#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_FLASH_ENTRY_ALERT_LSB 0x1d
-#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_FLASH_ENTRY_ALERT_MASK 0x20000000
-#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_FLASH_ENTRY_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_FLASH_ENTRY_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_FLASH_ENTRY_ALERT_OFFSET 0x4004
-#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_PW_ALERT_LSB 0x1e
-#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_PW_ALERT_MASK 0x40000000
-#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_PW_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_PW_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_PW_ALERT_OFFSET 0x4004
-#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_LSB 0x1f
-#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_MASK 0x80000000
-#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_INTR_STS0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_OFFSET 0x4004
-#define GC_GLOBALSEC_ALERT_INTR_STS1_KEYMGR0_SHA_FAULT_ALERT_LSB 0x0
-#define GC_GLOBALSEC_ALERT_INTR_STS1_KEYMGR0_SHA_FAULT_ALERT_MASK 0x1
-#define GC_GLOBALSEC_ALERT_INTR_STS1_KEYMGR0_SHA_FAULT_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_INTR_STS1_KEYMGR0_SHA_FAULT_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_INTR_STS1_KEYMGR0_SHA_FAULT_ALERT_OFFSET 0x4008
-#define GC_GLOBALSEC_ALERT_INTR_STS1_KEYMGR0_SHA_HKEY_ALERT_LSB 0x1
-#define GC_GLOBALSEC_ALERT_INTR_STS1_KEYMGR0_SHA_HKEY_ALERT_MASK 0x2
-#define GC_GLOBALSEC_ALERT_INTR_STS1_KEYMGR0_SHA_HKEY_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_INTR_STS1_KEYMGR0_SHA_HKEY_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_INTR_STS1_KEYMGR0_SHA_HKEY_ALERT_OFFSET 0x4008
-#define GC_GLOBALSEC_ALERT_INTR_STS1_PMU_BATTERY_MON_ALERT_LSB 0x2
-#define GC_GLOBALSEC_ALERT_INTR_STS1_PMU_BATTERY_MON_ALERT_MASK 0x4
-#define GC_GLOBALSEC_ALERT_INTR_STS1_PMU_BATTERY_MON_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_INTR_STS1_PMU_BATTERY_MON_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_INTR_STS1_PMU_BATTERY_MON_ALERT_OFFSET 0x4008
-#define GC_GLOBALSEC_ALERT_INTR_STS1_PMU_PMU_WDOG_ALERT_LSB 0x3
-#define GC_GLOBALSEC_ALERT_INTR_STS1_PMU_PMU_WDOG_ALERT_MASK 0x8
-#define GC_GLOBALSEC_ALERT_INTR_STS1_PMU_PMU_WDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_INTR_STS1_PMU_PMU_WDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_INTR_STS1_PMU_PMU_WDOG_ALERT_OFFSET 0x4008
-#define GC_GLOBALSEC_ALERT_INTR_STS1_RTC0_RTC_DEAD_ALERT_LSB 0x4
-#define GC_GLOBALSEC_ALERT_INTR_STS1_RTC0_RTC_DEAD_ALERT_MASK 0x10
-#define GC_GLOBALSEC_ALERT_INTR_STS1_RTC0_RTC_DEAD_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_INTR_STS1_RTC0_RTC_DEAD_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_INTR_STS1_RTC0_RTC_DEAD_ALERT_OFFSET 0x4008
-#define GC_GLOBALSEC_ALERT_INTR_STS1_TEMP0_MAX_TEMP_ALERT_LSB 0x5
-#define GC_GLOBALSEC_ALERT_INTR_STS1_TEMP0_MAX_TEMP_ALERT_MASK 0x20
-#define GC_GLOBALSEC_ALERT_INTR_STS1_TEMP0_MAX_TEMP_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_INTR_STS1_TEMP0_MAX_TEMP_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_INTR_STS1_TEMP0_MAX_TEMP_ALERT_OFFSET 0x4008
-#define GC_GLOBALSEC_ALERT_INTR_STS1_TEMP0_MAX_TEMP_DIFF_ALERT_LSB 0x6
-#define GC_GLOBALSEC_ALERT_INTR_STS1_TEMP0_MAX_TEMP_DIFF_ALERT_MASK 0x40
-#define GC_GLOBALSEC_ALERT_INTR_STS1_TEMP0_MAX_TEMP_DIFF_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_INTR_STS1_TEMP0_MAX_TEMP_DIFF_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_INTR_STS1_TEMP0_MAX_TEMP_DIFF_ALERT_OFFSET 0x4008
-#define GC_GLOBALSEC_ALERT_INTR_STS1_TEMP0_MIN_TEMP_ALERT_LSB 0x7
-#define GC_GLOBALSEC_ALERT_INTR_STS1_TEMP0_MIN_TEMP_ALERT_MASK 0x80
-#define GC_GLOBALSEC_ALERT_INTR_STS1_TEMP0_MIN_TEMP_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_INTR_STS1_TEMP0_MIN_TEMP_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_INTR_STS1_TEMP0_MIN_TEMP_ALERT_OFFSET 0x4008
-#define GC_GLOBALSEC_ALERT_INTR_STS1_TRNG0_OUT_OF_SPEC_ALERT_LSB 0x8
-#define GC_GLOBALSEC_ALERT_INTR_STS1_TRNG0_OUT_OF_SPEC_ALERT_MASK 0x100
-#define GC_GLOBALSEC_ALERT_INTR_STS1_TRNG0_OUT_OF_SPEC_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_INTR_STS1_TRNG0_OUT_OF_SPEC_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_INTR_STS1_TRNG0_OUT_OF_SPEC_ALERT_OFFSET 0x4008
-#define GC_GLOBALSEC_ALERT_INTR_STS1_TRNG0_TIMEOUT_ALERT_LSB 0x9
-#define GC_GLOBALSEC_ALERT_INTR_STS1_TRNG0_TIMEOUT_ALERT_MASK 0x200
-#define GC_GLOBALSEC_ALERT_INTR_STS1_TRNG0_TIMEOUT_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_INTR_STS1_TRNG0_TIMEOUT_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_INTR_STS1_TRNG0_TIMEOUT_ALERT_OFFSET 0x4008
-#define GC_GLOBALSEC_ALERT_INTR_STS1_VOLT0_VOLT_ERR_ALERT_LSB 0xa
-#define GC_GLOBALSEC_ALERT_INTR_STS1_VOLT0_VOLT_ERR_ALERT_MASK 0x400
-#define GC_GLOBALSEC_ALERT_INTR_STS1_VOLT0_VOLT_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_INTR_STS1_VOLT0_VOLT_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_INTR_STS1_VOLT0_VOLT_ERR_ALERT_OFFSET 0x4008
-#define GC_GLOBALSEC_ALERT_INTR_STS1_XO0_JITTERY_TRIM_DIS_ALERT_LSB 0xb
-#define GC_GLOBALSEC_ALERT_INTR_STS1_XO0_JITTERY_TRIM_DIS_ALERT_MASK 0x800
-#define GC_GLOBALSEC_ALERT_INTR_STS1_XO0_JITTERY_TRIM_DIS_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_INTR_STS1_XO0_JITTERY_TRIM_DIS_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_INTR_STS1_XO0_JITTERY_TRIM_DIS_ALERT_OFFSET 0x4008
-#define GC_GLOBALSEC_ALERT_NMI_EN0_CAMO0_BREACH_ALERT_LSB 0x0
-#define GC_GLOBALSEC_ALERT_NMI_EN0_CAMO0_BREACH_ALERT_MASK 0x1
-#define GC_GLOBALSEC_ALERT_NMI_EN0_CAMO0_BREACH_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_NMI_EN0_CAMO0_BREACH_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_NMI_EN0_CAMO0_BREACH_ALERT_OFFSET 0x400c
-#define GC_GLOBALSEC_ALERT_NMI_EN0_CRYPTO0_DMEM_PARITY_ALERT_LSB 0x1
-#define GC_GLOBALSEC_ALERT_NMI_EN0_CRYPTO0_DMEM_PARITY_ALERT_MASK 0x2
-#define GC_GLOBALSEC_ALERT_NMI_EN0_CRYPTO0_DMEM_PARITY_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_NMI_EN0_CRYPTO0_DMEM_PARITY_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_NMI_EN0_CRYPTO0_DMEM_PARITY_ALERT_OFFSET 0x400c
-#define GC_GLOBALSEC_ALERT_NMI_EN0_CRYPTO0_DRF_PARITY_ALERT_LSB 0x2
-#define GC_GLOBALSEC_ALERT_NMI_EN0_CRYPTO0_DRF_PARITY_ALERT_MASK 0x4
-#define GC_GLOBALSEC_ALERT_NMI_EN0_CRYPTO0_DRF_PARITY_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_NMI_EN0_CRYPTO0_DRF_PARITY_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_NMI_EN0_CRYPTO0_DRF_PARITY_ALERT_OFFSET 0x400c
-#define GC_GLOBALSEC_ALERT_NMI_EN0_CRYPTO0_IMEM_PARITY_ALERT_LSB 0x3
-#define GC_GLOBALSEC_ALERT_NMI_EN0_CRYPTO0_IMEM_PARITY_ALERT_MASK 0x8
-#define GC_GLOBALSEC_ALERT_NMI_EN0_CRYPTO0_IMEM_PARITY_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_NMI_EN0_CRYPTO0_IMEM_PARITY_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_NMI_EN0_CRYPTO0_IMEM_PARITY_ALERT_OFFSET 0x400c
-#define GC_GLOBALSEC_ALERT_NMI_EN0_CRYPTO0_PGM_FAULT_ALERT_LSB 0x4
-#define GC_GLOBALSEC_ALERT_NMI_EN0_CRYPTO0_PGM_FAULT_ALERT_MASK 0x10
-#define GC_GLOBALSEC_ALERT_NMI_EN0_CRYPTO0_PGM_FAULT_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_NMI_EN0_CRYPTO0_PGM_FAULT_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_NMI_EN0_CRYPTO0_PGM_FAULT_ALERT_OFFSET 0x400c
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_LSB 0x5
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_MASK 0x20
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_OFFSET 0x400c
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_LSB 0x6
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_MASK 0x40
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x400c
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_LSB 0x7
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_MASK 0x80
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_OFFSET 0x400c
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_LSB 0x8
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_MASK 0x100
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x400c
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_LSB 0x9
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_MASK 0x200
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_OFFSET 0x400c
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_LSB 0xa
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_MASK 0x400
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x400c
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_LSB 0xb
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_MASK 0x800
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_OFFSET 0x400c
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_LSB 0xc
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_MASK 0x1000
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x400c
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_LSB 0xd
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_MASK 0x2000
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_OFFSET 0x400c
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_LSB 0xe
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_MASK 0x4000
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x400c
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_LSB 0xf
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_MASK 0x8000
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_OFFSET 0x400c
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_LSB 0x10
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_MASK 0x10000
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_NMI_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x400c
-#define GC_GLOBALSEC_ALERT_NMI_EN0_FUSE0_FUSE_DEFAULTS_ALERT_LSB 0x11
-#define GC_GLOBALSEC_ALERT_NMI_EN0_FUSE0_FUSE_DEFAULTS_ALERT_MASK 0x20000
-#define GC_GLOBALSEC_ALERT_NMI_EN0_FUSE0_FUSE_DEFAULTS_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_NMI_EN0_FUSE0_FUSE_DEFAULTS_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_NMI_EN0_FUSE0_FUSE_DEFAULTS_ALERT_OFFSET 0x400c
-#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_DIFF_FAIL_ALERT_LSB 0x12
-#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_DIFF_FAIL_ALERT_MASK 0x40000
-#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_DIFF_FAIL_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_DIFF_FAIL_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_DIFF_FAIL_ALERT_OFFSET 0x400c
-#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW0_ALERT_LSB 0x13
-#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW0_ALERT_MASK 0x80000
-#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW0_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW0_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW0_ALERT_OFFSET 0x400c
-#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW1_ALERT_LSB 0x14
-#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW1_ALERT_MASK 0x100000
-#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW1_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW1_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW1_ALERT_OFFSET 0x400c
-#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW2_ALERT_LSB 0x15
-#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW2_ALERT_MASK 0x200000
-#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW2_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW2_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW2_ALERT_OFFSET 0x400c
-#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW3_ALERT_LSB 0x16
-#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW3_ALERT_MASK 0x400000
-#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW3_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW3_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_FW3_ALERT_OFFSET 0x400c
-#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_LSB 0x17
-#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_MASK 0x800000
-#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_OFFSET 0x400c
-#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_LSB 0x18
-#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_MASK 0x1000000
-#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_OFFSET 0x400c
-#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_LSB 0x19
-#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_MASK 0x2000000
-#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_NMI_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_OFFSET 0x400c
-#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_LSB 0x1a
-#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_MASK 0x4000000
-#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_OFFSET 0x400c
-#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_AES_HKEY_ALERT_LSB 0x1b
-#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_AES_HKEY_ALERT_MASK 0x8000000
-#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_AES_HKEY_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_AES_HKEY_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_AES_HKEY_ALERT_OFFSET 0x400c
-#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_CERT_LOOKUP_ALERT_LSB 0x1c
-#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_CERT_LOOKUP_ALERT_MASK 0x10000000
-#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_CERT_LOOKUP_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_CERT_LOOKUP_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_CERT_LOOKUP_ALERT_OFFSET 0x400c
-#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_FLASH_ENTRY_ALERT_LSB 0x1d
-#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_FLASH_ENTRY_ALERT_MASK 0x20000000
-#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_FLASH_ENTRY_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_FLASH_ENTRY_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_FLASH_ENTRY_ALERT_OFFSET 0x400c
-#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_PW_ALERT_LSB 0x1e
-#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_PW_ALERT_MASK 0x40000000
-#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_PW_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_PW_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_PW_ALERT_OFFSET 0x400c
-#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_LSB 0x1f
-#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_MASK 0x80000000
-#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_NMI_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_OFFSET 0x400c
-#define GC_GLOBALSEC_ALERT_NMI_EN1_KEYMGR0_SHA_FAULT_ALERT_LSB 0x0
-#define GC_GLOBALSEC_ALERT_NMI_EN1_KEYMGR0_SHA_FAULT_ALERT_MASK 0x1
-#define GC_GLOBALSEC_ALERT_NMI_EN1_KEYMGR0_SHA_FAULT_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_NMI_EN1_KEYMGR0_SHA_FAULT_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_NMI_EN1_KEYMGR0_SHA_FAULT_ALERT_OFFSET 0x4010
-#define GC_GLOBALSEC_ALERT_NMI_EN1_KEYMGR0_SHA_HKEY_ALERT_LSB 0x1
-#define GC_GLOBALSEC_ALERT_NMI_EN1_KEYMGR0_SHA_HKEY_ALERT_MASK 0x2
-#define GC_GLOBALSEC_ALERT_NMI_EN1_KEYMGR0_SHA_HKEY_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_NMI_EN1_KEYMGR0_SHA_HKEY_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_NMI_EN1_KEYMGR0_SHA_HKEY_ALERT_OFFSET 0x4010
-#define GC_GLOBALSEC_ALERT_NMI_EN1_PMU_BATTERY_MON_ALERT_LSB 0x2
-#define GC_GLOBALSEC_ALERT_NMI_EN1_PMU_BATTERY_MON_ALERT_MASK 0x4
-#define GC_GLOBALSEC_ALERT_NMI_EN1_PMU_BATTERY_MON_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_NMI_EN1_PMU_BATTERY_MON_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_NMI_EN1_PMU_BATTERY_MON_ALERT_OFFSET 0x4010
-#define GC_GLOBALSEC_ALERT_NMI_EN1_PMU_PMU_WDOG_ALERT_LSB 0x3
-#define GC_GLOBALSEC_ALERT_NMI_EN1_PMU_PMU_WDOG_ALERT_MASK 0x8
-#define GC_GLOBALSEC_ALERT_NMI_EN1_PMU_PMU_WDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_NMI_EN1_PMU_PMU_WDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_NMI_EN1_PMU_PMU_WDOG_ALERT_OFFSET 0x4010
-#define GC_GLOBALSEC_ALERT_NMI_EN1_RTC0_RTC_DEAD_ALERT_LSB 0x4
-#define GC_GLOBALSEC_ALERT_NMI_EN1_RTC0_RTC_DEAD_ALERT_MASK 0x10
-#define GC_GLOBALSEC_ALERT_NMI_EN1_RTC0_RTC_DEAD_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_NMI_EN1_RTC0_RTC_DEAD_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_NMI_EN1_RTC0_RTC_DEAD_ALERT_OFFSET 0x4010
-#define GC_GLOBALSEC_ALERT_NMI_EN1_TEMP0_MAX_TEMP_ALERT_LSB 0x5
-#define GC_GLOBALSEC_ALERT_NMI_EN1_TEMP0_MAX_TEMP_ALERT_MASK 0x20
-#define GC_GLOBALSEC_ALERT_NMI_EN1_TEMP0_MAX_TEMP_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_NMI_EN1_TEMP0_MAX_TEMP_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_NMI_EN1_TEMP0_MAX_TEMP_ALERT_OFFSET 0x4010
-#define GC_GLOBALSEC_ALERT_NMI_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_LSB 0x6
-#define GC_GLOBALSEC_ALERT_NMI_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_MASK 0x40
-#define GC_GLOBALSEC_ALERT_NMI_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_NMI_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_NMI_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_OFFSET 0x4010
-#define GC_GLOBALSEC_ALERT_NMI_EN1_TEMP0_MIN_TEMP_ALERT_LSB 0x7
-#define GC_GLOBALSEC_ALERT_NMI_EN1_TEMP0_MIN_TEMP_ALERT_MASK 0x80
-#define GC_GLOBALSEC_ALERT_NMI_EN1_TEMP0_MIN_TEMP_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_NMI_EN1_TEMP0_MIN_TEMP_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_NMI_EN1_TEMP0_MIN_TEMP_ALERT_OFFSET 0x4010
-#define GC_GLOBALSEC_ALERT_NMI_EN1_TRNG0_OUT_OF_SPEC_ALERT_LSB 0x8
-#define GC_GLOBALSEC_ALERT_NMI_EN1_TRNG0_OUT_OF_SPEC_ALERT_MASK 0x100
-#define GC_GLOBALSEC_ALERT_NMI_EN1_TRNG0_OUT_OF_SPEC_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_NMI_EN1_TRNG0_OUT_OF_SPEC_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_NMI_EN1_TRNG0_OUT_OF_SPEC_ALERT_OFFSET 0x4010
-#define GC_GLOBALSEC_ALERT_NMI_EN1_TRNG0_TIMEOUT_ALERT_LSB 0x9
-#define GC_GLOBALSEC_ALERT_NMI_EN1_TRNG0_TIMEOUT_ALERT_MASK 0x200
-#define GC_GLOBALSEC_ALERT_NMI_EN1_TRNG0_TIMEOUT_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_NMI_EN1_TRNG0_TIMEOUT_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_NMI_EN1_TRNG0_TIMEOUT_ALERT_OFFSET 0x4010
-#define GC_GLOBALSEC_ALERT_NMI_EN1_VOLT0_VOLT_ERR_ALERT_LSB 0xa
-#define GC_GLOBALSEC_ALERT_NMI_EN1_VOLT0_VOLT_ERR_ALERT_MASK 0x400
-#define GC_GLOBALSEC_ALERT_NMI_EN1_VOLT0_VOLT_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_NMI_EN1_VOLT0_VOLT_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_NMI_EN1_VOLT0_VOLT_ERR_ALERT_OFFSET 0x4010
-#define GC_GLOBALSEC_ALERT_NMI_EN1_XO0_JITTERY_TRIM_DIS_ALERT_LSB 0xb
-#define GC_GLOBALSEC_ALERT_NMI_EN1_XO0_JITTERY_TRIM_DIS_ALERT_MASK 0x800
-#define GC_GLOBALSEC_ALERT_NMI_EN1_XO0_JITTERY_TRIM_DIS_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_NMI_EN1_XO0_JITTERY_TRIM_DIS_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_NMI_EN1_XO0_JITTERY_TRIM_DIS_ALERT_OFFSET 0x4010
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CAMO0_BREACH_ALERT_LSB 0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CAMO0_BREACH_ALERT_MASK 0x1
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CAMO0_BREACH_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CAMO0_BREACH_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CAMO0_BREACH_ALERT_OFFSET 0x4014
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CRYPTO0_DMEM_PARITY_ALERT_LSB 0x1
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CRYPTO0_DMEM_PARITY_ALERT_MASK 0x2
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CRYPTO0_DMEM_PARITY_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CRYPTO0_DMEM_PARITY_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CRYPTO0_DMEM_PARITY_ALERT_OFFSET 0x4014
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CRYPTO0_DRF_PARITY_ALERT_LSB 0x2
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CRYPTO0_DRF_PARITY_ALERT_MASK 0x4
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CRYPTO0_DRF_PARITY_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CRYPTO0_DRF_PARITY_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CRYPTO0_DRF_PARITY_ALERT_OFFSET 0x4014
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CRYPTO0_IMEM_PARITY_ALERT_LSB 0x3
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CRYPTO0_IMEM_PARITY_ALERT_MASK 0x8
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CRYPTO0_IMEM_PARITY_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CRYPTO0_IMEM_PARITY_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CRYPTO0_IMEM_PARITY_ALERT_OFFSET 0x4014
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CRYPTO0_PGM_FAULT_ALERT_LSB 0x4
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CRYPTO0_PGM_FAULT_ALERT_MASK 0x10
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CRYPTO0_PGM_FAULT_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CRYPTO0_PGM_FAULT_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_CRYPTO0_PGM_FAULT_ALERT_OFFSET 0x4014
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_LSB 0x5
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_MASK 0x20
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_OFFSET 0x4014
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_LSB 0x6
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_MASK 0x40
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4014
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_LSB 0x7
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_MASK 0x80
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_OFFSET 0x4014
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_LSB 0x8
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_MASK 0x100
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4014
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_LSB 0x9
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_MASK 0x200
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_OFFSET 0x4014
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_LSB 0xa
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_MASK 0x400
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4014
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_LSB 0xb
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_MASK 0x800
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_OFFSET 0x4014
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_LSB 0xc
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_MASK 0x1000
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4014
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_LSB 0xd
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_MASK 0x2000
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_OFFSET 0x4014
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_LSB 0xe
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_MASK 0x4000
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4014
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_LSB 0xf
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_MASK 0x8000
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_OFFSET 0x4014
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_LSB 0x10
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_MASK 0x10000
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4014
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_FUSE0_FUSE_DEFAULTS_ALERT_LSB 0x11
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_FUSE0_FUSE_DEFAULTS_ALERT_MASK 0x20000
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_FUSE0_FUSE_DEFAULTS_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_FUSE0_FUSE_DEFAULTS_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_FUSE0_FUSE_DEFAULTS_ALERT_OFFSET 0x4014
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_DIFF_FAIL_ALERT_LSB 0x12
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_DIFF_FAIL_ALERT_MASK 0x40000
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_DIFF_FAIL_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_DIFF_FAIL_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_DIFF_FAIL_ALERT_OFFSET 0x4014
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW0_ALERT_LSB 0x13
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW0_ALERT_MASK 0x80000
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW0_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW0_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW0_ALERT_OFFSET 0x4014
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW1_ALERT_LSB 0x14
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW1_ALERT_MASK 0x100000
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW1_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW1_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW1_ALERT_OFFSET 0x4014
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW2_ALERT_LSB 0x15
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW2_ALERT_MASK 0x200000
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW2_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW2_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW2_ALERT_OFFSET 0x4014
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW3_ALERT_LSB 0x16
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW3_ALERT_MASK 0x400000
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW3_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW3_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_FW3_ALERT_OFFSET 0x4014
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_LSB 0x17
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_MASK 0x800000
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_OFFSET 0x4014
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_LSB 0x18
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_MASK 0x1000000
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_OFFSET 0x4014
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_LSB 0x19
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_MASK 0x2000000
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_OFFSET 0x4014
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_LSB 0x1a
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_MASK 0x4000000
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_OFFSET 0x4014
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_AES_HKEY_ALERT_LSB 0x1b
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_AES_HKEY_ALERT_MASK 0x8000000
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_AES_HKEY_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_AES_HKEY_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_AES_HKEY_ALERT_OFFSET 0x4014
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_CERT_LOOKUP_ALERT_LSB 0x1c
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_CERT_LOOKUP_ALERT_MASK 0x10000000
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_CERT_LOOKUP_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_CERT_LOOKUP_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_CERT_LOOKUP_ALERT_OFFSET 0x4014
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_FLASH_ENTRY_ALERT_LSB 0x1d
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_FLASH_ENTRY_ALERT_MASK 0x20000000
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_FLASH_ENTRY_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_FLASH_ENTRY_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_FLASH_ENTRY_ALERT_OFFSET 0x4014
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_PW_ALERT_LSB 0x1e
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_PW_ALERT_MASK 0x40000000
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_PW_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_PW_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_PW_ALERT_OFFSET 0x4014
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_LSB 0x1f
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_MASK 0x80000000
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_OFFSET 0x4014
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_KEYMGR0_SHA_FAULT_ALERT_LSB 0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_KEYMGR0_SHA_FAULT_ALERT_MASK 0x1
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_KEYMGR0_SHA_FAULT_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_KEYMGR0_SHA_FAULT_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_KEYMGR0_SHA_FAULT_ALERT_OFFSET 0x4018
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_KEYMGR0_SHA_HKEY_ALERT_LSB 0x1
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_KEYMGR0_SHA_HKEY_ALERT_MASK 0x2
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_KEYMGR0_SHA_HKEY_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_KEYMGR0_SHA_HKEY_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_KEYMGR0_SHA_HKEY_ALERT_OFFSET 0x4018
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_PMU_BATTERY_MON_ALERT_LSB 0x2
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_PMU_BATTERY_MON_ALERT_MASK 0x4
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_PMU_BATTERY_MON_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_PMU_BATTERY_MON_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_PMU_BATTERY_MON_ALERT_OFFSET 0x4018
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_PMU_PMU_WDOG_ALERT_LSB 0x3
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_PMU_PMU_WDOG_ALERT_MASK 0x8
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_PMU_PMU_WDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_PMU_PMU_WDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_PMU_PMU_WDOG_ALERT_OFFSET 0x4018
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_RTC0_RTC_DEAD_ALERT_LSB 0x4
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_RTC0_RTC_DEAD_ALERT_MASK 0x10
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_RTC0_RTC_DEAD_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_RTC0_RTC_DEAD_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_RTC0_RTC_DEAD_ALERT_OFFSET 0x4018
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_TEMP0_MAX_TEMP_ALERT_LSB 0x5
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_TEMP0_MAX_TEMP_ALERT_MASK 0x20
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_TEMP0_MAX_TEMP_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_TEMP0_MAX_TEMP_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_TEMP0_MAX_TEMP_ALERT_OFFSET 0x4018
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_LSB 0x6
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_MASK 0x40
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_OFFSET 0x4018
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_TEMP0_MIN_TEMP_ALERT_LSB 0x7
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_TEMP0_MIN_TEMP_ALERT_MASK 0x80
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_TEMP0_MIN_TEMP_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_TEMP0_MIN_TEMP_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_TEMP0_MIN_TEMP_ALERT_OFFSET 0x4018
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_TRNG0_OUT_OF_SPEC_ALERT_LSB 0x8
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_TRNG0_OUT_OF_SPEC_ALERT_MASK 0x100
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_TRNG0_OUT_OF_SPEC_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_TRNG0_OUT_OF_SPEC_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_TRNG0_OUT_OF_SPEC_ALERT_OFFSET 0x4018
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_TRNG0_TIMEOUT_ALERT_LSB 0x9
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_TRNG0_TIMEOUT_ALERT_MASK 0x200
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_TRNG0_TIMEOUT_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_TRNG0_TIMEOUT_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_TRNG0_TIMEOUT_ALERT_OFFSET 0x4018
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_VOLT0_VOLT_ERR_ALERT_LSB 0xa
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_VOLT0_VOLT_ERR_ALERT_MASK 0x400
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_VOLT0_VOLT_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_VOLT0_VOLT_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_VOLT0_VOLT_ERR_ALERT_OFFSET 0x4018
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_XO0_JITTERY_TRIM_DIS_ALERT_LSB 0xb
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_XO0_JITTERY_TRIM_DIS_ALERT_MASK 0x800
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_XO0_JITTERY_TRIM_DIS_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_XO0_JITTERY_TRIM_DIS_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPA_EN1_XO0_JITTERY_TRIM_DIS_ALERT_OFFSET 0x4018
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CAMO0_BREACH_ALERT_LSB 0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CAMO0_BREACH_ALERT_MASK 0x1
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CAMO0_BREACH_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CAMO0_BREACH_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CAMO0_BREACH_ALERT_OFFSET 0x401c
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CRYPTO0_DMEM_PARITY_ALERT_LSB 0x1
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CRYPTO0_DMEM_PARITY_ALERT_MASK 0x2
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CRYPTO0_DMEM_PARITY_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CRYPTO0_DMEM_PARITY_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CRYPTO0_DMEM_PARITY_ALERT_OFFSET 0x401c
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CRYPTO0_DRF_PARITY_ALERT_LSB 0x2
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CRYPTO0_DRF_PARITY_ALERT_MASK 0x4
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CRYPTO0_DRF_PARITY_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CRYPTO0_DRF_PARITY_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CRYPTO0_DRF_PARITY_ALERT_OFFSET 0x401c
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CRYPTO0_IMEM_PARITY_ALERT_LSB 0x3
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CRYPTO0_IMEM_PARITY_ALERT_MASK 0x8
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CRYPTO0_IMEM_PARITY_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CRYPTO0_IMEM_PARITY_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CRYPTO0_IMEM_PARITY_ALERT_OFFSET 0x401c
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CRYPTO0_PGM_FAULT_ALERT_LSB 0x4
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CRYPTO0_PGM_FAULT_ALERT_MASK 0x10
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CRYPTO0_PGM_FAULT_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CRYPTO0_PGM_FAULT_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_CRYPTO0_PGM_FAULT_ALERT_OFFSET 0x401c
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_LSB 0x5
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_MASK 0x20
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_OFFSET 0x401c
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_LSB 0x6
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_MASK 0x40
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x401c
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_LSB 0x7
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_MASK 0x80
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_OFFSET 0x401c
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_LSB 0x8
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_MASK 0x100
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x401c
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_LSB 0x9
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_MASK 0x200
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_OFFSET 0x401c
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_LSB 0xa
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_MASK 0x400
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x401c
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_LSB 0xb
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_MASK 0x800
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_OFFSET 0x401c
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_LSB 0xc
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_MASK 0x1000
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x401c
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_LSB 0xd
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_MASK 0x2000
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_OFFSET 0x401c
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_LSB 0xe
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_MASK 0x4000
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x401c
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_LSB 0xf
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_MASK 0x8000
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_OFFSET 0x401c
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_LSB 0x10
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_MASK 0x10000
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x401c
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_FUSE0_FUSE_DEFAULTS_ALERT_LSB 0x11
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_FUSE0_FUSE_DEFAULTS_ALERT_MASK 0x20000
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_FUSE0_FUSE_DEFAULTS_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_FUSE0_FUSE_DEFAULTS_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_FUSE0_FUSE_DEFAULTS_ALERT_OFFSET 0x401c
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_DIFF_FAIL_ALERT_LSB 0x12
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_DIFF_FAIL_ALERT_MASK 0x40000
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_DIFF_FAIL_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_DIFF_FAIL_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_DIFF_FAIL_ALERT_OFFSET 0x401c
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW0_ALERT_LSB 0x13
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW0_ALERT_MASK 0x80000
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW0_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW0_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW0_ALERT_OFFSET 0x401c
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW1_ALERT_LSB 0x14
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW1_ALERT_MASK 0x100000
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW1_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW1_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW1_ALERT_OFFSET 0x401c
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW2_ALERT_LSB 0x15
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW2_ALERT_MASK 0x200000
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW2_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW2_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW2_ALERT_OFFSET 0x401c
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW3_ALERT_LSB 0x16
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW3_ALERT_MASK 0x400000
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW3_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW3_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_FW3_ALERT_OFFSET 0x401c
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_LSB 0x17
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_MASK 0x800000
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_OFFSET 0x401c
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_LSB 0x18
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_MASK 0x1000000
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_OFFSET 0x401c
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_LSB 0x19
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_MASK 0x2000000
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_OFFSET 0x401c
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_LSB 0x1a
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_MASK 0x4000000
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_OFFSET 0x401c
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_AES_HKEY_ALERT_LSB 0x1b
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_AES_HKEY_ALERT_MASK 0x8000000
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_AES_HKEY_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_AES_HKEY_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_AES_HKEY_ALERT_OFFSET 0x401c
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_CERT_LOOKUP_ALERT_LSB 0x1c
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_CERT_LOOKUP_ALERT_MASK 0x10000000
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_CERT_LOOKUP_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_CERT_LOOKUP_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_CERT_LOOKUP_ALERT_OFFSET 0x401c
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_FLASH_ENTRY_ALERT_LSB 0x1d
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_FLASH_ENTRY_ALERT_MASK 0x20000000
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_FLASH_ENTRY_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_FLASH_ENTRY_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_FLASH_ENTRY_ALERT_OFFSET 0x401c
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_PW_ALERT_LSB 0x1e
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_PW_ALERT_MASK 0x40000000
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_PW_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_PW_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_PW_ALERT_OFFSET 0x401c
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_LSB 0x1f
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_MASK 0x80000000
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_OFFSET 0x401c
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_KEYMGR0_SHA_FAULT_ALERT_LSB 0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_KEYMGR0_SHA_FAULT_ALERT_MASK 0x1
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_KEYMGR0_SHA_FAULT_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_KEYMGR0_SHA_FAULT_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_KEYMGR0_SHA_FAULT_ALERT_OFFSET 0x4020
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_KEYMGR0_SHA_HKEY_ALERT_LSB 0x1
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_KEYMGR0_SHA_HKEY_ALERT_MASK 0x2
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_KEYMGR0_SHA_HKEY_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_KEYMGR0_SHA_HKEY_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_KEYMGR0_SHA_HKEY_ALERT_OFFSET 0x4020
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_PMU_BATTERY_MON_ALERT_LSB 0x2
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_PMU_BATTERY_MON_ALERT_MASK 0x4
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_PMU_BATTERY_MON_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_PMU_BATTERY_MON_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_PMU_BATTERY_MON_ALERT_OFFSET 0x4020
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_PMU_PMU_WDOG_ALERT_LSB 0x3
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_PMU_PMU_WDOG_ALERT_MASK 0x8
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_PMU_PMU_WDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_PMU_PMU_WDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_PMU_PMU_WDOG_ALERT_OFFSET 0x4020
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_RTC0_RTC_DEAD_ALERT_LSB 0x4
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_RTC0_RTC_DEAD_ALERT_MASK 0x10
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_RTC0_RTC_DEAD_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_RTC0_RTC_DEAD_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_RTC0_RTC_DEAD_ALERT_OFFSET 0x4020
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_TEMP0_MAX_TEMP_ALERT_LSB 0x5
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_TEMP0_MAX_TEMP_ALERT_MASK 0x20
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_TEMP0_MAX_TEMP_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_TEMP0_MAX_TEMP_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_TEMP0_MAX_TEMP_ALERT_OFFSET 0x4020
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_LSB 0x6
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_MASK 0x40
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_OFFSET 0x4020
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_TEMP0_MIN_TEMP_ALERT_LSB 0x7
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_TEMP0_MIN_TEMP_ALERT_MASK 0x80
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_TEMP0_MIN_TEMP_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_TEMP0_MIN_TEMP_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_TEMP0_MIN_TEMP_ALERT_OFFSET 0x4020
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_TRNG0_OUT_OF_SPEC_ALERT_LSB 0x8
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_TRNG0_OUT_OF_SPEC_ALERT_MASK 0x100
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_TRNG0_OUT_OF_SPEC_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_TRNG0_OUT_OF_SPEC_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_TRNG0_OUT_OF_SPEC_ALERT_OFFSET 0x4020
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_TRNG0_TIMEOUT_ALERT_LSB 0x9
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_TRNG0_TIMEOUT_ALERT_MASK 0x200
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_TRNG0_TIMEOUT_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_TRNG0_TIMEOUT_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_TRNG0_TIMEOUT_ALERT_OFFSET 0x4020
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_VOLT0_VOLT_ERR_ALERT_LSB 0xa
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_VOLT0_VOLT_ERR_ALERT_MASK 0x400
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_VOLT0_VOLT_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_VOLT0_VOLT_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_VOLT0_VOLT_ERR_ALERT_OFFSET 0x4020
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_XO0_JITTERY_TRIM_DIS_ALERT_LSB 0xb
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_XO0_JITTERY_TRIM_DIS_ALERT_MASK 0x800
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_XO0_JITTERY_TRIM_DIS_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_XO0_JITTERY_TRIM_DIS_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPB_EN1_XO0_JITTERY_TRIM_DIS_ALERT_OFFSET 0x4020
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CAMO0_BREACH_ALERT_LSB 0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CAMO0_BREACH_ALERT_MASK 0x1
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CAMO0_BREACH_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CAMO0_BREACH_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CAMO0_BREACH_ALERT_OFFSET 0x4024
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CRYPTO0_DMEM_PARITY_ALERT_LSB 0x1
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CRYPTO0_DMEM_PARITY_ALERT_MASK 0x2
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CRYPTO0_DMEM_PARITY_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CRYPTO0_DMEM_PARITY_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CRYPTO0_DMEM_PARITY_ALERT_OFFSET 0x4024
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CRYPTO0_DRF_PARITY_ALERT_LSB 0x2
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CRYPTO0_DRF_PARITY_ALERT_MASK 0x4
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CRYPTO0_DRF_PARITY_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CRYPTO0_DRF_PARITY_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CRYPTO0_DRF_PARITY_ALERT_OFFSET 0x4024
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CRYPTO0_IMEM_PARITY_ALERT_LSB 0x3
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CRYPTO0_IMEM_PARITY_ALERT_MASK 0x8
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CRYPTO0_IMEM_PARITY_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CRYPTO0_IMEM_PARITY_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CRYPTO0_IMEM_PARITY_ALERT_OFFSET 0x4024
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CRYPTO0_PGM_FAULT_ALERT_LSB 0x4
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CRYPTO0_PGM_FAULT_ALERT_MASK 0x10
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CRYPTO0_PGM_FAULT_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CRYPTO0_PGM_FAULT_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_CRYPTO0_PGM_FAULT_ALERT_OFFSET 0x4024
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_LSB 0x5
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_MASK 0x20
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_OFFSET 0x4024
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_LSB 0x6
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_MASK 0x40
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4024
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_LSB 0x7
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_MASK 0x80
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_OFFSET 0x4024
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_LSB 0x8
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_MASK 0x100
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4024
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_LSB 0x9
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_MASK 0x200
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_OFFSET 0x4024
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_LSB 0xa
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_MASK 0x400
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4024
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_LSB 0xb
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_MASK 0x800
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_OFFSET 0x4024
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_LSB 0xc
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_MASK 0x1000
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4024
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_LSB 0xd
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_MASK 0x2000
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_OFFSET 0x4024
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_LSB 0xe
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_MASK 0x4000
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4024
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_LSB 0xf
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_MASK 0x8000
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_OFFSET 0x4024
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_LSB 0x10
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_MASK 0x10000
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4024
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_FUSE0_FUSE_DEFAULTS_ALERT_LSB 0x11
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_FUSE0_FUSE_DEFAULTS_ALERT_MASK 0x20000
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_FUSE0_FUSE_DEFAULTS_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_FUSE0_FUSE_DEFAULTS_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_FUSE0_FUSE_DEFAULTS_ALERT_OFFSET 0x4024
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_DIFF_FAIL_ALERT_LSB 0x12
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_DIFF_FAIL_ALERT_MASK 0x40000
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_DIFF_FAIL_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_DIFF_FAIL_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_DIFF_FAIL_ALERT_OFFSET 0x4024
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW0_ALERT_LSB 0x13
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW0_ALERT_MASK 0x80000
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW0_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW0_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW0_ALERT_OFFSET 0x4024
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW1_ALERT_LSB 0x14
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW1_ALERT_MASK 0x100000
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW1_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW1_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW1_ALERT_OFFSET 0x4024
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW2_ALERT_LSB 0x15
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW2_ALERT_MASK 0x200000
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW2_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW2_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW2_ALERT_OFFSET 0x4024
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW3_ALERT_LSB 0x16
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW3_ALERT_MASK 0x400000
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW3_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW3_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_FW3_ALERT_OFFSET 0x4024
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_LSB 0x17
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_MASK 0x800000
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_OFFSET 0x4024
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_LSB 0x18
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_MASK 0x1000000
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_OFFSET 0x4024
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_LSB 0x19
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_MASK 0x2000000
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_OFFSET 0x4024
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_LSB 0x1a
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_MASK 0x4000000
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_OFFSET 0x4024
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_AES_HKEY_ALERT_LSB 0x1b
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_AES_HKEY_ALERT_MASK 0x8000000
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_AES_HKEY_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_AES_HKEY_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_AES_HKEY_ALERT_OFFSET 0x4024
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_CERT_LOOKUP_ALERT_LSB 0x1c
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_CERT_LOOKUP_ALERT_MASK 0x10000000
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_CERT_LOOKUP_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_CERT_LOOKUP_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_CERT_LOOKUP_ALERT_OFFSET 0x4024
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_FLASH_ENTRY_ALERT_LSB 0x1d
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_FLASH_ENTRY_ALERT_MASK 0x20000000
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_FLASH_ENTRY_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_FLASH_ENTRY_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_FLASH_ENTRY_ALERT_OFFSET 0x4024
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_PW_ALERT_LSB 0x1e
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_PW_ALERT_MASK 0x40000000
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_PW_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_PW_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_PW_ALERT_OFFSET 0x4024
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_LSB 0x1f
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_MASK 0x80000000
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_OFFSET 0x4024
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_KEYMGR0_SHA_FAULT_ALERT_LSB 0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_KEYMGR0_SHA_FAULT_ALERT_MASK 0x1
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_KEYMGR0_SHA_FAULT_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_KEYMGR0_SHA_FAULT_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_KEYMGR0_SHA_FAULT_ALERT_OFFSET 0x4028
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_KEYMGR0_SHA_HKEY_ALERT_LSB 0x1
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_KEYMGR0_SHA_HKEY_ALERT_MASK 0x2
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_KEYMGR0_SHA_HKEY_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_KEYMGR0_SHA_HKEY_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_KEYMGR0_SHA_HKEY_ALERT_OFFSET 0x4028
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_PMU_BATTERY_MON_ALERT_LSB 0x2
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_PMU_BATTERY_MON_ALERT_MASK 0x4
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_PMU_BATTERY_MON_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_PMU_BATTERY_MON_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_PMU_BATTERY_MON_ALERT_OFFSET 0x4028
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_PMU_PMU_WDOG_ALERT_LSB 0x3
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_PMU_PMU_WDOG_ALERT_MASK 0x8
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_PMU_PMU_WDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_PMU_PMU_WDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_PMU_PMU_WDOG_ALERT_OFFSET 0x4028
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_RTC0_RTC_DEAD_ALERT_LSB 0x4
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_RTC0_RTC_DEAD_ALERT_MASK 0x10
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_RTC0_RTC_DEAD_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_RTC0_RTC_DEAD_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_RTC0_RTC_DEAD_ALERT_OFFSET 0x4028
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_TEMP0_MAX_TEMP_ALERT_LSB 0x5
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_TEMP0_MAX_TEMP_ALERT_MASK 0x20
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_TEMP0_MAX_TEMP_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_TEMP0_MAX_TEMP_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_TEMP0_MAX_TEMP_ALERT_OFFSET 0x4028
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_LSB 0x6
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_MASK 0x40
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_OFFSET 0x4028
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_TEMP0_MIN_TEMP_ALERT_LSB 0x7
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_TEMP0_MIN_TEMP_ALERT_MASK 0x80
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_TEMP0_MIN_TEMP_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_TEMP0_MIN_TEMP_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_TEMP0_MIN_TEMP_ALERT_OFFSET 0x4028
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_TRNG0_OUT_OF_SPEC_ALERT_LSB 0x8
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_TRNG0_OUT_OF_SPEC_ALERT_MASK 0x100
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_TRNG0_OUT_OF_SPEC_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_TRNG0_OUT_OF_SPEC_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_TRNG0_OUT_OF_SPEC_ALERT_OFFSET 0x4028
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_TRNG0_TIMEOUT_ALERT_LSB 0x9
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_TRNG0_TIMEOUT_ALERT_MASK 0x200
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_TRNG0_TIMEOUT_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_TRNG0_TIMEOUT_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_TRNG0_TIMEOUT_ALERT_OFFSET 0x4028
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_VOLT0_VOLT_ERR_ALERT_LSB 0xa
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_VOLT0_VOLT_ERR_ALERT_MASK 0x400
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_VOLT0_VOLT_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_VOLT0_VOLT_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_VOLT0_VOLT_ERR_ALERT_OFFSET 0x4028
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_XO0_JITTERY_TRIM_DIS_ALERT_LSB 0xb
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_XO0_JITTERY_TRIM_DIS_ALERT_MASK 0x800
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_XO0_JITTERY_TRIM_DIS_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_XO0_JITTERY_TRIM_DIS_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_GROUPC_EN1_XO0_JITTERY_TRIM_DIS_ALERT_OFFSET 0x4028
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CAMO0_BREACH_ALERT_LSB 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CAMO0_BREACH_ALERT_MASK 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CAMO0_BREACH_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CAMO0_BREACH_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CAMO0_BREACH_ALERT_OFFSET 0x402c
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CRYPTO0_DMEM_PARITY_ALERT_LSB 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CRYPTO0_DMEM_PARITY_ALERT_MASK 0x2
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CRYPTO0_DMEM_PARITY_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CRYPTO0_DMEM_PARITY_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CRYPTO0_DMEM_PARITY_ALERT_OFFSET 0x402c
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CRYPTO0_DRF_PARITY_ALERT_LSB 0x2
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CRYPTO0_DRF_PARITY_ALERT_MASK 0x4
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CRYPTO0_DRF_PARITY_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CRYPTO0_DRF_PARITY_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CRYPTO0_DRF_PARITY_ALERT_OFFSET 0x402c
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CRYPTO0_IMEM_PARITY_ALERT_LSB 0x3
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CRYPTO0_IMEM_PARITY_ALERT_MASK 0x8
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CRYPTO0_IMEM_PARITY_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CRYPTO0_IMEM_PARITY_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CRYPTO0_IMEM_PARITY_ALERT_OFFSET 0x402c
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CRYPTO0_PGM_FAULT_ALERT_LSB 0x4
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CRYPTO0_PGM_FAULT_ALERT_MASK 0x10
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CRYPTO0_PGM_FAULT_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CRYPTO0_PGM_FAULT_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_CRYPTO0_PGM_FAULT_ALERT_OFFSET 0x402c
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_LSB 0x5
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_MASK 0x20
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_OFFSET 0x402c
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_LSB 0x6
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_MASK 0x40
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x402c
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_LSB 0x7
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_MASK 0x80
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_OFFSET 0x402c
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_LSB 0x8
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_MASK 0x100
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x402c
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_LSB 0x9
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_MASK 0x200
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_OFFSET 0x402c
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_LSB 0xa
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_MASK 0x400
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x402c
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_LSB 0xb
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_MASK 0x800
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_OFFSET 0x402c
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_LSB 0xc
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_MASK 0x1000
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x402c
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_LSB 0xd
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_MASK 0x2000
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_OFFSET 0x402c
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_LSB 0xe
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_MASK 0x4000
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x402c
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_LSB 0xf
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_MASK 0x8000
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_OFFSET 0x402c
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_LSB 0x10
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_MASK 0x10000
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x402c
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_FUSE0_FUSE_DEFAULTS_ALERT_LSB 0x11
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_FUSE0_FUSE_DEFAULTS_ALERT_MASK 0x20000
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_FUSE0_FUSE_DEFAULTS_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_FUSE0_FUSE_DEFAULTS_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_FUSE0_FUSE_DEFAULTS_ALERT_OFFSET 0x402c
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_DIFF_FAIL_ALERT_LSB 0x12
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_DIFF_FAIL_ALERT_MASK 0x40000
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_DIFF_FAIL_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_DIFF_FAIL_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_DIFF_FAIL_ALERT_OFFSET 0x402c
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW0_ALERT_LSB 0x13
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW0_ALERT_MASK 0x80000
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW0_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW0_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW0_ALERT_OFFSET 0x402c
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW1_ALERT_LSB 0x14
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW1_ALERT_MASK 0x100000
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW1_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW1_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW1_ALERT_OFFSET 0x402c
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW2_ALERT_LSB 0x15
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW2_ALERT_MASK 0x200000
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW2_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW2_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW2_ALERT_OFFSET 0x402c
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW3_ALERT_LSB 0x16
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW3_ALERT_MASK 0x400000
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW3_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW3_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_FW3_ALERT_OFFSET 0x402c
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_LSB 0x17
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_MASK 0x800000
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_OFFSET 0x402c
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_LSB 0x18
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_MASK 0x1000000
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_OFFSET 0x402c
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_LSB 0x19
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_MASK 0x2000000
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_OFFSET 0x402c
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_LSB 0x1a
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_MASK 0x4000000
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_OFFSET 0x402c
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_AES_HKEY_ALERT_LSB 0x1b
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_AES_HKEY_ALERT_MASK 0x8000000
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_AES_HKEY_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_AES_HKEY_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_AES_HKEY_ALERT_OFFSET 0x402c
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_CERT_LOOKUP_ALERT_LSB 0x1c
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_CERT_LOOKUP_ALERT_MASK 0x10000000
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_CERT_LOOKUP_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_CERT_LOOKUP_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_CERT_LOOKUP_ALERT_OFFSET 0x402c
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_FLASH_ENTRY_ALERT_LSB 0x1d
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_FLASH_ENTRY_ALERT_MASK 0x20000000
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_FLASH_ENTRY_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_FLASH_ENTRY_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_FLASH_ENTRY_ALERT_OFFSET 0x402c
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_PW_ALERT_LSB 0x1e
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_PW_ALERT_MASK 0x40000000
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_PW_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_PW_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_PW_ALERT_OFFSET 0x402c
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_LSB 0x1f
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_MASK 0x80000000
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_OFFSET 0x402c
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_KEYMGR0_SHA_FAULT_ALERT_LSB 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_KEYMGR0_SHA_FAULT_ALERT_MASK 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_KEYMGR0_SHA_FAULT_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_KEYMGR0_SHA_FAULT_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_KEYMGR0_SHA_FAULT_ALERT_OFFSET 0x4030
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_KEYMGR0_SHA_HKEY_ALERT_LSB 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_KEYMGR0_SHA_HKEY_ALERT_MASK 0x2
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_KEYMGR0_SHA_HKEY_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_KEYMGR0_SHA_HKEY_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_KEYMGR0_SHA_HKEY_ALERT_OFFSET 0x4030
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_PMU_BATTERY_MON_ALERT_LSB 0x2
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_PMU_BATTERY_MON_ALERT_MASK 0x4
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_PMU_BATTERY_MON_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_PMU_BATTERY_MON_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_PMU_BATTERY_MON_ALERT_OFFSET 0x4030
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_PMU_PMU_WDOG_ALERT_LSB 0x3
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_PMU_PMU_WDOG_ALERT_MASK 0x8
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_PMU_PMU_WDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_PMU_PMU_WDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_PMU_PMU_WDOG_ALERT_OFFSET 0x4030
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_RTC0_RTC_DEAD_ALERT_LSB 0x4
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_RTC0_RTC_DEAD_ALERT_MASK 0x10
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_RTC0_RTC_DEAD_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_RTC0_RTC_DEAD_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_RTC0_RTC_DEAD_ALERT_OFFSET 0x4030
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TEMP0_MAX_TEMP_ALERT_LSB 0x5
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TEMP0_MAX_TEMP_ALERT_MASK 0x20
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TEMP0_MAX_TEMP_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TEMP0_MAX_TEMP_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TEMP0_MAX_TEMP_ALERT_OFFSET 0x4030
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_LSB 0x6
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_MASK 0x40
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_OFFSET 0x4030
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TEMP0_MIN_TEMP_ALERT_LSB 0x7
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TEMP0_MIN_TEMP_ALERT_MASK 0x80
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TEMP0_MIN_TEMP_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TEMP0_MIN_TEMP_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TEMP0_MIN_TEMP_ALERT_OFFSET 0x4030
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TRNG0_OUT_OF_SPEC_ALERT_LSB 0x8
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TRNG0_OUT_OF_SPEC_ALERT_MASK 0x100
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TRNG0_OUT_OF_SPEC_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TRNG0_OUT_OF_SPEC_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TRNG0_OUT_OF_SPEC_ALERT_OFFSET 0x4030
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TRNG0_TIMEOUT_ALERT_LSB 0x9
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TRNG0_TIMEOUT_ALERT_MASK 0x200
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TRNG0_TIMEOUT_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TRNG0_TIMEOUT_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_TRNG0_TIMEOUT_ALERT_OFFSET 0x4030
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_VOLT0_VOLT_ERR_ALERT_LSB 0xa
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_VOLT0_VOLT_ERR_ALERT_MASK 0x400
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_VOLT0_VOLT_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_VOLT0_VOLT_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_VOLT0_VOLT_ERR_ALERT_OFFSET 0x4030
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_XO0_JITTERY_TRIM_DIS_ALERT_LSB 0xb
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_XO0_JITTERY_TRIM_DIS_ALERT_MASK 0x800
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_XO0_JITTERY_TRIM_DIS_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_XO0_JITTERY_TRIM_DIS_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR0_EN1_XO0_JITTERY_TRIM_DIS_ALERT_OFFSET 0x4030
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CAMO0_BREACH_ALERT_LSB 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CAMO0_BREACH_ALERT_MASK 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CAMO0_BREACH_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CAMO0_BREACH_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CAMO0_BREACH_ALERT_OFFSET 0x4034
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CRYPTO0_DMEM_PARITY_ALERT_LSB 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CRYPTO0_DMEM_PARITY_ALERT_MASK 0x2
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CRYPTO0_DMEM_PARITY_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CRYPTO0_DMEM_PARITY_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CRYPTO0_DMEM_PARITY_ALERT_OFFSET 0x4034
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CRYPTO0_DRF_PARITY_ALERT_LSB 0x2
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CRYPTO0_DRF_PARITY_ALERT_MASK 0x4
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CRYPTO0_DRF_PARITY_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CRYPTO0_DRF_PARITY_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CRYPTO0_DRF_PARITY_ALERT_OFFSET 0x4034
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CRYPTO0_IMEM_PARITY_ALERT_LSB 0x3
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CRYPTO0_IMEM_PARITY_ALERT_MASK 0x8
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CRYPTO0_IMEM_PARITY_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CRYPTO0_IMEM_PARITY_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CRYPTO0_IMEM_PARITY_ALERT_OFFSET 0x4034
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CRYPTO0_PGM_FAULT_ALERT_LSB 0x4
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CRYPTO0_PGM_FAULT_ALERT_MASK 0x10
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CRYPTO0_PGM_FAULT_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CRYPTO0_PGM_FAULT_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_CRYPTO0_PGM_FAULT_ALERT_OFFSET 0x4034
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_LSB 0x5
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_MASK 0x20
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_OFFSET 0x4034
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_LSB 0x6
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_MASK 0x40
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4034
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_LSB 0x7
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_MASK 0x80
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_OFFSET 0x4034
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_LSB 0x8
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_MASK 0x100
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4034
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_LSB 0x9
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_MASK 0x200
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_OFFSET 0x4034
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_LSB 0xa
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_MASK 0x400
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4034
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_LSB 0xb
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_MASK 0x800
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_OFFSET 0x4034
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_LSB 0xc
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_MASK 0x1000
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4034
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_LSB 0xd
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_MASK 0x2000
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_OFFSET 0x4034
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_LSB 0xe
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_MASK 0x4000
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4034
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_LSB 0xf
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_MASK 0x8000
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_OFFSET 0x4034
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_LSB 0x10
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_MASK 0x10000
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x4034
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_FUSE0_FUSE_DEFAULTS_ALERT_LSB 0x11
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_FUSE0_FUSE_DEFAULTS_ALERT_MASK 0x20000
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_FUSE0_FUSE_DEFAULTS_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_FUSE0_FUSE_DEFAULTS_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_FUSE0_FUSE_DEFAULTS_ALERT_OFFSET 0x4034
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_DIFF_FAIL_ALERT_LSB 0x12
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_DIFF_FAIL_ALERT_MASK 0x40000
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_DIFF_FAIL_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_DIFF_FAIL_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_DIFF_FAIL_ALERT_OFFSET 0x4034
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW0_ALERT_LSB 0x13
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW0_ALERT_MASK 0x80000
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW0_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW0_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW0_ALERT_OFFSET 0x4034
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW1_ALERT_LSB 0x14
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW1_ALERT_MASK 0x100000
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW1_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW1_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW1_ALERT_OFFSET 0x4034
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW2_ALERT_LSB 0x15
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW2_ALERT_MASK 0x200000
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW2_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW2_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW2_ALERT_OFFSET 0x4034
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW3_ALERT_LSB 0x16
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW3_ALERT_MASK 0x400000
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW3_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW3_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_FW3_ALERT_OFFSET 0x4034
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_LSB 0x17
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_MASK 0x800000
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_OFFSET 0x4034
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_LSB 0x18
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_MASK 0x1000000
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_OFFSET 0x4034
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_LSB 0x19
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_MASK 0x2000000
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_OFFSET 0x4034
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_LSB 0x1a
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_MASK 0x4000000
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_OFFSET 0x4034
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_AES_HKEY_ALERT_LSB 0x1b
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_AES_HKEY_ALERT_MASK 0x8000000
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_AES_HKEY_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_AES_HKEY_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_AES_HKEY_ALERT_OFFSET 0x4034
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_CERT_LOOKUP_ALERT_LSB 0x1c
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_CERT_LOOKUP_ALERT_MASK 0x10000000
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_CERT_LOOKUP_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_CERT_LOOKUP_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_CERT_LOOKUP_ALERT_OFFSET 0x4034
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_FLASH_ENTRY_ALERT_LSB 0x1d
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_FLASH_ENTRY_ALERT_MASK 0x20000000
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_FLASH_ENTRY_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_FLASH_ENTRY_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_FLASH_ENTRY_ALERT_OFFSET 0x4034
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_PW_ALERT_LSB 0x1e
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_PW_ALERT_MASK 0x40000000
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_PW_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_PW_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_PW_ALERT_OFFSET 0x4034
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_LSB 0x1f
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_MASK 0x80000000
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_OFFSET 0x4034
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_KEYMGR0_SHA_FAULT_ALERT_LSB 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_KEYMGR0_SHA_FAULT_ALERT_MASK 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_KEYMGR0_SHA_FAULT_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_KEYMGR0_SHA_FAULT_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_KEYMGR0_SHA_FAULT_ALERT_OFFSET 0x4038
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_KEYMGR0_SHA_HKEY_ALERT_LSB 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_KEYMGR0_SHA_HKEY_ALERT_MASK 0x2
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_KEYMGR0_SHA_HKEY_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_KEYMGR0_SHA_HKEY_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_KEYMGR0_SHA_HKEY_ALERT_OFFSET 0x4038
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_PMU_BATTERY_MON_ALERT_LSB 0x2
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_PMU_BATTERY_MON_ALERT_MASK 0x4
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_PMU_BATTERY_MON_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_PMU_BATTERY_MON_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_PMU_BATTERY_MON_ALERT_OFFSET 0x4038
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_PMU_PMU_WDOG_ALERT_LSB 0x3
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_PMU_PMU_WDOG_ALERT_MASK 0x8
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_PMU_PMU_WDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_PMU_PMU_WDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_PMU_PMU_WDOG_ALERT_OFFSET 0x4038
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_RTC0_RTC_DEAD_ALERT_LSB 0x4
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_RTC0_RTC_DEAD_ALERT_MASK 0x10
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_RTC0_RTC_DEAD_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_RTC0_RTC_DEAD_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_RTC0_RTC_DEAD_ALERT_OFFSET 0x4038
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TEMP0_MAX_TEMP_ALERT_LSB 0x5
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TEMP0_MAX_TEMP_ALERT_MASK 0x20
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TEMP0_MAX_TEMP_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TEMP0_MAX_TEMP_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TEMP0_MAX_TEMP_ALERT_OFFSET 0x4038
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_LSB 0x6
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_MASK 0x40
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_OFFSET 0x4038
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TEMP0_MIN_TEMP_ALERT_LSB 0x7
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TEMP0_MIN_TEMP_ALERT_MASK 0x80
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TEMP0_MIN_TEMP_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TEMP0_MIN_TEMP_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TEMP0_MIN_TEMP_ALERT_OFFSET 0x4038
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TRNG0_OUT_OF_SPEC_ALERT_LSB 0x8
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TRNG0_OUT_OF_SPEC_ALERT_MASK 0x100
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TRNG0_OUT_OF_SPEC_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TRNG0_OUT_OF_SPEC_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TRNG0_OUT_OF_SPEC_ALERT_OFFSET 0x4038
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TRNG0_TIMEOUT_ALERT_LSB 0x9
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TRNG0_TIMEOUT_ALERT_MASK 0x200
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TRNG0_TIMEOUT_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TRNG0_TIMEOUT_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_TRNG0_TIMEOUT_ALERT_OFFSET 0x4038
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_VOLT0_VOLT_ERR_ALERT_LSB 0xa
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_VOLT0_VOLT_ERR_ALERT_MASK 0x400
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_VOLT0_VOLT_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_VOLT0_VOLT_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_VOLT0_VOLT_ERR_ALERT_OFFSET 0x4038
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_XO0_JITTERY_TRIM_DIS_ALERT_LSB 0xb
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_XO0_JITTERY_TRIM_DIS_ALERT_MASK 0x800
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_XO0_JITTERY_TRIM_DIS_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_XO0_JITTERY_TRIM_DIS_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR1_EN1_XO0_JITTERY_TRIM_DIS_ALERT_OFFSET 0x4038
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CAMO0_BREACH_ALERT_LSB 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CAMO0_BREACH_ALERT_MASK 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CAMO0_BREACH_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CAMO0_BREACH_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CAMO0_BREACH_ALERT_OFFSET 0x403c
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CRYPTO0_DMEM_PARITY_ALERT_LSB 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CRYPTO0_DMEM_PARITY_ALERT_MASK 0x2
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CRYPTO0_DMEM_PARITY_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CRYPTO0_DMEM_PARITY_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CRYPTO0_DMEM_PARITY_ALERT_OFFSET 0x403c
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CRYPTO0_DRF_PARITY_ALERT_LSB 0x2
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CRYPTO0_DRF_PARITY_ALERT_MASK 0x4
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CRYPTO0_DRF_PARITY_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CRYPTO0_DRF_PARITY_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CRYPTO0_DRF_PARITY_ALERT_OFFSET 0x403c
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CRYPTO0_IMEM_PARITY_ALERT_LSB 0x3
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CRYPTO0_IMEM_PARITY_ALERT_MASK 0x8
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CRYPTO0_IMEM_PARITY_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CRYPTO0_IMEM_PARITY_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CRYPTO0_IMEM_PARITY_ALERT_OFFSET 0x403c
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CRYPTO0_PGM_FAULT_ALERT_LSB 0x4
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CRYPTO0_PGM_FAULT_ALERT_MASK 0x10
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CRYPTO0_PGM_FAULT_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CRYPTO0_PGM_FAULT_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_CRYPTO0_PGM_FAULT_ALERT_OFFSET 0x403c
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_LSB 0x5
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_MASK 0x20
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_OFFSET 0x403c
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_LSB 0x6
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_MASK 0x40
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x403c
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_LSB 0x7
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_MASK 0x80
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_OFFSET 0x403c
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_LSB 0x8
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_MASK 0x100
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x403c
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_LSB 0x9
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_MASK 0x200
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_OFFSET 0x403c
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_LSB 0xa
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_MASK 0x400
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x403c
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_LSB 0xb
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_MASK 0x800
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_OFFSET 0x403c
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_LSB 0xc
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_MASK 0x1000
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x403c
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_LSB 0xd
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_MASK 0x2000
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_OFFSET 0x403c
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_LSB 0xe
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_MASK 0x4000
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x403c
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_LSB 0xf
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_MASK 0x8000
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_OFFSET 0x403c
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_LSB 0x10
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_MASK 0x10000
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_OFFSET 0x403c
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_FUSE0_FUSE_DEFAULTS_ALERT_LSB 0x11
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_FUSE0_FUSE_DEFAULTS_ALERT_MASK 0x20000
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_FUSE0_FUSE_DEFAULTS_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_FUSE0_FUSE_DEFAULTS_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_FUSE0_FUSE_DEFAULTS_ALERT_OFFSET 0x403c
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_DIFF_FAIL_ALERT_LSB 0x12
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_DIFF_FAIL_ALERT_MASK 0x40000
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_DIFF_FAIL_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_DIFF_FAIL_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_DIFF_FAIL_ALERT_OFFSET 0x403c
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW0_ALERT_LSB 0x13
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW0_ALERT_MASK 0x80000
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW0_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW0_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW0_ALERT_OFFSET 0x403c
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW1_ALERT_LSB 0x14
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW1_ALERT_MASK 0x100000
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW1_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW1_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW1_ALERT_OFFSET 0x403c
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW2_ALERT_LSB 0x15
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW2_ALERT_MASK 0x200000
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW2_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW2_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW2_ALERT_OFFSET 0x403c
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW3_ALERT_LSB 0x16
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW3_ALERT_MASK 0x400000
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW3_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW3_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_FW3_ALERT_OFFSET 0x403c
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_LSB 0x17
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_MASK 0x800000
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_HEARTBEAT_FAIL_ALERT_OFFSET 0x403c
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_LSB 0x18
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_MASK 0x1000000
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_PROC_OPCODE_HASH_ALERT_OFFSET 0x403c
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_LSB 0x19
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_MASK 0x2000000
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_OFFSET 0x403c
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_LSB 0x1a
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_MASK 0x4000000
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_OFFSET 0x403c
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_AES_HKEY_ALERT_LSB 0x1b
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_AES_HKEY_ALERT_MASK 0x8000000
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_AES_HKEY_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_AES_HKEY_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_AES_HKEY_ALERT_OFFSET 0x403c
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_CERT_LOOKUP_ALERT_LSB 0x1c
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_CERT_LOOKUP_ALERT_MASK 0x10000000
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_CERT_LOOKUP_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_CERT_LOOKUP_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_CERT_LOOKUP_ALERT_OFFSET 0x403c
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_FLASH_ENTRY_ALERT_LSB 0x1d
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_FLASH_ENTRY_ALERT_MASK 0x20000000
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_FLASH_ENTRY_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_FLASH_ENTRY_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_FLASH_ENTRY_ALERT_OFFSET 0x403c
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_PW_ALERT_LSB 0x1e
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_PW_ALERT_MASK 0x40000000
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_PW_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_PW_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_PW_ALERT_OFFSET 0x403c
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_LSB 0x1f
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_MASK 0x80000000
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN0_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_OFFSET 0x403c
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_KEYMGR0_SHA_FAULT_ALERT_LSB 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_KEYMGR0_SHA_FAULT_ALERT_MASK 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_KEYMGR0_SHA_FAULT_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_KEYMGR0_SHA_FAULT_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_KEYMGR0_SHA_FAULT_ALERT_OFFSET 0x4040
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_KEYMGR0_SHA_HKEY_ALERT_LSB 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_KEYMGR0_SHA_HKEY_ALERT_MASK 0x2
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_KEYMGR0_SHA_HKEY_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_KEYMGR0_SHA_HKEY_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_KEYMGR0_SHA_HKEY_ALERT_OFFSET 0x4040
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_PMU_BATTERY_MON_ALERT_LSB 0x2
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_PMU_BATTERY_MON_ALERT_MASK 0x4
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_PMU_BATTERY_MON_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_PMU_BATTERY_MON_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_PMU_BATTERY_MON_ALERT_OFFSET 0x4040
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_PMU_PMU_WDOG_ALERT_LSB 0x3
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_PMU_PMU_WDOG_ALERT_MASK 0x8
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_PMU_PMU_WDOG_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_PMU_PMU_WDOG_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_PMU_PMU_WDOG_ALERT_OFFSET 0x4040
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_RTC0_RTC_DEAD_ALERT_LSB 0x4
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_RTC0_RTC_DEAD_ALERT_MASK 0x10
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_RTC0_RTC_DEAD_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_RTC0_RTC_DEAD_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_RTC0_RTC_DEAD_ALERT_OFFSET 0x4040
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TEMP0_MAX_TEMP_ALERT_LSB 0x5
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TEMP0_MAX_TEMP_ALERT_MASK 0x20
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TEMP0_MAX_TEMP_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TEMP0_MAX_TEMP_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TEMP0_MAX_TEMP_ALERT_OFFSET 0x4040
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_LSB 0x6
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_MASK 0x40
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TEMP0_MAX_TEMP_DIFF_ALERT_OFFSET 0x4040
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TEMP0_MIN_TEMP_ALERT_LSB 0x7
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TEMP0_MIN_TEMP_ALERT_MASK 0x80
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TEMP0_MIN_TEMP_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TEMP0_MIN_TEMP_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TEMP0_MIN_TEMP_ALERT_OFFSET 0x4040
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TRNG0_OUT_OF_SPEC_ALERT_LSB 0x8
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TRNG0_OUT_OF_SPEC_ALERT_MASK 0x100
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TRNG0_OUT_OF_SPEC_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TRNG0_OUT_OF_SPEC_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TRNG0_OUT_OF_SPEC_ALERT_OFFSET 0x4040
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TRNG0_TIMEOUT_ALERT_LSB 0x9
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TRNG0_TIMEOUT_ALERT_MASK 0x200
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TRNG0_TIMEOUT_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TRNG0_TIMEOUT_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_TRNG0_TIMEOUT_ALERT_OFFSET 0x4040
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_VOLT0_VOLT_ERR_ALERT_LSB 0xa
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_VOLT0_VOLT_ERR_ALERT_MASK 0x400
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_VOLT0_VOLT_ERR_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_VOLT0_VOLT_ERR_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_VOLT0_VOLT_ERR_ALERT_OFFSET 0x4040
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_XO0_JITTERY_TRIM_DIS_ALERT_LSB 0xb
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_XO0_JITTERY_TRIM_DIS_ALERT_MASK 0x800
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_XO0_JITTERY_TRIM_DIS_ALERT_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_XO0_JITTERY_TRIM_DIS_ALERT_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_DLYCTR2_EN1_XO0_JITTERY_TRIM_DIS_ALERT_OFFSET 0x4040
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPA_NMI_EN_LSB 0x0
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPA_NMI_EN_MASK 0x1
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPA_NMI_EN_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPA_NMI_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPA_NMI_EN_OFFSET 0x405c
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPA_DLYCTR0_EN_LSB 0x1
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPA_DLYCTR0_EN_MASK 0x2
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPA_DLYCTR0_EN_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPA_DLYCTR0_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPA_DLYCTR0_EN_OFFSET 0x405c
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPA_DLYCTR1_EN_LSB 0x2
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPA_DLYCTR1_EN_MASK 0x4
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPA_DLYCTR1_EN_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPA_DLYCTR1_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPA_DLYCTR1_EN_OFFSET 0x405c
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPA_DLYCTR2_EN_LSB 0x3
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPA_DLYCTR2_EN_MASK 0x8
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPA_DLYCTR2_EN_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPA_DLYCTR2_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPA_DLYCTR2_EN_OFFSET 0x405c
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPB_NMI_EN_LSB 0x4
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPB_NMI_EN_MASK 0x10
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPB_NMI_EN_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPB_NMI_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPB_NMI_EN_OFFSET 0x405c
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPB_DLYCTR0_EN_LSB 0x5
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPB_DLYCTR0_EN_MASK 0x20
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPB_DLYCTR0_EN_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPB_DLYCTR0_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPB_DLYCTR0_EN_OFFSET 0x405c
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPB_DLYCTR1_EN_LSB 0x6
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPB_DLYCTR1_EN_MASK 0x40
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPB_DLYCTR1_EN_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPB_DLYCTR1_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPB_DLYCTR1_EN_OFFSET 0x405c
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPB_DLYCTR2_EN_LSB 0x7
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPB_DLYCTR2_EN_MASK 0x80
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPB_DLYCTR2_EN_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPB_DLYCTR2_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPB_DLYCTR2_EN_OFFSET 0x405c
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPC_NMI_EN_LSB 0x8
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPC_NMI_EN_MASK 0x100
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPC_NMI_EN_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPC_NMI_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPC_NMI_EN_OFFSET 0x405c
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPC_DLYCTR0_EN_LSB 0x9
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPC_DLYCTR0_EN_MASK 0x200
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPC_DLYCTR0_EN_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPC_DLYCTR0_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPC_DLYCTR0_EN_OFFSET 0x405c
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPC_DLYCTR1_EN_LSB 0xa
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPC_DLYCTR1_EN_MASK 0x400
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPC_DLYCTR1_EN_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPC_DLYCTR1_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPC_DLYCTR1_EN_OFFSET 0x405c
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPC_DLYCTR2_EN_LSB 0xb
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPC_DLYCTR2_EN_MASK 0x800
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPC_DLYCTR2_EN_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPC_DLYCTR2_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_CONTROL_GROUPC_DLYCTR2_EN_OFFSET 0x405c
-#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR0_WDOG_DIS_LSB 0xc
-#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR0_WDOG_DIS_MASK 0x1000
-#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR0_WDOG_DIS_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR0_WDOG_DIS_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR0_WDOG_DIS_OFFSET 0x405c
-#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR0_SHUTDOWN_EN_LSB 0xd
-#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR0_SHUTDOWN_EN_MASK 0x2000
-#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR0_SHUTDOWN_EN_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR0_SHUTDOWN_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR0_SHUTDOWN_EN_OFFSET 0x405c
-#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR1_WDOG_DIS_LSB 0xe
-#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR1_WDOG_DIS_MASK 0x4000
-#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR1_WDOG_DIS_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR1_WDOG_DIS_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR1_WDOG_DIS_OFFSET 0x405c
-#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR1_SHUTDOWN_EN_LSB 0xf
-#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR1_SHUTDOWN_EN_MASK 0x8000
-#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR1_SHUTDOWN_EN_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR1_SHUTDOWN_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR1_SHUTDOWN_EN_OFFSET 0x405c
-#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR2_WDOG_DIS_LSB 0x10
-#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR2_WDOG_DIS_MASK 0x10000
-#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR2_WDOG_DIS_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR2_WDOG_DIS_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR2_WDOG_DIS_OFFSET 0x405c
-#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR2_SHUTDOWN_EN_LSB 0x11
-#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR2_SHUTDOWN_EN_MASK 0x20000
-#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR2_SHUTDOWN_EN_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR2_SHUTDOWN_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_CONTROL_DLYCTR2_SHUTDOWN_EN_OFFSET 0x405c
-#define GC_GLOBALSEC_ALERT_CONTROL_WATCHDOG_RESET_SHUTDOWN_EN_LSB 0x12
-#define GC_GLOBALSEC_ALERT_CONTROL_WATCHDOG_RESET_SHUTDOWN_EN_MASK 0x40000
-#define GC_GLOBALSEC_ALERT_CONTROL_WATCHDOG_RESET_SHUTDOWN_EN_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_CONTROL_WATCHDOG_RESET_SHUTDOWN_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_CONTROL_WATCHDOG_RESET_SHUTDOWN_EN_OFFSET 0x405c
-#define GC_GLOBALSEC_ALERT_CONTROL_WATCHDOG_RESET_FIREWALL_EN_LSB 0x13
-#define GC_GLOBALSEC_ALERT_CONTROL_WATCHDOG_RESET_FIREWALL_EN_MASK 0x80000
-#define GC_GLOBALSEC_ALERT_CONTROL_WATCHDOG_RESET_FIREWALL_EN_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_CONTROL_WATCHDOG_RESET_FIREWALL_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_CONTROL_WATCHDOG_RESET_FIREWALL_EN_OFFSET 0x405c
-#define GC_GLOBALSEC_ALERT_CONTROL_PROC_LOCKUP_SHUTDOWN_EN_LSB 0x14
-#define GC_GLOBALSEC_ALERT_CONTROL_PROC_LOCKUP_SHUTDOWN_EN_MASK 0x100000
-#define GC_GLOBALSEC_ALERT_CONTROL_PROC_LOCKUP_SHUTDOWN_EN_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_CONTROL_PROC_LOCKUP_SHUTDOWN_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_CONTROL_PROC_LOCKUP_SHUTDOWN_EN_OFFSET 0x405c
-#define GC_GLOBALSEC_ALERT_CONTROL_PROC_LOCKUP_FIREWALL_EN_LSB 0x15
-#define GC_GLOBALSEC_ALERT_CONTROL_PROC_LOCKUP_FIREWALL_EN_MASK 0x200000
-#define GC_GLOBALSEC_ALERT_CONTROL_PROC_LOCKUP_FIREWALL_EN_SIZE 0x1
-#define GC_GLOBALSEC_ALERT_CONTROL_PROC_LOCKUP_FIREWALL_EN_DEFAULT 0x0
-#define GC_GLOBALSEC_ALERT_CONTROL_PROC_LOCKUP_FIREWALL_EN_OFFSET 0x405c
-#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_DIG_IN_LSB 0x0
-#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_DIG_IN_MASK 0x3
-#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_DIG_IN_SIZE 0x2
-#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_DIG_IN_DEFAULT 0x3
-#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_DIG_IN_OFFSET 0x40d4
-#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_ENB_LSB 0x2
-#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_ENB_MASK 0xc
-#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_ENB_SIZE 0x2
-#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_ENB_DEFAULT 0x3
-#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_ENB_OFFSET 0x40d4
-#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_PWR_RDY_LSB 0x4
-#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_PWR_RDY_MASK 0x10
-#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_PWR_RDY_SIZE 0x1
-#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_PWR_RDY_DEFAULT 0x0
-#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_PWR_RDY_OFFSET 0x40d4
-#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_PWR_SW_ENB_LSB 0x5
-#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_PWR_SW_ENB_MASK 0x20
-#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_PWR_SW_ENB_SIZE 0x1
-#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_PWR_SW_ENB_DEFAULT 0x1
-#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_PWR_SW_ENB_OFFSET 0x40d4
-#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_RST_LSB 0x6
-#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_RST_MASK 0x40
-#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_RST_SIZE 0x1
-#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_RST_DEFAULT 0x0
-#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_RST_OFFSET 0x40d4
-#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_SEL_LSB 0x7
-#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_SEL_MASK 0x380
-#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_SEL_SIZE 0x3
-#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_SEL_DEFAULT 0x0
-#define GC_GLOBALSEC_ANTEST_SEN_LSR_INPUT_SEL_OFFSET 0x40d4
-#define GC_GLOBALSEC_VERSION_CHANGE_LSB          0x0
-#define GC_GLOBALSEC_VERSION_CHANGE_MASK         0xffffff
-#define GC_GLOBALSEC_VERSION_CHANGE_SIZE         0x18
-#define GC_GLOBALSEC_VERSION_CHANGE_DEFAULT      0x10913
-#define GC_GLOBALSEC_VERSION_CHANGE_OFFSET       0x40dc
-#define GC_GLOBALSEC_VERSION_REVISION_LSB        0x18
-#define GC_GLOBALSEC_VERSION_REVISION_MASK       0xff000000
-#define GC_GLOBALSEC_VERSION_REVISION_SIZE       0x8
-#define GC_GLOBALSEC_VERSION_REVISION_DEFAULT    0x59
-#define GC_GLOBALSEC_VERSION_REVISION_OFFSET     0x40dc
-#define GC_I2C_CTRL_PHASESTEPS_P0_LSB            0x0
-#define GC_I2C_CTRL_PHASESTEPS_P0_MASK           0x3f
-#define GC_I2C_CTRL_PHASESTEPS_P0_SIZE           0x6
-#define GC_I2C_CTRL_PHASESTEPS_P0_DEFAULT        0x6
-#define GC_I2C_CTRL_PHASESTEPS_P0_OFFSET         0x8
-#define GC_I2C_CTRL_PHASESTEPS_P1_LSB            0x6
-#define GC_I2C_CTRL_PHASESTEPS_P1_MASK           0xfc0
-#define GC_I2C_CTRL_PHASESTEPS_P1_SIZE           0x6
-#define GC_I2C_CTRL_PHASESTEPS_P1_DEFAULT        0x6
-#define GC_I2C_CTRL_PHASESTEPS_P1_OFFSET         0x8
-#define GC_I2C_CTRL_PHASESTEPS_P2_LSB            0xc
-#define GC_I2C_CTRL_PHASESTEPS_P2_MASK           0x3f000
-#define GC_I2C_CTRL_PHASESTEPS_P2_SIZE           0x6
-#define GC_I2C_CTRL_PHASESTEPS_P2_DEFAULT        0x8
-#define GC_I2C_CTRL_PHASESTEPS_P2_OFFSET         0x8
-#define GC_I2C_CTRL_PHASESTEPS_P3_LSB            0x12
-#define GC_I2C_CTRL_PHASESTEPS_P3_MASK           0xfc0000
-#define GC_I2C_CTRL_PHASESTEPS_P3_SIZE           0x6
-#define GC_I2C_CTRL_PHASESTEPS_P3_DEFAULT        0x6
-#define GC_I2C_CTRL_PHASESTEPS_P3_OFFSET         0x8
-#define GC_I2C_CTRL_SDA_VAL_FREE_BUS_PHASE0_LSB  0x0
-#define GC_I2C_CTRL_SDA_VAL_FREE_BUS_PHASE0_MASK 0x1
-#define GC_I2C_CTRL_SDA_VAL_FREE_BUS_PHASE0_SIZE 0x1
-#define GC_I2C_CTRL_SDA_VAL_FREE_BUS_PHASE0_DEFAULT 0x1
-#define GC_I2C_CTRL_SDA_VAL_FREE_BUS_PHASE0_OFFSET 0xc
-#define GC_I2C_CTRL_SDA_VAL_FREE_BUS_PHASE1_LSB  0x1
-#define GC_I2C_CTRL_SDA_VAL_FREE_BUS_PHASE1_MASK 0x2
-#define GC_I2C_CTRL_SDA_VAL_FREE_BUS_PHASE1_SIZE 0x1
-#define GC_I2C_CTRL_SDA_VAL_FREE_BUS_PHASE1_DEFAULT 0x1
-#define GC_I2C_CTRL_SDA_VAL_FREE_BUS_PHASE1_OFFSET 0xc
-#define GC_I2C_CTRL_SDA_VAL_FREE_BUS_PHASE2_LSB  0x2
-#define GC_I2C_CTRL_SDA_VAL_FREE_BUS_PHASE2_MASK 0x4
-#define GC_I2C_CTRL_SDA_VAL_FREE_BUS_PHASE2_SIZE 0x1
-#define GC_I2C_CTRL_SDA_VAL_FREE_BUS_PHASE2_DEFAULT 0x1
-#define GC_I2C_CTRL_SDA_VAL_FREE_BUS_PHASE2_OFFSET 0xc
-#define GC_I2C_CTRL_SDA_VAL_FREE_BUS_LSB         0x3
-#define GC_I2C_CTRL_SDA_VAL_FREE_BUS_MASK        0x8
-#define GC_I2C_CTRL_SDA_VAL_FREE_BUS_SIZE        0x1
-#define GC_I2C_CTRL_SDA_VAL_FREE_BUS_DEFAULT     0x1
-#define GC_I2C_CTRL_SDA_VAL_FREE_BUS_OFFSET      0xc
-#define GC_I2C_CTRL_SDA_VAL_WRITE0_PHASE0_LSB    0x4
-#define GC_I2C_CTRL_SDA_VAL_WRITE0_PHASE0_MASK   0x10
-#define GC_I2C_CTRL_SDA_VAL_WRITE0_PHASE0_SIZE   0x1
-#define GC_I2C_CTRL_SDA_VAL_WRITE0_PHASE0_DEFAULT 0x0
-#define GC_I2C_CTRL_SDA_VAL_WRITE0_PHASE0_OFFSET 0xc
-#define GC_I2C_CTRL_SDA_VAL_WRITE0_PHASE1_LSB    0x5
-#define GC_I2C_CTRL_SDA_VAL_WRITE0_PHASE1_MASK   0x20
-#define GC_I2C_CTRL_SDA_VAL_WRITE0_PHASE1_SIZE   0x1
-#define GC_I2C_CTRL_SDA_VAL_WRITE0_PHASE1_DEFAULT 0x0
-#define GC_I2C_CTRL_SDA_VAL_WRITE0_PHASE1_OFFSET 0xc
-#define GC_I2C_CTRL_SDA_VAL_WRITE0_PHASE2_LSB    0x6
-#define GC_I2C_CTRL_SDA_VAL_WRITE0_PHASE2_MASK   0x40
-#define GC_I2C_CTRL_SDA_VAL_WRITE0_PHASE2_SIZE   0x1
-#define GC_I2C_CTRL_SDA_VAL_WRITE0_PHASE2_DEFAULT 0x0
-#define GC_I2C_CTRL_SDA_VAL_WRITE0_PHASE2_OFFSET 0xc
-#define GC_I2C_CTRL_SDA_VAL_STANDBY_VAL0_LSB     0x7
-#define GC_I2C_CTRL_SDA_VAL_STANDBY_VAL0_MASK    0x80
-#define GC_I2C_CTRL_SDA_VAL_STANDBY_VAL0_SIZE    0x1
-#define GC_I2C_CTRL_SDA_VAL_STANDBY_VAL0_DEFAULT 0x0
-#define GC_I2C_CTRL_SDA_VAL_STANDBY_VAL0_OFFSET  0xc
-#define GC_I2C_CTRL_SDA_VAL_WRITE1_PHASE0_LSB    0x8
-#define GC_I2C_CTRL_SDA_VAL_WRITE1_PHASE0_MASK   0x100
-#define GC_I2C_CTRL_SDA_VAL_WRITE1_PHASE0_SIZE   0x1
-#define GC_I2C_CTRL_SDA_VAL_WRITE1_PHASE0_DEFAULT 0x1
-#define GC_I2C_CTRL_SDA_VAL_WRITE1_PHASE0_OFFSET 0xc
-#define GC_I2C_CTRL_SDA_VAL_WRITE1_PHASE1_LSB    0x9
-#define GC_I2C_CTRL_SDA_VAL_WRITE1_PHASE1_MASK   0x200
-#define GC_I2C_CTRL_SDA_VAL_WRITE1_PHASE1_SIZE   0x1
-#define GC_I2C_CTRL_SDA_VAL_WRITE1_PHASE1_DEFAULT 0x1
-#define GC_I2C_CTRL_SDA_VAL_WRITE1_PHASE1_OFFSET 0xc
-#define GC_I2C_CTRL_SDA_VAL_WRITE1_PHASE2_LSB    0xa
-#define GC_I2C_CTRL_SDA_VAL_WRITE1_PHASE2_MASK   0x400
-#define GC_I2C_CTRL_SDA_VAL_WRITE1_PHASE2_SIZE   0x1
-#define GC_I2C_CTRL_SDA_VAL_WRITE1_PHASE2_DEFAULT 0x1
-#define GC_I2C_CTRL_SDA_VAL_WRITE1_PHASE2_OFFSET 0xc
-#define GC_I2C_CTRL_SDA_VAL_STANDBY_VAL1_LSB     0xb
-#define GC_I2C_CTRL_SDA_VAL_STANDBY_VAL1_MASK    0x800
-#define GC_I2C_CTRL_SDA_VAL_STANDBY_VAL1_SIZE    0x1
-#define GC_I2C_CTRL_SDA_VAL_STANDBY_VAL1_DEFAULT 0x1
-#define GC_I2C_CTRL_SDA_VAL_STANDBY_VAL1_OFFSET  0xc
-#define GC_I2C_CTRL_SDA_VAL_READ_PHASE0_LSB      0xc
-#define GC_I2C_CTRL_SDA_VAL_READ_PHASE0_MASK     0x1000
-#define GC_I2C_CTRL_SDA_VAL_READ_PHASE0_SIZE     0x1
-#define GC_I2C_CTRL_SDA_VAL_READ_PHASE0_DEFAULT  0x1
-#define GC_I2C_CTRL_SDA_VAL_READ_PHASE0_OFFSET   0xc
-#define GC_I2C_CTRL_SDA_VAL_READ_PHASE1_LSB      0xd
-#define GC_I2C_CTRL_SDA_VAL_READ_PHASE1_MASK     0x2000
-#define GC_I2C_CTRL_SDA_VAL_READ_PHASE1_SIZE     0x1
-#define GC_I2C_CTRL_SDA_VAL_READ_PHASE1_DEFAULT  0x1
-#define GC_I2C_CTRL_SDA_VAL_READ_PHASE1_OFFSET   0xc
-#define GC_I2C_CTRL_SDA_VAL_READ_PHASE2_LSB      0xe
-#define GC_I2C_CTRL_SDA_VAL_READ_PHASE2_MASK     0x4000
-#define GC_I2C_CTRL_SDA_VAL_READ_PHASE2_SIZE     0x1
-#define GC_I2C_CTRL_SDA_VAL_READ_PHASE2_DEFAULT  0x1
-#define GC_I2C_CTRL_SDA_VAL_READ_PHASE2_OFFSET   0xc
-#define GC_I2C_CTRL_SDA_VAL_HOLD0_PHASE0_LSB     0xf
-#define GC_I2C_CTRL_SDA_VAL_HOLD0_PHASE0_MASK    0x8000
-#define GC_I2C_CTRL_SDA_VAL_HOLD0_PHASE0_SIZE    0x1
-#define GC_I2C_CTRL_SDA_VAL_HOLD0_PHASE0_DEFAULT 0x0
-#define GC_I2C_CTRL_SDA_VAL_HOLD0_PHASE0_OFFSET  0xc
-#define GC_I2C_CTRL_SDA_VAL_START_PHASE0_LSB     0x10
-#define GC_I2C_CTRL_SDA_VAL_START_PHASE0_MASK    0x10000
-#define GC_I2C_CTRL_SDA_VAL_START_PHASE0_SIZE    0x1
-#define GC_I2C_CTRL_SDA_VAL_START_PHASE0_DEFAULT 0x1
-#define GC_I2C_CTRL_SDA_VAL_START_PHASE0_OFFSET  0xc
-#define GC_I2C_CTRL_SDA_VAL_START_PHASE1_LSB     0x11
-#define GC_I2C_CTRL_SDA_VAL_START_PHASE1_MASK    0x20000
-#define GC_I2C_CTRL_SDA_VAL_START_PHASE1_SIZE    0x1
-#define GC_I2C_CTRL_SDA_VAL_START_PHASE1_DEFAULT 0x0
-#define GC_I2C_CTRL_SDA_VAL_START_PHASE1_OFFSET  0xc
-#define GC_I2C_CTRL_SDA_VAL_START_PHASE2_LSB     0x12
-#define GC_I2C_CTRL_SDA_VAL_START_PHASE2_MASK    0x40000
-#define GC_I2C_CTRL_SDA_VAL_START_PHASE2_SIZE    0x1
-#define GC_I2C_CTRL_SDA_VAL_START_PHASE2_DEFAULT 0x0
-#define GC_I2C_CTRL_SDA_VAL_START_PHASE2_OFFSET  0xc
-#define GC_I2C_CTRL_SDA_VAL_ERROR_SCL_CONFLICT_LSB 0x13
-#define GC_I2C_CTRL_SDA_VAL_ERROR_SCL_CONFLICT_MASK 0x80000
-#define GC_I2C_CTRL_SDA_VAL_ERROR_SCL_CONFLICT_SIZE 0x1
-#define GC_I2C_CTRL_SDA_VAL_ERROR_SCL_CONFLICT_DEFAULT 0x1
-#define GC_I2C_CTRL_SDA_VAL_ERROR_SCL_CONFLICT_OFFSET 0xc
-#define GC_I2C_CTRL_SDA_VAL_STOP_PHASE0_LSB      0x14
-#define GC_I2C_CTRL_SDA_VAL_STOP_PHASE0_MASK     0x100000
-#define GC_I2C_CTRL_SDA_VAL_STOP_PHASE0_SIZE     0x1
-#define GC_I2C_CTRL_SDA_VAL_STOP_PHASE0_DEFAULT  0x0
-#define GC_I2C_CTRL_SDA_VAL_STOP_PHASE0_OFFSET   0xc
-#define GC_I2C_CTRL_SDA_VAL_STOP_PHASE1_LSB      0x15
-#define GC_I2C_CTRL_SDA_VAL_STOP_PHASE1_MASK     0x200000
-#define GC_I2C_CTRL_SDA_VAL_STOP_PHASE1_SIZE     0x1
-#define GC_I2C_CTRL_SDA_VAL_STOP_PHASE1_DEFAULT  0x0
-#define GC_I2C_CTRL_SDA_VAL_STOP_PHASE1_OFFSET   0xc
-#define GC_I2C_CTRL_SDA_VAL_STOP_PHASE2_LSB      0x16
-#define GC_I2C_CTRL_SDA_VAL_STOP_PHASE2_MASK     0x400000
-#define GC_I2C_CTRL_SDA_VAL_STOP_PHASE2_SIZE     0x1
-#define GC_I2C_CTRL_SDA_VAL_STOP_PHASE2_DEFAULT  0x0
-#define GC_I2C_CTRL_SDA_VAL_STOP_PHASE2_OFFSET   0xc
-#define GC_I2C_CTRL_SDA_VAL_ERROR_SDA_CONFLICT_LSB 0x17
-#define GC_I2C_CTRL_SDA_VAL_ERROR_SDA_CONFLICT_MASK 0x800000
-#define GC_I2C_CTRL_SDA_VAL_ERROR_SDA_CONFLICT_SIZE 0x1
-#define GC_I2C_CTRL_SDA_VAL_ERROR_SDA_CONFLICT_DEFAULT 0x1
-#define GC_I2C_CTRL_SDA_VAL_ERROR_SDA_CONFLICT_OFFSET 0xc
-#define GC_I2C_CTRL_SDA_VAL_SCL0_PHASE0_LSB      0x18
-#define GC_I2C_CTRL_SDA_VAL_SCL0_PHASE0_MASK     0x1000000
-#define GC_I2C_CTRL_SDA_VAL_SCL0_PHASE0_SIZE     0x1
-#define GC_I2C_CTRL_SDA_VAL_SCL0_PHASE0_DEFAULT  0x1
-#define GC_I2C_CTRL_SDA_VAL_SCL0_PHASE0_OFFSET   0xc
-#define GC_I2C_CTRL_SDA_OVRD_HOLD0_PHASE0_LSB    0x0
-#define GC_I2C_CTRL_SDA_OVRD_HOLD0_PHASE0_MASK   0x1
-#define GC_I2C_CTRL_SDA_OVRD_HOLD0_PHASE0_SIZE   0x1
-#define GC_I2C_CTRL_SDA_OVRD_HOLD0_PHASE0_DEFAULT 0x0
-#define GC_I2C_CTRL_SDA_OVRD_HOLD0_PHASE0_OFFSET 0x10
-#define GC_I2C_CTRL_SDA_OVRD_READ_PHASE0_LSB     0x1
-#define GC_I2C_CTRL_SDA_OVRD_READ_PHASE0_MASK    0x2
-#define GC_I2C_CTRL_SDA_OVRD_READ_PHASE0_SIZE    0x1
-#define GC_I2C_CTRL_SDA_OVRD_READ_PHASE0_DEFAULT 0x0
-#define GC_I2C_CTRL_SDA_OVRD_READ_PHASE0_OFFSET  0x10
-#define GC_I2C_CTRL_SDA_OVRD_SCL0_PHASE0_LSB     0x2
-#define GC_I2C_CTRL_SDA_OVRD_SCL0_PHASE0_MASK    0x4
-#define GC_I2C_CTRL_SDA_OVRD_SCL0_PHASE0_SIZE    0x1
-#define GC_I2C_CTRL_SDA_OVRD_SCL0_PHASE0_DEFAULT 0x0
-#define GC_I2C_CTRL_SDA_OVRD_SCL0_PHASE0_OFFSET  0x10
-#define GC_I2C_CTRL_SDA_OVRD_START_PHASE0_LSB    0x3
-#define GC_I2C_CTRL_SDA_OVRD_START_PHASE0_MASK   0x8
-#define GC_I2C_CTRL_SDA_OVRD_START_PHASE0_SIZE   0x1
-#define GC_I2C_CTRL_SDA_OVRD_START_PHASE0_DEFAULT 0x0
-#define GC_I2C_CTRL_SDA_OVRD_START_PHASE0_OFFSET 0x10
-#define GC_I2C_CTRL_SDA_OVRD_STOP_PHASE0_LSB     0x4
-#define GC_I2C_CTRL_SDA_OVRD_STOP_PHASE0_MASK    0x10
-#define GC_I2C_CTRL_SDA_OVRD_STOP_PHASE0_SIZE    0x1
-#define GC_I2C_CTRL_SDA_OVRD_STOP_PHASE0_DEFAULT 0x0
-#define GC_I2C_CTRL_SDA_OVRD_STOP_PHASE0_OFFSET  0x10
-#define GC_I2C_CTRL_SDA_OVRD_WRITE0_PHASE0_LSB   0x5
-#define GC_I2C_CTRL_SDA_OVRD_WRITE0_PHASE0_MASK  0x20
-#define GC_I2C_CTRL_SDA_OVRD_WRITE0_PHASE0_SIZE  0x1
-#define GC_I2C_CTRL_SDA_OVRD_WRITE0_PHASE0_DEFAULT 0x0
-#define GC_I2C_CTRL_SDA_OVRD_WRITE0_PHASE0_OFFSET 0x10
-#define GC_I2C_CTRL_SDA_OVRD_WRITE1_PHASE0_LSB   0x6
-#define GC_I2C_CTRL_SDA_OVRD_WRITE1_PHASE0_MASK  0x40
-#define GC_I2C_CTRL_SDA_OVRD_WRITE1_PHASE0_SIZE  0x1
-#define GC_I2C_CTRL_SDA_OVRD_WRITE1_PHASE0_DEFAULT 0x0
-#define GC_I2C_CTRL_SDA_OVRD_WRITE1_PHASE0_OFFSET 0x10
-#define GC_I2C_CTRL_SDA_OVRD_FREE_BUS_PHASE0_LSB 0x7
-#define GC_I2C_CTRL_SDA_OVRD_FREE_BUS_PHASE0_MASK 0x80
-#define GC_I2C_CTRL_SDA_OVRD_FREE_BUS_PHASE0_SIZE 0x1
-#define GC_I2C_CTRL_SDA_OVRD_FREE_BUS_PHASE0_DEFAULT 0x0
-#define GC_I2C_CTRL_SDA_OVRD_FREE_BUS_PHASE0_OFFSET 0x10
-#define GC_I2C_CTRL_SDA_OVRD_FREE_BUS_PHASE1_LSB 0x8
-#define GC_I2C_CTRL_SDA_OVRD_FREE_BUS_PHASE1_MASK 0x100
-#define GC_I2C_CTRL_SDA_OVRD_FREE_BUS_PHASE1_SIZE 0x1
-#define GC_I2C_CTRL_SDA_OVRD_FREE_BUS_PHASE1_DEFAULT 0x1
-#define GC_I2C_CTRL_SDA_OVRD_FREE_BUS_PHASE1_OFFSET 0x10
-#define GC_I2C_CTRL_SDA_OVRD_FREE_BUS_PHASE2_LSB 0x9
-#define GC_I2C_CTRL_SDA_OVRD_FREE_BUS_PHASE2_MASK 0x200
-#define GC_I2C_CTRL_SDA_OVRD_FREE_BUS_PHASE2_SIZE 0x1
-#define GC_I2C_CTRL_SDA_OVRD_FREE_BUS_PHASE2_DEFAULT 0x1
-#define GC_I2C_CTRL_SDA_OVRD_FREE_BUS_PHASE2_OFFSET 0x10
-#define GC_I2C_CTRL_SDA_OVRD_ERROR_SDA_CONFLICT_LSB 0xa
-#define GC_I2C_CTRL_SDA_OVRD_ERROR_SDA_CONFLICT_MASK 0x400
-#define GC_I2C_CTRL_SDA_OVRD_ERROR_SDA_CONFLICT_SIZE 0x1
-#define GC_I2C_CTRL_SDA_OVRD_ERROR_SDA_CONFLICT_DEFAULT 0x0
-#define GC_I2C_CTRL_SDA_OVRD_ERROR_SDA_CONFLICT_OFFSET 0x10
-#define GC_I2C_CTRL_SCL_VAL_FREE_BUS_PHASE0_LSB  0x0
-#define GC_I2C_CTRL_SCL_VAL_FREE_BUS_PHASE0_MASK 0x1
-#define GC_I2C_CTRL_SCL_VAL_FREE_BUS_PHASE0_SIZE 0x1
-#define GC_I2C_CTRL_SCL_VAL_FREE_BUS_PHASE0_DEFAULT 0x0
-#define GC_I2C_CTRL_SCL_VAL_FREE_BUS_PHASE0_OFFSET 0x14
-#define GC_I2C_CTRL_SCL_VAL_FREE_BUS_PHASE1_LSB  0x1
-#define GC_I2C_CTRL_SCL_VAL_FREE_BUS_PHASE1_MASK 0x2
-#define GC_I2C_CTRL_SCL_VAL_FREE_BUS_PHASE1_SIZE 0x1
-#define GC_I2C_CTRL_SCL_VAL_FREE_BUS_PHASE1_DEFAULT 0x1
-#define GC_I2C_CTRL_SCL_VAL_FREE_BUS_PHASE1_OFFSET 0x14
-#define GC_I2C_CTRL_SCL_VAL_FREE_BUS_PHASE2_LSB  0x2
-#define GC_I2C_CTRL_SCL_VAL_FREE_BUS_PHASE2_MASK 0x4
-#define GC_I2C_CTRL_SCL_VAL_FREE_BUS_PHASE2_SIZE 0x1
-#define GC_I2C_CTRL_SCL_VAL_FREE_BUS_PHASE2_DEFAULT 0x1
-#define GC_I2C_CTRL_SCL_VAL_FREE_BUS_PHASE2_OFFSET 0x14
-#define GC_I2C_CTRL_SCL_VAL_FREE_BUS_LSB         0x3
-#define GC_I2C_CTRL_SCL_VAL_FREE_BUS_MASK        0x8
-#define GC_I2C_CTRL_SCL_VAL_FREE_BUS_SIZE        0x1
-#define GC_I2C_CTRL_SCL_VAL_FREE_BUS_DEFAULT     0x1
-#define GC_I2C_CTRL_SCL_VAL_FREE_BUS_OFFSET      0x14
-#define GC_I2C_CTRL_SCL_VAL_WRITE0_PHASE0_LSB    0x4
-#define GC_I2C_CTRL_SCL_VAL_WRITE0_PHASE0_MASK   0x10
-#define GC_I2C_CTRL_SCL_VAL_WRITE0_PHASE0_SIZE   0x1
-#define GC_I2C_CTRL_SCL_VAL_WRITE0_PHASE0_DEFAULT 0x0
-#define GC_I2C_CTRL_SCL_VAL_WRITE0_PHASE0_OFFSET 0x14
-#define GC_I2C_CTRL_SCL_VAL_WRITE0_PHASE1_LSB    0x5
-#define GC_I2C_CTRL_SCL_VAL_WRITE0_PHASE1_MASK   0x20
-#define GC_I2C_CTRL_SCL_VAL_WRITE0_PHASE1_SIZE   0x1
-#define GC_I2C_CTRL_SCL_VAL_WRITE0_PHASE1_DEFAULT 0x1
-#define GC_I2C_CTRL_SCL_VAL_WRITE0_PHASE1_OFFSET 0x14
-#define GC_I2C_CTRL_SCL_VAL_WRITE0_PHASE2_LSB    0x6
-#define GC_I2C_CTRL_SCL_VAL_WRITE0_PHASE2_MASK   0x40
-#define GC_I2C_CTRL_SCL_VAL_WRITE0_PHASE2_SIZE   0x1
-#define GC_I2C_CTRL_SCL_VAL_WRITE0_PHASE2_DEFAULT 0x1
-#define GC_I2C_CTRL_SCL_VAL_WRITE0_PHASE2_OFFSET 0x14
-#define GC_I2C_CTRL_SCL_VAL_STANDBY_VAL0_LSB     0x7
-#define GC_I2C_CTRL_SCL_VAL_STANDBY_VAL0_MASK    0x80
-#define GC_I2C_CTRL_SCL_VAL_STANDBY_VAL0_SIZE    0x1
-#define GC_I2C_CTRL_SCL_VAL_STANDBY_VAL0_DEFAULT 0x0
-#define GC_I2C_CTRL_SCL_VAL_STANDBY_VAL0_OFFSET  0x14
-#define GC_I2C_CTRL_SCL_VAL_WRITE1_PHASE0_LSB    0x8
-#define GC_I2C_CTRL_SCL_VAL_WRITE1_PHASE0_MASK   0x100
-#define GC_I2C_CTRL_SCL_VAL_WRITE1_PHASE0_SIZE   0x1
-#define GC_I2C_CTRL_SCL_VAL_WRITE1_PHASE0_DEFAULT 0x0
-#define GC_I2C_CTRL_SCL_VAL_WRITE1_PHASE0_OFFSET 0x14
-#define GC_I2C_CTRL_SCL_VAL_WRITE1_PHASE1_LSB    0x9
-#define GC_I2C_CTRL_SCL_VAL_WRITE1_PHASE1_MASK   0x200
-#define GC_I2C_CTRL_SCL_VAL_WRITE1_PHASE1_SIZE   0x1
-#define GC_I2C_CTRL_SCL_VAL_WRITE1_PHASE1_DEFAULT 0x1
-#define GC_I2C_CTRL_SCL_VAL_WRITE1_PHASE1_OFFSET 0x14
-#define GC_I2C_CTRL_SCL_VAL_WRITE1_PHASE2_LSB    0xa
-#define GC_I2C_CTRL_SCL_VAL_WRITE1_PHASE2_MASK   0x400
-#define GC_I2C_CTRL_SCL_VAL_WRITE1_PHASE2_SIZE   0x1
-#define GC_I2C_CTRL_SCL_VAL_WRITE1_PHASE2_DEFAULT 0x1
-#define GC_I2C_CTRL_SCL_VAL_WRITE1_PHASE2_OFFSET 0x14
-#define GC_I2C_CTRL_SCL_VAL_STANDBY_VAL1_LSB     0xb
-#define GC_I2C_CTRL_SCL_VAL_STANDBY_VAL1_MASK    0x800
-#define GC_I2C_CTRL_SCL_VAL_STANDBY_VAL1_SIZE    0x1
-#define GC_I2C_CTRL_SCL_VAL_STANDBY_VAL1_DEFAULT 0x0
-#define GC_I2C_CTRL_SCL_VAL_STANDBY_VAL1_OFFSET  0x14
-#define GC_I2C_CTRL_SCL_VAL_READ_PHASE0_LSB      0xc
-#define GC_I2C_CTRL_SCL_VAL_READ_PHASE0_MASK     0x1000
-#define GC_I2C_CTRL_SCL_VAL_READ_PHASE0_SIZE     0x1
-#define GC_I2C_CTRL_SCL_VAL_READ_PHASE0_DEFAULT  0x0
-#define GC_I2C_CTRL_SCL_VAL_READ_PHASE0_OFFSET   0x14
-#define GC_I2C_CTRL_SCL_VAL_READ_PHASE1_LSB      0xd
-#define GC_I2C_CTRL_SCL_VAL_READ_PHASE1_MASK     0x2000
-#define GC_I2C_CTRL_SCL_VAL_READ_PHASE1_SIZE     0x1
-#define GC_I2C_CTRL_SCL_VAL_READ_PHASE1_DEFAULT  0x1
-#define GC_I2C_CTRL_SCL_VAL_READ_PHASE1_OFFSET   0x14
-#define GC_I2C_CTRL_SCL_VAL_READ_PHASE2_LSB      0xe
-#define GC_I2C_CTRL_SCL_VAL_READ_PHASE2_MASK     0x4000
-#define GC_I2C_CTRL_SCL_VAL_READ_PHASE2_SIZE     0x1
-#define GC_I2C_CTRL_SCL_VAL_READ_PHASE2_DEFAULT  0x1
-#define GC_I2C_CTRL_SCL_VAL_READ_PHASE2_OFFSET   0x14
-#define GC_I2C_CTRL_SCL_VAL_HOLD0_PHASE0_LSB     0xf
-#define GC_I2C_CTRL_SCL_VAL_HOLD0_PHASE0_MASK    0x8000
-#define GC_I2C_CTRL_SCL_VAL_HOLD0_PHASE0_SIZE    0x1
-#define GC_I2C_CTRL_SCL_VAL_HOLD0_PHASE0_DEFAULT 0x0
-#define GC_I2C_CTRL_SCL_VAL_HOLD0_PHASE0_OFFSET  0x14
-#define GC_I2C_CTRL_SCL_VAL_START_PHASE0_LSB     0x10
-#define GC_I2C_CTRL_SCL_VAL_START_PHASE0_MASK    0x10000
-#define GC_I2C_CTRL_SCL_VAL_START_PHASE0_SIZE    0x1
-#define GC_I2C_CTRL_SCL_VAL_START_PHASE0_DEFAULT 0x1
-#define GC_I2C_CTRL_SCL_VAL_START_PHASE0_OFFSET  0x14
-#define GC_I2C_CTRL_SCL_VAL_START_PHASE1_LSB     0x11
-#define GC_I2C_CTRL_SCL_VAL_START_PHASE1_MASK    0x20000
-#define GC_I2C_CTRL_SCL_VAL_START_PHASE1_SIZE    0x1
-#define GC_I2C_CTRL_SCL_VAL_START_PHASE1_DEFAULT 0x1
-#define GC_I2C_CTRL_SCL_VAL_START_PHASE1_OFFSET  0x14
-#define GC_I2C_CTRL_SCL_VAL_START_PHASE2_LSB     0x12
-#define GC_I2C_CTRL_SCL_VAL_START_PHASE2_MASK    0x40000
-#define GC_I2C_CTRL_SCL_VAL_START_PHASE2_SIZE    0x1
-#define GC_I2C_CTRL_SCL_VAL_START_PHASE2_DEFAULT 0x1
-#define GC_I2C_CTRL_SCL_VAL_START_PHASE2_OFFSET  0x14
-#define GC_I2C_CTRL_SCL_VAL_ERROR_SCL_CONFLICT_LSB 0x13
-#define GC_I2C_CTRL_SCL_VAL_ERROR_SCL_CONFLICT_MASK 0x80000
-#define GC_I2C_CTRL_SCL_VAL_ERROR_SCL_CONFLICT_SIZE 0x1
-#define GC_I2C_CTRL_SCL_VAL_ERROR_SCL_CONFLICT_DEFAULT 0x0
-#define GC_I2C_CTRL_SCL_VAL_ERROR_SCL_CONFLICT_OFFSET 0x14
-#define GC_I2C_CTRL_SCL_VAL_STOP_PHASE0_LSB      0x14
-#define GC_I2C_CTRL_SCL_VAL_STOP_PHASE0_MASK     0x100000
-#define GC_I2C_CTRL_SCL_VAL_STOP_PHASE0_SIZE     0x1
-#define GC_I2C_CTRL_SCL_VAL_STOP_PHASE0_DEFAULT  0x0
-#define GC_I2C_CTRL_SCL_VAL_STOP_PHASE0_OFFSET   0x14
-#define GC_I2C_CTRL_SCL_VAL_STOP_PHASE1_LSB      0x15
-#define GC_I2C_CTRL_SCL_VAL_STOP_PHASE1_MASK     0x200000
-#define GC_I2C_CTRL_SCL_VAL_STOP_PHASE1_SIZE     0x1
-#define GC_I2C_CTRL_SCL_VAL_STOP_PHASE1_DEFAULT  0x1
-#define GC_I2C_CTRL_SCL_VAL_STOP_PHASE1_OFFSET   0x14
-#define GC_I2C_CTRL_SCL_VAL_STOP_PHASE2_LSB      0x16
-#define GC_I2C_CTRL_SCL_VAL_STOP_PHASE2_MASK     0x400000
-#define GC_I2C_CTRL_SCL_VAL_STOP_PHASE2_SIZE     0x1
-#define GC_I2C_CTRL_SCL_VAL_STOP_PHASE2_DEFAULT  0x1
-#define GC_I2C_CTRL_SCL_VAL_STOP_PHASE2_OFFSET   0x14
-#define GC_I2C_CTRL_SCL_VAL_ERROR_SDA_CONFLICT_LSB 0x17
-#define GC_I2C_CTRL_SCL_VAL_ERROR_SDA_CONFLICT_MASK 0x800000
-#define GC_I2C_CTRL_SCL_VAL_ERROR_SDA_CONFLICT_SIZE 0x1
-#define GC_I2C_CTRL_SCL_VAL_ERROR_SDA_CONFLICT_DEFAULT 0x0
-#define GC_I2C_CTRL_SCL_VAL_ERROR_SDA_CONFLICT_OFFSET 0x14
-#define GC_I2C_CTRL_SCL_VAL_SCL0_PHASE0_LSB      0x18
-#define GC_I2C_CTRL_SCL_VAL_SCL0_PHASE0_MASK     0x1000000
-#define GC_I2C_CTRL_SCL_VAL_SCL0_PHASE0_SIZE     0x1
-#define GC_I2C_CTRL_SCL_VAL_SCL0_PHASE0_DEFAULT  0x0
-#define GC_I2C_CTRL_SCL_VAL_SCL0_PHASE0_OFFSET   0x14
-#define GC_I2C_CTRL_SCL_OVRD_HOLD0_PHASE0_LSB    0x0
-#define GC_I2C_CTRL_SCL_OVRD_HOLD0_PHASE0_MASK   0x1
-#define GC_I2C_CTRL_SCL_OVRD_HOLD0_PHASE0_SIZE   0x1
-#define GC_I2C_CTRL_SCL_OVRD_HOLD0_PHASE0_DEFAULT 0x0
-#define GC_I2C_CTRL_SCL_OVRD_HOLD0_PHASE0_OFFSET 0x18
-#define GC_I2C_CTRL_SCL_OVRD_READ_PHASE0_LSB     0x1
-#define GC_I2C_CTRL_SCL_OVRD_READ_PHASE0_MASK    0x2
-#define GC_I2C_CTRL_SCL_OVRD_READ_PHASE0_SIZE    0x1
-#define GC_I2C_CTRL_SCL_OVRD_READ_PHASE0_DEFAULT 0x0
-#define GC_I2C_CTRL_SCL_OVRD_READ_PHASE0_OFFSET  0x18
-#define GC_I2C_CTRL_SCL_OVRD_SCL0_PHASE0_LSB     0x2
-#define GC_I2C_CTRL_SCL_OVRD_SCL0_PHASE0_MASK    0x4
-#define GC_I2C_CTRL_SCL_OVRD_SCL0_PHASE0_SIZE    0x1
-#define GC_I2C_CTRL_SCL_OVRD_SCL0_PHASE0_DEFAULT 0x0
-#define GC_I2C_CTRL_SCL_OVRD_SCL0_PHASE0_OFFSET  0x18
-#define GC_I2C_CTRL_SCL_OVRD_START_PHASE0_LSB    0x3
-#define GC_I2C_CTRL_SCL_OVRD_START_PHASE0_MASK   0x8
-#define GC_I2C_CTRL_SCL_OVRD_START_PHASE0_SIZE   0x1
-#define GC_I2C_CTRL_SCL_OVRD_START_PHASE0_DEFAULT 0x0
-#define GC_I2C_CTRL_SCL_OVRD_START_PHASE0_OFFSET 0x18
-#define GC_I2C_CTRL_SCL_OVRD_STOP_PHASE0_LSB     0x4
-#define GC_I2C_CTRL_SCL_OVRD_STOP_PHASE0_MASK    0x10
-#define GC_I2C_CTRL_SCL_OVRD_STOP_PHASE0_SIZE    0x1
-#define GC_I2C_CTRL_SCL_OVRD_STOP_PHASE0_DEFAULT 0x0
-#define GC_I2C_CTRL_SCL_OVRD_STOP_PHASE0_OFFSET  0x18
-#define GC_I2C_CTRL_SCL_OVRD_WRITE0_PHASE0_LSB   0x5
-#define GC_I2C_CTRL_SCL_OVRD_WRITE0_PHASE0_MASK  0x20
-#define GC_I2C_CTRL_SCL_OVRD_WRITE0_PHASE0_SIZE  0x1
-#define GC_I2C_CTRL_SCL_OVRD_WRITE0_PHASE0_DEFAULT 0x0
-#define GC_I2C_CTRL_SCL_OVRD_WRITE0_PHASE0_OFFSET 0x18
-#define GC_I2C_CTRL_SCL_OVRD_WRITE1_PHASE0_LSB   0x6
-#define GC_I2C_CTRL_SCL_OVRD_WRITE1_PHASE0_MASK  0x40
-#define GC_I2C_CTRL_SCL_OVRD_WRITE1_PHASE0_SIZE  0x1
-#define GC_I2C_CTRL_SCL_OVRD_WRITE1_PHASE0_DEFAULT 0x0
-#define GC_I2C_CTRL_SCL_OVRD_WRITE1_PHASE0_OFFSET 0x18
-#define GC_I2C_CTRL_SCL_OVRD_FREE_BUS_PHASE0_LSB 0x7
-#define GC_I2C_CTRL_SCL_OVRD_FREE_BUS_PHASE0_MASK 0x80
-#define GC_I2C_CTRL_SCL_OVRD_FREE_BUS_PHASE0_SIZE 0x1
-#define GC_I2C_CTRL_SCL_OVRD_FREE_BUS_PHASE0_DEFAULT 0x0
-#define GC_I2C_CTRL_SCL_OVRD_FREE_BUS_PHASE0_OFFSET 0x18
-#define GC_I2C_CTRL_SCL_OVRD_FREE_BUS_PHASE1_LSB 0x8
-#define GC_I2C_CTRL_SCL_OVRD_FREE_BUS_PHASE1_MASK 0x100
-#define GC_I2C_CTRL_SCL_OVRD_FREE_BUS_PHASE1_SIZE 0x1
-#define GC_I2C_CTRL_SCL_OVRD_FREE_BUS_PHASE1_DEFAULT 0x0
-#define GC_I2C_CTRL_SCL_OVRD_FREE_BUS_PHASE1_OFFSET 0x18
-#define GC_I2C_CTRL_SCL_OVRD_FREE_BUS_PHASE2_LSB 0x9
-#define GC_I2C_CTRL_SCL_OVRD_FREE_BUS_PHASE2_MASK 0x200
-#define GC_I2C_CTRL_SCL_OVRD_FREE_BUS_PHASE2_SIZE 0x1
-#define GC_I2C_CTRL_SCL_OVRD_FREE_BUS_PHASE2_DEFAULT 0x1
-#define GC_I2C_CTRL_SCL_OVRD_FREE_BUS_PHASE2_OFFSET 0x18
-#define GC_I2C_CTRL_SCL_OVRD_ERROR_SDA_CONFLICT_LSB 0xa
-#define GC_I2C_CTRL_SCL_OVRD_ERROR_SDA_CONFLICT_MASK 0x400
-#define GC_I2C_CTRL_SCL_OVRD_ERROR_SDA_CONFLICT_SIZE 0x1
-#define GC_I2C_CTRL_SCL_OVRD_ERROR_SDA_CONFLICT_DEFAULT 0x1
-#define GC_I2C_CTRL_SCL_OVRD_ERROR_SDA_CONFLICT_OFFSET 0x18
-#define GC_I2C_CTRL_AL_EN_LSB                    0x0
-#define GC_I2C_CTRL_AL_EN_MASK                   0x1
-#define GC_I2C_CTRL_AL_EN_SIZE                   0x1
-#define GC_I2C_CTRL_AL_EN_DEFAULT                0x1
-#define GC_I2C_CTRL_AL_EN_OFFSET                 0x20
-#define GC_I2C_CTRL_AL_PHASEMASK_LSB             0x1
-#define GC_I2C_CTRL_AL_PHASEMASK_MASK            0x1e
-#define GC_I2C_CTRL_AL_PHASEMASK_SIZE            0x4
-#define GC_I2C_CTRL_AL_PHASEMASK_DEFAULT         0xf
-#define GC_I2C_CTRL_AL_PHASEMASK_OFFSET          0x20
-#define GC_I2C_CTRL_CS_EN_LSB                    0x0
-#define GC_I2C_CTRL_CS_EN_MASK                   0x1
-#define GC_I2C_CTRL_CS_EN_SIZE                   0x1
-#define GC_I2C_CTRL_CS_EN_DEFAULT                0x1
-#define GC_I2C_CTRL_CS_EN_OFFSET                 0x24
-#define GC_I2C_CTRL_CS_TIMEOUTEN_LSB             0x1
-#define GC_I2C_CTRL_CS_TIMEOUTEN_MASK            0x2
-#define GC_I2C_CTRL_CS_TIMEOUTEN_SIZE            0x1
-#define GC_I2C_CTRL_CS_TIMEOUTEN_DEFAULT         0x1
-#define GC_I2C_CTRL_CS_TIMEOUTEN_OFFSET          0x24
-#define GC_I2C_CTRL_CS_TIMEOUTVAL_LSB            0x2
-#define GC_I2C_CTRL_CS_TIMEOUTVAL_MASK           0x3ffffc
-#define GC_I2C_CTRL_CS_TIMEOUTVAL_SIZE           0x14
-#define GC_I2C_CTRL_CS_TIMEOUTVAL_DEFAULT        0x4e20
-#define GC_I2C_CTRL_CS_TIMEOUTVAL_OFFSET         0x24
-#define GC_I2C_INST_RESERVED0_LSB                0x0
-#define GC_I2C_INST_RESERVED0_MASK               0x1
-#define GC_I2C_INST_RESERVED0_SIZE               0x1
-#define GC_I2C_INST_RESERVED0_DEFAULT            0x0
-#define GC_I2C_INST_RESERVED0_OFFSET             0x28
-#define GC_I2C_INST_START_LSB                    0x1
-#define GC_I2C_INST_START_MASK                   0x2
-#define GC_I2C_INST_START_SIZE                   0x1
-#define GC_I2C_INST_START_DEFAULT                0x0
-#define GC_I2C_INST_START_OFFSET                 0x28
-#define GC_I2C_INST_FWDEVADDR_LSB                0x2
-#define GC_I2C_INST_FWDEVADDR_MASK               0x4
-#define GC_I2C_INST_FWDEVADDR_SIZE               0x1
-#define GC_I2C_INST_FWDEVADDR_DEFAULT            0x0
-#define GC_I2C_INST_FWDEVADDR_OFFSET             0x28
-#define GC_I2C_INST_FWBYTESCOUNT_LSB             0x3
-#define GC_I2C_INST_FWBYTESCOUNT_MASK            0x38
-#define GC_I2C_INST_FWBYTESCOUNT_SIZE            0x3
-#define GC_I2C_INST_FWBYTESCOUNT_DEFAULT         0x0
-#define GC_I2C_INST_FWBYTESCOUNT_OFFSET          0x28
-#define GC_I2C_INST_SCL0_LSB                     0x6
-#define GC_I2C_INST_SCL0_MASK                    0x40
-#define GC_I2C_INST_SCL0_SIZE                    0x1
-#define GC_I2C_INST_SCL0_DEFAULT                 0x0
-#define GC_I2C_INST_SCL0_OFFSET                  0x28
-#define GC_I2C_INST_FREE_BUS_LSB                 0x7
-#define GC_I2C_INST_FREE_BUS_MASK                0x80
-#define GC_I2C_INST_FREE_BUS_SIZE                0x1
-#define GC_I2C_INST_FREE_BUS_DEFAULT             0x0
-#define GC_I2C_INST_FREE_BUS_OFFSET              0x28
-#define GC_I2C_INST_FIRSTSTOP_LSB                0x8
-#define GC_I2C_INST_FIRSTSTOP_MASK               0x100
-#define GC_I2C_INST_FIRSTSTOP_SIZE               0x1
-#define GC_I2C_INST_FIRSTSTOP_DEFAULT            0x0
-#define GC_I2C_INST_FIRSTSTOP_OFFSET             0x28
-#define GC_I2C_INST_REPEATEDSTART_LSB            0x9
-#define GC_I2C_INST_REPEATEDSTART_MASK           0x200
-#define GC_I2C_INST_REPEATEDSTART_SIZE           0x1
-#define GC_I2C_INST_REPEATEDSTART_DEFAULT        0x0
-#define GC_I2C_INST_REPEATEDSTART_OFFSET         0x28
-#define GC_I2C_INST_RWDEVADDR_LSB                0xa
-#define GC_I2C_INST_RWDEVADDR_MASK               0x400
-#define GC_I2C_INST_RWDEVADDR_SIZE               0x1
-#define GC_I2C_INST_RWDEVADDR_DEFAULT            0x0
-#define GC_I2C_INST_RWDEVADDR_OFFSET             0x28
-#define GC_I2C_INST_RWDEVADDR_RWB_LSB            0xb
-#define GC_I2C_INST_RWDEVADDR_RWB_MASK           0x800
-#define GC_I2C_INST_RWDEVADDR_RWB_SIZE           0x1
-#define GC_I2C_INST_RWDEVADDR_RWB_DEFAULT        0x0
-#define GC_I2C_INST_RWDEVADDR_RWB_OFFSET         0x28
-#define GC_I2C_INST_RWBYTESCOUNT_LSB             0xc
-#define GC_I2C_INST_RWBYTESCOUNT_MASK            0x7f000
-#define GC_I2C_INST_RWBYTESCOUNT_SIZE            0x7
-#define GC_I2C_INST_RWBYTESCOUNT_DEFAULT         0x0
-#define GC_I2C_INST_RWBYTESCOUNT_OFFSET          0x28
-#define GC_I2C_INST_FINALNA_LSB                  0x13
-#define GC_I2C_INST_FINALNA_MASK                 0x80000
-#define GC_I2C_INST_FINALNA_SIZE                 0x1
-#define GC_I2C_INST_FINALNA_DEFAULT              0x0
-#define GC_I2C_INST_FINALNA_OFFSET               0x28
-#define GC_I2C_INST_RWBIT_LSB                    0x14
-#define GC_I2C_INST_RWBIT_MASK                   0x300000
-#define GC_I2C_INST_RWBIT_SIZE                   0x2
-#define GC_I2C_INST_RWBIT_DEFAULT                0x0
-#define GC_I2C_INST_RWBIT_OFFSET                 0x28
-#define GC_I2C_INST_HOLD0_LSB                    0x16
-#define GC_I2C_INST_HOLD0_MASK                   0x400000
-#define GC_I2C_INST_HOLD0_SIZE                   0x1
-#define GC_I2C_INST_HOLD0_DEFAULT                0x0
-#define GC_I2C_INST_HOLD0_OFFSET                 0x28
-#define GC_I2C_INST_FINALSTOP_LSB                0x17
-#define GC_I2C_INST_FINALSTOP_MASK               0x800000
-#define GC_I2C_INST_FINALSTOP_SIZE               0x1
-#define GC_I2C_INST_FINALSTOP_DEFAULT            0x0
-#define GC_I2C_INST_FINALSTOP_OFFSET             0x28
-#define GC_I2C_INST_RESETB_RWPTR_LSB             0x18
-#define GC_I2C_INST_RESETB_RWPTR_MASK            0x1000000
-#define GC_I2C_INST_RESETB_RWPTR_SIZE            0x1
-#define GC_I2C_INST_RESETB_RWPTR_DEFAULT         0x0
-#define GC_I2C_INST_RESETB_RWPTR_OFFSET          0x28
-#define GC_I2C_INST_DEVADDRVAL_LSB               0x19
-#define GC_I2C_INST_DEVADDRVAL_MASK              0xfe000000
-#define GC_I2C_INST_DEVADDRVAL_SIZE              0x7
-#define GC_I2C_INST_DEVADDRVAL_DEFAULT           0x0
-#define GC_I2C_INST_DEVADDRVAL_OFFSET            0x28
-#define GC_I2C_STATUS_RESERVED0_LSB              0x0
-#define GC_I2C_STATUS_RESERVED0_MASK             0x1
-#define GC_I2C_STATUS_RESERVED0_SIZE             0x1
-#define GC_I2C_STATUS_RESERVED0_DEFAULT          0x0
-#define GC_I2C_STATUS_RESERVED0_OFFSET           0x2c
-#define GC_I2C_STATUS_START_LSB                  0x1
-#define GC_I2C_STATUS_START_MASK                 0x2
-#define GC_I2C_STATUS_START_SIZE                 0x1
-#define GC_I2C_STATUS_START_DEFAULT              0x0
-#define GC_I2C_STATUS_START_OFFSET               0x2c
-#define GC_I2C_STATUS_FWDEVADDR_LSB              0x2
-#define GC_I2C_STATUS_FWDEVADDR_MASK             0x4
-#define GC_I2C_STATUS_FWDEVADDR_SIZE             0x1
-#define GC_I2C_STATUS_FWDEVADDR_DEFAULT          0x0
-#define GC_I2C_STATUS_FWDEVADDR_OFFSET           0x2c
-#define GC_I2C_STATUS_FWBYTESCOUNT_LSB           0x3
-#define GC_I2C_STATUS_FWBYTESCOUNT_MASK          0x38
-#define GC_I2C_STATUS_FWBYTESCOUNT_SIZE          0x3
-#define GC_I2C_STATUS_FWBYTESCOUNT_DEFAULT       0x0
-#define GC_I2C_STATUS_FWBYTESCOUNT_OFFSET        0x2c
-#define GC_I2C_STATUS_SCL0_LSB                   0x6
-#define GC_I2C_STATUS_SCL0_MASK                  0x40
-#define GC_I2C_STATUS_SCL0_SIZE                  0x1
-#define GC_I2C_STATUS_SCL0_DEFAULT               0x0
-#define GC_I2C_STATUS_SCL0_OFFSET                0x2c
-#define GC_I2C_STATUS_FREE_BUS_LSB               0x7
-#define GC_I2C_STATUS_FREE_BUS_MASK              0x80
-#define GC_I2C_STATUS_FREE_BUS_SIZE              0x1
-#define GC_I2C_STATUS_FREE_BUS_DEFAULT           0x0
-#define GC_I2C_STATUS_FREE_BUS_OFFSET            0x2c
-#define GC_I2C_STATUS_FIRSTSTOP_LSB              0x8
-#define GC_I2C_STATUS_FIRSTSTOP_MASK             0x100
-#define GC_I2C_STATUS_FIRSTSTOP_SIZE             0x1
-#define GC_I2C_STATUS_FIRSTSTOP_DEFAULT          0x0
-#define GC_I2C_STATUS_FIRSTSTOP_OFFSET           0x2c
-#define GC_I2C_STATUS_REPEATEDSTART_LSB          0x9
-#define GC_I2C_STATUS_REPEATEDSTART_MASK         0x200
-#define GC_I2C_STATUS_REPEATEDSTART_SIZE         0x1
-#define GC_I2C_STATUS_REPEATEDSTART_DEFAULT      0x0
-#define GC_I2C_STATUS_REPEATEDSTART_OFFSET       0x2c
-#define GC_I2C_STATUS_RWDEVADDR_LSB              0xa
-#define GC_I2C_STATUS_RWDEVADDR_MASK             0x400
-#define GC_I2C_STATUS_RWDEVADDR_SIZE             0x1
-#define GC_I2C_STATUS_RWDEVADDR_DEFAULT          0x0
-#define GC_I2C_STATUS_RWDEVADDR_OFFSET           0x2c
-#define GC_I2C_STATUS_RWDEVADDR_RWB_LSB          0xb
-#define GC_I2C_STATUS_RWDEVADDR_RWB_MASK         0x800
-#define GC_I2C_STATUS_RWDEVADDR_RWB_SIZE         0x1
-#define GC_I2C_STATUS_RWDEVADDR_RWB_DEFAULT      0x0
-#define GC_I2C_STATUS_RWDEVADDR_RWB_OFFSET       0x2c
-#define GC_I2C_STATUS_RWBYTESCOUNT_LSB           0xc
-#define GC_I2C_STATUS_RWBYTESCOUNT_MASK          0x7f000
-#define GC_I2C_STATUS_RWBYTESCOUNT_SIZE          0x7
-#define GC_I2C_STATUS_RWBYTESCOUNT_DEFAULT       0x0
-#define GC_I2C_STATUS_RWBYTESCOUNT_OFFSET        0x2c
-#define GC_I2C_STATUS_FINALNA_LSB                0x13
-#define GC_I2C_STATUS_FINALNA_MASK               0x80000
-#define GC_I2C_STATUS_FINALNA_SIZE               0x1
-#define GC_I2C_STATUS_FINALNA_DEFAULT            0x0
-#define GC_I2C_STATUS_FINALNA_OFFSET             0x2c
-#define GC_I2C_STATUS_RWBIT_LSB                  0x14
-#define GC_I2C_STATUS_RWBIT_MASK                 0x300000
-#define GC_I2C_STATUS_RWBIT_SIZE                 0x2
-#define GC_I2C_STATUS_RWBIT_DEFAULT              0x0
-#define GC_I2C_STATUS_RWBIT_OFFSET               0x2c
-#define GC_I2C_STATUS_HOLD0_LSB                  0x16
-#define GC_I2C_STATUS_HOLD0_MASK                 0x400000
-#define GC_I2C_STATUS_HOLD0_SIZE                 0x1
-#define GC_I2C_STATUS_HOLD0_DEFAULT              0x0
-#define GC_I2C_STATUS_HOLD0_OFFSET               0x2c
-#define GC_I2C_STATUS_FINALSTOP_LSB              0x17
-#define GC_I2C_STATUS_FINALSTOP_MASK             0x800000
-#define GC_I2C_STATUS_FINALSTOP_SIZE             0x1
-#define GC_I2C_STATUS_FINALSTOP_DEFAULT          0x0
-#define GC_I2C_STATUS_FINALSTOP_OFFSET           0x2c
-#define GC_I2C_STATUS_INTB_LSB                   0x18
-#define GC_I2C_STATUS_INTB_MASK                  0x1000000
-#define GC_I2C_STATUS_INTB_SIZE                  0x1
-#define GC_I2C_STATUS_INTB_DEFAULT               0x0
-#define GC_I2C_STATUS_INTB_OFFSET                0x2c
-#define GC_I2C_STATUS_CA_NACK_LSB                0x19
-#define GC_I2C_STATUS_CA_NACK_MASK               0x2000000
-#define GC_I2C_STATUS_CA_NACK_SIZE               0x1
-#define GC_I2C_STATUS_CA_NACK_DEFAULT            0x0
-#define GC_I2C_STATUS_CA_NACK_OFFSET             0x2c
-#define GC_I2C_STATUS_AL_LSB                     0x1a
-#define GC_I2C_STATUS_AL_MASK                    0x4000000
-#define GC_I2C_STATUS_AL_SIZE                    0x1
-#define GC_I2C_STATUS_AL_DEFAULT                 0x0
-#define GC_I2C_STATUS_AL_OFFSET                  0x2c
-#define GC_I2C_STATUS_ALBITPTR_LSB               0x1b
-#define GC_I2C_STATUS_ALBITPTR_MASK              0x78000000
-#define GC_I2C_STATUS_ALBITPTR_SIZE              0x4
-#define GC_I2C_STATUS_ALBITPTR_DEFAULT           0x0
-#define GC_I2C_STATUS_ALBITPTR_OFFSET            0x2c
-#define GC_I2C_STATUS_CSTIMEOUT_LSB              0x1f
-#define GC_I2C_STATUS_CSTIMEOUT_MASK             0x80000000
-#define GC_I2C_STATUS_CSTIMEOUT_SIZE             0x1
-#define GC_I2C_STATUS_CSTIMEOUT_DEFAULT          0x0
-#define GC_I2C_STATUS_CSTIMEOUT_OFFSET           0x2c
-#define GC_I2C_READVAL_SDA_LSB                   0x0
-#define GC_I2C_READVAL_SDA_MASK                  0x1
-#define GC_I2C_READVAL_SDA_SIZE                  0x1
-#define GC_I2C_READVAL_SDA_DEFAULT               0x0
-#define GC_I2C_READVAL_SDA_OFFSET                0x78
-#define GC_I2C_READVAL_SCL_LSB                   0x1
-#define GC_I2C_READVAL_SCL_MASK                  0x2
-#define GC_I2C_READVAL_SCL_SIZE                  0x1
-#define GC_I2C_READVAL_SCL_DEFAULT               0x0
-#define GC_I2C_READVAL_SCL_OFFSET                0x78
-#define GC_I2C_CTRL_MSR_SDA_LSB                  0x0
-#define GC_I2C_CTRL_MSR_SDA_MASK                 0x3
-#define GC_I2C_CTRL_MSR_SDA_SIZE                 0x2
-#define GC_I2C_CTRL_MSR_SDA_DEFAULT              0x2
-#define GC_I2C_CTRL_MSR_SDA_OFFSET               0x7c
-#define GC_I2C_CTRL_MSR_SCL_LSB                  0x2
-#define GC_I2C_CTRL_MSR_SCL_MASK                 0xc
-#define GC_I2C_CTRL_MSR_SCL_SIZE                 0x2
-#define GC_I2C_CTRL_MSR_SCL_DEFAULT              0x2
-#define GC_I2C_CTRL_MSR_SCL_OFFSET               0x7c
-#define GC_I2CS_VERSION_CHANGE_LSB               0x0
-#define GC_I2CS_VERSION_CHANGE_MASK              0xffffff
-#define GC_I2CS_VERSION_CHANGE_SIZE              0x18
-#define GC_I2CS_VERSION_CHANGE_DEFAULT           0x1424a
-#define GC_I2CS_VERSION_CHANGE_OFFSET            0x0
-#define GC_I2CS_VERSION_REVISION_LSB             0x18
-#define GC_I2CS_VERSION_REVISION_MASK            0xff000000
-#define GC_I2CS_VERSION_REVISION_SIZE            0x8
-#define GC_I2CS_VERSION_REVISION_DEFAULT         0x1
-#define GC_I2CS_VERSION_REVISION_OFFSET          0x0
-#define GC_I2CS_INT_ENABLE_INTR_READ_BEGIN_LSB   0x0
-#define GC_I2CS_INT_ENABLE_INTR_READ_BEGIN_MASK  0x1
-#define GC_I2CS_INT_ENABLE_INTR_READ_BEGIN_SIZE  0x1
-#define GC_I2CS_INT_ENABLE_INTR_READ_BEGIN_DEFAULT 0x0
-#define GC_I2CS_INT_ENABLE_INTR_READ_BEGIN_OFFSET 0x4
-#define GC_I2CS_INT_ENABLE_INTR_READ_COMPLETE_LSB 0x1
-#define GC_I2CS_INT_ENABLE_INTR_READ_COMPLETE_MASK 0x2
-#define GC_I2CS_INT_ENABLE_INTR_READ_COMPLETE_SIZE 0x1
-#define GC_I2CS_INT_ENABLE_INTR_READ_COMPLETE_DEFAULT 0x0
-#define GC_I2CS_INT_ENABLE_INTR_READ_COMPLETE_OFFSET 0x4
-#define GC_I2CS_INT_ENABLE_INTR_WRITE_COMPLETE_LSB 0x2
-#define GC_I2CS_INT_ENABLE_INTR_WRITE_COMPLETE_MASK 0x4
-#define GC_I2CS_INT_ENABLE_INTR_WRITE_COMPLETE_SIZE 0x1
-#define GC_I2CS_INT_ENABLE_INTR_WRITE_COMPLETE_DEFAULT 0x0
-#define GC_I2CS_INT_ENABLE_INTR_WRITE_COMPLETE_OFFSET 0x4
-#define GC_I2CS_INT_STATE_INTR_READ_BEGIN_LSB    0x0
-#define GC_I2CS_INT_STATE_INTR_READ_BEGIN_MASK   0x1
-#define GC_I2CS_INT_STATE_INTR_READ_BEGIN_SIZE   0x1
-#define GC_I2CS_INT_STATE_INTR_READ_BEGIN_DEFAULT 0x0
-#define GC_I2CS_INT_STATE_INTR_READ_BEGIN_OFFSET 0x8
-#define GC_I2CS_INT_STATE_INTR_READ_COMPLETE_LSB 0x1
-#define GC_I2CS_INT_STATE_INTR_READ_COMPLETE_MASK 0x2
-#define GC_I2CS_INT_STATE_INTR_READ_COMPLETE_SIZE 0x1
-#define GC_I2CS_INT_STATE_INTR_READ_COMPLETE_DEFAULT 0x0
-#define GC_I2CS_INT_STATE_INTR_READ_COMPLETE_OFFSET 0x8
-#define GC_I2CS_INT_STATE_INTR_WRITE_COMPLETE_LSB 0x2
-#define GC_I2CS_INT_STATE_INTR_WRITE_COMPLETE_MASK 0x4
-#define GC_I2CS_INT_STATE_INTR_WRITE_COMPLETE_SIZE 0x1
-#define GC_I2CS_INT_STATE_INTR_WRITE_COMPLETE_DEFAULT 0x0
-#define GC_I2CS_INT_STATE_INTR_WRITE_COMPLETE_OFFSET 0x8
-#define GC_I2CS_INT_TEST_INTR_READ_BEGIN_LSB     0x0
-#define GC_I2CS_INT_TEST_INTR_READ_BEGIN_MASK    0x1
-#define GC_I2CS_INT_TEST_INTR_READ_BEGIN_SIZE    0x1
-#define GC_I2CS_INT_TEST_INTR_READ_BEGIN_DEFAULT 0x0
-#define GC_I2CS_INT_TEST_INTR_READ_BEGIN_OFFSET  0xc
-#define GC_I2CS_INT_TEST_INTR_READ_COMPLETE_LSB  0x1
-#define GC_I2CS_INT_TEST_INTR_READ_COMPLETE_MASK 0x2
-#define GC_I2CS_INT_TEST_INTR_READ_COMPLETE_SIZE 0x1
-#define GC_I2CS_INT_TEST_INTR_READ_COMPLETE_DEFAULT 0x0
-#define GC_I2CS_INT_TEST_INTR_READ_COMPLETE_OFFSET 0xc
-#define GC_I2CS_INT_TEST_INTR_WRITE_COMPLETE_LSB 0x2
-#define GC_I2CS_INT_TEST_INTR_WRITE_COMPLETE_MASK 0x4
-#define GC_I2CS_INT_TEST_INTR_WRITE_COMPLETE_SIZE 0x1
-#define GC_I2CS_INT_TEST_INTR_WRITE_COMPLETE_DEFAULT 0x0
-#define GC_I2CS_INT_TEST_INTR_WRITE_COMPLETE_OFFSET 0xc
-#define GC_I2CS_CTRL_SDA_VAL_FREE_BUS_S_LSB      0x0
-#define GC_I2CS_CTRL_SDA_VAL_FREE_BUS_S_MASK     0x1
-#define GC_I2CS_CTRL_SDA_VAL_FREE_BUS_S_SIZE     0x1
-#define GC_I2CS_CTRL_SDA_VAL_FREE_BUS_S_DEFAULT  0x1
-#define GC_I2CS_CTRL_SDA_VAL_FREE_BUS_S_OFFSET   0x10
-#define GC_I2CS_CTRL_SDA_VAL_READ0_S_LSB         0x1
-#define GC_I2CS_CTRL_SDA_VAL_READ0_S_MASK        0x2
-#define GC_I2CS_CTRL_SDA_VAL_READ0_S_SIZE        0x1
-#define GC_I2CS_CTRL_SDA_VAL_READ0_S_DEFAULT     0x0
-#define GC_I2CS_CTRL_SDA_VAL_READ0_S_OFFSET      0x10
-#define GC_I2CS_CTRL_SDA_VAL_READ1_S_LSB         0x2
-#define GC_I2CS_CTRL_SDA_VAL_READ1_S_MASK        0x4
-#define GC_I2CS_CTRL_SDA_VAL_READ1_S_SIZE        0x1
-#define GC_I2CS_CTRL_SDA_VAL_READ1_S_DEFAULT     0x1
-#define GC_I2CS_CTRL_SDA_VAL_READ1_S_OFFSET      0x10
-#define GC_I2CS_CTRL_SDA_VAL_WRITE_S_LSB         0x3
-#define GC_I2CS_CTRL_SDA_VAL_WRITE_S_MASK        0x8
-#define GC_I2CS_CTRL_SDA_VAL_WRITE_S_SIZE        0x1
-#define GC_I2CS_CTRL_SDA_VAL_WRITE_S_DEFAULT     0x1
-#define GC_I2CS_CTRL_SDA_VAL_WRITE_S_OFFSET      0x10
-#define GC_I2CS_CTRL_SDA_VAL_START_S_LSB         0x4
-#define GC_I2CS_CTRL_SDA_VAL_START_S_MASK        0x10
-#define GC_I2CS_CTRL_SDA_VAL_START_S_SIZE        0x1
-#define GC_I2CS_CTRL_SDA_VAL_START_S_DEFAULT     0x1
-#define GC_I2CS_CTRL_SDA_VAL_START_S_OFFSET      0x10
-#define GC_I2CS_CTRL_SDA_VAL_STOP_S_LSB          0x5
-#define GC_I2CS_CTRL_SDA_VAL_STOP_S_MASK         0x20
-#define GC_I2CS_CTRL_SDA_VAL_STOP_S_SIZE         0x1
-#define GC_I2CS_CTRL_SDA_VAL_STOP_S_DEFAULT      0x1
-#define GC_I2CS_CTRL_SDA_VAL_STOP_S_OFFSET       0x10
-#define GC_I2CS_READVAL_SDA_LSB                  0x0
-#define GC_I2CS_READVAL_SDA_MASK                 0x1
-#define GC_I2CS_READVAL_SDA_SIZE                 0x1
-#define GC_I2CS_READVAL_SDA_DEFAULT              0x0
-#define GC_I2CS_READVAL_SDA_OFFSET               0x2c
-#define GC_I2CS_READVAL_SCL_LSB                  0x1
-#define GC_I2CS_READVAL_SCL_MASK                 0x2
-#define GC_I2CS_READVAL_SCL_SIZE                 0x1
-#define GC_I2CS_READVAL_SCL_DEFAULT              0x0
-#define GC_I2CS_READVAL_SCL_OFFSET               0x2c
-#define GC_I2CS_CTRL_MSR_SDA_LSB                 0x0
-#define GC_I2CS_CTRL_MSR_SDA_MASK                0x3
-#define GC_I2CS_CTRL_MSR_SDA_SIZE                0x2
-#define GC_I2CS_CTRL_MSR_SDA_DEFAULT             0x2
-#define GC_I2CS_CTRL_MSR_SDA_OFFSET              0x30
-#define GC_I2CS_CTRL_MSR_SCL_LSB                 0x2
-#define GC_I2CS_CTRL_MSR_SCL_MASK                0xc
-#define GC_I2CS_CTRL_MSR_SCL_SIZE                0x2
-#define GC_I2CS_CTRL_MSR_SCL_DEFAULT             0x2
-#define GC_I2CS_CTRL_MSR_SCL_OFFSET              0x30
-#define GC_KEYMGR_AES_CTRL_RESET_LSB             0x0
-#define GC_KEYMGR_AES_CTRL_RESET_MASK            0x1
-#define GC_KEYMGR_AES_CTRL_RESET_SIZE            0x1
-#define GC_KEYMGR_AES_CTRL_RESET_DEFAULT         0x0
-#define GC_KEYMGR_AES_CTRL_RESET_OFFSET          0x0
-#define GC_KEYMGR_AES_CTRL_KEYSIZE_LSB           0x1
-#define GC_KEYMGR_AES_CTRL_KEYSIZE_MASK          0x6
-#define GC_KEYMGR_AES_CTRL_KEYSIZE_SIZE          0x2
-#define GC_KEYMGR_AES_CTRL_KEYSIZE_DEFAULT       0x0
-#define GC_KEYMGR_AES_CTRL_KEYSIZE_OFFSET        0x0
-#define GC_KEYMGR_AES_CTRL_CIPHER_MODE_LSB       0x3
-#define GC_KEYMGR_AES_CTRL_CIPHER_MODE_MASK      0x18
-#define GC_KEYMGR_AES_CTRL_CIPHER_MODE_SIZE      0x2
-#define GC_KEYMGR_AES_CTRL_CIPHER_MODE_DEFAULT   0x0
-#define GC_KEYMGR_AES_CTRL_CIPHER_MODE_OFFSET    0x0
-#define GC_KEYMGR_AES_CTRL_ENC_MODE_LSB          0x5
-#define GC_KEYMGR_AES_CTRL_ENC_MODE_MASK         0x20
-#define GC_KEYMGR_AES_CTRL_ENC_MODE_SIZE         0x1
-#define GC_KEYMGR_AES_CTRL_ENC_MODE_DEFAULT      0x0
-#define GC_KEYMGR_AES_CTRL_ENC_MODE_OFFSET       0x0
-#define GC_KEYMGR_AES_CTRL_CTR_ENDIAN_LSB        0x6
-#define GC_KEYMGR_AES_CTRL_CTR_ENDIAN_MASK       0x40
-#define GC_KEYMGR_AES_CTRL_CTR_ENDIAN_SIZE       0x1
-#define GC_KEYMGR_AES_CTRL_CTR_ENDIAN_DEFAULT    0x0
-#define GC_KEYMGR_AES_CTRL_CTR_ENDIAN_OFFSET     0x0
-#define GC_KEYMGR_AES_CTRL_ENABLE_LSB            0x7
-#define GC_KEYMGR_AES_CTRL_ENABLE_MASK           0x80
-#define GC_KEYMGR_AES_CTRL_ENABLE_SIZE           0x1
-#define GC_KEYMGR_AES_CTRL_ENABLE_DEFAULT        0x0
-#define GC_KEYMGR_AES_CTRL_ENABLE_OFFSET         0x0
-#define GC_KEYMGR_AES_RAND_STALL_CTL_STALL_EN_LSB 0x0
-#define GC_KEYMGR_AES_RAND_STALL_CTL_STALL_EN_MASK 0x1
-#define GC_KEYMGR_AES_RAND_STALL_CTL_STALL_EN_SIZE 0x1
-#define GC_KEYMGR_AES_RAND_STALL_CTL_STALL_EN_DEFAULT 0x1
-#define GC_KEYMGR_AES_RAND_STALL_CTL_STALL_EN_OFFSET 0x60
-#define GC_KEYMGR_AES_RAND_STALL_CTL_FREQ_LSB    0x1
-#define GC_KEYMGR_AES_RAND_STALL_CTL_FREQ_MASK   0x6
-#define GC_KEYMGR_AES_RAND_STALL_CTL_FREQ_SIZE   0x2
-#define GC_KEYMGR_AES_RAND_STALL_CTL_FREQ_DEFAULT 0x3
-#define GC_KEYMGR_AES_RAND_STALL_CTL_FREQ_OFFSET 0x60
-#define GC_KEYMGR_AES_INT_ENABLE_AES_WFIFO_OVERFLOW_LSB 0x0
-#define GC_KEYMGR_AES_INT_ENABLE_AES_WFIFO_OVERFLOW_MASK 0x1
-#define GC_KEYMGR_AES_INT_ENABLE_AES_WFIFO_OVERFLOW_SIZE 0x1
-#define GC_KEYMGR_AES_INT_ENABLE_AES_WFIFO_OVERFLOW_DEFAULT 0x0
-#define GC_KEYMGR_AES_INT_ENABLE_AES_WFIFO_OVERFLOW_OFFSET 0xb4
-#define GC_KEYMGR_AES_INT_ENABLE_AES_RFIFO_OVERFLOW_LSB 0x1
-#define GC_KEYMGR_AES_INT_ENABLE_AES_RFIFO_OVERFLOW_MASK 0x2
-#define GC_KEYMGR_AES_INT_ENABLE_AES_RFIFO_OVERFLOW_SIZE 0x1
-#define GC_KEYMGR_AES_INT_ENABLE_AES_RFIFO_OVERFLOW_DEFAULT 0x0
-#define GC_KEYMGR_AES_INT_ENABLE_AES_RFIFO_OVERFLOW_OFFSET 0xb4
-#define GC_KEYMGR_AES_INT_ENABLE_AES_RFIFO_UNDERFLOW_LSB 0x2
-#define GC_KEYMGR_AES_INT_ENABLE_AES_RFIFO_UNDERFLOW_MASK 0x4
-#define GC_KEYMGR_AES_INT_ENABLE_AES_RFIFO_UNDERFLOW_SIZE 0x1
-#define GC_KEYMGR_AES_INT_ENABLE_AES_RFIFO_UNDERFLOW_DEFAULT 0x0
-#define GC_KEYMGR_AES_INT_ENABLE_AES_RFIFO_UNDERFLOW_OFFSET 0xb4
-#define GC_KEYMGR_AES_INT_ENABLE_AES_DONE_CIPHER_LSB 0x3
-#define GC_KEYMGR_AES_INT_ENABLE_AES_DONE_CIPHER_MASK 0x8
-#define GC_KEYMGR_AES_INT_ENABLE_AES_DONE_CIPHER_SIZE 0x1
-#define GC_KEYMGR_AES_INT_ENABLE_AES_DONE_CIPHER_DEFAULT 0x0
-#define GC_KEYMGR_AES_INT_ENABLE_AES_DONE_CIPHER_OFFSET 0xb4
-#define GC_KEYMGR_AES_INT_ENABLE_AES_DONE_KEYEXPANSION_LSB 0x4
-#define GC_KEYMGR_AES_INT_ENABLE_AES_DONE_KEYEXPANSION_MASK 0x10
-#define GC_KEYMGR_AES_INT_ENABLE_AES_DONE_KEYEXPANSION_SIZE 0x1
-#define GC_KEYMGR_AES_INT_ENABLE_AES_DONE_KEYEXPANSION_DEFAULT 0x0
-#define GC_KEYMGR_AES_INT_ENABLE_AES_DONE_KEYEXPANSION_OFFSET 0xb4
-#define GC_KEYMGR_AES_INT_ENABLE_AES_DONE_WIPE_SECRETS_LSB 0x5
-#define GC_KEYMGR_AES_INT_ENABLE_AES_DONE_WIPE_SECRETS_MASK 0x20
-#define GC_KEYMGR_AES_INT_ENABLE_AES_DONE_WIPE_SECRETS_SIZE 0x1
-#define GC_KEYMGR_AES_INT_ENABLE_AES_DONE_WIPE_SECRETS_DEFAULT 0x0
-#define GC_KEYMGR_AES_INT_ENABLE_AES_DONE_WIPE_SECRETS_OFFSET 0xb4
-#define GC_KEYMGR_AES_INT_STATE_AES_WFIFO_OVERFLOW_LSB 0x0
-#define GC_KEYMGR_AES_INT_STATE_AES_WFIFO_OVERFLOW_MASK 0x1
-#define GC_KEYMGR_AES_INT_STATE_AES_WFIFO_OVERFLOW_SIZE 0x1
-#define GC_KEYMGR_AES_INT_STATE_AES_WFIFO_OVERFLOW_DEFAULT 0x0
-#define GC_KEYMGR_AES_INT_STATE_AES_WFIFO_OVERFLOW_OFFSET 0xb8
-#define GC_KEYMGR_AES_INT_STATE_AES_RFIFO_OVERFLOW_LSB 0x1
-#define GC_KEYMGR_AES_INT_STATE_AES_RFIFO_OVERFLOW_MASK 0x2
-#define GC_KEYMGR_AES_INT_STATE_AES_RFIFO_OVERFLOW_SIZE 0x1
-#define GC_KEYMGR_AES_INT_STATE_AES_RFIFO_OVERFLOW_DEFAULT 0x0
-#define GC_KEYMGR_AES_INT_STATE_AES_RFIFO_OVERFLOW_OFFSET 0xb8
-#define GC_KEYMGR_AES_INT_STATE_AES_RFIFO_UNDERFLOW_LSB 0x2
-#define GC_KEYMGR_AES_INT_STATE_AES_RFIFO_UNDERFLOW_MASK 0x4
-#define GC_KEYMGR_AES_INT_STATE_AES_RFIFO_UNDERFLOW_SIZE 0x1
-#define GC_KEYMGR_AES_INT_STATE_AES_RFIFO_UNDERFLOW_DEFAULT 0x0
-#define GC_KEYMGR_AES_INT_STATE_AES_RFIFO_UNDERFLOW_OFFSET 0xb8
-#define GC_KEYMGR_AES_INT_STATE_AES_DONE_CIPHER_LSB 0x3
-#define GC_KEYMGR_AES_INT_STATE_AES_DONE_CIPHER_MASK 0x8
-#define GC_KEYMGR_AES_INT_STATE_AES_DONE_CIPHER_SIZE 0x1
-#define GC_KEYMGR_AES_INT_STATE_AES_DONE_CIPHER_DEFAULT 0x0
-#define GC_KEYMGR_AES_INT_STATE_AES_DONE_CIPHER_OFFSET 0xb8
-#define GC_KEYMGR_AES_INT_STATE_AES_DONE_KEYEXPANSION_LSB 0x4
-#define GC_KEYMGR_AES_INT_STATE_AES_DONE_KEYEXPANSION_MASK 0x10
-#define GC_KEYMGR_AES_INT_STATE_AES_DONE_KEYEXPANSION_SIZE 0x1
-#define GC_KEYMGR_AES_INT_STATE_AES_DONE_KEYEXPANSION_DEFAULT 0x0
-#define GC_KEYMGR_AES_INT_STATE_AES_DONE_KEYEXPANSION_OFFSET 0xb8
-#define GC_KEYMGR_AES_INT_STATE_AES_DONE_WIPE_SECRETS_LSB 0x5
-#define GC_KEYMGR_AES_INT_STATE_AES_DONE_WIPE_SECRETS_MASK 0x20
-#define GC_KEYMGR_AES_INT_STATE_AES_DONE_WIPE_SECRETS_SIZE 0x1
-#define GC_KEYMGR_AES_INT_STATE_AES_DONE_WIPE_SECRETS_DEFAULT 0x0
-#define GC_KEYMGR_AES_INT_STATE_AES_DONE_WIPE_SECRETS_OFFSET 0xb8
-#define GC_KEYMGR_AES_INT_TEST_AES_WFIFO_OVERFLOW_LSB 0x0
-#define GC_KEYMGR_AES_INT_TEST_AES_WFIFO_OVERFLOW_MASK 0x1
-#define GC_KEYMGR_AES_INT_TEST_AES_WFIFO_OVERFLOW_SIZE 0x1
-#define GC_KEYMGR_AES_INT_TEST_AES_WFIFO_OVERFLOW_DEFAULT 0x0
-#define GC_KEYMGR_AES_INT_TEST_AES_WFIFO_OVERFLOW_OFFSET 0xbc
-#define GC_KEYMGR_AES_INT_TEST_AES_RFIFO_OVERFLOW_LSB 0x1
-#define GC_KEYMGR_AES_INT_TEST_AES_RFIFO_OVERFLOW_MASK 0x2
-#define GC_KEYMGR_AES_INT_TEST_AES_RFIFO_OVERFLOW_SIZE 0x1
-#define GC_KEYMGR_AES_INT_TEST_AES_RFIFO_OVERFLOW_DEFAULT 0x0
-#define GC_KEYMGR_AES_INT_TEST_AES_RFIFO_OVERFLOW_OFFSET 0xbc
-#define GC_KEYMGR_AES_INT_TEST_AES_RFIFO_UNDERFLOW_LSB 0x2
-#define GC_KEYMGR_AES_INT_TEST_AES_RFIFO_UNDERFLOW_MASK 0x4
-#define GC_KEYMGR_AES_INT_TEST_AES_RFIFO_UNDERFLOW_SIZE 0x1
-#define GC_KEYMGR_AES_INT_TEST_AES_RFIFO_UNDERFLOW_DEFAULT 0x0
-#define GC_KEYMGR_AES_INT_TEST_AES_RFIFO_UNDERFLOW_OFFSET 0xbc
-#define GC_KEYMGR_AES_INT_TEST_AES_DONE_CIPHER_LSB 0x3
-#define GC_KEYMGR_AES_INT_TEST_AES_DONE_CIPHER_MASK 0x8
-#define GC_KEYMGR_AES_INT_TEST_AES_DONE_CIPHER_SIZE 0x1
-#define GC_KEYMGR_AES_INT_TEST_AES_DONE_CIPHER_DEFAULT 0x0
-#define GC_KEYMGR_AES_INT_TEST_AES_DONE_CIPHER_OFFSET 0xbc
-#define GC_KEYMGR_AES_INT_TEST_AES_DONE_KEYEXPANSION_LSB 0x4
-#define GC_KEYMGR_AES_INT_TEST_AES_DONE_KEYEXPANSION_MASK 0x10
-#define GC_KEYMGR_AES_INT_TEST_AES_DONE_KEYEXPANSION_SIZE 0x1
-#define GC_KEYMGR_AES_INT_TEST_AES_DONE_KEYEXPANSION_DEFAULT 0x0
-#define GC_KEYMGR_AES_INT_TEST_AES_DONE_KEYEXPANSION_OFFSET 0xbc
-#define GC_KEYMGR_AES_INT_TEST_AES_DONE_WIPE_SECRETS_LSB 0x5
-#define GC_KEYMGR_AES_INT_TEST_AES_DONE_WIPE_SECRETS_MASK 0x20
-#define GC_KEYMGR_AES_INT_TEST_AES_DONE_WIPE_SECRETS_SIZE 0x1
-#define GC_KEYMGR_AES_INT_TEST_AES_DONE_WIPE_SECRETS_DEFAULT 0x0
-#define GC_KEYMGR_AES_INT_TEST_AES_DONE_WIPE_SECRETS_OFFSET 0xbc
-#define GC_KEYMGR_AES_USE_HIDDEN_KEY_INDEX_LSB   0x0
-#define GC_KEYMGR_AES_USE_HIDDEN_KEY_INDEX_MASK  0x3ff
-#define GC_KEYMGR_AES_USE_HIDDEN_KEY_INDEX_SIZE  0xa
-#define GC_KEYMGR_AES_USE_HIDDEN_KEY_INDEX_DEFAULT 0x0
-#define GC_KEYMGR_AES_USE_HIDDEN_KEY_INDEX_OFFSET 0xc0
-#define GC_KEYMGR_AES_USE_HIDDEN_KEY_ENABLE_LSB  0xa
-#define GC_KEYMGR_AES_USE_HIDDEN_KEY_ENABLE_MASK 0x400
-#define GC_KEYMGR_AES_USE_HIDDEN_KEY_ENABLE_SIZE 0x1
-#define GC_KEYMGR_AES_USE_HIDDEN_KEY_ENABLE_DEFAULT 0x0
-#define GC_KEYMGR_AES_USE_HIDDEN_KEY_ENABLE_OFFSET 0xc0
-#define GC_KEYMGR_INT_ENABLE_SHA_WFIFO_FULL_LSB  0x0
-#define GC_KEYMGR_INT_ENABLE_SHA_WFIFO_FULL_MASK 0x1
-#define GC_KEYMGR_INT_ENABLE_SHA_WFIFO_FULL_SIZE 0x1
-#define GC_KEYMGR_INT_ENABLE_SHA_WFIFO_FULL_DEFAULT 0x0
-#define GC_KEYMGR_INT_ENABLE_SHA_WFIFO_FULL_OFFSET 0xc4
-#define GC_KEYMGR_INT_STATE_SHA_WFIFO_FULL_LSB   0x0
-#define GC_KEYMGR_INT_STATE_SHA_WFIFO_FULL_MASK  0x1
-#define GC_KEYMGR_INT_STATE_SHA_WFIFO_FULL_SIZE  0x1
-#define GC_KEYMGR_INT_STATE_SHA_WFIFO_FULL_DEFAULT 0x0
-#define GC_KEYMGR_INT_STATE_SHA_WFIFO_FULL_OFFSET 0xc8
-#define GC_KEYMGR_INT_TEST_SHA_WFIFO_FULL_LSB    0x0
-#define GC_KEYMGR_INT_TEST_SHA_WFIFO_FULL_MASK   0x1
-#define GC_KEYMGR_INT_TEST_SHA_WFIFO_FULL_SIZE   0x1
-#define GC_KEYMGR_INT_TEST_SHA_WFIFO_FULL_DEFAULT 0x0
-#define GC_KEYMGR_INT_TEST_SHA_WFIFO_FULL_OFFSET 0xcc
-#define GC_KEYMGR_SHA_CFG_EN_BIG_ENDIAN_LSB      0x0
-#define GC_KEYMGR_SHA_CFG_EN_BIG_ENDIAN_MASK     0x1
-#define GC_KEYMGR_SHA_CFG_EN_BIG_ENDIAN_SIZE     0x1
-#define GC_KEYMGR_SHA_CFG_EN_BIG_ENDIAN_DEFAULT  0x1
-#define GC_KEYMGR_SHA_CFG_EN_BIG_ENDIAN_OFFSET   0x408
-#define GC_KEYMGR_SHA_CFG_EN_SHA1_LSB            0x1
-#define GC_KEYMGR_SHA_CFG_EN_SHA1_MASK           0x2
-#define GC_KEYMGR_SHA_CFG_EN_SHA1_SIZE           0x1
-#define GC_KEYMGR_SHA_CFG_EN_SHA1_DEFAULT        0x0
-#define GC_KEYMGR_SHA_CFG_EN_SHA1_OFFSET         0x408
-#define GC_KEYMGR_SHA_CFG_EN_BUS_ERROR_LSB       0x3
-#define GC_KEYMGR_SHA_CFG_EN_BUS_ERROR_MASK      0x8
-#define GC_KEYMGR_SHA_CFG_EN_BUS_ERROR_SIZE      0x1
-#define GC_KEYMGR_SHA_CFG_EN_BUS_ERROR_DEFAULT   0x0
-#define GC_KEYMGR_SHA_CFG_EN_BUS_ERROR_OFFSET    0x408
-#define GC_KEYMGR_SHA_CFG_EN_LIVESTREAM_LSB      0x4
-#define GC_KEYMGR_SHA_CFG_EN_LIVESTREAM_MASK     0x10
-#define GC_KEYMGR_SHA_CFG_EN_LIVESTREAM_SIZE     0x1
-#define GC_KEYMGR_SHA_CFG_EN_LIVESTREAM_DEFAULT  0x0
-#define GC_KEYMGR_SHA_CFG_EN_LIVESTREAM_OFFSET   0x408
-#define GC_KEYMGR_SHA_CFG_EN_HMAC_LSB            0x5
-#define GC_KEYMGR_SHA_CFG_EN_HMAC_MASK           0x20
-#define GC_KEYMGR_SHA_CFG_EN_HMAC_SIZE           0x1
-#define GC_KEYMGR_SHA_CFG_EN_HMAC_DEFAULT        0x0
-#define GC_KEYMGR_SHA_CFG_EN_HMAC_OFFSET         0x408
-#define GC_KEYMGR_SHA_CFG_EN_INT_EN_DONE_LSB     0x10
-#define GC_KEYMGR_SHA_CFG_EN_INT_EN_DONE_MASK    0x10000
-#define GC_KEYMGR_SHA_CFG_EN_INT_EN_DONE_SIZE    0x1
-#define GC_KEYMGR_SHA_CFG_EN_INT_EN_DONE_DEFAULT 0x0
-#define GC_KEYMGR_SHA_CFG_EN_INT_EN_DONE_OFFSET  0x408
-#define GC_KEYMGR_SHA_CFG_EN_INT_MASK_DONE_LSB   0x11
-#define GC_KEYMGR_SHA_CFG_EN_INT_MASK_DONE_MASK  0x20000
-#define GC_KEYMGR_SHA_CFG_EN_INT_MASK_DONE_SIZE  0x1
-#define GC_KEYMGR_SHA_CFG_EN_INT_MASK_DONE_DEFAULT 0x0
-#define GC_KEYMGR_SHA_CFG_EN_INT_MASK_DONE_OFFSET 0x408
-#define GC_KEYMGR_SHA_TRIG_TRIG_GO_LSB           0x0
-#define GC_KEYMGR_SHA_TRIG_TRIG_GO_MASK          0x1
-#define GC_KEYMGR_SHA_TRIG_TRIG_GO_SIZE          0x1
-#define GC_KEYMGR_SHA_TRIG_TRIG_GO_DEFAULT       0x0
-#define GC_KEYMGR_SHA_TRIG_TRIG_GO_OFFSET        0x410
-#define GC_KEYMGR_SHA_TRIG_TRIG_RESET_LSB        0x1
-#define GC_KEYMGR_SHA_TRIG_TRIG_RESET_MASK       0x2
-#define GC_KEYMGR_SHA_TRIG_TRIG_RESET_SIZE       0x1
-#define GC_KEYMGR_SHA_TRIG_TRIG_RESET_DEFAULT    0x0
-#define GC_KEYMGR_SHA_TRIG_TRIG_RESET_OFFSET     0x410
-#define GC_KEYMGR_SHA_TRIG_TRIG_STEP_LSB         0x2
-#define GC_KEYMGR_SHA_TRIG_TRIG_STEP_MASK        0x4
-#define GC_KEYMGR_SHA_TRIG_TRIG_STEP_SIZE        0x1
-#define GC_KEYMGR_SHA_TRIG_TRIG_STEP_DEFAULT     0x0
-#define GC_KEYMGR_SHA_TRIG_TRIG_STEP_OFFSET      0x410
-#define GC_KEYMGR_SHA_TRIG_TRIG_STOP_LSB         0x3
-#define GC_KEYMGR_SHA_TRIG_TRIG_STOP_MASK        0x8
-#define GC_KEYMGR_SHA_TRIG_TRIG_STOP_SIZE        0x1
-#define GC_KEYMGR_SHA_TRIG_TRIG_STOP_DEFAULT     0x0
-#define GC_KEYMGR_SHA_TRIG_TRIG_STOP_OFFSET      0x410
-#define GC_KEYMGR_SHA_STS_FIFO_EMPTY_LSB         0x0
-#define GC_KEYMGR_SHA_STS_FIFO_EMPTY_MASK        0x1
-#define GC_KEYMGR_SHA_STS_FIFO_EMPTY_SIZE        0x1
-#define GC_KEYMGR_SHA_STS_FIFO_EMPTY_DEFAULT     0x0
-#define GC_KEYMGR_SHA_STS_FIFO_EMPTY_OFFSET      0x484
-#define GC_KEYMGR_SHA_STS_FIFO_FULL_LSB          0x1
-#define GC_KEYMGR_SHA_STS_FIFO_FULL_MASK         0x2
-#define GC_KEYMGR_SHA_STS_FIFO_FULL_SIZE         0x1
-#define GC_KEYMGR_SHA_STS_FIFO_FULL_DEFAULT      0x0
-#define GC_KEYMGR_SHA_STS_FIFO_FULL_OFFSET       0x484
-#define GC_KEYMGR_SHA_STS_ERROR_LSB              0x2
-#define GC_KEYMGR_SHA_STS_ERROR_MASK             0x4
-#define GC_KEYMGR_SHA_STS_ERROR_SIZE             0x1
-#define GC_KEYMGR_SHA_STS_ERROR_DEFAULT          0x0
-#define GC_KEYMGR_SHA_STS_ERROR_OFFSET           0x484
-#define GC_KEYMGR_SHA_USE_HIDDEN_KEY_INDEX_LSB   0x0
-#define GC_KEYMGR_SHA_USE_HIDDEN_KEY_INDEX_MASK  0x3ff
-#define GC_KEYMGR_SHA_USE_HIDDEN_KEY_INDEX_SIZE  0xa
-#define GC_KEYMGR_SHA_USE_HIDDEN_KEY_INDEX_DEFAULT 0x0
-#define GC_KEYMGR_SHA_USE_HIDDEN_KEY_INDEX_OFFSET 0x490
-#define GC_KEYMGR_SHA_USE_HIDDEN_KEY_ENABLE_LSB  0xa
-#define GC_KEYMGR_SHA_USE_HIDDEN_KEY_ENABLE_MASK 0x400
-#define GC_KEYMGR_SHA_USE_HIDDEN_KEY_ENABLE_SIZE 0x1
-#define GC_KEYMGR_SHA_USE_HIDDEN_KEY_ENABLE_DEFAULT 0x0
-#define GC_KEYMGR_SHA_USE_HIDDEN_KEY_ENABLE_OFFSET 0x490
-#define GC_KEYMGR_SHA_USE_CERT_INDEX_LSB         0x0
-#define GC_KEYMGR_SHA_USE_CERT_INDEX_MASK        0x3f
-#define GC_KEYMGR_SHA_USE_CERT_INDEX_SIZE        0x6
-#define GC_KEYMGR_SHA_USE_CERT_INDEX_DEFAULT     0x0
-#define GC_KEYMGR_SHA_USE_CERT_INDEX_OFFSET      0x494
-#define GC_KEYMGR_SHA_USE_CERT_ENABLE_LSB        0x6
-#define GC_KEYMGR_SHA_USE_CERT_ENABLE_MASK       0x40
-#define GC_KEYMGR_SHA_USE_CERT_ENABLE_SIZE       0x1
-#define GC_KEYMGR_SHA_USE_CERT_ENABLE_DEFAULT    0x0
-#define GC_KEYMGR_SHA_USE_CERT_ENABLE_OFFSET     0x494
-#define GC_KEYMGR_SHA_USE_CERT_CHECK_ONLY_LSB    0x7
-#define GC_KEYMGR_SHA_USE_CERT_CHECK_ONLY_MASK   0x80
-#define GC_KEYMGR_SHA_USE_CERT_CHECK_ONLY_SIZE   0x1
-#define GC_KEYMGR_SHA_USE_CERT_CHECK_ONLY_DEFAULT 0x0
-#define GC_KEYMGR_SHA_USE_CERT_CHECK_ONLY_OFFSET 0x494
-#define GC_KEYMGR_SHA_CERT_OVERRIDE_DIGEST_PTR_LSB 0x0
-#define GC_KEYMGR_SHA_CERT_OVERRIDE_DIGEST_PTR_MASK 0x3f
-#define GC_KEYMGR_SHA_CERT_OVERRIDE_DIGEST_PTR_SIZE 0x6
-#define GC_KEYMGR_SHA_CERT_OVERRIDE_DIGEST_PTR_DEFAULT 0x0
-#define GC_KEYMGR_SHA_CERT_OVERRIDE_DIGEST_PTR_OFFSET 0x498
-#define GC_KEYMGR_SHA_CERT_OVERRIDE_KEY_PTR_LSB  0x10
-#define GC_KEYMGR_SHA_CERT_OVERRIDE_KEY_PTR_MASK 0x3f0000
-#define GC_KEYMGR_SHA_CERT_OVERRIDE_KEY_PTR_SIZE 0x6
-#define GC_KEYMGR_SHA_CERT_OVERRIDE_KEY_PTR_DEFAULT 0x0
-#define GC_KEYMGR_SHA_CERT_OVERRIDE_KEY_PTR_OFFSET 0x498
-#define GC_KEYMGR_SHA_RAND_STALL_CTL_STALL_EN_LSB 0x0
-#define GC_KEYMGR_SHA_RAND_STALL_CTL_STALL_EN_MASK 0x1
-#define GC_KEYMGR_SHA_RAND_STALL_CTL_STALL_EN_SIZE 0x1
-#define GC_KEYMGR_SHA_RAND_STALL_CTL_STALL_EN_DEFAULT 0x1
-#define GC_KEYMGR_SHA_RAND_STALL_CTL_STALL_EN_OFFSET 0x49c
-#define GC_KEYMGR_SHA_RAND_STALL_CTL_FREQ_LSB    0x1
-#define GC_KEYMGR_SHA_RAND_STALL_CTL_FREQ_MASK   0x6
-#define GC_KEYMGR_SHA_RAND_STALL_CTL_FREQ_SIZE   0x2
-#define GC_KEYMGR_SHA_RAND_STALL_CTL_FREQ_DEFAULT 0x3
-#define GC_KEYMGR_SHA_RAND_STALL_CTL_FREQ_OFFSET 0x49c
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_PHIK_LSB 0x0
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_PHIK_MASK 0x3
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_PHIK_SIZE 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_PHIK_DEFAULT 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_PHIK_OFFSET 0x4a8
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_PHIK_SIGNATURE_LSB 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_PHIK_SIGNATURE_MASK 0xc
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_PHIK_SIGNATURE_SIZE 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_PHIK_SIGNATURE_DEFAULT 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_PHIK_SIGNATURE_OFFSET 0x4a8
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_EXPORT_INTEGRITY_PHIK_LSB 0x4
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_EXPORT_INTEGRITY_PHIK_MASK 0x30
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_EXPORT_INTEGRITY_PHIK_SIZE 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_EXPORT_INTEGRITY_PHIK_DEFAULT 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_EXPORT_INTEGRITY_PHIK_OFFSET 0x4a8
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK_CREATION_PHIK_LSB 0x6
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK_CREATION_PHIK_MASK 0xc0
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK_CREATION_PHIK_SIZE 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK_CREATION_PHIK_DEFAULT 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK_CREATION_PHIK_OFFSET 0x4a8
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_CHURN_OBS_FBS_LSB 0x8
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_CHURN_OBS_FBS_MASK 0x300
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_CHURN_OBS_FBS_SIZE 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_CHURN_OBS_FBS_DEFAULT 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_CHURN_OBS_FBS_OFFSET 0x4a8
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK_ROOTKEY_LSB 0xa
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK_ROOTKEY_MASK 0xc00
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK_ROOTKEY_SIZE 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK_ROOTKEY_DEFAULT 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK_ROOTKEY_OFFSET 0x4a8
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK_RT_SIGNATURE_LSB 0xc
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK_RT_SIGNATURE_MASK 0x3000
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK_RT_SIGNATURE_SIZE 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK_RT_SIGNATURE_DEFAULT 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK_RT_SIGNATURE_OFFSET 0x4a8
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_BOOT_LOADER_HIK_LSB 0xe
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_BOOT_LOADER_HIK_MASK 0xc000
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_BOOT_LOADER_HIK_SIZE 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_BOOT_LOADER_HIK_DEFAULT 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_BOOT_LOADER_HIK_OFFSET 0x4a8
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK_PRIVATE_KEY_LSB 0x10
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK_PRIVATE_KEY_MASK 0x30000
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK_PRIVATE_KEY_SIZE 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK_PRIVATE_KEY_DEFAULT 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK_PRIVATE_KEY_OFFSET 0x4a8
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK0_FOR_EXPORT_LSB 0x12
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK0_FOR_EXPORT_MASK 0xc0000
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK0_FOR_EXPORT_SIZE 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK0_FOR_EXPORT_DEFAULT 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK0_FOR_EXPORT_OFFSET 0x4a8
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK1_FOR_EXPORT_LSB 0x14
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK1_FOR_EXPORT_MASK 0x300000
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK1_FOR_EXPORT_SIZE 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK1_FOR_EXPORT_DEFAULT 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK1_FOR_EXPORT_OFFSET 0x4a8
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK2_FOR_EXPORT_LSB 0x16
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK2_FOR_EXPORT_MASK 0xc00000
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK2_FOR_EXPORT_SIZE 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK2_FOR_EXPORT_DEFAULT 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK2_FOR_EXPORT_OFFSET 0x4a8
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_ENCRYPTED_PERSO_PAYLOAD_MAC_LSB 0x18
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_ENCRYPTED_PERSO_PAYLOAD_MAC_MASK 0x3000000
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_ENCRYPTED_PERSO_PAYLOAD_MAC_SIZE 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_ENCRYPTED_PERSO_PAYLOAD_MAC_DEFAULT 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_ENCRYPTED_PERSO_PAYLOAD_MAC_OFFSET 0x4a8
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK0_LSB 0x1a
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK0_MASK 0xc000000
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK0_SIZE 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK0_DEFAULT 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK0_OFFSET 0x4a8
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK1_LSB 0x1c
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK1_MASK 0x30000000
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK1_SIZE 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK1_DEFAULT 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK1_OFFSET 0x4a8
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK2_LSB 0x1e
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK2_MASK 0xc0000000
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK2_SIZE 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK2_DEFAULT 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL0_DERIVE_HIK2_OFFSET 0x4a8
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_TESTMODE_PASSWORD_ROOTKEY_LSB 0x0
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_TESTMODE_PASSWORD_ROOTKEY_MASK 0x3
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_TESTMODE_PASSWORD_ROOTKEY_SIZE 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_TESTMODE_PASSWORD_ROOTKEY_DEFAULT 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_TESTMODE_PASSWORD_ROOTKEY_OFFSET 0x4ac
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_TESTMODE_PASSWORD_LSB 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_TESTMODE_PASSWORD_MASK 0xc
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_TESTMODE_PASSWORD_SIZE 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_TESTMODE_PASSWORD_DEFAULT 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_TESTMODE_PASSWORD_OFFSET 0x4ac
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_STAGE2_FIRMWARE_HIK0_LSB 0x4
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_STAGE2_FIRMWARE_HIK0_MASK 0x30
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_STAGE2_FIRMWARE_HIK0_SIZE 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_STAGE2_FIRMWARE_HIK0_DEFAULT 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_STAGE2_FIRMWARE_HIK0_OFFSET 0x4ac
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_STAGE2_FIRMWARE_HIK1_LSB 0x6
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_STAGE2_FIRMWARE_HIK1_MASK 0xc0
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_STAGE2_FIRMWARE_HIK1_SIZE 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_STAGE2_FIRMWARE_HIK1_DEFAULT 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_STAGE2_FIRMWARE_HIK1_OFFSET 0x4ac
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_STAGE2_FIRMWARE_HIK2_LSB 0x8
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_STAGE2_FIRMWARE_HIK2_MASK 0x300
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_STAGE2_FIRMWARE_HIK2_SIZE 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_STAGE2_FIRMWARE_HIK2_DEFAULT 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_DERIVE_STAGE2_FIRMWARE_HIK2_OFFSET 0x4ac
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_STAGE2_HIK0_FIRMWARE_HASH_CHAIN_LSB 0xa
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_STAGE2_HIK0_FIRMWARE_HASH_CHAIN_MASK 0xc00
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_STAGE2_HIK0_FIRMWARE_HASH_CHAIN_SIZE 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_STAGE2_HIK0_FIRMWARE_HASH_CHAIN_DEFAULT 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_STAGE2_HIK0_FIRMWARE_HASH_CHAIN_OFFSET 0x4ac
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_FW2_HIK0_CHAIN_LAST_LINK_EXPORT_LSB 0xc
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_FW2_HIK0_CHAIN_LAST_LINK_EXPORT_MASK 0x3000
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_FW2_HIK0_CHAIN_LAST_LINK_EXPORT_SIZE 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_FW2_HIK0_CHAIN_LAST_LINK_EXPORT_DEFAULT 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_FW2_HIK0_CHAIN_LAST_LINK_EXPORT_OFFSET 0x4ac
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_STAGE2_HIK1_FIRMWARE_HASH_CHAIN_LSB 0xe
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_STAGE2_HIK1_FIRMWARE_HASH_CHAIN_MASK 0xc000
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_STAGE2_HIK1_FIRMWARE_HASH_CHAIN_SIZE 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_STAGE2_HIK1_FIRMWARE_HASH_CHAIN_DEFAULT 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_STAGE2_HIK1_FIRMWARE_HASH_CHAIN_OFFSET 0x4ac
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_FW2_HIK1_CHAIN_LAST_LINK_EXPORT_LSB 0x10
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_FW2_HIK1_CHAIN_LAST_LINK_EXPORT_MASK 0x30000
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_FW2_HIK1_CHAIN_LAST_LINK_EXPORT_SIZE 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_FW2_HIK1_CHAIN_LAST_LINK_EXPORT_DEFAULT 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_FW2_HIK1_CHAIN_LAST_LINK_EXPORT_OFFSET 0x4ac
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_STAGE2_HIK2_FIRMWARE_HASH_CHAIN_LSB 0x12
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_STAGE2_HIK2_FIRMWARE_HASH_CHAIN_MASK 0xc0000
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_STAGE2_HIK2_FIRMWARE_HASH_CHAIN_SIZE 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_STAGE2_HIK2_FIRMWARE_HASH_CHAIN_DEFAULT 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_STAGE2_HIK2_FIRMWARE_HASH_CHAIN_OFFSET 0x4ac
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_FW2_HIK2_CHAIN_LAST_LINK_EXPORT_LSB 0x14
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_FW2_HIK2_CHAIN_LAST_LINK_EXPORT_MASK 0x300000
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_FW2_HIK2_CHAIN_LAST_LINK_EXPORT_SIZE 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_FW2_HIK2_CHAIN_LAST_LINK_EXPORT_DEFAULT 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_FW2_HIK2_CHAIN_LAST_LINK_EXPORT_OFFSET 0x4ac
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_GET_STIRRED_RANDOM_DATA_LSB 0x16
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_GET_STIRRED_RANDOM_DATA_MASK 0xc00000
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_GET_STIRRED_RANDOM_DATA_SIZE 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_GET_STIRRED_RANDOM_DATA_DEFAULT 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_GET_STIRRED_RANDOM_DATA_OFFSET 0x4ac
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_STIR_RANDOM_DATA_AND_UPDATE_RSR_LSB 0x18
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_STIR_RANDOM_DATA_AND_UPDATE_RSR_MASK 0x3000000
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_STIR_RANDOM_DATA_AND_UPDATE_RSR_SIZE 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_STIR_RANDOM_DATA_AND_UPDATE_RSR_DEFAULT 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_STIR_RANDOM_DATA_AND_UPDATE_RSR_OFFSET 0x4ac
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_STIR_RANDOM_DATA_INTO_USRS_LSB 0x1a
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_STIR_RANDOM_DATA_INTO_USRS_MASK 0xc000000
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_STIR_RANDOM_DATA_INTO_USRS_SIZE 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_STIR_RANDOM_DATA_INTO_USRS_DEFAULT 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_STIR_RANDOM_DATA_INTO_USRS_OFFSET 0x4ac
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_HIK0_ISR0_KEYS_LSB 0x1c
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_HIK0_ISR0_KEYS_MASK 0x30000000
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_HIK0_ISR0_KEYS_SIZE 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_HIK0_ISR0_KEYS_DEFAULT 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_HIK0_ISR0_KEYS_OFFSET 0x4ac
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_HIK0_USR_KEYS_LSB 0x1e
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_HIK0_USR_KEYS_MASK 0xc0000000
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_HIK0_USR_KEYS_SIZE 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_HIK0_USR_KEYS_DEFAULT 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL1_HIK0_USR_KEYS_OFFSET 0x4ac
-#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK1_ISR1_KEYS_LSB 0x0
-#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK1_ISR1_KEYS_MASK 0x3
-#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK1_ISR1_KEYS_SIZE 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK1_ISR1_KEYS_DEFAULT 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK1_ISR1_KEYS_OFFSET 0x4b0
-#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK1_USR_KEYS_LSB 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK1_USR_KEYS_MASK 0xc
-#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK1_USR_KEYS_SIZE 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK1_USR_KEYS_DEFAULT 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK1_USR_KEYS_OFFSET 0x4b0
-#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK2_ISR2_KEYS_LSB 0x4
-#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK2_ISR2_KEYS_MASK 0x30
-#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK2_ISR2_KEYS_SIZE 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK2_ISR2_KEYS_DEFAULT 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK2_ISR2_KEYS_OFFSET 0x4b0
-#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK2_USR_KEYS_LSB 0x6
-#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK2_USR_KEYS_MASK 0xc0
-#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK2_USR_KEYS_SIZE 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK2_USR_KEYS_DEFAULT 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK2_USR_KEYS_OFFSET 0x4b0
-#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK0_HMAC_USER_DATA_LSB 0x8
-#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK0_HMAC_USER_DATA_MASK 0x300
-#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK0_HMAC_USER_DATA_SIZE 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK0_HMAC_USER_DATA_DEFAULT 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK0_HMAC_USER_DATA_OFFSET 0x4b0
-#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK1_HMAC_USER_DATA_LSB 0xa
-#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK1_HMAC_USER_DATA_MASK 0xc00
-#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK1_HMAC_USER_DATA_SIZE 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK1_HMAC_USER_DATA_DEFAULT 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK1_HMAC_USER_DATA_OFFSET 0x4b0
-#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK2_HMAC_USER_DATA_LSB 0xc
-#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK2_HMAC_USER_DATA_MASK 0x3000
-#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK2_HMAC_USER_DATA_SIZE 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK2_HMAC_USER_DATA_DEFAULT 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL2_HIK2_HMAC_USER_DATA_OFFSET 0x4b0
-#define GC_KEYMGR_CERT_REVOKE_CTRL2_HASH_ROM_FOR_RBC_LSB 0xe
-#define GC_KEYMGR_CERT_REVOKE_CTRL2_HASH_ROM_FOR_RBC_MASK 0xc000
-#define GC_KEYMGR_CERT_REVOKE_CTRL2_HASH_ROM_FOR_RBC_SIZE 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL2_HASH_ROM_FOR_RBC_DEFAULT 0x2
-#define GC_KEYMGR_CERT_REVOKE_CTRL2_HASH_ROM_FOR_RBC_OFFSET 0x4b0
-#define GC_KEYMGR_HKEY_ERR_FLAGS_AES_ALL_0S_ERR_LSB 0x0
-#define GC_KEYMGR_HKEY_ERR_FLAGS_AES_ALL_0S_ERR_MASK 0x1
-#define GC_KEYMGR_HKEY_ERR_FLAGS_AES_ALL_0S_ERR_SIZE 0x1
-#define GC_KEYMGR_HKEY_ERR_FLAGS_AES_ALL_0S_ERR_DEFAULT 0x0
-#define GC_KEYMGR_HKEY_ERR_FLAGS_AES_ALL_0S_ERR_OFFSET 0x3324
-#define GC_KEYMGR_HKEY_ERR_FLAGS_AES_ALL_1S_ERR_LSB 0x1
-#define GC_KEYMGR_HKEY_ERR_FLAGS_AES_ALL_1S_ERR_MASK 0x2
-#define GC_KEYMGR_HKEY_ERR_FLAGS_AES_ALL_1S_ERR_SIZE 0x1
-#define GC_KEYMGR_HKEY_ERR_FLAGS_AES_ALL_1S_ERR_DEFAULT 0x0
-#define GC_KEYMGR_HKEY_ERR_FLAGS_AES_ALL_1S_ERR_OFFSET 0x3324
-#define GC_KEYMGR_HKEY_ERR_FLAGS_AES_SLOT_VLD_ERR_LSB 0x2
-#define GC_KEYMGR_HKEY_ERR_FLAGS_AES_SLOT_VLD_ERR_MASK 0x4
-#define GC_KEYMGR_HKEY_ERR_FLAGS_AES_SLOT_VLD_ERR_SIZE 0x1
-#define GC_KEYMGR_HKEY_ERR_FLAGS_AES_SLOT_VLD_ERR_DEFAULT 0x0
-#define GC_KEYMGR_HKEY_ERR_FLAGS_AES_SLOT_VLD_ERR_OFFSET 0x3324
-#define GC_KEYMGR_HKEY_ERR_FLAGS_DIGEST_ADDR_ERR_LSB 0x3
-#define GC_KEYMGR_HKEY_ERR_FLAGS_DIGEST_ADDR_ERR_MASK 0x8
-#define GC_KEYMGR_HKEY_ERR_FLAGS_DIGEST_ADDR_ERR_SIZE 0x1
-#define GC_KEYMGR_HKEY_ERR_FLAGS_DIGEST_ADDR_ERR_DEFAULT 0x0
-#define GC_KEYMGR_HKEY_ERR_FLAGS_DIGEST_ADDR_ERR_OFFSET 0x3324
-#define GC_KEYMGR_HKEY_ERR_FLAGS_DIGEST_ALL_0S_ERR_LSB 0x4
-#define GC_KEYMGR_HKEY_ERR_FLAGS_DIGEST_ALL_0S_ERR_MASK 0x10
-#define GC_KEYMGR_HKEY_ERR_FLAGS_DIGEST_ALL_0S_ERR_SIZE 0x1
-#define GC_KEYMGR_HKEY_ERR_FLAGS_DIGEST_ALL_0S_ERR_DEFAULT 0x0
-#define GC_KEYMGR_HKEY_ERR_FLAGS_DIGEST_ALL_0S_ERR_OFFSET 0x3324
-#define GC_KEYMGR_HKEY_ERR_FLAGS_DIGEST_ALL_1S_ERR_LSB 0x5
-#define GC_KEYMGR_HKEY_ERR_FLAGS_DIGEST_ALL_1S_ERR_MASK 0x20
-#define GC_KEYMGR_HKEY_ERR_FLAGS_DIGEST_ALL_1S_ERR_SIZE 0x1
-#define GC_KEYMGR_HKEY_ERR_FLAGS_DIGEST_ALL_1S_ERR_DEFAULT 0x0
-#define GC_KEYMGR_HKEY_ERR_FLAGS_DIGEST_ALL_1S_ERR_OFFSET 0x3324
-#define GC_KEYMGR_HKEY_ERR_FLAGS_OVFL_GEN_ERR_LSB 0x6
-#define GC_KEYMGR_HKEY_ERR_FLAGS_OVFL_GEN_ERR_MASK 0x40
-#define GC_KEYMGR_HKEY_ERR_FLAGS_OVFL_GEN_ERR_SIZE 0x1
-#define GC_KEYMGR_HKEY_ERR_FLAGS_OVFL_GEN_ERR_DEFAULT 0x0
-#define GC_KEYMGR_HKEY_ERR_FLAGS_OVFL_GEN_ERR_OFFSET 0x3324
-#define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_ALL_0S_ERR_LSB 0x7
-#define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_ALL_0S_ERR_MASK 0x80
-#define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_ALL_0S_ERR_SIZE 0x1
-#define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_ALL_0S_ERR_DEFAULT 0x0
-#define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_ALL_0S_ERR_OFFSET 0x3324
-#define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_ALL_1S_ERR_LSB 0x8
-#define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_ALL_1S_ERR_MASK 0x100
-#define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_ALL_1S_ERR_SIZE 0x1
-#define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_ALL_1S_ERR_DEFAULT 0x0
-#define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_ALL_1S_ERR_OFFSET 0x3324
-#define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_SLOT_VLD_ERR_LSB 0x9
-#define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_SLOT_VLD_ERR_MASK 0x200
-#define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_SLOT_VLD_ERR_SIZE 0x1
-#define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_SLOT_VLD_ERR_DEFAULT 0x0
-#define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_SLOT_VLD_ERR_OFFSET 0x3324
-#define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_CMP_FAIL_ERR_LSB 0xa
-#define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_CMP_FAIL_ERR_MASK 0x400
-#define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_CMP_FAIL_ERR_SIZE 0x1
-#define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_CMP_FAIL_ERR_DEFAULT 0x0
-#define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_CMP_FAIL_ERR_OFFSET 0x3324
-#define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_WRG_GEN_ERR_LSB 0xb
-#define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_WRG_GEN_ERR_MASK 0x800
-#define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_WRG_GEN_ERR_SIZE 0x1
-#define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_WRG_GEN_ERR_DEFAULT 0x0
-#define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_WRG_GEN_ERR_OFFSET 0x3324
-#define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_WRG_ID_ERR_LSB 0xc
-#define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_WRG_ID_ERR_MASK 0x1000
-#define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_WRG_ID_ERR_SIZE 0x1
-#define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_WRG_ID_ERR_DEFAULT 0x0
-#define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_WRG_ID_ERR_OFFSET 0x3324
-#define GC_KEYMGR_HKEY_ERR_FLAGS_PW_ALL_0S_ERR_LSB 0xd
-#define GC_KEYMGR_HKEY_ERR_FLAGS_PW_ALL_0S_ERR_MASK 0x2000
-#define GC_KEYMGR_HKEY_ERR_FLAGS_PW_ALL_0S_ERR_SIZE 0x1
-#define GC_KEYMGR_HKEY_ERR_FLAGS_PW_ALL_0S_ERR_DEFAULT 0x0
-#define GC_KEYMGR_HKEY_ERR_FLAGS_PW_ALL_0S_ERR_OFFSET 0x3324
-#define GC_KEYMGR_HKEY_ERR_FLAGS_PW_ALL_1S_ERR_LSB 0xe
-#define GC_KEYMGR_HKEY_ERR_FLAGS_PW_ALL_1S_ERR_MASK 0x4000
-#define GC_KEYMGR_HKEY_ERR_FLAGS_PW_ALL_1S_ERR_SIZE 0x1
-#define GC_KEYMGR_HKEY_ERR_FLAGS_PW_ALL_1S_ERR_DEFAULT 0x0
-#define GC_KEYMGR_HKEY_ERR_FLAGS_PW_ALL_1S_ERR_OFFSET 0x3324
-#define GC_KEYMGR_HKEY_ERR_FLAGS_UNLOCK_TRYS_ERR_LSB 0xf
-#define GC_KEYMGR_HKEY_ERR_FLAGS_UNLOCK_TRYS_ERR_MASK 0x8000
-#define GC_KEYMGR_HKEY_ERR_FLAGS_UNLOCK_TRYS_ERR_SIZE 0x1
-#define GC_KEYMGR_HKEY_ERR_FLAGS_UNLOCK_TRYS_ERR_DEFAULT 0x0
-#define GC_KEYMGR_HKEY_ERR_FLAGS_UNLOCK_TRYS_ERR_OFFSET 0x3324
-#define GC_KEYMGR_HKEY_ERR_FLAGS_FLASH_FBS_ERR_LSB 0x10
-#define GC_KEYMGR_HKEY_ERR_FLAGS_FLASH_FBS_ERR_MASK 0x10000
-#define GC_KEYMGR_HKEY_ERR_FLAGS_FLASH_FBS_ERR_SIZE 0x1
-#define GC_KEYMGR_HKEY_ERR_FLAGS_FLASH_FBS_ERR_DEFAULT 0x0
-#define GC_KEYMGR_HKEY_ERR_FLAGS_FLASH_FBS_ERR_OFFSET 0x3324
-#define GC_KEYMGR_HKEY_ERR_FLAGS_FLASH_RSR_ERR_LSB 0x11
-#define GC_KEYMGR_HKEY_ERR_FLAGS_FLASH_RSR_ERR_MASK 0x20000
-#define GC_KEYMGR_HKEY_ERR_FLAGS_FLASH_RSR_ERR_SIZE 0x1
-#define GC_KEYMGR_HKEY_ERR_FLAGS_FLASH_RSR_ERR_DEFAULT 0x0
-#define GC_KEYMGR_HKEY_ERR_FLAGS_FLASH_RSR_ERR_OFFSET 0x3324
-#define GC_KEYMGR_HKEY_ERR_CTRL_LONG0_CHK_EN_LSB 0x0
-#define GC_KEYMGR_HKEY_ERR_CTRL_LONG0_CHK_EN_MASK 0x1
-#define GC_KEYMGR_HKEY_ERR_CTRL_LONG0_CHK_EN_SIZE 0x1
-#define GC_KEYMGR_HKEY_ERR_CTRL_LONG0_CHK_EN_DEFAULT 0x0
-#define GC_KEYMGR_HKEY_ERR_CTRL_LONG0_CHK_EN_OFFSET 0x3328
-#define GC_KEYMGR_HKEY_ERR_CTRL_LONG1_CHK_EN_LSB 0x1
-#define GC_KEYMGR_HKEY_ERR_CTRL_LONG1_CHK_EN_MASK 0x2
-#define GC_KEYMGR_HKEY_ERR_CTRL_LONG1_CHK_EN_SIZE 0x1
-#define GC_KEYMGR_HKEY_ERR_CTRL_LONG1_CHK_EN_DEFAULT 0x0
-#define GC_KEYMGR_HKEY_ERR_CTRL_LONG1_CHK_EN_OFFSET 0x3328
-#define GC_KEYMGR_HKEY_ERR_CTRL_TM_LONG0_CHK_EN_LSB 0x2
-#define GC_KEYMGR_HKEY_ERR_CTRL_TM_LONG0_CHK_EN_MASK 0x4
-#define GC_KEYMGR_HKEY_ERR_CTRL_TM_LONG0_CHK_EN_SIZE 0x1
-#define GC_KEYMGR_HKEY_ERR_CTRL_TM_LONG0_CHK_EN_DEFAULT 0x0
-#define GC_KEYMGR_HKEY_ERR_CTRL_TM_LONG0_CHK_EN_OFFSET 0x3328
-#define GC_KEYMGR_HKEY_ERR_CTRL_TM_LONG1_CHK_EN_LSB 0x3
-#define GC_KEYMGR_HKEY_ERR_CTRL_TM_LONG1_CHK_EN_MASK 0x8
-#define GC_KEYMGR_HKEY_ERR_CTRL_TM_LONG1_CHK_EN_SIZE 0x1
-#define GC_KEYMGR_HKEY_ERR_CTRL_TM_LONG1_CHK_EN_DEFAULT 0x0
-#define GC_KEYMGR_HKEY_ERR_CTRL_TM_LONG1_CHK_EN_OFFSET 0x3328
-#define GC_KEYMGR_HKEY_FLASH_RCV_STATUS_FBS_START_LSB 0x0
-#define GC_KEYMGR_HKEY_FLASH_RCV_STATUS_FBS_START_MASK 0x1
-#define GC_KEYMGR_HKEY_FLASH_RCV_STATUS_FBS_START_SIZE 0x1
-#define GC_KEYMGR_HKEY_FLASH_RCV_STATUS_FBS_START_DEFAULT 0x0
-#define GC_KEYMGR_HKEY_FLASH_RCV_STATUS_FBS_START_OFFSET 0x332c
-#define GC_KEYMGR_HKEY_FLASH_RCV_STATUS_FBS_SUCCESS_LSB 0x1
-#define GC_KEYMGR_HKEY_FLASH_RCV_STATUS_FBS_SUCCESS_MASK 0x2
-#define GC_KEYMGR_HKEY_FLASH_RCV_STATUS_FBS_SUCCESS_SIZE 0x1
-#define GC_KEYMGR_HKEY_FLASH_RCV_STATUS_FBS_SUCCESS_DEFAULT 0x0
-#define GC_KEYMGR_HKEY_FLASH_RCV_STATUS_FBS_SUCCESS_OFFSET 0x332c
-#define GC_KEYMGR_HKEY_FLASH_RCV_STATUS_RSR_START_LSB 0x2
-#define GC_KEYMGR_HKEY_FLASH_RCV_STATUS_RSR_START_MASK 0x4
-#define GC_KEYMGR_HKEY_FLASH_RCV_STATUS_RSR_START_SIZE 0x1
-#define GC_KEYMGR_HKEY_FLASH_RCV_STATUS_RSR_START_DEFAULT 0x0
-#define GC_KEYMGR_HKEY_FLASH_RCV_STATUS_RSR_START_OFFSET 0x332c
-#define GC_KEYMGR_HKEY_FLASH_RCV_STATUS_RSR_SUCCESS_LSB 0x3
-#define GC_KEYMGR_HKEY_FLASH_RCV_STATUS_RSR_SUCCESS_MASK 0x8
-#define GC_KEYMGR_HKEY_FLASH_RCV_STATUS_RSR_SUCCESS_SIZE 0x1
-#define GC_KEYMGR_HKEY_FLASH_RCV_STATUS_RSR_SUCCESS_DEFAULT 0x0
-#define GC_KEYMGR_HKEY_FLASH_RCV_STATUS_RSR_SUCCESS_OFFSET 0x332c
-#define GC_PINMUX_DIOM0_CTL_DS_LSB               0x0
-#define GC_PINMUX_DIOM0_CTL_DS_MASK              0x3
-#define GC_PINMUX_DIOM0_CTL_DS_SIZE              0x2
-#define GC_PINMUX_DIOM0_CTL_DS_DEFAULT           0x3
-#define GC_PINMUX_DIOM0_CTL_DS_OFFSET            0x4
-#define GC_PINMUX_DIOM0_CTL_IE_LSB               0x2
-#define GC_PINMUX_DIOM0_CTL_IE_MASK              0x4
-#define GC_PINMUX_DIOM0_CTL_IE_SIZE              0x1
-#define GC_PINMUX_DIOM0_CTL_IE_DEFAULT           0x0
-#define GC_PINMUX_DIOM0_CTL_IE_OFFSET            0x4
-#define GC_PINMUX_DIOM0_CTL_PD_LSB               0x3
-#define GC_PINMUX_DIOM0_CTL_PD_MASK              0x8
-#define GC_PINMUX_DIOM0_CTL_PD_SIZE              0x1
-#define GC_PINMUX_DIOM0_CTL_PD_DEFAULT           0x0
-#define GC_PINMUX_DIOM0_CTL_PD_OFFSET            0x4
-#define GC_PINMUX_DIOM0_CTL_PU_LSB               0x4
-#define GC_PINMUX_DIOM0_CTL_PU_MASK              0x10
-#define GC_PINMUX_DIOM0_CTL_PU_SIZE              0x1
-#define GC_PINMUX_DIOM0_CTL_PU_DEFAULT           0x0
-#define GC_PINMUX_DIOM0_CTL_PU_OFFSET            0x4
-#define GC_PINMUX_DIOM0_CTL_INV_LSB              0x5
-#define GC_PINMUX_DIOM0_CTL_INV_MASK             0x20
-#define GC_PINMUX_DIOM0_CTL_INV_SIZE             0x1
-#define GC_PINMUX_DIOM0_CTL_INV_DEFAULT          0x0
-#define GC_PINMUX_DIOM0_CTL_INV_OFFSET           0x4
-#define GC_PINMUX_DIOM1_CTL_DS_LSB               0x0
-#define GC_PINMUX_DIOM1_CTL_DS_MASK              0x3
-#define GC_PINMUX_DIOM1_CTL_DS_SIZE              0x2
-#define GC_PINMUX_DIOM1_CTL_DS_DEFAULT           0x3
-#define GC_PINMUX_DIOM1_CTL_DS_OFFSET            0xc
-#define GC_PINMUX_DIOM1_CTL_IE_LSB               0x2
-#define GC_PINMUX_DIOM1_CTL_IE_MASK              0x4
-#define GC_PINMUX_DIOM1_CTL_IE_SIZE              0x1
-#define GC_PINMUX_DIOM1_CTL_IE_DEFAULT           0x0
-#define GC_PINMUX_DIOM1_CTL_IE_OFFSET            0xc
-#define GC_PINMUX_DIOM1_CTL_PD_LSB               0x3
-#define GC_PINMUX_DIOM1_CTL_PD_MASK              0x8
-#define GC_PINMUX_DIOM1_CTL_PD_SIZE              0x1
-#define GC_PINMUX_DIOM1_CTL_PD_DEFAULT           0x0
-#define GC_PINMUX_DIOM1_CTL_PD_OFFSET            0xc
-#define GC_PINMUX_DIOM1_CTL_PU_LSB               0x4
-#define GC_PINMUX_DIOM1_CTL_PU_MASK              0x10
-#define GC_PINMUX_DIOM1_CTL_PU_SIZE              0x1
-#define GC_PINMUX_DIOM1_CTL_PU_DEFAULT           0x0
-#define GC_PINMUX_DIOM1_CTL_PU_OFFSET            0xc
-#define GC_PINMUX_DIOM1_CTL_INV_LSB              0x5
-#define GC_PINMUX_DIOM1_CTL_INV_MASK             0x20
-#define GC_PINMUX_DIOM1_CTL_INV_SIZE             0x1
-#define GC_PINMUX_DIOM1_CTL_INV_DEFAULT          0x0
-#define GC_PINMUX_DIOM1_CTL_INV_OFFSET           0xc
-#define GC_PINMUX_DIOM2_CTL_DS_LSB               0x0
-#define GC_PINMUX_DIOM2_CTL_DS_MASK              0x3
-#define GC_PINMUX_DIOM2_CTL_DS_SIZE              0x2
-#define GC_PINMUX_DIOM2_CTL_DS_DEFAULT           0x3
-#define GC_PINMUX_DIOM2_CTL_DS_OFFSET            0x14
-#define GC_PINMUX_DIOM2_CTL_IE_LSB               0x2
-#define GC_PINMUX_DIOM2_CTL_IE_MASK              0x4
-#define GC_PINMUX_DIOM2_CTL_IE_SIZE              0x1
-#define GC_PINMUX_DIOM2_CTL_IE_DEFAULT           0x0
-#define GC_PINMUX_DIOM2_CTL_IE_OFFSET            0x14
-#define GC_PINMUX_DIOM2_CTL_PD_LSB               0x3
-#define GC_PINMUX_DIOM2_CTL_PD_MASK              0x8
-#define GC_PINMUX_DIOM2_CTL_PD_SIZE              0x1
-#define GC_PINMUX_DIOM2_CTL_PD_DEFAULT           0x0
-#define GC_PINMUX_DIOM2_CTL_PD_OFFSET            0x14
-#define GC_PINMUX_DIOM2_CTL_PU_LSB               0x4
-#define GC_PINMUX_DIOM2_CTL_PU_MASK              0x10
-#define GC_PINMUX_DIOM2_CTL_PU_SIZE              0x1
-#define GC_PINMUX_DIOM2_CTL_PU_DEFAULT           0x0
-#define GC_PINMUX_DIOM2_CTL_PU_OFFSET            0x14
-#define GC_PINMUX_DIOM2_CTL_INV_LSB              0x5
-#define GC_PINMUX_DIOM2_CTL_INV_MASK             0x20
-#define GC_PINMUX_DIOM2_CTL_INV_SIZE             0x1
-#define GC_PINMUX_DIOM2_CTL_INV_DEFAULT          0x0
-#define GC_PINMUX_DIOM2_CTL_INV_OFFSET           0x14
-#define GC_PINMUX_DIOM3_CTL_DS_LSB               0x0
-#define GC_PINMUX_DIOM3_CTL_DS_MASK              0x3
-#define GC_PINMUX_DIOM3_CTL_DS_SIZE              0x2
-#define GC_PINMUX_DIOM3_CTL_DS_DEFAULT           0x3
-#define GC_PINMUX_DIOM3_CTL_DS_OFFSET            0x1c
-#define GC_PINMUX_DIOM3_CTL_IE_LSB               0x2
-#define GC_PINMUX_DIOM3_CTL_IE_MASK              0x4
-#define GC_PINMUX_DIOM3_CTL_IE_SIZE              0x1
-#define GC_PINMUX_DIOM3_CTL_IE_DEFAULT           0x0
-#define GC_PINMUX_DIOM3_CTL_IE_OFFSET            0x1c
-#define GC_PINMUX_DIOM3_CTL_PD_LSB               0x3
-#define GC_PINMUX_DIOM3_CTL_PD_MASK              0x8
-#define GC_PINMUX_DIOM3_CTL_PD_SIZE              0x1
-#define GC_PINMUX_DIOM3_CTL_PD_DEFAULT           0x0
-#define GC_PINMUX_DIOM3_CTL_PD_OFFSET            0x1c
-#define GC_PINMUX_DIOM3_CTL_PU_LSB               0x4
-#define GC_PINMUX_DIOM3_CTL_PU_MASK              0x10
-#define GC_PINMUX_DIOM3_CTL_PU_SIZE              0x1
-#define GC_PINMUX_DIOM3_CTL_PU_DEFAULT           0x0
-#define GC_PINMUX_DIOM3_CTL_PU_OFFSET            0x1c
-#define GC_PINMUX_DIOM3_CTL_INV_LSB              0x5
-#define GC_PINMUX_DIOM3_CTL_INV_MASK             0x20
-#define GC_PINMUX_DIOM3_CTL_INV_SIZE             0x1
-#define GC_PINMUX_DIOM3_CTL_INV_DEFAULT          0x0
-#define GC_PINMUX_DIOM3_CTL_INV_OFFSET           0x1c
-#define GC_PINMUX_DIOM4_CTL_DS_LSB               0x0
-#define GC_PINMUX_DIOM4_CTL_DS_MASK              0x3
-#define GC_PINMUX_DIOM4_CTL_DS_SIZE              0x2
-#define GC_PINMUX_DIOM4_CTL_DS_DEFAULT           0x3
-#define GC_PINMUX_DIOM4_CTL_DS_OFFSET            0x24
-#define GC_PINMUX_DIOM4_CTL_IE_LSB               0x2
-#define GC_PINMUX_DIOM4_CTL_IE_MASK              0x4
-#define GC_PINMUX_DIOM4_CTL_IE_SIZE              0x1
-#define GC_PINMUX_DIOM4_CTL_IE_DEFAULT           0x0
-#define GC_PINMUX_DIOM4_CTL_IE_OFFSET            0x24
-#define GC_PINMUX_DIOM4_CTL_PD_LSB               0x3
-#define GC_PINMUX_DIOM4_CTL_PD_MASK              0x8
-#define GC_PINMUX_DIOM4_CTL_PD_SIZE              0x1
-#define GC_PINMUX_DIOM4_CTL_PD_DEFAULT           0x0
-#define GC_PINMUX_DIOM4_CTL_PD_OFFSET            0x24
-#define GC_PINMUX_DIOM4_CTL_PU_LSB               0x4
-#define GC_PINMUX_DIOM4_CTL_PU_MASK              0x10
-#define GC_PINMUX_DIOM4_CTL_PU_SIZE              0x1
-#define GC_PINMUX_DIOM4_CTL_PU_DEFAULT           0x0
-#define GC_PINMUX_DIOM4_CTL_PU_OFFSET            0x24
-#define GC_PINMUX_DIOM4_CTL_INV_LSB              0x5
-#define GC_PINMUX_DIOM4_CTL_INV_MASK             0x20
-#define GC_PINMUX_DIOM4_CTL_INV_SIZE             0x1
-#define GC_PINMUX_DIOM4_CTL_INV_DEFAULT          0x0
-#define GC_PINMUX_DIOM4_CTL_INV_OFFSET           0x24
-#define GC_PINMUX_DIOA0_CTL_DS_LSB               0x0
-#define GC_PINMUX_DIOA0_CTL_DS_MASK              0x3
-#define GC_PINMUX_DIOA0_CTL_DS_SIZE              0x2
-#define GC_PINMUX_DIOA0_CTL_DS_DEFAULT           0x3
-#define GC_PINMUX_DIOA0_CTL_DS_OFFSET            0x2c
-#define GC_PINMUX_DIOA0_CTL_IE_LSB               0x2
-#define GC_PINMUX_DIOA0_CTL_IE_MASK              0x4
-#define GC_PINMUX_DIOA0_CTL_IE_SIZE              0x1
-#define GC_PINMUX_DIOA0_CTL_IE_DEFAULT           0x0
-#define GC_PINMUX_DIOA0_CTL_IE_OFFSET            0x2c
-#define GC_PINMUX_DIOA0_CTL_PD_LSB               0x3
-#define GC_PINMUX_DIOA0_CTL_PD_MASK              0x8
-#define GC_PINMUX_DIOA0_CTL_PD_SIZE              0x1
-#define GC_PINMUX_DIOA0_CTL_PD_DEFAULT           0x0
-#define GC_PINMUX_DIOA0_CTL_PD_OFFSET            0x2c
-#define GC_PINMUX_DIOA0_CTL_PU_LSB               0x4
-#define GC_PINMUX_DIOA0_CTL_PU_MASK              0x10
-#define GC_PINMUX_DIOA0_CTL_PU_SIZE              0x1
-#define GC_PINMUX_DIOA0_CTL_PU_DEFAULT           0x0
-#define GC_PINMUX_DIOA0_CTL_PU_OFFSET            0x2c
-#define GC_PINMUX_DIOA0_CTL_INV_LSB              0x5
-#define GC_PINMUX_DIOA0_CTL_INV_MASK             0x20
-#define GC_PINMUX_DIOA0_CTL_INV_SIZE             0x1
-#define GC_PINMUX_DIOA0_CTL_INV_DEFAULT          0x0
-#define GC_PINMUX_DIOA0_CTL_INV_OFFSET           0x2c
-#define GC_PINMUX_DIOA1_CTL_DS_LSB               0x0
-#define GC_PINMUX_DIOA1_CTL_DS_MASK              0x3
-#define GC_PINMUX_DIOA1_CTL_DS_SIZE              0x2
-#define GC_PINMUX_DIOA1_CTL_DS_DEFAULT           0x3
-#define GC_PINMUX_DIOA1_CTL_DS_OFFSET            0x34
-#define GC_PINMUX_DIOA1_CTL_IE_LSB               0x2
-#define GC_PINMUX_DIOA1_CTL_IE_MASK              0x4
-#define GC_PINMUX_DIOA1_CTL_IE_SIZE              0x1
-#define GC_PINMUX_DIOA1_CTL_IE_DEFAULT           0x0
-#define GC_PINMUX_DIOA1_CTL_IE_OFFSET            0x34
-#define GC_PINMUX_DIOA1_CTL_PD_LSB               0x3
-#define GC_PINMUX_DIOA1_CTL_PD_MASK              0x8
-#define GC_PINMUX_DIOA1_CTL_PD_SIZE              0x1
-#define GC_PINMUX_DIOA1_CTL_PD_DEFAULT           0x0
-#define GC_PINMUX_DIOA1_CTL_PD_OFFSET            0x34
-#define GC_PINMUX_DIOA1_CTL_PU_LSB               0x4
-#define GC_PINMUX_DIOA1_CTL_PU_MASK              0x10
-#define GC_PINMUX_DIOA1_CTL_PU_SIZE              0x1
-#define GC_PINMUX_DIOA1_CTL_PU_DEFAULT           0x0
-#define GC_PINMUX_DIOA1_CTL_PU_OFFSET            0x34
-#define GC_PINMUX_DIOA1_CTL_INV_LSB              0x5
-#define GC_PINMUX_DIOA1_CTL_INV_MASK             0x20
-#define GC_PINMUX_DIOA1_CTL_INV_SIZE             0x1
-#define GC_PINMUX_DIOA1_CTL_INV_DEFAULT          0x0
-#define GC_PINMUX_DIOA1_CTL_INV_OFFSET           0x34
-#define GC_PINMUX_DIOA2_CTL_DS_LSB               0x0
-#define GC_PINMUX_DIOA2_CTL_DS_MASK              0x3
-#define GC_PINMUX_DIOA2_CTL_DS_SIZE              0x2
-#define GC_PINMUX_DIOA2_CTL_DS_DEFAULT           0x3
-#define GC_PINMUX_DIOA2_CTL_DS_OFFSET            0x3c
-#define GC_PINMUX_DIOA2_CTL_IE_LSB               0x2
-#define GC_PINMUX_DIOA2_CTL_IE_MASK              0x4
-#define GC_PINMUX_DIOA2_CTL_IE_SIZE              0x1
-#define GC_PINMUX_DIOA2_CTL_IE_DEFAULT           0x0
-#define GC_PINMUX_DIOA2_CTL_IE_OFFSET            0x3c
-#define GC_PINMUX_DIOA2_CTL_PD_LSB               0x3
-#define GC_PINMUX_DIOA2_CTL_PD_MASK              0x8
-#define GC_PINMUX_DIOA2_CTL_PD_SIZE              0x1
-#define GC_PINMUX_DIOA2_CTL_PD_DEFAULT           0x0
-#define GC_PINMUX_DIOA2_CTL_PD_OFFSET            0x3c
-#define GC_PINMUX_DIOA2_CTL_PU_LSB               0x4
-#define GC_PINMUX_DIOA2_CTL_PU_MASK              0x10
-#define GC_PINMUX_DIOA2_CTL_PU_SIZE              0x1
-#define GC_PINMUX_DIOA2_CTL_PU_DEFAULT           0x0
-#define GC_PINMUX_DIOA2_CTL_PU_OFFSET            0x3c
-#define GC_PINMUX_DIOA2_CTL_INV_LSB              0x5
-#define GC_PINMUX_DIOA2_CTL_INV_MASK             0x20
-#define GC_PINMUX_DIOA2_CTL_INV_SIZE             0x1
-#define GC_PINMUX_DIOA2_CTL_INV_DEFAULT          0x0
-#define GC_PINMUX_DIOA2_CTL_INV_OFFSET           0x3c
-#define GC_PINMUX_DIOA3_CTL_DS_LSB               0x0
-#define GC_PINMUX_DIOA3_CTL_DS_MASK              0x3
-#define GC_PINMUX_DIOA3_CTL_DS_SIZE              0x2
-#define GC_PINMUX_DIOA3_CTL_DS_DEFAULT           0x3
-#define GC_PINMUX_DIOA3_CTL_DS_OFFSET            0x44
-#define GC_PINMUX_DIOA3_CTL_IE_LSB               0x2
-#define GC_PINMUX_DIOA3_CTL_IE_MASK              0x4
-#define GC_PINMUX_DIOA3_CTL_IE_SIZE              0x1
-#define GC_PINMUX_DIOA3_CTL_IE_DEFAULT           0x0
-#define GC_PINMUX_DIOA3_CTL_IE_OFFSET            0x44
-#define GC_PINMUX_DIOA3_CTL_PD_LSB               0x3
-#define GC_PINMUX_DIOA3_CTL_PD_MASK              0x8
-#define GC_PINMUX_DIOA3_CTL_PD_SIZE              0x1
-#define GC_PINMUX_DIOA3_CTL_PD_DEFAULT           0x0
-#define GC_PINMUX_DIOA3_CTL_PD_OFFSET            0x44
-#define GC_PINMUX_DIOA3_CTL_PU_LSB               0x4
-#define GC_PINMUX_DIOA3_CTL_PU_MASK              0x10
-#define GC_PINMUX_DIOA3_CTL_PU_SIZE              0x1
-#define GC_PINMUX_DIOA3_CTL_PU_DEFAULT           0x0
-#define GC_PINMUX_DIOA3_CTL_PU_OFFSET            0x44
-#define GC_PINMUX_DIOA3_CTL_INV_LSB              0x5
-#define GC_PINMUX_DIOA3_CTL_INV_MASK             0x20
-#define GC_PINMUX_DIOA3_CTL_INV_SIZE             0x1
-#define GC_PINMUX_DIOA3_CTL_INV_DEFAULT          0x0
-#define GC_PINMUX_DIOA3_CTL_INV_OFFSET           0x44
-#define GC_PINMUX_DIOA4_CTL_DS_LSB               0x0
-#define GC_PINMUX_DIOA4_CTL_DS_MASK              0x3
-#define GC_PINMUX_DIOA4_CTL_DS_SIZE              0x2
-#define GC_PINMUX_DIOA4_CTL_DS_DEFAULT           0x3
-#define GC_PINMUX_DIOA4_CTL_DS_OFFSET            0x4c
-#define GC_PINMUX_DIOA4_CTL_IE_LSB               0x2
-#define GC_PINMUX_DIOA4_CTL_IE_MASK              0x4
-#define GC_PINMUX_DIOA4_CTL_IE_SIZE              0x1
-#define GC_PINMUX_DIOA4_CTL_IE_DEFAULT           0x0
-#define GC_PINMUX_DIOA4_CTL_IE_OFFSET            0x4c
-#define GC_PINMUX_DIOA4_CTL_PD_LSB               0x3
-#define GC_PINMUX_DIOA4_CTL_PD_MASK              0x8
-#define GC_PINMUX_DIOA4_CTL_PD_SIZE              0x1
-#define GC_PINMUX_DIOA4_CTL_PD_DEFAULT           0x0
-#define GC_PINMUX_DIOA4_CTL_PD_OFFSET            0x4c
-#define GC_PINMUX_DIOA4_CTL_PU_LSB               0x4
-#define GC_PINMUX_DIOA4_CTL_PU_MASK              0x10
-#define GC_PINMUX_DIOA4_CTL_PU_SIZE              0x1
-#define GC_PINMUX_DIOA4_CTL_PU_DEFAULT           0x0
-#define GC_PINMUX_DIOA4_CTL_PU_OFFSET            0x4c
-#define GC_PINMUX_DIOA4_CTL_INV_LSB              0x5
-#define GC_PINMUX_DIOA4_CTL_INV_MASK             0x20
-#define GC_PINMUX_DIOA4_CTL_INV_SIZE             0x1
-#define GC_PINMUX_DIOA4_CTL_INV_DEFAULT          0x0
-#define GC_PINMUX_DIOA4_CTL_INV_OFFSET           0x4c
-#define GC_PINMUX_DIOA5_CTL_DS_LSB               0x0
-#define GC_PINMUX_DIOA5_CTL_DS_MASK              0x3
-#define GC_PINMUX_DIOA5_CTL_DS_SIZE              0x2
-#define GC_PINMUX_DIOA5_CTL_DS_DEFAULT           0x3
-#define GC_PINMUX_DIOA5_CTL_DS_OFFSET            0x54
-#define GC_PINMUX_DIOA5_CTL_IE_LSB               0x2
-#define GC_PINMUX_DIOA5_CTL_IE_MASK              0x4
-#define GC_PINMUX_DIOA5_CTL_IE_SIZE              0x1
-#define GC_PINMUX_DIOA5_CTL_IE_DEFAULT           0x0
-#define GC_PINMUX_DIOA5_CTL_IE_OFFSET            0x54
-#define GC_PINMUX_DIOA5_CTL_PD_LSB               0x3
-#define GC_PINMUX_DIOA5_CTL_PD_MASK              0x8
-#define GC_PINMUX_DIOA5_CTL_PD_SIZE              0x1
-#define GC_PINMUX_DIOA5_CTL_PD_DEFAULT           0x0
-#define GC_PINMUX_DIOA5_CTL_PD_OFFSET            0x54
-#define GC_PINMUX_DIOA5_CTL_PU_LSB               0x4
-#define GC_PINMUX_DIOA5_CTL_PU_MASK              0x10
-#define GC_PINMUX_DIOA5_CTL_PU_SIZE              0x1
-#define GC_PINMUX_DIOA5_CTL_PU_DEFAULT           0x0
-#define GC_PINMUX_DIOA5_CTL_PU_OFFSET            0x54
-#define GC_PINMUX_DIOA5_CTL_INV_LSB              0x5
-#define GC_PINMUX_DIOA5_CTL_INV_MASK             0x20
-#define GC_PINMUX_DIOA5_CTL_INV_SIZE             0x1
-#define GC_PINMUX_DIOA5_CTL_INV_DEFAULT          0x0
-#define GC_PINMUX_DIOA5_CTL_INV_OFFSET           0x54
-#define GC_PINMUX_DIOA6_CTL_DS_LSB               0x0
-#define GC_PINMUX_DIOA6_CTL_DS_MASK              0x3
-#define GC_PINMUX_DIOA6_CTL_DS_SIZE              0x2
-#define GC_PINMUX_DIOA6_CTL_DS_DEFAULT           0x3
-#define GC_PINMUX_DIOA6_CTL_DS_OFFSET            0x5c
-#define GC_PINMUX_DIOA6_CTL_IE_LSB               0x2
-#define GC_PINMUX_DIOA6_CTL_IE_MASK              0x4
-#define GC_PINMUX_DIOA6_CTL_IE_SIZE              0x1
-#define GC_PINMUX_DIOA6_CTL_IE_DEFAULT           0x0
-#define GC_PINMUX_DIOA6_CTL_IE_OFFSET            0x5c
-#define GC_PINMUX_DIOA6_CTL_PD_LSB               0x3
-#define GC_PINMUX_DIOA6_CTL_PD_MASK              0x8
-#define GC_PINMUX_DIOA6_CTL_PD_SIZE              0x1
-#define GC_PINMUX_DIOA6_CTL_PD_DEFAULT           0x0
-#define GC_PINMUX_DIOA6_CTL_PD_OFFSET            0x5c
-#define GC_PINMUX_DIOA6_CTL_PU_LSB               0x4
-#define GC_PINMUX_DIOA6_CTL_PU_MASK              0x10
-#define GC_PINMUX_DIOA6_CTL_PU_SIZE              0x1
-#define GC_PINMUX_DIOA6_CTL_PU_DEFAULT           0x0
-#define GC_PINMUX_DIOA6_CTL_PU_OFFSET            0x5c
-#define GC_PINMUX_DIOA6_CTL_INV_LSB              0x5
-#define GC_PINMUX_DIOA6_CTL_INV_MASK             0x20
-#define GC_PINMUX_DIOA6_CTL_INV_SIZE             0x1
-#define GC_PINMUX_DIOA6_CTL_INV_DEFAULT          0x0
-#define GC_PINMUX_DIOA6_CTL_INV_OFFSET           0x5c
-#define GC_PINMUX_DIOA7_CTL_DS_LSB               0x0
-#define GC_PINMUX_DIOA7_CTL_DS_MASK              0x3
-#define GC_PINMUX_DIOA7_CTL_DS_SIZE              0x2
-#define GC_PINMUX_DIOA7_CTL_DS_DEFAULT           0x3
-#define GC_PINMUX_DIOA7_CTL_DS_OFFSET            0x64
-#define GC_PINMUX_DIOA7_CTL_IE_LSB               0x2
-#define GC_PINMUX_DIOA7_CTL_IE_MASK              0x4
-#define GC_PINMUX_DIOA7_CTL_IE_SIZE              0x1
-#define GC_PINMUX_DIOA7_CTL_IE_DEFAULT           0x0
-#define GC_PINMUX_DIOA7_CTL_IE_OFFSET            0x64
-#define GC_PINMUX_DIOA7_CTL_PD_LSB               0x3
-#define GC_PINMUX_DIOA7_CTL_PD_MASK              0x8
-#define GC_PINMUX_DIOA7_CTL_PD_SIZE              0x1
-#define GC_PINMUX_DIOA7_CTL_PD_DEFAULT           0x0
-#define GC_PINMUX_DIOA7_CTL_PD_OFFSET            0x64
-#define GC_PINMUX_DIOA7_CTL_PU_LSB               0x4
-#define GC_PINMUX_DIOA7_CTL_PU_MASK              0x10
-#define GC_PINMUX_DIOA7_CTL_PU_SIZE              0x1
-#define GC_PINMUX_DIOA7_CTL_PU_DEFAULT           0x0
-#define GC_PINMUX_DIOA7_CTL_PU_OFFSET            0x64
-#define GC_PINMUX_DIOA7_CTL_INV_LSB              0x5
-#define GC_PINMUX_DIOA7_CTL_INV_MASK             0x20
-#define GC_PINMUX_DIOA7_CTL_INV_SIZE             0x1
-#define GC_PINMUX_DIOA7_CTL_INV_DEFAULT          0x0
-#define GC_PINMUX_DIOA7_CTL_INV_OFFSET           0x64
-#define GC_PINMUX_DIOA8_CTL_DS_LSB               0x0
-#define GC_PINMUX_DIOA8_CTL_DS_MASK              0x3
-#define GC_PINMUX_DIOA8_CTL_DS_SIZE              0x2
-#define GC_PINMUX_DIOA8_CTL_DS_DEFAULT           0x3
-#define GC_PINMUX_DIOA8_CTL_DS_OFFSET            0x6c
-#define GC_PINMUX_DIOA8_CTL_IE_LSB               0x2
-#define GC_PINMUX_DIOA8_CTL_IE_MASK              0x4
-#define GC_PINMUX_DIOA8_CTL_IE_SIZE              0x1
-#define GC_PINMUX_DIOA8_CTL_IE_DEFAULT           0x0
-#define GC_PINMUX_DIOA8_CTL_IE_OFFSET            0x6c
-#define GC_PINMUX_DIOA8_CTL_PD_LSB               0x3
-#define GC_PINMUX_DIOA8_CTL_PD_MASK              0x8
-#define GC_PINMUX_DIOA8_CTL_PD_SIZE              0x1
-#define GC_PINMUX_DIOA8_CTL_PD_DEFAULT           0x0
-#define GC_PINMUX_DIOA8_CTL_PD_OFFSET            0x6c
-#define GC_PINMUX_DIOA8_CTL_PU_LSB               0x4
-#define GC_PINMUX_DIOA8_CTL_PU_MASK              0x10
-#define GC_PINMUX_DIOA8_CTL_PU_SIZE              0x1
-#define GC_PINMUX_DIOA8_CTL_PU_DEFAULT           0x0
-#define GC_PINMUX_DIOA8_CTL_PU_OFFSET            0x6c
-#define GC_PINMUX_DIOA8_CTL_INV_LSB              0x5
-#define GC_PINMUX_DIOA8_CTL_INV_MASK             0x20
-#define GC_PINMUX_DIOA8_CTL_INV_SIZE             0x1
-#define GC_PINMUX_DIOA8_CTL_INV_DEFAULT          0x0
-#define GC_PINMUX_DIOA8_CTL_INV_OFFSET           0x6c
-#define GC_PINMUX_DIOA9_CTL_DS_LSB               0x0
-#define GC_PINMUX_DIOA9_CTL_DS_MASK              0x3
-#define GC_PINMUX_DIOA9_CTL_DS_SIZE              0x2
-#define GC_PINMUX_DIOA9_CTL_DS_DEFAULT           0x3
-#define GC_PINMUX_DIOA9_CTL_DS_OFFSET            0x74
-#define GC_PINMUX_DIOA9_CTL_IE_LSB               0x2
-#define GC_PINMUX_DIOA9_CTL_IE_MASK              0x4
-#define GC_PINMUX_DIOA9_CTL_IE_SIZE              0x1
-#define GC_PINMUX_DIOA9_CTL_IE_DEFAULT           0x0
-#define GC_PINMUX_DIOA9_CTL_IE_OFFSET            0x74
-#define GC_PINMUX_DIOA9_CTL_PD_LSB               0x3
-#define GC_PINMUX_DIOA9_CTL_PD_MASK              0x8
-#define GC_PINMUX_DIOA9_CTL_PD_SIZE              0x1
-#define GC_PINMUX_DIOA9_CTL_PD_DEFAULT           0x0
-#define GC_PINMUX_DIOA9_CTL_PD_OFFSET            0x74
-#define GC_PINMUX_DIOA9_CTL_PU_LSB               0x4
-#define GC_PINMUX_DIOA9_CTL_PU_MASK              0x10
-#define GC_PINMUX_DIOA9_CTL_PU_SIZE              0x1
-#define GC_PINMUX_DIOA9_CTL_PU_DEFAULT           0x0
-#define GC_PINMUX_DIOA9_CTL_PU_OFFSET            0x74
-#define GC_PINMUX_DIOA9_CTL_INV_LSB              0x5
-#define GC_PINMUX_DIOA9_CTL_INV_MASK             0x20
-#define GC_PINMUX_DIOA9_CTL_INV_SIZE             0x1
-#define GC_PINMUX_DIOA9_CTL_INV_DEFAULT          0x0
-#define GC_PINMUX_DIOA9_CTL_INV_OFFSET           0x74
-#define GC_PINMUX_DIOA10_CTL_DS_LSB              0x0
-#define GC_PINMUX_DIOA10_CTL_DS_MASK             0x3
-#define GC_PINMUX_DIOA10_CTL_DS_SIZE             0x2
-#define GC_PINMUX_DIOA10_CTL_DS_DEFAULT          0x3
-#define GC_PINMUX_DIOA10_CTL_DS_OFFSET           0x7c
-#define GC_PINMUX_DIOA10_CTL_IE_LSB              0x2
-#define GC_PINMUX_DIOA10_CTL_IE_MASK             0x4
-#define GC_PINMUX_DIOA10_CTL_IE_SIZE             0x1
-#define GC_PINMUX_DIOA10_CTL_IE_DEFAULT          0x0
-#define GC_PINMUX_DIOA10_CTL_IE_OFFSET           0x7c
-#define GC_PINMUX_DIOA10_CTL_PD_LSB              0x3
-#define GC_PINMUX_DIOA10_CTL_PD_MASK             0x8
-#define GC_PINMUX_DIOA10_CTL_PD_SIZE             0x1
-#define GC_PINMUX_DIOA10_CTL_PD_DEFAULT          0x0
-#define GC_PINMUX_DIOA10_CTL_PD_OFFSET           0x7c
-#define GC_PINMUX_DIOA10_CTL_PU_LSB              0x4
-#define GC_PINMUX_DIOA10_CTL_PU_MASK             0x10
-#define GC_PINMUX_DIOA10_CTL_PU_SIZE             0x1
-#define GC_PINMUX_DIOA10_CTL_PU_DEFAULT          0x0
-#define GC_PINMUX_DIOA10_CTL_PU_OFFSET           0x7c
-#define GC_PINMUX_DIOA10_CTL_INV_LSB             0x5
-#define GC_PINMUX_DIOA10_CTL_INV_MASK            0x20
-#define GC_PINMUX_DIOA10_CTL_INV_SIZE            0x1
-#define GC_PINMUX_DIOA10_CTL_INV_DEFAULT         0x0
-#define GC_PINMUX_DIOA10_CTL_INV_OFFSET          0x7c
-#define GC_PINMUX_DIOA11_CTL_DS_LSB              0x0
-#define GC_PINMUX_DIOA11_CTL_DS_MASK             0x3
-#define GC_PINMUX_DIOA11_CTL_DS_SIZE             0x2
-#define GC_PINMUX_DIOA11_CTL_DS_DEFAULT          0x3
-#define GC_PINMUX_DIOA11_CTL_DS_OFFSET           0x84
-#define GC_PINMUX_DIOA11_CTL_IE_LSB              0x2
-#define GC_PINMUX_DIOA11_CTL_IE_MASK             0x4
-#define GC_PINMUX_DIOA11_CTL_IE_SIZE             0x1
-#define GC_PINMUX_DIOA11_CTL_IE_DEFAULT          0x0
-#define GC_PINMUX_DIOA11_CTL_IE_OFFSET           0x84
-#define GC_PINMUX_DIOA11_CTL_PD_LSB              0x3
-#define GC_PINMUX_DIOA11_CTL_PD_MASK             0x8
-#define GC_PINMUX_DIOA11_CTL_PD_SIZE             0x1
-#define GC_PINMUX_DIOA11_CTL_PD_DEFAULT          0x0
-#define GC_PINMUX_DIOA11_CTL_PD_OFFSET           0x84
-#define GC_PINMUX_DIOA11_CTL_PU_LSB              0x4
-#define GC_PINMUX_DIOA11_CTL_PU_MASK             0x10
-#define GC_PINMUX_DIOA11_CTL_PU_SIZE             0x1
-#define GC_PINMUX_DIOA11_CTL_PU_DEFAULT          0x0
-#define GC_PINMUX_DIOA11_CTL_PU_OFFSET           0x84
-#define GC_PINMUX_DIOA11_CTL_INV_LSB             0x5
-#define GC_PINMUX_DIOA11_CTL_INV_MASK            0x20
-#define GC_PINMUX_DIOA11_CTL_INV_SIZE            0x1
-#define GC_PINMUX_DIOA11_CTL_INV_DEFAULT         0x0
-#define GC_PINMUX_DIOA11_CTL_INV_OFFSET          0x84
-#define GC_PINMUX_DIOA12_CTL_DS_LSB              0x0
-#define GC_PINMUX_DIOA12_CTL_DS_MASK             0x3
-#define GC_PINMUX_DIOA12_CTL_DS_SIZE             0x2
-#define GC_PINMUX_DIOA12_CTL_DS_DEFAULT          0x3
-#define GC_PINMUX_DIOA12_CTL_DS_OFFSET           0x8c
-#define GC_PINMUX_DIOA12_CTL_IE_LSB              0x2
-#define GC_PINMUX_DIOA12_CTL_IE_MASK             0x4
-#define GC_PINMUX_DIOA12_CTL_IE_SIZE             0x1
-#define GC_PINMUX_DIOA12_CTL_IE_DEFAULT          0x0
-#define GC_PINMUX_DIOA12_CTL_IE_OFFSET           0x8c
-#define GC_PINMUX_DIOA12_CTL_PD_LSB              0x3
-#define GC_PINMUX_DIOA12_CTL_PD_MASK             0x8
-#define GC_PINMUX_DIOA12_CTL_PD_SIZE             0x1
-#define GC_PINMUX_DIOA12_CTL_PD_DEFAULT          0x0
-#define GC_PINMUX_DIOA12_CTL_PD_OFFSET           0x8c
-#define GC_PINMUX_DIOA12_CTL_PU_LSB              0x4
-#define GC_PINMUX_DIOA12_CTL_PU_MASK             0x10
-#define GC_PINMUX_DIOA12_CTL_PU_SIZE             0x1
-#define GC_PINMUX_DIOA12_CTL_PU_DEFAULT          0x0
-#define GC_PINMUX_DIOA12_CTL_PU_OFFSET           0x8c
-#define GC_PINMUX_DIOA12_CTL_INV_LSB             0x5
-#define GC_PINMUX_DIOA12_CTL_INV_MASK            0x20
-#define GC_PINMUX_DIOA12_CTL_INV_SIZE            0x1
-#define GC_PINMUX_DIOA12_CTL_INV_DEFAULT         0x0
-#define GC_PINMUX_DIOA12_CTL_INV_OFFSET          0x8c
-#define GC_PINMUX_DIOA13_CTL_DS_LSB              0x0
-#define GC_PINMUX_DIOA13_CTL_DS_MASK             0x3
-#define GC_PINMUX_DIOA13_CTL_DS_SIZE             0x2
-#define GC_PINMUX_DIOA13_CTL_DS_DEFAULT          0x3
-#define GC_PINMUX_DIOA13_CTL_DS_OFFSET           0x94
-#define GC_PINMUX_DIOA13_CTL_IE_LSB              0x2
-#define GC_PINMUX_DIOA13_CTL_IE_MASK             0x4
-#define GC_PINMUX_DIOA13_CTL_IE_SIZE             0x1
-#define GC_PINMUX_DIOA13_CTL_IE_DEFAULT          0x0
-#define GC_PINMUX_DIOA13_CTL_IE_OFFSET           0x94
-#define GC_PINMUX_DIOA13_CTL_PD_LSB              0x3
-#define GC_PINMUX_DIOA13_CTL_PD_MASK             0x8
-#define GC_PINMUX_DIOA13_CTL_PD_SIZE             0x1
-#define GC_PINMUX_DIOA13_CTL_PD_DEFAULT          0x0
-#define GC_PINMUX_DIOA13_CTL_PD_OFFSET           0x94
-#define GC_PINMUX_DIOA13_CTL_PU_LSB              0x4
-#define GC_PINMUX_DIOA13_CTL_PU_MASK             0x10
-#define GC_PINMUX_DIOA13_CTL_PU_SIZE             0x1
-#define GC_PINMUX_DIOA13_CTL_PU_DEFAULT          0x0
-#define GC_PINMUX_DIOA13_CTL_PU_OFFSET           0x94
-#define GC_PINMUX_DIOA13_CTL_INV_LSB             0x5
-#define GC_PINMUX_DIOA13_CTL_INV_MASK            0x20
-#define GC_PINMUX_DIOA13_CTL_INV_SIZE            0x1
-#define GC_PINMUX_DIOA13_CTL_INV_DEFAULT         0x0
-#define GC_PINMUX_DIOA13_CTL_INV_OFFSET          0x94
-#define GC_PINMUX_DIOA14_CTL_DS_LSB              0x0
-#define GC_PINMUX_DIOA14_CTL_DS_MASK             0x3
-#define GC_PINMUX_DIOA14_CTL_DS_SIZE             0x2
-#define GC_PINMUX_DIOA14_CTL_DS_DEFAULT          0x3
-#define GC_PINMUX_DIOA14_CTL_DS_OFFSET           0x9c
-#define GC_PINMUX_DIOA14_CTL_IE_LSB              0x2
-#define GC_PINMUX_DIOA14_CTL_IE_MASK             0x4
-#define GC_PINMUX_DIOA14_CTL_IE_SIZE             0x1
-#define GC_PINMUX_DIOA14_CTL_IE_DEFAULT          0x0
-#define GC_PINMUX_DIOA14_CTL_IE_OFFSET           0x9c
-#define GC_PINMUX_DIOA14_CTL_PD_LSB              0x3
-#define GC_PINMUX_DIOA14_CTL_PD_MASK             0x8
-#define GC_PINMUX_DIOA14_CTL_PD_SIZE             0x1
-#define GC_PINMUX_DIOA14_CTL_PD_DEFAULT          0x0
-#define GC_PINMUX_DIOA14_CTL_PD_OFFSET           0x9c
-#define GC_PINMUX_DIOA14_CTL_PU_LSB              0x4
-#define GC_PINMUX_DIOA14_CTL_PU_MASK             0x10
-#define GC_PINMUX_DIOA14_CTL_PU_SIZE             0x1
-#define GC_PINMUX_DIOA14_CTL_PU_DEFAULT          0x0
-#define GC_PINMUX_DIOA14_CTL_PU_OFFSET           0x9c
-#define GC_PINMUX_DIOA14_CTL_INV_LSB             0x5
-#define GC_PINMUX_DIOA14_CTL_INV_MASK            0x20
-#define GC_PINMUX_DIOA14_CTL_INV_SIZE            0x1
-#define GC_PINMUX_DIOA14_CTL_INV_DEFAULT         0x0
-#define GC_PINMUX_DIOA14_CTL_INV_OFFSET          0x9c
-#define GC_PINMUX_DIOB0_CTL_DS_LSB               0x0
-#define GC_PINMUX_DIOB0_CTL_DS_MASK              0x3
-#define GC_PINMUX_DIOB0_CTL_DS_SIZE              0x2
-#define GC_PINMUX_DIOB0_CTL_DS_DEFAULT           0x3
-#define GC_PINMUX_DIOB0_CTL_DS_OFFSET            0xa4
-#define GC_PINMUX_DIOB0_CTL_IE_LSB               0x2
-#define GC_PINMUX_DIOB0_CTL_IE_MASK              0x4
-#define GC_PINMUX_DIOB0_CTL_IE_SIZE              0x1
-#define GC_PINMUX_DIOB0_CTL_IE_DEFAULT           0x0
-#define GC_PINMUX_DIOB0_CTL_IE_OFFSET            0xa4
-#define GC_PINMUX_DIOB0_CTL_PD_LSB               0x3
-#define GC_PINMUX_DIOB0_CTL_PD_MASK              0x8
-#define GC_PINMUX_DIOB0_CTL_PD_SIZE              0x1
-#define GC_PINMUX_DIOB0_CTL_PD_DEFAULT           0x0
-#define GC_PINMUX_DIOB0_CTL_PD_OFFSET            0xa4
-#define GC_PINMUX_DIOB0_CTL_PU_LSB               0x4
-#define GC_PINMUX_DIOB0_CTL_PU_MASK              0x10
-#define GC_PINMUX_DIOB0_CTL_PU_SIZE              0x1
-#define GC_PINMUX_DIOB0_CTL_PU_DEFAULT           0x0
-#define GC_PINMUX_DIOB0_CTL_PU_OFFSET            0xa4
-#define GC_PINMUX_DIOB0_CTL_INV_LSB              0x5
-#define GC_PINMUX_DIOB0_CTL_INV_MASK             0x20
-#define GC_PINMUX_DIOB0_CTL_INV_SIZE             0x1
-#define GC_PINMUX_DIOB0_CTL_INV_DEFAULT          0x0
-#define GC_PINMUX_DIOB0_CTL_INV_OFFSET           0xa4
-#define GC_PINMUX_DIOB1_CTL_DS_LSB               0x0
-#define GC_PINMUX_DIOB1_CTL_DS_MASK              0x3
-#define GC_PINMUX_DIOB1_CTL_DS_SIZE              0x2
-#define GC_PINMUX_DIOB1_CTL_DS_DEFAULT           0x3
-#define GC_PINMUX_DIOB1_CTL_DS_OFFSET            0xac
-#define GC_PINMUX_DIOB1_CTL_IE_LSB               0x2
-#define GC_PINMUX_DIOB1_CTL_IE_MASK              0x4
-#define GC_PINMUX_DIOB1_CTL_IE_SIZE              0x1
-#define GC_PINMUX_DIOB1_CTL_IE_DEFAULT           0x0
-#define GC_PINMUX_DIOB1_CTL_IE_OFFSET            0xac
-#define GC_PINMUX_DIOB1_CTL_PD_LSB               0x3
-#define GC_PINMUX_DIOB1_CTL_PD_MASK              0x8
-#define GC_PINMUX_DIOB1_CTL_PD_SIZE              0x1
-#define GC_PINMUX_DIOB1_CTL_PD_DEFAULT           0x0
-#define GC_PINMUX_DIOB1_CTL_PD_OFFSET            0xac
-#define GC_PINMUX_DIOB1_CTL_PU_LSB               0x4
-#define GC_PINMUX_DIOB1_CTL_PU_MASK              0x10
-#define GC_PINMUX_DIOB1_CTL_PU_SIZE              0x1
-#define GC_PINMUX_DIOB1_CTL_PU_DEFAULT           0x0
-#define GC_PINMUX_DIOB1_CTL_PU_OFFSET            0xac
-#define GC_PINMUX_DIOB1_CTL_INV_LSB              0x5
-#define GC_PINMUX_DIOB1_CTL_INV_MASK             0x20
-#define GC_PINMUX_DIOB1_CTL_INV_SIZE             0x1
-#define GC_PINMUX_DIOB1_CTL_INV_DEFAULT          0x0
-#define GC_PINMUX_DIOB1_CTL_INV_OFFSET           0xac
-#define GC_PINMUX_DIOB2_CTL_DS_LSB               0x0
-#define GC_PINMUX_DIOB2_CTL_DS_MASK              0x3
-#define GC_PINMUX_DIOB2_CTL_DS_SIZE              0x2
-#define GC_PINMUX_DIOB2_CTL_DS_DEFAULT           0x3
-#define GC_PINMUX_DIOB2_CTL_DS_OFFSET            0xb4
-#define GC_PINMUX_DIOB2_CTL_IE_LSB               0x2
-#define GC_PINMUX_DIOB2_CTL_IE_MASK              0x4
-#define GC_PINMUX_DIOB2_CTL_IE_SIZE              0x1
-#define GC_PINMUX_DIOB2_CTL_IE_DEFAULT           0x0
-#define GC_PINMUX_DIOB2_CTL_IE_OFFSET            0xb4
-#define GC_PINMUX_DIOB2_CTL_PD_LSB               0x3
-#define GC_PINMUX_DIOB2_CTL_PD_MASK              0x8
-#define GC_PINMUX_DIOB2_CTL_PD_SIZE              0x1
-#define GC_PINMUX_DIOB2_CTL_PD_DEFAULT           0x0
-#define GC_PINMUX_DIOB2_CTL_PD_OFFSET            0xb4
-#define GC_PINMUX_DIOB2_CTL_PU_LSB               0x4
-#define GC_PINMUX_DIOB2_CTL_PU_MASK              0x10
-#define GC_PINMUX_DIOB2_CTL_PU_SIZE              0x1
-#define GC_PINMUX_DIOB2_CTL_PU_DEFAULT           0x0
-#define GC_PINMUX_DIOB2_CTL_PU_OFFSET            0xb4
-#define GC_PINMUX_DIOB2_CTL_INV_LSB              0x5
-#define GC_PINMUX_DIOB2_CTL_INV_MASK             0x20
-#define GC_PINMUX_DIOB2_CTL_INV_SIZE             0x1
-#define GC_PINMUX_DIOB2_CTL_INV_DEFAULT          0x0
-#define GC_PINMUX_DIOB2_CTL_INV_OFFSET           0xb4
-#define GC_PINMUX_DIOB3_CTL_DS_LSB               0x0
-#define GC_PINMUX_DIOB3_CTL_DS_MASK              0x3
-#define GC_PINMUX_DIOB3_CTL_DS_SIZE              0x2
-#define GC_PINMUX_DIOB3_CTL_DS_DEFAULT           0x3
-#define GC_PINMUX_DIOB3_CTL_DS_OFFSET            0xbc
-#define GC_PINMUX_DIOB3_CTL_IE_LSB               0x2
-#define GC_PINMUX_DIOB3_CTL_IE_MASK              0x4
-#define GC_PINMUX_DIOB3_CTL_IE_SIZE              0x1
-#define GC_PINMUX_DIOB3_CTL_IE_DEFAULT           0x0
-#define GC_PINMUX_DIOB3_CTL_IE_OFFSET            0xbc
-#define GC_PINMUX_DIOB3_CTL_PD_LSB               0x3
-#define GC_PINMUX_DIOB3_CTL_PD_MASK              0x8
-#define GC_PINMUX_DIOB3_CTL_PD_SIZE              0x1
-#define GC_PINMUX_DIOB3_CTL_PD_DEFAULT           0x0
-#define GC_PINMUX_DIOB3_CTL_PD_OFFSET            0xbc
-#define GC_PINMUX_DIOB3_CTL_PU_LSB               0x4
-#define GC_PINMUX_DIOB3_CTL_PU_MASK              0x10
-#define GC_PINMUX_DIOB3_CTL_PU_SIZE              0x1
-#define GC_PINMUX_DIOB3_CTL_PU_DEFAULT           0x0
-#define GC_PINMUX_DIOB3_CTL_PU_OFFSET            0xbc
-#define GC_PINMUX_DIOB3_CTL_INV_LSB              0x5
-#define GC_PINMUX_DIOB3_CTL_INV_MASK             0x20
-#define GC_PINMUX_DIOB3_CTL_INV_SIZE             0x1
-#define GC_PINMUX_DIOB3_CTL_INV_DEFAULT          0x0
-#define GC_PINMUX_DIOB3_CTL_INV_OFFSET           0xbc
-#define GC_PINMUX_DIOB4_CTL_DS_LSB               0x0
-#define GC_PINMUX_DIOB4_CTL_DS_MASK              0x3
-#define GC_PINMUX_DIOB4_CTL_DS_SIZE              0x2
-#define GC_PINMUX_DIOB4_CTL_DS_DEFAULT           0x3
-#define GC_PINMUX_DIOB4_CTL_DS_OFFSET            0xc4
-#define GC_PINMUX_DIOB4_CTL_IE_LSB               0x2
-#define GC_PINMUX_DIOB4_CTL_IE_MASK              0x4
-#define GC_PINMUX_DIOB4_CTL_IE_SIZE              0x1
-#define GC_PINMUX_DIOB4_CTL_IE_DEFAULT           0x0
-#define GC_PINMUX_DIOB4_CTL_IE_OFFSET            0xc4
-#define GC_PINMUX_DIOB4_CTL_PD_LSB               0x3
-#define GC_PINMUX_DIOB4_CTL_PD_MASK              0x8
-#define GC_PINMUX_DIOB4_CTL_PD_SIZE              0x1
-#define GC_PINMUX_DIOB4_CTL_PD_DEFAULT           0x0
-#define GC_PINMUX_DIOB4_CTL_PD_OFFSET            0xc4
-#define GC_PINMUX_DIOB4_CTL_PU_LSB               0x4
-#define GC_PINMUX_DIOB4_CTL_PU_MASK              0x10
-#define GC_PINMUX_DIOB4_CTL_PU_SIZE              0x1
-#define GC_PINMUX_DIOB4_CTL_PU_DEFAULT           0x0
-#define GC_PINMUX_DIOB4_CTL_PU_OFFSET            0xc4
-#define GC_PINMUX_DIOB4_CTL_INV_LSB              0x5
-#define GC_PINMUX_DIOB4_CTL_INV_MASK             0x20
-#define GC_PINMUX_DIOB4_CTL_INV_SIZE             0x1
-#define GC_PINMUX_DIOB4_CTL_INV_DEFAULT          0x0
-#define GC_PINMUX_DIOB4_CTL_INV_OFFSET           0xc4
-#define GC_PINMUX_DIOB5_CTL_DS_LSB               0x0
-#define GC_PINMUX_DIOB5_CTL_DS_MASK              0x3
-#define GC_PINMUX_DIOB5_CTL_DS_SIZE              0x2
-#define GC_PINMUX_DIOB5_CTL_DS_DEFAULT           0x3
-#define GC_PINMUX_DIOB5_CTL_DS_OFFSET            0xcc
-#define GC_PINMUX_DIOB5_CTL_IE_LSB               0x2
-#define GC_PINMUX_DIOB5_CTL_IE_MASK              0x4
-#define GC_PINMUX_DIOB5_CTL_IE_SIZE              0x1
-#define GC_PINMUX_DIOB5_CTL_IE_DEFAULT           0x0
-#define GC_PINMUX_DIOB5_CTL_IE_OFFSET            0xcc
-#define GC_PINMUX_DIOB5_CTL_PD_LSB               0x3
-#define GC_PINMUX_DIOB5_CTL_PD_MASK              0x8
-#define GC_PINMUX_DIOB5_CTL_PD_SIZE              0x1
-#define GC_PINMUX_DIOB5_CTL_PD_DEFAULT           0x0
-#define GC_PINMUX_DIOB5_CTL_PD_OFFSET            0xcc
-#define GC_PINMUX_DIOB5_CTL_PU_LSB               0x4
-#define GC_PINMUX_DIOB5_CTL_PU_MASK              0x10
-#define GC_PINMUX_DIOB5_CTL_PU_SIZE              0x1
-#define GC_PINMUX_DIOB5_CTL_PU_DEFAULT           0x0
-#define GC_PINMUX_DIOB5_CTL_PU_OFFSET            0xcc
-#define GC_PINMUX_DIOB5_CTL_INV_LSB              0x5
-#define GC_PINMUX_DIOB5_CTL_INV_MASK             0x20
-#define GC_PINMUX_DIOB5_CTL_INV_SIZE             0x1
-#define GC_PINMUX_DIOB5_CTL_INV_DEFAULT          0x0
-#define GC_PINMUX_DIOB5_CTL_INV_OFFSET           0xcc
-#define GC_PINMUX_DIOB6_CTL_DS_LSB               0x0
-#define GC_PINMUX_DIOB6_CTL_DS_MASK              0x3
-#define GC_PINMUX_DIOB6_CTL_DS_SIZE              0x2
-#define GC_PINMUX_DIOB6_CTL_DS_DEFAULT           0x3
-#define GC_PINMUX_DIOB6_CTL_DS_OFFSET            0xd4
-#define GC_PINMUX_DIOB6_CTL_IE_LSB               0x2
-#define GC_PINMUX_DIOB6_CTL_IE_MASK              0x4
-#define GC_PINMUX_DIOB6_CTL_IE_SIZE              0x1
-#define GC_PINMUX_DIOB6_CTL_IE_DEFAULT           0x0
-#define GC_PINMUX_DIOB6_CTL_IE_OFFSET            0xd4
-#define GC_PINMUX_DIOB6_CTL_PD_LSB               0x3
-#define GC_PINMUX_DIOB6_CTL_PD_MASK              0x8
-#define GC_PINMUX_DIOB6_CTL_PD_SIZE              0x1
-#define GC_PINMUX_DIOB6_CTL_PD_DEFAULT           0x0
-#define GC_PINMUX_DIOB6_CTL_PD_OFFSET            0xd4
-#define GC_PINMUX_DIOB6_CTL_PU_LSB               0x4
-#define GC_PINMUX_DIOB6_CTL_PU_MASK              0x10
-#define GC_PINMUX_DIOB6_CTL_PU_SIZE              0x1
-#define GC_PINMUX_DIOB6_CTL_PU_DEFAULT           0x0
-#define GC_PINMUX_DIOB6_CTL_PU_OFFSET            0xd4
-#define GC_PINMUX_DIOB6_CTL_INV_LSB              0x5
-#define GC_PINMUX_DIOB6_CTL_INV_MASK             0x20
-#define GC_PINMUX_DIOB6_CTL_INV_SIZE             0x1
-#define GC_PINMUX_DIOB6_CTL_INV_DEFAULT          0x0
-#define GC_PINMUX_DIOB6_CTL_INV_OFFSET           0xd4
-#define GC_PINMUX_DIOB7_CTL_DS_LSB               0x0
-#define GC_PINMUX_DIOB7_CTL_DS_MASK              0x3
-#define GC_PINMUX_DIOB7_CTL_DS_SIZE              0x2
-#define GC_PINMUX_DIOB7_CTL_DS_DEFAULT           0x3
-#define GC_PINMUX_DIOB7_CTL_DS_OFFSET            0xdc
-#define GC_PINMUX_DIOB7_CTL_IE_LSB               0x2
-#define GC_PINMUX_DIOB7_CTL_IE_MASK              0x4
-#define GC_PINMUX_DIOB7_CTL_IE_SIZE              0x1
-#define GC_PINMUX_DIOB7_CTL_IE_DEFAULT           0x0
-#define GC_PINMUX_DIOB7_CTL_IE_OFFSET            0xdc
-#define GC_PINMUX_DIOB7_CTL_PD_LSB               0x3
-#define GC_PINMUX_DIOB7_CTL_PD_MASK              0x8
-#define GC_PINMUX_DIOB7_CTL_PD_SIZE              0x1
-#define GC_PINMUX_DIOB7_CTL_PD_DEFAULT           0x0
-#define GC_PINMUX_DIOB7_CTL_PD_OFFSET            0xdc
-#define GC_PINMUX_DIOB7_CTL_PU_LSB               0x4
-#define GC_PINMUX_DIOB7_CTL_PU_MASK              0x10
-#define GC_PINMUX_DIOB7_CTL_PU_SIZE              0x1
-#define GC_PINMUX_DIOB7_CTL_PU_DEFAULT           0x0
-#define GC_PINMUX_DIOB7_CTL_PU_OFFSET            0xdc
-#define GC_PINMUX_DIOB7_CTL_INV_LSB              0x5
-#define GC_PINMUX_DIOB7_CTL_INV_MASK             0x20
-#define GC_PINMUX_DIOB7_CTL_INV_SIZE             0x1
-#define GC_PINMUX_DIOB7_CTL_INV_DEFAULT          0x0
-#define GC_PINMUX_DIOB7_CTL_INV_OFFSET           0xdc
-#define GC_PINMUX_RESETB_CTL_DS_LSB              0x0
-#define GC_PINMUX_RESETB_CTL_DS_MASK             0x3
-#define GC_PINMUX_RESETB_CTL_DS_SIZE             0x2
-#define GC_PINMUX_RESETB_CTL_DS_DEFAULT          0x3
-#define GC_PINMUX_RESETB_CTL_DS_OFFSET           0xe4
-#define GC_PINMUX_RESETB_CTL_IE_LSB              0x2
-#define GC_PINMUX_RESETB_CTL_IE_MASK             0x4
-#define GC_PINMUX_RESETB_CTL_IE_SIZE             0x1
-#define GC_PINMUX_RESETB_CTL_IE_DEFAULT          0x1
-#define GC_PINMUX_RESETB_CTL_IE_OFFSET           0xe4
-#define GC_PINMUX_RESETB_CTL_PD_LSB              0x3
-#define GC_PINMUX_RESETB_CTL_PD_MASK             0x8
-#define GC_PINMUX_RESETB_CTL_PD_SIZE             0x1
-#define GC_PINMUX_RESETB_CTL_PD_DEFAULT          0x0
-#define GC_PINMUX_RESETB_CTL_PD_OFFSET           0xe4
-#define GC_PINMUX_RESETB_CTL_PU_LSB              0x4
-#define GC_PINMUX_RESETB_CTL_PU_MASK             0x10
-#define GC_PINMUX_RESETB_CTL_PU_SIZE             0x1
-#define GC_PINMUX_RESETB_CTL_PU_DEFAULT          0x0
-#define GC_PINMUX_RESETB_CTL_PU_OFFSET           0xe4
-#define GC_PINMUX_RESETB_CTL_INV_LSB             0x5
-#define GC_PINMUX_RESETB_CTL_INV_MASK            0x20
-#define GC_PINMUX_RESETB_CTL_INV_SIZE            0x1
-#define GC_PINMUX_RESETB_CTL_INV_DEFAULT         0x0
-#define GC_PINMUX_RESETB_CTL_INV_OFFSET          0xe4
-#define GC_PINMUX_VIO0_CTL_DS_LSB                0x0
-#define GC_PINMUX_VIO0_CTL_DS_MASK               0x3
-#define GC_PINMUX_VIO0_CTL_DS_SIZE               0x2
-#define GC_PINMUX_VIO0_CTL_DS_DEFAULT            0x3
-#define GC_PINMUX_VIO0_CTL_DS_OFFSET             0xec
-#define GC_PINMUX_VIO0_CTL_IE_LSB                0x2
-#define GC_PINMUX_VIO0_CTL_IE_MASK               0x4
-#define GC_PINMUX_VIO0_CTL_IE_SIZE               0x1
-#define GC_PINMUX_VIO0_CTL_IE_DEFAULT            0x0
-#define GC_PINMUX_VIO0_CTL_IE_OFFSET             0xec
-#define GC_PINMUX_VIO0_CTL_PD_LSB                0x3
-#define GC_PINMUX_VIO0_CTL_PD_MASK               0x8
-#define GC_PINMUX_VIO0_CTL_PD_SIZE               0x1
-#define GC_PINMUX_VIO0_CTL_PD_DEFAULT            0x0
-#define GC_PINMUX_VIO0_CTL_PD_OFFSET             0xec
-#define GC_PINMUX_VIO0_CTL_PU_LSB                0x4
-#define GC_PINMUX_VIO0_CTL_PU_MASK               0x10
-#define GC_PINMUX_VIO0_CTL_PU_SIZE               0x1
-#define GC_PINMUX_VIO0_CTL_PU_DEFAULT            0x0
-#define GC_PINMUX_VIO0_CTL_PU_OFFSET             0xec
-#define GC_PINMUX_VIO0_CTL_INV_LSB               0x5
-#define GC_PINMUX_VIO0_CTL_INV_MASK              0x20
-#define GC_PINMUX_VIO0_CTL_INV_SIZE              0x1
-#define GC_PINMUX_VIO0_CTL_INV_DEFAULT           0x0
-#define GC_PINMUX_VIO0_CTL_INV_OFFSET            0xec
-#define GC_PINMUX_VIO1_CTL_DS_LSB                0x0
-#define GC_PINMUX_VIO1_CTL_DS_MASK               0x3
-#define GC_PINMUX_VIO1_CTL_DS_SIZE               0x2
-#define GC_PINMUX_VIO1_CTL_DS_DEFAULT            0x3
-#define GC_PINMUX_VIO1_CTL_DS_OFFSET             0xf4
-#define GC_PINMUX_VIO1_CTL_IE_LSB                0x2
-#define GC_PINMUX_VIO1_CTL_IE_MASK               0x4
-#define GC_PINMUX_VIO1_CTL_IE_SIZE               0x1
-#define GC_PINMUX_VIO1_CTL_IE_DEFAULT            0x0
-#define GC_PINMUX_VIO1_CTL_IE_OFFSET             0xf4
-#define GC_PINMUX_VIO1_CTL_PD_LSB                0x3
-#define GC_PINMUX_VIO1_CTL_PD_MASK               0x8
-#define GC_PINMUX_VIO1_CTL_PD_SIZE               0x1
-#define GC_PINMUX_VIO1_CTL_PD_DEFAULT            0x0
-#define GC_PINMUX_VIO1_CTL_PD_OFFSET             0xf4
-#define GC_PINMUX_VIO1_CTL_PU_LSB                0x4
-#define GC_PINMUX_VIO1_CTL_PU_MASK               0x10
-#define GC_PINMUX_VIO1_CTL_PU_SIZE               0x1
-#define GC_PINMUX_VIO1_CTL_PU_DEFAULT            0x0
-#define GC_PINMUX_VIO1_CTL_PU_OFFSET             0xf4
-#define GC_PINMUX_VIO1_CTL_INV_LSB               0x5
-#define GC_PINMUX_VIO1_CTL_INV_MASK              0x20
-#define GC_PINMUX_VIO1_CTL_INV_SIZE              0x1
-#define GC_PINMUX_VIO1_CTL_INV_DEFAULT           0x0
-#define GC_PINMUX_VIO1_CTL_INV_OFFSET            0xf4
-#define GC_PINMUX_EXITEN0_DIOM0_LSB              0x0
-#define GC_PINMUX_EXITEN0_DIOM0_MASK             0x1
-#define GC_PINMUX_EXITEN0_DIOM0_SIZE             0x1
-#define GC_PINMUX_EXITEN0_DIOM0_DEFAULT          0x0
-#define GC_PINMUX_EXITEN0_DIOM0_OFFSET           0x284
-#define GC_PINMUX_EXITEN0_DIOM1_LSB              0x1
-#define GC_PINMUX_EXITEN0_DIOM1_MASK             0x2
-#define GC_PINMUX_EXITEN0_DIOM1_SIZE             0x1
-#define GC_PINMUX_EXITEN0_DIOM1_DEFAULT          0x0
-#define GC_PINMUX_EXITEN0_DIOM1_OFFSET           0x284
-#define GC_PINMUX_EXITEN0_DIOM2_LSB              0x2
-#define GC_PINMUX_EXITEN0_DIOM2_MASK             0x4
-#define GC_PINMUX_EXITEN0_DIOM2_SIZE             0x1
-#define GC_PINMUX_EXITEN0_DIOM2_DEFAULT          0x0
-#define GC_PINMUX_EXITEN0_DIOM2_OFFSET           0x284
-#define GC_PINMUX_EXITEN0_DIOM3_LSB              0x3
-#define GC_PINMUX_EXITEN0_DIOM3_MASK             0x8
-#define GC_PINMUX_EXITEN0_DIOM3_SIZE             0x1
-#define GC_PINMUX_EXITEN0_DIOM3_DEFAULT          0x0
-#define GC_PINMUX_EXITEN0_DIOM3_OFFSET           0x284
-#define GC_PINMUX_EXITEN0_DIOM4_LSB              0x4
-#define GC_PINMUX_EXITEN0_DIOM4_MASK             0x10
-#define GC_PINMUX_EXITEN0_DIOM4_SIZE             0x1
-#define GC_PINMUX_EXITEN0_DIOM4_DEFAULT          0x0
-#define GC_PINMUX_EXITEN0_DIOM4_OFFSET           0x284
-#define GC_PINMUX_EXITEN0_DIOA0_LSB              0x5
-#define GC_PINMUX_EXITEN0_DIOA0_MASK             0x20
-#define GC_PINMUX_EXITEN0_DIOA0_SIZE             0x1
-#define GC_PINMUX_EXITEN0_DIOA0_DEFAULT          0x0
-#define GC_PINMUX_EXITEN0_DIOA0_OFFSET           0x284
-#define GC_PINMUX_EXITEN0_DIOA1_LSB              0x6
-#define GC_PINMUX_EXITEN0_DIOA1_MASK             0x40
-#define GC_PINMUX_EXITEN0_DIOA1_SIZE             0x1
-#define GC_PINMUX_EXITEN0_DIOA1_DEFAULT          0x0
-#define GC_PINMUX_EXITEN0_DIOA1_OFFSET           0x284
-#define GC_PINMUX_EXITEN0_DIOA2_LSB              0x7
-#define GC_PINMUX_EXITEN0_DIOA2_MASK             0x80
-#define GC_PINMUX_EXITEN0_DIOA2_SIZE             0x1
-#define GC_PINMUX_EXITEN0_DIOA2_DEFAULT          0x0
-#define GC_PINMUX_EXITEN0_DIOA2_OFFSET           0x284
-#define GC_PINMUX_EXITEN0_DIOA3_LSB              0x8
-#define GC_PINMUX_EXITEN0_DIOA3_MASK             0x100
-#define GC_PINMUX_EXITEN0_DIOA3_SIZE             0x1
-#define GC_PINMUX_EXITEN0_DIOA3_DEFAULT          0x0
-#define GC_PINMUX_EXITEN0_DIOA3_OFFSET           0x284
-#define GC_PINMUX_EXITEN0_DIOA4_LSB              0x9
-#define GC_PINMUX_EXITEN0_DIOA4_MASK             0x200
-#define GC_PINMUX_EXITEN0_DIOA4_SIZE             0x1
-#define GC_PINMUX_EXITEN0_DIOA4_DEFAULT          0x0
-#define GC_PINMUX_EXITEN0_DIOA4_OFFSET           0x284
-#define GC_PINMUX_EXITEN0_DIOA5_LSB              0xa
-#define GC_PINMUX_EXITEN0_DIOA5_MASK             0x400
-#define GC_PINMUX_EXITEN0_DIOA5_SIZE             0x1
-#define GC_PINMUX_EXITEN0_DIOA5_DEFAULT          0x0
-#define GC_PINMUX_EXITEN0_DIOA5_OFFSET           0x284
-#define GC_PINMUX_EXITEN0_DIOA6_LSB              0xb
-#define GC_PINMUX_EXITEN0_DIOA6_MASK             0x800
-#define GC_PINMUX_EXITEN0_DIOA6_SIZE             0x1
-#define GC_PINMUX_EXITEN0_DIOA6_DEFAULT          0x0
-#define GC_PINMUX_EXITEN0_DIOA6_OFFSET           0x284
-#define GC_PINMUX_EXITEN0_DIOA7_LSB              0xc
-#define GC_PINMUX_EXITEN0_DIOA7_MASK             0x1000
-#define GC_PINMUX_EXITEN0_DIOA7_SIZE             0x1
-#define GC_PINMUX_EXITEN0_DIOA7_DEFAULT          0x0
-#define GC_PINMUX_EXITEN0_DIOA7_OFFSET           0x284
-#define GC_PINMUX_EXITEN0_DIOA8_LSB              0xd
-#define GC_PINMUX_EXITEN0_DIOA8_MASK             0x2000
-#define GC_PINMUX_EXITEN0_DIOA8_SIZE             0x1
-#define GC_PINMUX_EXITEN0_DIOA8_DEFAULT          0x0
-#define GC_PINMUX_EXITEN0_DIOA8_OFFSET           0x284
-#define GC_PINMUX_EXITEN0_DIOA9_LSB              0xe
-#define GC_PINMUX_EXITEN0_DIOA9_MASK             0x4000
-#define GC_PINMUX_EXITEN0_DIOA9_SIZE             0x1
-#define GC_PINMUX_EXITEN0_DIOA9_DEFAULT          0x0
-#define GC_PINMUX_EXITEN0_DIOA9_OFFSET           0x284
-#define GC_PINMUX_EXITEN0_DIOA10_LSB             0xf
-#define GC_PINMUX_EXITEN0_DIOA10_MASK            0x8000
-#define GC_PINMUX_EXITEN0_DIOA10_SIZE            0x1
-#define GC_PINMUX_EXITEN0_DIOA10_DEFAULT         0x0
-#define GC_PINMUX_EXITEN0_DIOA10_OFFSET          0x284
-#define GC_PINMUX_EXITEN0_DIOA11_LSB             0x10
-#define GC_PINMUX_EXITEN0_DIOA11_MASK            0x10000
-#define GC_PINMUX_EXITEN0_DIOA11_SIZE            0x1
-#define GC_PINMUX_EXITEN0_DIOA11_DEFAULT         0x0
-#define GC_PINMUX_EXITEN0_DIOA11_OFFSET          0x284
-#define GC_PINMUX_EXITEN0_DIOA12_LSB             0x11
-#define GC_PINMUX_EXITEN0_DIOA12_MASK            0x20000
-#define GC_PINMUX_EXITEN0_DIOA12_SIZE            0x1
-#define GC_PINMUX_EXITEN0_DIOA12_DEFAULT         0x0
-#define GC_PINMUX_EXITEN0_DIOA12_OFFSET          0x284
-#define GC_PINMUX_EXITEN0_DIOA13_LSB             0x12
-#define GC_PINMUX_EXITEN0_DIOA13_MASK            0x40000
-#define GC_PINMUX_EXITEN0_DIOA13_SIZE            0x1
-#define GC_PINMUX_EXITEN0_DIOA13_DEFAULT         0x0
-#define GC_PINMUX_EXITEN0_DIOA13_OFFSET          0x284
-#define GC_PINMUX_EXITEN0_DIOA14_LSB             0x13
-#define GC_PINMUX_EXITEN0_DIOA14_MASK            0x80000
-#define GC_PINMUX_EXITEN0_DIOA14_SIZE            0x1
-#define GC_PINMUX_EXITEN0_DIOA14_DEFAULT         0x0
-#define GC_PINMUX_EXITEN0_DIOA14_OFFSET          0x284
-#define GC_PINMUX_EXITEN0_DIOB0_LSB              0x14
-#define GC_PINMUX_EXITEN0_DIOB0_MASK             0x100000
-#define GC_PINMUX_EXITEN0_DIOB0_SIZE             0x1
-#define GC_PINMUX_EXITEN0_DIOB0_DEFAULT          0x0
-#define GC_PINMUX_EXITEN0_DIOB0_OFFSET           0x284
-#define GC_PINMUX_EXITEN0_DIOB1_LSB              0x15
-#define GC_PINMUX_EXITEN0_DIOB1_MASK             0x200000
-#define GC_PINMUX_EXITEN0_DIOB1_SIZE             0x1
-#define GC_PINMUX_EXITEN0_DIOB1_DEFAULT          0x0
-#define GC_PINMUX_EXITEN0_DIOB1_OFFSET           0x284
-#define GC_PINMUX_EXITEN0_DIOB2_LSB              0x16
-#define GC_PINMUX_EXITEN0_DIOB2_MASK             0x400000
-#define GC_PINMUX_EXITEN0_DIOB2_SIZE             0x1
-#define GC_PINMUX_EXITEN0_DIOB2_DEFAULT          0x0
-#define GC_PINMUX_EXITEN0_DIOB2_OFFSET           0x284
-#define GC_PINMUX_EXITEN0_DIOB3_LSB              0x17
-#define GC_PINMUX_EXITEN0_DIOB3_MASK             0x800000
-#define GC_PINMUX_EXITEN0_DIOB3_SIZE             0x1
-#define GC_PINMUX_EXITEN0_DIOB3_DEFAULT          0x0
-#define GC_PINMUX_EXITEN0_DIOB3_OFFSET           0x284
-#define GC_PINMUX_EXITEN0_DIOB4_LSB              0x18
-#define GC_PINMUX_EXITEN0_DIOB4_MASK             0x1000000
-#define GC_PINMUX_EXITEN0_DIOB4_SIZE             0x1
-#define GC_PINMUX_EXITEN0_DIOB4_DEFAULT          0x0
-#define GC_PINMUX_EXITEN0_DIOB4_OFFSET           0x284
-#define GC_PINMUX_EXITEN0_DIOB5_LSB              0x19
-#define GC_PINMUX_EXITEN0_DIOB5_MASK             0x2000000
-#define GC_PINMUX_EXITEN0_DIOB5_SIZE             0x1
-#define GC_PINMUX_EXITEN0_DIOB5_DEFAULT          0x0
-#define GC_PINMUX_EXITEN0_DIOB5_OFFSET           0x284
-#define GC_PINMUX_EXITEN0_DIOB6_LSB              0x1a
-#define GC_PINMUX_EXITEN0_DIOB6_MASK             0x4000000
-#define GC_PINMUX_EXITEN0_DIOB6_SIZE             0x1
-#define GC_PINMUX_EXITEN0_DIOB6_DEFAULT          0x0
-#define GC_PINMUX_EXITEN0_DIOB6_OFFSET           0x284
-#define GC_PINMUX_EXITEN0_DIOB7_LSB              0x1b
-#define GC_PINMUX_EXITEN0_DIOB7_MASK             0x8000000
-#define GC_PINMUX_EXITEN0_DIOB7_SIZE             0x1
-#define GC_PINMUX_EXITEN0_DIOB7_DEFAULT          0x0
-#define GC_PINMUX_EXITEN0_DIOB7_OFFSET           0x284
-#define GC_PINMUX_EXITEN0_VIO0_LSB               0x1c
-#define GC_PINMUX_EXITEN0_VIO0_MASK              0x10000000
-#define GC_PINMUX_EXITEN0_VIO0_SIZE              0x1
-#define GC_PINMUX_EXITEN0_VIO0_DEFAULT           0x0
-#define GC_PINMUX_EXITEN0_VIO0_OFFSET            0x284
-#define GC_PINMUX_EXITEN0_VIO1_LSB               0x1d
-#define GC_PINMUX_EXITEN0_VIO1_MASK              0x20000000
-#define GC_PINMUX_EXITEN0_VIO1_SIZE              0x1
-#define GC_PINMUX_EXITEN0_VIO1_DEFAULT           0x0
-#define GC_PINMUX_EXITEN0_VIO1_OFFSET            0x284
-#define GC_PINMUX_EXITEDGE0_DIOM0_LSB            0x0
-#define GC_PINMUX_EXITEDGE0_DIOM0_MASK           0x1
-#define GC_PINMUX_EXITEDGE0_DIOM0_SIZE           0x1
-#define GC_PINMUX_EXITEDGE0_DIOM0_DEFAULT        0x0
-#define GC_PINMUX_EXITEDGE0_DIOM0_OFFSET         0x288
-#define GC_PINMUX_EXITEDGE0_DIOM1_LSB            0x1
-#define GC_PINMUX_EXITEDGE0_DIOM1_MASK           0x2
-#define GC_PINMUX_EXITEDGE0_DIOM1_SIZE           0x1
-#define GC_PINMUX_EXITEDGE0_DIOM1_DEFAULT        0x0
-#define GC_PINMUX_EXITEDGE0_DIOM1_OFFSET         0x288
-#define GC_PINMUX_EXITEDGE0_DIOM2_LSB            0x2
-#define GC_PINMUX_EXITEDGE0_DIOM2_MASK           0x4
-#define GC_PINMUX_EXITEDGE0_DIOM2_SIZE           0x1
-#define GC_PINMUX_EXITEDGE0_DIOM2_DEFAULT        0x0
-#define GC_PINMUX_EXITEDGE0_DIOM2_OFFSET         0x288
-#define GC_PINMUX_EXITEDGE0_DIOM3_LSB            0x3
-#define GC_PINMUX_EXITEDGE0_DIOM3_MASK           0x8
-#define GC_PINMUX_EXITEDGE0_DIOM3_SIZE           0x1
-#define GC_PINMUX_EXITEDGE0_DIOM3_DEFAULT        0x0
-#define GC_PINMUX_EXITEDGE0_DIOM3_OFFSET         0x288
-#define GC_PINMUX_EXITEDGE0_DIOM4_LSB            0x4
-#define GC_PINMUX_EXITEDGE0_DIOM4_MASK           0x10
-#define GC_PINMUX_EXITEDGE0_DIOM4_SIZE           0x1
-#define GC_PINMUX_EXITEDGE0_DIOM4_DEFAULT        0x0
-#define GC_PINMUX_EXITEDGE0_DIOM4_OFFSET         0x288
-#define GC_PINMUX_EXITEDGE0_DIOA0_LSB            0x5
-#define GC_PINMUX_EXITEDGE0_DIOA0_MASK           0x20
-#define GC_PINMUX_EXITEDGE0_DIOA0_SIZE           0x1
-#define GC_PINMUX_EXITEDGE0_DIOA0_DEFAULT        0x0
-#define GC_PINMUX_EXITEDGE0_DIOA0_OFFSET         0x288
-#define GC_PINMUX_EXITEDGE0_DIOA1_LSB            0x6
-#define GC_PINMUX_EXITEDGE0_DIOA1_MASK           0x40
-#define GC_PINMUX_EXITEDGE0_DIOA1_SIZE           0x1
-#define GC_PINMUX_EXITEDGE0_DIOA1_DEFAULT        0x0
-#define GC_PINMUX_EXITEDGE0_DIOA1_OFFSET         0x288
-#define GC_PINMUX_EXITEDGE0_DIOA2_LSB            0x7
-#define GC_PINMUX_EXITEDGE0_DIOA2_MASK           0x80
-#define GC_PINMUX_EXITEDGE0_DIOA2_SIZE           0x1
-#define GC_PINMUX_EXITEDGE0_DIOA2_DEFAULT        0x0
-#define GC_PINMUX_EXITEDGE0_DIOA2_OFFSET         0x288
-#define GC_PINMUX_EXITEDGE0_DIOA3_LSB            0x8
-#define GC_PINMUX_EXITEDGE0_DIOA3_MASK           0x100
-#define GC_PINMUX_EXITEDGE0_DIOA3_SIZE           0x1
-#define GC_PINMUX_EXITEDGE0_DIOA3_DEFAULT        0x0
-#define GC_PINMUX_EXITEDGE0_DIOA3_OFFSET         0x288
-#define GC_PINMUX_EXITEDGE0_DIOA4_LSB            0x9
-#define GC_PINMUX_EXITEDGE0_DIOA4_MASK           0x200
-#define GC_PINMUX_EXITEDGE0_DIOA4_SIZE           0x1
-#define GC_PINMUX_EXITEDGE0_DIOA4_DEFAULT        0x0
-#define GC_PINMUX_EXITEDGE0_DIOA4_OFFSET         0x288
-#define GC_PINMUX_EXITEDGE0_DIOA5_LSB            0xa
-#define GC_PINMUX_EXITEDGE0_DIOA5_MASK           0x400
-#define GC_PINMUX_EXITEDGE0_DIOA5_SIZE           0x1
-#define GC_PINMUX_EXITEDGE0_DIOA5_DEFAULT        0x0
-#define GC_PINMUX_EXITEDGE0_DIOA5_OFFSET         0x288
-#define GC_PINMUX_EXITEDGE0_DIOA6_LSB            0xb
-#define GC_PINMUX_EXITEDGE0_DIOA6_MASK           0x800
-#define GC_PINMUX_EXITEDGE0_DIOA6_SIZE           0x1
-#define GC_PINMUX_EXITEDGE0_DIOA6_DEFAULT        0x0
-#define GC_PINMUX_EXITEDGE0_DIOA6_OFFSET         0x288
-#define GC_PINMUX_EXITEDGE0_DIOA7_LSB            0xc
-#define GC_PINMUX_EXITEDGE0_DIOA7_MASK           0x1000
-#define GC_PINMUX_EXITEDGE0_DIOA7_SIZE           0x1
-#define GC_PINMUX_EXITEDGE0_DIOA7_DEFAULT        0x0
-#define GC_PINMUX_EXITEDGE0_DIOA7_OFFSET         0x288
-#define GC_PINMUX_EXITEDGE0_DIOA8_LSB            0xd
-#define GC_PINMUX_EXITEDGE0_DIOA8_MASK           0x2000
-#define GC_PINMUX_EXITEDGE0_DIOA8_SIZE           0x1
-#define GC_PINMUX_EXITEDGE0_DIOA8_DEFAULT        0x0
-#define GC_PINMUX_EXITEDGE0_DIOA8_OFFSET         0x288
-#define GC_PINMUX_EXITEDGE0_DIOA9_LSB            0xe
-#define GC_PINMUX_EXITEDGE0_DIOA9_MASK           0x4000
-#define GC_PINMUX_EXITEDGE0_DIOA9_SIZE           0x1
-#define GC_PINMUX_EXITEDGE0_DIOA9_DEFAULT        0x0
-#define GC_PINMUX_EXITEDGE0_DIOA9_OFFSET         0x288
-#define GC_PINMUX_EXITEDGE0_DIOA10_LSB           0xf
-#define GC_PINMUX_EXITEDGE0_DIOA10_MASK          0x8000
-#define GC_PINMUX_EXITEDGE0_DIOA10_SIZE          0x1
-#define GC_PINMUX_EXITEDGE0_DIOA10_DEFAULT       0x0
-#define GC_PINMUX_EXITEDGE0_DIOA10_OFFSET        0x288
-#define GC_PINMUX_EXITEDGE0_DIOA11_LSB           0x10
-#define GC_PINMUX_EXITEDGE0_DIOA11_MASK          0x10000
-#define GC_PINMUX_EXITEDGE0_DIOA11_SIZE          0x1
-#define GC_PINMUX_EXITEDGE0_DIOA11_DEFAULT       0x0
-#define GC_PINMUX_EXITEDGE0_DIOA11_OFFSET        0x288
-#define GC_PINMUX_EXITEDGE0_DIOA12_LSB           0x11
-#define GC_PINMUX_EXITEDGE0_DIOA12_MASK          0x20000
-#define GC_PINMUX_EXITEDGE0_DIOA12_SIZE          0x1
-#define GC_PINMUX_EXITEDGE0_DIOA12_DEFAULT       0x0
-#define GC_PINMUX_EXITEDGE0_DIOA12_OFFSET        0x288
-#define GC_PINMUX_EXITEDGE0_DIOA13_LSB           0x12
-#define GC_PINMUX_EXITEDGE0_DIOA13_MASK          0x40000
-#define GC_PINMUX_EXITEDGE0_DIOA13_SIZE          0x1
-#define GC_PINMUX_EXITEDGE0_DIOA13_DEFAULT       0x0
-#define GC_PINMUX_EXITEDGE0_DIOA13_OFFSET        0x288
-#define GC_PINMUX_EXITEDGE0_DIOA14_LSB           0x13
-#define GC_PINMUX_EXITEDGE0_DIOA14_MASK          0x80000
-#define GC_PINMUX_EXITEDGE0_DIOA14_SIZE          0x1
-#define GC_PINMUX_EXITEDGE0_DIOA14_DEFAULT       0x0
-#define GC_PINMUX_EXITEDGE0_DIOA14_OFFSET        0x288
-#define GC_PINMUX_EXITEDGE0_DIOB0_LSB            0x14
-#define GC_PINMUX_EXITEDGE0_DIOB0_MASK           0x100000
-#define GC_PINMUX_EXITEDGE0_DIOB0_SIZE           0x1
-#define GC_PINMUX_EXITEDGE0_DIOB0_DEFAULT        0x0
-#define GC_PINMUX_EXITEDGE0_DIOB0_OFFSET         0x288
-#define GC_PINMUX_EXITEDGE0_DIOB1_LSB            0x15
-#define GC_PINMUX_EXITEDGE0_DIOB1_MASK           0x200000
-#define GC_PINMUX_EXITEDGE0_DIOB1_SIZE           0x1
-#define GC_PINMUX_EXITEDGE0_DIOB1_DEFAULT        0x0
-#define GC_PINMUX_EXITEDGE0_DIOB1_OFFSET         0x288
-#define GC_PINMUX_EXITEDGE0_DIOB2_LSB            0x16
-#define GC_PINMUX_EXITEDGE0_DIOB2_MASK           0x400000
-#define GC_PINMUX_EXITEDGE0_DIOB2_SIZE           0x1
-#define GC_PINMUX_EXITEDGE0_DIOB2_DEFAULT        0x0
-#define GC_PINMUX_EXITEDGE0_DIOB2_OFFSET         0x288
-#define GC_PINMUX_EXITEDGE0_DIOB3_LSB            0x17
-#define GC_PINMUX_EXITEDGE0_DIOB3_MASK           0x800000
-#define GC_PINMUX_EXITEDGE0_DIOB3_SIZE           0x1
-#define GC_PINMUX_EXITEDGE0_DIOB3_DEFAULT        0x0
-#define GC_PINMUX_EXITEDGE0_DIOB3_OFFSET         0x288
-#define GC_PINMUX_EXITEDGE0_DIOB4_LSB            0x18
-#define GC_PINMUX_EXITEDGE0_DIOB4_MASK           0x1000000
-#define GC_PINMUX_EXITEDGE0_DIOB4_SIZE           0x1
-#define GC_PINMUX_EXITEDGE0_DIOB4_DEFAULT        0x0
-#define GC_PINMUX_EXITEDGE0_DIOB4_OFFSET         0x288
-#define GC_PINMUX_EXITEDGE0_DIOB5_LSB            0x19
-#define GC_PINMUX_EXITEDGE0_DIOB5_MASK           0x2000000
-#define GC_PINMUX_EXITEDGE0_DIOB5_SIZE           0x1
-#define GC_PINMUX_EXITEDGE0_DIOB5_DEFAULT        0x0
-#define GC_PINMUX_EXITEDGE0_DIOB5_OFFSET         0x288
-#define GC_PINMUX_EXITEDGE0_DIOB6_LSB            0x1a
-#define GC_PINMUX_EXITEDGE0_DIOB6_MASK           0x4000000
-#define GC_PINMUX_EXITEDGE0_DIOB6_SIZE           0x1
-#define GC_PINMUX_EXITEDGE0_DIOB6_DEFAULT        0x0
-#define GC_PINMUX_EXITEDGE0_DIOB6_OFFSET         0x288
-#define GC_PINMUX_EXITEDGE0_DIOB7_LSB            0x1b
-#define GC_PINMUX_EXITEDGE0_DIOB7_MASK           0x8000000
-#define GC_PINMUX_EXITEDGE0_DIOB7_SIZE           0x1
-#define GC_PINMUX_EXITEDGE0_DIOB7_DEFAULT        0x0
-#define GC_PINMUX_EXITEDGE0_DIOB7_OFFSET         0x288
-#define GC_PINMUX_EXITEDGE0_VIO0_LSB             0x1c
-#define GC_PINMUX_EXITEDGE0_VIO0_MASK            0x10000000
-#define GC_PINMUX_EXITEDGE0_VIO0_SIZE            0x1
-#define GC_PINMUX_EXITEDGE0_VIO0_DEFAULT         0x0
-#define GC_PINMUX_EXITEDGE0_VIO0_OFFSET          0x288
-#define GC_PINMUX_EXITEDGE0_VIO1_LSB             0x1d
-#define GC_PINMUX_EXITEDGE0_VIO1_MASK            0x20000000
-#define GC_PINMUX_EXITEDGE0_VIO1_SIZE            0x1
-#define GC_PINMUX_EXITEDGE0_VIO1_DEFAULT         0x0
-#define GC_PINMUX_EXITEDGE0_VIO1_OFFSET          0x288
-#define GC_PINMUX_EXITINV0_DIOM0_LSB             0x0
-#define GC_PINMUX_EXITINV0_DIOM0_MASK            0x1
-#define GC_PINMUX_EXITINV0_DIOM0_SIZE            0x1
-#define GC_PINMUX_EXITINV0_DIOM0_DEFAULT         0x0
-#define GC_PINMUX_EXITINV0_DIOM0_OFFSET          0x28c
-#define GC_PINMUX_EXITINV0_DIOM1_LSB             0x1
-#define GC_PINMUX_EXITINV0_DIOM1_MASK            0x2
-#define GC_PINMUX_EXITINV0_DIOM1_SIZE            0x1
-#define GC_PINMUX_EXITINV0_DIOM1_DEFAULT         0x0
-#define GC_PINMUX_EXITINV0_DIOM1_OFFSET          0x28c
-#define GC_PINMUX_EXITINV0_DIOM2_LSB             0x2
-#define GC_PINMUX_EXITINV0_DIOM2_MASK            0x4
-#define GC_PINMUX_EXITINV0_DIOM2_SIZE            0x1
-#define GC_PINMUX_EXITINV0_DIOM2_DEFAULT         0x0
-#define GC_PINMUX_EXITINV0_DIOM2_OFFSET          0x28c
-#define GC_PINMUX_EXITINV0_DIOM3_LSB             0x3
-#define GC_PINMUX_EXITINV0_DIOM3_MASK            0x8
-#define GC_PINMUX_EXITINV0_DIOM3_SIZE            0x1
-#define GC_PINMUX_EXITINV0_DIOM3_DEFAULT         0x0
-#define GC_PINMUX_EXITINV0_DIOM3_OFFSET          0x28c
-#define GC_PINMUX_EXITINV0_DIOM4_LSB             0x4
-#define GC_PINMUX_EXITINV0_DIOM4_MASK            0x10
-#define GC_PINMUX_EXITINV0_DIOM4_SIZE            0x1
-#define GC_PINMUX_EXITINV0_DIOM4_DEFAULT         0x0
-#define GC_PINMUX_EXITINV0_DIOM4_OFFSET          0x28c
-#define GC_PINMUX_EXITINV0_DIOA0_LSB             0x5
-#define GC_PINMUX_EXITINV0_DIOA0_MASK            0x20
-#define GC_PINMUX_EXITINV0_DIOA0_SIZE            0x1
-#define GC_PINMUX_EXITINV0_DIOA0_DEFAULT         0x0
-#define GC_PINMUX_EXITINV0_DIOA0_OFFSET          0x28c
-#define GC_PINMUX_EXITINV0_DIOA1_LSB             0x6
-#define GC_PINMUX_EXITINV0_DIOA1_MASK            0x40
-#define GC_PINMUX_EXITINV0_DIOA1_SIZE            0x1
-#define GC_PINMUX_EXITINV0_DIOA1_DEFAULT         0x0
-#define GC_PINMUX_EXITINV0_DIOA1_OFFSET          0x28c
-#define GC_PINMUX_EXITINV0_DIOA2_LSB             0x7
-#define GC_PINMUX_EXITINV0_DIOA2_MASK            0x80
-#define GC_PINMUX_EXITINV0_DIOA2_SIZE            0x1
-#define GC_PINMUX_EXITINV0_DIOA2_DEFAULT         0x0
-#define GC_PINMUX_EXITINV0_DIOA2_OFFSET          0x28c
-#define GC_PINMUX_EXITINV0_DIOA3_LSB             0x8
-#define GC_PINMUX_EXITINV0_DIOA3_MASK            0x100
-#define GC_PINMUX_EXITINV0_DIOA3_SIZE            0x1
-#define GC_PINMUX_EXITINV0_DIOA3_DEFAULT         0x0
-#define GC_PINMUX_EXITINV0_DIOA3_OFFSET          0x28c
-#define GC_PINMUX_EXITINV0_DIOA4_LSB             0x9
-#define GC_PINMUX_EXITINV0_DIOA4_MASK            0x200
-#define GC_PINMUX_EXITINV0_DIOA4_SIZE            0x1
-#define GC_PINMUX_EXITINV0_DIOA4_DEFAULT         0x0
-#define GC_PINMUX_EXITINV0_DIOA4_OFFSET          0x28c
-#define GC_PINMUX_EXITINV0_DIOA5_LSB             0xa
-#define GC_PINMUX_EXITINV0_DIOA5_MASK            0x400
-#define GC_PINMUX_EXITINV0_DIOA5_SIZE            0x1
-#define GC_PINMUX_EXITINV0_DIOA5_DEFAULT         0x0
-#define GC_PINMUX_EXITINV0_DIOA5_OFFSET          0x28c
-#define GC_PINMUX_EXITINV0_DIOA6_LSB             0xb
-#define GC_PINMUX_EXITINV0_DIOA6_MASK            0x800
-#define GC_PINMUX_EXITINV0_DIOA6_SIZE            0x1
-#define GC_PINMUX_EXITINV0_DIOA6_DEFAULT         0x0
-#define GC_PINMUX_EXITINV0_DIOA6_OFFSET          0x28c
-#define GC_PINMUX_EXITINV0_DIOA7_LSB             0xc
-#define GC_PINMUX_EXITINV0_DIOA7_MASK            0x1000
-#define GC_PINMUX_EXITINV0_DIOA7_SIZE            0x1
-#define GC_PINMUX_EXITINV0_DIOA7_DEFAULT         0x0
-#define GC_PINMUX_EXITINV0_DIOA7_OFFSET          0x28c
-#define GC_PINMUX_EXITINV0_DIOA8_LSB             0xd
-#define GC_PINMUX_EXITINV0_DIOA8_MASK            0x2000
-#define GC_PINMUX_EXITINV0_DIOA8_SIZE            0x1
-#define GC_PINMUX_EXITINV0_DIOA8_DEFAULT         0x0
-#define GC_PINMUX_EXITINV0_DIOA8_OFFSET          0x28c
-#define GC_PINMUX_EXITINV0_DIOA9_LSB             0xe
-#define GC_PINMUX_EXITINV0_DIOA9_MASK            0x4000
-#define GC_PINMUX_EXITINV0_DIOA9_SIZE            0x1
-#define GC_PINMUX_EXITINV0_DIOA9_DEFAULT         0x0
-#define GC_PINMUX_EXITINV0_DIOA9_OFFSET          0x28c
-#define GC_PINMUX_EXITINV0_DIOA10_LSB            0xf
-#define GC_PINMUX_EXITINV0_DIOA10_MASK           0x8000
-#define GC_PINMUX_EXITINV0_DIOA10_SIZE           0x1
-#define GC_PINMUX_EXITINV0_DIOA10_DEFAULT        0x0
-#define GC_PINMUX_EXITINV0_DIOA10_OFFSET         0x28c
-#define GC_PINMUX_EXITINV0_DIOA11_LSB            0x10
-#define GC_PINMUX_EXITINV0_DIOA11_MASK           0x10000
-#define GC_PINMUX_EXITINV0_DIOA11_SIZE           0x1
-#define GC_PINMUX_EXITINV0_DIOA11_DEFAULT        0x0
-#define GC_PINMUX_EXITINV0_DIOA11_OFFSET         0x28c
-#define GC_PINMUX_EXITINV0_DIOA12_LSB            0x11
-#define GC_PINMUX_EXITINV0_DIOA12_MASK           0x20000
-#define GC_PINMUX_EXITINV0_DIOA12_SIZE           0x1
-#define GC_PINMUX_EXITINV0_DIOA12_DEFAULT        0x0
-#define GC_PINMUX_EXITINV0_DIOA12_OFFSET         0x28c
-#define GC_PINMUX_EXITINV0_DIOA13_LSB            0x12
-#define GC_PINMUX_EXITINV0_DIOA13_MASK           0x40000
-#define GC_PINMUX_EXITINV0_DIOA13_SIZE           0x1
-#define GC_PINMUX_EXITINV0_DIOA13_DEFAULT        0x0
-#define GC_PINMUX_EXITINV0_DIOA13_OFFSET         0x28c
-#define GC_PINMUX_EXITINV0_DIOA14_LSB            0x13
-#define GC_PINMUX_EXITINV0_DIOA14_MASK           0x80000
-#define GC_PINMUX_EXITINV0_DIOA14_SIZE           0x1
-#define GC_PINMUX_EXITINV0_DIOA14_DEFAULT        0x0
-#define GC_PINMUX_EXITINV0_DIOA14_OFFSET         0x28c
-#define GC_PINMUX_EXITINV0_DIOB0_LSB             0x14
-#define GC_PINMUX_EXITINV0_DIOB0_MASK            0x100000
-#define GC_PINMUX_EXITINV0_DIOB0_SIZE            0x1
-#define GC_PINMUX_EXITINV0_DIOB0_DEFAULT         0x0
-#define GC_PINMUX_EXITINV0_DIOB0_OFFSET          0x28c
-#define GC_PINMUX_EXITINV0_DIOB1_LSB             0x15
-#define GC_PINMUX_EXITINV0_DIOB1_MASK            0x200000
-#define GC_PINMUX_EXITINV0_DIOB1_SIZE            0x1
-#define GC_PINMUX_EXITINV0_DIOB1_DEFAULT         0x0
-#define GC_PINMUX_EXITINV0_DIOB1_OFFSET          0x28c
-#define GC_PINMUX_EXITINV0_DIOB2_LSB             0x16
-#define GC_PINMUX_EXITINV0_DIOB2_MASK            0x400000
-#define GC_PINMUX_EXITINV0_DIOB2_SIZE            0x1
-#define GC_PINMUX_EXITINV0_DIOB2_DEFAULT         0x0
-#define GC_PINMUX_EXITINV0_DIOB2_OFFSET          0x28c
-#define GC_PINMUX_EXITINV0_DIOB3_LSB             0x17
-#define GC_PINMUX_EXITINV0_DIOB3_MASK            0x800000
-#define GC_PINMUX_EXITINV0_DIOB3_SIZE            0x1
-#define GC_PINMUX_EXITINV0_DIOB3_DEFAULT         0x0
-#define GC_PINMUX_EXITINV0_DIOB3_OFFSET          0x28c
-#define GC_PINMUX_EXITINV0_DIOB4_LSB             0x18
-#define GC_PINMUX_EXITINV0_DIOB4_MASK            0x1000000
-#define GC_PINMUX_EXITINV0_DIOB4_SIZE            0x1
-#define GC_PINMUX_EXITINV0_DIOB4_DEFAULT         0x0
-#define GC_PINMUX_EXITINV0_DIOB4_OFFSET          0x28c
-#define GC_PINMUX_EXITINV0_DIOB5_LSB             0x19
-#define GC_PINMUX_EXITINV0_DIOB5_MASK            0x2000000
-#define GC_PINMUX_EXITINV0_DIOB5_SIZE            0x1
-#define GC_PINMUX_EXITINV0_DIOB5_DEFAULT         0x0
-#define GC_PINMUX_EXITINV0_DIOB5_OFFSET          0x28c
-#define GC_PINMUX_EXITINV0_DIOB6_LSB             0x1a
-#define GC_PINMUX_EXITINV0_DIOB6_MASK            0x4000000
-#define GC_PINMUX_EXITINV0_DIOB6_SIZE            0x1
-#define GC_PINMUX_EXITINV0_DIOB6_DEFAULT         0x0
-#define GC_PINMUX_EXITINV0_DIOB6_OFFSET          0x28c
-#define GC_PINMUX_EXITINV0_DIOB7_LSB             0x1b
-#define GC_PINMUX_EXITINV0_DIOB7_MASK            0x8000000
-#define GC_PINMUX_EXITINV0_DIOB7_SIZE            0x1
-#define GC_PINMUX_EXITINV0_DIOB7_DEFAULT         0x0
-#define GC_PINMUX_EXITINV0_DIOB7_OFFSET          0x28c
-#define GC_PINMUX_EXITINV0_VIO0_LSB              0x1c
-#define GC_PINMUX_EXITINV0_VIO0_MASK             0x10000000
-#define GC_PINMUX_EXITINV0_VIO0_SIZE             0x1
-#define GC_PINMUX_EXITINV0_VIO0_DEFAULT          0x0
-#define GC_PINMUX_EXITINV0_VIO0_OFFSET           0x28c
-#define GC_PINMUX_EXITINV0_VIO1_LSB              0x1d
-#define GC_PINMUX_EXITINV0_VIO1_MASK             0x20000000
-#define GC_PINMUX_EXITINV0_VIO1_SIZE             0x1
-#define GC_PINMUX_EXITINV0_VIO1_DEFAULT          0x0
-#define GC_PINMUX_EXITINV0_VIO1_OFFSET           0x28c
-#define GC_PMU_RESET_PORESETB1_LSB               0x0
-#define GC_PMU_RESET_PORESETB1_MASK              0x1
-#define GC_PMU_RESET_PORESETB1_SIZE              0x1
-#define GC_PMU_RESET_PORESETB1_DEFAULT           0x1
-#define GC_PMU_RESET_PORESETB1_OFFSET            0x0
-#define GC_PMU_RESET_DAPRESETB1_LSB              0x1
-#define GC_PMU_RESET_DAPRESETB1_MASK             0x2
-#define GC_PMU_RESET_DAPRESETB1_SIZE             0x1
-#define GC_PMU_RESET_DAPRESETB1_DEFAULT          0x1
-#define GC_PMU_RESET_DAPRESETB1_OFFSET           0x0
-#define GC_PMU_SETRST_SRC_LSB                    0x0
-#define GC_PMU_SETRST_SRC_MASK                   0x1
-#define GC_PMU_SETRST_SRC_SIZE                   0x1
-#define GC_PMU_SETRST_SRC_DEFAULT                0x0
-#define GC_PMU_SETRST_SRC_OFFSET                 0x4
-#define GC_PMU_CLRRST_SRC_LSB                    0x0
-#define GC_PMU_CLRRST_SRC_MASK                   0x1
-#define GC_PMU_CLRRST_SRC_SIZE                   0x1
-#define GC_PMU_CLRRST_SRC_DEFAULT                0x0
-#define GC_PMU_CLRRST_SRC_OFFSET                 0x8
-#define GC_PMU_RSTSRC_POR_LSB                    0x0
-#define GC_PMU_RSTSRC_POR_MASK                   0x1
-#define GC_PMU_RSTSRC_POR_SIZE                   0x1
-#define GC_PMU_RSTSRC_POR_DEFAULT                0x0
-#define GC_PMU_RSTSRC_POR_OFFSET                 0xc
-#define GC_PMU_RSTSRC_EXIT_LSB                   0x1
-#define GC_PMU_RSTSRC_EXIT_MASK                  0x2
-#define GC_PMU_RSTSRC_EXIT_SIZE                  0x1
-#define GC_PMU_RSTSRC_EXIT_DEFAULT               0x0
-#define GC_PMU_RSTSRC_EXIT_OFFSET                0xc
-#define GC_PMU_RSTSRC_WDOG_LSB                   0x2
-#define GC_PMU_RSTSRC_WDOG_MASK                  0x4
-#define GC_PMU_RSTSRC_WDOG_SIZE                  0x1
-#define GC_PMU_RSTSRC_WDOG_DEFAULT               0x0
-#define GC_PMU_RSTSRC_WDOG_OFFSET                0xc
-#define GC_PMU_RSTSRC_LOCKUP_LSB                 0x3
-#define GC_PMU_RSTSRC_LOCKUP_MASK                0x8
-#define GC_PMU_RSTSRC_LOCKUP_SIZE                0x1
-#define GC_PMU_RSTSRC_LOCKUP_DEFAULT             0x0
-#define GC_PMU_RSTSRC_LOCKUP_OFFSET              0xc
-#define GC_PMU_RSTSRC_SYSRESET_LSB               0x4
-#define GC_PMU_RSTSRC_SYSRESET_MASK              0x10
-#define GC_PMU_RSTSRC_SYSRESET_SIZE              0x1
-#define GC_PMU_RSTSRC_SYSRESET_DEFAULT           0x0
-#define GC_PMU_RSTSRC_SYSRESET_OFFSET            0xc
-#define GC_PMU_RSTSRC_SOFTWARE_LSB               0x5
-#define GC_PMU_RSTSRC_SOFTWARE_MASK              0x20
-#define GC_PMU_RSTSRC_SOFTWARE_SIZE              0x1
-#define GC_PMU_RSTSRC_SOFTWARE_DEFAULT           0x0
-#define GC_PMU_RSTSRC_SOFTWARE_OFFSET            0xc
-#define GC_PMU_RSTSRC_FST_BRNOUT_LSB             0x6
-#define GC_PMU_RSTSRC_FST_BRNOUT_MASK            0x40
-#define GC_PMU_RSTSRC_FST_BRNOUT_SIZE            0x1
-#define GC_PMU_RSTSRC_FST_BRNOUT_DEFAULT         0x0
-#define GC_PMU_RSTSRC_FST_BRNOUT_OFFSET          0xc
-#define GC_PMU_RSTSRC_SEC_THREAT_LSB             0x7
-#define GC_PMU_RSTSRC_SEC_THREAT_MASK            0x80
-#define GC_PMU_RSTSRC_SEC_THREAT_SIZE            0x1
-#define GC_PMU_RSTSRC_SEC_THREAT_DEFAULT         0x0
-#define GC_PMU_RSTSRC_SEC_THREAT_OFFSET          0xc
-#define GC_PMU_LOW_POWER_DIS_START_LSB           0x0
-#define GC_PMU_LOW_POWER_DIS_START_MASK          0x1
-#define GC_PMU_LOW_POWER_DIS_START_SIZE          0x1
-#define GC_PMU_LOW_POWER_DIS_START_DEFAULT       0x0
-#define GC_PMU_LOW_POWER_DIS_START_OFFSET        0x14
-#define GC_PMU_LOW_POWER_DIS_VDDL_LSB            0x1
-#define GC_PMU_LOW_POWER_DIS_VDDL_MASK           0x2
-#define GC_PMU_LOW_POWER_DIS_VDDL_SIZE           0x1
-#define GC_PMU_LOW_POWER_DIS_VDDL_DEFAULT        0x1
-#define GC_PMU_LOW_POWER_DIS_VDDL_OFFSET         0x14
-#define GC_PMU_LOW_POWER_DIS_VDDIOF_LSB          0x2
-#define GC_PMU_LOW_POWER_DIS_VDDIOF_MASK         0x4
-#define GC_PMU_LOW_POWER_DIS_VDDIOF_SIZE         0x1
-#define GC_PMU_LOW_POWER_DIS_VDDIOF_DEFAULT      0x1
-#define GC_PMU_LOW_POWER_DIS_VDDIOF_OFFSET       0x14
-#define GC_PMU_LOW_POWER_DIS_VDDXO_LSB           0x3
-#define GC_PMU_LOW_POWER_DIS_VDDXO_MASK          0x8
-#define GC_PMU_LOW_POWER_DIS_VDDXO_SIZE          0x1
-#define GC_PMU_LOW_POWER_DIS_VDDXO_DEFAULT       0x1
-#define GC_PMU_LOW_POWER_DIS_VDDXO_OFFSET        0x14
-#define GC_PMU_LOW_POWER_DIS_JTR_RC_LSB          0x4
-#define GC_PMU_LOW_POWER_DIS_JTR_RC_MASK         0x10
-#define GC_PMU_LOW_POWER_DIS_JTR_RC_SIZE         0x1
-#define GC_PMU_LOW_POWER_DIS_JTR_RC_DEFAULT      0x1
-#define GC_PMU_LOW_POWER_DIS_JTR_RC_OFFSET       0x14
-#define GC_PMU_LOW_POWER_BYPASS_VDDL_LSB         0x0
-#define GC_PMU_LOW_POWER_BYPASS_VDDL_MASK        0x1
-#define GC_PMU_LOW_POWER_BYPASS_VDDL_SIZE        0x1
-#define GC_PMU_LOW_POWER_BYPASS_VDDL_DEFAULT     0x0
-#define GC_PMU_LOW_POWER_BYPASS_VDDL_OFFSET      0x18
-#define GC_PMU_LOW_POWER_BYPASS_VDDIOF_LSB       0x1
-#define GC_PMU_LOW_POWER_BYPASS_VDDIOF_MASK      0x2
-#define GC_PMU_LOW_POWER_BYPASS_VDDIOF_SIZE      0x1
-#define GC_PMU_LOW_POWER_BYPASS_VDDIOF_DEFAULT   0x0
-#define GC_PMU_LOW_POWER_BYPASS_VDDIOF_OFFSET    0x18
-#define GC_PMU_LOW_POWER_BYPASS_VDDXO_LSB        0x2
-#define GC_PMU_LOW_POWER_BYPASS_VDDXO_MASK       0x4
-#define GC_PMU_LOW_POWER_BYPASS_VDDXO_SIZE       0x1
-#define GC_PMU_LOW_POWER_BYPASS_VDDXO_DEFAULT    0x0
-#define GC_PMU_LOW_POWER_BYPASS_VDDXO_OFFSET     0x18
-#define GC_PMU_LOW_POWER_BYPASS_VDDXO_COMP_LSB   0x3
-#define GC_PMU_LOW_POWER_BYPASS_VDDXO_COMP_MASK  0x8
-#define GC_PMU_LOW_POWER_BYPASS_VDDXO_COMP_SIZE  0x1
-#define GC_PMU_LOW_POWER_BYPASS_VDDXO_COMP_DEFAULT 0x0
-#define GC_PMU_LOW_POWER_BYPASS_VDDXO_COMP_OFFSET 0x18
-#define GC_PMU_LOW_POWER_BYPASS_JTR_RC_LSB       0x4
-#define GC_PMU_LOW_POWER_BYPASS_JTR_RC_MASK      0x10
-#define GC_PMU_LOW_POWER_BYPASS_JTR_RC_SIZE      0x1
-#define GC_PMU_LOW_POWER_BYPASS_JTR_RC_DEFAULT   0x0
-#define GC_PMU_LOW_POWER_BYPASS_JTR_RC_OFFSET    0x18
-#define GC_PMU_LOW_POWER_BYPASS_TIMER_RC_LSB     0x5
-#define GC_PMU_LOW_POWER_BYPASS_TIMER_RC_MASK    0x20
-#define GC_PMU_LOW_POWER_BYPASS_TIMER_RC_SIZE    0x1
-#define GC_PMU_LOW_POWER_BYPASS_TIMER_RC_DEFAULT 0x0
-#define GC_PMU_LOW_POWER_BYPASS_TIMER_RC_OFFSET  0x18
-#define GC_PMU_LOW_POWER_BYPASS_PDM25_LSB        0x6
-#define GC_PMU_LOW_POWER_BYPASS_PDM25_MASK       0x40
-#define GC_PMU_LOW_POWER_BYPASS_PDM25_SIZE       0x1
-#define GC_PMU_LOW_POWER_BYPASS_PDM25_DEFAULT    0x0
-#define GC_PMU_LOW_POWER_BYPASS_PDM25_OFFSET     0x18
-#define GC_PMU_LOW_POWER_BYPASS_VDDL_ISO_LSB     0x7
-#define GC_PMU_LOW_POWER_BYPASS_VDDL_ISO_MASK    0x80
-#define GC_PMU_LOW_POWER_BYPASS_VDDL_ISO_SIZE    0x1
-#define GC_PMU_LOW_POWER_BYPASS_VDDL_ISO_DEFAULT 0x0
-#define GC_PMU_LOW_POWER_BYPASS_VDDL_ISO_OFFSET  0x18
-#define GC_PMU_LOW_POWER_BYPASS_VDDXO_ISO_LSB    0x8
-#define GC_PMU_LOW_POWER_BYPASS_VDDXO_ISO_MASK   0x100
-#define GC_PMU_LOW_POWER_BYPASS_VDDXO_ISO_SIZE   0x1
-#define GC_PMU_LOW_POWER_BYPASS_VDDXO_ISO_DEFAULT 0x0
-#define GC_PMU_LOW_POWER_BYPASS_VDDXO_ISO_OFFSET 0x18
-#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDL_LSB   0x0
-#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDL_MASK  0x1
-#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDL_SIZE  0x1
-#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDL_DEFAULT 0x0
-#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDL_OFFSET 0x1c
-#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDIOF_LSB 0x1
-#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDIOF_MASK 0x2
-#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDIOF_SIZE 0x1
-#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDIOF_DEFAULT 0x0
-#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDIOF_OFFSET 0x1c
-#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDXO_LSB  0x2
-#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDXO_MASK 0x4
-#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDXO_SIZE 0x1
-#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDXO_DEFAULT 0x0
-#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDXO_OFFSET 0x1c
-#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDXO_COMP_LSB 0x3
-#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDXO_COMP_MASK 0x8
-#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDXO_COMP_SIZE 0x1
-#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDXO_COMP_DEFAULT 0x0
-#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDXO_COMP_OFFSET 0x1c
-#define GC_PMU_LOW_POWER_BYPASS_VALUE_JTR_RC_LSB 0x4
-#define GC_PMU_LOW_POWER_BYPASS_VALUE_JTR_RC_MASK 0x10
-#define GC_PMU_LOW_POWER_BYPASS_VALUE_JTR_RC_SIZE 0x1
-#define GC_PMU_LOW_POWER_BYPASS_VALUE_JTR_RC_DEFAULT 0x0
-#define GC_PMU_LOW_POWER_BYPASS_VALUE_JTR_RC_OFFSET 0x1c
-#define GC_PMU_LOW_POWER_BYPASS_VALUE_TIMER_RC_LSB 0x5
-#define GC_PMU_LOW_POWER_BYPASS_VALUE_TIMER_RC_MASK 0x20
-#define GC_PMU_LOW_POWER_BYPASS_VALUE_TIMER_RC_SIZE 0x1
-#define GC_PMU_LOW_POWER_BYPASS_VALUE_TIMER_RC_DEFAULT 0x0
-#define GC_PMU_LOW_POWER_BYPASS_VALUE_TIMER_RC_OFFSET 0x1c
-#define GC_PMU_LOW_POWER_BYPASS_VALUE_PDM25_LSB  0x6
-#define GC_PMU_LOW_POWER_BYPASS_VALUE_PDM25_MASK 0x40
-#define GC_PMU_LOW_POWER_BYPASS_VALUE_PDM25_SIZE 0x1
-#define GC_PMU_LOW_POWER_BYPASS_VALUE_PDM25_DEFAULT 0x0
-#define GC_PMU_LOW_POWER_BYPASS_VALUE_PDM25_OFFSET 0x1c
-#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDL_ISO_LSB 0x7
-#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDL_ISO_MASK 0x80
-#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDL_ISO_SIZE 0x1
-#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDL_ISO_DEFAULT 0x0
-#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDL_ISO_OFFSET 0x1c
-#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDXO_ISO_LSB 0x8
-#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDXO_ISO_MASK 0x100
-#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDXO_ISO_SIZE 0x1
-#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDXO_ISO_DEFAULT 0x0
-#define GC_PMU_LOW_POWER_BYPASS_VALUE_VDDXO_ISO_OFFSET 0x1c
-#define GC_PMU_SETWIC_PROC0_LSB                  0x0
-#define GC_PMU_SETWIC_PROC0_MASK                 0x1
-#define GC_PMU_SETWIC_PROC0_SIZE                 0x1
-#define GC_PMU_SETWIC_PROC0_DEFAULT              0x0
-#define GC_PMU_SETWIC_PROC0_OFFSET               0x20
-#define GC_PMU_CLRWIC_PROC0_LSB                  0x0
-#define GC_PMU_CLRWIC_PROC0_MASK                 0x1
-#define GC_PMU_CLRWIC_PROC0_SIZE                 0x1
-#define GC_PMU_CLRWIC_PROC0_DEFAULT              0x0
-#define GC_PMU_CLRWIC_PROC0_OFFSET               0x24
-#define GC_PMU_SW_PDB_TIMER_RC_LSB               0x0
-#define GC_PMU_SW_PDB_TIMER_RC_MASK              0x1
-#define GC_PMU_SW_PDB_TIMER_RC_SIZE              0x1
-#define GC_PMU_SW_PDB_TIMER_RC_DEFAULT           0x0
-#define GC_PMU_SW_PDB_TIMER_RC_OFFSET            0x30
-#define GC_PMU_SW_PDB_FST_BRNOUT_PWR_LSB         0x1
-#define GC_PMU_SW_PDB_FST_BRNOUT_PWR_MASK        0x2
-#define GC_PMU_SW_PDB_FST_BRNOUT_PWR_SIZE        0x1
-#define GC_PMU_SW_PDB_FST_BRNOUT_PWR_DEFAULT     0x0
-#define GC_PMU_SW_PDB_FST_BRNOUT_PWR_OFFSET      0x30
-#define GC_PMU_SW_PDB_FST_BRNOUT_LSB             0x2
-#define GC_PMU_SW_PDB_FST_BRNOUT_MASK            0x4
-#define GC_PMU_SW_PDB_FST_BRNOUT_SIZE            0x1
-#define GC_PMU_SW_PDB_FST_BRNOUT_DEFAULT         0x0
-#define GC_PMU_SW_PDB_FST_BRNOUT_OFFSET          0x30
-#define GC_PMU_SW_PDB_SECURE_BATMON_LSB          0x0
-#define GC_PMU_SW_PDB_SECURE_BATMON_MASK         0x1
-#define GC_PMU_SW_PDB_SECURE_BATMON_SIZE         0x1
-#define GC_PMU_SW_PDB_SECURE_BATMON_DEFAULT      0x0
-#define GC_PMU_SW_PDB_SECURE_BATMON_OFFSET       0x34
-#define GC_PMU_SW_PDB_SECURE_BATMON_EN_LSB       0x1
-#define GC_PMU_SW_PDB_SECURE_BATMON_EN_MASK      0x2
-#define GC_PMU_SW_PDB_SECURE_BATMON_EN_SIZE      0x1
-#define GC_PMU_SW_PDB_SECURE_BATMON_EN_DEFAULT   0x0
-#define GC_PMU_SW_PDB_SECURE_BATMON_EN_OFFSET    0x34
-#define GC_PMU_SW_PDB_SECURE_XTL_LSB             0x2
-#define GC_PMU_SW_PDB_SECURE_XTL_MASK            0x4
-#define GC_PMU_SW_PDB_SECURE_XTL_SIZE            0x1
-#define GC_PMU_SW_PDB_SECURE_XTL_DEFAULT         0x0
-#define GC_PMU_SW_PDB_SECURE_XTL_OFFSET          0x34
-#define GC_PMU_VREF_REG_LSB                      0x0
-#define GC_PMU_VREF_REG_MASK                     0xf
-#define GC_PMU_VREF_REG_SIZE                     0x4
-#define GC_PMU_VREF_REG_DEFAULT                  0xb
-#define GC_PMU_VREF_REG_OFFSET                   0x38
-#define GC_PMU_VREF_LDOXO_LSB                    0x4
-#define GC_PMU_VREF_LDOXO_MASK                   0xf0
-#define GC_PMU_VREF_LDOXO_SIZE                   0x4
-#define GC_PMU_VREF_LDOXO_DEFAULT                0xd
-#define GC_PMU_VREF_LDOXO_OFFSET                 0x38
-#define GC_PMU_VREF_BATMON_LSB                   0x8
-#define GC_PMU_VREF_BATMON_MASK                  0x700
-#define GC_PMU_VREF_BATMON_SIZE                  0x3
-#define GC_PMU_VREF_BATMON_DEFAULT               0x0
-#define GC_PMU_VREF_BATMON_OFFSET                0x38
-#define GC_PMU_VREF_BATMON_V1P9                  0x2
-#define GC_PMU_VREF_BATMON_V1P8                  0x1
-#define GC_PMU_VREF_BATMON_V1P7                  0x0
-#define GC_PMU_VREF_BATMON_V2P4                  0x7
-#define GC_PMU_VREF_BATMON_V2P0                  0x3
-#define GC_PMU_VREF_BATMON_V2P1                  0x4
-#define GC_PMU_VREF_BATMON_V2P2                  0x5
-#define GC_PMU_VREF_BATMON_V2P3                  0x6
-#define GC_PMU_B_REG_DIG_CTRL_RBANK_SEL_LSB      0x0
-#define GC_PMU_B_REG_DIG_CTRL_RBANK_SEL_MASK     0x3
-#define GC_PMU_B_REG_DIG_CTRL_RBANK_SEL_SIZE     0x2
-#define GC_PMU_B_REG_DIG_CTRL_RBANK_SEL_DEFAULT  0x2
-#define GC_PMU_B_REG_DIG_CTRL_RBANK_SEL_OFFSET   0x48
-#define GC_PMU_B_REG_DIG_CTRL_SPARE_LSB          0x2
-#define GC_PMU_B_REG_DIG_CTRL_SPARE_MASK         0x3c
-#define GC_PMU_B_REG_DIG_CTRL_SPARE_SIZE         0x4
-#define GC_PMU_B_REG_DIG_CTRL_SPARE_DEFAULT      0x0
-#define GC_PMU_B_REG_DIG_CTRL_SPARE_OFFSET       0x48
-#define GC_PMU_EXITPD_MASK_PIN_PD_EXIT_LSB       0x0
-#define GC_PMU_EXITPD_MASK_PIN_PD_EXIT_MASK      0x1
-#define GC_PMU_EXITPD_MASK_PIN_PD_EXIT_SIZE      0x1
-#define GC_PMU_EXITPD_MASK_PIN_PD_EXIT_DEFAULT   0x0
-#define GC_PMU_EXITPD_MASK_PIN_PD_EXIT_OFFSET    0x4c
-#define GC_PMU_EXITPD_MASK_UTMI_SUSPEND_N_LSB    0x1
-#define GC_PMU_EXITPD_MASK_UTMI_SUSPEND_N_MASK   0x2
-#define GC_PMU_EXITPD_MASK_UTMI_SUSPEND_N_SIZE   0x1
-#define GC_PMU_EXITPD_MASK_UTMI_SUSPEND_N_DEFAULT 0x0
-#define GC_PMU_EXITPD_MASK_UTMI_SUSPEND_N_OFFSET 0x4c
-#define GC_PMU_EXITPD_MASK_RDD0_PD_EXIT_TIMER_LSB 0x2
-#define GC_PMU_EXITPD_MASK_RDD0_PD_EXIT_TIMER_MASK 0x4
-#define GC_PMU_EXITPD_MASK_RDD0_PD_EXIT_TIMER_SIZE 0x1
-#define GC_PMU_EXITPD_MASK_RDD0_PD_EXIT_TIMER_DEFAULT 0x0
-#define GC_PMU_EXITPD_MASK_RDD0_PD_EXIT_TIMER_OFFSET 0x4c
-#define GC_PMU_EXITPD_MASK_TIMELS0_PD_EXIT_TIMER0_LSB 0x3
-#define GC_PMU_EXITPD_MASK_TIMELS0_PD_EXIT_TIMER0_MASK 0x8
-#define GC_PMU_EXITPD_MASK_TIMELS0_PD_EXIT_TIMER0_SIZE 0x1
-#define GC_PMU_EXITPD_MASK_TIMELS0_PD_EXIT_TIMER0_DEFAULT 0x0
-#define GC_PMU_EXITPD_MASK_TIMELS0_PD_EXIT_TIMER0_OFFSET 0x4c
-#define GC_PMU_EXITPD_MASK_TIMELS0_PD_EXIT_TIMER1_LSB 0x4
-#define GC_PMU_EXITPD_MASK_TIMELS0_PD_EXIT_TIMER1_MASK 0x10
-#define GC_PMU_EXITPD_MASK_TIMELS0_PD_EXIT_TIMER1_SIZE 0x1
-#define GC_PMU_EXITPD_MASK_TIMELS0_PD_EXIT_TIMER1_DEFAULT 0x0
-#define GC_PMU_EXITPD_MASK_TIMELS0_PD_EXIT_TIMER1_OFFSET 0x4c
-#define GC_PMU_EXITPD_MASK_RBOX_WAKEUP_LSB       0x5
-#define GC_PMU_EXITPD_MASK_RBOX_WAKEUP_MASK      0x20
-#define GC_PMU_EXITPD_MASK_RBOX_WAKEUP_SIZE      0x1
-#define GC_PMU_EXITPD_MASK_RBOX_WAKEUP_DEFAULT   0x0
-#define GC_PMU_EXITPD_MASK_RBOX_WAKEUP_OFFSET    0x4c
-#define GC_PMU_EXITPD_SRC_PIN_PD_EXIT_LSB        0x0
-#define GC_PMU_EXITPD_SRC_PIN_PD_EXIT_MASK       0x1
-#define GC_PMU_EXITPD_SRC_PIN_PD_EXIT_SIZE       0x1
-#define GC_PMU_EXITPD_SRC_PIN_PD_EXIT_DEFAULT    0x0
-#define GC_PMU_EXITPD_SRC_PIN_PD_EXIT_OFFSET     0x50
-#define GC_PMU_EXITPD_SRC_UTMI_SUSPEND_N_LSB     0x1
-#define GC_PMU_EXITPD_SRC_UTMI_SUSPEND_N_MASK    0x2
-#define GC_PMU_EXITPD_SRC_UTMI_SUSPEND_N_SIZE    0x1
-#define GC_PMU_EXITPD_SRC_UTMI_SUSPEND_N_DEFAULT 0x0
-#define GC_PMU_EXITPD_SRC_UTMI_SUSPEND_N_OFFSET  0x50
-#define GC_PMU_EXITPD_SRC_RDD0_PD_EXIT_TIMER_LSB 0x2
-#define GC_PMU_EXITPD_SRC_RDD0_PD_EXIT_TIMER_MASK 0x4
-#define GC_PMU_EXITPD_SRC_RDD0_PD_EXIT_TIMER_SIZE 0x1
-#define GC_PMU_EXITPD_SRC_RDD0_PD_EXIT_TIMER_DEFAULT 0x0
-#define GC_PMU_EXITPD_SRC_RDD0_PD_EXIT_TIMER_OFFSET 0x50
-#define GC_PMU_EXITPD_SRC_TIMELS0_PD_EXIT_TIMER0_LSB 0x3
-#define GC_PMU_EXITPD_SRC_TIMELS0_PD_EXIT_TIMER0_MASK 0x8
-#define GC_PMU_EXITPD_SRC_TIMELS0_PD_EXIT_TIMER0_SIZE 0x1
-#define GC_PMU_EXITPD_SRC_TIMELS0_PD_EXIT_TIMER0_DEFAULT 0x0
-#define GC_PMU_EXITPD_SRC_TIMELS0_PD_EXIT_TIMER0_OFFSET 0x50
-#define GC_PMU_EXITPD_SRC_TIMELS0_PD_EXIT_TIMER1_LSB 0x4
-#define GC_PMU_EXITPD_SRC_TIMELS0_PD_EXIT_TIMER1_MASK 0x10
-#define GC_PMU_EXITPD_SRC_TIMELS0_PD_EXIT_TIMER1_SIZE 0x1
-#define GC_PMU_EXITPD_SRC_TIMELS0_PD_EXIT_TIMER1_DEFAULT 0x0
-#define GC_PMU_EXITPD_SRC_TIMELS0_PD_EXIT_TIMER1_OFFSET 0x50
-#define GC_PMU_EXITPD_SRC_RBOX_WAKEUP_LSB        0x5
-#define GC_PMU_EXITPD_SRC_RBOX_WAKEUP_MASK       0x20
-#define GC_PMU_EXITPD_SRC_RBOX_WAKEUP_SIZE       0x1
-#define GC_PMU_EXITPD_SRC_RBOX_WAKEUP_DEFAULT    0x0
-#define GC_PMU_EXITPD_SRC_RBOX_WAKEUP_OFFSET     0x50
-#define GC_PMU_EXITPD_MON_PIN_PD_EXIT_LSB        0x0
-#define GC_PMU_EXITPD_MON_PIN_PD_EXIT_MASK       0x1
-#define GC_PMU_EXITPD_MON_PIN_PD_EXIT_SIZE       0x1
-#define GC_PMU_EXITPD_MON_PIN_PD_EXIT_DEFAULT    0x0
-#define GC_PMU_EXITPD_MON_PIN_PD_EXIT_OFFSET     0x54
-#define GC_PMU_EXITPD_MON_UTMI_SUSPEND_N_LSB     0x1
-#define GC_PMU_EXITPD_MON_UTMI_SUSPEND_N_MASK    0x2
-#define GC_PMU_EXITPD_MON_UTMI_SUSPEND_N_SIZE    0x1
-#define GC_PMU_EXITPD_MON_UTMI_SUSPEND_N_DEFAULT 0x0
-#define GC_PMU_EXITPD_MON_UTMI_SUSPEND_N_OFFSET  0x54
-#define GC_PMU_EXITPD_MON_RDD0_PD_EXIT_TIMER_LSB 0x2
-#define GC_PMU_EXITPD_MON_RDD0_PD_EXIT_TIMER_MASK 0x4
-#define GC_PMU_EXITPD_MON_RDD0_PD_EXIT_TIMER_SIZE 0x1
-#define GC_PMU_EXITPD_MON_RDD0_PD_EXIT_TIMER_DEFAULT 0x0
-#define GC_PMU_EXITPD_MON_RDD0_PD_EXIT_TIMER_OFFSET 0x54
-#define GC_PMU_EXITPD_MON_TIMELS0_PD_EXIT_TIMER0_LSB 0x3
-#define GC_PMU_EXITPD_MON_TIMELS0_PD_EXIT_TIMER0_MASK 0x8
-#define GC_PMU_EXITPD_MON_TIMELS0_PD_EXIT_TIMER0_SIZE 0x1
-#define GC_PMU_EXITPD_MON_TIMELS0_PD_EXIT_TIMER0_DEFAULT 0x0
-#define GC_PMU_EXITPD_MON_TIMELS0_PD_EXIT_TIMER0_OFFSET 0x54
-#define GC_PMU_EXITPD_MON_TIMELS0_PD_EXIT_TIMER1_LSB 0x4
-#define GC_PMU_EXITPD_MON_TIMELS0_PD_EXIT_TIMER1_MASK 0x10
-#define GC_PMU_EXITPD_MON_TIMELS0_PD_EXIT_TIMER1_SIZE 0x1
-#define GC_PMU_EXITPD_MON_TIMELS0_PD_EXIT_TIMER1_DEFAULT 0x0
-#define GC_PMU_EXITPD_MON_TIMELS0_PD_EXIT_TIMER1_OFFSET 0x54
-#define GC_PMU_EXITPD_MON_RBOX_WAKEUP_LSB        0x5
-#define GC_PMU_EXITPD_MON_RBOX_WAKEUP_MASK       0x20
-#define GC_PMU_EXITPD_MON_RBOX_WAKEUP_SIZE       0x1
-#define GC_PMU_EXITPD_MON_RBOX_WAKEUP_DEFAULT    0x0
-#define GC_PMU_EXITPD_MON_RBOX_WAKEUP_OFFSET     0x54
-#define GC_PMU_OSC_CTRL_XTL_READYB_LSB           0x0
-#define GC_PMU_OSC_CTRL_XTL_READYB_MASK          0x1
-#define GC_PMU_OSC_CTRL_XTL_READYB_SIZE          0x1
-#define GC_PMU_OSC_CTRL_XTL_READYB_DEFAULT       0x1
-#define GC_PMU_OSC_CTRL_XTL_READYB_OFFSET        0x58
-#define GC_PMU_MEMCLKSET_MEM_BANK_CLK0_LSB       0x0
-#define GC_PMU_MEMCLKSET_MEM_BANK_CLK0_MASK      0x1
-#define GC_PMU_MEMCLKSET_MEM_BANK_CLK0_SIZE      0x1
-#define GC_PMU_MEMCLKSET_MEM_BANK_CLK0_DEFAULT   0x1
-#define GC_PMU_MEMCLKSET_MEM_BANK_CLK0_OFFSET    0x5c
-#define GC_PMU_MEMCLKSET_MEM_BANK_CLK1_LSB       0x1
-#define GC_PMU_MEMCLKSET_MEM_BANK_CLK1_MASK      0x2
-#define GC_PMU_MEMCLKSET_MEM_BANK_CLK1_SIZE      0x1
-#define GC_PMU_MEMCLKSET_MEM_BANK_CLK1_DEFAULT   0x1
-#define GC_PMU_MEMCLKSET_MEM_BANK_CLK1_OFFSET    0x5c
-#define GC_PMU_MEMCLKSET_MEM_BANK_CLK2_LSB       0x2
-#define GC_PMU_MEMCLKSET_MEM_BANK_CLK2_MASK      0x4
-#define GC_PMU_MEMCLKSET_MEM_BANK_CLK2_SIZE      0x1
-#define GC_PMU_MEMCLKSET_MEM_BANK_CLK2_DEFAULT   0x1
-#define GC_PMU_MEMCLKSET_MEM_BANK_CLK2_OFFSET    0x5c
-#define GC_PMU_MEMCLKSET_MEM_BANK_CLK3_LSB       0x3
-#define GC_PMU_MEMCLKSET_MEM_BANK_CLK3_MASK      0x8
-#define GC_PMU_MEMCLKSET_MEM_BANK_CLK3_SIZE      0x1
-#define GC_PMU_MEMCLKSET_MEM_BANK_CLK3_DEFAULT   0x1
-#define GC_PMU_MEMCLKSET_MEM_BANK_CLK3_OFFSET    0x5c
-#define GC_PMU_MEMCLKSET_MEM_BANK_CLK4_LSB       0x4
-#define GC_PMU_MEMCLKSET_MEM_BANK_CLK4_MASK      0x10
-#define GC_PMU_MEMCLKSET_MEM_BANK_CLK4_SIZE      0x1
-#define GC_PMU_MEMCLKSET_MEM_BANK_CLK4_DEFAULT   0x1
-#define GC_PMU_MEMCLKSET_MEM_BANK_CLK4_OFFSET    0x5c
-#define GC_PMU_MEMCLKSET_MEM_BANK_CLK5_LSB       0x5
-#define GC_PMU_MEMCLKSET_MEM_BANK_CLK5_MASK      0x20
-#define GC_PMU_MEMCLKSET_MEM_BANK_CLK5_SIZE      0x1
-#define GC_PMU_MEMCLKSET_MEM_BANK_CLK5_DEFAULT   0x1
-#define GC_PMU_MEMCLKSET_MEM_BANK_CLK5_OFFSET    0x5c
-#define GC_PMU_MEMCLKSET_MEM_BANK_CLK6_LSB       0x6
-#define GC_PMU_MEMCLKSET_MEM_BANK_CLK6_MASK      0x40
-#define GC_PMU_MEMCLKSET_MEM_BANK_CLK6_SIZE      0x1
-#define GC_PMU_MEMCLKSET_MEM_BANK_CLK6_DEFAULT   0x1
-#define GC_PMU_MEMCLKSET_MEM_BANK_CLK6_OFFSET    0x5c
-#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK0_LSB       0x0
-#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK0_MASK      0x1
-#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK0_SIZE      0x1
-#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK0_DEFAULT   0x1
-#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK0_OFFSET    0x60
-#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK1_LSB       0x1
-#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK1_MASK      0x2
-#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK1_SIZE      0x1
-#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK1_DEFAULT   0x1
-#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK1_OFFSET    0x60
-#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK2_LSB       0x2
-#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK2_MASK      0x4
-#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK2_SIZE      0x1
-#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK2_DEFAULT   0x1
-#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK2_OFFSET    0x60
-#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK3_LSB       0x3
-#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK3_MASK      0x8
-#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK3_SIZE      0x1
-#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK3_DEFAULT   0x1
-#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK3_OFFSET    0x60
-#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK4_LSB       0x4
-#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK4_MASK      0x10
-#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK4_SIZE      0x1
-#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK4_DEFAULT   0x1
-#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK4_OFFSET    0x60
-#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK5_LSB       0x5
-#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK5_MASK      0x20
-#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK5_SIZE      0x1
-#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK5_DEFAULT   0x1
-#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK5_OFFSET    0x60
-#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK6_LSB       0x6
-#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK6_MASK      0x40
-#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK6_SIZE      0x1
-#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK6_DEFAULT   0x1
-#define GC_PMU_MEMCLKCLR_MEM_BANK_CLK6_OFFSET    0x60
-#define GC_PMU_PERICLKSET0_DCAMO0_CLK_LSB        0x0
-#define GC_PMU_PERICLKSET0_DCAMO0_CLK_MASK       0x1
-#define GC_PMU_PERICLKSET0_DCAMO0_CLK_SIZE       0x1
-#define GC_PMU_PERICLKSET0_DCAMO0_CLK_DEFAULT    0x1
-#define GC_PMU_PERICLKSET0_DCAMO0_CLK_OFFSET     0x64
-#define GC_PMU_PERICLKSET0_DCRYPTO0_CLK_LSB      0x1
-#define GC_PMU_PERICLKSET0_DCRYPTO0_CLK_MASK     0x2
-#define GC_PMU_PERICLKSET0_DCRYPTO0_CLK_SIZE     0x1
-#define GC_PMU_PERICLKSET0_DCRYPTO0_CLK_DEFAULT  0x1
-#define GC_PMU_PERICLKSET0_DCRYPTO0_CLK_OFFSET   0x64
-#define GC_PMU_PERICLKSET0_DDMA0_CLK_LSB         0x2
-#define GC_PMU_PERICLKSET0_DDMA0_CLK_MASK        0x4
-#define GC_PMU_PERICLKSET0_DDMA0_CLK_SIZE        0x1
-#define GC_PMU_PERICLKSET0_DDMA0_CLK_DEFAULT     0x0
-#define GC_PMU_PERICLKSET0_DDMA0_CLK_OFFSET      0x64
-#define GC_PMU_PERICLKSET0_DFLASH0_CLK_LSB       0x3
-#define GC_PMU_PERICLKSET0_DFLASH0_CLK_MASK      0x8
-#define GC_PMU_PERICLKSET0_DFLASH0_CLK_SIZE      0x1
-#define GC_PMU_PERICLKSET0_DFLASH0_CLK_DEFAULT   0x1
-#define GC_PMU_PERICLKSET0_DFLASH0_CLK_OFFSET    0x64
-#define GC_PMU_PERICLKSET0_DFUSE0_CLK_LSB        0x4
-#define GC_PMU_PERICLKSET0_DFUSE0_CLK_MASK       0x10
-#define GC_PMU_PERICLKSET0_DFUSE0_CLK_SIZE       0x1
-#define GC_PMU_PERICLKSET0_DFUSE0_CLK_DEFAULT    0x1
-#define GC_PMU_PERICLKSET0_DFUSE0_CLK_OFFSET     0x64
-#define GC_PMU_PERICLKSET0_DGLOBALSEC_CLK_LSB    0x5
-#define GC_PMU_PERICLKSET0_DGLOBALSEC_CLK_MASK   0x20
-#define GC_PMU_PERICLKSET0_DGLOBALSEC_CLK_SIZE   0x1
-#define GC_PMU_PERICLKSET0_DGLOBALSEC_CLK_DEFAULT 0x1
-#define GC_PMU_PERICLKSET0_DGLOBALSEC_CLK_OFFSET 0x64
-#define GC_PMU_PERICLKSET0_DGLOBALSEC_CLK_TIMER_LSB 0x6
-#define GC_PMU_PERICLKSET0_DGLOBALSEC_CLK_TIMER_MASK 0x40
-#define GC_PMU_PERICLKSET0_DGLOBALSEC_CLK_TIMER_SIZE 0x1
-#define GC_PMU_PERICLKSET0_DGLOBALSEC_CLK_TIMER_DEFAULT 0x1
-#define GC_PMU_PERICLKSET0_DGLOBALSEC_CLK_TIMER_OFFSET 0x64
-#define GC_PMU_PERICLKSET0_DGLOBALSEC_CLK_HS_LSB 0x7
-#define GC_PMU_PERICLKSET0_DGLOBALSEC_CLK_HS_MASK 0x80
-#define GC_PMU_PERICLKSET0_DGLOBALSEC_CLK_HS_SIZE 0x1
-#define GC_PMU_PERICLKSET0_DGLOBALSEC_CLK_HS_DEFAULT 0x1
-#define GC_PMU_PERICLKSET0_DGLOBALSEC_CLK_HS_OFFSET 0x64
-#define GC_PMU_PERICLKSET0_DGPIO0_CLK_LSB        0x8
-#define GC_PMU_PERICLKSET0_DGPIO0_CLK_MASK       0x100
-#define GC_PMU_PERICLKSET0_DGPIO0_CLK_SIZE       0x1
-#define GC_PMU_PERICLKSET0_DGPIO0_CLK_DEFAULT    0x0
-#define GC_PMU_PERICLKSET0_DGPIO0_CLK_OFFSET     0x64
-#define GC_PMU_PERICLKSET0_DGPIO1_CLK_LSB        0x9
-#define GC_PMU_PERICLKSET0_DGPIO1_CLK_MASK       0x200
-#define GC_PMU_PERICLKSET0_DGPIO1_CLK_SIZE       0x1
-#define GC_PMU_PERICLKSET0_DGPIO1_CLK_DEFAULT    0x0
-#define GC_PMU_PERICLKSET0_DGPIO1_CLK_OFFSET     0x64
-#define GC_PMU_PERICLKSET0_DI2C0_CLK_TIMER_LSB   0xa
-#define GC_PMU_PERICLKSET0_DI2C0_CLK_TIMER_MASK  0x400
-#define GC_PMU_PERICLKSET0_DI2C0_CLK_TIMER_SIZE  0x1
-#define GC_PMU_PERICLKSET0_DI2C0_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_PERICLKSET0_DI2C0_CLK_TIMER_OFFSET 0x64
-#define GC_PMU_PERICLKSET0_DI2C1_CLK_TIMER_LSB   0xb
-#define GC_PMU_PERICLKSET0_DI2C1_CLK_TIMER_MASK  0x800
-#define GC_PMU_PERICLKSET0_DI2C1_CLK_TIMER_SIZE  0x1
-#define GC_PMU_PERICLKSET0_DI2C1_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_PERICLKSET0_DI2C1_CLK_TIMER_OFFSET 0x64
-#define GC_PMU_PERICLKSET0_DI2CS0_CLK_LSB        0xc
-#define GC_PMU_PERICLKSET0_DI2CS0_CLK_MASK       0x1000
-#define GC_PMU_PERICLKSET0_DI2CS0_CLK_SIZE       0x1
-#define GC_PMU_PERICLKSET0_DI2CS0_CLK_DEFAULT    0x0
-#define GC_PMU_PERICLKSET0_DI2CS0_CLK_OFFSET     0x64
-#define GC_PMU_PERICLKSET0_DKEYMGR0_CLK_LSB      0xd
-#define GC_PMU_PERICLKSET0_DKEYMGR0_CLK_MASK     0x2000
-#define GC_PMU_PERICLKSET0_DKEYMGR0_CLK_SIZE     0x1
-#define GC_PMU_PERICLKSET0_DKEYMGR0_CLK_DEFAULT  0x1
-#define GC_PMU_PERICLKSET0_DKEYMGR0_CLK_OFFSET   0x64
-#define GC_PMU_PERICLKSET0_DPERI_APB0_CLK_LSB    0xe
-#define GC_PMU_PERICLKSET0_DPERI_APB0_CLK_MASK   0x4000
-#define GC_PMU_PERICLKSET0_DPERI_APB0_CLK_SIZE   0x1
-#define GC_PMU_PERICLKSET0_DPERI_APB0_CLK_DEFAULT 0x1
-#define GC_PMU_PERICLKSET0_DPERI_APB0_CLK_OFFSET 0x64
-#define GC_PMU_PERICLKSET0_DPERI_APB1_CLK_LSB    0xf
-#define GC_PMU_PERICLKSET0_DPERI_APB1_CLK_MASK   0x8000
-#define GC_PMU_PERICLKSET0_DPERI_APB1_CLK_SIZE   0x1
-#define GC_PMU_PERICLKSET0_DPERI_APB1_CLK_DEFAULT 0x1
-#define GC_PMU_PERICLKSET0_DPERI_APB1_CLK_OFFSET 0x64
-#define GC_PMU_PERICLKSET0_DPERI_APB2_CLK_LSB    0x10
-#define GC_PMU_PERICLKSET0_DPERI_APB2_CLK_MASK   0x10000
-#define GC_PMU_PERICLKSET0_DPERI_APB2_CLK_SIZE   0x1
-#define GC_PMU_PERICLKSET0_DPERI_APB2_CLK_DEFAULT 0x1
-#define GC_PMU_PERICLKSET0_DPERI_APB2_CLK_OFFSET 0x64
-#define GC_PMU_PERICLKSET0_DPERI_APB2_CLK_TIMER_LSB 0x11
-#define GC_PMU_PERICLKSET0_DPERI_APB2_CLK_TIMER_MASK 0x20000
-#define GC_PMU_PERICLKSET0_DPERI_APB2_CLK_TIMER_SIZE 0x1
-#define GC_PMU_PERICLKSET0_DPERI_APB2_CLK_TIMER_DEFAULT 0x1
-#define GC_PMU_PERICLKSET0_DPERI_APB2_CLK_TIMER_OFFSET 0x64
-#define GC_PMU_PERICLKSET0_DPERI_APB3_CLK_LSB    0x12
-#define GC_PMU_PERICLKSET0_DPERI_APB3_CLK_MASK   0x40000
-#define GC_PMU_PERICLKSET0_DPERI_APB3_CLK_SIZE   0x1
-#define GC_PMU_PERICLKSET0_DPERI_APB3_CLK_DEFAULT 0x1
-#define GC_PMU_PERICLKSET0_DPERI_APB3_CLK_OFFSET 0x64
-#define GC_PMU_PERICLKSET0_DPERI_APB3_CLK_HS_LSB 0x13
-#define GC_PMU_PERICLKSET0_DPERI_APB3_CLK_HS_MASK 0x80000
-#define GC_PMU_PERICLKSET0_DPERI_APB3_CLK_HS_SIZE 0x1
-#define GC_PMU_PERICLKSET0_DPERI_APB3_CLK_HS_DEFAULT 0x1
-#define GC_PMU_PERICLKSET0_DPERI_APB3_CLK_HS_OFFSET 0x64
-#define GC_PMU_PERICLKSET0_DPINMUX_CLK_LSB       0x14
-#define GC_PMU_PERICLKSET0_DPINMUX_CLK_MASK      0x100000
-#define GC_PMU_PERICLKSET0_DPINMUX_CLK_SIZE      0x1
-#define GC_PMU_PERICLKSET0_DPINMUX_CLK_DEFAULT   0x1
-#define GC_PMU_PERICLKSET0_DPINMUX_CLK_OFFSET    0x64
-#define GC_PMU_PERICLKSET0_DPMU_CLK_LSB          0x15
-#define GC_PMU_PERICLKSET0_DPMU_CLK_MASK         0x200000
-#define GC_PMU_PERICLKSET0_DPMU_CLK_SIZE         0x1
-#define GC_PMU_PERICLKSET0_DPMU_CLK_DEFAULT      0x1
-#define GC_PMU_PERICLKSET0_DPMU_CLK_OFFSET       0x64
-#define GC_PMU_PERICLKSET0_DRBOX0_CLK_LSB        0x16
-#define GC_PMU_PERICLKSET0_DRBOX0_CLK_MASK       0x400000
-#define GC_PMU_PERICLKSET0_DRBOX0_CLK_SIZE       0x1
-#define GC_PMU_PERICLKSET0_DRBOX0_CLK_DEFAULT    0x0
-#define GC_PMU_PERICLKSET0_DRBOX0_CLK_OFFSET     0x64
-#define GC_PMU_PERICLKSET0_DRDD0_CLK_LSB         0x17
-#define GC_PMU_PERICLKSET0_DRDD0_CLK_MASK        0x800000
-#define GC_PMU_PERICLKSET0_DRDD0_CLK_SIZE        0x1
-#define GC_PMU_PERICLKSET0_DRDD0_CLK_DEFAULT     0x0
-#define GC_PMU_PERICLKSET0_DRDD0_CLK_OFFSET      0x64
-#define GC_PMU_PERICLKSET0_DRTC0_CLK_LSB         0x18
-#define GC_PMU_PERICLKSET0_DRTC0_CLK_MASK        0x1000000
-#define GC_PMU_PERICLKSET0_DRTC0_CLK_SIZE        0x1
-#define GC_PMU_PERICLKSET0_DRTC0_CLK_DEFAULT     0x1
-#define GC_PMU_PERICLKSET0_DRTC0_CLK_OFFSET      0x64
-#define GC_PMU_PERICLKSET0_DRTC0_CLK_TIMER_LSB   0x19
-#define GC_PMU_PERICLKSET0_DRTC0_CLK_TIMER_MASK  0x2000000
-#define GC_PMU_PERICLKSET0_DRTC0_CLK_TIMER_SIZE  0x1
-#define GC_PMU_PERICLKSET0_DRTC0_CLK_TIMER_DEFAULT 0x1
-#define GC_PMU_PERICLKSET0_DRTC0_CLK_TIMER_OFFSET 0x64
-#define GC_PMU_PERICLKSET0_DSPI0_CLK_HS_LSB      0x1a
-#define GC_PMU_PERICLKSET0_DSPI0_CLK_HS_MASK     0x4000000
-#define GC_PMU_PERICLKSET0_DSPI0_CLK_HS_SIZE     0x1
-#define GC_PMU_PERICLKSET0_DSPI0_CLK_HS_DEFAULT  0x1
-#define GC_PMU_PERICLKSET0_DSPI0_CLK_HS_OFFSET   0x64
-#define GC_PMU_PERICLKSET0_DSPI1_CLK_HS_LSB      0x1b
-#define GC_PMU_PERICLKSET0_DSPI1_CLK_HS_MASK     0x8000000
-#define GC_PMU_PERICLKSET0_DSPI1_CLK_HS_SIZE     0x1
-#define GC_PMU_PERICLKSET0_DSPI1_CLK_HS_DEFAULT  0x1
-#define GC_PMU_PERICLKSET0_DSPI1_CLK_HS_OFFSET   0x64
-#define GC_PMU_PERICLKSET0_DSPS0_CLK_LSB         0x1c
-#define GC_PMU_PERICLKSET0_DSPS0_CLK_MASK        0x10000000
-#define GC_PMU_PERICLKSET0_DSPS0_CLK_SIZE        0x1
-#define GC_PMU_PERICLKSET0_DSPS0_CLK_DEFAULT     0x1
-#define GC_PMU_PERICLKSET0_DSPS0_CLK_OFFSET      0x64
-#define GC_PMU_PERICLKSET0_DSPS0_CLK_TIMER_HS_LSB 0x1d
-#define GC_PMU_PERICLKSET0_DSPS0_CLK_TIMER_HS_MASK 0x20000000
-#define GC_PMU_PERICLKSET0_DSPS0_CLK_TIMER_HS_SIZE 0x1
-#define GC_PMU_PERICLKSET0_DSPS0_CLK_TIMER_HS_DEFAULT 0x1
-#define GC_PMU_PERICLKSET0_DSPS0_CLK_TIMER_HS_OFFSET 0x64
-#define GC_PMU_PERICLKSET0_DSWDP0_CLK_LSB        0x1e
-#define GC_PMU_PERICLKSET0_DSWDP0_CLK_MASK       0x40000000
-#define GC_PMU_PERICLKSET0_DSWDP0_CLK_SIZE       0x1
-#define GC_PMU_PERICLKSET0_DSWDP0_CLK_DEFAULT    0x1
-#define GC_PMU_PERICLKSET0_DSWDP0_CLK_OFFSET     0x64
-#define GC_PMU_PERICLKSET0_DTEMP0_CLK_LSB        0x1f
-#define GC_PMU_PERICLKSET0_DTEMP0_CLK_MASK       0x80000000
-#define GC_PMU_PERICLKSET0_DTEMP0_CLK_SIZE       0x1
-#define GC_PMU_PERICLKSET0_DTEMP0_CLK_DEFAULT    0x1
-#define GC_PMU_PERICLKSET0_DTEMP0_CLK_OFFSET     0x64
-#define GC_PMU_PERICLKCLR0_DCAMO0_CLK_LSB        0x0
-#define GC_PMU_PERICLKCLR0_DCAMO0_CLK_MASK       0x1
-#define GC_PMU_PERICLKCLR0_DCAMO0_CLK_SIZE       0x1
-#define GC_PMU_PERICLKCLR0_DCAMO0_CLK_DEFAULT    0x1
-#define GC_PMU_PERICLKCLR0_DCAMO0_CLK_OFFSET     0x68
-#define GC_PMU_PERICLKCLR0_DCRYPTO0_CLK_LSB      0x1
-#define GC_PMU_PERICLKCLR0_DCRYPTO0_CLK_MASK     0x2
-#define GC_PMU_PERICLKCLR0_DCRYPTO0_CLK_SIZE     0x1
-#define GC_PMU_PERICLKCLR0_DCRYPTO0_CLK_DEFAULT  0x1
-#define GC_PMU_PERICLKCLR0_DCRYPTO0_CLK_OFFSET   0x68
-#define GC_PMU_PERICLKCLR0_DDMA0_CLK_LSB         0x2
-#define GC_PMU_PERICLKCLR0_DDMA0_CLK_MASK        0x4
-#define GC_PMU_PERICLKCLR0_DDMA0_CLK_SIZE        0x1
-#define GC_PMU_PERICLKCLR0_DDMA0_CLK_DEFAULT     0x0
-#define GC_PMU_PERICLKCLR0_DDMA0_CLK_OFFSET      0x68
-#define GC_PMU_PERICLKCLR0_DFLASH0_CLK_LSB       0x3
-#define GC_PMU_PERICLKCLR0_DFLASH0_CLK_MASK      0x8
-#define GC_PMU_PERICLKCLR0_DFLASH0_CLK_SIZE      0x1
-#define GC_PMU_PERICLKCLR0_DFLASH0_CLK_DEFAULT   0x1
-#define GC_PMU_PERICLKCLR0_DFLASH0_CLK_OFFSET    0x68
-#define GC_PMU_PERICLKCLR0_DFUSE0_CLK_LSB        0x4
-#define GC_PMU_PERICLKCLR0_DFUSE0_CLK_MASK       0x10
-#define GC_PMU_PERICLKCLR0_DFUSE0_CLK_SIZE       0x1
-#define GC_PMU_PERICLKCLR0_DFUSE0_CLK_DEFAULT    0x1
-#define GC_PMU_PERICLKCLR0_DFUSE0_CLK_OFFSET     0x68
-#define GC_PMU_PERICLKCLR0_DGLOBALSEC_CLK_LSB    0x5
-#define GC_PMU_PERICLKCLR0_DGLOBALSEC_CLK_MASK   0x20
-#define GC_PMU_PERICLKCLR0_DGLOBALSEC_CLK_SIZE   0x1
-#define GC_PMU_PERICLKCLR0_DGLOBALSEC_CLK_DEFAULT 0x1
-#define GC_PMU_PERICLKCLR0_DGLOBALSEC_CLK_OFFSET 0x68
-#define GC_PMU_PERICLKCLR0_DGLOBALSEC_CLK_TIMER_LSB 0x6
-#define GC_PMU_PERICLKCLR0_DGLOBALSEC_CLK_TIMER_MASK 0x40
-#define GC_PMU_PERICLKCLR0_DGLOBALSEC_CLK_TIMER_SIZE 0x1
-#define GC_PMU_PERICLKCLR0_DGLOBALSEC_CLK_TIMER_DEFAULT 0x1
-#define GC_PMU_PERICLKCLR0_DGLOBALSEC_CLK_TIMER_OFFSET 0x68
-#define GC_PMU_PERICLKCLR0_DGLOBALSEC_CLK_HS_LSB 0x7
-#define GC_PMU_PERICLKCLR0_DGLOBALSEC_CLK_HS_MASK 0x80
-#define GC_PMU_PERICLKCLR0_DGLOBALSEC_CLK_HS_SIZE 0x1
-#define GC_PMU_PERICLKCLR0_DGLOBALSEC_CLK_HS_DEFAULT 0x1
-#define GC_PMU_PERICLKCLR0_DGLOBALSEC_CLK_HS_OFFSET 0x68
-#define GC_PMU_PERICLKCLR0_DGPIO0_CLK_LSB        0x8
-#define GC_PMU_PERICLKCLR0_DGPIO0_CLK_MASK       0x100
-#define GC_PMU_PERICLKCLR0_DGPIO0_CLK_SIZE       0x1
-#define GC_PMU_PERICLKCLR0_DGPIO0_CLK_DEFAULT    0x0
-#define GC_PMU_PERICLKCLR0_DGPIO0_CLK_OFFSET     0x68
-#define GC_PMU_PERICLKCLR0_DGPIO1_CLK_LSB        0x9
-#define GC_PMU_PERICLKCLR0_DGPIO1_CLK_MASK       0x200
-#define GC_PMU_PERICLKCLR0_DGPIO1_CLK_SIZE       0x1
-#define GC_PMU_PERICLKCLR0_DGPIO1_CLK_DEFAULT    0x0
-#define GC_PMU_PERICLKCLR0_DGPIO1_CLK_OFFSET     0x68
-#define GC_PMU_PERICLKCLR0_DI2C0_CLK_TIMER_LSB   0xa
-#define GC_PMU_PERICLKCLR0_DI2C0_CLK_TIMER_MASK  0x400
-#define GC_PMU_PERICLKCLR0_DI2C0_CLK_TIMER_SIZE  0x1
-#define GC_PMU_PERICLKCLR0_DI2C0_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_PERICLKCLR0_DI2C0_CLK_TIMER_OFFSET 0x68
-#define GC_PMU_PERICLKCLR0_DI2C1_CLK_TIMER_LSB   0xb
-#define GC_PMU_PERICLKCLR0_DI2C1_CLK_TIMER_MASK  0x800
-#define GC_PMU_PERICLKCLR0_DI2C1_CLK_TIMER_SIZE  0x1
-#define GC_PMU_PERICLKCLR0_DI2C1_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_PERICLKCLR0_DI2C1_CLK_TIMER_OFFSET 0x68
-#define GC_PMU_PERICLKCLR0_DI2CS0_CLK_LSB        0xc
-#define GC_PMU_PERICLKCLR0_DI2CS0_CLK_MASK       0x1000
-#define GC_PMU_PERICLKCLR0_DI2CS0_CLK_SIZE       0x1
-#define GC_PMU_PERICLKCLR0_DI2CS0_CLK_DEFAULT    0x0
-#define GC_PMU_PERICLKCLR0_DI2CS0_CLK_OFFSET     0x68
-#define GC_PMU_PERICLKCLR0_DKEYMGR0_CLK_LSB      0xd
-#define GC_PMU_PERICLKCLR0_DKEYMGR0_CLK_MASK     0x2000
-#define GC_PMU_PERICLKCLR0_DKEYMGR0_CLK_SIZE     0x1
-#define GC_PMU_PERICLKCLR0_DKEYMGR0_CLK_DEFAULT  0x1
-#define GC_PMU_PERICLKCLR0_DKEYMGR0_CLK_OFFSET   0x68
-#define GC_PMU_PERICLKCLR0_DPERI_APB0_CLK_LSB    0xe
-#define GC_PMU_PERICLKCLR0_DPERI_APB0_CLK_MASK   0x4000
-#define GC_PMU_PERICLKCLR0_DPERI_APB0_CLK_SIZE   0x1
-#define GC_PMU_PERICLKCLR0_DPERI_APB0_CLK_DEFAULT 0x1
-#define GC_PMU_PERICLKCLR0_DPERI_APB0_CLK_OFFSET 0x68
-#define GC_PMU_PERICLKCLR0_DPERI_APB1_CLK_LSB    0xf
-#define GC_PMU_PERICLKCLR0_DPERI_APB1_CLK_MASK   0x8000
-#define GC_PMU_PERICLKCLR0_DPERI_APB1_CLK_SIZE   0x1
-#define GC_PMU_PERICLKCLR0_DPERI_APB1_CLK_DEFAULT 0x1
-#define GC_PMU_PERICLKCLR0_DPERI_APB1_CLK_OFFSET 0x68
-#define GC_PMU_PERICLKCLR0_DPERI_APB2_CLK_LSB    0x10
-#define GC_PMU_PERICLKCLR0_DPERI_APB2_CLK_MASK   0x10000
-#define GC_PMU_PERICLKCLR0_DPERI_APB2_CLK_SIZE   0x1
-#define GC_PMU_PERICLKCLR0_DPERI_APB2_CLK_DEFAULT 0x1
-#define GC_PMU_PERICLKCLR0_DPERI_APB2_CLK_OFFSET 0x68
-#define GC_PMU_PERICLKCLR0_DPERI_APB2_CLK_TIMER_LSB 0x11
-#define GC_PMU_PERICLKCLR0_DPERI_APB2_CLK_TIMER_MASK 0x20000
-#define GC_PMU_PERICLKCLR0_DPERI_APB2_CLK_TIMER_SIZE 0x1
-#define GC_PMU_PERICLKCLR0_DPERI_APB2_CLK_TIMER_DEFAULT 0x1
-#define GC_PMU_PERICLKCLR0_DPERI_APB2_CLK_TIMER_OFFSET 0x68
-#define GC_PMU_PERICLKCLR0_DPERI_APB3_CLK_LSB    0x12
-#define GC_PMU_PERICLKCLR0_DPERI_APB3_CLK_MASK   0x40000
-#define GC_PMU_PERICLKCLR0_DPERI_APB3_CLK_SIZE   0x1
-#define GC_PMU_PERICLKCLR0_DPERI_APB3_CLK_DEFAULT 0x1
-#define GC_PMU_PERICLKCLR0_DPERI_APB3_CLK_OFFSET 0x68
-#define GC_PMU_PERICLKCLR0_DPERI_APB3_CLK_HS_LSB 0x13
-#define GC_PMU_PERICLKCLR0_DPERI_APB3_CLK_HS_MASK 0x80000
-#define GC_PMU_PERICLKCLR0_DPERI_APB3_CLK_HS_SIZE 0x1
-#define GC_PMU_PERICLKCLR0_DPERI_APB3_CLK_HS_DEFAULT 0x1
-#define GC_PMU_PERICLKCLR0_DPERI_APB3_CLK_HS_OFFSET 0x68
-#define GC_PMU_PERICLKCLR0_DPINMUX_CLK_LSB       0x14
-#define GC_PMU_PERICLKCLR0_DPINMUX_CLK_MASK      0x100000
-#define GC_PMU_PERICLKCLR0_DPINMUX_CLK_SIZE      0x1
-#define GC_PMU_PERICLKCLR0_DPINMUX_CLK_DEFAULT   0x1
-#define GC_PMU_PERICLKCLR0_DPINMUX_CLK_OFFSET    0x68
-#define GC_PMU_PERICLKCLR0_DPMU_CLK_LSB          0x15
-#define GC_PMU_PERICLKCLR0_DPMU_CLK_MASK         0x200000
-#define GC_PMU_PERICLKCLR0_DPMU_CLK_SIZE         0x1
-#define GC_PMU_PERICLKCLR0_DPMU_CLK_DEFAULT      0x1
-#define GC_PMU_PERICLKCLR0_DPMU_CLK_OFFSET       0x68
-#define GC_PMU_PERICLKCLR0_DRBOX0_CLK_LSB        0x16
-#define GC_PMU_PERICLKCLR0_DRBOX0_CLK_MASK       0x400000
-#define GC_PMU_PERICLKCLR0_DRBOX0_CLK_SIZE       0x1
-#define GC_PMU_PERICLKCLR0_DRBOX0_CLK_DEFAULT    0x0
-#define GC_PMU_PERICLKCLR0_DRBOX0_CLK_OFFSET     0x68
-#define GC_PMU_PERICLKCLR0_DRDD0_CLK_LSB         0x17
-#define GC_PMU_PERICLKCLR0_DRDD0_CLK_MASK        0x800000
-#define GC_PMU_PERICLKCLR0_DRDD0_CLK_SIZE        0x1
-#define GC_PMU_PERICLKCLR0_DRDD0_CLK_DEFAULT     0x0
-#define GC_PMU_PERICLKCLR0_DRDD0_CLK_OFFSET      0x68
-#define GC_PMU_PERICLKCLR0_DRTC0_CLK_LSB         0x18
-#define GC_PMU_PERICLKCLR0_DRTC0_CLK_MASK        0x1000000
-#define GC_PMU_PERICLKCLR0_DRTC0_CLK_SIZE        0x1
-#define GC_PMU_PERICLKCLR0_DRTC0_CLK_DEFAULT     0x1
-#define GC_PMU_PERICLKCLR0_DRTC0_CLK_OFFSET      0x68
-#define GC_PMU_PERICLKCLR0_DRTC0_CLK_TIMER_LSB   0x19
-#define GC_PMU_PERICLKCLR0_DRTC0_CLK_TIMER_MASK  0x2000000
-#define GC_PMU_PERICLKCLR0_DRTC0_CLK_TIMER_SIZE  0x1
-#define GC_PMU_PERICLKCLR0_DRTC0_CLK_TIMER_DEFAULT 0x1
-#define GC_PMU_PERICLKCLR0_DRTC0_CLK_TIMER_OFFSET 0x68
-#define GC_PMU_PERICLKCLR0_DSPI0_CLK_HS_LSB      0x1a
-#define GC_PMU_PERICLKCLR0_DSPI0_CLK_HS_MASK     0x4000000
-#define GC_PMU_PERICLKCLR0_DSPI0_CLK_HS_SIZE     0x1
-#define GC_PMU_PERICLKCLR0_DSPI0_CLK_HS_DEFAULT  0x1
-#define GC_PMU_PERICLKCLR0_DSPI0_CLK_HS_OFFSET   0x68
-#define GC_PMU_PERICLKCLR0_DSPI1_CLK_HS_LSB      0x1b
-#define GC_PMU_PERICLKCLR0_DSPI1_CLK_HS_MASK     0x8000000
-#define GC_PMU_PERICLKCLR0_DSPI1_CLK_HS_SIZE     0x1
-#define GC_PMU_PERICLKCLR0_DSPI1_CLK_HS_DEFAULT  0x1
-#define GC_PMU_PERICLKCLR0_DSPI1_CLK_HS_OFFSET   0x68
-#define GC_PMU_PERICLKCLR0_DSPS0_CLK_LSB         0x1c
-#define GC_PMU_PERICLKCLR0_DSPS0_CLK_MASK        0x10000000
-#define GC_PMU_PERICLKCLR0_DSPS0_CLK_SIZE        0x1
-#define GC_PMU_PERICLKCLR0_DSPS0_CLK_DEFAULT     0x1
-#define GC_PMU_PERICLKCLR0_DSPS0_CLK_OFFSET      0x68
-#define GC_PMU_PERICLKCLR0_DSPS0_CLK_TIMER_HS_LSB 0x1d
-#define GC_PMU_PERICLKCLR0_DSPS0_CLK_TIMER_HS_MASK 0x20000000
-#define GC_PMU_PERICLKCLR0_DSPS0_CLK_TIMER_HS_SIZE 0x1
-#define GC_PMU_PERICLKCLR0_DSPS0_CLK_TIMER_HS_DEFAULT 0x1
-#define GC_PMU_PERICLKCLR0_DSPS0_CLK_TIMER_HS_OFFSET 0x68
-#define GC_PMU_PERICLKCLR0_DSWDP0_CLK_LSB        0x1e
-#define GC_PMU_PERICLKCLR0_DSWDP0_CLK_MASK       0x40000000
-#define GC_PMU_PERICLKCLR0_DSWDP0_CLK_SIZE       0x1
-#define GC_PMU_PERICLKCLR0_DSWDP0_CLK_DEFAULT    0x1
-#define GC_PMU_PERICLKCLR0_DSWDP0_CLK_OFFSET     0x68
-#define GC_PMU_PERICLKCLR0_DTEMP0_CLK_LSB        0x1f
-#define GC_PMU_PERICLKCLR0_DTEMP0_CLK_MASK       0x80000000
-#define GC_PMU_PERICLKCLR0_DTEMP0_CLK_SIZE       0x1
-#define GC_PMU_PERICLKCLR0_DTEMP0_CLK_DEFAULT    0x1
-#define GC_PMU_PERICLKCLR0_DTEMP0_CLK_OFFSET     0x68
-#define GC_PMU_PERICLKSET1_DTIMEHS0_CLK_TIMER_LSB 0x0
-#define GC_PMU_PERICLKSET1_DTIMEHS0_CLK_TIMER_MASK 0x1
-#define GC_PMU_PERICLKSET1_DTIMEHS0_CLK_TIMER_SIZE 0x1
-#define GC_PMU_PERICLKSET1_DTIMEHS0_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_PERICLKSET1_DTIMEHS0_CLK_TIMER_OFFSET 0x6c
-#define GC_PMU_PERICLKSET1_DTIMEHS1_CLK_TIMER_LSB 0x1
-#define GC_PMU_PERICLKSET1_DTIMEHS1_CLK_TIMER_MASK 0x2
-#define GC_PMU_PERICLKSET1_DTIMEHS1_CLK_TIMER_SIZE 0x1
-#define GC_PMU_PERICLKSET1_DTIMEHS1_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_PERICLKSET1_DTIMEHS1_CLK_TIMER_OFFSET 0x6c
-#define GC_PMU_PERICLKSET1_DTIMELS0_CLK_LSB      0x2
-#define GC_PMU_PERICLKSET1_DTIMELS0_CLK_MASK     0x4
-#define GC_PMU_PERICLKSET1_DTIMELS0_CLK_SIZE     0x1
-#define GC_PMU_PERICLKSET1_DTIMELS0_CLK_DEFAULT  0x0
-#define GC_PMU_PERICLKSET1_DTIMELS0_CLK_OFFSET   0x6c
-#define GC_PMU_PERICLKSET1_DTIMEUS0_CLK_TIMER_LSB 0x3
-#define GC_PMU_PERICLKSET1_DTIMEUS0_CLK_TIMER_MASK 0x8
-#define GC_PMU_PERICLKSET1_DTIMEUS0_CLK_TIMER_SIZE 0x1
-#define GC_PMU_PERICLKSET1_DTIMEUS0_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_PERICLKSET1_DTIMEUS0_CLK_TIMER_OFFSET 0x6c
-#define GC_PMU_PERICLKSET1_DTRNG0_CLK_LSB        0x4
-#define GC_PMU_PERICLKSET1_DTRNG0_CLK_MASK       0x10
-#define GC_PMU_PERICLKSET1_DTRNG0_CLK_SIZE       0x1
-#define GC_PMU_PERICLKSET1_DTRNG0_CLK_DEFAULT    0x1
-#define GC_PMU_PERICLKSET1_DTRNG0_CLK_OFFSET     0x6c
-#define GC_PMU_PERICLKSET1_DUART0_CLK_TIMER_LSB  0x5
-#define GC_PMU_PERICLKSET1_DUART0_CLK_TIMER_MASK 0x20
-#define GC_PMU_PERICLKSET1_DUART0_CLK_TIMER_SIZE 0x1
-#define GC_PMU_PERICLKSET1_DUART0_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_PERICLKSET1_DUART0_CLK_TIMER_OFFSET 0x6c
-#define GC_PMU_PERICLKSET1_DUART1_CLK_TIMER_LSB  0x6
-#define GC_PMU_PERICLKSET1_DUART1_CLK_TIMER_MASK 0x40
-#define GC_PMU_PERICLKSET1_DUART1_CLK_TIMER_SIZE 0x1
-#define GC_PMU_PERICLKSET1_DUART1_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_PERICLKSET1_DUART1_CLK_TIMER_OFFSET 0x6c
-#define GC_PMU_PERICLKSET1_DUART2_CLK_TIMER_LSB  0x7
-#define GC_PMU_PERICLKSET1_DUART2_CLK_TIMER_MASK 0x80
-#define GC_PMU_PERICLKSET1_DUART2_CLK_TIMER_SIZE 0x1
-#define GC_PMU_PERICLKSET1_DUART2_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_PERICLKSET1_DUART2_CLK_TIMER_OFFSET 0x6c
-#define GC_PMU_PERICLKSET1_DUSB0_CLK_LSB         0x8
-#define GC_PMU_PERICLKSET1_DUSB0_CLK_MASK        0x100
-#define GC_PMU_PERICLKSET1_DUSB0_CLK_SIZE        0x1
-#define GC_PMU_PERICLKSET1_DUSB0_CLK_DEFAULT     0x1
-#define GC_PMU_PERICLKSET1_DUSB0_CLK_OFFSET      0x6c
-#define GC_PMU_PERICLKSET1_DUSB0_CLK_TIMER_HS_LSB 0x9
-#define GC_PMU_PERICLKSET1_DUSB0_CLK_TIMER_HS_MASK 0x200
-#define GC_PMU_PERICLKSET1_DUSB0_CLK_TIMER_HS_SIZE 0x1
-#define GC_PMU_PERICLKSET1_DUSB0_CLK_TIMER_HS_DEFAULT 0x1
-#define GC_PMU_PERICLKSET1_DUSB0_CLK_TIMER_HS_OFFSET 0x6c
-#define GC_PMU_PERICLKSET1_DVOLT0_CLK_LSB        0xa
-#define GC_PMU_PERICLKSET1_DVOLT0_CLK_MASK       0x400
-#define GC_PMU_PERICLKSET1_DVOLT0_CLK_SIZE       0x1
-#define GC_PMU_PERICLKSET1_DVOLT0_CLK_DEFAULT    0x1
-#define GC_PMU_PERICLKSET1_DVOLT0_CLK_OFFSET     0x6c
-#define GC_PMU_PERICLKSET1_DWATCHDOG0_CLK_LSB    0xb
-#define GC_PMU_PERICLKSET1_DWATCHDOG0_CLK_MASK   0x800
-#define GC_PMU_PERICLKSET1_DWATCHDOG0_CLK_SIZE   0x1
-#define GC_PMU_PERICLKSET1_DWATCHDOG0_CLK_DEFAULT 0x1
-#define GC_PMU_PERICLKSET1_DWATCHDOG0_CLK_OFFSET 0x6c
-#define GC_PMU_PERICLKSET1_DXO0_CLK_LSB          0xc
-#define GC_PMU_PERICLKSET1_DXO0_CLK_MASK         0x1000
-#define GC_PMU_PERICLKSET1_DXO0_CLK_SIZE         0x1
-#define GC_PMU_PERICLKSET1_DXO0_CLK_DEFAULT      0x1
-#define GC_PMU_PERICLKSET1_DXO0_CLK_OFFSET       0x6c
-#define GC_PMU_PERICLKSET1_DXO0_CLK_TIMER_LSB    0xd
-#define GC_PMU_PERICLKSET1_DXO0_CLK_TIMER_MASK   0x2000
-#define GC_PMU_PERICLKSET1_DXO0_CLK_TIMER_SIZE   0x1
-#define GC_PMU_PERICLKSET1_DXO0_CLK_TIMER_DEFAULT 0x1
-#define GC_PMU_PERICLKSET1_DXO0_CLK_TIMER_OFFSET 0x6c
-#define GC_PMU_PERICLKSET1_PERI_MASTER_MATRIX_CLK_LSB 0xe
-#define GC_PMU_PERICLKSET1_PERI_MASTER_MATRIX_CLK_MASK 0x4000
-#define GC_PMU_PERICLKSET1_PERI_MASTER_MATRIX_CLK_SIZE 0x1
-#define GC_PMU_PERICLKSET1_PERI_MASTER_MATRIX_CLK_DEFAULT 0x1
-#define GC_PMU_PERICLKSET1_PERI_MASTER_MATRIX_CLK_OFFSET 0x6c
-#define GC_PMU_PERICLKSET1_PERI_MATRIX_CLK_LSB   0xf
-#define GC_PMU_PERICLKSET1_PERI_MATRIX_CLK_MASK  0x8000
-#define GC_PMU_PERICLKSET1_PERI_MATRIX_CLK_SIZE  0x1
-#define GC_PMU_PERICLKSET1_PERI_MATRIX_CLK_DEFAULT 0x1
-#define GC_PMU_PERICLKSET1_PERI_MATRIX_CLK_OFFSET 0x6c
-#define GC_PMU_PERICLKCLR1_DTIMEHS0_CLK_TIMER_LSB 0x0
-#define GC_PMU_PERICLKCLR1_DTIMEHS0_CLK_TIMER_MASK 0x1
-#define GC_PMU_PERICLKCLR1_DTIMEHS0_CLK_TIMER_SIZE 0x1
-#define GC_PMU_PERICLKCLR1_DTIMEHS0_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_PERICLKCLR1_DTIMEHS0_CLK_TIMER_OFFSET 0x70
-#define GC_PMU_PERICLKCLR1_DTIMEHS1_CLK_TIMER_LSB 0x1
-#define GC_PMU_PERICLKCLR1_DTIMEHS1_CLK_TIMER_MASK 0x2
-#define GC_PMU_PERICLKCLR1_DTIMEHS1_CLK_TIMER_SIZE 0x1
-#define GC_PMU_PERICLKCLR1_DTIMEHS1_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_PERICLKCLR1_DTIMEHS1_CLK_TIMER_OFFSET 0x70
-#define GC_PMU_PERICLKCLR1_DTIMELS0_CLK_LSB      0x2
-#define GC_PMU_PERICLKCLR1_DTIMELS0_CLK_MASK     0x4
-#define GC_PMU_PERICLKCLR1_DTIMELS0_CLK_SIZE     0x1
-#define GC_PMU_PERICLKCLR1_DTIMELS0_CLK_DEFAULT  0x0
-#define GC_PMU_PERICLKCLR1_DTIMELS0_CLK_OFFSET   0x70
-#define GC_PMU_PERICLKCLR1_DTIMEUS0_CLK_TIMER_LSB 0x3
-#define GC_PMU_PERICLKCLR1_DTIMEUS0_CLK_TIMER_MASK 0x8
-#define GC_PMU_PERICLKCLR1_DTIMEUS0_CLK_TIMER_SIZE 0x1
-#define GC_PMU_PERICLKCLR1_DTIMEUS0_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_PERICLKCLR1_DTIMEUS0_CLK_TIMER_OFFSET 0x70
-#define GC_PMU_PERICLKCLR1_DTRNG0_CLK_LSB        0x4
-#define GC_PMU_PERICLKCLR1_DTRNG0_CLK_MASK       0x10
-#define GC_PMU_PERICLKCLR1_DTRNG0_CLK_SIZE       0x1
-#define GC_PMU_PERICLKCLR1_DTRNG0_CLK_DEFAULT    0x1
-#define GC_PMU_PERICLKCLR1_DTRNG0_CLK_OFFSET     0x70
-#define GC_PMU_PERICLKCLR1_DUART0_CLK_TIMER_LSB  0x5
-#define GC_PMU_PERICLKCLR1_DUART0_CLK_TIMER_MASK 0x20
-#define GC_PMU_PERICLKCLR1_DUART0_CLK_TIMER_SIZE 0x1
-#define GC_PMU_PERICLKCLR1_DUART0_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_PERICLKCLR1_DUART0_CLK_TIMER_OFFSET 0x70
-#define GC_PMU_PERICLKCLR1_DUART1_CLK_TIMER_LSB  0x6
-#define GC_PMU_PERICLKCLR1_DUART1_CLK_TIMER_MASK 0x40
-#define GC_PMU_PERICLKCLR1_DUART1_CLK_TIMER_SIZE 0x1
-#define GC_PMU_PERICLKCLR1_DUART1_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_PERICLKCLR1_DUART1_CLK_TIMER_OFFSET 0x70
-#define GC_PMU_PERICLKCLR1_DUART2_CLK_TIMER_LSB  0x7
-#define GC_PMU_PERICLKCLR1_DUART2_CLK_TIMER_MASK 0x80
-#define GC_PMU_PERICLKCLR1_DUART2_CLK_TIMER_SIZE 0x1
-#define GC_PMU_PERICLKCLR1_DUART2_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_PERICLKCLR1_DUART2_CLK_TIMER_OFFSET 0x70
-#define GC_PMU_PERICLKCLR1_DUSB0_CLK_LSB         0x8
-#define GC_PMU_PERICLKCLR1_DUSB0_CLK_MASK        0x100
-#define GC_PMU_PERICLKCLR1_DUSB0_CLK_SIZE        0x1
-#define GC_PMU_PERICLKCLR1_DUSB0_CLK_DEFAULT     0x1
-#define GC_PMU_PERICLKCLR1_DUSB0_CLK_OFFSET      0x70
-#define GC_PMU_PERICLKCLR1_DUSB0_CLK_TIMER_HS_LSB 0x9
-#define GC_PMU_PERICLKCLR1_DUSB0_CLK_TIMER_HS_MASK 0x200
-#define GC_PMU_PERICLKCLR1_DUSB0_CLK_TIMER_HS_SIZE 0x1
-#define GC_PMU_PERICLKCLR1_DUSB0_CLK_TIMER_HS_DEFAULT 0x1
-#define GC_PMU_PERICLKCLR1_DUSB0_CLK_TIMER_HS_OFFSET 0x70
-#define GC_PMU_PERICLKCLR1_DVOLT0_CLK_LSB        0xa
-#define GC_PMU_PERICLKCLR1_DVOLT0_CLK_MASK       0x400
-#define GC_PMU_PERICLKCLR1_DVOLT0_CLK_SIZE       0x1
-#define GC_PMU_PERICLKCLR1_DVOLT0_CLK_DEFAULT    0x1
-#define GC_PMU_PERICLKCLR1_DVOLT0_CLK_OFFSET     0x70
-#define GC_PMU_PERICLKCLR1_DWATCHDOG0_CLK_LSB    0xb
-#define GC_PMU_PERICLKCLR1_DWATCHDOG0_CLK_MASK   0x800
-#define GC_PMU_PERICLKCLR1_DWATCHDOG0_CLK_SIZE   0x1
-#define GC_PMU_PERICLKCLR1_DWATCHDOG0_CLK_DEFAULT 0x1
-#define GC_PMU_PERICLKCLR1_DWATCHDOG0_CLK_OFFSET 0x70
-#define GC_PMU_PERICLKCLR1_DXO0_CLK_LSB          0xc
-#define GC_PMU_PERICLKCLR1_DXO0_CLK_MASK         0x1000
-#define GC_PMU_PERICLKCLR1_DXO0_CLK_SIZE         0x1
-#define GC_PMU_PERICLKCLR1_DXO0_CLK_DEFAULT      0x1
-#define GC_PMU_PERICLKCLR1_DXO0_CLK_OFFSET       0x70
-#define GC_PMU_PERICLKCLR1_DXO0_CLK_TIMER_LSB    0xd
-#define GC_PMU_PERICLKCLR1_DXO0_CLK_TIMER_MASK   0x2000
-#define GC_PMU_PERICLKCLR1_DXO0_CLK_TIMER_SIZE   0x1
-#define GC_PMU_PERICLKCLR1_DXO0_CLK_TIMER_DEFAULT 0x1
-#define GC_PMU_PERICLKCLR1_DXO0_CLK_TIMER_OFFSET 0x70
-#define GC_PMU_PERICLKCLR1_PERI_MASTER_MATRIX_CLK_LSB 0xe
-#define GC_PMU_PERICLKCLR1_PERI_MASTER_MATRIX_CLK_MASK 0x4000
-#define GC_PMU_PERICLKCLR1_PERI_MASTER_MATRIX_CLK_SIZE 0x1
-#define GC_PMU_PERICLKCLR1_PERI_MASTER_MATRIX_CLK_DEFAULT 0x1
-#define GC_PMU_PERICLKCLR1_PERI_MASTER_MATRIX_CLK_OFFSET 0x70
-#define GC_PMU_PERICLKCLR1_PERI_MATRIX_CLK_LSB   0xf
-#define GC_PMU_PERICLKCLR1_PERI_MATRIX_CLK_MASK  0x8000
-#define GC_PMU_PERICLKCLR1_PERI_MATRIX_CLK_SIZE  0x1
-#define GC_PMU_PERICLKCLR1_PERI_MATRIX_CLK_DEFAULT 0x1
-#define GC_PMU_PERICLKCLR1_PERI_MATRIX_CLK_OFFSET 0x70
-#define GC_PMU_CLK_RO_MASK0_DCAMO0_CLK_LSB       0x0
-#define GC_PMU_CLK_RO_MASK0_DCAMO0_CLK_MASK      0x1
-#define GC_PMU_CLK_RO_MASK0_DCAMO0_CLK_SIZE      0x1
-#define GC_PMU_CLK_RO_MASK0_DCAMO0_CLK_DEFAULT   0x1
-#define GC_PMU_CLK_RO_MASK0_DCAMO0_CLK_OFFSET    0x74
-#define GC_PMU_CLK_RO_MASK0_DCRYPTO0_CLK_LSB     0x1
-#define GC_PMU_CLK_RO_MASK0_DCRYPTO0_CLK_MASK    0x2
-#define GC_PMU_CLK_RO_MASK0_DCRYPTO0_CLK_SIZE    0x1
-#define GC_PMU_CLK_RO_MASK0_DCRYPTO0_CLK_DEFAULT 0x0
-#define GC_PMU_CLK_RO_MASK0_DCRYPTO0_CLK_OFFSET  0x74
-#define GC_PMU_CLK_RO_MASK0_DDMA0_CLK_LSB        0x2
-#define GC_PMU_CLK_RO_MASK0_DDMA0_CLK_MASK       0x4
-#define GC_PMU_CLK_RO_MASK0_DDMA0_CLK_SIZE       0x1
-#define GC_PMU_CLK_RO_MASK0_DDMA0_CLK_DEFAULT    0x0
-#define GC_PMU_CLK_RO_MASK0_DDMA0_CLK_OFFSET     0x74
-#define GC_PMU_CLK_RO_MASK0_DFLASH0_CLK_LSB      0x3
-#define GC_PMU_CLK_RO_MASK0_DFLASH0_CLK_MASK     0x8
-#define GC_PMU_CLK_RO_MASK0_DFLASH0_CLK_SIZE     0x1
-#define GC_PMU_CLK_RO_MASK0_DFLASH0_CLK_DEFAULT  0x0
-#define GC_PMU_CLK_RO_MASK0_DFLASH0_CLK_OFFSET   0x74
-#define GC_PMU_CLK_RO_MASK0_DFUSE0_CLK_LSB       0x4
-#define GC_PMU_CLK_RO_MASK0_DFUSE0_CLK_MASK      0x10
-#define GC_PMU_CLK_RO_MASK0_DFUSE0_CLK_SIZE      0x1
-#define GC_PMU_CLK_RO_MASK0_DFUSE0_CLK_DEFAULT   0x0
-#define GC_PMU_CLK_RO_MASK0_DFUSE0_CLK_OFFSET    0x74
-#define GC_PMU_CLK_RO_MASK0_DGLOBALSEC_CLK_LSB   0x5
-#define GC_PMU_CLK_RO_MASK0_DGLOBALSEC_CLK_MASK  0x20
-#define GC_PMU_CLK_RO_MASK0_DGLOBALSEC_CLK_SIZE  0x1
-#define GC_PMU_CLK_RO_MASK0_DGLOBALSEC_CLK_DEFAULT 0x1
-#define GC_PMU_CLK_RO_MASK0_DGLOBALSEC_CLK_OFFSET 0x74
-#define GC_PMU_CLK_RO_MASK0_DGLOBALSEC_CLK_TIMER_LSB 0x6
-#define GC_PMU_CLK_RO_MASK0_DGLOBALSEC_CLK_TIMER_MASK 0x40
-#define GC_PMU_CLK_RO_MASK0_DGLOBALSEC_CLK_TIMER_SIZE 0x1
-#define GC_PMU_CLK_RO_MASK0_DGLOBALSEC_CLK_TIMER_DEFAULT 0x1
-#define GC_PMU_CLK_RO_MASK0_DGLOBALSEC_CLK_TIMER_OFFSET 0x74
-#define GC_PMU_CLK_RO_MASK0_DGLOBALSEC_CLK_HS_LSB 0x7
-#define GC_PMU_CLK_RO_MASK0_DGLOBALSEC_CLK_HS_MASK 0x80
-#define GC_PMU_CLK_RO_MASK0_DGLOBALSEC_CLK_HS_SIZE 0x1
-#define GC_PMU_CLK_RO_MASK0_DGLOBALSEC_CLK_HS_DEFAULT 0x1
-#define GC_PMU_CLK_RO_MASK0_DGLOBALSEC_CLK_HS_OFFSET 0x74
-#define GC_PMU_CLK_RO_MASK0_DGPIO0_CLK_LSB       0x8
-#define GC_PMU_CLK_RO_MASK0_DGPIO0_CLK_MASK      0x100
-#define GC_PMU_CLK_RO_MASK0_DGPIO0_CLK_SIZE      0x1
-#define GC_PMU_CLK_RO_MASK0_DGPIO0_CLK_DEFAULT   0x0
-#define GC_PMU_CLK_RO_MASK0_DGPIO0_CLK_OFFSET    0x74
-#define GC_PMU_CLK_RO_MASK0_DGPIO1_CLK_LSB       0x9
-#define GC_PMU_CLK_RO_MASK0_DGPIO1_CLK_MASK      0x200
-#define GC_PMU_CLK_RO_MASK0_DGPIO1_CLK_SIZE      0x1
-#define GC_PMU_CLK_RO_MASK0_DGPIO1_CLK_DEFAULT   0x0
-#define GC_PMU_CLK_RO_MASK0_DGPIO1_CLK_OFFSET    0x74
-#define GC_PMU_CLK_RO_MASK0_DI2C0_CLK_TIMER_LSB  0xa
-#define GC_PMU_CLK_RO_MASK0_DI2C0_CLK_TIMER_MASK 0x400
-#define GC_PMU_CLK_RO_MASK0_DI2C0_CLK_TIMER_SIZE 0x1
-#define GC_PMU_CLK_RO_MASK0_DI2C0_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_CLK_RO_MASK0_DI2C0_CLK_TIMER_OFFSET 0x74
-#define GC_PMU_CLK_RO_MASK0_DI2C1_CLK_TIMER_LSB  0xb
-#define GC_PMU_CLK_RO_MASK0_DI2C1_CLK_TIMER_MASK 0x800
-#define GC_PMU_CLK_RO_MASK0_DI2C1_CLK_TIMER_SIZE 0x1
-#define GC_PMU_CLK_RO_MASK0_DI2C1_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_CLK_RO_MASK0_DI2C1_CLK_TIMER_OFFSET 0x74
-#define GC_PMU_CLK_RO_MASK0_DI2CS0_CLK_LSB       0xc
-#define GC_PMU_CLK_RO_MASK0_DI2CS0_CLK_MASK      0x1000
-#define GC_PMU_CLK_RO_MASK0_DI2CS0_CLK_SIZE      0x1
-#define GC_PMU_CLK_RO_MASK0_DI2CS0_CLK_DEFAULT   0x0
-#define GC_PMU_CLK_RO_MASK0_DI2CS0_CLK_OFFSET    0x74
-#define GC_PMU_CLK_RO_MASK0_DKEYMGR0_CLK_LSB     0xd
-#define GC_PMU_CLK_RO_MASK0_DKEYMGR0_CLK_MASK    0x2000
-#define GC_PMU_CLK_RO_MASK0_DKEYMGR0_CLK_SIZE    0x1
-#define GC_PMU_CLK_RO_MASK0_DKEYMGR0_CLK_DEFAULT 0x0
-#define GC_PMU_CLK_RO_MASK0_DKEYMGR0_CLK_OFFSET  0x74
-#define GC_PMU_CLK_RO_MASK0_DPERI_APB0_CLK_LSB   0xe
-#define GC_PMU_CLK_RO_MASK0_DPERI_APB0_CLK_MASK  0x4000
-#define GC_PMU_CLK_RO_MASK0_DPERI_APB0_CLK_SIZE  0x1
-#define GC_PMU_CLK_RO_MASK0_DPERI_APB0_CLK_DEFAULT 0x1
-#define GC_PMU_CLK_RO_MASK0_DPERI_APB0_CLK_OFFSET 0x74
-#define GC_PMU_CLK_RO_MASK0_DPERI_APB1_CLK_LSB   0xf
-#define GC_PMU_CLK_RO_MASK0_DPERI_APB1_CLK_MASK  0x8000
-#define GC_PMU_CLK_RO_MASK0_DPERI_APB1_CLK_SIZE  0x1
-#define GC_PMU_CLK_RO_MASK0_DPERI_APB1_CLK_DEFAULT 0x1
-#define GC_PMU_CLK_RO_MASK0_DPERI_APB1_CLK_OFFSET 0x74
-#define GC_PMU_CLK_RO_MASK0_DPERI_APB2_CLK_LSB   0x10
-#define GC_PMU_CLK_RO_MASK0_DPERI_APB2_CLK_MASK  0x10000
-#define GC_PMU_CLK_RO_MASK0_DPERI_APB2_CLK_SIZE  0x1
-#define GC_PMU_CLK_RO_MASK0_DPERI_APB2_CLK_DEFAULT 0x1
-#define GC_PMU_CLK_RO_MASK0_DPERI_APB2_CLK_OFFSET 0x74
-#define GC_PMU_CLK_RO_MASK0_DPERI_APB2_CLK_TIMER_LSB 0x11
-#define GC_PMU_CLK_RO_MASK0_DPERI_APB2_CLK_TIMER_MASK 0x20000
-#define GC_PMU_CLK_RO_MASK0_DPERI_APB2_CLK_TIMER_SIZE 0x1
-#define GC_PMU_CLK_RO_MASK0_DPERI_APB2_CLK_TIMER_DEFAULT 0x1
-#define GC_PMU_CLK_RO_MASK0_DPERI_APB2_CLK_TIMER_OFFSET 0x74
-#define GC_PMU_CLK_RO_MASK0_DPERI_APB3_CLK_LSB   0x12
-#define GC_PMU_CLK_RO_MASK0_DPERI_APB3_CLK_MASK  0x40000
-#define GC_PMU_CLK_RO_MASK0_DPERI_APB3_CLK_SIZE  0x1
-#define GC_PMU_CLK_RO_MASK0_DPERI_APB3_CLK_DEFAULT 0x1
-#define GC_PMU_CLK_RO_MASK0_DPERI_APB3_CLK_OFFSET 0x74
-#define GC_PMU_CLK_RO_MASK0_DPERI_APB3_CLK_HS_LSB 0x13
-#define GC_PMU_CLK_RO_MASK0_DPERI_APB3_CLK_HS_MASK 0x80000
-#define GC_PMU_CLK_RO_MASK0_DPERI_APB3_CLK_HS_SIZE 0x1
-#define GC_PMU_CLK_RO_MASK0_DPERI_APB3_CLK_HS_DEFAULT 0x1
-#define GC_PMU_CLK_RO_MASK0_DPERI_APB3_CLK_HS_OFFSET 0x74
-#define GC_PMU_CLK_RO_MASK0_DPINMUX_CLK_LSB      0x14
-#define GC_PMU_CLK_RO_MASK0_DPINMUX_CLK_MASK     0x100000
-#define GC_PMU_CLK_RO_MASK0_DPINMUX_CLK_SIZE     0x1
-#define GC_PMU_CLK_RO_MASK0_DPINMUX_CLK_DEFAULT  0x0
-#define GC_PMU_CLK_RO_MASK0_DPINMUX_CLK_OFFSET   0x74
-#define GC_PMU_CLK_RO_MASK0_DPMU_CLK_LSB         0x15
-#define GC_PMU_CLK_RO_MASK0_DPMU_CLK_MASK        0x200000
-#define GC_PMU_CLK_RO_MASK0_DPMU_CLK_SIZE        0x1
-#define GC_PMU_CLK_RO_MASK0_DPMU_CLK_DEFAULT     0x0
-#define GC_PMU_CLK_RO_MASK0_DPMU_CLK_OFFSET      0x74
-#define GC_PMU_CLK_RO_MASK0_DRBOX0_CLK_LSB       0x16
-#define GC_PMU_CLK_RO_MASK0_DRBOX0_CLK_MASK      0x400000
-#define GC_PMU_CLK_RO_MASK0_DRBOX0_CLK_SIZE      0x1
-#define GC_PMU_CLK_RO_MASK0_DRBOX0_CLK_DEFAULT   0x0
-#define GC_PMU_CLK_RO_MASK0_DRBOX0_CLK_OFFSET    0x74
-#define GC_PMU_CLK_RO_MASK0_DRDD0_CLK_LSB        0x17
-#define GC_PMU_CLK_RO_MASK0_DRDD0_CLK_MASK       0x800000
-#define GC_PMU_CLK_RO_MASK0_DRDD0_CLK_SIZE       0x1
-#define GC_PMU_CLK_RO_MASK0_DRDD0_CLK_DEFAULT    0x0
-#define GC_PMU_CLK_RO_MASK0_DRDD0_CLK_OFFSET     0x74
-#define GC_PMU_CLK_RO_MASK0_DRTC0_CLK_LSB        0x18
-#define GC_PMU_CLK_RO_MASK0_DRTC0_CLK_MASK       0x1000000
-#define GC_PMU_CLK_RO_MASK0_DRTC0_CLK_SIZE       0x1
-#define GC_PMU_CLK_RO_MASK0_DRTC0_CLK_DEFAULT    0x0
-#define GC_PMU_CLK_RO_MASK0_DRTC0_CLK_OFFSET     0x74
-#define GC_PMU_CLK_RO_MASK0_DRTC0_CLK_TIMER_LSB  0x19
-#define GC_PMU_CLK_RO_MASK0_DRTC0_CLK_TIMER_MASK 0x2000000
-#define GC_PMU_CLK_RO_MASK0_DRTC0_CLK_TIMER_SIZE 0x1
-#define GC_PMU_CLK_RO_MASK0_DRTC0_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_CLK_RO_MASK0_DRTC0_CLK_TIMER_OFFSET 0x74
-#define GC_PMU_CLK_RO_MASK0_DSPI0_CLK_HS_LSB     0x1a
-#define GC_PMU_CLK_RO_MASK0_DSPI0_CLK_HS_MASK    0x4000000
-#define GC_PMU_CLK_RO_MASK0_DSPI0_CLK_HS_SIZE    0x1
-#define GC_PMU_CLK_RO_MASK0_DSPI0_CLK_HS_DEFAULT 0x0
-#define GC_PMU_CLK_RO_MASK0_DSPI0_CLK_HS_OFFSET  0x74
-#define GC_PMU_CLK_RO_MASK0_DSPI1_CLK_HS_LSB     0x1b
-#define GC_PMU_CLK_RO_MASK0_DSPI1_CLK_HS_MASK    0x8000000
-#define GC_PMU_CLK_RO_MASK0_DSPI1_CLK_HS_SIZE    0x1
-#define GC_PMU_CLK_RO_MASK0_DSPI1_CLK_HS_DEFAULT 0x0
-#define GC_PMU_CLK_RO_MASK0_DSPI1_CLK_HS_OFFSET  0x74
-#define GC_PMU_CLK_RO_MASK0_DSPS0_CLK_LSB        0x1c
-#define GC_PMU_CLK_RO_MASK0_DSPS0_CLK_MASK       0x10000000
-#define GC_PMU_CLK_RO_MASK0_DSPS0_CLK_SIZE       0x1
-#define GC_PMU_CLK_RO_MASK0_DSPS0_CLK_DEFAULT    0x0
-#define GC_PMU_CLK_RO_MASK0_DSPS0_CLK_OFFSET     0x74
-#define GC_PMU_CLK_RO_MASK0_DSPS0_CLK_TIMER_HS_LSB 0x1d
-#define GC_PMU_CLK_RO_MASK0_DSPS0_CLK_TIMER_HS_MASK 0x20000000
-#define GC_PMU_CLK_RO_MASK0_DSPS0_CLK_TIMER_HS_SIZE 0x1
-#define GC_PMU_CLK_RO_MASK0_DSPS0_CLK_TIMER_HS_DEFAULT 0x0
-#define GC_PMU_CLK_RO_MASK0_DSPS0_CLK_TIMER_HS_OFFSET 0x74
-#define GC_PMU_CLK_RO_MASK0_DSWDP0_CLK_LSB       0x1e
-#define GC_PMU_CLK_RO_MASK0_DSWDP0_CLK_MASK      0x40000000
-#define GC_PMU_CLK_RO_MASK0_DSWDP0_CLK_SIZE      0x1
-#define GC_PMU_CLK_RO_MASK0_DSWDP0_CLK_DEFAULT   0x0
-#define GC_PMU_CLK_RO_MASK0_DSWDP0_CLK_OFFSET    0x74
-#define GC_PMU_CLK_RO_MASK0_DTEMP0_CLK_LSB       0x1f
-#define GC_PMU_CLK_RO_MASK0_DTEMP0_CLK_MASK      0x80000000
-#define GC_PMU_CLK_RO_MASK0_DTEMP0_CLK_SIZE      0x1
-#define GC_PMU_CLK_RO_MASK0_DTEMP0_CLK_DEFAULT   0x1
-#define GC_PMU_CLK_RO_MASK0_DTEMP0_CLK_OFFSET    0x74
-#define GC_PMU_CLK_RO_MASK1_DTIMEHS0_CLK_TIMER_LSB 0x0
-#define GC_PMU_CLK_RO_MASK1_DTIMEHS0_CLK_TIMER_MASK 0x1
-#define GC_PMU_CLK_RO_MASK1_DTIMEHS0_CLK_TIMER_SIZE 0x1
-#define GC_PMU_CLK_RO_MASK1_DTIMEHS0_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_CLK_RO_MASK1_DTIMEHS0_CLK_TIMER_OFFSET 0x78
-#define GC_PMU_CLK_RO_MASK1_DTIMEHS1_CLK_TIMER_LSB 0x1
-#define GC_PMU_CLK_RO_MASK1_DTIMEHS1_CLK_TIMER_MASK 0x2
-#define GC_PMU_CLK_RO_MASK1_DTIMEHS1_CLK_TIMER_SIZE 0x1
-#define GC_PMU_CLK_RO_MASK1_DTIMEHS1_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_CLK_RO_MASK1_DTIMEHS1_CLK_TIMER_OFFSET 0x78
-#define GC_PMU_CLK_RO_MASK1_DTIMELS0_CLK_LSB     0x2
-#define GC_PMU_CLK_RO_MASK1_DTIMELS0_CLK_MASK    0x4
-#define GC_PMU_CLK_RO_MASK1_DTIMELS0_CLK_SIZE    0x1
-#define GC_PMU_CLK_RO_MASK1_DTIMELS0_CLK_DEFAULT 0x0
-#define GC_PMU_CLK_RO_MASK1_DTIMELS0_CLK_OFFSET  0x78
-#define GC_PMU_CLK_RO_MASK1_DTIMEUS0_CLK_TIMER_LSB 0x3
-#define GC_PMU_CLK_RO_MASK1_DTIMEUS0_CLK_TIMER_MASK 0x8
-#define GC_PMU_CLK_RO_MASK1_DTIMEUS0_CLK_TIMER_SIZE 0x1
-#define GC_PMU_CLK_RO_MASK1_DTIMEUS0_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_CLK_RO_MASK1_DTIMEUS0_CLK_TIMER_OFFSET 0x78
-#define GC_PMU_CLK_RO_MASK1_DTRNG0_CLK_LSB       0x4
-#define GC_PMU_CLK_RO_MASK1_DTRNG0_CLK_MASK      0x10
-#define GC_PMU_CLK_RO_MASK1_DTRNG0_CLK_SIZE      0x1
-#define GC_PMU_CLK_RO_MASK1_DTRNG0_CLK_DEFAULT   0x0
-#define GC_PMU_CLK_RO_MASK1_DTRNG0_CLK_OFFSET    0x78
-#define GC_PMU_CLK_RO_MASK1_DUART0_CLK_TIMER_LSB 0x5
-#define GC_PMU_CLK_RO_MASK1_DUART0_CLK_TIMER_MASK 0x20
-#define GC_PMU_CLK_RO_MASK1_DUART0_CLK_TIMER_SIZE 0x1
-#define GC_PMU_CLK_RO_MASK1_DUART0_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_CLK_RO_MASK1_DUART0_CLK_TIMER_OFFSET 0x78
-#define GC_PMU_CLK_RO_MASK1_DUART1_CLK_TIMER_LSB 0x6
-#define GC_PMU_CLK_RO_MASK1_DUART1_CLK_TIMER_MASK 0x40
-#define GC_PMU_CLK_RO_MASK1_DUART1_CLK_TIMER_SIZE 0x1
-#define GC_PMU_CLK_RO_MASK1_DUART1_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_CLK_RO_MASK1_DUART1_CLK_TIMER_OFFSET 0x78
-#define GC_PMU_CLK_RO_MASK1_DUART2_CLK_TIMER_LSB 0x7
-#define GC_PMU_CLK_RO_MASK1_DUART2_CLK_TIMER_MASK 0x80
-#define GC_PMU_CLK_RO_MASK1_DUART2_CLK_TIMER_SIZE 0x1
-#define GC_PMU_CLK_RO_MASK1_DUART2_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_CLK_RO_MASK1_DUART2_CLK_TIMER_OFFSET 0x78
-#define GC_PMU_CLK_RO_MASK1_DUSB0_CLK_LSB        0x8
-#define GC_PMU_CLK_RO_MASK1_DUSB0_CLK_MASK       0x100
-#define GC_PMU_CLK_RO_MASK1_DUSB0_CLK_SIZE       0x1
-#define GC_PMU_CLK_RO_MASK1_DUSB0_CLK_DEFAULT    0x0
-#define GC_PMU_CLK_RO_MASK1_DUSB0_CLK_OFFSET     0x78
-#define GC_PMU_CLK_RO_MASK1_DUSB0_CLK_TIMER_HS_LSB 0x9
-#define GC_PMU_CLK_RO_MASK1_DUSB0_CLK_TIMER_HS_MASK 0x200
-#define GC_PMU_CLK_RO_MASK1_DUSB0_CLK_TIMER_HS_SIZE 0x1
-#define GC_PMU_CLK_RO_MASK1_DUSB0_CLK_TIMER_HS_DEFAULT 0x0
-#define GC_PMU_CLK_RO_MASK1_DUSB0_CLK_TIMER_HS_OFFSET 0x78
-#define GC_PMU_CLK_RO_MASK1_DVOLT0_CLK_LSB       0xa
-#define GC_PMU_CLK_RO_MASK1_DVOLT0_CLK_MASK      0x400
-#define GC_PMU_CLK_RO_MASK1_DVOLT0_CLK_SIZE      0x1
-#define GC_PMU_CLK_RO_MASK1_DVOLT0_CLK_DEFAULT   0x1
-#define GC_PMU_CLK_RO_MASK1_DVOLT0_CLK_OFFSET    0x78
-#define GC_PMU_CLK_RO_MASK1_DWATCHDOG0_CLK_LSB   0xb
-#define GC_PMU_CLK_RO_MASK1_DWATCHDOG0_CLK_MASK  0x800
-#define GC_PMU_CLK_RO_MASK1_DWATCHDOG0_CLK_SIZE  0x1
-#define GC_PMU_CLK_RO_MASK1_DWATCHDOG0_CLK_DEFAULT 0x1
-#define GC_PMU_CLK_RO_MASK1_DWATCHDOG0_CLK_OFFSET 0x78
-#define GC_PMU_CLK_RO_MASK1_DXO0_CLK_LSB         0xc
-#define GC_PMU_CLK_RO_MASK1_DXO0_CLK_MASK        0x1000
-#define GC_PMU_CLK_RO_MASK1_DXO0_CLK_SIZE        0x1
-#define GC_PMU_CLK_RO_MASK1_DXO0_CLK_DEFAULT     0x0
-#define GC_PMU_CLK_RO_MASK1_DXO0_CLK_OFFSET      0x78
-#define GC_PMU_CLK_RO_MASK1_DXO0_CLK_TIMER_LSB   0xd
-#define GC_PMU_CLK_RO_MASK1_DXO0_CLK_TIMER_MASK  0x2000
-#define GC_PMU_CLK_RO_MASK1_DXO0_CLK_TIMER_SIZE  0x1
-#define GC_PMU_CLK_RO_MASK1_DXO0_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_CLK_RO_MASK1_DXO0_CLK_TIMER_OFFSET 0x78
-#define GC_PMU_CLK_RO_MASK1_PERI_MASTER_MATRIX_CLK_LSB 0xe
-#define GC_PMU_CLK_RO_MASK1_PERI_MASTER_MATRIX_CLK_MASK 0x4000
-#define GC_PMU_CLK_RO_MASK1_PERI_MASTER_MATRIX_CLK_SIZE 0x1
-#define GC_PMU_CLK_RO_MASK1_PERI_MASTER_MATRIX_CLK_DEFAULT 0x1
-#define GC_PMU_CLK_RO_MASK1_PERI_MASTER_MATRIX_CLK_OFFSET 0x78
-#define GC_PMU_CLK_RO_MASK1_PERI_MATRIX_CLK_LSB  0xf
-#define GC_PMU_CLK_RO_MASK1_PERI_MATRIX_CLK_MASK 0x8000
-#define GC_PMU_CLK_RO_MASK1_PERI_MATRIX_CLK_SIZE 0x1
-#define GC_PMU_CLK_RO_MASK1_PERI_MATRIX_CLK_DEFAULT 0x1
-#define GC_PMU_CLK_RO_MASK1_PERI_MATRIX_CLK_OFFSET 0x78
-#define GC_PMU_PERIGATEONSLEEPSET0_DCAMO0_CLK_LSB 0x0
-#define GC_PMU_PERIGATEONSLEEPSET0_DCAMO0_CLK_MASK 0x1
-#define GC_PMU_PERIGATEONSLEEPSET0_DCAMO0_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPSET0_DCAMO0_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPSET0_DCAMO0_CLK_OFFSET 0x7c
-#define GC_PMU_PERIGATEONSLEEPSET0_DCRYPTO0_CLK_LSB 0x1
-#define GC_PMU_PERIGATEONSLEEPSET0_DCRYPTO0_CLK_MASK 0x2
-#define GC_PMU_PERIGATEONSLEEPSET0_DCRYPTO0_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPSET0_DCRYPTO0_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPSET0_DCRYPTO0_CLK_OFFSET 0x7c
-#define GC_PMU_PERIGATEONSLEEPSET0_DDMA0_CLK_LSB 0x2
-#define GC_PMU_PERIGATEONSLEEPSET0_DDMA0_CLK_MASK 0x4
-#define GC_PMU_PERIGATEONSLEEPSET0_DDMA0_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPSET0_DDMA0_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPSET0_DDMA0_CLK_OFFSET 0x7c
-#define GC_PMU_PERIGATEONSLEEPSET0_DFLASH0_CLK_LSB 0x3
-#define GC_PMU_PERIGATEONSLEEPSET0_DFLASH0_CLK_MASK 0x8
-#define GC_PMU_PERIGATEONSLEEPSET0_DFLASH0_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPSET0_DFLASH0_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPSET0_DFLASH0_CLK_OFFSET 0x7c
-#define GC_PMU_PERIGATEONSLEEPSET0_DFUSE0_CLK_LSB 0x4
-#define GC_PMU_PERIGATEONSLEEPSET0_DFUSE0_CLK_MASK 0x10
-#define GC_PMU_PERIGATEONSLEEPSET0_DFUSE0_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPSET0_DFUSE0_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPSET0_DFUSE0_CLK_OFFSET 0x7c
-#define GC_PMU_PERIGATEONSLEEPSET0_DGLOBALSEC_CLK_LSB 0x5
-#define GC_PMU_PERIGATEONSLEEPSET0_DGLOBALSEC_CLK_MASK 0x20
-#define GC_PMU_PERIGATEONSLEEPSET0_DGLOBALSEC_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPSET0_DGLOBALSEC_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPSET0_DGLOBALSEC_CLK_OFFSET 0x7c
-#define GC_PMU_PERIGATEONSLEEPSET0_DGLOBALSEC_CLK_TIMER_LSB 0x6
-#define GC_PMU_PERIGATEONSLEEPSET0_DGLOBALSEC_CLK_TIMER_MASK 0x40
-#define GC_PMU_PERIGATEONSLEEPSET0_DGLOBALSEC_CLK_TIMER_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPSET0_DGLOBALSEC_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPSET0_DGLOBALSEC_CLK_TIMER_OFFSET 0x7c
-#define GC_PMU_PERIGATEONSLEEPSET0_DGLOBALSEC_CLK_HS_LSB 0x7
-#define GC_PMU_PERIGATEONSLEEPSET0_DGLOBALSEC_CLK_HS_MASK 0x80
-#define GC_PMU_PERIGATEONSLEEPSET0_DGLOBALSEC_CLK_HS_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPSET0_DGLOBALSEC_CLK_HS_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPSET0_DGLOBALSEC_CLK_HS_OFFSET 0x7c
-#define GC_PMU_PERIGATEONSLEEPSET0_DGPIO0_CLK_LSB 0x8
-#define GC_PMU_PERIGATEONSLEEPSET0_DGPIO0_CLK_MASK 0x100
-#define GC_PMU_PERIGATEONSLEEPSET0_DGPIO0_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPSET0_DGPIO0_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPSET0_DGPIO0_CLK_OFFSET 0x7c
-#define GC_PMU_PERIGATEONSLEEPSET0_DGPIO1_CLK_LSB 0x9
-#define GC_PMU_PERIGATEONSLEEPSET0_DGPIO1_CLK_MASK 0x200
-#define GC_PMU_PERIGATEONSLEEPSET0_DGPIO1_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPSET0_DGPIO1_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPSET0_DGPIO1_CLK_OFFSET 0x7c
-#define GC_PMU_PERIGATEONSLEEPSET0_DI2C0_CLK_TIMER_LSB 0xa
-#define GC_PMU_PERIGATEONSLEEPSET0_DI2C0_CLK_TIMER_MASK 0x400
-#define GC_PMU_PERIGATEONSLEEPSET0_DI2C0_CLK_TIMER_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPSET0_DI2C0_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPSET0_DI2C0_CLK_TIMER_OFFSET 0x7c
-#define GC_PMU_PERIGATEONSLEEPSET0_DI2C1_CLK_TIMER_LSB 0xb
-#define GC_PMU_PERIGATEONSLEEPSET0_DI2C1_CLK_TIMER_MASK 0x800
-#define GC_PMU_PERIGATEONSLEEPSET0_DI2C1_CLK_TIMER_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPSET0_DI2C1_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPSET0_DI2C1_CLK_TIMER_OFFSET 0x7c
-#define GC_PMU_PERIGATEONSLEEPSET0_DI2CS0_CLK_LSB 0xc
-#define GC_PMU_PERIGATEONSLEEPSET0_DI2CS0_CLK_MASK 0x1000
-#define GC_PMU_PERIGATEONSLEEPSET0_DI2CS0_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPSET0_DI2CS0_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPSET0_DI2CS0_CLK_OFFSET 0x7c
-#define GC_PMU_PERIGATEONSLEEPSET0_DKEYMGR0_CLK_LSB 0xd
-#define GC_PMU_PERIGATEONSLEEPSET0_DKEYMGR0_CLK_MASK 0x2000
-#define GC_PMU_PERIGATEONSLEEPSET0_DKEYMGR0_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPSET0_DKEYMGR0_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPSET0_DKEYMGR0_CLK_OFFSET 0x7c
-#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB0_CLK_LSB 0xe
-#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB0_CLK_MASK 0x4000
-#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB0_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB0_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB0_CLK_OFFSET 0x7c
-#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB1_CLK_LSB 0xf
-#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB1_CLK_MASK 0x8000
-#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB1_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB1_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB1_CLK_OFFSET 0x7c
-#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB2_CLK_LSB 0x10
-#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB2_CLK_MASK 0x10000
-#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB2_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB2_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB2_CLK_OFFSET 0x7c
-#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB2_CLK_TIMER_LSB 0x11
-#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB2_CLK_TIMER_MASK 0x20000
-#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB2_CLK_TIMER_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB2_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB2_CLK_TIMER_OFFSET 0x7c
-#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB3_CLK_LSB 0x12
-#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB3_CLK_MASK 0x40000
-#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB3_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB3_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB3_CLK_OFFSET 0x7c
-#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB3_CLK_HS_LSB 0x13
-#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB3_CLK_HS_MASK 0x80000
-#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB3_CLK_HS_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB3_CLK_HS_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPSET0_DPERI_APB3_CLK_HS_OFFSET 0x7c
-#define GC_PMU_PERIGATEONSLEEPSET0_DPINMUX_CLK_LSB 0x14
-#define GC_PMU_PERIGATEONSLEEPSET0_DPINMUX_CLK_MASK 0x100000
-#define GC_PMU_PERIGATEONSLEEPSET0_DPINMUX_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPSET0_DPINMUX_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPSET0_DPINMUX_CLK_OFFSET 0x7c
-#define GC_PMU_PERIGATEONSLEEPSET0_DPMU_CLK_LSB  0x15
-#define GC_PMU_PERIGATEONSLEEPSET0_DPMU_CLK_MASK 0x200000
-#define GC_PMU_PERIGATEONSLEEPSET0_DPMU_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPSET0_DPMU_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPSET0_DPMU_CLK_OFFSET 0x7c
-#define GC_PMU_PERIGATEONSLEEPSET0_DRBOX0_CLK_LSB 0x16
-#define GC_PMU_PERIGATEONSLEEPSET0_DRBOX0_CLK_MASK 0x400000
-#define GC_PMU_PERIGATEONSLEEPSET0_DRBOX0_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPSET0_DRBOX0_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPSET0_DRBOX0_CLK_OFFSET 0x7c
-#define GC_PMU_PERIGATEONSLEEPSET0_DRDD0_CLK_LSB 0x17
-#define GC_PMU_PERIGATEONSLEEPSET0_DRDD0_CLK_MASK 0x800000
-#define GC_PMU_PERIGATEONSLEEPSET0_DRDD0_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPSET0_DRDD0_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPSET0_DRDD0_CLK_OFFSET 0x7c
-#define GC_PMU_PERIGATEONSLEEPSET0_DRTC0_CLK_LSB 0x18
-#define GC_PMU_PERIGATEONSLEEPSET0_DRTC0_CLK_MASK 0x1000000
-#define GC_PMU_PERIGATEONSLEEPSET0_DRTC0_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPSET0_DRTC0_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPSET0_DRTC0_CLK_OFFSET 0x7c
-#define GC_PMU_PERIGATEONSLEEPSET0_DRTC0_CLK_TIMER_LSB 0x19
-#define GC_PMU_PERIGATEONSLEEPSET0_DRTC0_CLK_TIMER_MASK 0x2000000
-#define GC_PMU_PERIGATEONSLEEPSET0_DRTC0_CLK_TIMER_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPSET0_DRTC0_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPSET0_DRTC0_CLK_TIMER_OFFSET 0x7c
-#define GC_PMU_PERIGATEONSLEEPSET0_DSPI0_CLK_HS_LSB 0x1a
-#define GC_PMU_PERIGATEONSLEEPSET0_DSPI0_CLK_HS_MASK 0x4000000
-#define GC_PMU_PERIGATEONSLEEPSET0_DSPI0_CLK_HS_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPSET0_DSPI0_CLK_HS_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPSET0_DSPI0_CLK_HS_OFFSET 0x7c
-#define GC_PMU_PERIGATEONSLEEPSET0_DSPI1_CLK_HS_LSB 0x1b
-#define GC_PMU_PERIGATEONSLEEPSET0_DSPI1_CLK_HS_MASK 0x8000000
-#define GC_PMU_PERIGATEONSLEEPSET0_DSPI1_CLK_HS_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPSET0_DSPI1_CLK_HS_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPSET0_DSPI1_CLK_HS_OFFSET 0x7c
-#define GC_PMU_PERIGATEONSLEEPSET0_DSPS0_CLK_LSB 0x1c
-#define GC_PMU_PERIGATEONSLEEPSET0_DSPS0_CLK_MASK 0x10000000
-#define GC_PMU_PERIGATEONSLEEPSET0_DSPS0_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPSET0_DSPS0_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPSET0_DSPS0_CLK_OFFSET 0x7c
-#define GC_PMU_PERIGATEONSLEEPSET0_DSPS0_CLK_TIMER_HS_LSB 0x1d
-#define GC_PMU_PERIGATEONSLEEPSET0_DSPS0_CLK_TIMER_HS_MASK 0x20000000
-#define GC_PMU_PERIGATEONSLEEPSET0_DSPS0_CLK_TIMER_HS_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPSET0_DSPS0_CLK_TIMER_HS_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPSET0_DSPS0_CLK_TIMER_HS_OFFSET 0x7c
-#define GC_PMU_PERIGATEONSLEEPSET0_DSWDP0_CLK_LSB 0x1e
-#define GC_PMU_PERIGATEONSLEEPSET0_DSWDP0_CLK_MASK 0x40000000
-#define GC_PMU_PERIGATEONSLEEPSET0_DSWDP0_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPSET0_DSWDP0_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPSET0_DSWDP0_CLK_OFFSET 0x7c
-#define GC_PMU_PERIGATEONSLEEPSET0_DTEMP0_CLK_LSB 0x1f
-#define GC_PMU_PERIGATEONSLEEPSET0_DTEMP0_CLK_MASK 0x80000000
-#define GC_PMU_PERIGATEONSLEEPSET0_DTEMP0_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPSET0_DTEMP0_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPSET0_DTEMP0_CLK_OFFSET 0x7c
-#define GC_PMU_PERIGATEONSLEEPCLR0_DCAMO0_CLK_LSB 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR0_DCAMO0_CLK_MASK 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR0_DCAMO0_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR0_DCAMO0_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR0_DCAMO0_CLK_OFFSET 0x80
-#define GC_PMU_PERIGATEONSLEEPCLR0_DCRYPTO0_CLK_LSB 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR0_DCRYPTO0_CLK_MASK 0x2
-#define GC_PMU_PERIGATEONSLEEPCLR0_DCRYPTO0_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR0_DCRYPTO0_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR0_DCRYPTO0_CLK_OFFSET 0x80
-#define GC_PMU_PERIGATEONSLEEPCLR0_DDMA0_CLK_LSB 0x2
-#define GC_PMU_PERIGATEONSLEEPCLR0_DDMA0_CLK_MASK 0x4
-#define GC_PMU_PERIGATEONSLEEPCLR0_DDMA0_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR0_DDMA0_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR0_DDMA0_CLK_OFFSET 0x80
-#define GC_PMU_PERIGATEONSLEEPCLR0_DFLASH0_CLK_LSB 0x3
-#define GC_PMU_PERIGATEONSLEEPCLR0_DFLASH0_CLK_MASK 0x8
-#define GC_PMU_PERIGATEONSLEEPCLR0_DFLASH0_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR0_DFLASH0_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR0_DFLASH0_CLK_OFFSET 0x80
-#define GC_PMU_PERIGATEONSLEEPCLR0_DFUSE0_CLK_LSB 0x4
-#define GC_PMU_PERIGATEONSLEEPCLR0_DFUSE0_CLK_MASK 0x10
-#define GC_PMU_PERIGATEONSLEEPCLR0_DFUSE0_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR0_DFUSE0_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR0_DFUSE0_CLK_OFFSET 0x80
-#define GC_PMU_PERIGATEONSLEEPCLR0_DGLOBALSEC_CLK_LSB 0x5
-#define GC_PMU_PERIGATEONSLEEPCLR0_DGLOBALSEC_CLK_MASK 0x20
-#define GC_PMU_PERIGATEONSLEEPCLR0_DGLOBALSEC_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR0_DGLOBALSEC_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR0_DGLOBALSEC_CLK_OFFSET 0x80
-#define GC_PMU_PERIGATEONSLEEPCLR0_DGLOBALSEC_CLK_TIMER_LSB 0x6
-#define GC_PMU_PERIGATEONSLEEPCLR0_DGLOBALSEC_CLK_TIMER_MASK 0x40
-#define GC_PMU_PERIGATEONSLEEPCLR0_DGLOBALSEC_CLK_TIMER_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR0_DGLOBALSEC_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR0_DGLOBALSEC_CLK_TIMER_OFFSET 0x80
-#define GC_PMU_PERIGATEONSLEEPCLR0_DGLOBALSEC_CLK_HS_LSB 0x7
-#define GC_PMU_PERIGATEONSLEEPCLR0_DGLOBALSEC_CLK_HS_MASK 0x80
-#define GC_PMU_PERIGATEONSLEEPCLR0_DGLOBALSEC_CLK_HS_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR0_DGLOBALSEC_CLK_HS_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR0_DGLOBALSEC_CLK_HS_OFFSET 0x80
-#define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO0_CLK_LSB 0x8
-#define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO0_CLK_MASK 0x100
-#define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO0_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO0_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO0_CLK_OFFSET 0x80
-#define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO1_CLK_LSB 0x9
-#define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO1_CLK_MASK 0x200
-#define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO1_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO1_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR0_DGPIO1_CLK_OFFSET 0x80
-#define GC_PMU_PERIGATEONSLEEPCLR0_DI2C0_CLK_TIMER_LSB 0xa
-#define GC_PMU_PERIGATEONSLEEPCLR0_DI2C0_CLK_TIMER_MASK 0x400
-#define GC_PMU_PERIGATEONSLEEPCLR0_DI2C0_CLK_TIMER_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR0_DI2C0_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR0_DI2C0_CLK_TIMER_OFFSET 0x80
-#define GC_PMU_PERIGATEONSLEEPCLR0_DI2C1_CLK_TIMER_LSB 0xb
-#define GC_PMU_PERIGATEONSLEEPCLR0_DI2C1_CLK_TIMER_MASK 0x800
-#define GC_PMU_PERIGATEONSLEEPCLR0_DI2C1_CLK_TIMER_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR0_DI2C1_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR0_DI2C1_CLK_TIMER_OFFSET 0x80
-#define GC_PMU_PERIGATEONSLEEPCLR0_DI2CS0_CLK_LSB 0xc
-#define GC_PMU_PERIGATEONSLEEPCLR0_DI2CS0_CLK_MASK 0x1000
-#define GC_PMU_PERIGATEONSLEEPCLR0_DI2CS0_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR0_DI2CS0_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR0_DI2CS0_CLK_OFFSET 0x80
-#define GC_PMU_PERIGATEONSLEEPCLR0_DKEYMGR0_CLK_LSB 0xd
-#define GC_PMU_PERIGATEONSLEEPCLR0_DKEYMGR0_CLK_MASK 0x2000
-#define GC_PMU_PERIGATEONSLEEPCLR0_DKEYMGR0_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR0_DKEYMGR0_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR0_DKEYMGR0_CLK_OFFSET 0x80
-#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB0_CLK_LSB 0xe
-#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB0_CLK_MASK 0x4000
-#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB0_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB0_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB0_CLK_OFFSET 0x80
-#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB1_CLK_LSB 0xf
-#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB1_CLK_MASK 0x8000
-#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB1_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB1_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB1_CLK_OFFSET 0x80
-#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB2_CLK_LSB 0x10
-#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB2_CLK_MASK 0x10000
-#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB2_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB2_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB2_CLK_OFFSET 0x80
-#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB2_CLK_TIMER_LSB 0x11
-#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB2_CLK_TIMER_MASK 0x20000
-#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB2_CLK_TIMER_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB2_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB2_CLK_TIMER_OFFSET 0x80
-#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB3_CLK_LSB 0x12
-#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB3_CLK_MASK 0x40000
-#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB3_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB3_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB3_CLK_OFFSET 0x80
-#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB3_CLK_HS_LSB 0x13
-#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB3_CLK_HS_MASK 0x80000
-#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB3_CLK_HS_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB3_CLK_HS_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR0_DPERI_APB3_CLK_HS_OFFSET 0x80
-#define GC_PMU_PERIGATEONSLEEPCLR0_DPINMUX_CLK_LSB 0x14
-#define GC_PMU_PERIGATEONSLEEPCLR0_DPINMUX_CLK_MASK 0x100000
-#define GC_PMU_PERIGATEONSLEEPCLR0_DPINMUX_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR0_DPINMUX_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR0_DPINMUX_CLK_OFFSET 0x80
-#define GC_PMU_PERIGATEONSLEEPCLR0_DPMU_CLK_LSB  0x15
-#define GC_PMU_PERIGATEONSLEEPCLR0_DPMU_CLK_MASK 0x200000
-#define GC_PMU_PERIGATEONSLEEPCLR0_DPMU_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR0_DPMU_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR0_DPMU_CLK_OFFSET 0x80
-#define GC_PMU_PERIGATEONSLEEPCLR0_DRBOX0_CLK_LSB 0x16
-#define GC_PMU_PERIGATEONSLEEPCLR0_DRBOX0_CLK_MASK 0x400000
-#define GC_PMU_PERIGATEONSLEEPCLR0_DRBOX0_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR0_DRBOX0_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR0_DRBOX0_CLK_OFFSET 0x80
-#define GC_PMU_PERIGATEONSLEEPCLR0_DRDD0_CLK_LSB 0x17
-#define GC_PMU_PERIGATEONSLEEPCLR0_DRDD0_CLK_MASK 0x800000
-#define GC_PMU_PERIGATEONSLEEPCLR0_DRDD0_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR0_DRDD0_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR0_DRDD0_CLK_OFFSET 0x80
-#define GC_PMU_PERIGATEONSLEEPCLR0_DRTC0_CLK_LSB 0x18
-#define GC_PMU_PERIGATEONSLEEPCLR0_DRTC0_CLK_MASK 0x1000000
-#define GC_PMU_PERIGATEONSLEEPCLR0_DRTC0_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR0_DRTC0_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR0_DRTC0_CLK_OFFSET 0x80
-#define GC_PMU_PERIGATEONSLEEPCLR0_DRTC0_CLK_TIMER_LSB 0x19
-#define GC_PMU_PERIGATEONSLEEPCLR0_DRTC0_CLK_TIMER_MASK 0x2000000
-#define GC_PMU_PERIGATEONSLEEPCLR0_DRTC0_CLK_TIMER_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR0_DRTC0_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR0_DRTC0_CLK_TIMER_OFFSET 0x80
-#define GC_PMU_PERIGATEONSLEEPCLR0_DSPI0_CLK_HS_LSB 0x1a
-#define GC_PMU_PERIGATEONSLEEPCLR0_DSPI0_CLK_HS_MASK 0x4000000
-#define GC_PMU_PERIGATEONSLEEPCLR0_DSPI0_CLK_HS_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR0_DSPI0_CLK_HS_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR0_DSPI0_CLK_HS_OFFSET 0x80
-#define GC_PMU_PERIGATEONSLEEPCLR0_DSPI1_CLK_HS_LSB 0x1b
-#define GC_PMU_PERIGATEONSLEEPCLR0_DSPI1_CLK_HS_MASK 0x8000000
-#define GC_PMU_PERIGATEONSLEEPCLR0_DSPI1_CLK_HS_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR0_DSPI1_CLK_HS_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR0_DSPI1_CLK_HS_OFFSET 0x80
-#define GC_PMU_PERIGATEONSLEEPCLR0_DSPS0_CLK_LSB 0x1c
-#define GC_PMU_PERIGATEONSLEEPCLR0_DSPS0_CLK_MASK 0x10000000
-#define GC_PMU_PERIGATEONSLEEPCLR0_DSPS0_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR0_DSPS0_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR0_DSPS0_CLK_OFFSET 0x80
-#define GC_PMU_PERIGATEONSLEEPCLR0_DSPS0_CLK_TIMER_HS_LSB 0x1d
-#define GC_PMU_PERIGATEONSLEEPCLR0_DSPS0_CLK_TIMER_HS_MASK 0x20000000
-#define GC_PMU_PERIGATEONSLEEPCLR0_DSPS0_CLK_TIMER_HS_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR0_DSPS0_CLK_TIMER_HS_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR0_DSPS0_CLK_TIMER_HS_OFFSET 0x80
-#define GC_PMU_PERIGATEONSLEEPCLR0_DSWDP0_CLK_LSB 0x1e
-#define GC_PMU_PERIGATEONSLEEPCLR0_DSWDP0_CLK_MASK 0x40000000
-#define GC_PMU_PERIGATEONSLEEPCLR0_DSWDP0_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR0_DSWDP0_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR0_DSWDP0_CLK_OFFSET 0x80
-#define GC_PMU_PERIGATEONSLEEPCLR0_DTEMP0_CLK_LSB 0x1f
-#define GC_PMU_PERIGATEONSLEEPCLR0_DTEMP0_CLK_MASK 0x80000000
-#define GC_PMU_PERIGATEONSLEEPCLR0_DTEMP0_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR0_DTEMP0_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR0_DTEMP0_CLK_OFFSET 0x80
-#define GC_PMU_PERIGATEONSLEEPSET1_DTIMEHS0_CLK_TIMER_LSB 0x0
-#define GC_PMU_PERIGATEONSLEEPSET1_DTIMEHS0_CLK_TIMER_MASK 0x1
-#define GC_PMU_PERIGATEONSLEEPSET1_DTIMEHS0_CLK_TIMER_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPSET1_DTIMEHS0_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPSET1_DTIMEHS0_CLK_TIMER_OFFSET 0x84
-#define GC_PMU_PERIGATEONSLEEPSET1_DTIMEHS1_CLK_TIMER_LSB 0x1
-#define GC_PMU_PERIGATEONSLEEPSET1_DTIMEHS1_CLK_TIMER_MASK 0x2
-#define GC_PMU_PERIGATEONSLEEPSET1_DTIMEHS1_CLK_TIMER_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPSET1_DTIMEHS1_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPSET1_DTIMEHS1_CLK_TIMER_OFFSET 0x84
-#define GC_PMU_PERIGATEONSLEEPSET1_DTIMELS0_CLK_LSB 0x2
-#define GC_PMU_PERIGATEONSLEEPSET1_DTIMELS0_CLK_MASK 0x4
-#define GC_PMU_PERIGATEONSLEEPSET1_DTIMELS0_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPSET1_DTIMELS0_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPSET1_DTIMELS0_CLK_OFFSET 0x84
-#define GC_PMU_PERIGATEONSLEEPSET1_DTIMEUS0_CLK_TIMER_LSB 0x3
-#define GC_PMU_PERIGATEONSLEEPSET1_DTIMEUS0_CLK_TIMER_MASK 0x8
-#define GC_PMU_PERIGATEONSLEEPSET1_DTIMEUS0_CLK_TIMER_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPSET1_DTIMEUS0_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPSET1_DTIMEUS0_CLK_TIMER_OFFSET 0x84
-#define GC_PMU_PERIGATEONSLEEPSET1_DTRNG0_CLK_LSB 0x4
-#define GC_PMU_PERIGATEONSLEEPSET1_DTRNG0_CLK_MASK 0x10
-#define GC_PMU_PERIGATEONSLEEPSET1_DTRNG0_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPSET1_DTRNG0_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPSET1_DTRNG0_CLK_OFFSET 0x84
-#define GC_PMU_PERIGATEONSLEEPSET1_DUART0_CLK_TIMER_LSB 0x5
-#define GC_PMU_PERIGATEONSLEEPSET1_DUART0_CLK_TIMER_MASK 0x20
-#define GC_PMU_PERIGATEONSLEEPSET1_DUART0_CLK_TIMER_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPSET1_DUART0_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPSET1_DUART0_CLK_TIMER_OFFSET 0x84
-#define GC_PMU_PERIGATEONSLEEPSET1_DUART1_CLK_TIMER_LSB 0x6
-#define GC_PMU_PERIGATEONSLEEPSET1_DUART1_CLK_TIMER_MASK 0x40
-#define GC_PMU_PERIGATEONSLEEPSET1_DUART1_CLK_TIMER_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPSET1_DUART1_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPSET1_DUART1_CLK_TIMER_OFFSET 0x84
-#define GC_PMU_PERIGATEONSLEEPSET1_DUART2_CLK_TIMER_LSB 0x7
-#define GC_PMU_PERIGATEONSLEEPSET1_DUART2_CLK_TIMER_MASK 0x80
-#define GC_PMU_PERIGATEONSLEEPSET1_DUART2_CLK_TIMER_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPSET1_DUART2_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPSET1_DUART2_CLK_TIMER_OFFSET 0x84
-#define GC_PMU_PERIGATEONSLEEPSET1_DUSB0_CLK_LSB 0x8
-#define GC_PMU_PERIGATEONSLEEPSET1_DUSB0_CLK_MASK 0x100
-#define GC_PMU_PERIGATEONSLEEPSET1_DUSB0_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPSET1_DUSB0_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPSET1_DUSB0_CLK_OFFSET 0x84
-#define GC_PMU_PERIGATEONSLEEPSET1_DUSB0_CLK_TIMER_HS_LSB 0x9
-#define GC_PMU_PERIGATEONSLEEPSET1_DUSB0_CLK_TIMER_HS_MASK 0x200
-#define GC_PMU_PERIGATEONSLEEPSET1_DUSB0_CLK_TIMER_HS_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPSET1_DUSB0_CLK_TIMER_HS_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPSET1_DUSB0_CLK_TIMER_HS_OFFSET 0x84
-#define GC_PMU_PERIGATEONSLEEPSET1_DVOLT0_CLK_LSB 0xa
-#define GC_PMU_PERIGATEONSLEEPSET1_DVOLT0_CLK_MASK 0x400
-#define GC_PMU_PERIGATEONSLEEPSET1_DVOLT0_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPSET1_DVOLT0_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPSET1_DVOLT0_CLK_OFFSET 0x84
-#define GC_PMU_PERIGATEONSLEEPSET1_DWATCHDOG0_CLK_LSB 0xb
-#define GC_PMU_PERIGATEONSLEEPSET1_DWATCHDOG0_CLK_MASK 0x800
-#define GC_PMU_PERIGATEONSLEEPSET1_DWATCHDOG0_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPSET1_DWATCHDOG0_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPSET1_DWATCHDOG0_CLK_OFFSET 0x84
-#define GC_PMU_PERIGATEONSLEEPSET1_DXO0_CLK_LSB  0xc
-#define GC_PMU_PERIGATEONSLEEPSET1_DXO0_CLK_MASK 0x1000
-#define GC_PMU_PERIGATEONSLEEPSET1_DXO0_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPSET1_DXO0_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPSET1_DXO0_CLK_OFFSET 0x84
-#define GC_PMU_PERIGATEONSLEEPSET1_DXO0_CLK_TIMER_LSB 0xd
-#define GC_PMU_PERIGATEONSLEEPSET1_DXO0_CLK_TIMER_MASK 0x2000
-#define GC_PMU_PERIGATEONSLEEPSET1_DXO0_CLK_TIMER_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPSET1_DXO0_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPSET1_DXO0_CLK_TIMER_OFFSET 0x84
-#define GC_PMU_PERIGATEONSLEEPSET1_PERI_MASTER_MATRIX_CLK_LSB 0xe
-#define GC_PMU_PERIGATEONSLEEPSET1_PERI_MASTER_MATRIX_CLK_MASK 0x4000
-#define GC_PMU_PERIGATEONSLEEPSET1_PERI_MASTER_MATRIX_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPSET1_PERI_MASTER_MATRIX_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPSET1_PERI_MASTER_MATRIX_CLK_OFFSET 0x84
-#define GC_PMU_PERIGATEONSLEEPSET1_PERI_MATRIX_CLK_LSB 0xf
-#define GC_PMU_PERIGATEONSLEEPSET1_PERI_MATRIX_CLK_MASK 0x8000
-#define GC_PMU_PERIGATEONSLEEPSET1_PERI_MATRIX_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPSET1_PERI_MATRIX_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPSET1_PERI_MATRIX_CLK_OFFSET 0x84
-#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMEHS0_CLK_TIMER_LSB 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMEHS0_CLK_TIMER_MASK 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMEHS0_CLK_TIMER_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMEHS0_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMEHS0_CLK_TIMER_OFFSET 0x88
-#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMEHS1_CLK_TIMER_LSB 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMEHS1_CLK_TIMER_MASK 0x2
-#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMEHS1_CLK_TIMER_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMEHS1_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMEHS1_CLK_TIMER_OFFSET 0x88
-#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMELS0_CLK_LSB 0x2
-#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMELS0_CLK_MASK 0x4
-#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMELS0_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMELS0_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMELS0_CLK_OFFSET 0x88
-#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMEUS0_CLK_TIMER_LSB 0x3
-#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMEUS0_CLK_TIMER_MASK 0x8
-#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMEUS0_CLK_TIMER_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMEUS0_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR1_DTIMEUS0_CLK_TIMER_OFFSET 0x88
-#define GC_PMU_PERIGATEONSLEEPCLR1_DTRNG0_CLK_LSB 0x4
-#define GC_PMU_PERIGATEONSLEEPCLR1_DTRNG0_CLK_MASK 0x10
-#define GC_PMU_PERIGATEONSLEEPCLR1_DTRNG0_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR1_DTRNG0_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR1_DTRNG0_CLK_OFFSET 0x88
-#define GC_PMU_PERIGATEONSLEEPCLR1_DUART0_CLK_TIMER_LSB 0x5
-#define GC_PMU_PERIGATEONSLEEPCLR1_DUART0_CLK_TIMER_MASK 0x20
-#define GC_PMU_PERIGATEONSLEEPCLR1_DUART0_CLK_TIMER_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR1_DUART0_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR1_DUART0_CLK_TIMER_OFFSET 0x88
-#define GC_PMU_PERIGATEONSLEEPCLR1_DUART1_CLK_TIMER_LSB 0x6
-#define GC_PMU_PERIGATEONSLEEPCLR1_DUART1_CLK_TIMER_MASK 0x40
-#define GC_PMU_PERIGATEONSLEEPCLR1_DUART1_CLK_TIMER_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR1_DUART1_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR1_DUART1_CLK_TIMER_OFFSET 0x88
-#define GC_PMU_PERIGATEONSLEEPCLR1_DUART2_CLK_TIMER_LSB 0x7
-#define GC_PMU_PERIGATEONSLEEPCLR1_DUART2_CLK_TIMER_MASK 0x80
-#define GC_PMU_PERIGATEONSLEEPCLR1_DUART2_CLK_TIMER_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR1_DUART2_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR1_DUART2_CLK_TIMER_OFFSET 0x88
-#define GC_PMU_PERIGATEONSLEEPCLR1_DUSB0_CLK_LSB 0x8
-#define GC_PMU_PERIGATEONSLEEPCLR1_DUSB0_CLK_MASK 0x100
-#define GC_PMU_PERIGATEONSLEEPCLR1_DUSB0_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR1_DUSB0_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR1_DUSB0_CLK_OFFSET 0x88
-#define GC_PMU_PERIGATEONSLEEPCLR1_DUSB0_CLK_TIMER_HS_LSB 0x9
-#define GC_PMU_PERIGATEONSLEEPCLR1_DUSB0_CLK_TIMER_HS_MASK 0x200
-#define GC_PMU_PERIGATEONSLEEPCLR1_DUSB0_CLK_TIMER_HS_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR1_DUSB0_CLK_TIMER_HS_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR1_DUSB0_CLK_TIMER_HS_OFFSET 0x88
-#define GC_PMU_PERIGATEONSLEEPCLR1_DVOLT0_CLK_LSB 0xa
-#define GC_PMU_PERIGATEONSLEEPCLR1_DVOLT0_CLK_MASK 0x400
-#define GC_PMU_PERIGATEONSLEEPCLR1_DVOLT0_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR1_DVOLT0_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR1_DVOLT0_CLK_OFFSET 0x88
-#define GC_PMU_PERIGATEONSLEEPCLR1_DWATCHDOG0_CLK_LSB 0xb
-#define GC_PMU_PERIGATEONSLEEPCLR1_DWATCHDOG0_CLK_MASK 0x800
-#define GC_PMU_PERIGATEONSLEEPCLR1_DWATCHDOG0_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR1_DWATCHDOG0_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR1_DWATCHDOG0_CLK_OFFSET 0x88
-#define GC_PMU_PERIGATEONSLEEPCLR1_DXO0_CLK_LSB  0xc
-#define GC_PMU_PERIGATEONSLEEPCLR1_DXO0_CLK_MASK 0x1000
-#define GC_PMU_PERIGATEONSLEEPCLR1_DXO0_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR1_DXO0_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR1_DXO0_CLK_OFFSET 0x88
-#define GC_PMU_PERIGATEONSLEEPCLR1_DXO0_CLK_TIMER_LSB 0xd
-#define GC_PMU_PERIGATEONSLEEPCLR1_DXO0_CLK_TIMER_MASK 0x2000
-#define GC_PMU_PERIGATEONSLEEPCLR1_DXO0_CLK_TIMER_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR1_DXO0_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR1_DXO0_CLK_TIMER_OFFSET 0x88
-#define GC_PMU_PERIGATEONSLEEPCLR1_PERI_MASTER_MATRIX_CLK_LSB 0xe
-#define GC_PMU_PERIGATEONSLEEPCLR1_PERI_MASTER_MATRIX_CLK_MASK 0x4000
-#define GC_PMU_PERIGATEONSLEEPCLR1_PERI_MASTER_MATRIX_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR1_PERI_MASTER_MATRIX_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR1_PERI_MASTER_MATRIX_CLK_OFFSET 0x88
-#define GC_PMU_PERIGATEONSLEEPCLR1_PERI_MATRIX_CLK_LSB 0xf
-#define GC_PMU_PERIGATEONSLEEPCLR1_PERI_MATRIX_CLK_MASK 0x8000
-#define GC_PMU_PERIGATEONSLEEPCLR1_PERI_MATRIX_CLK_SIZE 0x1
-#define GC_PMU_PERIGATEONSLEEPCLR1_PERI_MATRIX_CLK_DEFAULT 0x0
-#define GC_PMU_PERIGATEONSLEEPCLR1_PERI_MATRIX_CLK_OFFSET 0x88
-#define GC_PMU_CLK0_HCLKGATEEN_LSB               0x0
-#define GC_PMU_CLK0_HCLKGATEEN_MASK              0x1
-#define GC_PMU_CLK0_HCLKGATEEN_SIZE              0x1
-#define GC_PMU_CLK0_HCLKGATEEN_DEFAULT           0x1
-#define GC_PMU_CLK0_HCLKGATEEN_OFFSET            0x8c
-#define GC_PMU_CLK0_DAPCLKGATEEN_LSB             0x1
-#define GC_PMU_CLK0_DAPCLKGATEEN_MASK            0x2
-#define GC_PMU_CLK0_DAPCLKGATEEN_SIZE            0x1
-#define GC_PMU_CLK0_DAPCLKGATEEN_DEFAULT         0x1
-#define GC_PMU_CLK0_DAPCLKGATEEN_OFFSET          0x8c
-#define GC_PMU_CLK0_TPIUGATEEN_LSB               0x2
-#define GC_PMU_CLK0_TPIUGATEEN_MASK              0x4
-#define GC_PMU_CLK0_TPIUGATEEN_SIZE              0x1
-#define GC_PMU_CLK0_TPIUGATEEN_DEFAULT           0x1
-#define GC_PMU_CLK0_TPIUGATEEN_OFFSET            0x8c
-#define GC_PMU_CLK0_FCLKEN_LSB                   0x3
-#define GC_PMU_CLK0_FCLKEN_MASK                  0x8
-#define GC_PMU_CLK0_FCLKEN_SIZE                  0x1
-#define GC_PMU_CLK0_FCLKEN_DEFAULT               0x1
-#define GC_PMU_CLK0_FCLKEN_OFFSET                0x8c
-#define GC_PMU_CLK0_DAPCLKEN_LSB                 0x4
-#define GC_PMU_CLK0_DAPCLKEN_MASK                0x10
-#define GC_PMU_CLK0_DAPCLKEN_SIZE                0x1
-#define GC_PMU_CLK0_DAPCLKEN_DEFAULT             0x1
-#define GC_PMU_CLK0_DAPCLKEN_OFFSET              0x8c
-#define GC_PMU_CLK0_TPIUCLKEN_LSB                0x5
-#define GC_PMU_CLK0_TPIUCLKEN_MASK               0x20
-#define GC_PMU_CLK0_TPIUCLKEN_SIZE               0x1
-#define GC_PMU_CLK0_TPIUCLKEN_DEFAULT            0x0
-#define GC_PMU_CLK0_TPIUCLKEN_OFFSET             0x8c
-#define GC_PMU_CLK0_TRACECLKEN_LSB               0x6
-#define GC_PMU_CLK0_TRACECLKEN_MASK              0x40
-#define GC_PMU_CLK0_TRACECLKEN_SIZE              0x1
-#define GC_PMU_CLK0_TRACECLKEN_DEFAULT           0x0
-#define GC_PMU_CLK0_TRACECLKEN_OFFSET            0x8c
-#define GC_PMU_RST0_DCAMO0_AON_LSB               0x0
-#define GC_PMU_RST0_DCAMO0_AON_MASK              0x1
-#define GC_PMU_RST0_DCAMO0_AON_SIZE              0x1
-#define GC_PMU_RST0_DCAMO0_AON_DEFAULT           0x0
-#define GC_PMU_RST0_DCAMO0_AON_OFFSET            0x94
-#define GC_PMU_RST0_DCRYPTO0_LSB                 0x1
-#define GC_PMU_RST0_DCRYPTO0_MASK                0x2
-#define GC_PMU_RST0_DCRYPTO0_SIZE                0x1
-#define GC_PMU_RST0_DCRYPTO0_DEFAULT             0x0
-#define GC_PMU_RST0_DCRYPTO0_OFFSET              0x94
-#define GC_PMU_RST0_DDMA0_LSB                    0x2
-#define GC_PMU_RST0_DDMA0_MASK                   0x4
-#define GC_PMU_RST0_DDMA0_SIZE                   0x1
-#define GC_PMU_RST0_DDMA0_DEFAULT                0x0
-#define GC_PMU_RST0_DDMA0_OFFSET                 0x94
-#define GC_PMU_RST0_DFLASH0_LSB                  0x3
-#define GC_PMU_RST0_DFLASH0_MASK                 0x8
-#define GC_PMU_RST0_DFLASH0_SIZE                 0x1
-#define GC_PMU_RST0_DFLASH0_DEFAULT              0x0
-#define GC_PMU_RST0_DFLASH0_OFFSET               0x94
-#define GC_PMU_RST0_DFUSE0_LSB                   0x4
-#define GC_PMU_RST0_DFUSE0_MASK                  0x10
-#define GC_PMU_RST0_DFUSE0_SIZE                  0x1
-#define GC_PMU_RST0_DFUSE0_DEFAULT               0x0
-#define GC_PMU_RST0_DFUSE0_OFFSET                0x94
-#define GC_PMU_RST0_DGLOBALSEC_LSB               0x5
-#define GC_PMU_RST0_DGLOBALSEC_MASK              0x20
-#define GC_PMU_RST0_DGLOBALSEC_SIZE              0x1
-#define GC_PMU_RST0_DGLOBALSEC_DEFAULT           0x0
-#define GC_PMU_RST0_DGLOBALSEC_OFFSET            0x94
-#define GC_PMU_RST0_DGLOBALSEC_CLK_TIMER_LSB     0x6
-#define GC_PMU_RST0_DGLOBALSEC_CLK_TIMER_MASK    0x40
-#define GC_PMU_RST0_DGLOBALSEC_CLK_TIMER_SIZE    0x1
-#define GC_PMU_RST0_DGLOBALSEC_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_RST0_DGLOBALSEC_CLK_TIMER_OFFSET  0x94
-#define GC_PMU_RST0_DGLOBALSEC_CLK_HS_LSB        0x7
-#define GC_PMU_RST0_DGLOBALSEC_CLK_HS_MASK       0x80
-#define GC_PMU_RST0_DGLOBALSEC_CLK_HS_SIZE       0x1
-#define GC_PMU_RST0_DGLOBALSEC_CLK_HS_DEFAULT    0x0
-#define GC_PMU_RST0_DGLOBALSEC_CLK_HS_OFFSET     0x94
-#define GC_PMU_RST0_DGPIO0_LSB                   0x8
-#define GC_PMU_RST0_DGPIO0_MASK                  0x100
-#define GC_PMU_RST0_DGPIO0_SIZE                  0x1
-#define GC_PMU_RST0_DGPIO0_DEFAULT               0x0
-#define GC_PMU_RST0_DGPIO0_OFFSET                0x94
-#define GC_PMU_RST0_DGPIO1_LSB                   0x9
-#define GC_PMU_RST0_DGPIO1_MASK                  0x200
-#define GC_PMU_RST0_DGPIO1_SIZE                  0x1
-#define GC_PMU_RST0_DGPIO1_DEFAULT               0x0
-#define GC_PMU_RST0_DGPIO1_OFFSET                0x94
-#define GC_PMU_RST0_DI2C0_CLK_TIMER_LSB          0xa
-#define GC_PMU_RST0_DI2C0_CLK_TIMER_MASK         0x400
-#define GC_PMU_RST0_DI2C0_CLK_TIMER_SIZE         0x1
-#define GC_PMU_RST0_DI2C0_CLK_TIMER_DEFAULT      0x0
-#define GC_PMU_RST0_DI2C0_CLK_TIMER_OFFSET       0x94
-#define GC_PMU_RST0_DI2C1_CLK_TIMER_LSB          0xb
-#define GC_PMU_RST0_DI2C1_CLK_TIMER_MASK         0x800
-#define GC_PMU_RST0_DI2C1_CLK_TIMER_SIZE         0x1
-#define GC_PMU_RST0_DI2C1_CLK_TIMER_DEFAULT      0x0
-#define GC_PMU_RST0_DI2C1_CLK_TIMER_OFFSET       0x94
-#define GC_PMU_RST0_DI2CS0_LSB                   0xc
-#define GC_PMU_RST0_DI2CS0_MASK                  0x1000
-#define GC_PMU_RST0_DI2CS0_SIZE                  0x1
-#define GC_PMU_RST0_DI2CS0_DEFAULT               0x0
-#define GC_PMU_RST0_DI2CS0_OFFSET                0x94
-#define GC_PMU_RST0_DKEYMGR0_LSB                 0xd
-#define GC_PMU_RST0_DKEYMGR0_MASK                0x2000
-#define GC_PMU_RST0_DKEYMGR0_SIZE                0x1
-#define GC_PMU_RST0_DKEYMGR0_DEFAULT             0x0
-#define GC_PMU_RST0_DKEYMGR0_OFFSET              0x94
-#define GC_PMU_RST0_DPERI_APB0_LSB               0xe
-#define GC_PMU_RST0_DPERI_APB0_MASK              0x4000
-#define GC_PMU_RST0_DPERI_APB0_SIZE              0x1
-#define GC_PMU_RST0_DPERI_APB0_DEFAULT           0x0
-#define GC_PMU_RST0_DPERI_APB0_OFFSET            0x94
-#define GC_PMU_RST0_DPERI_APB1_LSB               0xf
-#define GC_PMU_RST0_DPERI_APB1_MASK              0x8000
-#define GC_PMU_RST0_DPERI_APB1_SIZE              0x1
-#define GC_PMU_RST0_DPERI_APB1_DEFAULT           0x0
-#define GC_PMU_RST0_DPERI_APB1_OFFSET            0x94
-#define GC_PMU_RST0_DPERI_APB2_LSB               0x10
-#define GC_PMU_RST0_DPERI_APB2_MASK              0x10000
-#define GC_PMU_RST0_DPERI_APB2_SIZE              0x1
-#define GC_PMU_RST0_DPERI_APB2_DEFAULT           0x0
-#define GC_PMU_RST0_DPERI_APB2_OFFSET            0x94
-#define GC_PMU_RST0_DPERI_APB2_CLK_TIMER_LSB     0x11
-#define GC_PMU_RST0_DPERI_APB2_CLK_TIMER_MASK    0x20000
-#define GC_PMU_RST0_DPERI_APB2_CLK_TIMER_SIZE    0x1
-#define GC_PMU_RST0_DPERI_APB2_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_RST0_DPERI_APB2_CLK_TIMER_OFFSET  0x94
-#define GC_PMU_RST0_DPERI_APB3_LSB               0x12
-#define GC_PMU_RST0_DPERI_APB3_MASK              0x40000
-#define GC_PMU_RST0_DPERI_APB3_SIZE              0x1
-#define GC_PMU_RST0_DPERI_APB3_DEFAULT           0x0
-#define GC_PMU_RST0_DPERI_APB3_OFFSET            0x94
-#define GC_PMU_RST0_DPERI_APB3_CLK_HS_LSB        0x13
-#define GC_PMU_RST0_DPERI_APB3_CLK_HS_MASK       0x80000
-#define GC_PMU_RST0_DPERI_APB3_CLK_HS_SIZE       0x1
-#define GC_PMU_RST0_DPERI_APB3_CLK_HS_DEFAULT    0x0
-#define GC_PMU_RST0_DPERI_APB3_CLK_HS_OFFSET     0x94
-#define GC_PMU_RST0_DPINMUX_AON_LSB              0x14
-#define GC_PMU_RST0_DPINMUX_AON_MASK             0x100000
-#define GC_PMU_RST0_DPINMUX_AON_SIZE             0x1
-#define GC_PMU_RST0_DPINMUX_AON_DEFAULT          0x0
-#define GC_PMU_RST0_DPINMUX_AON_OFFSET           0x94
-#define GC_PMU_RST0_DPMU_AON_LSB                 0x15
-#define GC_PMU_RST0_DPMU_AON_MASK                0x200000
-#define GC_PMU_RST0_DPMU_AON_SIZE                0x1
-#define GC_PMU_RST0_DPMU_AON_DEFAULT             0x0
-#define GC_PMU_RST0_DPMU_AON_OFFSET              0x94
-#define GC_PMU_RST0_DRBOX0_AON_LSB               0x16
-#define GC_PMU_RST0_DRBOX0_AON_MASK              0x400000
-#define GC_PMU_RST0_DRBOX0_AON_SIZE              0x1
-#define GC_PMU_RST0_DRBOX0_AON_DEFAULT           0x0
-#define GC_PMU_RST0_DRBOX0_AON_OFFSET            0x94
-#define GC_PMU_RST0_DRDD0_AON_LSB                0x17
-#define GC_PMU_RST0_DRDD0_AON_MASK               0x800000
-#define GC_PMU_RST0_DRDD0_AON_SIZE               0x1
-#define GC_PMU_RST0_DRDD0_AON_DEFAULT            0x0
-#define GC_PMU_RST0_DRDD0_AON_OFFSET             0x94
-#define GC_PMU_RST0_DRTC0_AON_LSB                0x18
-#define GC_PMU_RST0_DRTC0_AON_MASK               0x1000000
-#define GC_PMU_RST0_DRTC0_AON_SIZE               0x1
-#define GC_PMU_RST0_DRTC0_AON_DEFAULT            0x0
-#define GC_PMU_RST0_DRTC0_AON_OFFSET             0x94
-#define GC_PMU_RST0_DRTC0_CLK_TIMER_AON_LSB      0x19
-#define GC_PMU_RST0_DRTC0_CLK_TIMER_AON_MASK     0x2000000
-#define GC_PMU_RST0_DRTC0_CLK_TIMER_AON_SIZE     0x1
-#define GC_PMU_RST0_DRTC0_CLK_TIMER_AON_DEFAULT  0x0
-#define GC_PMU_RST0_DRTC0_CLK_TIMER_AON_OFFSET   0x94
-#define GC_PMU_RST0_DSPI0_CLK_HS_LSB             0x1a
-#define GC_PMU_RST0_DSPI0_CLK_HS_MASK            0x4000000
-#define GC_PMU_RST0_DSPI0_CLK_HS_SIZE            0x1
-#define GC_PMU_RST0_DSPI0_CLK_HS_DEFAULT         0x0
-#define GC_PMU_RST0_DSPI0_CLK_HS_OFFSET          0x94
-#define GC_PMU_RST0_DSPI1_CLK_HS_LSB             0x1b
-#define GC_PMU_RST0_DSPI1_CLK_HS_MASK            0x8000000
-#define GC_PMU_RST0_DSPI1_CLK_HS_SIZE            0x1
-#define GC_PMU_RST0_DSPI1_CLK_HS_DEFAULT         0x0
-#define GC_PMU_RST0_DSPI1_CLK_HS_OFFSET          0x94
-#define GC_PMU_RST0_DSPS0_LSB                    0x1c
-#define GC_PMU_RST0_DSPS0_MASK                   0x10000000
-#define GC_PMU_RST0_DSPS0_SIZE                   0x1
-#define GC_PMU_RST0_DSPS0_DEFAULT                0x0
-#define GC_PMU_RST0_DSPS0_OFFSET                 0x94
-#define GC_PMU_RST0_DSPS0_CLK_TIMER_HS_LSB       0x1d
-#define GC_PMU_RST0_DSPS0_CLK_TIMER_HS_MASK      0x20000000
-#define GC_PMU_RST0_DSPS0_CLK_TIMER_HS_SIZE      0x1
-#define GC_PMU_RST0_DSPS0_CLK_TIMER_HS_DEFAULT   0x0
-#define GC_PMU_RST0_DSPS0_CLK_TIMER_HS_OFFSET    0x94
-#define GC_PMU_RST0_DSWDP0_LSB                   0x1e
-#define GC_PMU_RST0_DSWDP0_MASK                  0x40000000
-#define GC_PMU_RST0_DSWDP0_SIZE                  0x1
-#define GC_PMU_RST0_DSWDP0_DEFAULT               0x0
-#define GC_PMU_RST0_DSWDP0_OFFSET                0x94
-#define GC_PMU_RST0_DTEMP0_LSB                   0x1f
-#define GC_PMU_RST0_DTEMP0_MASK                  0x80000000
-#define GC_PMU_RST0_DTEMP0_SIZE                  0x1
-#define GC_PMU_RST0_DTEMP0_DEFAULT               0x0
-#define GC_PMU_RST0_DTEMP0_OFFSET                0x94
-#define GC_PMU_RST1_DTIMEHS0_CLK_TIMER_LSB       0x0
-#define GC_PMU_RST1_DTIMEHS0_CLK_TIMER_MASK      0x1
-#define GC_PMU_RST1_DTIMEHS0_CLK_TIMER_SIZE      0x1
-#define GC_PMU_RST1_DTIMEHS0_CLK_TIMER_DEFAULT   0x0
-#define GC_PMU_RST1_DTIMEHS0_CLK_TIMER_OFFSET    0x9c
-#define GC_PMU_RST1_DTIMEHS1_CLK_TIMER_LSB       0x1
-#define GC_PMU_RST1_DTIMEHS1_CLK_TIMER_MASK      0x2
-#define GC_PMU_RST1_DTIMEHS1_CLK_TIMER_SIZE      0x1
-#define GC_PMU_RST1_DTIMEHS1_CLK_TIMER_DEFAULT   0x0
-#define GC_PMU_RST1_DTIMEHS1_CLK_TIMER_OFFSET    0x9c
-#define GC_PMU_RST1_DTIMELS0_AON_LSB             0x2
-#define GC_PMU_RST1_DTIMELS0_AON_MASK            0x4
-#define GC_PMU_RST1_DTIMELS0_AON_SIZE            0x1
-#define GC_PMU_RST1_DTIMELS0_AON_DEFAULT         0x0
-#define GC_PMU_RST1_DTIMELS0_AON_OFFSET          0x9c
-#define GC_PMU_RST1_DTIMEUS0_CLK_TIMER_LSB       0x3
-#define GC_PMU_RST1_DTIMEUS0_CLK_TIMER_MASK      0x8
-#define GC_PMU_RST1_DTIMEUS0_CLK_TIMER_SIZE      0x1
-#define GC_PMU_RST1_DTIMEUS0_CLK_TIMER_DEFAULT   0x0
-#define GC_PMU_RST1_DTIMEUS0_CLK_TIMER_OFFSET    0x9c
-#define GC_PMU_RST1_DTRNG0_LSB                   0x4
-#define GC_PMU_RST1_DTRNG0_MASK                  0x10
-#define GC_PMU_RST1_DTRNG0_SIZE                  0x1
-#define GC_PMU_RST1_DTRNG0_DEFAULT               0x0
-#define GC_PMU_RST1_DTRNG0_OFFSET                0x9c
-#define GC_PMU_RST1_DUART0_CLK_TIMER_LSB         0x5
-#define GC_PMU_RST1_DUART0_CLK_TIMER_MASK        0x20
-#define GC_PMU_RST1_DUART0_CLK_TIMER_SIZE        0x1
-#define GC_PMU_RST1_DUART0_CLK_TIMER_DEFAULT     0x0
-#define GC_PMU_RST1_DUART0_CLK_TIMER_OFFSET      0x9c
-#define GC_PMU_RST1_DUART1_CLK_TIMER_LSB         0x6
-#define GC_PMU_RST1_DUART1_CLK_TIMER_MASK        0x40
-#define GC_PMU_RST1_DUART1_CLK_TIMER_SIZE        0x1
-#define GC_PMU_RST1_DUART1_CLK_TIMER_DEFAULT     0x0
-#define GC_PMU_RST1_DUART1_CLK_TIMER_OFFSET      0x9c
-#define GC_PMU_RST1_DUART2_CLK_TIMER_LSB         0x7
-#define GC_PMU_RST1_DUART2_CLK_TIMER_MASK        0x80
-#define GC_PMU_RST1_DUART2_CLK_TIMER_SIZE        0x1
-#define GC_PMU_RST1_DUART2_CLK_TIMER_DEFAULT     0x0
-#define GC_PMU_RST1_DUART2_CLK_TIMER_OFFSET      0x9c
-#define GC_PMU_RST1_DUSB0_LSB                    0x8
-#define GC_PMU_RST1_DUSB0_MASK                   0x100
-#define GC_PMU_RST1_DUSB0_SIZE                   0x1
-#define GC_PMU_RST1_DUSB0_DEFAULT                0x0
-#define GC_PMU_RST1_DUSB0_OFFSET                 0x9c
-#define GC_PMU_RST1_DUSB0_AON_LSB                0x9
-#define GC_PMU_RST1_DUSB0_AON_MASK               0x200
-#define GC_PMU_RST1_DUSB0_AON_SIZE               0x1
-#define GC_PMU_RST1_DUSB0_AON_DEFAULT            0x0
-#define GC_PMU_RST1_DUSB0_AON_OFFSET             0x9c
-#define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_LSB       0xa
-#define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_MASK      0x400
-#define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_SIZE      0x1
-#define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_DEFAULT   0x0
-#define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_OFFSET    0x9c
-#define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_AON_LSB   0xb
-#define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_AON_MASK  0x800
-#define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_AON_SIZE  0x1
-#define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_AON_DEFAULT 0x0
-#define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_AON_OFFSET 0x9c
-#define GC_PMU_RST1_DVOLT0_LSB                   0xc
-#define GC_PMU_RST1_DVOLT0_MASK                  0x1000
-#define GC_PMU_RST1_DVOLT0_SIZE                  0x1
-#define GC_PMU_RST1_DVOLT0_DEFAULT               0x0
-#define GC_PMU_RST1_DVOLT0_OFFSET                0x9c
-#define GC_PMU_RST1_DWATCHDOG0_LSB               0xd
-#define GC_PMU_RST1_DWATCHDOG0_MASK              0x2000
-#define GC_PMU_RST1_DWATCHDOG0_SIZE              0x1
-#define GC_PMU_RST1_DWATCHDOG0_DEFAULT           0x0
-#define GC_PMU_RST1_DWATCHDOG0_OFFSET            0x9c
-#define GC_PMU_RST1_DXO0_AON_LSB                 0xe
-#define GC_PMU_RST1_DXO0_AON_MASK                0x4000
-#define GC_PMU_RST1_DXO0_AON_SIZE                0x1
-#define GC_PMU_RST1_DXO0_AON_DEFAULT             0x0
-#define GC_PMU_RST1_DXO0_AON_OFFSET              0x9c
-#define GC_PMU_RST1_DXO0_CLK_TIMER_AON_LSB       0xf
-#define GC_PMU_RST1_DXO0_CLK_TIMER_AON_MASK      0x8000
-#define GC_PMU_RST1_DXO0_CLK_TIMER_AON_SIZE      0x1
-#define GC_PMU_RST1_DXO0_CLK_TIMER_AON_DEFAULT   0x0
-#define GC_PMU_RST1_DXO0_CLK_TIMER_AON_OFFSET    0x9c
-#define GC_PMU_RST1_PERI_MASTER_MATRIX_LSB       0x10
-#define GC_PMU_RST1_PERI_MASTER_MATRIX_MASK      0x10000
-#define GC_PMU_RST1_PERI_MASTER_MATRIX_SIZE      0x1
-#define GC_PMU_RST1_PERI_MASTER_MATRIX_DEFAULT   0x0
-#define GC_PMU_RST1_PERI_MASTER_MATRIX_OFFSET    0x9c
-#define GC_PMU_RST1_PERI_MATRIX_LSB              0x11
-#define GC_PMU_RST1_PERI_MATRIX_MASK             0x20000
-#define GC_PMU_RST1_PERI_MATRIX_SIZE             0x1
-#define GC_PMU_RST1_PERI_MATRIX_DEFAULT          0x0
-#define GC_PMU_RST1_PERI_MATRIX_OFFSET           0x9c
-#define GC_PMU_RST1_SEC_FABRIC_LSB               0x12
-#define GC_PMU_RST1_SEC_FABRIC_MASK              0x40000
-#define GC_PMU_RST1_SEC_FABRIC_SIZE              0x1
-#define GC_PMU_RST1_SEC_FABRIC_DEFAULT           0x0
-#define GC_PMU_RST1_SEC_FABRIC_OFFSET            0x9c
-#define GC_PMU_RST1_SEC_FABRIC_CLK_TIMER_LSB     0x13
-#define GC_PMU_RST1_SEC_FABRIC_CLK_TIMER_MASK    0x80000
-#define GC_PMU_RST1_SEC_FABRIC_CLK_TIMER_SIZE    0x1
-#define GC_PMU_RST1_SEC_FABRIC_CLK_TIMER_DEFAULT 0x0
-#define GC_PMU_RST1_SEC_FABRIC_CLK_TIMER_OFFSET  0x9c
-#define GC_PMU_RST1_SEC_FABRIC_CLK_HS_LSB        0x14
-#define GC_PMU_RST1_SEC_FABRIC_CLK_HS_MASK       0x100000
-#define GC_PMU_RST1_SEC_FABRIC_CLK_HS_SIZE       0x1
-#define GC_PMU_RST1_SEC_FABRIC_CLK_HS_DEFAULT    0x0
-#define GC_PMU_RST1_SEC_FABRIC_CLK_HS_OFFSET     0x9c
-#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG0_LSB  0x0
-#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG0_MASK 0x1
-#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG0_SIZE 0x1
-#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG0_DEFAULT 0x0
-#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG0_OFFSET 0x128
-#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG1_LSB  0x1
-#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG1_MASK 0x2
-#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG1_SIZE 0x1
-#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG1_DEFAULT 0x0
-#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG1_OFFSET 0x128
-#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG2_LSB  0x2
-#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG2_MASK 0x4
-#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG2_SIZE 0x1
-#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG2_DEFAULT 0x0
-#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG2_OFFSET 0x128
-#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG3_LSB  0x3
-#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG3_MASK 0x8
-#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG3_SIZE 0x1
-#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG3_DEFAULT 0x0
-#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG3_OFFSET 0x128
-#define GC_PMU_INT_ENABLE_INTR_WAKEUP_LSB        0x0
-#define GC_PMU_INT_ENABLE_INTR_WAKEUP_MASK       0x1
-#define GC_PMU_INT_ENABLE_INTR_WAKEUP_SIZE       0x1
-#define GC_PMU_INT_ENABLE_INTR_WAKEUP_DEFAULT    0x0
-#define GC_PMU_INT_ENABLE_INTR_WAKEUP_OFFSET     0x13c
-#define GC_PMU_INT_STATE_INTR_WAKEUP_LSB         0x0
-#define GC_PMU_INT_STATE_INTR_WAKEUP_MASK        0x1
-#define GC_PMU_INT_STATE_INTR_WAKEUP_SIZE        0x1
-#define GC_PMU_INT_STATE_INTR_WAKEUP_DEFAULT     0x0
-#define GC_PMU_INT_STATE_INTR_WAKEUP_OFFSET      0x140
-#define GC_PMU_INT_TEST_INTR_WAKEUP_LSB          0x0
-#define GC_PMU_INT_TEST_INTR_WAKEUP_MASK         0x1
-#define GC_PMU_INT_TEST_INTR_WAKEUP_SIZE         0x1
-#define GC_PMU_INT_TEST_INTR_WAKEUP_DEFAULT      0x0
-#define GC_PMU_INT_TEST_INTR_WAKEUP_OFFSET       0x144
-#define GC_PMU_ANTEST_TOP_CTRL_ATEST_PAD_ENB_LSB 0x0
-#define GC_PMU_ANTEST_TOP_CTRL_ATEST_PAD_ENB_MASK 0x1
-#define GC_PMU_ANTEST_TOP_CTRL_ATEST_PAD_ENB_SIZE 0x1
-#define GC_PMU_ANTEST_TOP_CTRL_ATEST_PAD_ENB_DEFAULT 0x1
-#define GC_PMU_ANTEST_TOP_CTRL_ATEST_PAD_ENB_OFFSET 0x1008
-#define GC_PMU_ANTEST_TOP_CTRL_ATEST_CLAMP_EN_LSB 0x1
-#define GC_PMU_ANTEST_TOP_CTRL_ATEST_CLAMP_EN_MASK 0x2
-#define GC_PMU_ANTEST_TOP_CTRL_ATEST_CLAMP_EN_SIZE 0x1
-#define GC_PMU_ANTEST_TOP_CTRL_ATEST_CLAMP_EN_DEFAULT 0x1
-#define GC_PMU_ANTEST_TOP_CTRL_ATEST_CLAMP_EN_OFFSET 0x1008
-#define GC_PMU_CHIP_ID_JTAG_STANDARD_LSB         0x0
-#define GC_PMU_CHIP_ID_JTAG_STANDARD_MASK        0x1
-#define GC_PMU_CHIP_ID_JTAG_STANDARD_SIZE        0x1
-#define GC_PMU_CHIP_ID_JTAG_STANDARD_DEFAULT     0x1
-#define GC_PMU_CHIP_ID_JTAG_STANDARD_OFFSET      0x1fff8
-#define GC_PMU_CHIP_ID_MFG_ID_LSB                0x1
-#define GC_PMU_CHIP_ID_MFG_ID_MASK               0xffe
-#define GC_PMU_CHIP_ID_MFG_ID_SIZE               0xb
-#define GC_PMU_CHIP_ID_MFG_ID_DEFAULT            0x4a6
-#define GC_PMU_CHIP_ID_MFG_ID_OFFSET             0x1fff8
-#define GC_PMU_CHIP_ID_PART_NUM_LSB              0xc
-#define GC_PMU_CHIP_ID_PART_NUM_MASK             0xffff000
-#define GC_PMU_CHIP_ID_PART_NUM_SIZE             0x10
-#define GC_PMU_CHIP_ID_PART_NUM_DEFAULT          0x4856
-#define GC_PMU_CHIP_ID_PART_NUM_OFFSET           0x1fff8
-#define GC_PMU_CHIP_ID_REVISION_LSB              0x1c
-#define GC_PMU_CHIP_ID_REVISION_MASK             0xf0000000
-#define GC_PMU_CHIP_ID_REVISION_SIZE             0x4
-#define GC_PMU_CHIP_ID_REVISION_DEFAULT          0x1
-#define GC_PMU_CHIP_ID_REVISION_OFFSET           0x1fff8
-#define GC_PMU_VERSION_CHANGE_LSB                0x0
-#define GC_PMU_VERSION_CHANGE_MASK               0xffffff
-#define GC_PMU_VERSION_CHANGE_SIZE               0x18
-#define GC_PMU_VERSION_CHANGE_DEFAULT            0x11f6d
-#define GC_PMU_VERSION_CHANGE_OFFSET             0x1fffc
-#define GC_PMU_VERSION_REVISION_LSB              0x18
-#define GC_PMU_VERSION_REVISION_MASK             0xff000000
-#define GC_PMU_VERSION_REVISION_SIZE             0x8
-#define GC_PMU_VERSION_REVISION_DEFAULT          0x24
-#define GC_PMU_VERSION_REVISION_OFFSET           0x1fffc
-#define GC_RBOX_INT_ENABLE_INTR_AC_PRESENT_RED_LSB 0x0
-#define GC_RBOX_INT_ENABLE_INTR_AC_PRESENT_RED_MASK 0x1
-#define GC_RBOX_INT_ENABLE_INTR_AC_PRESENT_RED_SIZE 0x1
-#define GC_RBOX_INT_ENABLE_INTR_AC_PRESENT_RED_DEFAULT 0x0
-#define GC_RBOX_INT_ENABLE_INTR_AC_PRESENT_RED_OFFSET 0x0
-#define GC_RBOX_INT_ENABLE_INTR_AC_PRESENT_FED_LSB 0x1
-#define GC_RBOX_INT_ENABLE_INTR_AC_PRESENT_FED_MASK 0x2
-#define GC_RBOX_INT_ENABLE_INTR_AC_PRESENT_FED_SIZE 0x1
-#define GC_RBOX_INT_ENABLE_INTR_AC_PRESENT_FED_DEFAULT 0x0
-#define GC_RBOX_INT_ENABLE_INTR_AC_PRESENT_FED_OFFSET 0x0
-#define GC_RBOX_INT_ENABLE_INTR_ENTERING_RW_RED_LSB 0x2
-#define GC_RBOX_INT_ENABLE_INTR_ENTERING_RW_RED_MASK 0x4
-#define GC_RBOX_INT_ENABLE_INTR_ENTERING_RW_RED_SIZE 0x1
-#define GC_RBOX_INT_ENABLE_INTR_ENTERING_RW_RED_DEFAULT 0x0
-#define GC_RBOX_INT_ENABLE_INTR_ENTERING_RW_RED_OFFSET 0x0
-#define GC_RBOX_INT_ENABLE_INTR_ENTERING_RW_FED_LSB 0x3
-#define GC_RBOX_INT_ENABLE_INTR_ENTERING_RW_FED_MASK 0x8
-#define GC_RBOX_INT_ENABLE_INTR_ENTERING_RW_FED_SIZE 0x1
-#define GC_RBOX_INT_ENABLE_INTR_ENTERING_RW_FED_DEFAULT 0x0
-#define GC_RBOX_INT_ENABLE_INTR_ENTERING_RW_FED_OFFSET 0x0
-#define GC_RBOX_INT_ENABLE_INTR_PWRB_IN_RED_LSB  0x4
-#define GC_RBOX_INT_ENABLE_INTR_PWRB_IN_RED_MASK 0x10
-#define GC_RBOX_INT_ENABLE_INTR_PWRB_IN_RED_SIZE 0x1
-#define GC_RBOX_INT_ENABLE_INTR_PWRB_IN_RED_DEFAULT 0x0
-#define GC_RBOX_INT_ENABLE_INTR_PWRB_IN_RED_OFFSET 0x0
-#define GC_RBOX_INT_ENABLE_INTR_PWRB_IN_FED_LSB  0x5
-#define GC_RBOX_INT_ENABLE_INTR_PWRB_IN_FED_MASK 0x20
-#define GC_RBOX_INT_ENABLE_INTR_PWRB_IN_FED_SIZE 0x1
-#define GC_RBOX_INT_ENABLE_INTR_PWRB_IN_FED_DEFAULT 0x0
-#define GC_RBOX_INT_ENABLE_INTR_PWRB_IN_FED_OFFSET 0x0
-#define GC_RBOX_INT_ENABLE_INTR_KEY0_IN_RED_LSB  0x6
-#define GC_RBOX_INT_ENABLE_INTR_KEY0_IN_RED_MASK 0x40
-#define GC_RBOX_INT_ENABLE_INTR_KEY0_IN_RED_SIZE 0x1
-#define GC_RBOX_INT_ENABLE_INTR_KEY0_IN_RED_DEFAULT 0x0
-#define GC_RBOX_INT_ENABLE_INTR_KEY0_IN_RED_OFFSET 0x0
-#define GC_RBOX_INT_ENABLE_INTR_KEY0_IN_FED_LSB  0x7
-#define GC_RBOX_INT_ENABLE_INTR_KEY0_IN_FED_MASK 0x80
-#define GC_RBOX_INT_ENABLE_INTR_KEY0_IN_FED_SIZE 0x1
-#define GC_RBOX_INT_ENABLE_INTR_KEY0_IN_FED_DEFAULT 0x0
-#define GC_RBOX_INT_ENABLE_INTR_KEY0_IN_FED_OFFSET 0x0
-#define GC_RBOX_INT_ENABLE_INTR_KEY1_IN_RED_LSB  0x8
-#define GC_RBOX_INT_ENABLE_INTR_KEY1_IN_RED_MASK 0x100
-#define GC_RBOX_INT_ENABLE_INTR_KEY1_IN_RED_SIZE 0x1
-#define GC_RBOX_INT_ENABLE_INTR_KEY1_IN_RED_DEFAULT 0x0
-#define GC_RBOX_INT_ENABLE_INTR_KEY1_IN_RED_OFFSET 0x0
-#define GC_RBOX_INT_ENABLE_INTR_KEY1_IN_FED_LSB  0x9
-#define GC_RBOX_INT_ENABLE_INTR_KEY1_IN_FED_MASK 0x200
-#define GC_RBOX_INT_ENABLE_INTR_KEY1_IN_FED_SIZE 0x1
-#define GC_RBOX_INT_ENABLE_INTR_KEY1_IN_FED_DEFAULT 0x0
-#define GC_RBOX_INT_ENABLE_INTR_KEY1_IN_FED_OFFSET 0x0
-#define GC_RBOX_INT_ENABLE_INTR_EC_RST_RED_LSB   0xa
-#define GC_RBOX_INT_ENABLE_INTR_EC_RST_RED_MASK  0x400
-#define GC_RBOX_INT_ENABLE_INTR_EC_RST_RED_SIZE  0x1
-#define GC_RBOX_INT_ENABLE_INTR_EC_RST_RED_DEFAULT 0x0
-#define GC_RBOX_INT_ENABLE_INTR_EC_RST_RED_OFFSET 0x0
-#define GC_RBOX_INT_ENABLE_INTR_EC_RST_FED_LSB   0xb
-#define GC_RBOX_INT_ENABLE_INTR_EC_RST_FED_MASK  0x800
-#define GC_RBOX_INT_ENABLE_INTR_EC_RST_FED_SIZE  0x1
-#define GC_RBOX_INT_ENABLE_INTR_EC_RST_FED_DEFAULT 0x0
-#define GC_RBOX_INT_ENABLE_INTR_EC_RST_FED_OFFSET 0x0
-#define GC_RBOX_INT_ENABLE_INTR_BUTTON_COMBO0_RDY_LSB 0xc
-#define GC_RBOX_INT_ENABLE_INTR_BUTTON_COMBO0_RDY_MASK 0x1000
-#define GC_RBOX_INT_ENABLE_INTR_BUTTON_COMBO0_RDY_SIZE 0x1
-#define GC_RBOX_INT_ENABLE_INTR_BUTTON_COMBO0_RDY_DEFAULT 0x0
-#define GC_RBOX_INT_ENABLE_INTR_BUTTON_COMBO0_RDY_OFFSET 0x0
-#define GC_RBOX_INT_ENABLE_INTR_BUTTON_COMBO1_RDY_LSB 0xd
-#define GC_RBOX_INT_ENABLE_INTR_BUTTON_COMBO1_RDY_MASK 0x2000
-#define GC_RBOX_INT_ENABLE_INTR_BUTTON_COMBO1_RDY_SIZE 0x1
-#define GC_RBOX_INT_ENABLE_INTR_BUTTON_COMBO1_RDY_DEFAULT 0x0
-#define GC_RBOX_INT_ENABLE_INTR_BUTTON_COMBO1_RDY_OFFSET 0x0
-#define GC_RBOX_INT_ENABLE_INTR_BUTTON_COMBO2_RDY_LSB 0xe
-#define GC_RBOX_INT_ENABLE_INTR_BUTTON_COMBO2_RDY_MASK 0x4000
-#define GC_RBOX_INT_ENABLE_INTR_BUTTON_COMBO2_RDY_SIZE 0x1
-#define GC_RBOX_INT_ENABLE_INTR_BUTTON_COMBO2_RDY_DEFAULT 0x0
-#define GC_RBOX_INT_ENABLE_INTR_BUTTON_COMBO2_RDY_OFFSET 0x0
-#define GC_RBOX_INT_STATE_INTR_AC_PRESENT_RED_LSB 0x0
-#define GC_RBOX_INT_STATE_INTR_AC_PRESENT_RED_MASK 0x1
-#define GC_RBOX_INT_STATE_INTR_AC_PRESENT_RED_SIZE 0x1
-#define GC_RBOX_INT_STATE_INTR_AC_PRESENT_RED_DEFAULT 0x0
-#define GC_RBOX_INT_STATE_INTR_AC_PRESENT_RED_OFFSET 0x4
-#define GC_RBOX_INT_STATE_INTR_AC_PRESENT_FED_LSB 0x1
-#define GC_RBOX_INT_STATE_INTR_AC_PRESENT_FED_MASK 0x2
-#define GC_RBOX_INT_STATE_INTR_AC_PRESENT_FED_SIZE 0x1
-#define GC_RBOX_INT_STATE_INTR_AC_PRESENT_FED_DEFAULT 0x0
-#define GC_RBOX_INT_STATE_INTR_AC_PRESENT_FED_OFFSET 0x4
-#define GC_RBOX_INT_STATE_INTR_ENTERING_RW_RED_LSB 0x2
-#define GC_RBOX_INT_STATE_INTR_ENTERING_RW_RED_MASK 0x4
-#define GC_RBOX_INT_STATE_INTR_ENTERING_RW_RED_SIZE 0x1
-#define GC_RBOX_INT_STATE_INTR_ENTERING_RW_RED_DEFAULT 0x0
-#define GC_RBOX_INT_STATE_INTR_ENTERING_RW_RED_OFFSET 0x4
-#define GC_RBOX_INT_STATE_INTR_ENTERING_RW_FED_LSB 0x3
-#define GC_RBOX_INT_STATE_INTR_ENTERING_RW_FED_MASK 0x8
-#define GC_RBOX_INT_STATE_INTR_ENTERING_RW_FED_SIZE 0x1
-#define GC_RBOX_INT_STATE_INTR_ENTERING_RW_FED_DEFAULT 0x0
-#define GC_RBOX_INT_STATE_INTR_ENTERING_RW_FED_OFFSET 0x4
-#define GC_RBOX_INT_STATE_INTR_PWRB_IN_RED_LSB   0x4
-#define GC_RBOX_INT_STATE_INTR_PWRB_IN_RED_MASK  0x10
-#define GC_RBOX_INT_STATE_INTR_PWRB_IN_RED_SIZE  0x1
-#define GC_RBOX_INT_STATE_INTR_PWRB_IN_RED_DEFAULT 0x0
-#define GC_RBOX_INT_STATE_INTR_PWRB_IN_RED_OFFSET 0x4
-#define GC_RBOX_INT_STATE_INTR_PWRB_IN_FED_LSB   0x5
-#define GC_RBOX_INT_STATE_INTR_PWRB_IN_FED_MASK  0x20
-#define GC_RBOX_INT_STATE_INTR_PWRB_IN_FED_SIZE  0x1
-#define GC_RBOX_INT_STATE_INTR_PWRB_IN_FED_DEFAULT 0x0
-#define GC_RBOX_INT_STATE_INTR_PWRB_IN_FED_OFFSET 0x4
-#define GC_RBOX_INT_STATE_INTR_KEY0_IN_RED_LSB   0x6
-#define GC_RBOX_INT_STATE_INTR_KEY0_IN_RED_MASK  0x40
-#define GC_RBOX_INT_STATE_INTR_KEY0_IN_RED_SIZE  0x1
-#define GC_RBOX_INT_STATE_INTR_KEY0_IN_RED_DEFAULT 0x0
-#define GC_RBOX_INT_STATE_INTR_KEY0_IN_RED_OFFSET 0x4
-#define GC_RBOX_INT_STATE_INTR_KEY0_IN_FED_LSB   0x7
-#define GC_RBOX_INT_STATE_INTR_KEY0_IN_FED_MASK  0x80
-#define GC_RBOX_INT_STATE_INTR_KEY0_IN_FED_SIZE  0x1
-#define GC_RBOX_INT_STATE_INTR_KEY0_IN_FED_DEFAULT 0x0
-#define GC_RBOX_INT_STATE_INTR_KEY0_IN_FED_OFFSET 0x4
-#define GC_RBOX_INT_STATE_INTR_KEY1_IN_RED_LSB   0x8
-#define GC_RBOX_INT_STATE_INTR_KEY1_IN_RED_MASK  0x100
-#define GC_RBOX_INT_STATE_INTR_KEY1_IN_RED_SIZE  0x1
-#define GC_RBOX_INT_STATE_INTR_KEY1_IN_RED_DEFAULT 0x0
-#define GC_RBOX_INT_STATE_INTR_KEY1_IN_RED_OFFSET 0x4
-#define GC_RBOX_INT_STATE_INTR_KEY1_IN_FED_LSB   0x9
-#define GC_RBOX_INT_STATE_INTR_KEY1_IN_FED_MASK  0x200
-#define GC_RBOX_INT_STATE_INTR_KEY1_IN_FED_SIZE  0x1
-#define GC_RBOX_INT_STATE_INTR_KEY1_IN_FED_DEFAULT 0x0
-#define GC_RBOX_INT_STATE_INTR_KEY1_IN_FED_OFFSET 0x4
-#define GC_RBOX_INT_STATE_INTR_EC_RST_RED_LSB    0xa
-#define GC_RBOX_INT_STATE_INTR_EC_RST_RED_MASK   0x400
-#define GC_RBOX_INT_STATE_INTR_EC_RST_RED_SIZE   0x1
-#define GC_RBOX_INT_STATE_INTR_EC_RST_RED_DEFAULT 0x0
-#define GC_RBOX_INT_STATE_INTR_EC_RST_RED_OFFSET 0x4
-#define GC_RBOX_INT_STATE_INTR_EC_RST_FED_LSB    0xb
-#define GC_RBOX_INT_STATE_INTR_EC_RST_FED_MASK   0x800
-#define GC_RBOX_INT_STATE_INTR_EC_RST_FED_SIZE   0x1
-#define GC_RBOX_INT_STATE_INTR_EC_RST_FED_DEFAULT 0x0
-#define GC_RBOX_INT_STATE_INTR_EC_RST_FED_OFFSET 0x4
-#define GC_RBOX_INT_STATE_INTR_BUTTON_COMBO0_RDY_LSB 0xc
-#define GC_RBOX_INT_STATE_INTR_BUTTON_COMBO0_RDY_MASK 0x1000
-#define GC_RBOX_INT_STATE_INTR_BUTTON_COMBO0_RDY_SIZE 0x1
-#define GC_RBOX_INT_STATE_INTR_BUTTON_COMBO0_RDY_DEFAULT 0x0
-#define GC_RBOX_INT_STATE_INTR_BUTTON_COMBO0_RDY_OFFSET 0x4
-#define GC_RBOX_INT_STATE_INTR_BUTTON_COMBO1_RDY_LSB 0xd
-#define GC_RBOX_INT_STATE_INTR_BUTTON_COMBO1_RDY_MASK 0x2000
-#define GC_RBOX_INT_STATE_INTR_BUTTON_COMBO1_RDY_SIZE 0x1
-#define GC_RBOX_INT_STATE_INTR_BUTTON_COMBO1_RDY_DEFAULT 0x0
-#define GC_RBOX_INT_STATE_INTR_BUTTON_COMBO1_RDY_OFFSET 0x4
-#define GC_RBOX_INT_STATE_INTR_BUTTON_COMBO2_RDY_LSB 0xe
-#define GC_RBOX_INT_STATE_INTR_BUTTON_COMBO2_RDY_MASK 0x4000
-#define GC_RBOX_INT_STATE_INTR_BUTTON_COMBO2_RDY_SIZE 0x1
-#define GC_RBOX_INT_STATE_INTR_BUTTON_COMBO2_RDY_DEFAULT 0x0
-#define GC_RBOX_INT_STATE_INTR_BUTTON_COMBO2_RDY_OFFSET 0x4
-#define GC_RBOX_INT_TEST_INTR_AC_PRESENT_RED_LSB 0x0
-#define GC_RBOX_INT_TEST_INTR_AC_PRESENT_RED_MASK 0x1
-#define GC_RBOX_INT_TEST_INTR_AC_PRESENT_RED_SIZE 0x1
-#define GC_RBOX_INT_TEST_INTR_AC_PRESENT_RED_DEFAULT 0x0
-#define GC_RBOX_INT_TEST_INTR_AC_PRESENT_RED_OFFSET 0x8
-#define GC_RBOX_INT_TEST_INTR_AC_PRESENT_FED_LSB 0x1
-#define GC_RBOX_INT_TEST_INTR_AC_PRESENT_FED_MASK 0x2
-#define GC_RBOX_INT_TEST_INTR_AC_PRESENT_FED_SIZE 0x1
-#define GC_RBOX_INT_TEST_INTR_AC_PRESENT_FED_DEFAULT 0x0
-#define GC_RBOX_INT_TEST_INTR_AC_PRESENT_FED_OFFSET 0x8
-#define GC_RBOX_INT_TEST_INTR_ENTERING_RW_RED_LSB 0x2
-#define GC_RBOX_INT_TEST_INTR_ENTERING_RW_RED_MASK 0x4
-#define GC_RBOX_INT_TEST_INTR_ENTERING_RW_RED_SIZE 0x1
-#define GC_RBOX_INT_TEST_INTR_ENTERING_RW_RED_DEFAULT 0x0
-#define GC_RBOX_INT_TEST_INTR_ENTERING_RW_RED_OFFSET 0x8
-#define GC_RBOX_INT_TEST_INTR_ENTERING_RW_FED_LSB 0x3
-#define GC_RBOX_INT_TEST_INTR_ENTERING_RW_FED_MASK 0x8
-#define GC_RBOX_INT_TEST_INTR_ENTERING_RW_FED_SIZE 0x1
-#define GC_RBOX_INT_TEST_INTR_ENTERING_RW_FED_DEFAULT 0x0
-#define GC_RBOX_INT_TEST_INTR_ENTERING_RW_FED_OFFSET 0x8
-#define GC_RBOX_INT_TEST_INTR_PWRB_IN_RED_LSB    0x4
-#define GC_RBOX_INT_TEST_INTR_PWRB_IN_RED_MASK   0x10
-#define GC_RBOX_INT_TEST_INTR_PWRB_IN_RED_SIZE   0x1
-#define GC_RBOX_INT_TEST_INTR_PWRB_IN_RED_DEFAULT 0x0
-#define GC_RBOX_INT_TEST_INTR_PWRB_IN_RED_OFFSET 0x8
-#define GC_RBOX_INT_TEST_INTR_PWRB_IN_FED_LSB    0x5
-#define GC_RBOX_INT_TEST_INTR_PWRB_IN_FED_MASK   0x20
-#define GC_RBOX_INT_TEST_INTR_PWRB_IN_FED_SIZE   0x1
-#define GC_RBOX_INT_TEST_INTR_PWRB_IN_FED_DEFAULT 0x0
-#define GC_RBOX_INT_TEST_INTR_PWRB_IN_FED_OFFSET 0x8
-#define GC_RBOX_INT_TEST_INTR_KEY0_IN_RED_LSB    0x6
-#define GC_RBOX_INT_TEST_INTR_KEY0_IN_RED_MASK   0x40
-#define GC_RBOX_INT_TEST_INTR_KEY0_IN_RED_SIZE   0x1
-#define GC_RBOX_INT_TEST_INTR_KEY0_IN_RED_DEFAULT 0x0
-#define GC_RBOX_INT_TEST_INTR_KEY0_IN_RED_OFFSET 0x8
-#define GC_RBOX_INT_TEST_INTR_KEY0_IN_FED_LSB    0x7
-#define GC_RBOX_INT_TEST_INTR_KEY0_IN_FED_MASK   0x80
-#define GC_RBOX_INT_TEST_INTR_KEY0_IN_FED_SIZE   0x1
-#define GC_RBOX_INT_TEST_INTR_KEY0_IN_FED_DEFAULT 0x0
-#define GC_RBOX_INT_TEST_INTR_KEY0_IN_FED_OFFSET 0x8
-#define GC_RBOX_INT_TEST_INTR_KEY1_IN_RED_LSB    0x8
-#define GC_RBOX_INT_TEST_INTR_KEY1_IN_RED_MASK   0x100
-#define GC_RBOX_INT_TEST_INTR_KEY1_IN_RED_SIZE   0x1
-#define GC_RBOX_INT_TEST_INTR_KEY1_IN_RED_DEFAULT 0x0
-#define GC_RBOX_INT_TEST_INTR_KEY1_IN_RED_OFFSET 0x8
-#define GC_RBOX_INT_TEST_INTR_KEY1_IN_FED_LSB    0x9
-#define GC_RBOX_INT_TEST_INTR_KEY1_IN_FED_MASK   0x200
-#define GC_RBOX_INT_TEST_INTR_KEY1_IN_FED_SIZE   0x1
-#define GC_RBOX_INT_TEST_INTR_KEY1_IN_FED_DEFAULT 0x0
-#define GC_RBOX_INT_TEST_INTR_KEY1_IN_FED_OFFSET 0x8
-#define GC_RBOX_INT_TEST_INTR_EC_RST_RED_LSB     0xa
-#define GC_RBOX_INT_TEST_INTR_EC_RST_RED_MASK    0x400
-#define GC_RBOX_INT_TEST_INTR_EC_RST_RED_SIZE    0x1
-#define GC_RBOX_INT_TEST_INTR_EC_RST_RED_DEFAULT 0x0
-#define GC_RBOX_INT_TEST_INTR_EC_RST_RED_OFFSET  0x8
-#define GC_RBOX_INT_TEST_INTR_EC_RST_FED_LSB     0xb
-#define GC_RBOX_INT_TEST_INTR_EC_RST_FED_MASK    0x800
-#define GC_RBOX_INT_TEST_INTR_EC_RST_FED_SIZE    0x1
-#define GC_RBOX_INT_TEST_INTR_EC_RST_FED_DEFAULT 0x0
-#define GC_RBOX_INT_TEST_INTR_EC_RST_FED_OFFSET  0x8
-#define GC_RBOX_INT_TEST_INTR_BUTTON_COMBO0_RDY_LSB 0xc
-#define GC_RBOX_INT_TEST_INTR_BUTTON_COMBO0_RDY_MASK 0x1000
-#define GC_RBOX_INT_TEST_INTR_BUTTON_COMBO0_RDY_SIZE 0x1
-#define GC_RBOX_INT_TEST_INTR_BUTTON_COMBO0_RDY_DEFAULT 0x0
-#define GC_RBOX_INT_TEST_INTR_BUTTON_COMBO0_RDY_OFFSET 0x8
-#define GC_RBOX_INT_TEST_INTR_BUTTON_COMBO1_RDY_LSB 0xd
-#define GC_RBOX_INT_TEST_INTR_BUTTON_COMBO1_RDY_MASK 0x2000
-#define GC_RBOX_INT_TEST_INTR_BUTTON_COMBO1_RDY_SIZE 0x1
-#define GC_RBOX_INT_TEST_INTR_BUTTON_COMBO1_RDY_DEFAULT 0x0
-#define GC_RBOX_INT_TEST_INTR_BUTTON_COMBO1_RDY_OFFSET 0x8
-#define GC_RBOX_INT_TEST_INTR_BUTTON_COMBO2_RDY_LSB 0xe
-#define GC_RBOX_INT_TEST_INTR_BUTTON_COMBO2_RDY_MASK 0x4000
-#define GC_RBOX_INT_TEST_INTR_BUTTON_COMBO2_RDY_SIZE 0x1
-#define GC_RBOX_INT_TEST_INTR_BUTTON_COMBO2_RDY_DEFAULT 0x0
-#define GC_RBOX_INT_TEST_INTR_BUTTON_COMBO2_RDY_OFFSET 0x8
-#define GC_RBOX_OVERRIDE_OUTPUT_EN_LSB           0x0
-#define GC_RBOX_OVERRIDE_OUTPUT_EN_MASK          0x7f
-#define GC_RBOX_OVERRIDE_OUTPUT_EN_SIZE          0x7
-#define GC_RBOX_OVERRIDE_OUTPUT_EN_DEFAULT       0x0
-#define GC_RBOX_OVERRIDE_OUTPUT_EN_OFFSET        0x14
-#define GC_RBOX_OVERRIDE_OUTPUT_VAL_LSB          0x7
-#define GC_RBOX_OVERRIDE_OUTPUT_VAL_MASK         0x3f80
-#define GC_RBOX_OVERRIDE_OUTPUT_VAL_SIZE         0x7
-#define GC_RBOX_OVERRIDE_OUTPUT_VAL_DEFAULT      0x5d
-#define GC_RBOX_OVERRIDE_OUTPUT_VAL_OFFSET       0x14
-#define GC_RBOX_OVERRIDE_OUTPUT_OEN_LSB          0xe
-#define GC_RBOX_OVERRIDE_OUTPUT_OEN_MASK         0x1fc000
-#define GC_RBOX_OVERRIDE_OUTPUT_OEN_SIZE         0x7
-#define GC_RBOX_OVERRIDE_OUTPUT_OEN_DEFAULT      0x0
-#define GC_RBOX_OVERRIDE_OUTPUT_OEN_OFFSET       0x14
-#define GC_RBOX_CHECK_INPUT_AC_PRESENT_LSB       0x0
-#define GC_RBOX_CHECK_INPUT_AC_PRESENT_MASK      0x1
-#define GC_RBOX_CHECK_INPUT_AC_PRESENT_SIZE      0x1
-#define GC_RBOX_CHECK_INPUT_AC_PRESENT_DEFAULT   0x0
-#define GC_RBOX_CHECK_INPUT_AC_PRESENT_OFFSET    0x18
-#define GC_RBOX_CHECK_INPUT_ENTERING_RW_LSB      0x1
-#define GC_RBOX_CHECK_INPUT_ENTERING_RW_MASK     0x2
-#define GC_RBOX_CHECK_INPUT_ENTERING_RW_SIZE     0x1
-#define GC_RBOX_CHECK_INPUT_ENTERING_RW_DEFAULT  0x0
-#define GC_RBOX_CHECK_INPUT_ENTERING_RW_OFFSET   0x18
-#define GC_RBOX_CHECK_INPUT_PWRB_IN_LSB          0x2
-#define GC_RBOX_CHECK_INPUT_PWRB_IN_MASK         0x4
-#define GC_RBOX_CHECK_INPUT_PWRB_IN_SIZE         0x1
-#define GC_RBOX_CHECK_INPUT_PWRB_IN_DEFAULT      0x0
-#define GC_RBOX_CHECK_INPUT_PWRB_IN_OFFSET       0x18
-#define GC_RBOX_CHECK_INPUT_KEY0_IN_LSB          0x3
-#define GC_RBOX_CHECK_INPUT_KEY0_IN_MASK         0x8
-#define GC_RBOX_CHECK_INPUT_KEY0_IN_SIZE         0x1
-#define GC_RBOX_CHECK_INPUT_KEY0_IN_DEFAULT      0x0
-#define GC_RBOX_CHECK_INPUT_KEY0_IN_OFFSET       0x18
-#define GC_RBOX_CHECK_INPUT_KEY1_IN_LSB          0x4
-#define GC_RBOX_CHECK_INPUT_KEY1_IN_MASK         0x10
-#define GC_RBOX_CHECK_INPUT_KEY1_IN_SIZE         0x1
-#define GC_RBOX_CHECK_INPUT_KEY1_IN_DEFAULT      0x0
-#define GC_RBOX_CHECK_INPUT_KEY1_IN_OFFSET       0x18
-#define GC_RBOX_CHECK_INPUT_EC_RST_LSB           0x5
-#define GC_RBOX_CHECK_INPUT_EC_RST_MASK          0x20
-#define GC_RBOX_CHECK_INPUT_EC_RST_SIZE          0x1
-#define GC_RBOX_CHECK_INPUT_EC_RST_DEFAULT       0x0
-#define GC_RBOX_CHECK_INPUT_EC_RST_OFFSET        0x18
-#define GC_RBOX_CHECK_OUTPUT_BATT_DISABLE_LSB    0x0
-#define GC_RBOX_CHECK_OUTPUT_BATT_DISABLE_MASK   0x1
-#define GC_RBOX_CHECK_OUTPUT_BATT_DISABLE_SIZE   0x1
-#define GC_RBOX_CHECK_OUTPUT_BATT_DISABLE_DEFAULT 0x0
-#define GC_RBOX_CHECK_OUTPUT_BATT_DISABLE_OFFSET 0x1c
-#define GC_RBOX_CHECK_OUTPUT_EC_IN_RW_LSB        0x1
-#define GC_RBOX_CHECK_OUTPUT_EC_IN_RW_MASK       0x2
-#define GC_RBOX_CHECK_OUTPUT_EC_IN_RW_SIZE       0x1
-#define GC_RBOX_CHECK_OUTPUT_EC_IN_RW_DEFAULT    0x0
-#define GC_RBOX_CHECK_OUTPUT_EC_IN_RW_OFFSET     0x1c
-#define GC_RBOX_CHECK_OUTPUT_PWRB_OUT_LSB        0x2
-#define GC_RBOX_CHECK_OUTPUT_PWRB_OUT_MASK       0x4
-#define GC_RBOX_CHECK_OUTPUT_PWRB_OUT_SIZE       0x1
-#define GC_RBOX_CHECK_OUTPUT_PWRB_OUT_DEFAULT    0x0
-#define GC_RBOX_CHECK_OUTPUT_PWRB_OUT_OFFSET     0x1c
-#define GC_RBOX_CHECK_OUTPUT_KEY0_OUT_LSB        0x3
-#define GC_RBOX_CHECK_OUTPUT_KEY0_OUT_MASK       0x8
-#define GC_RBOX_CHECK_OUTPUT_KEY0_OUT_SIZE       0x1
-#define GC_RBOX_CHECK_OUTPUT_KEY0_OUT_DEFAULT    0x0
-#define GC_RBOX_CHECK_OUTPUT_KEY0_OUT_OFFSET     0x1c
-#define GC_RBOX_CHECK_OUTPUT_KEY1_OUT_LSB        0x4
-#define GC_RBOX_CHECK_OUTPUT_KEY1_OUT_MASK       0x10
-#define GC_RBOX_CHECK_OUTPUT_KEY1_OUT_SIZE       0x1
-#define GC_RBOX_CHECK_OUTPUT_KEY1_OUT_DEFAULT    0x0
-#define GC_RBOX_CHECK_OUTPUT_KEY1_OUT_OFFSET     0x1c
-#define GC_RBOX_CHECK_OUTPUT_EC_WP_L_LSB         0x5
-#define GC_RBOX_CHECK_OUTPUT_EC_WP_L_MASK        0x20
-#define GC_RBOX_CHECK_OUTPUT_EC_WP_L_SIZE        0x1
-#define GC_RBOX_CHECK_OUTPUT_EC_WP_L_DEFAULT     0x0
-#define GC_RBOX_CHECK_OUTPUT_EC_WP_L_OFFSET      0x1c
-#define GC_RBOX_CHECK_OUTPUT_EC_RST_LSB          0x6
-#define GC_RBOX_CHECK_OUTPUT_EC_RST_MASK         0x40
-#define GC_RBOX_CHECK_OUTPUT_EC_RST_SIZE         0x1
-#define GC_RBOX_CHECK_OUTPUT_EC_RST_DEFAULT      0x0
-#define GC_RBOX_CHECK_OUTPUT_EC_RST_OFFSET       0x1c
-#define GC_RBOX_CHECK_OEN_BATT_DISABLE_LSB       0x0
-#define GC_RBOX_CHECK_OEN_BATT_DISABLE_MASK      0x1
-#define GC_RBOX_CHECK_OEN_BATT_DISABLE_SIZE      0x1
-#define GC_RBOX_CHECK_OEN_BATT_DISABLE_DEFAULT   0x0
-#define GC_RBOX_CHECK_OEN_BATT_DISABLE_OFFSET    0x20
-#define GC_RBOX_CHECK_OEN_EC_IN_RW_LSB           0x1
-#define GC_RBOX_CHECK_OEN_EC_IN_RW_MASK          0x2
-#define GC_RBOX_CHECK_OEN_EC_IN_RW_SIZE          0x1
-#define GC_RBOX_CHECK_OEN_EC_IN_RW_DEFAULT       0x0
-#define GC_RBOX_CHECK_OEN_EC_IN_RW_OFFSET        0x20
-#define GC_RBOX_CHECK_OEN_PWRB_OUT_LSB           0x2
-#define GC_RBOX_CHECK_OEN_PWRB_OUT_MASK          0x4
-#define GC_RBOX_CHECK_OEN_PWRB_OUT_SIZE          0x1
-#define GC_RBOX_CHECK_OEN_PWRB_OUT_DEFAULT       0x0
-#define GC_RBOX_CHECK_OEN_PWRB_OUT_OFFSET        0x20
-#define GC_RBOX_CHECK_OEN_KEY0_OUT_LSB           0x3
-#define GC_RBOX_CHECK_OEN_KEY0_OUT_MASK          0x8
-#define GC_RBOX_CHECK_OEN_KEY0_OUT_SIZE          0x1
-#define GC_RBOX_CHECK_OEN_KEY0_OUT_DEFAULT       0x0
-#define GC_RBOX_CHECK_OEN_KEY0_OUT_OFFSET        0x20
-#define GC_RBOX_CHECK_OEN_KEY1_OUT_LSB           0x4
-#define GC_RBOX_CHECK_OEN_KEY1_OUT_MASK          0x10
-#define GC_RBOX_CHECK_OEN_KEY1_OUT_SIZE          0x1
-#define GC_RBOX_CHECK_OEN_KEY1_OUT_DEFAULT       0x0
-#define GC_RBOX_CHECK_OEN_KEY1_OUT_OFFSET        0x20
-#define GC_RBOX_CHECK_OEN_EC_WP_L_LSB            0x5
-#define GC_RBOX_CHECK_OEN_EC_WP_L_MASK           0x20
-#define GC_RBOX_CHECK_OEN_EC_WP_L_SIZE           0x1
-#define GC_RBOX_CHECK_OEN_EC_WP_L_DEFAULT        0x0
-#define GC_RBOX_CHECK_OEN_EC_WP_L_OFFSET         0x20
-#define GC_RBOX_CHECK_OEN_EC_RST_LSB             0x6
-#define GC_RBOX_CHECK_OEN_EC_RST_MASK            0x40
-#define GC_RBOX_CHECK_OEN_EC_RST_SIZE            0x1
-#define GC_RBOX_CHECK_OEN_EC_RST_DEFAULT         0x0
-#define GC_RBOX_CHECK_OEN_EC_RST_OFFSET          0x20
-#define GC_RBOX_CHECK_TERM_PU_AC_PRESENT_LSB     0x0
-#define GC_RBOX_CHECK_TERM_PU_AC_PRESENT_MASK    0x1
-#define GC_RBOX_CHECK_TERM_PU_AC_PRESENT_SIZE    0x1
-#define GC_RBOX_CHECK_TERM_PU_AC_PRESENT_DEFAULT 0x0
-#define GC_RBOX_CHECK_TERM_PU_AC_PRESENT_OFFSET  0x24
-#define GC_RBOX_CHECK_TERM_PD_AC_PRESENT_LSB     0x1
-#define GC_RBOX_CHECK_TERM_PD_AC_PRESENT_MASK    0x2
-#define GC_RBOX_CHECK_TERM_PD_AC_PRESENT_SIZE    0x1
-#define GC_RBOX_CHECK_TERM_PD_AC_PRESENT_DEFAULT 0x0
-#define GC_RBOX_CHECK_TERM_PD_AC_PRESENT_OFFSET  0x24
-#define GC_RBOX_CHECK_TERM_PU_ENTERING_RW_LSB    0x2
-#define GC_RBOX_CHECK_TERM_PU_ENTERING_RW_MASK   0x4
-#define GC_RBOX_CHECK_TERM_PU_ENTERING_RW_SIZE   0x1
-#define GC_RBOX_CHECK_TERM_PU_ENTERING_RW_DEFAULT 0x0
-#define GC_RBOX_CHECK_TERM_PU_ENTERING_RW_OFFSET 0x24
-#define GC_RBOX_CHECK_TERM_PD_ENTERING_RW_LSB    0x3
-#define GC_RBOX_CHECK_TERM_PD_ENTERING_RW_MASK   0x8
-#define GC_RBOX_CHECK_TERM_PD_ENTERING_RW_SIZE   0x1
-#define GC_RBOX_CHECK_TERM_PD_ENTERING_RW_DEFAULT 0x0
-#define GC_RBOX_CHECK_TERM_PD_ENTERING_RW_OFFSET 0x24
-#define GC_RBOX_CHECK_TERM_PU_PWRB_IN_LSB        0x4
-#define GC_RBOX_CHECK_TERM_PU_PWRB_IN_MASK       0x10
-#define GC_RBOX_CHECK_TERM_PU_PWRB_IN_SIZE       0x1
-#define GC_RBOX_CHECK_TERM_PU_PWRB_IN_DEFAULT    0x0
-#define GC_RBOX_CHECK_TERM_PU_PWRB_IN_OFFSET     0x24
-#define GC_RBOX_CHECK_TERM_PD_PWRB_IN_LSB        0x5
-#define GC_RBOX_CHECK_TERM_PD_PWRB_IN_MASK       0x20
-#define GC_RBOX_CHECK_TERM_PD_PWRB_IN_SIZE       0x1
-#define GC_RBOX_CHECK_TERM_PD_PWRB_IN_DEFAULT    0x0
-#define GC_RBOX_CHECK_TERM_PD_PWRB_IN_OFFSET     0x24
-#define GC_RBOX_CHECK_TERM_PU_KEY0_IN_LSB        0x6
-#define GC_RBOX_CHECK_TERM_PU_KEY0_IN_MASK       0x40
-#define GC_RBOX_CHECK_TERM_PU_KEY0_IN_SIZE       0x1
-#define GC_RBOX_CHECK_TERM_PU_KEY0_IN_DEFAULT    0x0
-#define GC_RBOX_CHECK_TERM_PU_KEY0_IN_OFFSET     0x24
-#define GC_RBOX_CHECK_TERM_PD_KEY0_IN_LSB        0x7
-#define GC_RBOX_CHECK_TERM_PD_KEY0_IN_MASK       0x80
-#define GC_RBOX_CHECK_TERM_PD_KEY0_IN_SIZE       0x1
-#define GC_RBOX_CHECK_TERM_PD_KEY0_IN_DEFAULT    0x0
-#define GC_RBOX_CHECK_TERM_PD_KEY0_IN_OFFSET     0x24
-#define GC_RBOX_CHECK_TERM_PU_KEY1_IN_LSB        0x8
-#define GC_RBOX_CHECK_TERM_PU_KEY1_IN_MASK       0x100
-#define GC_RBOX_CHECK_TERM_PU_KEY1_IN_SIZE       0x1
-#define GC_RBOX_CHECK_TERM_PU_KEY1_IN_DEFAULT    0x0
-#define GC_RBOX_CHECK_TERM_PU_KEY1_IN_OFFSET     0x24
-#define GC_RBOX_CHECK_TERM_PD_KEY1_IN_LSB        0x9
-#define GC_RBOX_CHECK_TERM_PD_KEY1_IN_MASK       0x200
-#define GC_RBOX_CHECK_TERM_PD_KEY1_IN_SIZE       0x1
-#define GC_RBOX_CHECK_TERM_PD_KEY1_IN_DEFAULT    0x0
-#define GC_RBOX_CHECK_TERM_PD_KEY1_IN_OFFSET     0x24
-#define GC_RBOX_CHECK_TERM_PU_EC_RST_LSB         0xa
-#define GC_RBOX_CHECK_TERM_PU_EC_RST_MASK        0x400
-#define GC_RBOX_CHECK_TERM_PU_EC_RST_SIZE        0x1
-#define GC_RBOX_CHECK_TERM_PU_EC_RST_DEFAULT     0x0
-#define GC_RBOX_CHECK_TERM_PU_EC_RST_OFFSET      0x24
-#define GC_RBOX_CHECK_TERM_PD_EC_RST_LSB         0xb
-#define GC_RBOX_CHECK_TERM_PD_EC_RST_MASK        0x800
-#define GC_RBOX_CHECK_TERM_PD_EC_RST_SIZE        0x1
-#define GC_RBOX_CHECK_TERM_PD_EC_RST_DEFAULT     0x0
-#define GC_RBOX_CHECK_TERM_PD_EC_RST_OFFSET      0x24
-#define GC_RBOX_CHECK_TERM_PU_BATT_DISABLE_LSB   0xc
-#define GC_RBOX_CHECK_TERM_PU_BATT_DISABLE_MASK  0x1000
-#define GC_RBOX_CHECK_TERM_PU_BATT_DISABLE_SIZE  0x1
-#define GC_RBOX_CHECK_TERM_PU_BATT_DISABLE_DEFAULT 0x0
-#define GC_RBOX_CHECK_TERM_PU_BATT_DISABLE_OFFSET 0x24
-#define GC_RBOX_CHECK_TERM_PD_BATT_DISABLE_LSB   0xd
-#define GC_RBOX_CHECK_TERM_PD_BATT_DISABLE_MASK  0x2000
-#define GC_RBOX_CHECK_TERM_PD_BATT_DISABLE_SIZE  0x1
-#define GC_RBOX_CHECK_TERM_PD_BATT_DISABLE_DEFAULT 0x0
-#define GC_RBOX_CHECK_TERM_PD_BATT_DISABLE_OFFSET 0x24
-#define GC_RBOX_CHECK_TERM_PU_EC_IN_RW_LSB       0xe
-#define GC_RBOX_CHECK_TERM_PU_EC_IN_RW_MASK      0x4000
-#define GC_RBOX_CHECK_TERM_PU_EC_IN_RW_SIZE      0x1
-#define GC_RBOX_CHECK_TERM_PU_EC_IN_RW_DEFAULT   0x0
-#define GC_RBOX_CHECK_TERM_PU_EC_IN_RW_OFFSET    0x24
-#define GC_RBOX_CHECK_TERM_PD_EC_IN_RW_LSB       0xf
-#define GC_RBOX_CHECK_TERM_PD_EC_IN_RW_MASK      0x8000
-#define GC_RBOX_CHECK_TERM_PD_EC_IN_RW_SIZE      0x1
-#define GC_RBOX_CHECK_TERM_PD_EC_IN_RW_DEFAULT   0x0
-#define GC_RBOX_CHECK_TERM_PD_EC_IN_RW_OFFSET    0x24
-#define GC_RBOX_CHECK_TERM_PU_PWRB_OUT_LSB       0x10
-#define GC_RBOX_CHECK_TERM_PU_PWRB_OUT_MASK      0x10000
-#define GC_RBOX_CHECK_TERM_PU_PWRB_OUT_SIZE      0x1
-#define GC_RBOX_CHECK_TERM_PU_PWRB_OUT_DEFAULT   0x0
-#define GC_RBOX_CHECK_TERM_PU_PWRB_OUT_OFFSET    0x24
-#define GC_RBOX_CHECK_TERM_PD_PWRB_OUT_LSB       0x11
-#define GC_RBOX_CHECK_TERM_PD_PWRB_OUT_MASK      0x20000
-#define GC_RBOX_CHECK_TERM_PD_PWRB_OUT_SIZE      0x1
-#define GC_RBOX_CHECK_TERM_PD_PWRB_OUT_DEFAULT   0x0
-#define GC_RBOX_CHECK_TERM_PD_PWRB_OUT_OFFSET    0x24
-#define GC_RBOX_CHECK_TERM_PU_KEY0_OUT_LSB       0x12
-#define GC_RBOX_CHECK_TERM_PU_KEY0_OUT_MASK      0x40000
-#define GC_RBOX_CHECK_TERM_PU_KEY0_OUT_SIZE      0x1
-#define GC_RBOX_CHECK_TERM_PU_KEY0_OUT_DEFAULT   0x0
-#define GC_RBOX_CHECK_TERM_PU_KEY0_OUT_OFFSET    0x24
-#define GC_RBOX_CHECK_TERM_PD_KEY0_OUT_LSB       0x13
-#define GC_RBOX_CHECK_TERM_PD_KEY0_OUT_MASK      0x80000
-#define GC_RBOX_CHECK_TERM_PD_KEY0_OUT_SIZE      0x1
-#define GC_RBOX_CHECK_TERM_PD_KEY0_OUT_DEFAULT   0x0
-#define GC_RBOX_CHECK_TERM_PD_KEY0_OUT_OFFSET    0x24
-#define GC_RBOX_CHECK_TERM_PU_KEY1_OUT_LSB       0x14
-#define GC_RBOX_CHECK_TERM_PU_KEY1_OUT_MASK      0x100000
-#define GC_RBOX_CHECK_TERM_PU_KEY1_OUT_SIZE      0x1
-#define GC_RBOX_CHECK_TERM_PU_KEY1_OUT_DEFAULT   0x0
-#define GC_RBOX_CHECK_TERM_PU_KEY1_OUT_OFFSET    0x24
-#define GC_RBOX_CHECK_TERM_PD_KEY1_OUT_LSB       0x15
-#define GC_RBOX_CHECK_TERM_PD_KEY1_OUT_MASK      0x200000
-#define GC_RBOX_CHECK_TERM_PD_KEY1_OUT_SIZE      0x1
-#define GC_RBOX_CHECK_TERM_PD_KEY1_OUT_DEFAULT   0x0
-#define GC_RBOX_CHECK_TERM_PD_KEY1_OUT_OFFSET    0x24
-#define GC_RBOX_CHECK_TERM_PU_EC_WP_L_LSB        0x16
-#define GC_RBOX_CHECK_TERM_PU_EC_WP_L_MASK       0x400000
-#define GC_RBOX_CHECK_TERM_PU_EC_WP_L_SIZE       0x1
-#define GC_RBOX_CHECK_TERM_PU_EC_WP_L_DEFAULT    0x0
-#define GC_RBOX_CHECK_TERM_PU_EC_WP_L_OFFSET     0x24
-#define GC_RBOX_CHECK_TERM_PD_EC_WP_L_LSB        0x17
-#define GC_RBOX_CHECK_TERM_PD_EC_WP_L_MASK       0x800000
-#define GC_RBOX_CHECK_TERM_PD_EC_WP_L_SIZE       0x1
-#define GC_RBOX_CHECK_TERM_PD_EC_WP_L_DEFAULT    0x0
-#define GC_RBOX_CHECK_TERM_PD_EC_WP_L_OFFSET     0x24
-#define GC_RBOX_STATUS_FUSE_READY_LSB            0x0
-#define GC_RBOX_STATUS_FUSE_READY_MASK           0x1
-#define GC_RBOX_STATUS_FUSE_READY_SIZE           0x1
-#define GC_RBOX_STATUS_FUSE_READY_DEFAULT        0x0
-#define GC_RBOX_STATUS_FUSE_READY_OFFSET         0x28
-#define GC_RBOX_STATUS_DISABLE_FUSE_OVERRIDE_LSB 0x1
-#define GC_RBOX_STATUS_DISABLE_FUSE_OVERRIDE_MASK 0x2
-#define GC_RBOX_STATUS_DISABLE_FUSE_OVERRIDE_SIZE 0x1
-#define GC_RBOX_STATUS_DISABLE_FUSE_OVERRIDE_DEFAULT 0x0
-#define GC_RBOX_STATUS_DISABLE_FUSE_OVERRIDE_OFFSET 0x28
-#define GC_RBOX_STATUS_DISABLE_OUTPUT_OVERRIDE_LSB 0x2
-#define GC_RBOX_STATUS_DISABLE_OUTPUT_OVERRIDE_MASK 0x1fc
-#define GC_RBOX_STATUS_DISABLE_OUTPUT_OVERRIDE_SIZE 0x7
-#define GC_RBOX_STATUS_DISABLE_OUTPUT_OVERRIDE_DEFAULT 0x0
-#define GC_RBOX_STATUS_DISABLE_OUTPUT_OVERRIDE_OFFSET 0x28
-#define GC_RBOX_FUSE_CTRL_OVERRIDE_FUSE_LSB      0x0
-#define GC_RBOX_FUSE_CTRL_OVERRIDE_FUSE_MASK     0x1
-#define GC_RBOX_FUSE_CTRL_OVERRIDE_FUSE_SIZE     0x1
-#define GC_RBOX_FUSE_CTRL_OVERRIDE_FUSE_DEFAULT  0x0
-#define GC_RBOX_FUSE_CTRL_OVERRIDE_FUSE_OFFSET   0x2c
-#define GC_RBOX_FUSE_CTRL_OVERRIDE_FUSE_READY_LSB 0x1
-#define GC_RBOX_FUSE_CTRL_OVERRIDE_FUSE_READY_MASK 0x2
-#define GC_RBOX_FUSE_CTRL_OVERRIDE_FUSE_READY_SIZE 0x1
-#define GC_RBOX_FUSE_CTRL_OVERRIDE_FUSE_READY_DEFAULT 0x0
-#define GC_RBOX_FUSE_CTRL_OVERRIDE_FUSE_READY_OFFSET 0x2c
-#define GC_RBOX_FUSE_CTRL_USE_SILEGO_LSB         0x2
-#define GC_RBOX_FUSE_CTRL_USE_SILEGO_MASK        0x4
-#define GC_RBOX_FUSE_CTRL_USE_SILEGO_SIZE        0x1
-#define GC_RBOX_FUSE_CTRL_USE_SILEGO_DEFAULT     0x0
-#define GC_RBOX_FUSE_CTRL_USE_SILEGO_OFFSET      0x2c
-#define GC_RBOX_FUSE_CTRL_SILEGO_CHOICE_LSB      0x3
-#define GC_RBOX_FUSE_CTRL_SILEGO_CHOICE_MASK     0x8
-#define GC_RBOX_FUSE_CTRL_SILEGO_CHOICE_SIZE     0x1
-#define GC_RBOX_FUSE_CTRL_SILEGO_CHOICE_DEFAULT  0x0
-#define GC_RBOX_FUSE_CTRL_SILEGO_CHOICE_OFFSET   0x2c
-#define GC_RBOX_DEBUG_DEBOUNCE_PERIOD_LSB        0x0
-#define GC_RBOX_DEBUG_DEBOUNCE_PERIOD_MASK       0xffff
-#define GC_RBOX_DEBUG_DEBOUNCE_PERIOD_SIZE       0x10
-#define GC_RBOX_DEBUG_DEBOUNCE_PERIOD_DEFAULT    0x0
-#define GC_RBOX_DEBUG_DEBOUNCE_PERIOD_OFFSET     0x30
-#define GC_RBOX_DEBUG_DEBOUNCE_BYPASS_PWRB_LSB   0x10
-#define GC_RBOX_DEBUG_DEBOUNCE_BYPASS_PWRB_MASK  0x10000
-#define GC_RBOX_DEBUG_DEBOUNCE_BYPASS_PWRB_SIZE  0x1
-#define GC_RBOX_DEBUG_DEBOUNCE_BYPASS_PWRB_DEFAULT 0x1
-#define GC_RBOX_DEBUG_DEBOUNCE_BYPASS_PWRB_OFFSET 0x30
-#define GC_RBOX_DEBUG_DEBOUNCE_BYPASS_KEY0_LSB   0x11
-#define GC_RBOX_DEBUG_DEBOUNCE_BYPASS_KEY0_MASK  0x20000
-#define GC_RBOX_DEBUG_DEBOUNCE_BYPASS_KEY0_SIZE  0x1
-#define GC_RBOX_DEBUG_DEBOUNCE_BYPASS_KEY0_DEFAULT 0x1
-#define GC_RBOX_DEBUG_DEBOUNCE_BYPASS_KEY0_OFFSET 0x30
-#define GC_RBOX_DEBUG_DEBOUNCE_BYPASS_KEY1_LSB   0x12
-#define GC_RBOX_DEBUG_DEBOUNCE_BYPASS_KEY1_MASK  0x40000
-#define GC_RBOX_DEBUG_DEBOUNCE_BYPASS_KEY1_SIZE  0x1
-#define GC_RBOX_DEBUG_DEBOUNCE_BYPASS_KEY1_DEFAULT 0x1
-#define GC_RBOX_DEBUG_DEBOUNCE_BYPASS_KEY1_OFFSET 0x30
-#define GC_RBOX_DEBUG_KEY_COMBO0_VAL_LSB         0x0
-#define GC_RBOX_DEBUG_KEY_COMBO0_VAL_MASK        0xff
-#define GC_RBOX_DEBUG_KEY_COMBO0_VAL_SIZE        0x8
-#define GC_RBOX_DEBUG_KEY_COMBO0_VAL_DEFAULT     0xc0
-#define GC_RBOX_DEBUG_KEY_COMBO0_VAL_OFFSET      0x34
-#define GC_RBOX_DEBUG_KEY_COMBO0_HOLD_LSB        0x8
-#define GC_RBOX_DEBUG_KEY_COMBO0_HOLD_MASK       0xff00
-#define GC_RBOX_DEBUG_KEY_COMBO0_HOLD_SIZE       0x8
-#define GC_RBOX_DEBUG_KEY_COMBO0_HOLD_DEFAULT    0x0
-#define GC_RBOX_DEBUG_KEY_COMBO0_HOLD_OFFSET     0x34
-#define GC_RBOX_DEBUG_KEY_COMBO1_VAL_LSB         0x0
-#define GC_RBOX_DEBUG_KEY_COMBO1_VAL_MASK        0xff
-#define GC_RBOX_DEBUG_KEY_COMBO1_VAL_SIZE        0x8
-#define GC_RBOX_DEBUG_KEY_COMBO1_VAL_DEFAULT     0x0
-#define GC_RBOX_DEBUG_KEY_COMBO1_VAL_OFFSET      0x38
-#define GC_RBOX_DEBUG_KEY_COMBO1_HOLD_LSB        0x8
-#define GC_RBOX_DEBUG_KEY_COMBO1_HOLD_MASK       0xff00
-#define GC_RBOX_DEBUG_KEY_COMBO1_HOLD_SIZE       0x8
-#define GC_RBOX_DEBUG_KEY_COMBO1_HOLD_DEFAULT    0x0
-#define GC_RBOX_DEBUG_KEY_COMBO1_HOLD_OFFSET     0x38
-#define GC_RBOX_DEBUG_KEY_COMBO2_VAL_LSB         0x0
-#define GC_RBOX_DEBUG_KEY_COMBO2_VAL_MASK        0xff
-#define GC_RBOX_DEBUG_KEY_COMBO2_VAL_SIZE        0x8
-#define GC_RBOX_DEBUG_KEY_COMBO2_VAL_DEFAULT     0x0
-#define GC_RBOX_DEBUG_KEY_COMBO2_VAL_OFFSET      0x3c
-#define GC_RBOX_DEBUG_KEY_COMBO2_HOLD_LSB        0x8
-#define GC_RBOX_DEBUG_KEY_COMBO2_HOLD_MASK       0xff00
-#define GC_RBOX_DEBUG_KEY_COMBO2_HOLD_SIZE       0x8
-#define GC_RBOX_DEBUG_KEY_COMBO2_HOLD_DEFAULT    0x0
-#define GC_RBOX_DEBUG_KEY_COMBO2_HOLD_OFFSET     0x3c
-#define GC_RBOX_DEBUG_BLOCK_OUTPUT_KEY0_SEL_LSB  0x0
-#define GC_RBOX_DEBUG_BLOCK_OUTPUT_KEY0_SEL_MASK 0x1
-#define GC_RBOX_DEBUG_BLOCK_OUTPUT_KEY0_SEL_SIZE 0x1
-#define GC_RBOX_DEBUG_BLOCK_OUTPUT_KEY0_SEL_DEFAULT 0x0
-#define GC_RBOX_DEBUG_BLOCK_OUTPUT_KEY0_SEL_OFFSET 0x40
-#define GC_RBOX_DEBUG_BLOCK_OUTPUT_KEY1_SEL_LSB  0x1
-#define GC_RBOX_DEBUG_BLOCK_OUTPUT_KEY1_SEL_MASK 0x2
-#define GC_RBOX_DEBUG_BLOCK_OUTPUT_KEY1_SEL_SIZE 0x1
-#define GC_RBOX_DEBUG_BLOCK_OUTPUT_KEY1_SEL_DEFAULT 0x0
-#define GC_RBOX_DEBUG_BLOCK_OUTPUT_KEY1_SEL_OFFSET 0x40
-#define GC_RBOX_DEBUG_BLOCK_OUTPUT_KEY0_VAL_LSB  0x2
-#define GC_RBOX_DEBUG_BLOCK_OUTPUT_KEY0_VAL_MASK 0x4
-#define GC_RBOX_DEBUG_BLOCK_OUTPUT_KEY0_VAL_SIZE 0x1
-#define GC_RBOX_DEBUG_BLOCK_OUTPUT_KEY0_VAL_DEFAULT 0x0
-#define GC_RBOX_DEBUG_BLOCK_OUTPUT_KEY0_VAL_OFFSET 0x40
-#define GC_RBOX_DEBUG_BLOCK_OUTPUT_KEY1_VAL_LSB  0x3
-#define GC_RBOX_DEBUG_BLOCK_OUTPUT_KEY1_VAL_MASK 0x8
-#define GC_RBOX_DEBUG_BLOCK_OUTPUT_KEY1_VAL_SIZE 0x1
-#define GC_RBOX_DEBUG_BLOCK_OUTPUT_KEY1_VAL_DEFAULT 0x0
-#define GC_RBOX_DEBUG_BLOCK_OUTPUT_KEY1_VAL_OFFSET 0x40
-#define GC_RBOX_DEBUG_POL_AC_PRESENT_LSB         0x0
-#define GC_RBOX_DEBUG_POL_AC_PRESENT_MASK        0x1
-#define GC_RBOX_DEBUG_POL_AC_PRESENT_SIZE        0x1
-#define GC_RBOX_DEBUG_POL_AC_PRESENT_DEFAULT     0x1
-#define GC_RBOX_DEBUG_POL_AC_PRESENT_OFFSET      0x44
-#define GC_RBOX_DEBUG_POL_PWRB_IN_LSB            0x1
-#define GC_RBOX_DEBUG_POL_PWRB_IN_MASK           0x2
-#define GC_RBOX_DEBUG_POL_PWRB_IN_SIZE           0x1
-#define GC_RBOX_DEBUG_POL_PWRB_IN_DEFAULT        0x0
-#define GC_RBOX_DEBUG_POL_PWRB_IN_OFFSET         0x44
-#define GC_RBOX_DEBUG_POL_PWRB_OUT_LSB           0x2
-#define GC_RBOX_DEBUG_POL_PWRB_OUT_MASK          0x4
-#define GC_RBOX_DEBUG_POL_PWRB_OUT_SIZE          0x1
-#define GC_RBOX_DEBUG_POL_PWRB_OUT_DEFAULT       0x0
-#define GC_RBOX_DEBUG_POL_PWRB_OUT_OFFSET        0x44
-#define GC_RBOX_DEBUG_POL_KEY0_IN_LSB            0x3
-#define GC_RBOX_DEBUG_POL_KEY0_IN_MASK           0x8
-#define GC_RBOX_DEBUG_POL_KEY0_IN_SIZE           0x1
-#define GC_RBOX_DEBUG_POL_KEY0_IN_DEFAULT        0x0
-#define GC_RBOX_DEBUG_POL_KEY0_IN_OFFSET         0x44
-#define GC_RBOX_DEBUG_POL_KEY0_OUT_LSB           0x4
-#define GC_RBOX_DEBUG_POL_KEY0_OUT_MASK          0x10
-#define GC_RBOX_DEBUG_POL_KEY0_OUT_SIZE          0x1
-#define GC_RBOX_DEBUG_POL_KEY0_OUT_DEFAULT       0x0
-#define GC_RBOX_DEBUG_POL_KEY0_OUT_OFFSET        0x44
-#define GC_RBOX_DEBUG_POL_KEY1_IN_LSB            0x5
-#define GC_RBOX_DEBUG_POL_KEY1_IN_MASK           0x20
-#define GC_RBOX_DEBUG_POL_KEY1_IN_SIZE           0x1
-#define GC_RBOX_DEBUG_POL_KEY1_IN_DEFAULT        0x0
-#define GC_RBOX_DEBUG_POL_KEY1_IN_OFFSET         0x44
-#define GC_RBOX_DEBUG_POL_KEY1_OUT_LSB           0x6
-#define GC_RBOX_DEBUG_POL_KEY1_OUT_MASK          0x40
-#define GC_RBOX_DEBUG_POL_KEY1_OUT_SIZE          0x1
-#define GC_RBOX_DEBUG_POL_KEY1_OUT_DEFAULT       0x0
-#define GC_RBOX_DEBUG_POL_KEY1_OUT_OFFSET        0x44
-#define GC_RBOX_DEBUG_POL_EC_RST_LSB             0x7
-#define GC_RBOX_DEBUG_POL_EC_RST_MASK            0x80
-#define GC_RBOX_DEBUG_POL_EC_RST_SIZE            0x1
-#define GC_RBOX_DEBUG_POL_EC_RST_DEFAULT         0x0
-#define GC_RBOX_DEBUG_POL_EC_RST_OFFSET          0x44
-#define GC_RBOX_DEBUG_POL_BATT_DISABLE_LSB       0x8
-#define GC_RBOX_DEBUG_POL_BATT_DISABLE_MASK      0x100
-#define GC_RBOX_DEBUG_POL_BATT_DISABLE_SIZE      0x1
-#define GC_RBOX_DEBUG_POL_BATT_DISABLE_DEFAULT   0x0
-#define GC_RBOX_DEBUG_POL_BATT_DISABLE_OFFSET    0x44
-#define GC_RBOX_DEBUG_TERM_AC_PRESENT_LSB        0x0
-#define GC_RBOX_DEBUG_TERM_AC_PRESENT_MASK       0x3
-#define GC_RBOX_DEBUG_TERM_AC_PRESENT_SIZE       0x2
-#define GC_RBOX_DEBUG_TERM_AC_PRESENT_DEFAULT    0x0
-#define GC_RBOX_DEBUG_TERM_AC_PRESENT_OFFSET     0x48
-#define GC_RBOX_DEBUG_TERM_ENTERING_RW_LSB       0x2
-#define GC_RBOX_DEBUG_TERM_ENTERING_RW_MASK      0xc
-#define GC_RBOX_DEBUG_TERM_ENTERING_RW_SIZE      0x2
-#define GC_RBOX_DEBUG_TERM_ENTERING_RW_DEFAULT   0x0
-#define GC_RBOX_DEBUG_TERM_ENTERING_RW_OFFSET    0x48
-#define GC_RBOX_DEBUG_TERM_PWRB_IN_LSB           0x4
-#define GC_RBOX_DEBUG_TERM_PWRB_IN_MASK          0x30
-#define GC_RBOX_DEBUG_TERM_PWRB_IN_SIZE          0x2
-#define GC_RBOX_DEBUG_TERM_PWRB_IN_DEFAULT       0x0
-#define GC_RBOX_DEBUG_TERM_PWRB_IN_OFFSET        0x48
-#define GC_RBOX_DEBUG_TERM_PWRB_OUT_LSB          0x6
-#define GC_RBOX_DEBUG_TERM_PWRB_OUT_MASK         0xc0
-#define GC_RBOX_DEBUG_TERM_PWRB_OUT_SIZE         0x2
-#define GC_RBOX_DEBUG_TERM_PWRB_OUT_DEFAULT      0x0
-#define GC_RBOX_DEBUG_TERM_PWRB_OUT_OFFSET       0x48
-#define GC_RBOX_DEBUG_TERM_KEY0_IN_LSB           0x8
-#define GC_RBOX_DEBUG_TERM_KEY0_IN_MASK          0x300
-#define GC_RBOX_DEBUG_TERM_KEY0_IN_SIZE          0x2
-#define GC_RBOX_DEBUG_TERM_KEY0_IN_DEFAULT       0x0
-#define GC_RBOX_DEBUG_TERM_KEY0_IN_OFFSET        0x48
-#define GC_RBOX_DEBUG_TERM_KEY0_OUT_LSB          0xa
-#define GC_RBOX_DEBUG_TERM_KEY0_OUT_MASK         0xc00
-#define GC_RBOX_DEBUG_TERM_KEY0_OUT_SIZE         0x2
-#define GC_RBOX_DEBUG_TERM_KEY0_OUT_DEFAULT      0x0
-#define GC_RBOX_DEBUG_TERM_KEY0_OUT_OFFSET       0x48
-#define GC_RBOX_DEBUG_TERM_KEY1_IN_LSB           0xc
-#define GC_RBOX_DEBUG_TERM_KEY1_IN_MASK          0x3000
-#define GC_RBOX_DEBUG_TERM_KEY1_IN_SIZE          0x2
-#define GC_RBOX_DEBUG_TERM_KEY1_IN_DEFAULT       0x0
-#define GC_RBOX_DEBUG_TERM_KEY1_IN_OFFSET        0x48
-#define GC_RBOX_DEBUG_TERM_KEY1_OUT_LSB          0xe
-#define GC_RBOX_DEBUG_TERM_KEY1_OUT_MASK         0xc000
-#define GC_RBOX_DEBUG_TERM_KEY1_OUT_SIZE         0x2
-#define GC_RBOX_DEBUG_TERM_KEY1_OUT_DEFAULT      0x0
-#define GC_RBOX_DEBUG_TERM_KEY1_OUT_OFFSET       0x48
-#define GC_RBOX_DEBUG_DRIVE_PWRB_OUT_LSB         0x0
-#define GC_RBOX_DEBUG_DRIVE_PWRB_OUT_MASK        0x3
-#define GC_RBOX_DEBUG_DRIVE_PWRB_OUT_SIZE        0x2
-#define GC_RBOX_DEBUG_DRIVE_PWRB_OUT_DEFAULT     0x3
-#define GC_RBOX_DEBUG_DRIVE_PWRB_OUT_OFFSET      0x4c
-#define GC_RBOX_DEBUG_DRIVE_KEY0_OUT_LSB         0x2
-#define GC_RBOX_DEBUG_DRIVE_KEY0_OUT_MASK        0xc
-#define GC_RBOX_DEBUG_DRIVE_KEY0_OUT_SIZE        0x2
-#define GC_RBOX_DEBUG_DRIVE_KEY0_OUT_DEFAULT     0x3
-#define GC_RBOX_DEBUG_DRIVE_KEY0_OUT_OFFSET      0x4c
-#define GC_RBOX_DEBUG_DRIVE_KEY1_OUT_LSB         0x4
-#define GC_RBOX_DEBUG_DRIVE_KEY1_OUT_MASK        0x30
-#define GC_RBOX_DEBUG_DRIVE_KEY1_OUT_SIZE        0x2
-#define GC_RBOX_DEBUG_DRIVE_KEY1_OUT_DEFAULT     0x3
-#define GC_RBOX_DEBUG_DRIVE_KEY1_OUT_OFFSET      0x4c
-#define GC_RBOX_DEBUG_DRIVE_EC_RST_LSB           0x6
-#define GC_RBOX_DEBUG_DRIVE_EC_RST_MASK          0xc0
-#define GC_RBOX_DEBUG_DRIVE_EC_RST_SIZE          0x2
-#define GC_RBOX_DEBUG_DRIVE_EC_RST_DEFAULT       0x1
-#define GC_RBOX_DEBUG_DRIVE_EC_RST_OFFSET        0x4c
-#define GC_RBOX_DEBUG_DRIVE_BATT_DISABLE_LSB     0x8
-#define GC_RBOX_DEBUG_DRIVE_BATT_DISABLE_MASK    0x300
-#define GC_RBOX_DEBUG_DRIVE_BATT_DISABLE_SIZE    0x2
-#define GC_RBOX_DEBUG_DRIVE_BATT_DISABLE_DEFAULT 0x1
-#define GC_RBOX_DEBUG_DRIVE_BATT_DISABLE_OFFSET  0x4c
-#define GC_RBOX_CONFIG_DEBOUNCE_PERIOD_LSB       0x0
-#define GC_RBOX_CONFIG_DEBOUNCE_PERIOD_MASK      0xffff
-#define GC_RBOX_CONFIG_DEBOUNCE_PERIOD_SIZE      0x10
-#define GC_RBOX_CONFIG_DEBOUNCE_PERIOD_DEFAULT   0x0
-#define GC_RBOX_CONFIG_DEBOUNCE_PERIOD_OFFSET    0x6c
-#define GC_RBOX_CONFIG_DEBOUNCE_BYPASS_PWRB_LSB  0x10
-#define GC_RBOX_CONFIG_DEBOUNCE_BYPASS_PWRB_MASK 0x10000
-#define GC_RBOX_CONFIG_DEBOUNCE_BYPASS_PWRB_SIZE 0x1
-#define GC_RBOX_CONFIG_DEBOUNCE_BYPASS_PWRB_DEFAULT 0x0
-#define GC_RBOX_CONFIG_DEBOUNCE_BYPASS_PWRB_OFFSET 0x6c
-#define GC_RBOX_CONFIG_DEBOUNCE_BYPASS_KEY0_LSB  0x11
-#define GC_RBOX_CONFIG_DEBOUNCE_BYPASS_KEY0_MASK 0x20000
-#define GC_RBOX_CONFIG_DEBOUNCE_BYPASS_KEY0_SIZE 0x1
-#define GC_RBOX_CONFIG_DEBOUNCE_BYPASS_KEY0_DEFAULT 0x0
-#define GC_RBOX_CONFIG_DEBOUNCE_BYPASS_KEY0_OFFSET 0x6c
-#define GC_RBOX_CONFIG_DEBOUNCE_BYPASS_KEY1_LSB  0x12
-#define GC_RBOX_CONFIG_DEBOUNCE_BYPASS_KEY1_MASK 0x40000
-#define GC_RBOX_CONFIG_DEBOUNCE_BYPASS_KEY1_SIZE 0x1
-#define GC_RBOX_CONFIG_DEBOUNCE_BYPASS_KEY1_DEFAULT 0x0
-#define GC_RBOX_CONFIG_DEBOUNCE_BYPASS_KEY1_OFFSET 0x6c
-#define GC_RBOX_CONFIG_KEY_COMBO0_VAL_LSB        0x0
-#define GC_RBOX_CONFIG_KEY_COMBO0_VAL_MASK       0xff
-#define GC_RBOX_CONFIG_KEY_COMBO0_VAL_SIZE       0x8
-#define GC_RBOX_CONFIG_KEY_COMBO0_VAL_DEFAULT    0x0
-#define GC_RBOX_CONFIG_KEY_COMBO0_VAL_OFFSET     0x70
-#define GC_RBOX_CONFIG_KEY_COMBO0_HOLD_LSB       0x8
-#define GC_RBOX_CONFIG_KEY_COMBO0_HOLD_MASK      0xff00
-#define GC_RBOX_CONFIG_KEY_COMBO0_HOLD_SIZE      0x8
-#define GC_RBOX_CONFIG_KEY_COMBO0_HOLD_DEFAULT   0x0
-#define GC_RBOX_CONFIG_KEY_COMBO0_HOLD_OFFSET    0x70
-#define GC_RBOX_CONFIG_KEY_COMBO1_VAL_LSB        0x0
-#define GC_RBOX_CONFIG_KEY_COMBO1_VAL_MASK       0xff
-#define GC_RBOX_CONFIG_KEY_COMBO1_VAL_SIZE       0x8
-#define GC_RBOX_CONFIG_KEY_COMBO1_VAL_DEFAULT    0x0
-#define GC_RBOX_CONFIG_KEY_COMBO1_VAL_OFFSET     0x74
-#define GC_RBOX_CONFIG_KEY_COMBO1_HOLD_LSB       0x8
-#define GC_RBOX_CONFIG_KEY_COMBO1_HOLD_MASK      0xff00
-#define GC_RBOX_CONFIG_KEY_COMBO1_HOLD_SIZE      0x8
-#define GC_RBOX_CONFIG_KEY_COMBO1_HOLD_DEFAULT   0x0
-#define GC_RBOX_CONFIG_KEY_COMBO1_HOLD_OFFSET    0x74
-#define GC_RBOX_CONFIG_KEY_COMBO2_VAL_LSB        0x0
-#define GC_RBOX_CONFIG_KEY_COMBO2_VAL_MASK       0xff
-#define GC_RBOX_CONFIG_KEY_COMBO2_VAL_SIZE       0x8
-#define GC_RBOX_CONFIG_KEY_COMBO2_VAL_DEFAULT    0x0
-#define GC_RBOX_CONFIG_KEY_COMBO2_VAL_OFFSET     0x78
-#define GC_RBOX_CONFIG_KEY_COMBO2_HOLD_LSB       0x8
-#define GC_RBOX_CONFIG_KEY_COMBO2_HOLD_MASK      0xff00
-#define GC_RBOX_CONFIG_KEY_COMBO2_HOLD_SIZE      0x8
-#define GC_RBOX_CONFIG_KEY_COMBO2_HOLD_DEFAULT   0x0
-#define GC_RBOX_CONFIG_KEY_COMBO2_HOLD_OFFSET    0x78
-#define GC_RBOX_CONFIG_BLOCK_OUTPUT_KEY0_SEL_LSB 0x0
-#define GC_RBOX_CONFIG_BLOCK_OUTPUT_KEY0_SEL_MASK 0x1
-#define GC_RBOX_CONFIG_BLOCK_OUTPUT_KEY0_SEL_SIZE 0x1
-#define GC_RBOX_CONFIG_BLOCK_OUTPUT_KEY0_SEL_DEFAULT 0x0
-#define GC_RBOX_CONFIG_BLOCK_OUTPUT_KEY0_SEL_OFFSET 0x7c
-#define GC_RBOX_CONFIG_BLOCK_OUTPUT_KEY1_SEL_LSB 0x1
-#define GC_RBOX_CONFIG_BLOCK_OUTPUT_KEY1_SEL_MASK 0x2
-#define GC_RBOX_CONFIG_BLOCK_OUTPUT_KEY1_SEL_SIZE 0x1
-#define GC_RBOX_CONFIG_BLOCK_OUTPUT_KEY1_SEL_DEFAULT 0x0
-#define GC_RBOX_CONFIG_BLOCK_OUTPUT_KEY1_SEL_OFFSET 0x7c
-#define GC_RBOX_CONFIG_BLOCK_OUTPUT_KEY0_VAL_LSB 0x2
-#define GC_RBOX_CONFIG_BLOCK_OUTPUT_KEY0_VAL_MASK 0x4
-#define GC_RBOX_CONFIG_BLOCK_OUTPUT_KEY0_VAL_SIZE 0x1
-#define GC_RBOX_CONFIG_BLOCK_OUTPUT_KEY0_VAL_DEFAULT 0x0
-#define GC_RBOX_CONFIG_BLOCK_OUTPUT_KEY0_VAL_OFFSET 0x7c
-#define GC_RBOX_CONFIG_BLOCK_OUTPUT_KEY1_VAL_LSB 0x3
-#define GC_RBOX_CONFIG_BLOCK_OUTPUT_KEY1_VAL_MASK 0x8
-#define GC_RBOX_CONFIG_BLOCK_OUTPUT_KEY1_VAL_SIZE 0x1
-#define GC_RBOX_CONFIG_BLOCK_OUTPUT_KEY1_VAL_DEFAULT 0x0
-#define GC_RBOX_CONFIG_BLOCK_OUTPUT_KEY1_VAL_OFFSET 0x7c
-#define GC_RBOX_CONFIG_POL_AC_PRESENT_LSB        0x0
-#define GC_RBOX_CONFIG_POL_AC_PRESENT_MASK       0x1
-#define GC_RBOX_CONFIG_POL_AC_PRESENT_SIZE       0x1
-#define GC_RBOX_CONFIG_POL_AC_PRESENT_DEFAULT    0x1
-#define GC_RBOX_CONFIG_POL_AC_PRESENT_OFFSET     0x80
-#define GC_RBOX_CONFIG_POL_PWRB_IN_LSB           0x1
-#define GC_RBOX_CONFIG_POL_PWRB_IN_MASK          0x2
-#define GC_RBOX_CONFIG_POL_PWRB_IN_SIZE          0x1
-#define GC_RBOX_CONFIG_POL_PWRB_IN_DEFAULT       0x0
-#define GC_RBOX_CONFIG_POL_PWRB_IN_OFFSET        0x80
-#define GC_RBOX_CONFIG_POL_PWRB_OUT_LSB          0x2
-#define GC_RBOX_CONFIG_POL_PWRB_OUT_MASK         0x4
-#define GC_RBOX_CONFIG_POL_PWRB_OUT_SIZE         0x1
-#define GC_RBOX_CONFIG_POL_PWRB_OUT_DEFAULT      0x0
-#define GC_RBOX_CONFIG_POL_PWRB_OUT_OFFSET       0x80
-#define GC_RBOX_CONFIG_POL_KEY0_IN_LSB           0x3
-#define GC_RBOX_CONFIG_POL_KEY0_IN_MASK          0x8
-#define GC_RBOX_CONFIG_POL_KEY0_IN_SIZE          0x1
-#define GC_RBOX_CONFIG_POL_KEY0_IN_DEFAULT       0x0
-#define GC_RBOX_CONFIG_POL_KEY0_IN_OFFSET        0x80
-#define GC_RBOX_CONFIG_POL_KEY0_OUT_LSB          0x4
-#define GC_RBOX_CONFIG_POL_KEY0_OUT_MASK         0x10
-#define GC_RBOX_CONFIG_POL_KEY0_OUT_SIZE         0x1
-#define GC_RBOX_CONFIG_POL_KEY0_OUT_DEFAULT      0x0
-#define GC_RBOX_CONFIG_POL_KEY0_OUT_OFFSET       0x80
-#define GC_RBOX_CONFIG_POL_KEY1_IN_LSB           0x5
-#define GC_RBOX_CONFIG_POL_KEY1_IN_MASK          0x20
-#define GC_RBOX_CONFIG_POL_KEY1_IN_SIZE          0x1
-#define GC_RBOX_CONFIG_POL_KEY1_IN_DEFAULT       0x0
-#define GC_RBOX_CONFIG_POL_KEY1_IN_OFFSET        0x80
-#define GC_RBOX_CONFIG_POL_KEY1_OUT_LSB          0x6
-#define GC_RBOX_CONFIG_POL_KEY1_OUT_MASK         0x40
-#define GC_RBOX_CONFIG_POL_KEY1_OUT_SIZE         0x1
-#define GC_RBOX_CONFIG_POL_KEY1_OUT_DEFAULT      0x0
-#define GC_RBOX_CONFIG_POL_KEY1_OUT_OFFSET       0x80
-#define GC_RBOX_CONFIG_POL_EC_RST_LSB            0x7
-#define GC_RBOX_CONFIG_POL_EC_RST_MASK           0x80
-#define GC_RBOX_CONFIG_POL_EC_RST_SIZE           0x1
-#define GC_RBOX_CONFIG_POL_EC_RST_DEFAULT        0x0
-#define GC_RBOX_CONFIG_POL_EC_RST_OFFSET         0x80
-#define GC_RBOX_CONFIG_POL_BATT_DISABLE_LSB      0x8
-#define GC_RBOX_CONFIG_POL_BATT_DISABLE_MASK     0x100
-#define GC_RBOX_CONFIG_POL_BATT_DISABLE_SIZE     0x1
-#define GC_RBOX_CONFIG_POL_BATT_DISABLE_DEFAULT  0x0
-#define GC_RBOX_CONFIG_POL_BATT_DISABLE_OFFSET   0x80
-#define GC_RBOX_CONFIG_TERM_AC_PRESENT_LSB       0x0
-#define GC_RBOX_CONFIG_TERM_AC_PRESENT_MASK      0x3
-#define GC_RBOX_CONFIG_TERM_AC_PRESENT_SIZE      0x2
-#define GC_RBOX_CONFIG_TERM_AC_PRESENT_DEFAULT   0x0
-#define GC_RBOX_CONFIG_TERM_AC_PRESENT_OFFSET    0x84
-#define GC_RBOX_CONFIG_TERM_ENTERING_RW_LSB      0x2
-#define GC_RBOX_CONFIG_TERM_ENTERING_RW_MASK     0xc
-#define GC_RBOX_CONFIG_TERM_ENTERING_RW_SIZE     0x2
-#define GC_RBOX_CONFIG_TERM_ENTERING_RW_DEFAULT  0x0
-#define GC_RBOX_CONFIG_TERM_ENTERING_RW_OFFSET   0x84
-#define GC_RBOX_CONFIG_TERM_PWRB_IN_LSB          0x4
-#define GC_RBOX_CONFIG_TERM_PWRB_IN_MASK         0x30
-#define GC_RBOX_CONFIG_TERM_PWRB_IN_SIZE         0x2
-#define GC_RBOX_CONFIG_TERM_PWRB_IN_DEFAULT      0x0
-#define GC_RBOX_CONFIG_TERM_PWRB_IN_OFFSET       0x84
-#define GC_RBOX_CONFIG_TERM_PWRB_OUT_LSB         0x6
-#define GC_RBOX_CONFIG_TERM_PWRB_OUT_MASK        0xc0
-#define GC_RBOX_CONFIG_TERM_PWRB_OUT_SIZE        0x2
-#define GC_RBOX_CONFIG_TERM_PWRB_OUT_DEFAULT     0x0
-#define GC_RBOX_CONFIG_TERM_PWRB_OUT_OFFSET      0x84
-#define GC_RBOX_CONFIG_TERM_KEY0_IN_LSB          0x8
-#define GC_RBOX_CONFIG_TERM_KEY0_IN_MASK         0x300
-#define GC_RBOX_CONFIG_TERM_KEY0_IN_SIZE         0x2
-#define GC_RBOX_CONFIG_TERM_KEY0_IN_DEFAULT      0x0
-#define GC_RBOX_CONFIG_TERM_KEY0_IN_OFFSET       0x84
-#define GC_RBOX_CONFIG_TERM_KEY0_OUT_LSB         0xa
-#define GC_RBOX_CONFIG_TERM_KEY0_OUT_MASK        0xc00
-#define GC_RBOX_CONFIG_TERM_KEY0_OUT_SIZE        0x2
-#define GC_RBOX_CONFIG_TERM_KEY0_OUT_DEFAULT     0x0
-#define GC_RBOX_CONFIG_TERM_KEY0_OUT_OFFSET      0x84
-#define GC_RBOX_CONFIG_TERM_KEY1_IN_LSB          0xc
-#define GC_RBOX_CONFIG_TERM_KEY1_IN_MASK         0x3000
-#define GC_RBOX_CONFIG_TERM_KEY1_IN_SIZE         0x2
-#define GC_RBOX_CONFIG_TERM_KEY1_IN_DEFAULT      0x0
-#define GC_RBOX_CONFIG_TERM_KEY1_IN_OFFSET       0x84
-#define GC_RBOX_CONFIG_TERM_KEY1_OUT_LSB         0xe
-#define GC_RBOX_CONFIG_TERM_KEY1_OUT_MASK        0xc000
-#define GC_RBOX_CONFIG_TERM_KEY1_OUT_SIZE        0x2
-#define GC_RBOX_CONFIG_TERM_KEY1_OUT_DEFAULT     0x0
-#define GC_RBOX_CONFIG_TERM_KEY1_OUT_OFFSET      0x84
-#define GC_RBOX_CONFIG_DRIVE_PWRB_OUT_LSB        0x0
-#define GC_RBOX_CONFIG_DRIVE_PWRB_OUT_MASK       0x3
-#define GC_RBOX_CONFIG_DRIVE_PWRB_OUT_SIZE       0x2
-#define GC_RBOX_CONFIG_DRIVE_PWRB_OUT_DEFAULT    0x0
-#define GC_RBOX_CONFIG_DRIVE_PWRB_OUT_OFFSET     0x88
-#define GC_RBOX_CONFIG_DRIVE_KEY0_OUT_LSB        0x2
-#define GC_RBOX_CONFIG_DRIVE_KEY0_OUT_MASK       0xc
-#define GC_RBOX_CONFIG_DRIVE_KEY0_OUT_SIZE       0x2
-#define GC_RBOX_CONFIG_DRIVE_KEY0_OUT_DEFAULT    0x0
-#define GC_RBOX_CONFIG_DRIVE_KEY0_OUT_OFFSET     0x88
-#define GC_RBOX_CONFIG_DRIVE_KEY1_OUT_LSB        0x4
-#define GC_RBOX_CONFIG_DRIVE_KEY1_OUT_MASK       0x30
-#define GC_RBOX_CONFIG_DRIVE_KEY1_OUT_SIZE       0x2
-#define GC_RBOX_CONFIG_DRIVE_KEY1_OUT_DEFAULT    0x0
-#define GC_RBOX_CONFIG_DRIVE_KEY1_OUT_OFFSET     0x88
-#define GC_RBOX_CONFIG_DRIVE_EC_RST_LSB          0x6
-#define GC_RBOX_CONFIG_DRIVE_EC_RST_MASK         0xc0
-#define GC_RBOX_CONFIG_DRIVE_EC_RST_SIZE         0x2
-#define GC_RBOX_CONFIG_DRIVE_EC_RST_DEFAULT      0x0
-#define GC_RBOX_CONFIG_DRIVE_EC_RST_OFFSET       0x88
-#define GC_RBOX_CONFIG_DRIVE_BATT_DISABLE_LSB    0x8
-#define GC_RBOX_CONFIG_DRIVE_BATT_DISABLE_MASK   0x300
-#define GC_RBOX_CONFIG_DRIVE_BATT_DISABLE_SIZE   0x2
-#define GC_RBOX_CONFIG_DRIVE_BATT_DISABLE_DEFAULT 0x0
-#define GC_RBOX_CONFIG_DRIVE_BATT_DISABLE_OFFSET 0x88
-#define GC_RBOX_WAKEUP_ENABLE_LSB                0x0
-#define GC_RBOX_WAKEUP_ENABLE_MASK               0x1
-#define GC_RBOX_WAKEUP_ENABLE_SIZE               0x1
-#define GC_RBOX_WAKEUP_ENABLE_DEFAULT            0x0
-#define GC_RBOX_WAKEUP_ENABLE_OFFSET             0x98
-#define GC_RBOX_WAKEUP_CLEAR_LSB                 0x1
-#define GC_RBOX_WAKEUP_CLEAR_MASK                0x2
-#define GC_RBOX_WAKEUP_CLEAR_SIZE                0x1
-#define GC_RBOX_WAKEUP_CLEAR_DEFAULT             0x0
-#define GC_RBOX_WAKEUP_CLEAR_OFFSET              0x98
-#define GC_RBOX_WAKEUP_MASK_LSB                  0x2
-#define GC_RBOX_WAKEUP_MASK_MASK                 0x4
-#define GC_RBOX_WAKEUP_MASK_SIZE                 0x1
-#define GC_RBOX_WAKEUP_MASK_DEFAULT              0x0
-#define GC_RBOX_WAKEUP_MASK_OFFSET               0x98
-#define GC_RBOX_WAKEUP_INTR_AC_PRESENT_RED_LSB   0x0
-#define GC_RBOX_WAKEUP_INTR_AC_PRESENT_RED_MASK  0x1
-#define GC_RBOX_WAKEUP_INTR_AC_PRESENT_RED_SIZE  0x1
-#define GC_RBOX_WAKEUP_INTR_AC_PRESENT_RED_DEFAULT 0x0
-#define GC_RBOX_WAKEUP_INTR_AC_PRESENT_RED_OFFSET 0x9c
-#define GC_RBOX_WAKEUP_INTR_AC_PRESENT_FED_LSB   0x1
-#define GC_RBOX_WAKEUP_INTR_AC_PRESENT_FED_MASK  0x2
-#define GC_RBOX_WAKEUP_INTR_AC_PRESENT_FED_SIZE  0x1
-#define GC_RBOX_WAKEUP_INTR_AC_PRESENT_FED_DEFAULT 0x0
-#define GC_RBOX_WAKEUP_INTR_AC_PRESENT_FED_OFFSET 0x9c
-#define GC_RBOX_WAKEUP_INTR_ENTERING_RW_RED_LSB  0x2
-#define GC_RBOX_WAKEUP_INTR_ENTERING_RW_RED_MASK 0x4
-#define GC_RBOX_WAKEUP_INTR_ENTERING_RW_RED_SIZE 0x1
-#define GC_RBOX_WAKEUP_INTR_ENTERING_RW_RED_DEFAULT 0x0
-#define GC_RBOX_WAKEUP_INTR_ENTERING_RW_RED_OFFSET 0x9c
-#define GC_RBOX_WAKEUP_INTR_ENTERING_RW_FED_LSB  0x3
-#define GC_RBOX_WAKEUP_INTR_ENTERING_RW_FED_MASK 0x8
-#define GC_RBOX_WAKEUP_INTR_ENTERING_RW_FED_SIZE 0x1
-#define GC_RBOX_WAKEUP_INTR_ENTERING_RW_FED_DEFAULT 0x0
-#define GC_RBOX_WAKEUP_INTR_ENTERING_RW_FED_OFFSET 0x9c
-#define GC_RBOX_WAKEUP_INTR_PWRB_IN_RED_LSB      0x4
-#define GC_RBOX_WAKEUP_INTR_PWRB_IN_RED_MASK     0x10
-#define GC_RBOX_WAKEUP_INTR_PWRB_IN_RED_SIZE     0x1
-#define GC_RBOX_WAKEUP_INTR_PWRB_IN_RED_DEFAULT  0x0
-#define GC_RBOX_WAKEUP_INTR_PWRB_IN_RED_OFFSET   0x9c
-#define GC_RBOX_WAKEUP_INTR_PWRB_IN_FED_LSB      0x5
-#define GC_RBOX_WAKEUP_INTR_PWRB_IN_FED_MASK     0x20
-#define GC_RBOX_WAKEUP_INTR_PWRB_IN_FED_SIZE     0x1
-#define GC_RBOX_WAKEUP_INTR_PWRB_IN_FED_DEFAULT  0x0
-#define GC_RBOX_WAKEUP_INTR_PWRB_IN_FED_OFFSET   0x9c
-#define GC_RBOX_WAKEUP_INTR_KEY0_IN_RED_LSB      0x6
-#define GC_RBOX_WAKEUP_INTR_KEY0_IN_RED_MASK     0x40
-#define GC_RBOX_WAKEUP_INTR_KEY0_IN_RED_SIZE     0x1
-#define GC_RBOX_WAKEUP_INTR_KEY0_IN_RED_DEFAULT  0x0
-#define GC_RBOX_WAKEUP_INTR_KEY0_IN_RED_OFFSET   0x9c
-#define GC_RBOX_WAKEUP_INTR_KEY0_IN_FED_LSB      0x7
-#define GC_RBOX_WAKEUP_INTR_KEY0_IN_FED_MASK     0x80
-#define GC_RBOX_WAKEUP_INTR_KEY0_IN_FED_SIZE     0x1
-#define GC_RBOX_WAKEUP_INTR_KEY0_IN_FED_DEFAULT  0x0
-#define GC_RBOX_WAKEUP_INTR_KEY0_IN_FED_OFFSET   0x9c
-#define GC_RBOX_WAKEUP_INTR_KEY1_IN_RED_LSB      0x8
-#define GC_RBOX_WAKEUP_INTR_KEY1_IN_RED_MASK     0x100
-#define GC_RBOX_WAKEUP_INTR_KEY1_IN_RED_SIZE     0x1
-#define GC_RBOX_WAKEUP_INTR_KEY1_IN_RED_DEFAULT  0x0
-#define GC_RBOX_WAKEUP_INTR_KEY1_IN_RED_OFFSET   0x9c
-#define GC_RBOX_WAKEUP_INTR_KEY1_IN_FED_LSB      0x9
-#define GC_RBOX_WAKEUP_INTR_KEY1_IN_FED_MASK     0x200
-#define GC_RBOX_WAKEUP_INTR_KEY1_IN_FED_SIZE     0x1
-#define GC_RBOX_WAKEUP_INTR_KEY1_IN_FED_DEFAULT  0x0
-#define GC_RBOX_WAKEUP_INTR_KEY1_IN_FED_OFFSET   0x9c
-#define GC_RBOX_WAKEUP_INTR_EC_RST_RED_LSB       0xa
-#define GC_RBOX_WAKEUP_INTR_EC_RST_RED_MASK      0x400
-#define GC_RBOX_WAKEUP_INTR_EC_RST_RED_SIZE      0x1
-#define GC_RBOX_WAKEUP_INTR_EC_RST_RED_DEFAULT   0x0
-#define GC_RBOX_WAKEUP_INTR_EC_RST_RED_OFFSET    0x9c
-#define GC_RBOX_WAKEUP_INTR_EC_RST_FED_LSB       0xb
-#define GC_RBOX_WAKEUP_INTR_EC_RST_FED_MASK      0x800
-#define GC_RBOX_WAKEUP_INTR_EC_RST_FED_SIZE      0x1
-#define GC_RBOX_WAKEUP_INTR_EC_RST_FED_DEFAULT   0x0
-#define GC_RBOX_WAKEUP_INTR_EC_RST_FED_OFFSET    0x9c
-#define GC_RBOX_WAKEUP_INTR_BUTTON_COMBO0_RDY_LSB 0xc
-#define GC_RBOX_WAKEUP_INTR_BUTTON_COMBO0_RDY_MASK 0x1000
-#define GC_RBOX_WAKEUP_INTR_BUTTON_COMBO0_RDY_SIZE 0x1
-#define GC_RBOX_WAKEUP_INTR_BUTTON_COMBO0_RDY_DEFAULT 0x0
-#define GC_RBOX_WAKEUP_INTR_BUTTON_COMBO0_RDY_OFFSET 0x9c
-#define GC_RBOX_WAKEUP_INTR_BUTTON_COMBO1_RDY_LSB 0xd
-#define GC_RBOX_WAKEUP_INTR_BUTTON_COMBO1_RDY_MASK 0x2000
-#define GC_RBOX_WAKEUP_INTR_BUTTON_COMBO1_RDY_SIZE 0x1
-#define GC_RBOX_WAKEUP_INTR_BUTTON_COMBO1_RDY_DEFAULT 0x0
-#define GC_RBOX_WAKEUP_INTR_BUTTON_COMBO1_RDY_OFFSET 0x9c
-#define GC_RBOX_WAKEUP_INTR_BUTTON_COMBO2_RDY_LSB 0xe
-#define GC_RBOX_WAKEUP_INTR_BUTTON_COMBO2_RDY_MASK 0x4000
-#define GC_RBOX_WAKEUP_INTR_BUTTON_COMBO2_RDY_SIZE 0x1
-#define GC_RBOX_WAKEUP_INTR_BUTTON_COMBO2_RDY_DEFAULT 0x0
-#define GC_RBOX_WAKEUP_INTR_BUTTON_COMBO2_RDY_OFFSET 0x9c
-#define GC_RBOX_VERSION_CHANGE_LSB               0x0
-#define GC_RBOX_VERSION_CHANGE_MASK              0xffffff
-#define GC_RBOX_VERSION_CHANGE_SIZE              0x18
-#define GC_RBOX_VERSION_CHANGE_DEFAULT           0x14125
-#define GC_RBOX_VERSION_CHANGE_OFFSET            0xa0
-#define GC_RBOX_VERSION_REVISION_LSB             0x18
-#define GC_RBOX_VERSION_REVISION_MASK            0xff000000
-#define GC_RBOX_VERSION_REVISION_SIZE            0x8
-#define GC_RBOX_VERSION_REVISION_DEFAULT         0x1
-#define GC_RBOX_VERSION_REVISION_OFFSET          0xa0
-#define GC_RDD_VERSION_CHANGE_LSB                0x0
-#define GC_RDD_VERSION_CHANGE_MASK               0xffffff
-#define GC_RDD_VERSION_CHANGE_SIZE               0x18
-#define GC_RDD_VERSION_CHANGE_DEFAULT            0x11f09
-#define GC_RDD_VERSION_CHANGE_OFFSET             0x0
-#define GC_RDD_VERSION_REVISION_LSB              0x18
-#define GC_RDD_VERSION_REVISION_MASK             0xff000000
-#define GC_RDD_VERSION_REVISION_SIZE             0x8
-#define GC_RDD_VERSION_REVISION_DEFAULT          0x24
-#define GC_RDD_VERSION_REVISION_OFFSET           0x0
-#define GC_RDD_INT_ENABLE_INTR_DEBUG_STATE_DETECTED_LSB 0x0
-#define GC_RDD_INT_ENABLE_INTR_DEBUG_STATE_DETECTED_MASK 0x1
-#define GC_RDD_INT_ENABLE_INTR_DEBUG_STATE_DETECTED_SIZE 0x1
-#define GC_RDD_INT_ENABLE_INTR_DEBUG_STATE_DETECTED_DEFAULT 0x0
-#define GC_RDD_INT_ENABLE_INTR_DEBUG_STATE_DETECTED_OFFSET 0x4
-#define GC_RDD_INT_STATE_INTR_DEBUG_STATE_DETECTED_LSB 0x0
-#define GC_RDD_INT_STATE_INTR_DEBUG_STATE_DETECTED_MASK 0x1
-#define GC_RDD_INT_STATE_INTR_DEBUG_STATE_DETECTED_SIZE 0x1
-#define GC_RDD_INT_STATE_INTR_DEBUG_STATE_DETECTED_DEFAULT 0x0
-#define GC_RDD_INT_STATE_INTR_DEBUG_STATE_DETECTED_OFFSET 0x8
-#define GC_RDD_INT_TEST_INTR_DEBUG_STATE_DETECTED_LSB 0x0
-#define GC_RDD_INT_TEST_INTR_DEBUG_STATE_DETECTED_MASK 0x1
-#define GC_RDD_INT_TEST_INTR_DEBUG_STATE_DETECTED_SIZE 0x1
-#define GC_RDD_INT_TEST_INTR_DEBUG_STATE_DETECTED_DEFAULT 0x0
-#define GC_RDD_INT_TEST_INTR_DEBUG_STATE_DETECTED_OFFSET 0xc
-#define GC_RDD_ANTEST_EN_LSB                     0x0
-#define GC_RDD_ANTEST_EN_MASK                    0x1
-#define GC_RDD_ANTEST_EN_SIZE                    0x1
-#define GC_RDD_ANTEST_EN_DEFAULT                 0x0
-#define GC_RDD_ANTEST_EN_OFFSET                  0x14
-#define GC_RDD_REF_ADJ_LVL0P2V_LSB               0x0
-#define GC_RDD_REF_ADJ_LVL0P2V_MASK              0x3
-#define GC_RDD_REF_ADJ_LVL0P2V_SIZE              0x2
-#define GC_RDD_REF_ADJ_LVL0P2V_DEFAULT           0x1
-#define GC_RDD_REF_ADJ_LVL0P2V_OFFSET            0x20
-#define GC_RDD_REF_ADJ_LVL0P4V_LSB               0x2
-#define GC_RDD_REF_ADJ_LVL0P4V_MASK              0xc
-#define GC_RDD_REF_ADJ_LVL0P4V_SIZE              0x2
-#define GC_RDD_REF_ADJ_LVL0P4V_DEFAULT           0x1
-#define GC_RDD_REF_ADJ_LVL0P4V_OFFSET            0x20
-#define GC_RDD_REF_ADJ_LVL2P0V_LSB               0x4
-#define GC_RDD_REF_ADJ_LVL2P0V_MASK              0x30
-#define GC_RDD_REF_ADJ_LVL2P0V_SIZE              0x2
-#define GC_RDD_REF_ADJ_LVL2P0V_DEFAULT           0x1
-#define GC_RDD_REF_ADJ_LVL2P0V_OFFSET            0x20
-#define GC_RDD_INPUT_PIN_VALUES_CC1_LSB          0x0
-#define GC_RDD_INPUT_PIN_VALUES_CC1_MASK         0x7
-#define GC_RDD_INPUT_PIN_VALUES_CC1_SIZE         0x3
-#define GC_RDD_INPUT_PIN_VALUES_CC1_DEFAULT      0x0
-#define GC_RDD_INPUT_PIN_VALUES_CC1_OFFSET       0x24
-#define GC_RDD_INPUT_PIN_VALUES_CC2_LSB          0x3
-#define GC_RDD_INPUT_PIN_VALUES_CC2_MASK         0x38
-#define GC_RDD_INPUT_PIN_VALUES_CC2_SIZE         0x3
-#define GC_RDD_INPUT_PIN_VALUES_CC2_DEFAULT      0x3
-#define GC_RDD_INPUT_PIN_VALUES_CC2_OFFSET       0x24
-#define GC_RDD_CUR_STABLE_STATE_DEBUG_LSB        0x0
-#define GC_RDD_CUR_STABLE_STATE_DEBUG_MASK       0x1
-#define GC_RDD_CUR_STABLE_STATE_DEBUG_SIZE       0x1
-#define GC_RDD_CUR_STABLE_STATE_DEBUG_DEFAULT    0x0
-#define GC_RDD_CUR_STABLE_STATE_DEBUG_OFFSET     0x2c
-#define GC_RDD_CUR_STABLE_STATE_INVALID_LSB      0x1
-#define GC_RDD_CUR_STABLE_STATE_INVALID_MASK     0x2
-#define GC_RDD_CUR_STABLE_STATE_INVALID_SIZE     0x1
-#define GC_RDD_CUR_STABLE_STATE_INVALID_DEFAULT  0x1
-#define GC_RDD_CUR_STABLE_STATE_INVALID_OFFSET   0x2c
-#define GC_RTC_CTRL_X_RTC_RC_CTRL_LSB            0x0
-#define GC_RTC_CTRL_X_RTC_RC_CTRL_MASK           0xff
-#define GC_RTC_CTRL_X_RTC_RC_CTRL_SIZE           0x8
-#define GC_RTC_CTRL_X_RTC_RC_CTRL_DEFAULT        0x0
-#define GC_RTC_CTRL_X_RTC_RC_CTRL_OFFSET         0x0
-#define GC_RTC_PULSE_STRETCH_CNT_LSB             0x0
-#define GC_RTC_PULSE_STRETCH_CNT_MASK            0xffff
-#define GC_RTC_PULSE_STRETCH_CNT_SIZE            0x10
-#define GC_RTC_PULSE_STRETCH_CNT_DEFAULT         0x0
-#define GC_RTC_PULSE_STRETCH_CNT_OFFSET          0x8
-#define GC_RTC_PULSE_STRETCH_EN_LSB              0x10
-#define GC_RTC_PULSE_STRETCH_EN_MASK             0x10000
-#define GC_RTC_PULSE_STRETCH_EN_SIZE             0x1
-#define GC_RTC_PULSE_STRETCH_EN_DEFAULT          0x0
-#define GC_RTC_PULSE_STRETCH_EN_OFFSET           0x8
-#define GC_RTC_SW_TRIM_COUNTER_VALUE_LSB         0x0
-#define GC_RTC_SW_TRIM_COUNTER_VALUE_MASK        0xffffff
-#define GC_RTC_SW_TRIM_COUNTER_VALUE_SIZE        0x18
-#define GC_RTC_SW_TRIM_COUNTER_VALUE_DEFAULT     0x0
-#define GC_RTC_SW_TRIM_COUNTER_VALUE_OFFSET      0x10
-#define GC_RTC_SW_TRIM_COUNTER_DONE_LSB          0x18
-#define GC_RTC_SW_TRIM_COUNTER_DONE_MASK         0x1000000
-#define GC_RTC_SW_TRIM_COUNTER_DONE_SIZE         0x1
-#define GC_RTC_SW_TRIM_COUNTER_DONE_DEFAULT      0x0
-#define GC_RTC_SW_TRIM_COUNTER_DONE_OFFSET       0x10
-#define GC_SPI_CTRL_CPOL_LSB                     0x0
-#define GC_SPI_CTRL_CPOL_MASK                    0x1
-#define GC_SPI_CTRL_CPOL_SIZE                    0x1
-#define GC_SPI_CTRL_CPOL_DEFAULT                 0x0
-#define GC_SPI_CTRL_CPOL_OFFSET                  0x0
-#define GC_SPI_CTRL_CPHA_LSB                     0x1
-#define GC_SPI_CTRL_CPHA_MASK                    0x2
-#define GC_SPI_CTRL_CPHA_SIZE                    0x1
-#define GC_SPI_CTRL_CPHA_DEFAULT                 0x0
-#define GC_SPI_CTRL_CPHA_OFFSET                  0x0
-#define GC_SPI_CTRL_CSBSU_LSB                    0x2
-#define GC_SPI_CTRL_CSBSU_MASK                   0x3c
-#define GC_SPI_CTRL_CSBSU_SIZE                   0x4
-#define GC_SPI_CTRL_CSBSU_DEFAULT                0x0
-#define GC_SPI_CTRL_CSBSU_OFFSET                 0x0
-#define GC_SPI_CTRL_CSBHLD_LSB                   0x6
-#define GC_SPI_CTRL_CSBHLD_MASK                  0x3c0
-#define GC_SPI_CTRL_CSBHLD_SIZE                  0x4
-#define GC_SPI_CTRL_CSBHLD_DEFAULT               0x0
-#define GC_SPI_CTRL_CSBHLD_OFFSET                0x0
-#define GC_SPI_CTRL_IDIV_LSB                     0xa
-#define GC_SPI_CTRL_IDIV_MASK                    0x3ffc00
-#define GC_SPI_CTRL_IDIV_SIZE                    0xc
-#define GC_SPI_CTRL_IDIV_DEFAULT                 0x2
-#define GC_SPI_CTRL_IDIV_OFFSET                  0x0
-#define GC_SPI_CTRL_CSBPOL_LSB                   0x16
-#define GC_SPI_CTRL_CSBPOL_MASK                  0x400000
-#define GC_SPI_CTRL_CSBPOL_SIZE                  0x1
-#define GC_SPI_CTRL_CSBPOL_DEFAULT               0x0
-#define GC_SPI_CTRL_CSBPOL_OFFSET                0x0
-#define GC_SPI_CTRL_TXBITOR_LSB                  0x17
-#define GC_SPI_CTRL_TXBITOR_MASK                 0x800000
-#define GC_SPI_CTRL_TXBITOR_SIZE                 0x1
-#define GC_SPI_CTRL_TXBITOR_DEFAULT              0x1
-#define GC_SPI_CTRL_TXBITOR_OFFSET               0x0
-#define GC_SPI_CTRL_TXBYTOR_LSB                  0x18
-#define GC_SPI_CTRL_TXBYTOR_MASK                 0x1000000
-#define GC_SPI_CTRL_TXBYTOR_SIZE                 0x1
-#define GC_SPI_CTRL_TXBYTOR_DEFAULT              0x0
-#define GC_SPI_CTRL_TXBYTOR_OFFSET               0x0
-#define GC_SPI_CTRL_RXBITOR_LSB                  0x19
-#define GC_SPI_CTRL_RXBITOR_MASK                 0x2000000
-#define GC_SPI_CTRL_RXBITOR_SIZE                 0x1
-#define GC_SPI_CTRL_RXBITOR_DEFAULT              0x1
-#define GC_SPI_CTRL_RXBITOR_OFFSET               0x0
-#define GC_SPI_CTRL_RXBYTOR_LSB                  0x1a
-#define GC_SPI_CTRL_RXBYTOR_MASK                 0x4000000
-#define GC_SPI_CTRL_RXBYTOR_SIZE                 0x1
-#define GC_SPI_CTRL_RXBYTOR_DEFAULT              0x0
-#define GC_SPI_CTRL_RXBYTOR_OFFSET               0x0
-#define GC_SPI_CTRL_ENPASSTHRU_LSB               0x1b
-#define GC_SPI_CTRL_ENPASSTHRU_MASK              0x8000000
-#define GC_SPI_CTRL_ENPASSTHRU_SIZE              0x1
-#define GC_SPI_CTRL_ENPASSTHRU_DEFAULT           0x0
-#define GC_SPI_CTRL_ENPASSTHRU_OFFSET            0x0
-#define GC_SPI_XACT_START_LSB                    0x0
-#define GC_SPI_XACT_START_MASK                   0x1
-#define GC_SPI_XACT_START_SIZE                   0x1
-#define GC_SPI_XACT_START_DEFAULT                0x0
-#define GC_SPI_XACT_START_OFFSET                 0x4
-#define GC_SPI_XACT_BCNT_LSB                     0x1
-#define GC_SPI_XACT_BCNT_MASK                    0xe
-#define GC_SPI_XACT_BCNT_SIZE                    0x3
-#define GC_SPI_XACT_BCNT_DEFAULT                 0x7
-#define GC_SPI_XACT_BCNT_OFFSET                  0x4
-#define GC_SPI_XACT_SIZE_LSB                     0x4
-#define GC_SPI_XACT_SIZE_MASK                    0x7f0
-#define GC_SPI_XACT_SIZE_SIZE                    0x7
-#define GC_SPI_XACT_SIZE_DEFAULT                 0x0
-#define GC_SPI_XACT_SIZE_OFFSET                  0x4
-#define GC_SPI_XACT_RDY_POLL_LSB                 0xb
-#define GC_SPI_XACT_RDY_POLL_MASK                0x800
-#define GC_SPI_XACT_RDY_POLL_SIZE                0x1
-#define GC_SPI_XACT_RDY_POLL_DEFAULT             0x0
-#define GC_SPI_XACT_RDY_POLL_OFFSET              0x4
-#define GC_SPI_XACT_RDY_POLL_DLY_LSB             0xc
-#define GC_SPI_XACT_RDY_POLL_DLY_MASK            0x1f000
-#define GC_SPI_XACT_RDY_POLL_DLY_SIZE            0x5
-#define GC_SPI_XACT_RDY_POLL_DLY_DEFAULT         0x0
-#define GC_SPI_XACT_RDY_POLL_DLY_OFFSET          0x4
-#define GC_SPI_ICTRL_TXDONE_LSB                  0x0
-#define GC_SPI_ICTRL_TXDONE_MASK                 0x1
-#define GC_SPI_ICTRL_TXDONE_SIZE                 0x1
-#define GC_SPI_ICTRL_TXDONE_DEFAULT              0x0
-#define GC_SPI_ICTRL_TXDONE_OFFSET               0x8
-#define GC_SPI_ISTATE_TXDONE_LSB                 0x0
-#define GC_SPI_ISTATE_TXDONE_MASK                0x1
-#define GC_SPI_ISTATE_TXDONE_SIZE                0x1
-#define GC_SPI_ISTATE_TXDONE_DEFAULT             0x0
-#define GC_SPI_ISTATE_TXDONE_OFFSET              0xc
-#define GC_SPI_ISTATE_CLR_TXDONE_LSB             0x0
-#define GC_SPI_ISTATE_CLR_TXDONE_MASK            0x1
-#define GC_SPI_ISTATE_CLR_TXDONE_SIZE            0x1
-#define GC_SPI_ISTATE_CLR_TXDONE_DEFAULT         0x0
-#define GC_SPI_ISTATE_CLR_TXDONE_OFFSET          0x10
-#define GC_SPI_OVRD_SCKEN_LSB                    0x0
-#define GC_SPI_OVRD_SCKEN_MASK                   0x1
-#define GC_SPI_OVRD_SCKEN_SIZE                   0x1
-#define GC_SPI_OVRD_SCKEN_DEFAULT                0x0
-#define GC_SPI_OVRD_SCKEN_OFFSET                 0x14
-#define GC_SPI_OVRD_SCKVAL_LSB                   0x1
-#define GC_SPI_OVRD_SCKVAL_MASK                  0x2
-#define GC_SPI_OVRD_SCKVAL_SIZE                  0x1
-#define GC_SPI_OVRD_SCKVAL_DEFAULT               0x0
-#define GC_SPI_OVRD_SCKVAL_OFFSET                0x14
-#define GC_SPI_OVRD_CSBEN_LSB                    0x2
-#define GC_SPI_OVRD_CSBEN_MASK                   0x4
-#define GC_SPI_OVRD_CSBEN_SIZE                   0x1
-#define GC_SPI_OVRD_CSBEN_DEFAULT                0x0
-#define GC_SPI_OVRD_CSBEN_OFFSET                 0x14
-#define GC_SPI_OVRD_CSBVAL_LSB                   0x3
-#define GC_SPI_OVRD_CSBVAL_MASK                  0x8
-#define GC_SPI_OVRD_CSBVAL_SIZE                  0x1
-#define GC_SPI_OVRD_CSBVAL_DEFAULT               0x1
-#define GC_SPI_OVRD_CSBVAL_OFFSET                0x14
-#define GC_SPI_OVRD_MOSIEN_LSB                   0x4
-#define GC_SPI_OVRD_MOSIEN_MASK                  0x10
-#define GC_SPI_OVRD_MOSIEN_SIZE                  0x1
-#define GC_SPI_OVRD_MOSIEN_DEFAULT               0x0
-#define GC_SPI_OVRD_MOSIEN_OFFSET                0x14
-#define GC_SPI_OVRD_MOSIVAL_LSB                  0x5
-#define GC_SPI_OVRD_MOSIVAL_MASK                 0x20
-#define GC_SPI_OVRD_MOSIVAL_SIZE                 0x1
-#define GC_SPI_OVRD_MOSIVAL_DEFAULT              0x0
-#define GC_SPI_OVRD_MOSIVAL_OFFSET               0x14
-#define GC_SPI_VAL_MISO_LSB                      0x0
-#define GC_SPI_VAL_MISO_MASK                     0x1
-#define GC_SPI_VAL_MISO_SIZE                     0x1
-#define GC_SPI_VAL_MISO_DEFAULT                  0x0
-#define GC_SPI_VAL_MISO_OFFSET                   0x18
-#define GC_SPI_VAL_MOSI_LSB                      0x1
-#define GC_SPI_VAL_MOSI_MASK                     0x2
-#define GC_SPI_VAL_MOSI_SIZE                     0x1
-#define GC_SPI_VAL_MOSI_DEFAULT                  0x0
-#define GC_SPI_VAL_MOSI_OFFSET                   0x18
-#define GC_SPI_VAL_CSB_LSB                       0x2
-#define GC_SPI_VAL_CSB_MASK                      0x4
-#define GC_SPI_VAL_CSB_SIZE                      0x1
-#define GC_SPI_VAL_CSB_DEFAULT                   0x0
-#define GC_SPI_VAL_CSB_OFFSET                    0x18
-#define GC_SPI_VAL_SCK_LSB                       0x3
-#define GC_SPI_VAL_SCK_MASK                      0x8
-#define GC_SPI_VAL_SCK_SIZE                      0x1
-#define GC_SPI_VAL_SCK_DEFAULT                   0x0
-#define GC_SPI_VAL_SCK_OFFSET                    0x18
-#define GC_SPI_ITOP_TXDONE_LSB                   0x0
-#define GC_SPI_ITOP_TXDONE_MASK                  0x1
-#define GC_SPI_ITOP_TXDONE_SIZE                  0x1
-#define GC_SPI_ITOP_TXDONE_DEFAULT               0x0
-#define GC_SPI_ITOP_TXDONE_OFFSET                0xf04
-#define GC_SPS_CTRL_MODE_LSB                     0x0
-#define GC_SPS_CTRL_MODE_MASK                    0x3
-#define GC_SPS_CTRL_MODE_SIZE                    0x2
-#define GC_SPS_CTRL_MODE_DEFAULT                 0x1
-#define GC_SPS_CTRL_MODE_OFFSET                  0x0
-#define GC_SPS_CTRL_CPHA_LSB                     0x2
-#define GC_SPS_CTRL_CPHA_MASK                    0x4
-#define GC_SPS_CTRL_CPHA_SIZE                    0x1
-#define GC_SPS_CTRL_CPHA_DEFAULT                 0x0
-#define GC_SPS_CTRL_CPHA_OFFSET                  0x0
-#define GC_SPS_CTRL_CPOL_LSB                     0x3
-#define GC_SPS_CTRL_CPOL_MASK                    0x8
-#define GC_SPS_CTRL_CPOL_SIZE                    0x1
-#define GC_SPS_CTRL_CPOL_DEFAULT                 0x0
-#define GC_SPS_CTRL_CPOL_OFFSET                  0x0
-#define GC_SPS_CTRL_IDLE_LVL_LSB                 0x4
-#define GC_SPS_CTRL_IDLE_LVL_MASK                0x10
-#define GC_SPS_CTRL_IDLE_LVL_SIZE                0x1
-#define GC_SPS_CTRL_IDLE_LVL_DEFAULT             0x0
-#define GC_SPS_CTRL_IDLE_LVL_OFFSET              0x0
-#define GC_SPS_CTRL_TXBITOR_LSB                  0x5
-#define GC_SPS_CTRL_TXBITOR_MASK                 0x20
-#define GC_SPS_CTRL_TXBITOR_SIZE                 0x1
-#define GC_SPS_CTRL_TXBITOR_DEFAULT              0x0
-#define GC_SPS_CTRL_TXBITOR_OFFSET               0x0
-#define GC_SPS_CTRL_RXBITOR_LSB                  0x6
-#define GC_SPS_CTRL_RXBITOR_MASK                 0x40
-#define GC_SPS_CTRL_RXBITOR_SIZE                 0x1
-#define GC_SPS_CTRL_RXBITOR_DEFAULT              0x0
-#define GC_SPS_CTRL_RXBITOR_OFFSET               0x0
-#define GC_SPS_STATUS01_STATUS0L_LSB             0x0
-#define GC_SPS_STATUS01_STATUS0L_MASK            0xff
-#define GC_SPS_STATUS01_STATUS0L_SIZE            0x8
-#define GC_SPS_STATUS01_STATUS0L_DEFAULT         0x0
-#define GC_SPS_STATUS01_STATUS0L_OFFSET          0x8
-#define GC_SPS_STATUS01_STATUS0H_LSB             0x8
-#define GC_SPS_STATUS01_STATUS0H_MASK            0xff00
-#define GC_SPS_STATUS01_STATUS0H_SIZE            0x8
-#define GC_SPS_STATUS01_STATUS0H_DEFAULT         0x0
-#define GC_SPS_STATUS01_STATUS0H_OFFSET          0x8
-#define GC_SPS_STATUS01_STATUS1_LSB              0x10
-#define GC_SPS_STATUS01_STATUS1_MASK             0xffff0000
-#define GC_SPS_STATUS01_STATUS1_SIZE             0x10
-#define GC_SPS_STATUS01_STATUS1_DEFAULT          0x0
-#define GC_SPS_STATUS01_STATUS1_OFFSET           0x8
-#define GC_SPS_STATUS23_STATUS2_LSB              0x0
-#define GC_SPS_STATUS23_STATUS2_MASK             0xffff
-#define GC_SPS_STATUS23_STATUS2_SIZE             0x10
-#define GC_SPS_STATUS23_STATUS2_DEFAULT          0x0
-#define GC_SPS_STATUS23_STATUS2_OFFSET           0xc
-#define GC_SPS_STATUS23_STATUS3_LSB              0x10
-#define GC_SPS_STATUS23_STATUS3_MASK             0xffff0000
-#define GC_SPS_STATUS23_STATUS3_SIZE             0x10
-#define GC_SPS_STATUS23_STATUS3_DEFAULT          0x0
-#define GC_SPS_STATUS23_STATUS3_OFFSET           0xc
-#define GC_SPS_STATUS45_STATUS4_LSB              0x0
-#define GC_SPS_STATUS45_STATUS4_MASK             0xffff
-#define GC_SPS_STATUS45_STATUS4_SIZE             0x10
-#define GC_SPS_STATUS45_STATUS4_DEFAULT          0x0
-#define GC_SPS_STATUS45_STATUS4_OFFSET           0x10
-#define GC_SPS_STATUS45_STATUS5_LSB              0x10
-#define GC_SPS_STATUS45_STATUS5_MASK             0xffff0000
-#define GC_SPS_STATUS45_STATUS5_SIZE             0x10
-#define GC_SPS_STATUS45_STATUS5_DEFAULT          0x0
-#define GC_SPS_STATUS45_STATUS5_OFFSET           0x10
-#define GC_SPS_STATUS67_STATUS6_LSB              0x0
-#define GC_SPS_STATUS67_STATUS6_MASK             0xffff
-#define GC_SPS_STATUS67_STATUS6_SIZE             0x10
-#define GC_SPS_STATUS67_STATUS6_DEFAULT          0x0
-#define GC_SPS_STATUS67_STATUS6_OFFSET           0x14
-#define GC_SPS_STATUS67_STATUS7_LSB              0x10
-#define GC_SPS_STATUS67_STATUS7_MASK             0xffff0000
-#define GC_SPS_STATUS67_STATUS7_SIZE             0x10
-#define GC_SPS_STATUS67_STATUS7_DEFAULT          0x0
-#define GC_SPS_STATUS67_STATUS7_OFFSET           0x14
-#define GC_SPS_CTRL01_CTRL0_LSB                  0x0
-#define GC_SPS_CTRL01_CTRL0_MASK                 0xffff
-#define GC_SPS_CTRL01_CTRL0_SIZE                 0x10
-#define GC_SPS_CTRL01_CTRL0_DEFAULT              0x0
-#define GC_SPS_CTRL01_CTRL0_OFFSET               0x18
-#define GC_SPS_CTRL01_CTRL1_LSB                  0x10
-#define GC_SPS_CTRL01_CTRL1_MASK                 0xffff0000
-#define GC_SPS_CTRL01_CTRL1_SIZE                 0x10
-#define GC_SPS_CTRL01_CTRL1_DEFAULT              0x0
-#define GC_SPS_CTRL01_CTRL1_OFFSET               0x18
-#define GC_SPS_CTRL23_CTRL2_LSB                  0x0
-#define GC_SPS_CTRL23_CTRL2_MASK                 0xffff
-#define GC_SPS_CTRL23_CTRL2_SIZE                 0x10
-#define GC_SPS_CTRL23_CTRL2_DEFAULT              0x0
-#define GC_SPS_CTRL23_CTRL2_OFFSET               0x1c
-#define GC_SPS_CTRL23_CTRL3_LSB                  0x10
-#define GC_SPS_CTRL23_CTRL3_MASK                 0xffff0000
-#define GC_SPS_CTRL23_CTRL3_SIZE                 0x10
-#define GC_SPS_CTRL23_CTRL3_DEFAULT              0x0
-#define GC_SPS_CTRL23_CTRL3_OFFSET               0x1c
-#define GC_SPS_CTRL45_CTRL4_LSB                  0x0
-#define GC_SPS_CTRL45_CTRL4_MASK                 0xffff
-#define GC_SPS_CTRL45_CTRL4_SIZE                 0x10
-#define GC_SPS_CTRL45_CTRL4_DEFAULT              0x0
-#define GC_SPS_CTRL45_CTRL4_OFFSET               0x20
-#define GC_SPS_CTRL45_CTRL5_LSB                  0x10
-#define GC_SPS_CTRL45_CTRL5_MASK                 0xffff0000
-#define GC_SPS_CTRL45_CTRL5_SIZE                 0x10
-#define GC_SPS_CTRL45_CTRL5_DEFAULT              0x0
-#define GC_SPS_CTRL45_CTRL5_OFFSET               0x20
-#define GC_SPS_CTRL67_CTRL6_LSB                  0x0
-#define GC_SPS_CTRL67_CTRL6_MASK                 0xffff
-#define GC_SPS_CTRL67_CTRL6_SIZE                 0x10
-#define GC_SPS_CTRL67_CTRL6_DEFAULT              0x0
-#define GC_SPS_CTRL67_CTRL6_OFFSET               0x24
-#define GC_SPS_CTRL67_CTRL7_LSB                  0x10
-#define GC_SPS_CTRL67_CTRL7_MASK                 0xffff0000
-#define GC_SPS_CTRL67_CTRL7_SIZE                 0x10
-#define GC_SPS_CTRL67_CTRL7_DEFAULT              0x0
-#define GC_SPS_CTRL67_CTRL7_OFFSET               0x24
-#define GC_SPS_FIFO_CTRL_TXFIFO_RST_LSB          0x0
-#define GC_SPS_FIFO_CTRL_TXFIFO_RST_MASK         0x1
-#define GC_SPS_FIFO_CTRL_TXFIFO_RST_SIZE         0x1
-#define GC_SPS_FIFO_CTRL_TXFIFO_RST_DEFAULT      0x0
-#define GC_SPS_FIFO_CTRL_TXFIFO_RST_OFFSET       0x28
-#define GC_SPS_FIFO_CTRL_TXFIFO_EN_LSB           0x1
-#define GC_SPS_FIFO_CTRL_TXFIFO_EN_MASK          0x2
-#define GC_SPS_FIFO_CTRL_TXFIFO_EN_SIZE          0x1
-#define GC_SPS_FIFO_CTRL_TXFIFO_EN_DEFAULT       0x0
-#define GC_SPS_FIFO_CTRL_TXFIFO_EN_OFFSET        0x28
-#define GC_SPS_FIFO_CTRL_TXFIFO_AUTO_DIS_LSB     0x2
-#define GC_SPS_FIFO_CTRL_TXFIFO_AUTO_DIS_MASK    0x4
-#define GC_SPS_FIFO_CTRL_TXFIFO_AUTO_DIS_SIZE    0x1
-#define GC_SPS_FIFO_CTRL_TXFIFO_AUTO_DIS_DEFAULT 0x0
-#define GC_SPS_FIFO_CTRL_TXFIFO_AUTO_DIS_OFFSET  0x28
-#define GC_SPS_FIFO_CTRL_RXFIFO_RST_LSB          0x3
-#define GC_SPS_FIFO_CTRL_RXFIFO_RST_MASK         0x8
-#define GC_SPS_FIFO_CTRL_RXFIFO_RST_SIZE         0x1
-#define GC_SPS_FIFO_CTRL_RXFIFO_RST_DEFAULT      0x0
-#define GC_SPS_FIFO_CTRL_RXFIFO_RST_OFFSET       0x28
-#define GC_SPS_FIFO_CTRL_RXFIFO_EN_LSB           0x4
-#define GC_SPS_FIFO_CTRL_RXFIFO_EN_MASK          0x10
-#define GC_SPS_FIFO_CTRL_RXFIFO_EN_SIZE          0x1
-#define GC_SPS_FIFO_CTRL_RXFIFO_EN_DEFAULT       0x0
-#define GC_SPS_FIFO_CTRL_RXFIFO_EN_OFFSET        0x28
-#define GC_SPS_FIFO_CTRL_RXFIFO_AUTO_DIS_LSB     0x5
-#define GC_SPS_FIFO_CTRL_RXFIFO_AUTO_DIS_MASK    0x20
-#define GC_SPS_FIFO_CTRL_RXFIFO_AUTO_DIS_SIZE    0x1
-#define GC_SPS_FIFO_CTRL_RXFIFO_AUTO_DIS_DEFAULT 0x0
-#define GC_SPS_FIFO_CTRL_RXFIFO_AUTO_DIS_OFFSET  0x28
-#define GC_SPS_OVRD_MISOEN_LSB                   0x0
-#define GC_SPS_OVRD_MISOEN_MASK                  0x1
-#define GC_SPS_OVRD_MISOEN_SIZE                  0x1
-#define GC_SPS_OVRD_MISOEN_DEFAULT               0x0
-#define GC_SPS_OVRD_MISOEN_OFFSET                0x4c
-#define GC_SPS_OVRD_MISOVAL_LSB                  0x1
-#define GC_SPS_OVRD_MISOVAL_MASK                 0x2
-#define GC_SPS_OVRD_MISOVAL_SIZE                 0x1
-#define GC_SPS_OVRD_MISOVAL_DEFAULT              0x0
-#define GC_SPS_OVRD_MISOVAL_OFFSET               0x4c
-#define GC_SPS_VAL_MISO_LSB                      0x0
-#define GC_SPS_VAL_MISO_MASK                     0x1
-#define GC_SPS_VAL_MISO_SIZE                     0x1
-#define GC_SPS_VAL_MISO_DEFAULT                  0x0
-#define GC_SPS_VAL_MISO_OFFSET                   0x50
-#define GC_SPS_VAL_MOSI_LSB                      0x1
-#define GC_SPS_VAL_MOSI_MASK                     0x2
-#define GC_SPS_VAL_MOSI_SIZE                     0x1
-#define GC_SPS_VAL_MOSI_DEFAULT                  0x0
-#define GC_SPS_VAL_MOSI_OFFSET                   0x50
-#define GC_SPS_VAL_CSB_LSB                       0x2
-#define GC_SPS_VAL_CSB_MASK                      0x4
-#define GC_SPS_VAL_CSB_SIZE                      0x1
-#define GC_SPS_VAL_CSB_DEFAULT                   0x0
-#define GC_SPS_VAL_CSB_OFFSET                    0x50
-#define GC_SPS_VAL_SCK_LSB                       0x3
-#define GC_SPS_VAL_SCK_MASK                      0x8
-#define GC_SPS_VAL_SCK_SIZE                      0x1
-#define GC_SPS_VAL_SCK_DEFAULT                   0x0
-#define GC_SPS_VAL_SCK_OFFSET                    0x50
-#define GC_SPS_ISTATE_CTLWR0_LSB                 0x0
-#define GC_SPS_ISTATE_CTLWR0_MASK                0x1
-#define GC_SPS_ISTATE_CTLWR0_SIZE                0x1
-#define GC_SPS_ISTATE_CTLWR0_DEFAULT             0x0
-#define GC_SPS_ISTATE_CTLWR0_OFFSET              0x54
-#define GC_SPS_ISTATE_CTLWR1_LSB                 0x1
-#define GC_SPS_ISTATE_CTLWR1_MASK                0x2
-#define GC_SPS_ISTATE_CTLWR1_SIZE                0x1
-#define GC_SPS_ISTATE_CTLWR1_DEFAULT             0x0
-#define GC_SPS_ISTATE_CTLWR1_OFFSET              0x54
-#define GC_SPS_ISTATE_CTLWR2_LSB                 0x2
-#define GC_SPS_ISTATE_CTLWR2_MASK                0x4
-#define GC_SPS_ISTATE_CTLWR2_SIZE                0x1
-#define GC_SPS_ISTATE_CTLWR2_DEFAULT             0x0
-#define GC_SPS_ISTATE_CTLWR2_OFFSET              0x54
-#define GC_SPS_ISTATE_CTLWR3_LSB                 0x3
-#define GC_SPS_ISTATE_CTLWR3_MASK                0x8
-#define GC_SPS_ISTATE_CTLWR3_SIZE                0x1
-#define GC_SPS_ISTATE_CTLWR3_DEFAULT             0x0
-#define GC_SPS_ISTATE_CTLWR3_OFFSET              0x54
-#define GC_SPS_ISTATE_CTLWR4_LSB                 0x4
-#define GC_SPS_ISTATE_CTLWR4_MASK                0x10
-#define GC_SPS_ISTATE_CTLWR4_SIZE                0x1
-#define GC_SPS_ISTATE_CTLWR4_DEFAULT             0x0
-#define GC_SPS_ISTATE_CTLWR4_OFFSET              0x54
-#define GC_SPS_ISTATE_CTLWR5_LSB                 0x5
-#define GC_SPS_ISTATE_CTLWR5_MASK                0x20
-#define GC_SPS_ISTATE_CTLWR5_SIZE                0x1
-#define GC_SPS_ISTATE_CTLWR5_DEFAULT             0x0
-#define GC_SPS_ISTATE_CTLWR5_OFFSET              0x54
-#define GC_SPS_ISTATE_CTLWR6_LSB                 0x6
-#define GC_SPS_ISTATE_CTLWR6_MASK                0x40
-#define GC_SPS_ISTATE_CTLWR6_SIZE                0x1
-#define GC_SPS_ISTATE_CTLWR6_DEFAULT             0x0
-#define GC_SPS_ISTATE_CTLWR6_OFFSET              0x54
-#define GC_SPS_ISTATE_CTLWR7_LSB                 0x7
-#define GC_SPS_ISTATE_CTLWR7_MASK                0x80
-#define GC_SPS_ISTATE_CTLWR7_SIZE                0x1
-#define GC_SPS_ISTATE_CTLWR7_DEFAULT             0x0
-#define GC_SPS_ISTATE_CTLWR7_OFFSET              0x54
-#define GC_SPS_ISTATE_CS_ASSERT_LSB              0x8
-#define GC_SPS_ISTATE_CS_ASSERT_MASK             0x100
-#define GC_SPS_ISTATE_CS_ASSERT_SIZE             0x1
-#define GC_SPS_ISTATE_CS_ASSERT_DEFAULT          0x0
-#define GC_SPS_ISTATE_CS_ASSERT_OFFSET           0x54
-#define GC_SPS_ISTATE_CS_DEASSERT_LSB            0x9
-#define GC_SPS_ISTATE_CS_DEASSERT_MASK           0x200
-#define GC_SPS_ISTATE_CS_DEASSERT_SIZE           0x1
-#define GC_SPS_ISTATE_CS_DEASSERT_DEFAULT        0x0
-#define GC_SPS_ISTATE_CS_DEASSERT_OFFSET         0x54
-#define GC_SPS_ISTATE_RXFIFO_OVERFLOW_LSB        0xa
-#define GC_SPS_ISTATE_RXFIFO_OVERFLOW_MASK       0x400
-#define GC_SPS_ISTATE_RXFIFO_OVERFLOW_SIZE       0x1
-#define GC_SPS_ISTATE_RXFIFO_OVERFLOW_DEFAULT    0x0
-#define GC_SPS_ISTATE_RXFIFO_OVERFLOW_OFFSET     0x54
-#define GC_SPS_ISTATE_TXFIFO_EMPTY_LSB           0xb
-#define GC_SPS_ISTATE_TXFIFO_EMPTY_MASK          0x800
-#define GC_SPS_ISTATE_TXFIFO_EMPTY_SIZE          0x1
-#define GC_SPS_ISTATE_TXFIFO_EMPTY_DEFAULT       0x0
-#define GC_SPS_ISTATE_TXFIFO_EMPTY_OFFSET        0x54
-#define GC_SPS_ISTATE_TXFIFO_FULL_LSB            0xc
-#define GC_SPS_ISTATE_TXFIFO_FULL_MASK           0x1000
-#define GC_SPS_ISTATE_TXFIFO_FULL_SIZE           0x1
-#define GC_SPS_ISTATE_TXFIFO_FULL_DEFAULT        0x0
-#define GC_SPS_ISTATE_TXFIFO_FULL_OFFSET         0x54
-#define GC_SPS_ISTATE_TXFIFO_LVL_LSB             0xd
-#define GC_SPS_ISTATE_TXFIFO_LVL_MASK            0x2000
-#define GC_SPS_ISTATE_TXFIFO_LVL_SIZE            0x1
-#define GC_SPS_ISTATE_TXFIFO_LVL_DEFAULT         0x0
-#define GC_SPS_ISTATE_TXFIFO_LVL_OFFSET          0x54
-#define GC_SPS_ISTATE_RXFIFO_LVL_LSB             0xe
-#define GC_SPS_ISTATE_RXFIFO_LVL_MASK            0x4000
-#define GC_SPS_ISTATE_RXFIFO_LVL_SIZE            0x1
-#define GC_SPS_ISTATE_RXFIFO_LVL_DEFAULT         0x0
-#define GC_SPS_ISTATE_RXFIFO_LVL_OFFSET          0x54
-#define GC_SPS_ISTATE_CLR_CTLWR0_LSB             0x0
-#define GC_SPS_ISTATE_CLR_CTLWR0_MASK            0x1
-#define GC_SPS_ISTATE_CLR_CTLWR0_SIZE            0x1
-#define GC_SPS_ISTATE_CLR_CTLWR0_DEFAULT         0x0
-#define GC_SPS_ISTATE_CLR_CTLWR0_OFFSET          0x58
-#define GC_SPS_ISTATE_CLR_CTLWR1_LSB             0x1
-#define GC_SPS_ISTATE_CLR_CTLWR1_MASK            0x2
-#define GC_SPS_ISTATE_CLR_CTLWR1_SIZE            0x1
-#define GC_SPS_ISTATE_CLR_CTLWR1_DEFAULT         0x0
-#define GC_SPS_ISTATE_CLR_CTLWR1_OFFSET          0x58
-#define GC_SPS_ISTATE_CLR_CTLWR2_LSB             0x2
-#define GC_SPS_ISTATE_CLR_CTLWR2_MASK            0x4
-#define GC_SPS_ISTATE_CLR_CTLWR2_SIZE            0x1
-#define GC_SPS_ISTATE_CLR_CTLWR2_DEFAULT         0x0
-#define GC_SPS_ISTATE_CLR_CTLWR2_OFFSET          0x58
-#define GC_SPS_ISTATE_CLR_CTLWR3_LSB             0x3
-#define GC_SPS_ISTATE_CLR_CTLWR3_MASK            0x8
-#define GC_SPS_ISTATE_CLR_CTLWR3_SIZE            0x1
-#define GC_SPS_ISTATE_CLR_CTLWR3_DEFAULT         0x0
-#define GC_SPS_ISTATE_CLR_CTLWR3_OFFSET          0x58
-#define GC_SPS_ISTATE_CLR_CTLWR4_LSB             0x4
-#define GC_SPS_ISTATE_CLR_CTLWR4_MASK            0x10
-#define GC_SPS_ISTATE_CLR_CTLWR4_SIZE            0x1
-#define GC_SPS_ISTATE_CLR_CTLWR4_DEFAULT         0x0
-#define GC_SPS_ISTATE_CLR_CTLWR4_OFFSET          0x58
-#define GC_SPS_ISTATE_CLR_CTLWR5_LSB             0x5
-#define GC_SPS_ISTATE_CLR_CTLWR5_MASK            0x20
-#define GC_SPS_ISTATE_CLR_CTLWR5_SIZE            0x1
-#define GC_SPS_ISTATE_CLR_CTLWR5_DEFAULT         0x0
-#define GC_SPS_ISTATE_CLR_CTLWR5_OFFSET          0x58
-#define GC_SPS_ISTATE_CLR_CTLWR6_LSB             0x6
-#define GC_SPS_ISTATE_CLR_CTLWR6_MASK            0x40
-#define GC_SPS_ISTATE_CLR_CTLWR6_SIZE            0x1
-#define GC_SPS_ISTATE_CLR_CTLWR6_DEFAULT         0x0
-#define GC_SPS_ISTATE_CLR_CTLWR6_OFFSET          0x58
-#define GC_SPS_ISTATE_CLR_CTLWR7_LSB             0x7
-#define GC_SPS_ISTATE_CLR_CTLWR7_MASK            0x80
-#define GC_SPS_ISTATE_CLR_CTLWR7_SIZE            0x1
-#define GC_SPS_ISTATE_CLR_CTLWR7_DEFAULT         0x0
-#define GC_SPS_ISTATE_CLR_CTLWR7_OFFSET          0x58
-#define GC_SPS_ISTATE_CLR_CS_ASSERT_LSB          0x8
-#define GC_SPS_ISTATE_CLR_CS_ASSERT_MASK         0x100
-#define GC_SPS_ISTATE_CLR_CS_ASSERT_SIZE         0x1
-#define GC_SPS_ISTATE_CLR_CS_ASSERT_DEFAULT      0x0
-#define GC_SPS_ISTATE_CLR_CS_ASSERT_OFFSET       0x58
-#define GC_SPS_ISTATE_CLR_CS_DEASSERT_LSB        0x9
-#define GC_SPS_ISTATE_CLR_CS_DEASSERT_MASK       0x200
-#define GC_SPS_ISTATE_CLR_CS_DEASSERT_SIZE       0x1
-#define GC_SPS_ISTATE_CLR_CS_DEASSERT_DEFAULT    0x0
-#define GC_SPS_ISTATE_CLR_CS_DEASSERT_OFFSET     0x58
-#define GC_SPS_ISTATE_CLR_RXFIFO_OVERFLOW_LSB    0xa
-#define GC_SPS_ISTATE_CLR_RXFIFO_OVERFLOW_MASK   0x400
-#define GC_SPS_ISTATE_CLR_RXFIFO_OVERFLOW_SIZE   0x1
-#define GC_SPS_ISTATE_CLR_RXFIFO_OVERFLOW_DEFAULT 0x0
-#define GC_SPS_ISTATE_CLR_RXFIFO_OVERFLOW_OFFSET 0x58
-#define GC_SPS_ITOP_CTRLINT0_LSB                 0x0
-#define GC_SPS_ITOP_CTRLINT0_MASK                0x1
-#define GC_SPS_ITOP_CTRLINT0_SIZE                0x1
-#define GC_SPS_ITOP_CTRLINT0_DEFAULT             0x0
-#define GC_SPS_ITOP_CTRLINT0_OFFSET              0x60
-#define GC_SPS_ITOP_CTRLINT1_LSB                 0x1
-#define GC_SPS_ITOP_CTRLINT1_MASK                0x2
-#define GC_SPS_ITOP_CTRLINT1_SIZE                0x1
-#define GC_SPS_ITOP_CTRLINT1_DEFAULT             0x0
-#define GC_SPS_ITOP_CTRLINT1_OFFSET              0x60
-#define GC_SPS_ITOP_CTRLINT2_LSB                 0x2
-#define GC_SPS_ITOP_CTRLINT2_MASK                0x4
-#define GC_SPS_ITOP_CTRLINT2_SIZE                0x1
-#define GC_SPS_ITOP_CTRLINT2_DEFAULT             0x0
-#define GC_SPS_ITOP_CTRLINT2_OFFSET              0x60
-#define GC_SPS_ITOP_CTRLINT3_LSB                 0x3
-#define GC_SPS_ITOP_CTRLINT3_MASK                0x8
-#define GC_SPS_ITOP_CTRLINT3_SIZE                0x1
-#define GC_SPS_ITOP_CTRLINT3_DEFAULT             0x0
-#define GC_SPS_ITOP_CTRLINT3_OFFSET              0x60
-#define GC_SPS_ITOP_CTRLINT4_LSB                 0x4
-#define GC_SPS_ITOP_CTRLINT4_MASK                0x10
-#define GC_SPS_ITOP_CTRLINT4_SIZE                0x1
-#define GC_SPS_ITOP_CTRLINT4_DEFAULT             0x0
-#define GC_SPS_ITOP_CTRLINT4_OFFSET              0x60
-#define GC_SPS_ITOP_CTRLINT5_LSB                 0x5
-#define GC_SPS_ITOP_CTRLINT5_MASK                0x20
-#define GC_SPS_ITOP_CTRLINT5_SIZE                0x1
-#define GC_SPS_ITOP_CTRLINT5_DEFAULT             0x0
-#define GC_SPS_ITOP_CTRLINT5_OFFSET              0x60
-#define GC_SPS_ITOP_CTRLINT6_LSB                 0x6
-#define GC_SPS_ITOP_CTRLINT6_MASK                0x40
-#define GC_SPS_ITOP_CTRLINT6_SIZE                0x1
-#define GC_SPS_ITOP_CTRLINT6_DEFAULT             0x0
-#define GC_SPS_ITOP_CTRLINT6_OFFSET              0x60
-#define GC_SPS_ITOP_CTRLINT7_LSB                 0x7
-#define GC_SPS_ITOP_CTRLINT7_MASK                0x80
-#define GC_SPS_ITOP_CTRLINT7_SIZE                0x1
-#define GC_SPS_ITOP_CTRLINT7_DEFAULT             0x0
-#define GC_SPS_ITOP_CTRLINT7_OFFSET              0x60
-#define GC_SPS_ITOP_CS_ASSERT_LSB                0x8
-#define GC_SPS_ITOP_CS_ASSERT_MASK               0x100
-#define GC_SPS_ITOP_CS_ASSERT_SIZE               0x1
-#define GC_SPS_ITOP_CS_ASSERT_DEFAULT            0x0
-#define GC_SPS_ITOP_CS_ASSERT_OFFSET             0x60
-#define GC_SPS_ITOP_CS_DEASSERT_LSB              0x9
-#define GC_SPS_ITOP_CS_DEASSERT_MASK             0x200
-#define GC_SPS_ITOP_CS_DEASSERT_SIZE             0x1
-#define GC_SPS_ITOP_CS_DEASSERT_DEFAULT          0x0
-#define GC_SPS_ITOP_CS_DEASSERT_OFFSET           0x60
-#define GC_SPS_ITOP_RXFIFO_OVERFLOW_LSB          0xa
-#define GC_SPS_ITOP_RXFIFO_OVERFLOW_MASK         0x400
-#define GC_SPS_ITOP_RXFIFO_OVERFLOW_SIZE         0x1
-#define GC_SPS_ITOP_RXFIFO_OVERFLOW_DEFAULT      0x0
-#define GC_SPS_ITOP_RXFIFO_OVERFLOW_OFFSET       0x60
-#define GC_SPS_ITOP_TXFIFO_EMPTY_LSB             0xb
-#define GC_SPS_ITOP_TXFIFO_EMPTY_MASK            0x800
-#define GC_SPS_ITOP_TXFIFO_EMPTY_SIZE            0x1
-#define GC_SPS_ITOP_TXFIFO_EMPTY_DEFAULT         0x0
-#define GC_SPS_ITOP_TXFIFO_EMPTY_OFFSET          0x60
-#define GC_SPS_ITOP_TXFIFO_FULL_LSB              0xc
-#define GC_SPS_ITOP_TXFIFO_FULL_MASK             0x1000
-#define GC_SPS_ITOP_TXFIFO_FULL_SIZE             0x1
-#define GC_SPS_ITOP_TXFIFO_FULL_DEFAULT          0x0
-#define GC_SPS_ITOP_TXFIFO_FULL_OFFSET           0x60
-#define GC_SPS_ITOP_TXFIFO_LVL_LSB               0xd
-#define GC_SPS_ITOP_TXFIFO_LVL_MASK              0x2000
-#define GC_SPS_ITOP_TXFIFO_LVL_SIZE              0x1
-#define GC_SPS_ITOP_TXFIFO_LVL_DEFAULT           0x0
-#define GC_SPS_ITOP_TXFIFO_LVL_OFFSET            0x60
-#define GC_SPS_ITOP_RXFIFO_LVL_LSB               0xe
-#define GC_SPS_ITOP_RXFIFO_LVL_MASK              0x4000
-#define GC_SPS_ITOP_RXFIFO_LVL_SIZE              0x1
-#define GC_SPS_ITOP_RXFIFO_LVL_DEFAULT           0x0
-#define GC_SPS_ITOP_RXFIFO_LVL_OFFSET            0x60
-#define GC_SPS_ICTRL_CTLWR0_LSB                  0x0
-#define GC_SPS_ICTRL_CTLWR0_MASK                 0x1
-#define GC_SPS_ICTRL_CTLWR0_SIZE                 0x1
-#define GC_SPS_ICTRL_CTLWR0_DEFAULT              0x0
-#define GC_SPS_ICTRL_CTLWR0_OFFSET               0x64
-#define GC_SPS_ICTRL_CTLWR1_LSB                  0x1
-#define GC_SPS_ICTRL_CTLWR1_MASK                 0x2
-#define GC_SPS_ICTRL_CTLWR1_SIZE                 0x1
-#define GC_SPS_ICTRL_CTLWR1_DEFAULT              0x0
-#define GC_SPS_ICTRL_CTLWR1_OFFSET               0x64
-#define GC_SPS_ICTRL_CTLWR2_LSB                  0x2
-#define GC_SPS_ICTRL_CTLWR2_MASK                 0x4
-#define GC_SPS_ICTRL_CTLWR2_SIZE                 0x1
-#define GC_SPS_ICTRL_CTLWR2_DEFAULT              0x0
-#define GC_SPS_ICTRL_CTLWR2_OFFSET               0x64
-#define GC_SPS_ICTRL_CTLWR3_LSB                  0x3
-#define GC_SPS_ICTRL_CTLWR3_MASK                 0x8
-#define GC_SPS_ICTRL_CTLWR3_SIZE                 0x1
-#define GC_SPS_ICTRL_CTLWR3_DEFAULT              0x0
-#define GC_SPS_ICTRL_CTLWR3_OFFSET               0x64
-#define GC_SPS_ICTRL_CTLWR4_LSB                  0x4
-#define GC_SPS_ICTRL_CTLWR4_MASK                 0x10
-#define GC_SPS_ICTRL_CTLWR4_SIZE                 0x1
-#define GC_SPS_ICTRL_CTLWR4_DEFAULT              0x0
-#define GC_SPS_ICTRL_CTLWR4_OFFSET               0x64
-#define GC_SPS_ICTRL_CTLWR5_LSB                  0x5
-#define GC_SPS_ICTRL_CTLWR5_MASK                 0x20
-#define GC_SPS_ICTRL_CTLWR5_SIZE                 0x1
-#define GC_SPS_ICTRL_CTLWR5_DEFAULT              0x0
-#define GC_SPS_ICTRL_CTLWR5_OFFSET               0x64
-#define GC_SPS_ICTRL_CTLWR6_LSB                  0x6
-#define GC_SPS_ICTRL_CTLWR6_MASK                 0x40
-#define GC_SPS_ICTRL_CTLWR6_SIZE                 0x1
-#define GC_SPS_ICTRL_CTLWR6_DEFAULT              0x0
-#define GC_SPS_ICTRL_CTLWR6_OFFSET               0x64
-#define GC_SPS_ICTRL_CTLWR7_LSB                  0x7
-#define GC_SPS_ICTRL_CTLWR7_MASK                 0x80
-#define GC_SPS_ICTRL_CTLWR7_SIZE                 0x1
-#define GC_SPS_ICTRL_CTLWR7_DEFAULT              0x0
-#define GC_SPS_ICTRL_CTLWR7_OFFSET               0x64
-#define GC_SPS_ICTRL_CS_ASSERT_LSB               0x8
-#define GC_SPS_ICTRL_CS_ASSERT_MASK              0x100
-#define GC_SPS_ICTRL_CS_ASSERT_SIZE              0x1
-#define GC_SPS_ICTRL_CS_ASSERT_DEFAULT           0x0
-#define GC_SPS_ICTRL_CS_ASSERT_OFFSET            0x64
-#define GC_SPS_ICTRL_CS_DEASSERT_LSB             0x9
-#define GC_SPS_ICTRL_CS_DEASSERT_MASK            0x200
-#define GC_SPS_ICTRL_CS_DEASSERT_SIZE            0x1
-#define GC_SPS_ICTRL_CS_DEASSERT_DEFAULT         0x0
-#define GC_SPS_ICTRL_CS_DEASSERT_OFFSET          0x64
-#define GC_SPS_ICTRL_RXFIFO_OVERFLOW_LSB         0xa
-#define GC_SPS_ICTRL_RXFIFO_OVERFLOW_MASK        0x400
-#define GC_SPS_ICTRL_RXFIFO_OVERFLOW_SIZE        0x1
-#define GC_SPS_ICTRL_RXFIFO_OVERFLOW_DEFAULT     0x0
-#define GC_SPS_ICTRL_RXFIFO_OVERFLOW_OFFSET      0x64
-#define GC_SPS_ICTRL_TXFIFO_EMPTY_LSB            0xb
-#define GC_SPS_ICTRL_TXFIFO_EMPTY_MASK           0x800
-#define GC_SPS_ICTRL_TXFIFO_EMPTY_SIZE           0x1
-#define GC_SPS_ICTRL_TXFIFO_EMPTY_DEFAULT        0x0
-#define GC_SPS_ICTRL_TXFIFO_EMPTY_OFFSET         0x64
-#define GC_SPS_ICTRL_TXFIFO_FULL_LSB             0xc
-#define GC_SPS_ICTRL_TXFIFO_FULL_MASK            0x1000
-#define GC_SPS_ICTRL_TXFIFO_FULL_SIZE            0x1
-#define GC_SPS_ICTRL_TXFIFO_FULL_DEFAULT         0x0
-#define GC_SPS_ICTRL_TXFIFO_FULL_OFFSET          0x64
-#define GC_SPS_ICTRL_TXFIFO_LVL_LSB              0xd
-#define GC_SPS_ICTRL_TXFIFO_LVL_MASK             0x2000
-#define GC_SPS_ICTRL_TXFIFO_LVL_SIZE             0x1
-#define GC_SPS_ICTRL_TXFIFO_LVL_DEFAULT          0x0
-#define GC_SPS_ICTRL_TXFIFO_LVL_OFFSET           0x64
-#define GC_SPS_ICTRL_RXFIFO_LVL_LSB              0xe
-#define GC_SPS_ICTRL_RXFIFO_LVL_MASK             0x4000
-#define GC_SPS_ICTRL_RXFIFO_LVL_SIZE             0x1
-#define GC_SPS_ICTRL_RXFIFO_LVL_DEFAULT          0x0
-#define GC_SPS_ICTRL_RXFIFO_LVL_OFFSET           0x64
-#define GC_SPS_EEPROM_CTRL_ADDR_MODE_LSB         0x0
-#define GC_SPS_EEPROM_CTRL_ADDR_MODE_MASK        0x1
-#define GC_SPS_EEPROM_CTRL_ADDR_MODE_SIZE        0x1
-#define GC_SPS_EEPROM_CTRL_ADDR_MODE_DEFAULT     0x0
-#define GC_SPS_EEPROM_CTRL_ADDR_MODE_OFFSET      0x400
-#define GC_SPS_EEPROM_CTRL_PASSTHRU_DIS_LSB      0x1
-#define GC_SPS_EEPROM_CTRL_PASSTHRU_DIS_MASK     0x2
-#define GC_SPS_EEPROM_CTRL_PASSTHRU_DIS_SIZE     0x1
-#define GC_SPS_EEPROM_CTRL_PASSTHRU_DIS_DEFAULT  0x0
-#define GC_SPS_EEPROM_CTRL_PASSTHRU_DIS_OFFSET   0x400
-#define GC_SPS_EEPROM_CTRL_EXT_FLASH_DIS_LSB     0x2
-#define GC_SPS_EEPROM_CTRL_EXT_FLASH_DIS_MASK    0x4
-#define GC_SPS_EEPROM_CTRL_EXT_FLASH_DIS_SIZE    0x1
-#define GC_SPS_EEPROM_CTRL_EXT_FLASH_DIS_DEFAULT 0x0
-#define GC_SPS_EEPROM_CTRL_EXT_FLASH_DIS_OFFSET  0x400
-#define GC_SPS_EEPROM_CTRL_INT_FLASH_DIS_LSB     0x3
-#define GC_SPS_EEPROM_CTRL_INT_FLASH_DIS_MASK    0x8
-#define GC_SPS_EEPROM_CTRL_INT_FLASH_DIS_SIZE    0x1
-#define GC_SPS_EEPROM_CTRL_INT_FLASH_DIS_DEFAULT 0x0
-#define GC_SPS_EEPROM_CTRL_INT_FLASH_DIS_OFFSET  0x400
-#define GC_SPS_EEPROM_CTRL_RAM_DIS_LSB           0x4
-#define GC_SPS_EEPROM_CTRL_RAM_DIS_MASK          0x10
-#define GC_SPS_EEPROM_CTRL_RAM_DIS_SIZE          0x1
-#define GC_SPS_EEPROM_CTRL_RAM_DIS_DEFAULT       0x0
-#define GC_SPS_EEPROM_CTRL_RAM_DIS_OFFSET        0x400
-#define GC_SPS_EEPROM_CTRL_MAILBOX_EN_LSB        0x5
-#define GC_SPS_EEPROM_CTRL_MAILBOX_EN_MASK       0x20
-#define GC_SPS_EEPROM_CTRL_MAILBOX_EN_SIZE       0x1
-#define GC_SPS_EEPROM_CTRL_MAILBOX_EN_DEFAULT    0x0
-#define GC_SPS_EEPROM_CTRL_MAILBOX_EN_OFFSET     0x400
-#define GC_SPS_EEPROM_CTRL_FIFO_PREFETCH_LIMIT_LSB 0x6
-#define GC_SPS_EEPROM_CTRL_FIFO_PREFETCH_LIMIT_MASK 0x3c0
-#define GC_SPS_EEPROM_CTRL_FIFO_PREFETCH_LIMIT_SIZE 0x4
-#define GC_SPS_EEPROM_CTRL_FIFO_PREFETCH_LIMIT_DEFAULT 0x2
-#define GC_SPS_EEPROM_CTRL_FIFO_PREFETCH_LIMIT_OFFSET 0x400
-#define GC_SPS_EEPROM_CTRL_FAST_DUAL_RD_EN_LSB   0xa
-#define GC_SPS_EEPROM_CTRL_FAST_DUAL_RD_EN_MASK  0x400
-#define GC_SPS_EEPROM_CTRL_FAST_DUAL_RD_EN_SIZE  0x1
-#define GC_SPS_EEPROM_CTRL_FAST_DUAL_RD_EN_DEFAULT 0x1
-#define GC_SPS_EEPROM_CTRL_FAST_DUAL_RD_EN_OFFSET 0x400
-#define GC_SPS_EEPROM_CTRL_VIRTUAL_ADDR_FILTER_EN_LSB 0xb
-#define GC_SPS_EEPROM_CTRL_VIRTUAL_ADDR_FILTER_EN_MASK 0x800
-#define GC_SPS_EEPROM_CTRL_VIRTUAL_ADDR_FILTER_EN_SIZE 0x1
-#define GC_SPS_EEPROM_CTRL_VIRTUAL_ADDR_FILTER_EN_DEFAULT 0x0
-#define GC_SPS_EEPROM_CTRL_VIRTUAL_ADDR_FILTER_EN_OFFSET 0x400
-#define GC_SPS_BUSY_OPCODE0_EN_LSB               0x0
-#define GC_SPS_BUSY_OPCODE0_EN_MASK              0x1
-#define GC_SPS_BUSY_OPCODE0_EN_SIZE              0x1
-#define GC_SPS_BUSY_OPCODE0_EN_DEFAULT           0x0
-#define GC_SPS_BUSY_OPCODE0_EN_OFFSET            0x40c
-#define GC_SPS_BUSY_OPCODE0_VALUE_LSB            0x1
-#define GC_SPS_BUSY_OPCODE0_VALUE_MASK           0x1fe
-#define GC_SPS_BUSY_OPCODE0_VALUE_SIZE           0x8
-#define GC_SPS_BUSY_OPCODE0_VALUE_DEFAULT        0x0
-#define GC_SPS_BUSY_OPCODE0_VALUE_OFFSET         0x40c
-#define GC_SPS_BUSY_OPCODE1_EN_LSB               0x0
-#define GC_SPS_BUSY_OPCODE1_EN_MASK              0x1
-#define GC_SPS_BUSY_OPCODE1_EN_SIZE              0x1
-#define GC_SPS_BUSY_OPCODE1_EN_DEFAULT           0x0
-#define GC_SPS_BUSY_OPCODE1_EN_OFFSET            0x410
-#define GC_SPS_BUSY_OPCODE1_VALUE_LSB            0x1
-#define GC_SPS_BUSY_OPCODE1_VALUE_MASK           0x1fe
-#define GC_SPS_BUSY_OPCODE1_VALUE_SIZE           0x8
-#define GC_SPS_BUSY_OPCODE1_VALUE_DEFAULT        0x0
-#define GC_SPS_BUSY_OPCODE1_VALUE_OFFSET         0x410
-#define GC_SPS_BUSY_OPCODE2_EN_LSB               0x0
-#define GC_SPS_BUSY_OPCODE2_EN_MASK              0x1
-#define GC_SPS_BUSY_OPCODE2_EN_SIZE              0x1
-#define GC_SPS_BUSY_OPCODE2_EN_DEFAULT           0x0
-#define GC_SPS_BUSY_OPCODE2_EN_OFFSET            0x414
-#define GC_SPS_BUSY_OPCODE2_VALUE_LSB            0x1
-#define GC_SPS_BUSY_OPCODE2_VALUE_MASK           0x1fe
-#define GC_SPS_BUSY_OPCODE2_VALUE_SIZE           0x8
-#define GC_SPS_BUSY_OPCODE2_VALUE_DEFAULT        0x0
-#define GC_SPS_BUSY_OPCODE2_VALUE_OFFSET         0x414
-#define GC_SPS_BUSY_OPCODE3_EN_LSB               0x0
-#define GC_SPS_BUSY_OPCODE3_EN_MASK              0x1
-#define GC_SPS_BUSY_OPCODE3_EN_SIZE              0x1
-#define GC_SPS_BUSY_OPCODE3_EN_DEFAULT           0x0
-#define GC_SPS_BUSY_OPCODE3_EN_OFFSET            0x418
-#define GC_SPS_BUSY_OPCODE3_VALUE_LSB            0x1
-#define GC_SPS_BUSY_OPCODE3_VALUE_MASK           0x1fe
-#define GC_SPS_BUSY_OPCODE3_VALUE_SIZE           0x8
-#define GC_SPS_BUSY_OPCODE3_VALUE_DEFAULT        0x0
-#define GC_SPS_BUSY_OPCODE3_VALUE_OFFSET         0x418
-#define GC_SPS_BUSY_OPCODE4_EN_LSB               0x0
-#define GC_SPS_BUSY_OPCODE4_EN_MASK              0x1
-#define GC_SPS_BUSY_OPCODE4_EN_SIZE              0x1
-#define GC_SPS_BUSY_OPCODE4_EN_DEFAULT           0x0
-#define GC_SPS_BUSY_OPCODE4_EN_OFFSET            0x41c
-#define GC_SPS_BUSY_OPCODE4_VALUE_LSB            0x1
-#define GC_SPS_BUSY_OPCODE4_VALUE_MASK           0x1fe
-#define GC_SPS_BUSY_OPCODE4_VALUE_SIZE           0x8
-#define GC_SPS_BUSY_OPCODE4_VALUE_DEFAULT        0x0
-#define GC_SPS_BUSY_OPCODE4_VALUE_OFFSET         0x41c
-#define GC_SPS_BUSY_OPCODE5_EN_LSB               0x0
-#define GC_SPS_BUSY_OPCODE5_EN_MASK              0x1
-#define GC_SPS_BUSY_OPCODE5_EN_SIZE              0x1
-#define GC_SPS_BUSY_OPCODE5_EN_DEFAULT           0x0
-#define GC_SPS_BUSY_OPCODE5_EN_OFFSET            0x420
-#define GC_SPS_BUSY_OPCODE5_VALUE_LSB            0x1
-#define GC_SPS_BUSY_OPCODE5_VALUE_MASK           0x1fe
-#define GC_SPS_BUSY_OPCODE5_VALUE_SIZE           0x8
-#define GC_SPS_BUSY_OPCODE5_VALUE_DEFAULT        0x0
-#define GC_SPS_BUSY_OPCODE5_VALUE_OFFSET         0x420
-#define GC_SPS_BUSY_OPCODE6_EN_LSB               0x0
-#define GC_SPS_BUSY_OPCODE6_EN_MASK              0x1
-#define GC_SPS_BUSY_OPCODE6_EN_SIZE              0x1
-#define GC_SPS_BUSY_OPCODE6_EN_DEFAULT           0x0
-#define GC_SPS_BUSY_OPCODE6_EN_OFFSET            0x424
-#define GC_SPS_BUSY_OPCODE6_VALUE_LSB            0x1
-#define GC_SPS_BUSY_OPCODE6_VALUE_MASK           0x1fe
-#define GC_SPS_BUSY_OPCODE6_VALUE_SIZE           0x8
-#define GC_SPS_BUSY_OPCODE6_VALUE_DEFAULT        0x0
-#define GC_SPS_BUSY_OPCODE6_VALUE_OFFSET         0x424
-#define GC_SPS_BUSY_OPCODE7_EN_LSB               0x0
-#define GC_SPS_BUSY_OPCODE7_EN_MASK              0x1
-#define GC_SPS_BUSY_OPCODE7_EN_SIZE              0x1
-#define GC_SPS_BUSY_OPCODE7_EN_DEFAULT           0x0
-#define GC_SPS_BUSY_OPCODE7_EN_OFFSET            0x428
-#define GC_SPS_BUSY_OPCODE7_VALUE_LSB            0x1
-#define GC_SPS_BUSY_OPCODE7_VALUE_MASK           0x1fe
-#define GC_SPS_BUSY_OPCODE7_VALUE_SIZE           0x8
-#define GC_SPS_BUSY_OPCODE7_VALUE_DEFAULT        0x0
-#define GC_SPS_BUSY_OPCODE7_VALUE_OFFSET         0x428
-#define GC_SPS_RAM_CTRL_PAGE0_WRAP_MODE_LSB      0x0
-#define GC_SPS_RAM_CTRL_PAGE0_WRAP_MODE_MASK     0x1
-#define GC_SPS_RAM_CTRL_PAGE0_WRAP_MODE_SIZE     0x1
-#define GC_SPS_RAM_CTRL_PAGE0_WRAP_MODE_DEFAULT  0x0
-#define GC_SPS_RAM_CTRL_PAGE0_WRAP_MODE_OFFSET   0x4dc
-#define GC_SPS_RAM_CTRL_PAGE0_INT_LVL_LSB        0x1
-#define GC_SPS_RAM_CTRL_PAGE0_INT_LVL_MASK       0x3fe
-#define GC_SPS_RAM_CTRL_PAGE0_INT_LVL_SIZE       0x9
-#define GC_SPS_RAM_CTRL_PAGE0_INT_LVL_DEFAULT    0x0
-#define GC_SPS_RAM_CTRL_PAGE0_INT_LVL_OFFSET     0x4dc
-#define GC_SPS_RAM_CTRL_PAGE1_WRAP_MODE_LSB      0x0
-#define GC_SPS_RAM_CTRL_PAGE1_WRAP_MODE_MASK     0x1
-#define GC_SPS_RAM_CTRL_PAGE1_WRAP_MODE_SIZE     0x1
-#define GC_SPS_RAM_CTRL_PAGE1_WRAP_MODE_DEFAULT  0x0
-#define GC_SPS_RAM_CTRL_PAGE1_WRAP_MODE_OFFSET   0x4e0
-#define GC_SPS_RAM_CTRL_PAGE1_INT_LVL_LSB        0x1
-#define GC_SPS_RAM_CTRL_PAGE1_INT_LVL_MASK       0x3fe
-#define GC_SPS_RAM_CTRL_PAGE1_INT_LVL_SIZE       0x9
-#define GC_SPS_RAM_CTRL_PAGE1_INT_LVL_DEFAULT    0x0
-#define GC_SPS_RAM_CTRL_PAGE1_INT_LVL_OFFSET     0x4e0
-#define GC_SPS_RAM_CTRL_PAGE2_WRAP_MODE_LSB      0x0
-#define GC_SPS_RAM_CTRL_PAGE2_WRAP_MODE_MASK     0x1
-#define GC_SPS_RAM_CTRL_PAGE2_WRAP_MODE_SIZE     0x1
-#define GC_SPS_RAM_CTRL_PAGE2_WRAP_MODE_DEFAULT  0x0
-#define GC_SPS_RAM_CTRL_PAGE2_WRAP_MODE_OFFSET   0x4e4
-#define GC_SPS_RAM_CTRL_PAGE2_INT_LVL_LSB        0x1
-#define GC_SPS_RAM_CTRL_PAGE2_INT_LVL_MASK       0x3fe
-#define GC_SPS_RAM_CTRL_PAGE2_INT_LVL_SIZE       0x9
-#define GC_SPS_RAM_CTRL_PAGE2_INT_LVL_DEFAULT    0x0
-#define GC_SPS_RAM_CTRL_PAGE2_INT_LVL_OFFSET     0x4e4
-#define GC_SPS_RAM_CTRL_PAGE3_WRAP_MODE_LSB      0x0
-#define GC_SPS_RAM_CTRL_PAGE3_WRAP_MODE_MASK     0x1
-#define GC_SPS_RAM_CTRL_PAGE3_WRAP_MODE_SIZE     0x1
-#define GC_SPS_RAM_CTRL_PAGE3_WRAP_MODE_DEFAULT  0x0
-#define GC_SPS_RAM_CTRL_PAGE3_WRAP_MODE_OFFSET   0x4e8
-#define GC_SPS_RAM_CTRL_PAGE3_INT_LVL_LSB        0x1
-#define GC_SPS_RAM_CTRL_PAGE3_INT_LVL_MASK       0x3fe
-#define GC_SPS_RAM_CTRL_PAGE3_INT_LVL_SIZE       0x9
-#define GC_SPS_RAM_CTRL_PAGE3_INT_LVL_DEFAULT    0x0
-#define GC_SPS_RAM_CTRL_PAGE3_INT_LVL_OFFSET     0x4e8
-#define GC_SPS_EEPROM_INT_ENABLE_INTR_CMD_ADDR_FIFO_NOT_EMPTY_LSB 0x0
-#define GC_SPS_EEPROM_INT_ENABLE_INTR_CMD_ADDR_FIFO_NOT_EMPTY_MASK 0x1
-#define GC_SPS_EEPROM_INT_ENABLE_INTR_CMD_ADDR_FIFO_NOT_EMPTY_SIZE 0x1
-#define GC_SPS_EEPROM_INT_ENABLE_INTR_CMD_ADDR_FIFO_NOT_EMPTY_DEFAULT 0x0
-#define GC_SPS_EEPROM_INT_ENABLE_INTR_CMD_ADDR_FIFO_NOT_EMPTY_OFFSET 0x578
-#define GC_SPS_EEPROM_INT_ENABLE_INTR_CMD_ADDR_FIFO_OVFL_LSB 0x1
-#define GC_SPS_EEPROM_INT_ENABLE_INTR_CMD_ADDR_FIFO_OVFL_MASK 0x2
-#define GC_SPS_EEPROM_INT_ENABLE_INTR_CMD_ADDR_FIFO_OVFL_SIZE 0x1
-#define GC_SPS_EEPROM_INT_ENABLE_INTR_CMD_ADDR_FIFO_OVFL_DEFAULT 0x0
-#define GC_SPS_EEPROM_INT_ENABLE_INTR_CMD_ADDR_FIFO_OVFL_OFFSET 0x578
-#define GC_SPS_EEPROM_INT_ENABLE_INTR_CMD_MEM_OVFL_LSB 0x2
-#define GC_SPS_EEPROM_INT_ENABLE_INTR_CMD_MEM_OVFL_MASK 0x4
-#define GC_SPS_EEPROM_INT_ENABLE_INTR_CMD_MEM_OVFL_SIZE 0x1
-#define GC_SPS_EEPROM_INT_ENABLE_INTR_CMD_MEM_OVFL_DEFAULT 0x0
-#define GC_SPS_EEPROM_INT_ENABLE_INTR_CMD_MEM_OVFL_OFFSET 0x578
-#define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE0_LVL_LSB 0x3
-#define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE0_LVL_MASK 0x8
-#define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE0_LVL_SIZE 0x1
-#define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE0_LVL_DEFAULT 0x0
-#define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE0_LVL_OFFSET 0x578
-#define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE1_LVL_LSB 0x4
-#define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE1_LVL_MASK 0x10
-#define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE1_LVL_SIZE 0x1
-#define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE1_LVL_DEFAULT 0x0
-#define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE1_LVL_OFFSET 0x578
-#define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE2_LVL_LSB 0x5
-#define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE2_LVL_MASK 0x20
-#define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE2_LVL_SIZE 0x1
-#define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE2_LVL_DEFAULT 0x0
-#define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE2_LVL_OFFSET 0x578
-#define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE3_LVL_LSB 0x6
-#define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE3_LVL_MASK 0x40
-#define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE3_LVL_SIZE 0x1
-#define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE3_LVL_DEFAULT 0x0
-#define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE3_LVL_OFFSET 0x578
-#define GC_SPS_EEPROM_INT_STATE_INTR_CMD_ADDR_FIFO_NOT_EMPTY_LSB 0x0
-#define GC_SPS_EEPROM_INT_STATE_INTR_CMD_ADDR_FIFO_NOT_EMPTY_MASK 0x1
-#define GC_SPS_EEPROM_INT_STATE_INTR_CMD_ADDR_FIFO_NOT_EMPTY_SIZE 0x1
-#define GC_SPS_EEPROM_INT_STATE_INTR_CMD_ADDR_FIFO_NOT_EMPTY_DEFAULT 0x0
-#define GC_SPS_EEPROM_INT_STATE_INTR_CMD_ADDR_FIFO_NOT_EMPTY_OFFSET 0x57c
-#define GC_SPS_EEPROM_INT_STATE_INTR_CMD_ADDR_FIFO_OVFL_LSB 0x1
-#define GC_SPS_EEPROM_INT_STATE_INTR_CMD_ADDR_FIFO_OVFL_MASK 0x2
-#define GC_SPS_EEPROM_INT_STATE_INTR_CMD_ADDR_FIFO_OVFL_SIZE 0x1
-#define GC_SPS_EEPROM_INT_STATE_INTR_CMD_ADDR_FIFO_OVFL_DEFAULT 0x0
-#define GC_SPS_EEPROM_INT_STATE_INTR_CMD_ADDR_FIFO_OVFL_OFFSET 0x57c
-#define GC_SPS_EEPROM_INT_STATE_INTR_CMD_MEM_OVFL_LSB 0x2
-#define GC_SPS_EEPROM_INT_STATE_INTR_CMD_MEM_OVFL_MASK 0x4
-#define GC_SPS_EEPROM_INT_STATE_INTR_CMD_MEM_OVFL_SIZE 0x1
-#define GC_SPS_EEPROM_INT_STATE_INTR_CMD_MEM_OVFL_DEFAULT 0x0
-#define GC_SPS_EEPROM_INT_STATE_INTR_CMD_MEM_OVFL_OFFSET 0x57c
-#define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE0_LVL_LSB 0x3
-#define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE0_LVL_MASK 0x8
-#define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE0_LVL_SIZE 0x1
-#define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE0_LVL_DEFAULT 0x0
-#define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE0_LVL_OFFSET 0x57c
-#define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE1_LVL_LSB 0x4
-#define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE1_LVL_MASK 0x10
-#define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE1_LVL_SIZE 0x1
-#define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE1_LVL_DEFAULT 0x0
-#define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE1_LVL_OFFSET 0x57c
-#define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE2_LVL_LSB 0x5
-#define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE2_LVL_MASK 0x20
-#define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE2_LVL_SIZE 0x1
-#define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE2_LVL_DEFAULT 0x0
-#define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE2_LVL_OFFSET 0x57c
-#define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE3_LVL_LSB 0x6
-#define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE3_LVL_MASK 0x40
-#define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE3_LVL_SIZE 0x1
-#define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE3_LVL_DEFAULT 0x0
-#define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE3_LVL_OFFSET 0x57c
-#define GC_SPS_EEPROM_INT_TEST_INTR_CMD_ADDR_FIFO_NOT_EMPTY_LSB 0x0
-#define GC_SPS_EEPROM_INT_TEST_INTR_CMD_ADDR_FIFO_NOT_EMPTY_MASK 0x1
-#define GC_SPS_EEPROM_INT_TEST_INTR_CMD_ADDR_FIFO_NOT_EMPTY_SIZE 0x1
-#define GC_SPS_EEPROM_INT_TEST_INTR_CMD_ADDR_FIFO_NOT_EMPTY_DEFAULT 0x0
-#define GC_SPS_EEPROM_INT_TEST_INTR_CMD_ADDR_FIFO_NOT_EMPTY_OFFSET 0x580
-#define GC_SPS_EEPROM_INT_TEST_INTR_CMD_ADDR_FIFO_OVFL_LSB 0x1
-#define GC_SPS_EEPROM_INT_TEST_INTR_CMD_ADDR_FIFO_OVFL_MASK 0x2
-#define GC_SPS_EEPROM_INT_TEST_INTR_CMD_ADDR_FIFO_OVFL_SIZE 0x1
-#define GC_SPS_EEPROM_INT_TEST_INTR_CMD_ADDR_FIFO_OVFL_DEFAULT 0x0
-#define GC_SPS_EEPROM_INT_TEST_INTR_CMD_ADDR_FIFO_OVFL_OFFSET 0x580
-#define GC_SPS_EEPROM_INT_TEST_INTR_CMD_MEM_OVFL_LSB 0x2
-#define GC_SPS_EEPROM_INT_TEST_INTR_CMD_MEM_OVFL_MASK 0x4
-#define GC_SPS_EEPROM_INT_TEST_INTR_CMD_MEM_OVFL_SIZE 0x1
-#define GC_SPS_EEPROM_INT_TEST_INTR_CMD_MEM_OVFL_DEFAULT 0x0
-#define GC_SPS_EEPROM_INT_TEST_INTR_CMD_MEM_OVFL_OFFSET 0x580
-#define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE0_LVL_LSB 0x3
-#define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE0_LVL_MASK 0x8
-#define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE0_LVL_SIZE 0x1
-#define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE0_LVL_DEFAULT 0x0
-#define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE0_LVL_OFFSET 0x580
-#define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE1_LVL_LSB 0x4
-#define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE1_LVL_MASK 0x10
-#define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE1_LVL_SIZE 0x1
-#define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE1_LVL_DEFAULT 0x0
-#define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE1_LVL_OFFSET 0x580
-#define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE2_LVL_LSB 0x5
-#define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE2_LVL_MASK 0x20
-#define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE2_LVL_SIZE 0x1
-#define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE2_LVL_DEFAULT 0x0
-#define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE2_LVL_OFFSET 0x580
-#define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE3_LVL_LSB 0x6
-#define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE3_LVL_MASK 0x40
-#define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE3_LVL_SIZE 0x1
-#define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE3_LVL_DEFAULT 0x0
-#define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE3_LVL_OFFSET 0x580
-#define GC_SWDP_TEST_PORT_DISABLE_SWD_LSB        0x0
-#define GC_SWDP_TEST_PORT_DISABLE_SWD_MASK       0x1
-#define GC_SWDP_TEST_PORT_DISABLE_SWD_SIZE       0x1
-#define GC_SWDP_TEST_PORT_DISABLE_SWD_DEFAULT    0x0
-#define GC_SWDP_TEST_PORT_DISABLE_SWD_OFFSET     0x38
-#define GC_SWDP_TEST_PORT_DISABLE_TAP_LSB        0x1
-#define GC_SWDP_TEST_PORT_DISABLE_TAP_MASK       0x2
-#define GC_SWDP_TEST_PORT_DISABLE_TAP_SIZE       0x1
-#define GC_SWDP_TEST_PORT_DISABLE_TAP_DEFAULT    0x0
-#define GC_SWDP_TEST_PORT_DISABLE_TAP_OFFSET     0x38
-#define GC_TEMP_VERSION_CHANGE_LSB               0x0
-#define GC_TEMP_VERSION_CHANGE_MASK              0xffffff
-#define GC_TEMP_VERSION_CHANGE_SIZE              0x18
-#define GC_TEMP_VERSION_CHANGE_DEFAULT           0x14125
-#define GC_TEMP_VERSION_CHANGE_OFFSET            0x0
-#define GC_TEMP_VERSION_REVISION_LSB             0x18
-#define GC_TEMP_VERSION_REVISION_MASK            0xff000000
-#define GC_TEMP_VERSION_REVISION_SIZE            0x8
-#define GC_TEMP_VERSION_REVISION_DEFAULT         0x1
-#define GC_TEMP_VERSION_REVISION_OFFSET          0x0
-#define GC_TEMP_ADC_INT_ENABLE_ADC_ICLKDV_LSB    0x0
-#define GC_TEMP_ADC_INT_ENABLE_ADC_ICLKDV_MASK   0x1
-#define GC_TEMP_ADC_INT_ENABLE_ADC_ICLKDV_SIZE   0x1
-#define GC_TEMP_ADC_INT_ENABLE_ADC_ICLKDV_DEFAULT 0x0
-#define GC_TEMP_ADC_INT_ENABLE_ADC_ICLKDV_OFFSET 0x4
-#define GC_TEMP_ADC_INT_ENABLE_COMP_OVERFLOW_LSB 0x1
-#define GC_TEMP_ADC_INT_ENABLE_COMP_OVERFLOW_MASK 0x2
-#define GC_TEMP_ADC_INT_ENABLE_COMP_OVERFLOW_SIZE 0x1
-#define GC_TEMP_ADC_INT_ENABLE_COMP_OVERFLOW_DEFAULT 0x0
-#define GC_TEMP_ADC_INT_ENABLE_COMP_OVERFLOW_OFFSET 0x4
-#define GC_TEMP_ADC_INT_STATE_ADC_ICLKDV_LSB     0x0
-#define GC_TEMP_ADC_INT_STATE_ADC_ICLKDV_MASK    0x1
-#define GC_TEMP_ADC_INT_STATE_ADC_ICLKDV_SIZE    0x1
-#define GC_TEMP_ADC_INT_STATE_ADC_ICLKDV_DEFAULT 0x0
-#define GC_TEMP_ADC_INT_STATE_ADC_ICLKDV_OFFSET  0x8
-#define GC_TEMP_ADC_INT_STATE_COMP_OVERFLOW_LSB  0x1
-#define GC_TEMP_ADC_INT_STATE_COMP_OVERFLOW_MASK 0x2
-#define GC_TEMP_ADC_INT_STATE_COMP_OVERFLOW_SIZE 0x1
-#define GC_TEMP_ADC_INT_STATE_COMP_OVERFLOW_DEFAULT 0x0
-#define GC_TEMP_ADC_INT_STATE_COMP_OVERFLOW_OFFSET 0x8
-#define GC_TEMP_ADC_INT_TEST_ADC_ICLKDV_LSB      0x0
-#define GC_TEMP_ADC_INT_TEST_ADC_ICLKDV_MASK     0x1
-#define GC_TEMP_ADC_INT_TEST_ADC_ICLKDV_SIZE     0x1
-#define GC_TEMP_ADC_INT_TEST_ADC_ICLKDV_DEFAULT  0x0
-#define GC_TEMP_ADC_INT_TEST_ADC_ICLKDV_OFFSET   0xc
-#define GC_TEMP_ADC_INT_TEST_COMP_OVERFLOW_LSB   0x1
-#define GC_TEMP_ADC_INT_TEST_COMP_OVERFLOW_MASK  0x2
-#define GC_TEMP_ADC_INT_TEST_COMP_OVERFLOW_SIZE  0x1
-#define GC_TEMP_ADC_INT_TEST_COMP_OVERFLOW_DEFAULT 0x0
-#define GC_TEMP_ADC_INT_TEST_COMP_OVERFLOW_OFFSET 0xc
-#define GC_TEMP_ADC_ANALOG_CTRL_REFERENCE_LSB    0x0
-#define GC_TEMP_ADC_ANALOG_CTRL_REFERENCE_MASK   0x7
-#define GC_TEMP_ADC_ANALOG_CTRL_REFERENCE_SIZE   0x3
-#define GC_TEMP_ADC_ANALOG_CTRL_REFERENCE_DEFAULT 0x5
-#define GC_TEMP_ADC_ANALOG_CTRL_REFERENCE_OFFSET 0x14
-#define GC_TEMP_ADC_ANALOG_CTRL_REFERENCE_0P906V 0x3
-#define GC_TEMP_ADC_ANALOG_CTRL_REFERENCE_1P120V 0x6
-#define GC_TEMP_ADC_ANALOG_CTRL_REFERENCE_0P763V 0x1
-#define GC_TEMP_ADC_ANALOG_CTRL_REFERENCE_0P691V 0x0
-#define GC_TEMP_ADC_ANALOG_CTRL_REFERENCE_1P192V 0x7
-#define GC_TEMP_ADC_ANALOG_CTRL_REFERENCE_0P977V 0x4
-#define GC_TEMP_ADC_ANALOG_CTRL_REFERENCE_1P049V 0x5
-#define GC_TEMP_ADC_ANALOG_CTRL_REFERENCE_0P834V 0x2
-#define GC_TEMP_ADC_ANALOG_CTRL_COMMON_MODE_LSB  0x4
-#define GC_TEMP_ADC_ANALOG_CTRL_COMMON_MODE_MASK 0x70
-#define GC_TEMP_ADC_ANALOG_CTRL_COMMON_MODE_SIZE 0x3
-#define GC_TEMP_ADC_ANALOG_CTRL_COMMON_MODE_DEFAULT 0x3
-#define GC_TEMP_ADC_ANALOG_CTRL_COMMON_MODE_OFFSET 0x14
-#define GC_TEMP_ADC_ANALOG_CTRL_COMMON_MODE_0P429V 0x2
-#define GC_TEMP_ADC_ANALOG_CTRL_COMMON_MODE_0P477V 0x3
-#define GC_TEMP_ADC_ANALOG_CTRL_COMMON_MODE_0P382V 0x1
-#define GC_TEMP_ADC_ANALOG_CTRL_COMMON_MODE_0P572V 0x5
-#define GC_TEMP_ADC_ANALOG_CTRL_COMMON_MODE_0P524V 0x4
-#define GC_TEMP_ADC_FSM_CTRL_SYNC_IQ_LSB         0x0
-#define GC_TEMP_ADC_FSM_CTRL_SYNC_IQ_MASK        0x1
-#define GC_TEMP_ADC_FSM_CTRL_SYNC_IQ_SIZE        0x1
-#define GC_TEMP_ADC_FSM_CTRL_SYNC_IQ_DEFAULT     0x0
-#define GC_TEMP_ADC_FSM_CTRL_SYNC_IQ_OFFSET      0x18
-#define GC_TEMP_ADC_FSM_CTRL_ONESHOT_MODE_LSB    0x1
-#define GC_TEMP_ADC_FSM_CTRL_ONESHOT_MODE_MASK   0x2
-#define GC_TEMP_ADC_FSM_CTRL_ONESHOT_MODE_SIZE   0x1
-#define GC_TEMP_ADC_FSM_CTRL_ONESHOT_MODE_DEFAULT 0x0
-#define GC_TEMP_ADC_FSM_CTRL_ONESHOT_MODE_OFFSET 0x18
-#define GC_TEMP_ADC_FSM_CTRL_SINGLE_MODE_LSB     0x2
-#define GC_TEMP_ADC_FSM_CTRL_SINGLE_MODE_MASK    0x4
-#define GC_TEMP_ADC_FSM_CTRL_SINGLE_MODE_SIZE    0x1
-#define GC_TEMP_ADC_FSM_CTRL_SINGLE_MODE_DEFAULT 0x1
-#define GC_TEMP_ADC_FSM_CTRL_SINGLE_MODE_OFFSET  0x18
-#define GC_TEMP_ADC_FSM_CTRL_SINGLE_SIDE_LSB     0x3
-#define GC_TEMP_ADC_FSM_CTRL_SINGLE_SIDE_MASK    0x8
-#define GC_TEMP_ADC_FSM_CTRL_SINGLE_SIDE_SIZE    0x1
-#define GC_TEMP_ADC_FSM_CTRL_SINGLE_SIDE_DEFAULT 0x0
-#define GC_TEMP_ADC_FSM_CTRL_SINGLE_SIDE_OFFSET  0x18
-#define GC_TEMP_ADC_FSM_CTRL_MUX_CTRL_LSB        0x4
-#define GC_TEMP_ADC_FSM_CTRL_MUX_CTRL_MASK       0x70
-#define GC_TEMP_ADC_FSM_CTRL_MUX_CTRL_SIZE       0x3
-#define GC_TEMP_ADC_FSM_CTRL_MUX_CTRL_DEFAULT    0x6
-#define GC_TEMP_ADC_FSM_CTRL_MUX_CTRL_OFFSET     0x18
-#define GC_TEMP_ADC_FSM_CTRL_MUX_CTRL_ADC_INP_N5 0x5
-#define GC_TEMP_ADC_FSM_CTRL_MUX_CTRL_ADC_INP_N4 0x4
-#define GC_TEMP_ADC_FSM_CTRL_MUX_CTRL_ADC_INP_N3 0x3
-#define GC_TEMP_ADC_FSM_CTRL_MUX_CTRL_ADC_INP_N2 0x2
-#define GC_TEMP_ADC_FSM_CTRL_MUX_CTRL_ADC_INP_N1 0x1
-#define GC_TEMP_ADC_FSM_CTRL_MUX_CTRL_ADC_INP_N0 0x0
-#define GC_TEMP_ADC_FSM_CTRL_MUX_CTRL_VPTAT_CORE 0x6
-#define GC_TEMP_ADC_FSM_CTRL_MUX_CTRL_ANALOG_TEST_BUS 0x7
-#define GC_TEMP_ADC_FSM_CTRL_SMPL_DUR_FINE_LSB   0x7
-#define GC_TEMP_ADC_FSM_CTRL_SMPL_DUR_FINE_MASK  0x780
-#define GC_TEMP_ADC_FSM_CTRL_SMPL_DUR_FINE_SIZE  0x4
-#define GC_TEMP_ADC_FSM_CTRL_SMPL_DUR_FINE_DEFAULT 0x0
-#define GC_TEMP_ADC_FSM_CTRL_SMPL_DUR_FINE_OFFSET 0x18
-#define GC_TEMP_ADC_FSM_CTRL_SMPL_DUR_COARSE_LSB 0xb
-#define GC_TEMP_ADC_FSM_CTRL_SMPL_DUR_COARSE_MASK 0x7800
-#define GC_TEMP_ADC_FSM_CTRL_SMPL_DUR_COARSE_SIZE 0x4
-#define GC_TEMP_ADC_FSM_CTRL_SMPL_DUR_COARSE_DEFAULT 0x1
-#define GC_TEMP_ADC_FSM_CTRL_SMPL_DUR_COARSE_OFFSET 0x18
-#define GC_TEMP_ADC_FSM_CTRL_CHOP_REFBUF_AMP_LSB 0xf
-#define GC_TEMP_ADC_FSM_CTRL_CHOP_REFBUF_AMP_MASK 0x8000
-#define GC_TEMP_ADC_FSM_CTRL_CHOP_REFBUF_AMP_SIZE 0x1
-#define GC_TEMP_ADC_FSM_CTRL_CHOP_REFBUF_AMP_DEFAULT 0x1
-#define GC_TEMP_ADC_FSM_CTRL_CHOP_REFBUF_AMP_OFFSET 0x18
-#define GC_TEMP_ADC_FSM_CTRL_CHOP_CURRENT_MIRROR_LSB 0x10
-#define GC_TEMP_ADC_FSM_CTRL_CHOP_CURRENT_MIRROR_MASK 0x10000
-#define GC_TEMP_ADC_FSM_CTRL_CHOP_CURRENT_MIRROR_SIZE 0x1
-#define GC_TEMP_ADC_FSM_CTRL_CHOP_CURRENT_MIRROR_DEFAULT 0x1
-#define GC_TEMP_ADC_FSM_CTRL_CHOP_CURRENT_MIRROR_OFFSET 0x18
-#define GC_TEMP_ADC_FSM_CTRL_CHOP_FEEDBACK_AMP_LSB 0x11
-#define GC_TEMP_ADC_FSM_CTRL_CHOP_FEEDBACK_AMP_MASK 0x20000
-#define GC_TEMP_ADC_FSM_CTRL_CHOP_FEEDBACK_AMP_SIZE 0x1
-#define GC_TEMP_ADC_FSM_CTRL_CHOP_FEEDBACK_AMP_DEFAULT 0x1
-#define GC_TEMP_ADC_FSM_CTRL_CHOP_FEEDBACK_AMP_OFFSET 0x18
-#define GC_TEMP_ADC_OPERATION_RESET_B_LSB        0x0
-#define GC_TEMP_ADC_OPERATION_RESET_B_MASK       0x1
-#define GC_TEMP_ADC_OPERATION_RESET_B_SIZE       0x1
-#define GC_TEMP_ADC_OPERATION_RESET_B_DEFAULT    0x0
-#define GC_TEMP_ADC_OPERATION_RESET_B_OFFSET     0x28
-#define GC_TEMP_ADC_OPERATION_ENABLE_LSB         0x1
-#define GC_TEMP_ADC_OPERATION_ENABLE_MASK        0x2
-#define GC_TEMP_ADC_OPERATION_ENABLE_SIZE        0x1
-#define GC_TEMP_ADC_OPERATION_ENABLE_DEFAULT     0x0
-#define GC_TEMP_ADC_OPERATION_ENABLE_OFFSET      0x28
-#define GC_TEMP_ADC_CONFIG_SAMPLE_SELECT_LSB     0x0
-#define GC_TEMP_ADC_CONFIG_SAMPLE_SELECT_MASK    0x3
-#define GC_TEMP_ADC_CONFIG_SAMPLE_SELECT_SIZE    0x2
-#define GC_TEMP_ADC_CONFIG_SAMPLE_SELECT_DEFAULT 0x0
-#define GC_TEMP_ADC_CONFIG_SAMPLE_SELECT_OFFSET  0x40
-#define GC_TEMP_ADC_CONFIG_SAMPLE_SELECT_ADC_SUM2 0x1
-#define GC_TEMP_ADC_CONFIG_SAMPLE_SELECT_ADC_IOUT 0x0
-#define GC_TEMP_ADC_CONFIG_SAMPLE_SELECT_ADC_SUM8 0x3
-#define GC_TEMP_ADC_CONFIG_SAMPLE_SELECT_ADC_SUM4 0x2
-#define GC_TEMP_ABS_LIMIT_MIN_LSB                0x0
-#define GC_TEMP_ABS_LIMIT_MIN_MASK               0xfff
-#define GC_TEMP_ABS_LIMIT_MIN_SIZE               0xc
-#define GC_TEMP_ABS_LIMIT_MIN_DEFAULT            0x0
-#define GC_TEMP_ABS_LIMIT_MIN_OFFSET             0x44
-#define GC_TEMP_ABS_LIMIT_MAX_LSB                0xc
-#define GC_TEMP_ABS_LIMIT_MAX_MASK               0xfff000
-#define GC_TEMP_ABS_LIMIT_MAX_SIZE               0xc
-#define GC_TEMP_ABS_LIMIT_MAX_DEFAULT            0x0
-#define GC_TEMP_ABS_LIMIT_MAX_OFFSET             0x44
-#define GC_TEMP_DIFF_PARAM_MAX_LSB               0x0
-#define GC_TEMP_DIFF_PARAM_MAX_MASK              0xfff
-#define GC_TEMP_DIFF_PARAM_MAX_SIZE              0xc
-#define GC_TEMP_DIFF_PARAM_MAX_DEFAULT           0x0
-#define GC_TEMP_DIFF_PARAM_MAX_OFFSET            0x48
-#define GC_TEMP_DIFF_PARAM_PERIOD_LSB            0xc
-#define GC_TEMP_DIFF_PARAM_PERIOD_MASK           0xfffff000
-#define GC_TEMP_DIFF_PARAM_PERIOD_SIZE           0x14
-#define GC_TEMP_DIFF_PARAM_PERIOD_DEFAULT        0x0
-#define GC_TEMP_DIFF_PARAM_PERIOD_OFFSET         0x48
-#define GC_TEMP_METRIC_DIFF_LSB                  0x0
-#define GC_TEMP_METRIC_DIFF_MASK                 0xfff
-#define GC_TEMP_METRIC_DIFF_SIZE                 0xc
-#define GC_TEMP_METRIC_DIFF_DEFAULT              0x0
-#define GC_TEMP_METRIC_DIFF_OFFSET               0x4c
-#define GC_TEMP_METRIC_CTR_LSB                   0xc
-#define GC_TEMP_METRIC_CTR_MASK                  0xfffff000
-#define GC_TEMP_METRIC_CTR_SIZE                  0x14
-#define GC_TEMP_METRIC_CTR_DEFAULT               0x0
-#define GC_TEMP_METRIC_CTR_OFFSET                0x4c
-#define GC_TEMP_ANTEST_EN_INPUTS_LSB             0x0
-#define GC_TEMP_ANTEST_EN_INPUTS_MASK            0x1
-#define GC_TEMP_ANTEST_EN_INPUTS_SIZE            0x1
-#define GC_TEMP_ANTEST_EN_INPUTS_DEFAULT         0x0
-#define GC_TEMP_ANTEST_EN_INPUTS_OFFSET          0x54
-#define GC_TEMP_ANTEST_EN_REF_LSB                0x1
-#define GC_TEMP_ANTEST_EN_REF_MASK               0x2
-#define GC_TEMP_ANTEST_EN_REF_SIZE               0x1
-#define GC_TEMP_ANTEST_EN_REF_DEFAULT            0x0
-#define GC_TEMP_ANTEST_EN_REF_OFFSET             0x54
-#define GC_TEMP_ANTEST_EN_VPTAT_LSB              0x2
-#define GC_TEMP_ANTEST_EN_VPTAT_MASK             0x4
-#define GC_TEMP_ANTEST_EN_VPTAT_SIZE             0x1
-#define GC_TEMP_ANTEST_EN_VPTAT_DEFAULT          0x0
-#define GC_TEMP_ANTEST_EN_VPTAT_OFFSET           0x54
-#define GC_TEMP_ANTEST_EN_CM_LSB                 0x3
-#define GC_TEMP_ANTEST_EN_CM_MASK                0x8
-#define GC_TEMP_ANTEST_EN_CM_SIZE                0x1
-#define GC_TEMP_ANTEST_EN_CM_DEFAULT             0x0
-#define GC_TEMP_ANTEST_EN_CM_OFFSET              0x54
-#define GC_TIMEHS_TIMER1CONTROL_ONESHOT_LSB      0x0
-#define GC_TIMEHS_TIMER1CONTROL_ONESHOT_MASK     0x1
-#define GC_TIMEHS_TIMER1CONTROL_ONESHOT_SIZE     0x1
-#define GC_TIMEHS_TIMER1CONTROL_ONESHOT_DEFAULT  0x0
-#define GC_TIMEHS_TIMER1CONTROL_ONESHOT_OFFSET   0x8
-#define GC_TIMEHS_TIMER1CONTROL_SIZE_LSB         0x1
-#define GC_TIMEHS_TIMER1CONTROL_SIZE_MASK        0x2
-#define GC_TIMEHS_TIMER1CONTROL_SIZE_SIZE        0x1
-#define GC_TIMEHS_TIMER1CONTROL_SIZE_DEFAULT     0x0
-#define GC_TIMEHS_TIMER1CONTROL_SIZE_OFFSET      0x8
-#define GC_TIMEHS_TIMER1CONTROL_PRE_LSB          0x2
-#define GC_TIMEHS_TIMER1CONTROL_PRE_MASK         0xc
-#define GC_TIMEHS_TIMER1CONTROL_PRE_SIZE         0x2
-#define GC_TIMEHS_TIMER1CONTROL_PRE_DEFAULT      0x0
-#define GC_TIMEHS_TIMER1CONTROL_PRE_OFFSET       0x8
-#define GC_TIMEHS_TIMER1CONTROL_RESERVED_LSB     0x4
-#define GC_TIMEHS_TIMER1CONTROL_RESERVED_MASK    0x10
-#define GC_TIMEHS_TIMER1CONTROL_RESERVED_SIZE    0x1
-#define GC_TIMEHS_TIMER1CONTROL_RESERVED_DEFAULT 0x0
-#define GC_TIMEHS_TIMER1CONTROL_RESERVED_OFFSET  0x8
-#define GC_TIMEHS_TIMER1CONTROL_INTENABLE_LSB    0x5
-#define GC_TIMEHS_TIMER1CONTROL_INTENABLE_MASK   0x20
-#define GC_TIMEHS_TIMER1CONTROL_INTENABLE_SIZE   0x1
-#define GC_TIMEHS_TIMER1CONTROL_INTENABLE_DEFAULT 0x1
-#define GC_TIMEHS_TIMER1CONTROL_INTENABLE_OFFSET 0x8
-#define GC_TIMEHS_TIMER1CONTROL_MODE_LSB         0x6
-#define GC_TIMEHS_TIMER1CONTROL_MODE_MASK        0x40
-#define GC_TIMEHS_TIMER1CONTROL_MODE_SIZE        0x1
-#define GC_TIMEHS_TIMER1CONTROL_MODE_DEFAULT     0x0
-#define GC_TIMEHS_TIMER1CONTROL_MODE_OFFSET      0x8
-#define GC_TIMEHS_TIMER1CONTROL_ENABLE_LSB       0x7
-#define GC_TIMEHS_TIMER1CONTROL_ENABLE_MASK      0x80
-#define GC_TIMEHS_TIMER1CONTROL_ENABLE_SIZE      0x1
-#define GC_TIMEHS_TIMER1CONTROL_ENABLE_DEFAULT   0x0
-#define GC_TIMEHS_TIMER1CONTROL_ENABLE_OFFSET    0x8
-#define GC_TIMEHS_TIMER2CONTROL_ONESHOT_LSB      0x0
-#define GC_TIMEHS_TIMER2CONTROL_ONESHOT_MASK     0x1
-#define GC_TIMEHS_TIMER2CONTROL_ONESHOT_SIZE     0x1
-#define GC_TIMEHS_TIMER2CONTROL_ONESHOT_DEFAULT  0x0
-#define GC_TIMEHS_TIMER2CONTROL_ONESHOT_OFFSET   0x28
-#define GC_TIMEHS_TIMER2CONTROL_SIZE_LSB         0x1
-#define GC_TIMEHS_TIMER2CONTROL_SIZE_MASK        0x2
-#define GC_TIMEHS_TIMER2CONTROL_SIZE_SIZE        0x1
-#define GC_TIMEHS_TIMER2CONTROL_SIZE_DEFAULT     0x0
-#define GC_TIMEHS_TIMER2CONTROL_SIZE_OFFSET      0x28
-#define GC_TIMEHS_TIMER2CONTROL_PRE_LSB          0x2
-#define GC_TIMEHS_TIMER2CONTROL_PRE_MASK         0xc
-#define GC_TIMEHS_TIMER2CONTROL_PRE_SIZE         0x2
-#define GC_TIMEHS_TIMER2CONTROL_PRE_DEFAULT      0x0
-#define GC_TIMEHS_TIMER2CONTROL_PRE_OFFSET       0x28
-#define GC_TIMEHS_TIMER2CONTROL_RESERVED_LSB     0x4
-#define GC_TIMEHS_TIMER2CONTROL_RESERVED_MASK    0x10
-#define GC_TIMEHS_TIMER2CONTROL_RESERVED_SIZE    0x1
-#define GC_TIMEHS_TIMER2CONTROL_RESERVED_DEFAULT 0x0
-#define GC_TIMEHS_TIMER2CONTROL_RESERVED_OFFSET  0x28
-#define GC_TIMEHS_TIMER2CONTROL_INTENABLE_LSB    0x5
-#define GC_TIMEHS_TIMER2CONTROL_INTENABLE_MASK   0x20
-#define GC_TIMEHS_TIMER2CONTROL_INTENABLE_SIZE   0x1
-#define GC_TIMEHS_TIMER2CONTROL_INTENABLE_DEFAULT 0x1
-#define GC_TIMEHS_TIMER2CONTROL_INTENABLE_OFFSET 0x28
-#define GC_TIMEHS_TIMER2CONTROL_MODE_LSB         0x6
-#define GC_TIMEHS_TIMER2CONTROL_MODE_MASK        0x40
-#define GC_TIMEHS_TIMER2CONTROL_MODE_SIZE        0x1
-#define GC_TIMEHS_TIMER2CONTROL_MODE_DEFAULT     0x0
-#define GC_TIMEHS_TIMER2CONTROL_MODE_OFFSET      0x28
-#define GC_TIMEHS_TIMER2CONTROL_ENABLE_LSB       0x7
-#define GC_TIMEHS_TIMER2CONTROL_ENABLE_MASK      0x80
-#define GC_TIMEHS_TIMER2CONTROL_ENABLE_SIZE      0x1
-#define GC_TIMEHS_TIMER2CONTROL_ENABLE_DEFAULT   0x0
-#define GC_TIMEHS_TIMER2CONTROL_ENABLE_OFFSET    0x28
-#define GC_TIMEHS_TIMERITOP_TIMINT1_LSB          0x0
-#define GC_TIMEHS_TIMERITOP_TIMINT1_MASK         0x1
-#define GC_TIMEHS_TIMERITOP_TIMINT1_SIZE         0x1
-#define GC_TIMEHS_TIMERITOP_TIMINT1_DEFAULT      0x0
-#define GC_TIMEHS_TIMERITOP_TIMINT1_OFFSET       0xf04
-#define GC_TIMEHS_TIMERITOP_TIMINT2_LSB          0x1
-#define GC_TIMEHS_TIMERITOP_TIMINT2_MASK         0x2
-#define GC_TIMEHS_TIMERITOP_TIMINT2_SIZE         0x1
-#define GC_TIMEHS_TIMERITOP_TIMINT2_DEFAULT      0x0
-#define GC_TIMEHS_TIMERITOP_TIMINT2_OFFSET       0xf04
-#define GC_TIMELS_TIMER0_CONTROL_ENABLE_LSB      0x0
-#define GC_TIMELS_TIMER0_CONTROL_ENABLE_MASK     0x1
-#define GC_TIMELS_TIMER0_CONTROL_ENABLE_SIZE     0x1
-#define GC_TIMELS_TIMER0_CONTROL_ENABLE_DEFAULT  0x0
-#define GC_TIMELS_TIMER0_CONTROL_ENABLE_OFFSET   0x0
-#define GC_TIMELS_TIMER0_CONTROL_RELOAD_LSB      0x1
-#define GC_TIMELS_TIMER0_CONTROL_RELOAD_MASK     0x2
-#define GC_TIMELS_TIMER0_CONTROL_RELOAD_SIZE     0x1
-#define GC_TIMELS_TIMER0_CONTROL_RELOAD_DEFAULT  0x0
-#define GC_TIMELS_TIMER0_CONTROL_RELOAD_OFFSET   0x0
-#define GC_TIMELS_TIMER0_CONTROL_WRAP_LSB        0x2
-#define GC_TIMELS_TIMER0_CONTROL_WRAP_MASK       0x4
-#define GC_TIMELS_TIMER0_CONTROL_WRAP_SIZE       0x1
-#define GC_TIMELS_TIMER0_CONTROL_WRAP_DEFAULT    0x0
-#define GC_TIMELS_TIMER0_CONTROL_WRAP_OFFSET     0x0
-#define GC_TIMELS_TIMER0_CONTROL_TEST_LSB        0x3
-#define GC_TIMELS_TIMER0_CONTROL_TEST_MASK       0x8
-#define GC_TIMELS_TIMER0_CONTROL_TEST_SIZE       0x1
-#define GC_TIMELS_TIMER0_CONTROL_TEST_DEFAULT    0x0
-#define GC_TIMELS_TIMER0_CONTROL_TEST_OFFSET     0x0
-#define GC_TIMELS_TIMER0_STATUS_SYNCING_LOAD_LSB 0x0
-#define GC_TIMELS_TIMER0_STATUS_SYNCING_LOAD_MASK 0x1
-#define GC_TIMELS_TIMER0_STATUS_SYNCING_LOAD_SIZE 0x1
-#define GC_TIMELS_TIMER0_STATUS_SYNCING_LOAD_DEFAULT 0x0
-#define GC_TIMELS_TIMER0_STATUS_SYNCING_LOAD_OFFSET 0x4
-#define GC_TIMELS_TIMER0_STATUS_WAITING_LOAD_LSB 0x1
-#define GC_TIMELS_TIMER0_STATUS_WAITING_LOAD_MASK 0x2
-#define GC_TIMELS_TIMER0_STATUS_WAITING_LOAD_SIZE 0x1
-#define GC_TIMELS_TIMER0_STATUS_WAITING_LOAD_DEFAULT 0x0
-#define GC_TIMELS_TIMER0_STATUS_WAITING_LOAD_OFFSET 0x4
-#define GC_TIMELS_TIMER0_STATUS_PENDING_LOAD_LSB 0x2
-#define GC_TIMELS_TIMER0_STATUS_PENDING_LOAD_MASK 0x4
-#define GC_TIMELS_TIMER0_STATUS_PENDING_LOAD_SIZE 0x1
-#define GC_TIMELS_TIMER0_STATUS_PENDING_LOAD_DEFAULT 0x0
-#define GC_TIMELS_TIMER0_STATUS_PENDING_LOAD_OFFSET 0x4
-#define GC_TIMELS_TIMER0_STATUS_SYNCING_RELOAD_LSB 0x3
-#define GC_TIMELS_TIMER0_STATUS_SYNCING_RELOAD_MASK 0x8
-#define GC_TIMELS_TIMER0_STATUS_SYNCING_RELOAD_SIZE 0x1
-#define GC_TIMELS_TIMER0_STATUS_SYNCING_RELOAD_DEFAULT 0x0
-#define GC_TIMELS_TIMER0_STATUS_SYNCING_RELOAD_OFFSET 0x4
-#define GC_TIMELS_TIMER0_STATUS_WAITING_RELOAD_LSB 0x4
-#define GC_TIMELS_TIMER0_STATUS_WAITING_RELOAD_MASK 0x10
-#define GC_TIMELS_TIMER0_STATUS_WAITING_RELOAD_SIZE 0x1
-#define GC_TIMELS_TIMER0_STATUS_WAITING_RELOAD_DEFAULT 0x0
-#define GC_TIMELS_TIMER0_STATUS_WAITING_RELOAD_OFFSET 0x4
-#define GC_TIMELS_TIMER0_STATUS_PENDING_RELOAD_LSB 0x5
-#define GC_TIMELS_TIMER0_STATUS_PENDING_RELOAD_MASK 0x20
-#define GC_TIMELS_TIMER0_STATUS_PENDING_RELOAD_SIZE 0x1
-#define GC_TIMELS_TIMER0_STATUS_PENDING_RELOAD_DEFAULT 0x0
-#define GC_TIMELS_TIMER0_STATUS_PENDING_RELOAD_OFFSET 0x4
-#define GC_TIMELS_TIMER0_STATUS_WRAPPED_LSB      0x6
-#define GC_TIMELS_TIMER0_STATUS_WRAPPED_MASK     0x40
-#define GC_TIMELS_TIMER0_STATUS_WRAPPED_SIZE     0x1
-#define GC_TIMELS_TIMER0_STATUS_WRAPPED_DEFAULT  0x0
-#define GC_TIMELS_TIMER0_STATUS_WRAPPED_OFFSET   0x4
-#define GC_TIMELS_TIMER1_CONTROL_ENABLE_LSB      0x0
-#define GC_TIMELS_TIMER1_CONTROL_ENABLE_MASK     0x1
-#define GC_TIMELS_TIMER1_CONTROL_ENABLE_SIZE     0x1
-#define GC_TIMELS_TIMER1_CONTROL_ENABLE_DEFAULT  0x0
-#define GC_TIMELS_TIMER1_CONTROL_ENABLE_OFFSET   0x40
-#define GC_TIMELS_TIMER1_CONTROL_RELOAD_LSB      0x1
-#define GC_TIMELS_TIMER1_CONTROL_RELOAD_MASK     0x2
-#define GC_TIMELS_TIMER1_CONTROL_RELOAD_SIZE     0x1
-#define GC_TIMELS_TIMER1_CONTROL_RELOAD_DEFAULT  0x0
-#define GC_TIMELS_TIMER1_CONTROL_RELOAD_OFFSET   0x40
-#define GC_TIMELS_TIMER1_CONTROL_WRAP_LSB        0x2
-#define GC_TIMELS_TIMER1_CONTROL_WRAP_MASK       0x4
-#define GC_TIMELS_TIMER1_CONTROL_WRAP_SIZE       0x1
-#define GC_TIMELS_TIMER1_CONTROL_WRAP_DEFAULT    0x0
-#define GC_TIMELS_TIMER1_CONTROL_WRAP_OFFSET     0x40
-#define GC_TIMELS_TIMER1_CONTROL_TEST_LSB        0x3
-#define GC_TIMELS_TIMER1_CONTROL_TEST_MASK       0x8
-#define GC_TIMELS_TIMER1_CONTROL_TEST_SIZE       0x1
-#define GC_TIMELS_TIMER1_CONTROL_TEST_DEFAULT    0x0
-#define GC_TIMELS_TIMER1_CONTROL_TEST_OFFSET     0x40
-#define GC_TIMELS_TIMER1_STATUS_SYNCING_LOAD_LSB 0x0
-#define GC_TIMELS_TIMER1_STATUS_SYNCING_LOAD_MASK 0x1
-#define GC_TIMELS_TIMER1_STATUS_SYNCING_LOAD_SIZE 0x1
-#define GC_TIMELS_TIMER1_STATUS_SYNCING_LOAD_DEFAULT 0x0
-#define GC_TIMELS_TIMER1_STATUS_SYNCING_LOAD_OFFSET 0x44
-#define GC_TIMELS_TIMER1_STATUS_WAITING_LOAD_LSB 0x1
-#define GC_TIMELS_TIMER1_STATUS_WAITING_LOAD_MASK 0x2
-#define GC_TIMELS_TIMER1_STATUS_WAITING_LOAD_SIZE 0x1
-#define GC_TIMELS_TIMER1_STATUS_WAITING_LOAD_DEFAULT 0x0
-#define GC_TIMELS_TIMER1_STATUS_WAITING_LOAD_OFFSET 0x44
-#define GC_TIMELS_TIMER1_STATUS_PENDING_LOAD_LSB 0x2
-#define GC_TIMELS_TIMER1_STATUS_PENDING_LOAD_MASK 0x4
-#define GC_TIMELS_TIMER1_STATUS_PENDING_LOAD_SIZE 0x1
-#define GC_TIMELS_TIMER1_STATUS_PENDING_LOAD_DEFAULT 0x0
-#define GC_TIMELS_TIMER1_STATUS_PENDING_LOAD_OFFSET 0x44
-#define GC_TIMELS_TIMER1_STATUS_SYNCING_RELOAD_LSB 0x3
-#define GC_TIMELS_TIMER1_STATUS_SYNCING_RELOAD_MASK 0x8
-#define GC_TIMELS_TIMER1_STATUS_SYNCING_RELOAD_SIZE 0x1
-#define GC_TIMELS_TIMER1_STATUS_SYNCING_RELOAD_DEFAULT 0x0
-#define GC_TIMELS_TIMER1_STATUS_SYNCING_RELOAD_OFFSET 0x44
-#define GC_TIMELS_TIMER1_STATUS_WAITING_RELOAD_LSB 0x4
-#define GC_TIMELS_TIMER1_STATUS_WAITING_RELOAD_MASK 0x10
-#define GC_TIMELS_TIMER1_STATUS_WAITING_RELOAD_SIZE 0x1
-#define GC_TIMELS_TIMER1_STATUS_WAITING_RELOAD_DEFAULT 0x0
-#define GC_TIMELS_TIMER1_STATUS_WAITING_RELOAD_OFFSET 0x44
-#define GC_TIMELS_TIMER1_STATUS_PENDING_RELOAD_LSB 0x5
-#define GC_TIMELS_TIMER1_STATUS_PENDING_RELOAD_MASK 0x20
-#define GC_TIMELS_TIMER1_STATUS_PENDING_RELOAD_SIZE 0x1
-#define GC_TIMELS_TIMER1_STATUS_PENDING_RELOAD_DEFAULT 0x0
-#define GC_TIMELS_TIMER1_STATUS_PENDING_RELOAD_OFFSET 0x44
-#define GC_TIMELS_TIMER1_STATUS_WRAPPED_LSB      0x6
-#define GC_TIMELS_TIMER1_STATUS_WRAPPED_MASK     0x40
-#define GC_TIMELS_TIMER1_STATUS_WRAPPED_SIZE     0x1
-#define GC_TIMELS_TIMER1_STATUS_WRAPPED_DEFAULT  0x0
-#define GC_TIMELS_TIMER1_STATUS_WRAPPED_OFFSET   0x44
-#define GC_TIMELS_ITOP_TIMINT0_LSB               0x0
-#define GC_TIMELS_ITOP_TIMINT0_MASK              0x1
-#define GC_TIMELS_ITOP_TIMINT0_SIZE              0x1
-#define GC_TIMELS_ITOP_TIMINT0_DEFAULT           0x0
-#define GC_TIMELS_ITOP_TIMINT0_OFFSET            0xf04
-#define GC_TIMELS_ITOP_TIMINT1_LSB               0x1
-#define GC_TIMELS_ITOP_TIMINT1_MASK              0x2
-#define GC_TIMELS_ITOP_TIMINT1_SIZE              0x1
-#define GC_TIMELS_ITOP_TIMINT1_DEFAULT           0x0
-#define GC_TIMELS_ITOP_TIMINT1_OFFSET            0xf04
-#define GC_TIMEUS_VERSION_CHANGE_LSB             0x0
-#define GC_TIMEUS_VERSION_CHANGE_MASK            0xffffff
-#define GC_TIMEUS_VERSION_CHANGE_SIZE            0x18
-#define GC_TIMEUS_VERSION_CHANGE_DEFAULT         0x1424a
-#define GC_TIMEUS_VERSION_CHANGE_OFFSET          0x0
-#define GC_TIMEUS_VERSION_REVISION_LSB           0x18
-#define GC_TIMEUS_VERSION_REVISION_MASK          0xff000000
-#define GC_TIMEUS_VERSION_REVISION_SIZE          0x8
-#define GC_TIMEUS_VERSION_REVISION_DEFAULT       0x1
-#define GC_TIMEUS_VERSION_REVISION_OFFSET        0x0
-#define GC_TIMEUS_INT_ENABLE_INTR_PROG_COUNT_HIT0_LSB 0x0
-#define GC_TIMEUS_INT_ENABLE_INTR_PROG_COUNT_HIT0_MASK 0x1
-#define GC_TIMEUS_INT_ENABLE_INTR_PROG_COUNT_HIT0_SIZE 0x1
-#define GC_TIMEUS_INT_ENABLE_INTR_PROG_COUNT_HIT0_DEFAULT 0x0
-#define GC_TIMEUS_INT_ENABLE_INTR_PROG_COUNT_HIT0_OFFSET 0x4
-#define GC_TIMEUS_INT_ENABLE_INTR_MAX_COUNT_HIT0_LSB 0x1
-#define GC_TIMEUS_INT_ENABLE_INTR_MAX_COUNT_HIT0_MASK 0x2
-#define GC_TIMEUS_INT_ENABLE_INTR_MAX_COUNT_HIT0_SIZE 0x1
-#define GC_TIMEUS_INT_ENABLE_INTR_MAX_COUNT_HIT0_DEFAULT 0x0
-#define GC_TIMEUS_INT_ENABLE_INTR_MAX_COUNT_HIT0_OFFSET 0x4
-#define GC_TIMEUS_INT_ENABLE_INTR_PROG_COUNT_HIT1_LSB 0x2
-#define GC_TIMEUS_INT_ENABLE_INTR_PROG_COUNT_HIT1_MASK 0x4
-#define GC_TIMEUS_INT_ENABLE_INTR_PROG_COUNT_HIT1_SIZE 0x1
-#define GC_TIMEUS_INT_ENABLE_INTR_PROG_COUNT_HIT1_DEFAULT 0x0
-#define GC_TIMEUS_INT_ENABLE_INTR_PROG_COUNT_HIT1_OFFSET 0x4
-#define GC_TIMEUS_INT_ENABLE_INTR_MAX_COUNT_HIT1_LSB 0x3
-#define GC_TIMEUS_INT_ENABLE_INTR_MAX_COUNT_HIT1_MASK 0x8
-#define GC_TIMEUS_INT_ENABLE_INTR_MAX_COUNT_HIT1_SIZE 0x1
-#define GC_TIMEUS_INT_ENABLE_INTR_MAX_COUNT_HIT1_DEFAULT 0x0
-#define GC_TIMEUS_INT_ENABLE_INTR_MAX_COUNT_HIT1_OFFSET 0x4
-#define GC_TIMEUS_INT_ENABLE_INTR_PROG_COUNT_HIT2_LSB 0x4
-#define GC_TIMEUS_INT_ENABLE_INTR_PROG_COUNT_HIT2_MASK 0x10
-#define GC_TIMEUS_INT_ENABLE_INTR_PROG_COUNT_HIT2_SIZE 0x1
-#define GC_TIMEUS_INT_ENABLE_INTR_PROG_COUNT_HIT2_DEFAULT 0x0
-#define GC_TIMEUS_INT_ENABLE_INTR_PROG_COUNT_HIT2_OFFSET 0x4
-#define GC_TIMEUS_INT_ENABLE_INTR_MAX_COUNT_HIT2_LSB 0x5
-#define GC_TIMEUS_INT_ENABLE_INTR_MAX_COUNT_HIT2_MASK 0x20
-#define GC_TIMEUS_INT_ENABLE_INTR_MAX_COUNT_HIT2_SIZE 0x1
-#define GC_TIMEUS_INT_ENABLE_INTR_MAX_COUNT_HIT2_DEFAULT 0x0
-#define GC_TIMEUS_INT_ENABLE_INTR_MAX_COUNT_HIT2_OFFSET 0x4
-#define GC_TIMEUS_INT_ENABLE_INTR_PROG_COUNT_HIT3_LSB 0x6
-#define GC_TIMEUS_INT_ENABLE_INTR_PROG_COUNT_HIT3_MASK 0x40
-#define GC_TIMEUS_INT_ENABLE_INTR_PROG_COUNT_HIT3_SIZE 0x1
-#define GC_TIMEUS_INT_ENABLE_INTR_PROG_COUNT_HIT3_DEFAULT 0x0
-#define GC_TIMEUS_INT_ENABLE_INTR_PROG_COUNT_HIT3_OFFSET 0x4
-#define GC_TIMEUS_INT_ENABLE_INTR_MAX_COUNT_HIT3_LSB 0x7
-#define GC_TIMEUS_INT_ENABLE_INTR_MAX_COUNT_HIT3_MASK 0x80
-#define GC_TIMEUS_INT_ENABLE_INTR_MAX_COUNT_HIT3_SIZE 0x1
-#define GC_TIMEUS_INT_ENABLE_INTR_MAX_COUNT_HIT3_DEFAULT 0x0
-#define GC_TIMEUS_INT_ENABLE_INTR_MAX_COUNT_HIT3_OFFSET 0x4
-#define GC_TIMEUS_INT_STATE_INTR_PROG_COUNT_HIT0_LSB 0x0
-#define GC_TIMEUS_INT_STATE_INTR_PROG_COUNT_HIT0_MASK 0x1
-#define GC_TIMEUS_INT_STATE_INTR_PROG_COUNT_HIT0_SIZE 0x1
-#define GC_TIMEUS_INT_STATE_INTR_PROG_COUNT_HIT0_DEFAULT 0x0
-#define GC_TIMEUS_INT_STATE_INTR_PROG_COUNT_HIT0_OFFSET 0x8
-#define GC_TIMEUS_INT_STATE_INTR_MAX_COUNT_HIT0_LSB 0x1
-#define GC_TIMEUS_INT_STATE_INTR_MAX_COUNT_HIT0_MASK 0x2
-#define GC_TIMEUS_INT_STATE_INTR_MAX_COUNT_HIT0_SIZE 0x1
-#define GC_TIMEUS_INT_STATE_INTR_MAX_COUNT_HIT0_DEFAULT 0x0
-#define GC_TIMEUS_INT_STATE_INTR_MAX_COUNT_HIT0_OFFSET 0x8
-#define GC_TIMEUS_INT_STATE_INTR_PROG_COUNT_HIT1_LSB 0x2
-#define GC_TIMEUS_INT_STATE_INTR_PROG_COUNT_HIT1_MASK 0x4
-#define GC_TIMEUS_INT_STATE_INTR_PROG_COUNT_HIT1_SIZE 0x1
-#define GC_TIMEUS_INT_STATE_INTR_PROG_COUNT_HIT1_DEFAULT 0x0
-#define GC_TIMEUS_INT_STATE_INTR_PROG_COUNT_HIT1_OFFSET 0x8
-#define GC_TIMEUS_INT_STATE_INTR_MAX_COUNT_HIT1_LSB 0x3
-#define GC_TIMEUS_INT_STATE_INTR_MAX_COUNT_HIT1_MASK 0x8
-#define GC_TIMEUS_INT_STATE_INTR_MAX_COUNT_HIT1_SIZE 0x1
-#define GC_TIMEUS_INT_STATE_INTR_MAX_COUNT_HIT1_DEFAULT 0x0
-#define GC_TIMEUS_INT_STATE_INTR_MAX_COUNT_HIT1_OFFSET 0x8
-#define GC_TIMEUS_INT_STATE_INTR_PROG_COUNT_HIT2_LSB 0x4
-#define GC_TIMEUS_INT_STATE_INTR_PROG_COUNT_HIT2_MASK 0x10
-#define GC_TIMEUS_INT_STATE_INTR_PROG_COUNT_HIT2_SIZE 0x1
-#define GC_TIMEUS_INT_STATE_INTR_PROG_COUNT_HIT2_DEFAULT 0x0
-#define GC_TIMEUS_INT_STATE_INTR_PROG_COUNT_HIT2_OFFSET 0x8
-#define GC_TIMEUS_INT_STATE_INTR_MAX_COUNT_HIT2_LSB 0x5
-#define GC_TIMEUS_INT_STATE_INTR_MAX_COUNT_HIT2_MASK 0x20
-#define GC_TIMEUS_INT_STATE_INTR_MAX_COUNT_HIT2_SIZE 0x1
-#define GC_TIMEUS_INT_STATE_INTR_MAX_COUNT_HIT2_DEFAULT 0x0
-#define GC_TIMEUS_INT_STATE_INTR_MAX_COUNT_HIT2_OFFSET 0x8
-#define GC_TIMEUS_INT_STATE_INTR_PROG_COUNT_HIT3_LSB 0x6
-#define GC_TIMEUS_INT_STATE_INTR_PROG_COUNT_HIT3_MASK 0x40
-#define GC_TIMEUS_INT_STATE_INTR_PROG_COUNT_HIT3_SIZE 0x1
-#define GC_TIMEUS_INT_STATE_INTR_PROG_COUNT_HIT3_DEFAULT 0x0
-#define GC_TIMEUS_INT_STATE_INTR_PROG_COUNT_HIT3_OFFSET 0x8
-#define GC_TIMEUS_INT_STATE_INTR_MAX_COUNT_HIT3_LSB 0x7
-#define GC_TIMEUS_INT_STATE_INTR_MAX_COUNT_HIT3_MASK 0x80
-#define GC_TIMEUS_INT_STATE_INTR_MAX_COUNT_HIT3_SIZE 0x1
-#define GC_TIMEUS_INT_STATE_INTR_MAX_COUNT_HIT3_DEFAULT 0x0
-#define GC_TIMEUS_INT_STATE_INTR_MAX_COUNT_HIT3_OFFSET 0x8
-#define GC_TIMEUS_INT_TEST_INTR_PROG_COUNT_HIT0_LSB 0x0
-#define GC_TIMEUS_INT_TEST_INTR_PROG_COUNT_HIT0_MASK 0x1
-#define GC_TIMEUS_INT_TEST_INTR_PROG_COUNT_HIT0_SIZE 0x1
-#define GC_TIMEUS_INT_TEST_INTR_PROG_COUNT_HIT0_DEFAULT 0x0
-#define GC_TIMEUS_INT_TEST_INTR_PROG_COUNT_HIT0_OFFSET 0xc
-#define GC_TIMEUS_INT_TEST_INTR_MAX_COUNT_HIT0_LSB 0x1
-#define GC_TIMEUS_INT_TEST_INTR_MAX_COUNT_HIT0_MASK 0x2
-#define GC_TIMEUS_INT_TEST_INTR_MAX_COUNT_HIT0_SIZE 0x1
-#define GC_TIMEUS_INT_TEST_INTR_MAX_COUNT_HIT0_DEFAULT 0x0
-#define GC_TIMEUS_INT_TEST_INTR_MAX_COUNT_HIT0_OFFSET 0xc
-#define GC_TIMEUS_INT_TEST_INTR_PROG_COUNT_HIT1_LSB 0x2
-#define GC_TIMEUS_INT_TEST_INTR_PROG_COUNT_HIT1_MASK 0x4
-#define GC_TIMEUS_INT_TEST_INTR_PROG_COUNT_HIT1_SIZE 0x1
-#define GC_TIMEUS_INT_TEST_INTR_PROG_COUNT_HIT1_DEFAULT 0x0
-#define GC_TIMEUS_INT_TEST_INTR_PROG_COUNT_HIT1_OFFSET 0xc
-#define GC_TIMEUS_INT_TEST_INTR_MAX_COUNT_HIT1_LSB 0x3
-#define GC_TIMEUS_INT_TEST_INTR_MAX_COUNT_HIT1_MASK 0x8
-#define GC_TIMEUS_INT_TEST_INTR_MAX_COUNT_HIT1_SIZE 0x1
-#define GC_TIMEUS_INT_TEST_INTR_MAX_COUNT_HIT1_DEFAULT 0x0
-#define GC_TIMEUS_INT_TEST_INTR_MAX_COUNT_HIT1_OFFSET 0xc
-#define GC_TIMEUS_INT_TEST_INTR_PROG_COUNT_HIT2_LSB 0x4
-#define GC_TIMEUS_INT_TEST_INTR_PROG_COUNT_HIT2_MASK 0x10
-#define GC_TIMEUS_INT_TEST_INTR_PROG_COUNT_HIT2_SIZE 0x1
-#define GC_TIMEUS_INT_TEST_INTR_PROG_COUNT_HIT2_DEFAULT 0x0
-#define GC_TIMEUS_INT_TEST_INTR_PROG_COUNT_HIT2_OFFSET 0xc
-#define GC_TIMEUS_INT_TEST_INTR_MAX_COUNT_HIT2_LSB 0x5
-#define GC_TIMEUS_INT_TEST_INTR_MAX_COUNT_HIT2_MASK 0x20
-#define GC_TIMEUS_INT_TEST_INTR_MAX_COUNT_HIT2_SIZE 0x1
-#define GC_TIMEUS_INT_TEST_INTR_MAX_COUNT_HIT2_DEFAULT 0x0
-#define GC_TIMEUS_INT_TEST_INTR_MAX_COUNT_HIT2_OFFSET 0xc
-#define GC_TIMEUS_INT_TEST_INTR_PROG_COUNT_HIT3_LSB 0x6
-#define GC_TIMEUS_INT_TEST_INTR_PROG_COUNT_HIT3_MASK 0x40
-#define GC_TIMEUS_INT_TEST_INTR_PROG_COUNT_HIT3_SIZE 0x1
-#define GC_TIMEUS_INT_TEST_INTR_PROG_COUNT_HIT3_DEFAULT 0x0
-#define GC_TIMEUS_INT_TEST_INTR_PROG_COUNT_HIT3_OFFSET 0xc
-#define GC_TIMEUS_INT_TEST_INTR_MAX_COUNT_HIT3_LSB 0x7
-#define GC_TIMEUS_INT_TEST_INTR_MAX_COUNT_HIT3_MASK 0x80
-#define GC_TIMEUS_INT_TEST_INTR_MAX_COUNT_HIT3_SIZE 0x1
-#define GC_TIMEUS_INT_TEST_INTR_MAX_COUNT_HIT3_DEFAULT 0x0
-#define GC_TIMEUS_INT_TEST_INTR_MAX_COUNT_HIT3_OFFSET 0xc
-#define GC_TRNG_VERSION_CHANGE_LSB               0x0
-#define GC_TRNG_VERSION_CHANGE_MASK              0xffffff
-#define GC_TRNG_VERSION_CHANGE_SIZE              0x18
-#define GC_TRNG_VERSION_CHANGE_DEFAULT           0x14125
-#define GC_TRNG_VERSION_CHANGE_OFFSET            0x0
-#define GC_TRNG_VERSION_REVISION_LSB             0x18
-#define GC_TRNG_VERSION_REVISION_MASK            0xff000000
-#define GC_TRNG_VERSION_REVISION_SIZE            0x8
-#define GC_TRNG_VERSION_REVISION_DEFAULT         0x1
-#define GC_TRNG_VERSION_REVISION_OFFSET          0x0
-#define GC_TRNG_INT_ENABLE_INTR_BUFFER_FULL_LSB  0x0
-#define GC_TRNG_INT_ENABLE_INTR_BUFFER_FULL_MASK 0x1
-#define GC_TRNG_INT_ENABLE_INTR_BUFFER_FULL_SIZE 0x1
-#define GC_TRNG_INT_ENABLE_INTR_BUFFER_FULL_DEFAULT 0x0
-#define GC_TRNG_INT_ENABLE_INTR_BUFFER_FULL_OFFSET 0x4
-#define GC_TRNG_INT_ENABLE_INTR_ONE_SHOT_DONE_LSB 0x1
-#define GC_TRNG_INT_ENABLE_INTR_ONE_SHOT_DONE_MASK 0x2
-#define GC_TRNG_INT_ENABLE_INTR_ONE_SHOT_DONE_SIZE 0x1
-#define GC_TRNG_INT_ENABLE_INTR_ONE_SHOT_DONE_DEFAULT 0x0
-#define GC_TRNG_INT_ENABLE_INTR_ONE_SHOT_DONE_OFFSET 0x4
-#define GC_TRNG_INT_ENABLE_INTR_READ_EMPTY_LSB   0x2
-#define GC_TRNG_INT_ENABLE_INTR_READ_EMPTY_MASK  0x4
-#define GC_TRNG_INT_ENABLE_INTR_READ_EMPTY_SIZE  0x1
-#define GC_TRNG_INT_ENABLE_INTR_READ_EMPTY_DEFAULT 0x0
-#define GC_TRNG_INT_ENABLE_INTR_READ_EMPTY_OFFSET 0x4
-#define GC_TRNG_INT_STATE_INTR_BUFFER_FULL_LSB   0x0
-#define GC_TRNG_INT_STATE_INTR_BUFFER_FULL_MASK  0x1
-#define GC_TRNG_INT_STATE_INTR_BUFFER_FULL_SIZE  0x1
-#define GC_TRNG_INT_STATE_INTR_BUFFER_FULL_DEFAULT 0x0
-#define GC_TRNG_INT_STATE_INTR_BUFFER_FULL_OFFSET 0x8
-#define GC_TRNG_INT_STATE_INTR_ONE_SHOT_DONE_LSB 0x1
-#define GC_TRNG_INT_STATE_INTR_ONE_SHOT_DONE_MASK 0x2
-#define GC_TRNG_INT_STATE_INTR_ONE_SHOT_DONE_SIZE 0x1
-#define GC_TRNG_INT_STATE_INTR_ONE_SHOT_DONE_DEFAULT 0x0
-#define GC_TRNG_INT_STATE_INTR_ONE_SHOT_DONE_OFFSET 0x8
-#define GC_TRNG_INT_STATE_INTR_READ_EMPTY_LSB    0x2
-#define GC_TRNG_INT_STATE_INTR_READ_EMPTY_MASK   0x4
-#define GC_TRNG_INT_STATE_INTR_READ_EMPTY_SIZE   0x1
-#define GC_TRNG_INT_STATE_INTR_READ_EMPTY_DEFAULT 0x0
-#define GC_TRNG_INT_STATE_INTR_READ_EMPTY_OFFSET 0x8
-#define GC_TRNG_INT_TEST_INTR_BUFFER_FULL_LSB    0x0
-#define GC_TRNG_INT_TEST_INTR_BUFFER_FULL_MASK   0x1
-#define GC_TRNG_INT_TEST_INTR_BUFFER_FULL_SIZE   0x1
-#define GC_TRNG_INT_TEST_INTR_BUFFER_FULL_DEFAULT 0x0
-#define GC_TRNG_INT_TEST_INTR_BUFFER_FULL_OFFSET 0xc
-#define GC_TRNG_INT_TEST_INTR_ONE_SHOT_DONE_LSB  0x1
-#define GC_TRNG_INT_TEST_INTR_ONE_SHOT_DONE_MASK 0x2
-#define GC_TRNG_INT_TEST_INTR_ONE_SHOT_DONE_SIZE 0x1
-#define GC_TRNG_INT_TEST_INTR_ONE_SHOT_DONE_DEFAULT 0x0
-#define GC_TRNG_INT_TEST_INTR_ONE_SHOT_DONE_OFFSET 0xc
-#define GC_TRNG_INT_TEST_INTR_READ_EMPTY_LSB     0x2
-#define GC_TRNG_INT_TEST_INTR_READ_EMPTY_MASK    0x4
-#define GC_TRNG_INT_TEST_INTR_READ_EMPTY_SIZE    0x1
-#define GC_TRNG_INT_TEST_INTR_READ_EMPTY_DEFAULT 0x0
-#define GC_TRNG_INT_TEST_INTR_READ_EMPTY_OFFSET  0xc
-#define GC_TRNG_SECURE_POST_PROCESSING_CTRL_REJECT_EXTREME_VALUES_LSB 0x0
-#define GC_TRNG_SECURE_POST_PROCESSING_CTRL_REJECT_EXTREME_VALUES_MASK 0x1
-#define GC_TRNG_SECURE_POST_PROCESSING_CTRL_REJECT_EXTREME_VALUES_SIZE 0x1
-#define GC_TRNG_SECURE_POST_PROCESSING_CTRL_REJECT_EXTREME_VALUES_DEFAULT 0x1
-#define GC_TRNG_SECURE_POST_PROCESSING_CTRL_REJECT_EXTREME_VALUES_OFFSET 0x10
-#define GC_TRNG_POST_PROCESSING_CTRL_XOR_SLICE_LIMIT_LSB 0x0
-#define GC_TRNG_POST_PROCESSING_CTRL_XOR_SLICE_LIMIT_MASK 0x1
-#define GC_TRNG_POST_PROCESSING_CTRL_XOR_SLICE_LIMIT_SIZE 0x1
-#define GC_TRNG_POST_PROCESSING_CTRL_XOR_SLICE_LIMIT_DEFAULT 0x1
-#define GC_TRNG_POST_PROCESSING_CTRL_XOR_SLICE_LIMIT_OFFSET 0x14
-#define GC_TRNG_POST_PROCESSING_CTRL_SHUFFLE_BITS_LSB 0x1
-#define GC_TRNG_POST_PROCESSING_CTRL_SHUFFLE_BITS_MASK 0x2
-#define GC_TRNG_POST_PROCESSING_CTRL_SHUFFLE_BITS_SIZE 0x1
-#define GC_TRNG_POST_PROCESSING_CTRL_SHUFFLE_BITS_DEFAULT 0x1
-#define GC_TRNG_POST_PROCESSING_CTRL_SHUFFLE_BITS_OFFSET 0x14
-#define GC_TRNG_POST_PROCESSING_CTRL_VON_NEUMANN_LSB 0x2
-#define GC_TRNG_POST_PROCESSING_CTRL_VON_NEUMANN_MASK 0x4
-#define GC_TRNG_POST_PROCESSING_CTRL_VON_NEUMANN_SIZE 0x1
-#define GC_TRNG_POST_PROCESSING_CTRL_VON_NEUMANN_DEFAULT 0x1
-#define GC_TRNG_POST_PROCESSING_CTRL_VON_NEUMANN_OFFSET 0x14
-#define GC_TRNG_POST_PROCESSING_CTRL_CHURN_MODE_LSB 0x3
-#define GC_TRNG_POST_PROCESSING_CTRL_CHURN_MODE_MASK 0x8
-#define GC_TRNG_POST_PROCESSING_CTRL_CHURN_MODE_SIZE 0x1
-#define GC_TRNG_POST_PROCESSING_CTRL_CHURN_MODE_DEFAULT 0x1
-#define GC_TRNG_POST_PROCESSING_CTRL_CHURN_MODE_OFFSET 0x14
-#define GC_TRNG_FSM_STATE_FSM_IDLE_LSB           0x0
-#define GC_TRNG_FSM_STATE_FSM_IDLE_MASK          0x1
-#define GC_TRNG_FSM_STATE_FSM_IDLE_SIZE          0x1
-#define GC_TRNG_FSM_STATE_FSM_IDLE_DEFAULT       0x1
-#define GC_TRNG_FSM_STATE_FSM_IDLE_OFFSET        0x2c
-#define GC_TRNG_FSM_STATE_FSM_PRECHARGE_LSB      0x1
-#define GC_TRNG_FSM_STATE_FSM_PRECHARGE_MASK     0x2
-#define GC_TRNG_FSM_STATE_FSM_PRECHARGE_SIZE     0x1
-#define GC_TRNG_FSM_STATE_FSM_PRECHARGE_DEFAULT  0x0
-#define GC_TRNG_FSM_STATE_FSM_PRECHARGE_OFFSET   0x2c
-#define GC_TRNG_FSM_STATE_FSM_WAIT_LSB           0x2
-#define GC_TRNG_FSM_STATE_FSM_WAIT_MASK          0x4
-#define GC_TRNG_FSM_STATE_FSM_WAIT_SIZE          0x1
-#define GC_TRNG_FSM_STATE_FSM_WAIT_DEFAULT       0x0
-#define GC_TRNG_FSM_STATE_FSM_WAIT_OFFSET        0x2c
-#define GC_TRNG_FSM_STATE_FSM_TIMEOUT_LSB        0x3
-#define GC_TRNG_FSM_STATE_FSM_TIMEOUT_MASK       0x8
-#define GC_TRNG_FSM_STATE_FSM_TIMEOUT_SIZE       0x1
-#define GC_TRNG_FSM_STATE_FSM_TIMEOUT_DEFAULT    0x0
-#define GC_TRNG_FSM_STATE_FSM_TIMEOUT_OFFSET     0x2c
-#define GC_TRNG_FSM_STATE_FSM_CAPTURE_LSB        0x4
-#define GC_TRNG_FSM_STATE_FSM_CAPTURE_MASK       0x10
-#define GC_TRNG_FSM_STATE_FSM_CAPTURE_SIZE       0x1
-#define GC_TRNG_FSM_STATE_FSM_CAPTURE_DEFAULT    0x0
-#define GC_TRNG_FSM_STATE_FSM_CAPTURE_OFFSET     0x2c
-#define GC_TRNG_FSM_STATE_FSM_FULL_LSB           0x5
-#define GC_TRNG_FSM_STATE_FSM_FULL_MASK          0x20
-#define GC_TRNG_FSM_STATE_FSM_FULL_SIZE          0x1
-#define GC_TRNG_FSM_STATE_FSM_FULL_DEFAULT       0x0
-#define GC_TRNG_FSM_STATE_FSM_FULL_OFFSET        0x2c
-#define GC_TRNG_ALLOWED_VALUES_MIN_LSB           0x0
-#define GC_TRNG_ALLOWED_VALUES_MIN_MASK          0x7
-#define GC_TRNG_ALLOWED_VALUES_MIN_SIZE          0x3
-#define GC_TRNG_ALLOWED_VALUES_MIN_DEFAULT       0x1
-#define GC_TRNG_ALLOWED_VALUES_MIN_OFFSET        0x30
-#define GC_TRNG_ALLOWED_VALUES_MAX_LSB           0x3
-#define GC_TRNG_ALLOWED_VALUES_MAX_MASK          0x38
-#define GC_TRNG_ALLOWED_VALUES_MAX_SIZE          0x3
-#define GC_TRNG_ALLOWED_VALUES_MAX_DEFAULT       0x4
-#define GC_TRNG_ALLOWED_VALUES_MAX_OFFSET        0x30
-#define GC_TRNG_ANTEST_VLDO_EN_LSB               0x0
-#define GC_TRNG_ANTEST_VLDO_EN_MASK              0x1
-#define GC_TRNG_ANTEST_VLDO_EN_SIZE              0x1
-#define GC_TRNG_ANTEST_VLDO_EN_DEFAULT           0x0
-#define GC_TRNG_ANTEST_VLDO_EN_OFFSET            0x54
-#define GC_TRNG_ANALOG_SEN_LSR_INPUT_DIG_IN_LSB  0x0
-#define GC_TRNG_ANALOG_SEN_LSR_INPUT_DIG_IN_MASK 0x1
-#define GC_TRNG_ANALOG_SEN_LSR_INPUT_DIG_IN_SIZE 0x1
-#define GC_TRNG_ANALOG_SEN_LSR_INPUT_DIG_IN_DEFAULT 0x1
-#define GC_TRNG_ANALOG_SEN_LSR_INPUT_DIG_IN_OFFSET 0x58
-#define GC_TRNG_ANALOG_SEN_LSR_INPUT_ENB_LSB     0x1
-#define GC_TRNG_ANALOG_SEN_LSR_INPUT_ENB_MASK    0x2
-#define GC_TRNG_ANALOG_SEN_LSR_INPUT_ENB_SIZE    0x1
-#define GC_TRNG_ANALOG_SEN_LSR_INPUT_ENB_DEFAULT 0x1
-#define GC_TRNG_ANALOG_SEN_LSR_INPUT_ENB_OFFSET  0x58
-#define GC_TRNG_ANALOG_SEN_LSR_INPUT_PWR_RDY_LSB 0x2
-#define GC_TRNG_ANALOG_SEN_LSR_INPUT_PWR_RDY_MASK 0x4
-#define GC_TRNG_ANALOG_SEN_LSR_INPUT_PWR_RDY_SIZE 0x1
-#define GC_TRNG_ANALOG_SEN_LSR_INPUT_PWR_RDY_DEFAULT 0x0
-#define GC_TRNG_ANALOG_SEN_LSR_INPUT_PWR_RDY_OFFSET 0x58
-#define GC_TRNG_ANALOG_SEN_LSR_INPUT_PWR_SW_ENB_LSB 0x3
-#define GC_TRNG_ANALOG_SEN_LSR_INPUT_PWR_SW_ENB_MASK 0x8
-#define GC_TRNG_ANALOG_SEN_LSR_INPUT_PWR_SW_ENB_SIZE 0x1
-#define GC_TRNG_ANALOG_SEN_LSR_INPUT_PWR_SW_ENB_DEFAULT 0x1
-#define GC_TRNG_ANALOG_SEN_LSR_INPUT_PWR_SW_ENB_OFFSET 0x58
-#define GC_TRNG_ANALOG_SEN_LSR_INPUT_RST_LSB     0x4
-#define GC_TRNG_ANALOG_SEN_LSR_INPUT_RST_MASK    0x10
-#define GC_TRNG_ANALOG_SEN_LSR_INPUT_RST_SIZE    0x1
-#define GC_TRNG_ANALOG_SEN_LSR_INPUT_RST_DEFAULT 0x0
-#define GC_TRNG_ANALOG_SEN_LSR_INPUT_RST_OFFSET  0x58
-#define GC_TRNG_ANALOG_SEN_LSR_OUTPUT_OUT_LSB    0x0
-#define GC_TRNG_ANALOG_SEN_LSR_OUTPUT_OUT_MASK   0x1
-#define GC_TRNG_ANALOG_SEN_LSR_OUTPUT_OUT_SIZE   0x1
-#define GC_TRNG_ANALOG_SEN_LSR_OUTPUT_OUT_DEFAULT 0x0
-#define GC_TRNG_ANALOG_SEN_LSR_OUTPUT_OUT_OFFSET 0x5c
-#define GC_TRNG_ANALOG_TEST_DIV_EN_LSB           0x0
-#define GC_TRNG_ANALOG_TEST_DIV_EN_MASK          0x1
-#define GC_TRNG_ANALOG_TEST_DIV_EN_SIZE          0x1
-#define GC_TRNG_ANALOG_TEST_DIV_EN_DEFAULT       0x0
-#define GC_TRNG_ANALOG_TEST_DIV_EN_OFFSET        0x60
-#define GC_TRNG_ANALOG_TEST_RO_CALIBRATION_MODE_LSB 0x1
-#define GC_TRNG_ANALOG_TEST_RO_CALIBRATION_MODE_MASK 0x2
-#define GC_TRNG_ANALOG_TEST_RO_CALIBRATION_MODE_SIZE 0x1
-#define GC_TRNG_ANALOG_TEST_RO_CALIBRATION_MODE_DEFAULT 0x0
-#define GC_TRNG_ANALOG_TEST_RO_CALIBRATION_MODE_OFFSET 0x60
-#define GC_TRNG_ANALOG_CTRL_EN_RO_LONG_LSB       0x0
-#define GC_TRNG_ANALOG_CTRL_EN_RO_LONG_MASK      0x1
-#define GC_TRNG_ANALOG_CTRL_EN_RO_LONG_SIZE      0x1
-#define GC_TRNG_ANALOG_CTRL_EN_RO_LONG_DEFAULT   0x0
-#define GC_TRNG_ANALOG_CTRL_EN_RO_LONG_OFFSET    0x64
-#define GC_TRNG_ANALOG_CTRL_RO_REF_SHORT_BYP_DIVB_LSB 0x1
-#define GC_TRNG_ANALOG_CTRL_RO_REF_SHORT_BYP_DIVB_MASK 0x2
-#define GC_TRNG_ANALOG_CTRL_RO_REF_SHORT_BYP_DIVB_SIZE 0x1
-#define GC_TRNG_ANALOG_CTRL_RO_REF_SHORT_BYP_DIVB_DEFAULT 0x0
-#define GC_TRNG_ANALOG_CTRL_RO_REF_SHORT_BYP_DIVB_OFFSET 0x64
-#define GC_TRNG_ANALOG_CTRL_BLD_RES_CTRL_LSB     0x2
-#define GC_TRNG_ANALOG_CTRL_BLD_RES_CTRL_MASK    0xc
-#define GC_TRNG_ANALOG_CTRL_BLD_RES_CTRL_SIZE    0x2
-#define GC_TRNG_ANALOG_CTRL_BLD_RES_CTRL_DEFAULT 0x0
-#define GC_TRNG_ANALOG_CTRL_BLD_RES_CTRL_OFFSET  0x64
-#define GC_UART_CTRL_TX_LSB                      0x0
-#define GC_UART_CTRL_TX_MASK                     0x1
-#define GC_UART_CTRL_TX_SIZE                     0x1
-#define GC_UART_CTRL_TX_DEFAULT                  0x0
-#define GC_UART_CTRL_TX_OFFSET                   0xc
-#define GC_UART_CTRL_RX_LSB                      0x1
-#define GC_UART_CTRL_RX_MASK                     0x2
-#define GC_UART_CTRL_RX_SIZE                     0x1
-#define GC_UART_CTRL_RX_DEFAULT                  0x0
-#define GC_UART_CTRL_RX_OFFSET                   0xc
-#define GC_UART_CTRL_CTS_LSB                     0x2
-#define GC_UART_CTRL_CTS_MASK                    0x4
-#define GC_UART_CTRL_CTS_SIZE                    0x1
-#define GC_UART_CTRL_CTS_DEFAULT                 0x0
-#define GC_UART_CTRL_CTS_OFFSET                  0xc
-#define GC_UART_CTRL_RTS_LSB                     0x3
-#define GC_UART_CTRL_RTS_MASK                    0x8
-#define GC_UART_CTRL_RTS_SIZE                    0x1
-#define GC_UART_CTRL_RTS_DEFAULT                 0x0
-#define GC_UART_CTRL_RTS_OFFSET                  0xc
-#define GC_UART_CTRL_SLPBK_LSB                   0x4
-#define GC_UART_CTRL_SLPBK_MASK                  0x10
-#define GC_UART_CTRL_SLPBK_SIZE                  0x1
-#define GC_UART_CTRL_SLPBK_DEFAULT               0x0
-#define GC_UART_CTRL_SLPBK_OFFSET                0xc
-#define GC_UART_CTRL_LLPBK_LSB                   0x5
-#define GC_UART_CTRL_LLPBK_MASK                  0x20
-#define GC_UART_CTRL_LLPBK_SIZE                  0x1
-#define GC_UART_CTRL_LLPBK_DEFAULT               0x0
-#define GC_UART_CTRL_LLPBK_OFFSET                0xc
-#define GC_UART_CTRL_RCOS_LSB                    0x6
-#define GC_UART_CTRL_RCOS_MASK                   0x40
-#define GC_UART_CTRL_RCOS_SIZE                   0x1
-#define GC_UART_CTRL_RCOS_DEFAULT                0x0
-#define GC_UART_CTRL_RCOS_OFFSET                 0xc
-#define GC_UART_CTRL_NF_LSB                      0x7
-#define GC_UART_CTRL_NF_MASK                     0x80
-#define GC_UART_CTRL_NF_SIZE                     0x1
-#define GC_UART_CTRL_NF_DEFAULT                  0x0
-#define GC_UART_CTRL_NF_OFFSET                   0xc
-#define GC_UART_ICTRL_TX_LSB                     0x0
-#define GC_UART_ICTRL_TX_MASK                    0x1
-#define GC_UART_ICTRL_TX_SIZE                    0x1
-#define GC_UART_ICTRL_TX_DEFAULT                 0x0
-#define GC_UART_ICTRL_TX_OFFSET                  0x10
-#define GC_UART_ICTRL_RX_LSB                     0x1
-#define GC_UART_ICTRL_RX_MASK                    0x2
-#define GC_UART_ICTRL_RX_SIZE                    0x1
-#define GC_UART_ICTRL_RX_DEFAULT                 0x0
-#define GC_UART_ICTRL_RX_OFFSET                  0x10
-#define GC_UART_ICTRL_TXO_LSB                    0x2
-#define GC_UART_ICTRL_TXO_MASK                   0x4
-#define GC_UART_ICTRL_TXO_SIZE                   0x1
-#define GC_UART_ICTRL_TXO_DEFAULT                0x0
-#define GC_UART_ICTRL_TXO_OFFSET                 0x10
-#define GC_UART_ICTRL_RXO_LSB                    0x3
-#define GC_UART_ICTRL_RXO_MASK                   0x8
-#define GC_UART_ICTRL_RXO_SIZE                   0x1
-#define GC_UART_ICTRL_RXO_DEFAULT                0x0
-#define GC_UART_ICTRL_RXO_OFFSET                 0x10
-#define GC_UART_ICTRL_RXF_LSB                    0x4
-#define GC_UART_ICTRL_RXF_MASK                   0x10
-#define GC_UART_ICTRL_RXF_SIZE                   0x1
-#define GC_UART_ICTRL_RXF_DEFAULT                0x0
-#define GC_UART_ICTRL_RXF_OFFSET                 0x10
-#define GC_UART_ICTRL_RXB_LSB                    0x5
-#define GC_UART_ICTRL_RXB_MASK                   0x20
-#define GC_UART_ICTRL_RXB_SIZE                   0x1
-#define GC_UART_ICTRL_RXB_DEFAULT                0x0
-#define GC_UART_ICTRL_RXB_OFFSET                 0x10
-#define GC_UART_ICTRL_RXBLVL_LSB                 0x6
-#define GC_UART_ICTRL_RXBLVL_MASK                0xc0
-#define GC_UART_ICTRL_RXBLVL_SIZE                0x2
-#define GC_UART_ICTRL_RXBLVL_DEFAULT             0x0
-#define GC_UART_ICTRL_RXBLVL_OFFSET              0x10
-#define GC_UART_ICTRL_RXTO_LSB                   0x8
-#define GC_UART_ICTRL_RXTO_MASK                  0x100
-#define GC_UART_ICTRL_RXTO_SIZE                  0x1
-#define GC_UART_ICTRL_RXTO_DEFAULT               0x0
-#define GC_UART_ICTRL_RXTO_OFFSET                0x10
-#define GC_UART_STATE_TX_LSB                     0x0
-#define GC_UART_STATE_TX_MASK                    0x1
-#define GC_UART_STATE_TX_SIZE                    0x1
-#define GC_UART_STATE_TX_DEFAULT                 0x0
-#define GC_UART_STATE_TX_OFFSET                  0x14
-#define GC_UART_STATE_RX_LSB                     0x1
-#define GC_UART_STATE_RX_MASK                    0x2
-#define GC_UART_STATE_RX_SIZE                    0x1
-#define GC_UART_STATE_RX_DEFAULT                 0x0
-#define GC_UART_STATE_RX_OFFSET                  0x14
-#define GC_UART_STATE_TXO_LSB                    0x2
-#define GC_UART_STATE_TXO_MASK                   0x4
-#define GC_UART_STATE_TXO_SIZE                   0x1
-#define GC_UART_STATE_TXO_DEFAULT                0x0
-#define GC_UART_STATE_TXO_OFFSET                 0x14
-#define GC_UART_STATE_RXO_LSB                    0x3
-#define GC_UART_STATE_RXO_MASK                   0x8
-#define GC_UART_STATE_RXO_SIZE                   0x1
-#define GC_UART_STATE_RXO_DEFAULT                0x0
-#define GC_UART_STATE_RXO_OFFSET                 0x14
-#define GC_UART_STATE_TXEMPTY_LSB                0x4
-#define GC_UART_STATE_TXEMPTY_MASK               0x10
-#define GC_UART_STATE_TXEMPTY_SIZE               0x1
-#define GC_UART_STATE_TXEMPTY_DEFAULT            0x1
-#define GC_UART_STATE_TXEMPTY_OFFSET             0x14
-#define GC_UART_STATE_TXIDLE_LSB                 0x5
-#define GC_UART_STATE_TXIDLE_MASK                0x20
-#define GC_UART_STATE_TXIDLE_SIZE                0x1
-#define GC_UART_STATE_TXIDLE_DEFAULT             0x0
-#define GC_UART_STATE_TXIDLE_OFFSET              0x14
-#define GC_UART_STATE_RXIDLE_LSB                 0x6
-#define GC_UART_STATE_RXIDLE_MASK                0x40
-#define GC_UART_STATE_RXIDLE_SIZE                0x1
-#define GC_UART_STATE_RXIDLE_DEFAULT             0x0
-#define GC_UART_STATE_RXIDLE_OFFSET              0x14
-#define GC_UART_STATE_RXEMPTY_LSB                0x7
-#define GC_UART_STATE_RXEMPTY_MASK               0x80
-#define GC_UART_STATE_RXEMPTY_SIZE               0x1
-#define GC_UART_STATE_RXEMPTY_DEFAULT            0x1
-#define GC_UART_STATE_RXEMPTY_OFFSET             0x14
-#define GC_UART_STATECLR_RES0_LSB                0x0
-#define GC_UART_STATECLR_RES0_MASK               0x1
-#define GC_UART_STATECLR_RES0_SIZE               0x1
-#define GC_UART_STATECLR_RES0_DEFAULT            0x0
-#define GC_UART_STATECLR_RES0_OFFSET             0x18
-#define GC_UART_STATECLR_RES1_LSB                0x1
-#define GC_UART_STATECLR_RES1_MASK               0x2
-#define GC_UART_STATECLR_RES1_SIZE               0x1
-#define GC_UART_STATECLR_RES1_DEFAULT            0x0
-#define GC_UART_STATECLR_RES1_OFFSET             0x18
-#define GC_UART_STATECLR_TXO_LSB                 0x2
-#define GC_UART_STATECLR_TXO_MASK                0x4
-#define GC_UART_STATECLR_TXO_SIZE                0x1
-#define GC_UART_STATECLR_TXO_DEFAULT             0x0
-#define GC_UART_STATECLR_TXO_OFFSET              0x18
-#define GC_UART_STATECLR_RXO_LSB                 0x3
-#define GC_UART_STATECLR_RXO_MASK                0x8
-#define GC_UART_STATECLR_RXO_SIZE                0x1
-#define GC_UART_STATECLR_RXO_DEFAULT             0x0
-#define GC_UART_STATECLR_RXO_OFFSET              0x18
-#define GC_UART_ISTATE_TX_LSB                    0x0
-#define GC_UART_ISTATE_TX_MASK                   0x1
-#define GC_UART_ISTATE_TX_SIZE                   0x1
-#define GC_UART_ISTATE_TX_DEFAULT                0x0
-#define GC_UART_ISTATE_TX_OFFSET                 0x1c
-#define GC_UART_ISTATE_RX_LSB                    0x1
-#define GC_UART_ISTATE_RX_MASK                   0x2
-#define GC_UART_ISTATE_RX_SIZE                   0x1
-#define GC_UART_ISTATE_RX_DEFAULT                0x0
-#define GC_UART_ISTATE_RX_OFFSET                 0x1c
-#define GC_UART_ISTATE_TXO_LSB                   0x2
-#define GC_UART_ISTATE_TXO_MASK                  0x4
-#define GC_UART_ISTATE_TXO_SIZE                  0x1
-#define GC_UART_ISTATE_TXO_DEFAULT               0x0
-#define GC_UART_ISTATE_TXO_OFFSET                0x1c
-#define GC_UART_ISTATE_RXO_LSB                   0x3
-#define GC_UART_ISTATE_RXO_MASK                  0x8
-#define GC_UART_ISTATE_RXO_SIZE                  0x1
-#define GC_UART_ISTATE_RXO_DEFAULT               0x0
-#define GC_UART_ISTATE_RXO_OFFSET                0x1c
-#define GC_UART_ISTATE_RXF_LSB                   0x4
-#define GC_UART_ISTATE_RXF_MASK                  0x10
-#define GC_UART_ISTATE_RXF_SIZE                  0x1
-#define GC_UART_ISTATE_RXF_DEFAULT               0x0
-#define GC_UART_ISTATE_RXF_OFFSET                0x1c
-#define GC_UART_ISTATE_RXB_LSB                   0x5
-#define GC_UART_ISTATE_RXB_MASK                  0x20
-#define GC_UART_ISTATE_RXB_SIZE                  0x1
-#define GC_UART_ISTATE_RXB_DEFAULT               0x0
-#define GC_UART_ISTATE_RXB_OFFSET                0x1c
-#define GC_UART_ISTATE_RXTO_LSB                  0x6
-#define GC_UART_ISTATE_RXTO_MASK                 0x40
-#define GC_UART_ISTATE_RXTO_SIZE                 0x1
-#define GC_UART_ISTATE_RXTO_DEFAULT              0x0
-#define GC_UART_ISTATE_RXTO_OFFSET               0x1c
-#define GC_UART_ISTATECLR_TX_LSB                 0x0
-#define GC_UART_ISTATECLR_TX_MASK                0x1
-#define GC_UART_ISTATECLR_TX_SIZE                0x1
-#define GC_UART_ISTATECLR_TX_DEFAULT             0x0
-#define GC_UART_ISTATECLR_TX_OFFSET              0x20
-#define GC_UART_ISTATECLR_RX_LSB                 0x1
-#define GC_UART_ISTATECLR_RX_MASK                0x2
-#define GC_UART_ISTATECLR_RX_SIZE                0x1
-#define GC_UART_ISTATECLR_RX_DEFAULT             0x0
-#define GC_UART_ISTATECLR_RX_OFFSET              0x20
-#define GC_UART_ISTATECLR_TXO_LSB                0x2
-#define GC_UART_ISTATECLR_TXO_MASK               0x4
-#define GC_UART_ISTATECLR_TXO_SIZE               0x1
-#define GC_UART_ISTATECLR_TXO_DEFAULT            0x0
-#define GC_UART_ISTATECLR_TXO_OFFSET             0x20
-#define GC_UART_ISTATECLR_RXO_LSB                0x3
-#define GC_UART_ISTATECLR_RXO_MASK               0x8
-#define GC_UART_ISTATECLR_RXO_SIZE               0x1
-#define GC_UART_ISTATECLR_RXO_DEFAULT            0x0
-#define GC_UART_ISTATECLR_RXO_OFFSET             0x20
-#define GC_UART_ISTATECLR_RXF_LSB                0x4
-#define GC_UART_ISTATECLR_RXF_MASK               0x10
-#define GC_UART_ISTATECLR_RXF_SIZE               0x1
-#define GC_UART_ISTATECLR_RXF_DEFAULT            0x0
-#define GC_UART_ISTATECLR_RXF_OFFSET             0x20
-#define GC_UART_ISTATECLR_RXB_LSB                0x5
-#define GC_UART_ISTATECLR_RXB_MASK               0x20
-#define GC_UART_ISTATECLR_RXB_SIZE               0x1
-#define GC_UART_ISTATECLR_RXB_DEFAULT            0x0
-#define GC_UART_ISTATECLR_RXB_OFFSET             0x20
-#define GC_UART_ISTATECLR_RXTO_LSB               0x6
-#define GC_UART_ISTATECLR_RXTO_MASK              0x40
-#define GC_UART_ISTATECLR_RXTO_SIZE              0x1
-#define GC_UART_ISTATECLR_RXTO_DEFAULT           0x0
-#define GC_UART_ISTATECLR_RXTO_OFFSET            0x20
-#define GC_UART_FIFO_RXRST_LSB                   0x0
-#define GC_UART_FIFO_RXRST_MASK                  0x1
-#define GC_UART_FIFO_RXRST_SIZE                  0x1
-#define GC_UART_FIFO_RXRST_DEFAULT               0x0
-#define GC_UART_FIFO_RXRST_OFFSET                0x24
-#define GC_UART_FIFO_TXRST_LSB                   0x1
-#define GC_UART_FIFO_TXRST_MASK                  0x2
-#define GC_UART_FIFO_TXRST_SIZE                  0x1
-#define GC_UART_FIFO_TXRST_DEFAULT               0x0
-#define GC_UART_FIFO_TXRST_OFFSET                0x24
-#define GC_UART_FIFO_RXILVL_LSB                  0x2
-#define GC_UART_FIFO_RXILVL_MASK                 0x1c
-#define GC_UART_FIFO_RXILVL_SIZE                 0x3
-#define GC_UART_FIFO_RXILVL_DEFAULT              0x0
-#define GC_UART_FIFO_RXILVL_OFFSET               0x24
-#define GC_UART_FIFO_TXILVL_LSB                  0x5
-#define GC_UART_FIFO_TXILVL_MASK                 0x60
-#define GC_UART_FIFO_TXILVL_SIZE                 0x2
-#define GC_UART_FIFO_TXILVL_DEFAULT              0x0
-#define GC_UART_FIFO_TXILVL_OFFSET               0x24
-#define GC_UART_RFIFO_TXLVL_LSB                  0x0
-#define GC_UART_RFIFO_TXLVL_MASK                 0x3f
-#define GC_UART_RFIFO_TXLVL_SIZE                 0x6
-#define GC_UART_RFIFO_TXLVL_DEFAULT              0x0
-#define GC_UART_RFIFO_TXLVL_OFFSET               0x28
-#define GC_UART_RFIFO_RXLVL_LSB                  0x6
-#define GC_UART_RFIFO_RXLVL_MASK                 0xfc0
-#define GC_UART_RFIFO_RXLVL_SIZE                 0x6
-#define GC_UART_RFIFO_RXLVL_DEFAULT              0x0
-#define GC_UART_RFIFO_RXLVL_OFFSET               0x28
-#define GC_UART_OVRD_TXEN_LSB                    0x0
-#define GC_UART_OVRD_TXEN_MASK                   0x1
-#define GC_UART_OVRD_TXEN_SIZE                   0x1
-#define GC_UART_OVRD_TXEN_DEFAULT                0x0
-#define GC_UART_OVRD_TXEN_OFFSET                 0x2c
-#define GC_UART_OVRD_TXVAL_LSB                   0x1
-#define GC_UART_OVRD_TXVAL_MASK                  0x2
-#define GC_UART_OVRD_TXVAL_SIZE                  0x1
-#define GC_UART_OVRD_TXVAL_DEFAULT               0x0
-#define GC_UART_OVRD_TXVAL_OFFSET                0x2c
-#define GC_UART_OVRD_RTSEN_LSB                   0x2
-#define GC_UART_OVRD_RTSEN_MASK                  0x4
-#define GC_UART_OVRD_RTSEN_SIZE                  0x1
-#define GC_UART_OVRD_RTSEN_DEFAULT               0x0
-#define GC_UART_OVRD_RTSEN_OFFSET                0x2c
-#define GC_UART_OVRD_RTSVAL_LSB                  0x3
-#define GC_UART_OVRD_RTSVAL_MASK                 0x8
-#define GC_UART_OVRD_RTSVAL_SIZE                 0x1
-#define GC_UART_OVRD_RTSVAL_DEFAULT              0x0
-#define GC_UART_OVRD_RTSVAL_OFFSET               0x2c
-#define GC_UART_VAL_RX_LSB                       0x0
-#define GC_UART_VAL_RX_MASK                      0xffff
-#define GC_UART_VAL_RX_SIZE                      0x10
-#define GC_UART_VAL_RX_DEFAULT                   0x0
-#define GC_UART_VAL_RX_OFFSET                    0x30
-#define GC_UART_VAL_CTS_LSB                      0x10
-#define GC_UART_VAL_CTS_MASK                     0xffff0000
-#define GC_UART_VAL_CTS_SIZE                     0x10
-#define GC_UART_VAL_CTS_DEFAULT                  0x0
-#define GC_UART_VAL_CTS_OFFSET                   0x30
-#define GC_UART_RXTO_EN_LSB                      0x0
-#define GC_UART_RXTO_EN_MASK                     0x1
-#define GC_UART_RXTO_EN_SIZE                     0x1
-#define GC_UART_RXTO_EN_DEFAULT                  0x0
-#define GC_UART_RXTO_EN_OFFSET                   0x34
-#define GC_UART_RXTO_VAL_LSB                     0x1
-#define GC_UART_RXTO_VAL_MASK                    0x1fffffe
-#define GC_UART_RXTO_VAL_SIZE                    0x18
-#define GC_UART_RXTO_VAL_DEFAULT                 0x0
-#define GC_UART_RXTO_VAL_OFFSET                  0x34
-#define GC_UART_ITOP_TX_LSB                      0x0
-#define GC_UART_ITOP_TX_MASK                     0x1
-#define GC_UART_ITOP_TX_SIZE                     0x1
-#define GC_UART_ITOP_TX_DEFAULT                  0x0
-#define GC_UART_ITOP_TX_OFFSET                   0xf04
-#define GC_UART_ITOP_RX_LSB                      0x1
-#define GC_UART_ITOP_RX_MASK                     0x2
-#define GC_UART_ITOP_RX_SIZE                     0x1
-#define GC_UART_ITOP_RX_DEFAULT                  0x0
-#define GC_UART_ITOP_RX_OFFSET                   0xf04
-#define GC_UART_ITOP_TXO_LSB                     0x2
-#define GC_UART_ITOP_TXO_MASK                    0x4
-#define GC_UART_ITOP_TXO_SIZE                    0x1
-#define GC_UART_ITOP_TXO_DEFAULT                 0x0
-#define GC_UART_ITOP_TXO_OFFSET                  0xf04
-#define GC_UART_ITOP_RXO_LSB                     0x3
-#define GC_UART_ITOP_RXO_MASK                    0x8
-#define GC_UART_ITOP_RXO_SIZE                    0x1
-#define GC_UART_ITOP_RXO_DEFAULT                 0x0
-#define GC_UART_ITOP_RXO_OFFSET                  0xf04
-#define GC_UART_ITOP_RXF_LSB                     0x4
-#define GC_UART_ITOP_RXF_MASK                    0x10
-#define GC_UART_ITOP_RXF_SIZE                    0x1
-#define GC_UART_ITOP_RXF_DEFAULT                 0x0
-#define GC_UART_ITOP_RXF_OFFSET                  0xf04
-#define GC_UART_ITOP_RXB_LSB                     0x5
-#define GC_UART_ITOP_RXB_MASK                    0x20
-#define GC_UART_ITOP_RXB_SIZE                    0x1
-#define GC_UART_ITOP_RXB_DEFAULT                 0x0
-#define GC_UART_ITOP_RXB_OFFSET                  0xf04
-#define GC_UART_ITOP_RXTO_LSB                    0x6
-#define GC_UART_ITOP_RXTO_MASK                   0x40
-#define GC_UART_ITOP_RXTO_SIZE                   0x1
-#define GC_UART_ITOP_RXTO_DEFAULT                0x0
-#define GC_UART_ITOP_RXTO_OFFSET                 0xf04
-#define GC_USB_GOTGCTL_BVALIDOVEN_LSB            0x6
-#define GC_USB_GOTGCTL_BVALIDOVEN_MASK           0x40
-#define GC_USB_GOTGCTL_BVALIDOVEN_SIZE           0x1
-#define GC_USB_GOTGCTL_BVALIDOVEN_DEFAULT        0x0
-#define GC_USB_GOTGCTL_BVALIDOVEN_OFFSET         0x0
-#define GC_USB_GOTGCTL_BVALIDOVVAL_LSB           0x7
-#define GC_USB_GOTGCTL_BVALIDOVVAL_MASK          0x80
-#define GC_USB_GOTGCTL_BVALIDOVVAL_SIZE          0x1
-#define GC_USB_GOTGCTL_BVALIDOVVAL_DEFAULT       0x0
-#define GC_USB_GOTGCTL_BVALIDOVVAL_OFFSET        0x0
-#define GC_USB_GOTGCTL_CONIDSTS_LSB              0x10
-#define GC_USB_GOTGCTL_CONIDSTS_MASK             0x10000
-#define GC_USB_GOTGCTL_CONIDSTS_SIZE             0x1
-#define GC_USB_GOTGCTL_CONIDSTS_DEFAULT          0x0
-#define GC_USB_GOTGCTL_CONIDSTS_OFFSET           0x0
-#define GC_USB_GOTGCTL_BSESVLD_LSB               0x13
-#define GC_USB_GOTGCTL_BSESVLD_MASK              0x80000
-#define GC_USB_GOTGCTL_BSESVLD_SIZE              0x1
-#define GC_USB_GOTGCTL_BSESVLD_DEFAULT           0x0
-#define GC_USB_GOTGCTL_BSESVLD_OFFSET            0x0
-#define GC_USB_GOTGCTL_OTGVER_LSB                0x14
-#define GC_USB_GOTGCTL_OTGVER_MASK               0x100000
-#define GC_USB_GOTGCTL_OTGVER_SIZE               0x1
-#define GC_USB_GOTGCTL_OTGVER_DEFAULT            0x0
-#define GC_USB_GOTGCTL_OTGVER_OFFSET             0x0
-#define GC_USB_GOTGCTL_CURMOD_LSB                0x15
-#define GC_USB_GOTGCTL_CURMOD_MASK               0x200000
-#define GC_USB_GOTGCTL_CURMOD_SIZE               0x1
-#define GC_USB_GOTGCTL_CURMOD_DEFAULT            0x0
-#define GC_USB_GOTGCTL_CURMOD_OFFSET             0x0
-#define GC_USB_GOTGINT_SESENDDET_LSB             0x2
-#define GC_USB_GOTGINT_SESENDDET_MASK            0x4
-#define GC_USB_GOTGINT_SESENDDET_SIZE            0x1
-#define GC_USB_GOTGINT_SESENDDET_DEFAULT         0x0
-#define GC_USB_GOTGINT_SESENDDET_OFFSET          0x4
-#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_LSB      0x8
-#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_MASK     0x100
-#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_SIZE     0x1
-#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_DEFAULT  0x0
-#define GC_USB_GOTGINT_SESREQSUCSTSCHNG_OFFSET   0x4
-#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_LSB      0x9
-#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_MASK     0x200
-#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_SIZE     0x1
-#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_DEFAULT  0x0
-#define GC_USB_GOTGINT_HSTNEGSUCSTSCHNG_OFFSET   0x4
-#define GC_USB_GOTGINT_HSTNEGDET_LSB             0x11
-#define GC_USB_GOTGINT_HSTNEGDET_MASK            0x20000
-#define GC_USB_GOTGINT_HSTNEGDET_SIZE            0x1
-#define GC_USB_GOTGINT_HSTNEGDET_DEFAULT         0x0
-#define GC_USB_GOTGINT_HSTNEGDET_OFFSET          0x4
-#define GC_USB_GOTGINT_ADEVTOUTCHG_LSB           0x12
-#define GC_USB_GOTGINT_ADEVTOUTCHG_MASK          0x40000
-#define GC_USB_GOTGINT_ADEVTOUTCHG_SIZE          0x1
-#define GC_USB_GOTGINT_ADEVTOUTCHG_DEFAULT       0x0
-#define GC_USB_GOTGINT_ADEVTOUTCHG_OFFSET        0x4
-#define GC_USB_GAHBCFG_GLBLINTRMSK_LSB           0x0
-#define GC_USB_GAHBCFG_GLBLINTRMSK_MASK          0x1
-#define GC_USB_GAHBCFG_GLBLINTRMSK_SIZE          0x1
-#define GC_USB_GAHBCFG_GLBLINTRMSK_DEFAULT       0x0
-#define GC_USB_GAHBCFG_GLBLINTRMSK_OFFSET        0x8
-#define GC_USB_GAHBCFG_HBSTLEN_LSB               0x1
-#define GC_USB_GAHBCFG_HBSTLEN_MASK              0x1e
-#define GC_USB_GAHBCFG_HBSTLEN_SIZE              0x4
-#define GC_USB_GAHBCFG_HBSTLEN_DEFAULT           0x0
-#define GC_USB_GAHBCFG_HBSTLEN_OFFSET            0x8
-#define GC_USB_GAHBCFG_DMAEN_LSB                 0x5
-#define GC_USB_GAHBCFG_DMAEN_MASK                0x20
-#define GC_USB_GAHBCFG_DMAEN_SIZE                0x1
-#define GC_USB_GAHBCFG_DMAEN_DEFAULT             0x0
-#define GC_USB_GAHBCFG_DMAEN_OFFSET              0x8
-#define GC_USB_GAHBCFG_NPTXFEMPLVL_LSB           0x7
-#define GC_USB_GAHBCFG_NPTXFEMPLVL_MASK          0x80
-#define GC_USB_GAHBCFG_NPTXFEMPLVL_SIZE          0x1
-#define GC_USB_GAHBCFG_NPTXFEMPLVL_DEFAULT       0x0
-#define GC_USB_GAHBCFG_NPTXFEMPLVL_OFFSET        0x8
-#define GC_USB_GAHBCFG_REMMEMSUPP_LSB            0x15
-#define GC_USB_GAHBCFG_REMMEMSUPP_MASK           0x200000
-#define GC_USB_GAHBCFG_REMMEMSUPP_SIZE           0x1
-#define GC_USB_GAHBCFG_REMMEMSUPP_DEFAULT        0x0
-#define GC_USB_GAHBCFG_REMMEMSUPP_OFFSET         0x8
-#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_LSB        0x16
-#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_MASK       0x400000
-#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_SIZE       0x1
-#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_DEFAULT    0x0
-#define GC_USB_GAHBCFG_NOTIALLDMAWRIT_OFFSET     0x8
-#define GC_USB_GAHBCFG_AHBSINGLE_LSB             0x17
-#define GC_USB_GAHBCFG_AHBSINGLE_MASK            0x800000
-#define GC_USB_GAHBCFG_AHBSINGLE_SIZE            0x1
-#define GC_USB_GAHBCFG_AHBSINGLE_DEFAULT         0x0
-#define GC_USB_GAHBCFG_AHBSINGLE_OFFSET          0x8
-#define GC_USB_GAHBCFG_INVDESCENDIANESS_LSB      0x18
-#define GC_USB_GAHBCFG_INVDESCENDIANESS_MASK     0x1000000
-#define GC_USB_GAHBCFG_INVDESCENDIANESS_SIZE     0x1
-#define GC_USB_GAHBCFG_INVDESCENDIANESS_DEFAULT  0x0
-#define GC_USB_GAHBCFG_INVDESCENDIANESS_OFFSET   0x8
-#define GC_USB_GUSBCFG_TOUTCAL_LSB               0x0
-#define GC_USB_GUSBCFG_TOUTCAL_MASK              0x7
-#define GC_USB_GUSBCFG_TOUTCAL_SIZE              0x3
-#define GC_USB_GUSBCFG_TOUTCAL_DEFAULT           0x0
-#define GC_USB_GUSBCFG_TOUTCAL_OFFSET            0xc
-#define GC_USB_GUSBCFG_PHYIF_LSB                 0x3
-#define GC_USB_GUSBCFG_PHYIF_MASK                0x8
-#define GC_USB_GUSBCFG_PHYIF_SIZE                0x1
-#define GC_USB_GUSBCFG_PHYIF_DEFAULT             0x0
-#define GC_USB_GUSBCFG_PHYIF_OFFSET              0xc
-#define GC_USB_GUSBCFG_ULPI_UTMI_SEL_LSB         0x4
-#define GC_USB_GUSBCFG_ULPI_UTMI_SEL_MASK        0x10
-#define GC_USB_GUSBCFG_ULPI_UTMI_SEL_SIZE        0x1
-#define GC_USB_GUSBCFG_ULPI_UTMI_SEL_DEFAULT     0x0
-#define GC_USB_GUSBCFG_ULPI_UTMI_SEL_OFFSET      0xc
-#define GC_USB_GUSBCFG_FSINTF_LSB                0x5
-#define GC_USB_GUSBCFG_FSINTF_MASK               0x20
-#define GC_USB_GUSBCFG_FSINTF_SIZE               0x1
-#define GC_USB_GUSBCFG_FSINTF_DEFAULT            0x0
-#define GC_USB_GUSBCFG_FSINTF_OFFSET             0xc
-#define GC_USB_GUSBCFG_PHYSEL_LSB                0x6
-#define GC_USB_GUSBCFG_PHYSEL_MASK               0x40
-#define GC_USB_GUSBCFG_PHYSEL_SIZE               0x1
-#define GC_USB_GUSBCFG_PHYSEL_DEFAULT            0x0
-#define GC_USB_GUSBCFG_PHYSEL_OFFSET             0xc
-#define GC_USB_GUSBCFG_DDRSEL_LSB                0x7
-#define GC_USB_GUSBCFG_DDRSEL_MASK               0x80
-#define GC_USB_GUSBCFG_DDRSEL_SIZE               0x1
-#define GC_USB_GUSBCFG_DDRSEL_DEFAULT            0x0
-#define GC_USB_GUSBCFG_DDRSEL_OFFSET             0xc
-#define GC_USB_GUSBCFG_USBTRDTIM_LSB             0xa
-#define GC_USB_GUSBCFG_USBTRDTIM_MASK            0x3c00
-#define GC_USB_GUSBCFG_USBTRDTIM_SIZE            0x4
-#define GC_USB_GUSBCFG_USBTRDTIM_DEFAULT         0x0
-#define GC_USB_GUSBCFG_USBTRDTIM_OFFSET          0xc
-#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_LSB         0xf
-#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_MASK        0x8000
-#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_SIZE        0x1
-#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_DEFAULT     0x0
-#define GC_USB_GUSBCFG_PHYLPWRCLKSEL_OFFSET      0xc
-#define GC_USB_GUSBCFG_ULPIFSLS_LSB              0x11
-#define GC_USB_GUSBCFG_ULPIFSLS_MASK             0x20000
-#define GC_USB_GUSBCFG_ULPIFSLS_SIZE             0x1
-#define GC_USB_GUSBCFG_ULPIFSLS_DEFAULT          0x0
-#define GC_USB_GUSBCFG_ULPIFSLS_OFFSET           0xc
-#define GC_USB_GUSBCFG_ULPIAUTORES_LSB           0x12
-#define GC_USB_GUSBCFG_ULPIAUTORES_MASK          0x40000
-#define GC_USB_GUSBCFG_ULPIAUTORES_SIZE          0x1
-#define GC_USB_GUSBCFG_ULPIAUTORES_DEFAULT       0x0
-#define GC_USB_GUSBCFG_ULPIAUTORES_OFFSET        0xc
-#define GC_USB_GUSBCFG_ULPICLKSUSM_LSB           0x13
-#define GC_USB_GUSBCFG_ULPICLKSUSM_MASK          0x80000
-#define GC_USB_GUSBCFG_ULPICLKSUSM_SIZE          0x1
-#define GC_USB_GUSBCFG_ULPICLKSUSM_DEFAULT       0x0
-#define GC_USB_GUSBCFG_ULPICLKSUSM_OFFSET        0xc
-#define GC_USB_GUSBCFG_TERMSELDLPULSE_LSB        0x16
-#define GC_USB_GUSBCFG_TERMSELDLPULSE_MASK       0x400000
-#define GC_USB_GUSBCFG_TERMSELDLPULSE_SIZE       0x1
-#define GC_USB_GUSBCFG_TERMSELDLPULSE_DEFAULT    0x0
-#define GC_USB_GUSBCFG_TERMSELDLPULSE_OFFSET     0xc
-#define GC_USB_GUSBCFG_IC_USBCAP_LSB             0x1a
-#define GC_USB_GUSBCFG_IC_USBCAP_MASK            0x4000000
-#define GC_USB_GUSBCFG_IC_USBCAP_SIZE            0x1
-#define GC_USB_GUSBCFG_IC_USBCAP_DEFAULT         0x0
-#define GC_USB_GUSBCFG_IC_USBCAP_OFFSET          0xc
-#define GC_USB_GUSBCFG_TXENDDELAY_LSB            0x1c
-#define GC_USB_GUSBCFG_TXENDDELAY_MASK           0x10000000
-#define GC_USB_GUSBCFG_TXENDDELAY_SIZE           0x1
-#define GC_USB_GUSBCFG_TXENDDELAY_DEFAULT        0x0
-#define GC_USB_GUSBCFG_TXENDDELAY_OFFSET         0xc
-#define GC_USB_GUSBCFG_CORRUPTTXPKT_LSB          0x1f
-#define GC_USB_GUSBCFG_CORRUPTTXPKT_MASK         0x80000000
-#define GC_USB_GUSBCFG_CORRUPTTXPKT_SIZE         0x1
-#define GC_USB_GUSBCFG_CORRUPTTXPKT_DEFAULT      0x0
-#define GC_USB_GUSBCFG_CORRUPTTXPKT_OFFSET       0xc
-#define GC_USB_GRSTCTL_CSFTRST_LSB               0x0
-#define GC_USB_GRSTCTL_CSFTRST_MASK              0x1
-#define GC_USB_GRSTCTL_CSFTRST_SIZE              0x1
-#define GC_USB_GRSTCTL_CSFTRST_DEFAULT           0x0
-#define GC_USB_GRSTCTL_CSFTRST_OFFSET            0x10
-#define GC_USB_GRSTCTL_PIUFSSFTRST_LSB           0x1
-#define GC_USB_GRSTCTL_PIUFSSFTRST_MASK          0x2
-#define GC_USB_GRSTCTL_PIUFSSFTRST_SIZE          0x1
-#define GC_USB_GRSTCTL_PIUFSSFTRST_DEFAULT       0x0
-#define GC_USB_GRSTCTL_PIUFSSFTRST_OFFSET        0x10
-#define GC_USB_GRSTCTL_RXFFLSH_LSB               0x4
-#define GC_USB_GRSTCTL_RXFFLSH_MASK              0x10
-#define GC_USB_GRSTCTL_RXFFLSH_SIZE              0x1
-#define GC_USB_GRSTCTL_RXFFLSH_DEFAULT           0x0
-#define GC_USB_GRSTCTL_RXFFLSH_OFFSET            0x10
-#define GC_USB_GRSTCTL_TXFFLSH_LSB               0x5
-#define GC_USB_GRSTCTL_TXFFLSH_MASK              0x20
-#define GC_USB_GRSTCTL_TXFFLSH_SIZE              0x1
-#define GC_USB_GRSTCTL_TXFFLSH_DEFAULT           0x0
-#define GC_USB_GRSTCTL_TXFFLSH_OFFSET            0x10
-#define GC_USB_GRSTCTL_TXFNUM_LSB                0x6
-#define GC_USB_GRSTCTL_TXFNUM_MASK               0x7c0
-#define GC_USB_GRSTCTL_TXFNUM_SIZE               0x5
-#define GC_USB_GRSTCTL_TXFNUM_DEFAULT            0x0
-#define GC_USB_GRSTCTL_TXFNUM_OFFSET             0x10
-#define GC_USB_GRSTCTL_DMAREQ_LSB                0x1e
-#define GC_USB_GRSTCTL_DMAREQ_MASK               0x40000000
-#define GC_USB_GRSTCTL_DMAREQ_SIZE               0x1
-#define GC_USB_GRSTCTL_DMAREQ_DEFAULT            0x0
-#define GC_USB_GRSTCTL_DMAREQ_OFFSET             0x10
-#define GC_USB_GRSTCTL_AHBIDLE_LSB               0x1f
-#define GC_USB_GRSTCTL_AHBIDLE_MASK              0x80000000
-#define GC_USB_GRSTCTL_AHBIDLE_SIZE              0x1
-#define GC_USB_GRSTCTL_AHBIDLE_DEFAULT           0x0
-#define GC_USB_GRSTCTL_AHBIDLE_OFFSET            0x10
-#define GC_USB_GINTSTS_CURMOD_LSB                0x0
-#define GC_USB_GINTSTS_CURMOD_MASK               0x1
-#define GC_USB_GINTSTS_CURMOD_SIZE               0x1
-#define GC_USB_GINTSTS_CURMOD_DEFAULT            0x0
-#define GC_USB_GINTSTS_CURMOD_OFFSET             0x14
-#define GC_USB_GINTSTS_MODEMIS_LSB               0x1
-#define GC_USB_GINTSTS_MODEMIS_MASK              0x2
-#define GC_USB_GINTSTS_MODEMIS_SIZE              0x1
-#define GC_USB_GINTSTS_MODEMIS_DEFAULT           0x0
-#define GC_USB_GINTSTS_MODEMIS_OFFSET            0x14
-#define GC_USB_GINTSTS_OTGINT_LSB                0x2
-#define GC_USB_GINTSTS_OTGINT_MASK               0x4
-#define GC_USB_GINTSTS_OTGINT_SIZE               0x1
-#define GC_USB_GINTSTS_OTGINT_DEFAULT            0x0
-#define GC_USB_GINTSTS_OTGINT_OFFSET             0x14
-#define GC_USB_GINTSTS_SOF_LSB                   0x3
-#define GC_USB_GINTSTS_SOF_MASK                  0x8
-#define GC_USB_GINTSTS_SOF_SIZE                  0x1
-#define GC_USB_GINTSTS_SOF_DEFAULT               0x0
-#define GC_USB_GINTSTS_SOF_OFFSET                0x14
-#define GC_USB_GINTSTS_RXFLVL_LSB                0x4
-#define GC_USB_GINTSTS_RXFLVL_MASK               0x10
-#define GC_USB_GINTSTS_RXFLVL_SIZE               0x1
-#define GC_USB_GINTSTS_RXFLVL_DEFAULT            0x0
-#define GC_USB_GINTSTS_RXFLVL_OFFSET             0x14
-#define GC_USB_GINTSTS_GINNAKEFF_LSB             0x6
-#define GC_USB_GINTSTS_GINNAKEFF_MASK            0x40
-#define GC_USB_GINTSTS_GINNAKEFF_SIZE            0x1
-#define GC_USB_GINTSTS_GINNAKEFF_DEFAULT         0x0
-#define GC_USB_GINTSTS_GINNAKEFF_OFFSET          0x14
-#define GC_USB_GINTSTS_GOUTNAKEFF_LSB            0x7
-#define GC_USB_GINTSTS_GOUTNAKEFF_MASK           0x80
-#define GC_USB_GINTSTS_GOUTNAKEFF_SIZE           0x1
-#define GC_USB_GINTSTS_GOUTNAKEFF_DEFAULT        0x0
-#define GC_USB_GINTSTS_GOUTNAKEFF_OFFSET         0x14
-#define GC_USB_GINTSTS_ERLYSUSP_LSB              0xa
-#define GC_USB_GINTSTS_ERLYSUSP_MASK             0x400
-#define GC_USB_GINTSTS_ERLYSUSP_SIZE             0x1
-#define GC_USB_GINTSTS_ERLYSUSP_DEFAULT          0x0
-#define GC_USB_GINTSTS_ERLYSUSP_OFFSET           0x14
-#define GC_USB_GINTSTS_USBSUSP_LSB               0xb
-#define GC_USB_GINTSTS_USBSUSP_MASK              0x800
-#define GC_USB_GINTSTS_USBSUSP_SIZE              0x1
-#define GC_USB_GINTSTS_USBSUSP_DEFAULT           0x0
-#define GC_USB_GINTSTS_USBSUSP_OFFSET            0x14
-#define GC_USB_GINTSTS_USBRST_LSB                0xc
-#define GC_USB_GINTSTS_USBRST_MASK               0x1000
-#define GC_USB_GINTSTS_USBRST_SIZE               0x1
-#define GC_USB_GINTSTS_USBRST_DEFAULT            0x0
-#define GC_USB_GINTSTS_USBRST_OFFSET             0x14
-#define GC_USB_GINTSTS_ENUMDONE_LSB              0xd
-#define GC_USB_GINTSTS_ENUMDONE_MASK             0x2000
-#define GC_USB_GINTSTS_ENUMDONE_SIZE             0x1
-#define GC_USB_GINTSTS_ENUMDONE_DEFAULT          0x0
-#define GC_USB_GINTSTS_ENUMDONE_OFFSET           0x14
-#define GC_USB_GINTSTS_ISOOUTDROP_LSB            0xe
-#define GC_USB_GINTSTS_ISOOUTDROP_MASK           0x4000
-#define GC_USB_GINTSTS_ISOOUTDROP_SIZE           0x1
-#define GC_USB_GINTSTS_ISOOUTDROP_DEFAULT        0x0
-#define GC_USB_GINTSTS_ISOOUTDROP_OFFSET         0x14
-#define GC_USB_GINTSTS_EOPF_LSB                  0xf
-#define GC_USB_GINTSTS_EOPF_MASK                 0x8000
-#define GC_USB_GINTSTS_EOPF_SIZE                 0x1
-#define GC_USB_GINTSTS_EOPF_DEFAULT              0x0
-#define GC_USB_GINTSTS_EOPF_OFFSET               0x14
-#define GC_USB_GINTSTS_EPMIS_LSB                 0x11
-#define GC_USB_GINTSTS_EPMIS_MASK                0x20000
-#define GC_USB_GINTSTS_EPMIS_SIZE                0x1
-#define GC_USB_GINTSTS_EPMIS_DEFAULT             0x0
-#define GC_USB_GINTSTS_EPMIS_OFFSET              0x14
-#define GC_USB_GINTSTS_IEPINT_LSB                0x12
-#define GC_USB_GINTSTS_IEPINT_MASK               0x40000
-#define GC_USB_GINTSTS_IEPINT_SIZE               0x1
-#define GC_USB_GINTSTS_IEPINT_DEFAULT            0x0
-#define GC_USB_GINTSTS_IEPINT_OFFSET             0x14
-#define GC_USB_GINTSTS_OEPINT_LSB                0x13
-#define GC_USB_GINTSTS_OEPINT_MASK               0x80000
-#define GC_USB_GINTSTS_OEPINT_SIZE               0x1
-#define GC_USB_GINTSTS_OEPINT_DEFAULT            0x0
-#define GC_USB_GINTSTS_OEPINT_OFFSET             0x14
-#define GC_USB_GINTSTS_INCOMPISOIN_LSB           0x14
-#define GC_USB_GINTSTS_INCOMPISOIN_MASK          0x100000
-#define GC_USB_GINTSTS_INCOMPISOIN_SIZE          0x1
-#define GC_USB_GINTSTS_INCOMPISOIN_DEFAULT       0x0
-#define GC_USB_GINTSTS_INCOMPISOIN_OFFSET        0x14
-#define GC_USB_GINTSTS_INCOMPLP_LSB              0x15
-#define GC_USB_GINTSTS_INCOMPLP_MASK             0x200000
-#define GC_USB_GINTSTS_INCOMPLP_SIZE             0x1
-#define GC_USB_GINTSTS_INCOMPLP_DEFAULT          0x0
-#define GC_USB_GINTSTS_INCOMPLP_OFFSET           0x14
-#define GC_USB_GINTSTS_FETSUSP_LSB               0x16
-#define GC_USB_GINTSTS_FETSUSP_MASK              0x400000
-#define GC_USB_GINTSTS_FETSUSP_SIZE              0x1
-#define GC_USB_GINTSTS_FETSUSP_DEFAULT           0x0
-#define GC_USB_GINTSTS_FETSUSP_OFFSET            0x14
-#define GC_USB_GINTSTS_RESETDET_LSB              0x17
-#define GC_USB_GINTSTS_RESETDET_MASK             0x800000
-#define GC_USB_GINTSTS_RESETDET_SIZE             0x1
-#define GC_USB_GINTSTS_RESETDET_DEFAULT          0x0
-#define GC_USB_GINTSTS_RESETDET_OFFSET           0x14
-#define GC_USB_GINTSTS_CONIDSTSCHNG_LSB          0x1c
-#define GC_USB_GINTSTS_CONIDSTSCHNG_MASK         0x10000000
-#define GC_USB_GINTSTS_CONIDSTSCHNG_SIZE         0x1
-#define GC_USB_GINTSTS_CONIDSTSCHNG_DEFAULT      0x0
-#define GC_USB_GINTSTS_CONIDSTSCHNG_OFFSET       0x14
-#define GC_USB_GINTSTS_SESSREQINT_LSB            0x1e
-#define GC_USB_GINTSTS_SESSREQINT_MASK           0x40000000
-#define GC_USB_GINTSTS_SESSREQINT_SIZE           0x1
-#define GC_USB_GINTSTS_SESSREQINT_DEFAULT        0x0
-#define GC_USB_GINTSTS_SESSREQINT_OFFSET         0x14
-#define GC_USB_GINTSTS_WKUPINT_LSB               0x1f
-#define GC_USB_GINTSTS_WKUPINT_MASK              0x80000000
-#define GC_USB_GINTSTS_WKUPINT_SIZE              0x1
-#define GC_USB_GINTSTS_WKUPINT_DEFAULT           0x0
-#define GC_USB_GINTSTS_WKUPINT_OFFSET            0x14
-#define GC_USB_GINTMSK_MODEMISMSK_LSB            0x1
-#define GC_USB_GINTMSK_MODEMISMSK_MASK           0x2
-#define GC_USB_GINTMSK_MODEMISMSK_SIZE           0x1
-#define GC_USB_GINTMSK_MODEMISMSK_DEFAULT        0x0
-#define GC_USB_GINTMSK_MODEMISMSK_OFFSET         0x18
-#define GC_USB_GINTMSK_OTGINTMSK_LSB             0x2
-#define GC_USB_GINTMSK_OTGINTMSK_MASK            0x4
-#define GC_USB_GINTMSK_OTGINTMSK_SIZE            0x1
-#define GC_USB_GINTMSK_OTGINTMSK_DEFAULT         0x0
-#define GC_USB_GINTMSK_OTGINTMSK_OFFSET          0x18
-#define GC_USB_GINTMSK_SOFMSK_LSB                0x3
-#define GC_USB_GINTMSK_SOFMSK_MASK               0x8
-#define GC_USB_GINTMSK_SOFMSK_SIZE               0x1
-#define GC_USB_GINTMSK_SOFMSK_DEFAULT            0x0
-#define GC_USB_GINTMSK_SOFMSK_OFFSET             0x18
-#define GC_USB_GINTMSK_RXFLVLMSK_LSB             0x4
-#define GC_USB_GINTMSK_RXFLVLMSK_MASK            0x10
-#define GC_USB_GINTMSK_RXFLVLMSK_SIZE            0x1
-#define GC_USB_GINTMSK_RXFLVLMSK_DEFAULT         0x0
-#define GC_USB_GINTMSK_RXFLVLMSK_OFFSET          0x18
-#define GC_USB_GINTMSK_UNKNOWN5_LSB              0x5
-#define GC_USB_GINTMSK_UNKNOWN5_MASK             0x20
-#define GC_USB_GINTMSK_UNKNOWN5_SIZE             0x1
-#define GC_USB_GINTMSK_UNKNOWN5_DEFAULT          0x0
-#define GC_USB_GINTMSK_UNKNOWN5_OFFSET           0x18
-#define GC_USB_GINTMSK_GINNAKEFFMSK_LSB          0x6
-#define GC_USB_GINTMSK_GINNAKEFFMSK_MASK         0x40
-#define GC_USB_GINTMSK_GINNAKEFFMSK_SIZE         0x1
-#define GC_USB_GINTMSK_GINNAKEFFMSK_DEFAULT      0x0
-#define GC_USB_GINTMSK_GINNAKEFFMSK_OFFSET       0x18
-#define GC_USB_GINTMSK_GOUTNAKEFFMSK_LSB         0x7
-#define GC_USB_GINTMSK_GOUTNAKEFFMSK_MASK        0x80
-#define GC_USB_GINTMSK_GOUTNAKEFFMSK_SIZE        0x1
-#define GC_USB_GINTMSK_GOUTNAKEFFMSK_DEFAULT     0x0
-#define GC_USB_GINTMSK_GOUTNAKEFFMSK_OFFSET      0x18
-#define GC_USB_GINTMSK_ERLYSUSPMSK_LSB           0xa
-#define GC_USB_GINTMSK_ERLYSUSPMSK_MASK          0x400
-#define GC_USB_GINTMSK_ERLYSUSPMSK_SIZE          0x1
-#define GC_USB_GINTMSK_ERLYSUSPMSK_DEFAULT       0x0
-#define GC_USB_GINTMSK_ERLYSUSPMSK_OFFSET        0x18
-#define GC_USB_GINTMSK_USBSUSPMSK_LSB            0xb
-#define GC_USB_GINTMSK_USBSUSPMSK_MASK           0x800
-#define GC_USB_GINTMSK_USBSUSPMSK_SIZE           0x1
-#define GC_USB_GINTMSK_USBSUSPMSK_DEFAULT        0x0
-#define GC_USB_GINTMSK_USBSUSPMSK_OFFSET         0x18
-#define GC_USB_GINTMSK_USBRSTMSK_LSB             0xc
-#define GC_USB_GINTMSK_USBRSTMSK_MASK            0x1000
-#define GC_USB_GINTMSK_USBRSTMSK_SIZE            0x1
-#define GC_USB_GINTMSK_USBRSTMSK_DEFAULT         0x0
-#define GC_USB_GINTMSK_USBRSTMSK_OFFSET          0x18
-#define GC_USB_GINTMSK_ENUMDONEMSK_LSB           0xd
-#define GC_USB_GINTMSK_ENUMDONEMSK_MASK          0x2000
-#define GC_USB_GINTMSK_ENUMDONEMSK_SIZE          0x1
-#define GC_USB_GINTMSK_ENUMDONEMSK_DEFAULT       0x0
-#define GC_USB_GINTMSK_ENUMDONEMSK_OFFSET        0x18
-#define GC_USB_GINTMSK_ISOOUTDROPMSK_LSB         0xe
-#define GC_USB_GINTMSK_ISOOUTDROPMSK_MASK        0x4000
-#define GC_USB_GINTMSK_ISOOUTDROPMSK_SIZE        0x1
-#define GC_USB_GINTMSK_ISOOUTDROPMSK_DEFAULT     0x0
-#define GC_USB_GINTMSK_ISOOUTDROPMSK_OFFSET      0x18
-#define GC_USB_GINTMSK_EOPFMSK_LSB               0xf
-#define GC_USB_GINTMSK_EOPFMSK_MASK              0x8000
-#define GC_USB_GINTMSK_EOPFMSK_SIZE              0x1
-#define GC_USB_GINTMSK_EOPFMSK_DEFAULT           0x0
-#define GC_USB_GINTMSK_EOPFMSK_OFFSET            0x18
-#define GC_USB_GINTMSK_UNKNOWN16_LSB             0x10
-#define GC_USB_GINTMSK_UNKNOWN16_MASK            0x10000
-#define GC_USB_GINTMSK_UNKNOWN16_SIZE            0x1
-#define GC_USB_GINTMSK_UNKNOWN16_DEFAULT         0x0
-#define GC_USB_GINTMSK_UNKNOWN16_OFFSET          0x18
-#define GC_USB_GINTMSK_EPMISMSK_LSB              0x11
-#define GC_USB_GINTMSK_EPMISMSK_MASK             0x20000
-#define GC_USB_GINTMSK_EPMISMSK_SIZE             0x1
-#define GC_USB_GINTMSK_EPMISMSK_DEFAULT          0x0
-#define GC_USB_GINTMSK_EPMISMSK_OFFSET           0x18
-#define GC_USB_GINTMSK_IEPINTMSK_LSB             0x12
-#define GC_USB_GINTMSK_IEPINTMSK_MASK            0x40000
-#define GC_USB_GINTMSK_IEPINTMSK_SIZE            0x1
-#define GC_USB_GINTMSK_IEPINTMSK_DEFAULT         0x0
-#define GC_USB_GINTMSK_IEPINTMSK_OFFSET          0x18
-#define GC_USB_GINTMSK_OEPINTMSK_LSB             0x13
-#define GC_USB_GINTMSK_OEPINTMSK_MASK            0x80000
-#define GC_USB_GINTMSK_OEPINTMSK_SIZE            0x1
-#define GC_USB_GINTMSK_OEPINTMSK_DEFAULT         0x0
-#define GC_USB_GINTMSK_OEPINTMSK_OFFSET          0x18
-#define GC_USB_GINTMSK_INCOMPISOINMSK_LSB        0x14
-#define GC_USB_GINTMSK_INCOMPISOINMSK_MASK       0x100000
-#define GC_USB_GINTMSK_INCOMPISOINMSK_SIZE       0x1
-#define GC_USB_GINTMSK_INCOMPISOINMSK_DEFAULT    0x0
-#define GC_USB_GINTMSK_INCOMPISOINMSK_OFFSET     0x18
-#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_LSB      0x15
-#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_MASK     0x200000
-#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_SIZE     0x1
-#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_DEFAULT  0x0
-#define GC_USB_GINTMSK_INCOMPLISOOUTMSK_OFFSET   0x18
-#define GC_USB_GINTMSK_FETSUSPMSK_LSB            0x16
-#define GC_USB_GINTMSK_FETSUSPMSK_MASK           0x400000
-#define GC_USB_GINTMSK_FETSUSPMSK_SIZE           0x1
-#define GC_USB_GINTMSK_FETSUSPMSK_DEFAULT        0x0
-#define GC_USB_GINTMSK_FETSUSPMSK_OFFSET         0x18
-#define GC_USB_GINTMSK_RESETDETMSK_LSB           0x17
-#define GC_USB_GINTMSK_RESETDETMSK_MASK          0x800000
-#define GC_USB_GINTMSK_RESETDETMSK_SIZE          0x1
-#define GC_USB_GINTMSK_RESETDETMSK_DEFAULT       0x0
-#define GC_USB_GINTMSK_RESETDETMSK_OFFSET        0x18
-#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_LSB       0x1c
-#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_MASK      0x10000000
-#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_SIZE      0x1
-#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_DEFAULT   0x0
-#define GC_USB_GINTMSK_CONIDSTSCHNGMSK_OFFSET    0x18
-#define GC_USB_GINTMSK_DISCONNINTMSK_LSB         0x1d
-#define GC_USB_GINTMSK_DISCONNINTMSK_MASK        0x20000000
-#define GC_USB_GINTMSK_DISCONNINTMSK_SIZE        0x1
-#define GC_USB_GINTMSK_DISCONNINTMSK_DEFAULT     0x0
-#define GC_USB_GINTMSK_DISCONNINTMSK_OFFSET      0x18
-#define GC_USB_GINTMSK_SESSREQINTMSK_LSB         0x1e
-#define GC_USB_GINTMSK_SESSREQINTMSK_MASK        0x40000000
-#define GC_USB_GINTMSK_SESSREQINTMSK_SIZE        0x1
-#define GC_USB_GINTMSK_SESSREQINTMSK_DEFAULT     0x0
-#define GC_USB_GINTMSK_SESSREQINTMSK_OFFSET      0x18
-#define GC_USB_GINTMSK_WKUPINTMSK_LSB            0x1f
-#define GC_USB_GINTMSK_WKUPINTMSK_MASK           0x80000000
-#define GC_USB_GINTMSK_WKUPINTMSK_SIZE           0x1
-#define GC_USB_GINTMSK_WKUPINTMSK_DEFAULT        0x0
-#define GC_USB_GINTMSK_WKUPINTMSK_OFFSET         0x18
-#define GC_USB_GRXSTSR_CHNUM_LSB                 0x0
-#define GC_USB_GRXSTSR_CHNUM_MASK                0xf
-#define GC_USB_GRXSTSR_CHNUM_SIZE                0x4
-#define GC_USB_GRXSTSR_CHNUM_DEFAULT             0x0
-#define GC_USB_GRXSTSR_CHNUM_OFFSET              0x1c
-#define GC_USB_GRXSTSR_BCNT_LSB                  0x4
-#define GC_USB_GRXSTSR_BCNT_MASK                 0x7ff0
-#define GC_USB_GRXSTSR_BCNT_SIZE                 0xb
-#define GC_USB_GRXSTSR_BCNT_DEFAULT              0x0
-#define GC_USB_GRXSTSR_BCNT_OFFSET               0x1c
-#define GC_USB_GRXSTSR_DPID_LSB                  0xf
-#define GC_USB_GRXSTSR_DPID_MASK                 0x18000
-#define GC_USB_GRXSTSR_DPID_SIZE                 0x2
-#define GC_USB_GRXSTSR_DPID_DEFAULT              0x0
-#define GC_USB_GRXSTSR_DPID_OFFSET               0x1c
-#define GC_USB_GRXSTSR_PKTSTS_LSB                0x11
-#define GC_USB_GRXSTSR_PKTSTS_MASK               0x1e0000
-#define GC_USB_GRXSTSR_PKTSTS_SIZE               0x4
-#define GC_USB_GRXSTSR_PKTSTS_DEFAULT            0x0
-#define GC_USB_GRXSTSR_PKTSTS_OFFSET             0x1c
-#define GC_USB_GRXSTSR_FN_LSB                    0x15
-#define GC_USB_GRXSTSR_FN_MASK                   0x1e00000
-#define GC_USB_GRXSTSR_FN_SIZE                   0x4
-#define GC_USB_GRXSTSR_FN_DEFAULT                0x0
-#define GC_USB_GRXSTSR_FN_OFFSET                 0x1c
-#define GC_USB_GRXSTSP_CHNUM_LSB                 0x0
-#define GC_USB_GRXSTSP_CHNUM_MASK                0xf
-#define GC_USB_GRXSTSP_CHNUM_SIZE                0x4
-#define GC_USB_GRXSTSP_CHNUM_DEFAULT             0x0
-#define GC_USB_GRXSTSP_CHNUM_OFFSET              0x20
-#define GC_USB_GRXSTSP_BCNT_LSB                  0x4
-#define GC_USB_GRXSTSP_BCNT_MASK                 0x7ff0
-#define GC_USB_GRXSTSP_BCNT_SIZE                 0xb
-#define GC_USB_GRXSTSP_BCNT_DEFAULT              0x0
-#define GC_USB_GRXSTSP_BCNT_OFFSET               0x20
-#define GC_USB_GRXSTSP_DPID_LSB                  0xf
-#define GC_USB_GRXSTSP_DPID_MASK                 0x18000
-#define GC_USB_GRXSTSP_DPID_SIZE                 0x2
-#define GC_USB_GRXSTSP_DPID_DEFAULT              0x0
-#define GC_USB_GRXSTSP_DPID_OFFSET               0x20
-#define GC_USB_GRXSTSP_PKTSTS_LSB                0x11
-#define GC_USB_GRXSTSP_PKTSTS_MASK               0x1e0000
-#define GC_USB_GRXSTSP_PKTSTS_SIZE               0x4
-#define GC_USB_GRXSTSP_PKTSTS_DEFAULT            0x0
-#define GC_USB_GRXSTSP_PKTSTS_OFFSET             0x20
-#define GC_USB_GRXSTSP_FN_LSB                    0x15
-#define GC_USB_GRXSTSP_FN_MASK                   0x1e00000
-#define GC_USB_GRXSTSP_FN_SIZE                   0x4
-#define GC_USB_GRXSTSP_FN_DEFAULT                0x0
-#define GC_USB_GRXSTSP_FN_OFFSET                 0x20
-#define GC_USB_GRXFSIZ_RXFDEP_LSB                0x0
-#define GC_USB_GRXFSIZ_RXFDEP_MASK               0x7ff
-#define GC_USB_GRXFSIZ_RXFDEP_SIZE               0xb
-#define GC_USB_GRXFSIZ_RXFDEP_DEFAULT            0x0
-#define GC_USB_GRXFSIZ_RXFDEP_OFFSET             0x24
-#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_LSB      0x0
-#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_MASK     0xffff
-#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_SIZE     0x10
-#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_DEFAULT  0x0
-#define GC_USB_GNPTXFSIZ_INEPTXF0STADDR_OFFSET   0x28
-#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_LSB         0x10
-#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_MASK        0xffff0000
-#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_SIZE        0x10
-#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_DEFAULT     0x0
-#define GC_USB_GNPTXFSIZ_INEPTXF0DEP_OFFSET      0x28
-#define GC_USB_GGPIO_GPI_LSB                     0x0
-#define GC_USB_GGPIO_GPI_MASK                    0xffff
-#define GC_USB_GGPIO_GPI_SIZE                    0x10
-#define GC_USB_GGPIO_GPI_DEFAULT                 0x0
-#define GC_USB_GGPIO_GPI_OFFSET                  0x38
-#define GC_USB_GGPIO_GPO_LSB                     0x10
-#define GC_USB_GGPIO_GPO_MASK                    0xffff0000
-#define GC_USB_GGPIO_GPO_SIZE                    0x10
-#define GC_USB_GGPIO_GPO_DEFAULT                 0x0
-#define GC_USB_GGPIO_GPO_OFFSET                  0x38
-#define GC_USB_GUID_GUID_LSB                     0x0
-#define GC_USB_GUID_GUID_MASK                    0xffffffff
-#define GC_USB_GUID_GUID_SIZE                    0x20
-#define GC_USB_GUID_GUID_DEFAULT                 0x0
-#define GC_USB_GUID_GUID_OFFSET                  0x3c
-#define GC_USB_GSNPSID_SYNOPSYSID_LSB            0x0
-#define GC_USB_GSNPSID_SYNOPSYSID_MASK           0xffffffff
-#define GC_USB_GSNPSID_SYNOPSYSID_SIZE           0x20
-#define GC_USB_GSNPSID_SYNOPSYSID_DEFAULT        0x0
-#define GC_USB_GSNPSID_SYNOPSYSID_OFFSET         0x40
-#define GC_USB_GHWCFG1_EPDIR_LSB                 0x0
-#define GC_USB_GHWCFG1_EPDIR_MASK                0xffffffff
-#define GC_USB_GHWCFG1_EPDIR_SIZE                0x20
-#define GC_USB_GHWCFG1_EPDIR_DEFAULT             0x0
-#define GC_USB_GHWCFG1_EPDIR_OFFSET              0x44
-#define GC_USB_GHWCFG2_OTGMODE_LSB               0x0
-#define GC_USB_GHWCFG2_OTGMODE_MASK              0x7
-#define GC_USB_GHWCFG2_OTGMODE_SIZE              0x3
-#define GC_USB_GHWCFG2_OTGMODE_DEFAULT           0x0
-#define GC_USB_GHWCFG2_OTGMODE_OFFSET            0x48
-#define GC_USB_GHWCFG2_OTGARCH_LSB               0x3
-#define GC_USB_GHWCFG2_OTGARCH_MASK              0x18
-#define GC_USB_GHWCFG2_OTGARCH_SIZE              0x2
-#define GC_USB_GHWCFG2_OTGARCH_DEFAULT           0x0
-#define GC_USB_GHWCFG2_OTGARCH_OFFSET            0x48
-#define GC_USB_GHWCFG2_SINGPNT_LSB               0x5
-#define GC_USB_GHWCFG2_SINGPNT_MASK              0x20
-#define GC_USB_GHWCFG2_SINGPNT_SIZE              0x1
-#define GC_USB_GHWCFG2_SINGPNT_DEFAULT           0x0
-#define GC_USB_GHWCFG2_SINGPNT_OFFSET            0x48
-#define GC_USB_GHWCFG2_HSPHYTYPE_LSB             0x6
-#define GC_USB_GHWCFG2_HSPHYTYPE_MASK            0xc0
-#define GC_USB_GHWCFG2_HSPHYTYPE_SIZE            0x2
-#define GC_USB_GHWCFG2_HSPHYTYPE_DEFAULT         0x0
-#define GC_USB_GHWCFG2_HSPHYTYPE_OFFSET          0x48
-#define GC_USB_GHWCFG2_FSPHYTYPE_LSB             0x8
-#define GC_USB_GHWCFG2_FSPHYTYPE_MASK            0x300
-#define GC_USB_GHWCFG2_FSPHYTYPE_SIZE            0x2
-#define GC_USB_GHWCFG2_FSPHYTYPE_DEFAULT         0x0
-#define GC_USB_GHWCFG2_FSPHYTYPE_OFFSET          0x48
-#define GC_USB_GHWCFG2_NUMDEVEPS_LSB             0xa
-#define GC_USB_GHWCFG2_NUMDEVEPS_MASK            0x3c00
-#define GC_USB_GHWCFG2_NUMDEVEPS_SIZE            0x4
-#define GC_USB_GHWCFG2_NUMDEVEPS_DEFAULT         0x0
-#define GC_USB_GHWCFG2_NUMDEVEPS_OFFSET          0x48
-#define GC_USB_GHWCFG2_NUMHSTCHNL_LSB            0xe
-#define GC_USB_GHWCFG2_NUMHSTCHNL_MASK           0x3c000
-#define GC_USB_GHWCFG2_NUMHSTCHNL_SIZE           0x4
-#define GC_USB_GHWCFG2_NUMHSTCHNL_DEFAULT        0x0
-#define GC_USB_GHWCFG2_NUMHSTCHNL_OFFSET         0x48
-#define GC_USB_GHWCFG2_PERIOSUPPORT_LSB          0x12
-#define GC_USB_GHWCFG2_PERIOSUPPORT_MASK         0x40000
-#define GC_USB_GHWCFG2_PERIOSUPPORT_SIZE         0x1
-#define GC_USB_GHWCFG2_PERIOSUPPORT_DEFAULT      0x0
-#define GC_USB_GHWCFG2_PERIOSUPPORT_OFFSET       0x48
-#define GC_USB_GHWCFG2_DYNFIFOSIZING_LSB         0x13
-#define GC_USB_GHWCFG2_DYNFIFOSIZING_MASK        0x80000
-#define GC_USB_GHWCFG2_DYNFIFOSIZING_SIZE        0x1
-#define GC_USB_GHWCFG2_DYNFIFOSIZING_DEFAULT     0x0
-#define GC_USB_GHWCFG2_DYNFIFOSIZING_OFFSET      0x48
-#define GC_USB_GHWCFG2_MULTIPROCINTRPT_LSB       0x14
-#define GC_USB_GHWCFG2_MULTIPROCINTRPT_MASK      0x100000
-#define GC_USB_GHWCFG2_MULTIPROCINTRPT_SIZE      0x1
-#define GC_USB_GHWCFG2_MULTIPROCINTRPT_DEFAULT   0x0
-#define GC_USB_GHWCFG2_MULTIPROCINTRPT_OFFSET    0x48
-#define GC_USB_GHWCFG2_NPTXQDEPTH_LSB            0x16
-#define GC_USB_GHWCFG2_NPTXQDEPTH_MASK           0xc00000
-#define GC_USB_GHWCFG2_NPTXQDEPTH_SIZE           0x2
-#define GC_USB_GHWCFG2_NPTXQDEPTH_DEFAULT        0x0
-#define GC_USB_GHWCFG2_NPTXQDEPTH_OFFSET         0x48
-#define GC_USB_GHWCFG2_PTXQDEPTH_LSB             0x18
-#define GC_USB_GHWCFG2_PTXQDEPTH_MASK            0x3000000
-#define GC_USB_GHWCFG2_PTXQDEPTH_SIZE            0x2
-#define GC_USB_GHWCFG2_PTXQDEPTH_DEFAULT         0x0
-#define GC_USB_GHWCFG2_PTXQDEPTH_OFFSET          0x48
-#define GC_USB_GHWCFG2_TKNQDEPTH_LSB             0x1a
-#define GC_USB_GHWCFG2_TKNQDEPTH_MASK            0x7c000000
-#define GC_USB_GHWCFG2_TKNQDEPTH_SIZE            0x5
-#define GC_USB_GHWCFG2_TKNQDEPTH_DEFAULT         0x0
-#define GC_USB_GHWCFG2_TKNQDEPTH_OFFSET          0x48
-#define GC_USB_GHWCFG3_XFERSIZEWIDTH_LSB         0x0
-#define GC_USB_GHWCFG3_XFERSIZEWIDTH_MASK        0xf
-#define GC_USB_GHWCFG3_XFERSIZEWIDTH_SIZE        0x4
-#define GC_USB_GHWCFG3_XFERSIZEWIDTH_DEFAULT     0x0
-#define GC_USB_GHWCFG3_XFERSIZEWIDTH_OFFSET      0x4c
-#define GC_USB_GHWCFG3_PKTSIZEWIDTH_LSB          0x4
-#define GC_USB_GHWCFG3_PKTSIZEWIDTH_MASK         0x70
-#define GC_USB_GHWCFG3_PKTSIZEWIDTH_SIZE         0x3
-#define GC_USB_GHWCFG3_PKTSIZEWIDTH_DEFAULT      0x0
-#define GC_USB_GHWCFG3_PKTSIZEWIDTH_OFFSET       0x4c
-#define GC_USB_GHWCFG3_OTGEN_LSB                 0x7
-#define GC_USB_GHWCFG3_OTGEN_MASK                0x80
-#define GC_USB_GHWCFG3_OTGEN_SIZE                0x1
-#define GC_USB_GHWCFG3_OTGEN_DEFAULT             0x0
-#define GC_USB_GHWCFG3_OTGEN_OFFSET              0x4c
-#define GC_USB_GHWCFG3_I2CINTSEL_LSB             0x8
-#define GC_USB_GHWCFG3_I2CINTSEL_MASK            0x100
-#define GC_USB_GHWCFG3_I2CINTSEL_SIZE            0x1
-#define GC_USB_GHWCFG3_I2CINTSEL_DEFAULT         0x0
-#define GC_USB_GHWCFG3_I2CINTSEL_OFFSET          0x4c
-#define GC_USB_GHWCFG3_VNDCTLSUPT_LSB            0x9
-#define GC_USB_GHWCFG3_VNDCTLSUPT_MASK           0x200
-#define GC_USB_GHWCFG3_VNDCTLSUPT_SIZE           0x1
-#define GC_USB_GHWCFG3_VNDCTLSUPT_DEFAULT        0x0
-#define GC_USB_GHWCFG3_VNDCTLSUPT_OFFSET         0x4c
-#define GC_USB_GHWCFG3_OPTFEATURE_LSB            0xa
-#define GC_USB_GHWCFG3_OPTFEATURE_MASK           0x400
-#define GC_USB_GHWCFG3_OPTFEATURE_SIZE           0x1
-#define GC_USB_GHWCFG3_OPTFEATURE_DEFAULT        0x0
-#define GC_USB_GHWCFG3_OPTFEATURE_OFFSET         0x4c
-#define GC_USB_GHWCFG3_RSTTYPE_LSB               0xb
-#define GC_USB_GHWCFG3_RSTTYPE_MASK              0x800
-#define GC_USB_GHWCFG3_RSTTYPE_SIZE              0x1
-#define GC_USB_GHWCFG3_RSTTYPE_DEFAULT           0x0
-#define GC_USB_GHWCFG3_RSTTYPE_OFFSET            0x4c
-#define GC_USB_GHWCFG3_ADPSUPPORT_LSB            0xc
-#define GC_USB_GHWCFG3_ADPSUPPORT_MASK           0x1000
-#define GC_USB_GHWCFG3_ADPSUPPORT_SIZE           0x1
-#define GC_USB_GHWCFG3_ADPSUPPORT_DEFAULT        0x0
-#define GC_USB_GHWCFG3_ADPSUPPORT_OFFSET         0x4c
-#define GC_USB_GHWCFG3_HSICMODE_LSB              0xd
-#define GC_USB_GHWCFG3_HSICMODE_MASK             0x2000
-#define GC_USB_GHWCFG3_HSICMODE_SIZE             0x1
-#define GC_USB_GHWCFG3_HSICMODE_DEFAULT          0x0
-#define GC_USB_GHWCFG3_HSICMODE_OFFSET           0x4c
-#define GC_USB_GHWCFG3_BCSUPPORT_LSB             0xe
-#define GC_USB_GHWCFG3_BCSUPPORT_MASK            0x4000
-#define GC_USB_GHWCFG3_BCSUPPORT_SIZE            0x1
-#define GC_USB_GHWCFG3_BCSUPPORT_DEFAULT         0x0
-#define GC_USB_GHWCFG3_BCSUPPORT_OFFSET          0x4c
-#define GC_USB_GHWCFG3_LPMMODE_LSB               0xf
-#define GC_USB_GHWCFG3_LPMMODE_MASK              0x8000
-#define GC_USB_GHWCFG3_LPMMODE_SIZE              0x1
-#define GC_USB_GHWCFG3_LPMMODE_DEFAULT           0x0
-#define GC_USB_GHWCFG3_LPMMODE_OFFSET            0x4c
-#define GC_USB_GHWCFG3_DFIFODEPTH_LSB            0x10
-#define GC_USB_GHWCFG3_DFIFODEPTH_MASK           0xffff0000
-#define GC_USB_GHWCFG3_DFIFODEPTH_SIZE           0x10
-#define GC_USB_GHWCFG3_DFIFODEPTH_DEFAULT        0x0
-#define GC_USB_GHWCFG3_DFIFODEPTH_OFFSET         0x4c
-#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_LSB        0x0
-#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_MASK       0xf
-#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_SIZE       0x4
-#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_DEFAULT    0x0
-#define GC_USB_GHWCFG4_NUMDEVPERIOEPS_OFFSET     0x50
-#define GC_USB_GHWCFG4_PARTIALPWRDN_LSB          0x4
-#define GC_USB_GHWCFG4_PARTIALPWRDN_MASK         0x10
-#define GC_USB_GHWCFG4_PARTIALPWRDN_SIZE         0x1
-#define GC_USB_GHWCFG4_PARTIALPWRDN_DEFAULT      0x0
-#define GC_USB_GHWCFG4_PARTIALPWRDN_OFFSET       0x50
-#define GC_USB_GHWCFG4_AHBFREQ_LSB               0x5
-#define GC_USB_GHWCFG4_AHBFREQ_MASK              0x20
-#define GC_USB_GHWCFG4_AHBFREQ_SIZE              0x1
-#define GC_USB_GHWCFG4_AHBFREQ_DEFAULT           0x0
-#define GC_USB_GHWCFG4_AHBFREQ_OFFSET            0x50
-#define GC_USB_GHWCFG4_HIBERNATION_LSB           0x6
-#define GC_USB_GHWCFG4_HIBERNATION_MASK          0x40
-#define GC_USB_GHWCFG4_HIBERNATION_SIZE          0x1
-#define GC_USB_GHWCFG4_HIBERNATION_DEFAULT       0x0
-#define GC_USB_GHWCFG4_HIBERNATION_OFFSET        0x50
-#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_LSB   0x7
-#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_MASK  0x80
-#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_SIZE  0x1
-#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_DEFAULT 0x0
-#define GC_USB_GHWCFG4_EXTENDEDHIBERNATION_OFFSET 0x50
-#define GC_USB_GHWCFG4_PHYDATAWIDTH_LSB          0xe
-#define GC_USB_GHWCFG4_PHYDATAWIDTH_MASK         0xc000
-#define GC_USB_GHWCFG4_PHYDATAWIDTH_SIZE         0x2
-#define GC_USB_GHWCFG4_PHYDATAWIDTH_DEFAULT      0x0
-#define GC_USB_GHWCFG4_PHYDATAWIDTH_OFFSET       0x50
-#define GC_USB_GHWCFG4_NUMCTLEPS_LSB             0x10
-#define GC_USB_GHWCFG4_NUMCTLEPS_MASK            0xf0000
-#define GC_USB_GHWCFG4_NUMCTLEPS_SIZE            0x4
-#define GC_USB_GHWCFG4_NUMCTLEPS_DEFAULT         0x0
-#define GC_USB_GHWCFG4_NUMCTLEPS_OFFSET          0x50
-#define GC_USB_GHWCFG4_IDDGFLTR_LSB              0x14
-#define GC_USB_GHWCFG4_IDDGFLTR_MASK             0x100000
-#define GC_USB_GHWCFG4_IDDGFLTR_SIZE             0x1
-#define GC_USB_GHWCFG4_IDDGFLTR_DEFAULT          0x0
-#define GC_USB_GHWCFG4_IDDGFLTR_OFFSET           0x50
-#define GC_USB_GHWCFG4_VBUSVALIDFLTR_LSB         0x15
-#define GC_USB_GHWCFG4_VBUSVALIDFLTR_MASK        0x200000
-#define GC_USB_GHWCFG4_VBUSVALIDFLTR_SIZE        0x1
-#define GC_USB_GHWCFG4_VBUSVALIDFLTR_DEFAULT     0x0
-#define GC_USB_GHWCFG4_VBUSVALIDFLTR_OFFSET      0x50
-#define GC_USB_GHWCFG4_AVALIDFLTR_LSB            0x16
-#define GC_USB_GHWCFG4_AVALIDFLTR_MASK           0x400000
-#define GC_USB_GHWCFG4_AVALIDFLTR_SIZE           0x1
-#define GC_USB_GHWCFG4_AVALIDFLTR_DEFAULT        0x0
-#define GC_USB_GHWCFG4_AVALIDFLTR_OFFSET         0x50
-#define GC_USB_GHWCFG4_BVALIDFLTR_LSB            0x17
-#define GC_USB_GHWCFG4_BVALIDFLTR_MASK           0x800000
-#define GC_USB_GHWCFG4_BVALIDFLTR_SIZE           0x1
-#define GC_USB_GHWCFG4_BVALIDFLTR_DEFAULT        0x0
-#define GC_USB_GHWCFG4_BVALIDFLTR_OFFSET         0x50
-#define GC_USB_GHWCFG4_SESSENDFLTR_LSB           0x18
-#define GC_USB_GHWCFG4_SESSENDFLTR_MASK          0x1000000
-#define GC_USB_GHWCFG4_SESSENDFLTR_SIZE          0x1
-#define GC_USB_GHWCFG4_SESSENDFLTR_DEFAULT       0x0
-#define GC_USB_GHWCFG4_SESSENDFLTR_OFFSET        0x50
-#define GC_USB_GHWCFG4_DEDFIFOMODE_LSB           0x19
-#define GC_USB_GHWCFG4_DEDFIFOMODE_MASK          0x2000000
-#define GC_USB_GHWCFG4_DEDFIFOMODE_SIZE          0x1
-#define GC_USB_GHWCFG4_DEDFIFOMODE_DEFAULT       0x0
-#define GC_USB_GHWCFG4_DEDFIFOMODE_OFFSET        0x50
-#define GC_USB_GHWCFG4_INEPS_LSB                 0x1a
-#define GC_USB_GHWCFG4_INEPS_MASK                0x3c000000
-#define GC_USB_GHWCFG4_INEPS_SIZE                0x4
-#define GC_USB_GHWCFG4_INEPS_DEFAULT             0x0
-#define GC_USB_GHWCFG4_INEPS_OFFSET              0x50
-#define GC_USB_GHWCFG4_DESCDMAENABLED_LSB        0x1e
-#define GC_USB_GHWCFG4_DESCDMAENABLED_MASK       0x40000000
-#define GC_USB_GHWCFG4_DESCDMAENABLED_SIZE       0x1
-#define GC_USB_GHWCFG4_DESCDMAENABLED_DEFAULT    0x0
-#define GC_USB_GHWCFG4_DESCDMAENABLED_OFFSET     0x50
-#define GC_USB_GHWCFG4_DESCDMA_LSB               0x1f
-#define GC_USB_GHWCFG4_DESCDMA_MASK              0x80000000
-#define GC_USB_GHWCFG4_DESCDMA_SIZE              0x1
-#define GC_USB_GHWCFG4_DESCDMA_DEFAULT           0x0
-#define GC_USB_GHWCFG4_DESCDMA_OFFSET            0x50
-#define GC_USB_GDFIFOCFG_GDFIFOCFG_LSB           0x0
-#define GC_USB_GDFIFOCFG_GDFIFOCFG_MASK          0xffff
-#define GC_USB_GDFIFOCFG_GDFIFOCFG_SIZE          0x10
-#define GC_USB_GDFIFOCFG_GDFIFOCFG_DEFAULT       0x0
-#define GC_USB_GDFIFOCFG_GDFIFOCFG_OFFSET        0x5c
-#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_LSB      0x10
-#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_MASK     0xffff0000
-#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_SIZE     0x10
-#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_DEFAULT  0x0
-#define GC_USB_GDFIFOCFG_EPINFOBASEADDR_OFFSET   0x5c
-#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_LSB       0x0
-#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_MASK      0x7ff
-#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_SIZE      0xb
-#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_DEFAULT   0x0
-#define GC_USB_DIEPTXF1_INEPNTXFSTADDR_OFFSET    0x104
-#define GC_USB_DIEPTXF1_RESERVED11_LSB           0xc
-#define GC_USB_DIEPTXF1_RESERVED11_MASK          0x1000
-#define GC_USB_DIEPTXF1_RESERVED11_SIZE          0x1
-#define GC_USB_DIEPTXF1_RESERVED11_DEFAULT       0x1
-#define GC_USB_DIEPTXF1_RESERVED11_OFFSET        0x104
-#define GC_USB_DIEPTXF1_INEPNTXFDEP_LSB          0x10
-#define GC_USB_DIEPTXF1_INEPNTXFDEP_MASK         0x3f0000
-#define GC_USB_DIEPTXF1_INEPNTXFDEP_SIZE         0x6
-#define GC_USB_DIEPTXF1_INEPNTXFDEP_DEFAULT      0x0
-#define GC_USB_DIEPTXF1_INEPNTXFDEP_OFFSET       0x104
-#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_LSB       0x0
-#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_MASK      0x7ff
-#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_SIZE      0xb
-#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_DEFAULT   0x0
-#define GC_USB_DIEPTXF2_INEPNTXFSTADDR_OFFSET    0x108
-#define GC_USB_DIEPTXF2_INEPNTXFDEP_LSB          0x10
-#define GC_USB_DIEPTXF2_INEPNTXFDEP_MASK         0x3f0000
-#define GC_USB_DIEPTXF2_INEPNTXFDEP_SIZE         0x6
-#define GC_USB_DIEPTXF2_INEPNTXFDEP_DEFAULT      0x0
-#define GC_USB_DIEPTXF2_INEPNTXFDEP_OFFSET       0x108
-#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_LSB       0x0
-#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_MASK      0x7ff
-#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_SIZE      0xb
-#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_DEFAULT   0x0
-#define GC_USB_DIEPTXF3_INEPNTXFSTADDR_OFFSET    0x10c
-#define GC_USB_DIEPTXF3_INEPNTXFDEP_LSB          0x10
-#define GC_USB_DIEPTXF3_INEPNTXFDEP_MASK         0x3f0000
-#define GC_USB_DIEPTXF3_INEPNTXFDEP_SIZE         0x6
-#define GC_USB_DIEPTXF3_INEPNTXFDEP_DEFAULT      0x0
-#define GC_USB_DIEPTXF3_INEPNTXFDEP_OFFSET       0x10c
-#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_LSB       0x0
-#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_MASK      0x7ff
-#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_SIZE      0xb
-#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_DEFAULT   0x0
-#define GC_USB_DIEPTXF4_INEPNTXFSTADDR_OFFSET    0x110
-#define GC_USB_DIEPTXF4_INEPNTXFDEP_LSB          0x10
-#define GC_USB_DIEPTXF4_INEPNTXFDEP_MASK         0x3f0000
-#define GC_USB_DIEPTXF4_INEPNTXFDEP_SIZE         0x6
-#define GC_USB_DIEPTXF4_INEPNTXFDEP_DEFAULT      0x0
-#define GC_USB_DIEPTXF4_INEPNTXFDEP_OFFSET       0x110
-#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_LSB       0x0
-#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_MASK      0x7ff
-#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_SIZE      0xb
-#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_DEFAULT   0x0
-#define GC_USB_DIEPTXF5_INEPNTXFSTADDR_OFFSET    0x114
-#define GC_USB_DIEPTXF5_INEPNTXFDEP_LSB          0x10
-#define GC_USB_DIEPTXF5_INEPNTXFDEP_MASK         0x3f0000
-#define GC_USB_DIEPTXF5_INEPNTXFDEP_SIZE         0x6
-#define GC_USB_DIEPTXF5_INEPNTXFDEP_DEFAULT      0x0
-#define GC_USB_DIEPTXF5_INEPNTXFDEP_OFFSET       0x114
-#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_LSB       0x0
-#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_MASK      0x7ff
-#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_SIZE      0xb
-#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_DEFAULT   0x0
-#define GC_USB_DIEPTXF6_INEPNTXFSTADDR_OFFSET    0x118
-#define GC_USB_DIEPTXF6_INEPNTXFDEP_LSB          0x10
-#define GC_USB_DIEPTXF6_INEPNTXFDEP_MASK         0x3f0000
-#define GC_USB_DIEPTXF6_INEPNTXFDEP_SIZE         0x6
-#define GC_USB_DIEPTXF6_INEPNTXFDEP_DEFAULT      0x0
-#define GC_USB_DIEPTXF6_INEPNTXFDEP_OFFSET       0x118
-#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_LSB       0x0
-#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_MASK      0x7ff
-#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_SIZE      0xb
-#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_DEFAULT   0x0
-#define GC_USB_DIEPTXF7_INEPNTXFSTADDR_OFFSET    0x11c
-#define GC_USB_DIEPTXF7_INEPNTXFDEP_LSB          0x10
-#define GC_USB_DIEPTXF7_INEPNTXFDEP_MASK         0x3f0000
-#define GC_USB_DIEPTXF7_INEPNTXFDEP_SIZE         0x6
-#define GC_USB_DIEPTXF7_INEPNTXFDEP_DEFAULT      0x0
-#define GC_USB_DIEPTXF7_INEPNTXFDEP_OFFSET       0x11c
-#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_LSB       0x0
-#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_MASK      0x7ff
-#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_SIZE      0xb
-#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_DEFAULT   0x0
-#define GC_USB_DIEPTXF8_INEPNTXFSTADDR_OFFSET    0x120
-#define GC_USB_DIEPTXF8_INEPNTXFDEP_LSB          0x10
-#define GC_USB_DIEPTXF8_INEPNTXFDEP_MASK         0x3f0000
-#define GC_USB_DIEPTXF8_INEPNTXFDEP_SIZE         0x6
-#define GC_USB_DIEPTXF8_INEPNTXFDEP_DEFAULT      0x0
-#define GC_USB_DIEPTXF8_INEPNTXFDEP_OFFSET       0x120
-#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_LSB       0x0
-#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_MASK      0x7ff
-#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_SIZE      0xb
-#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_DEFAULT   0x0
-#define GC_USB_DIEPTXF9_INEPNTXFSTADDR_OFFSET    0x124
-#define GC_USB_DIEPTXF9_INEPNTXFDEP_LSB          0x10
-#define GC_USB_DIEPTXF9_INEPNTXFDEP_MASK         0x3f0000
-#define GC_USB_DIEPTXF9_INEPNTXFDEP_SIZE         0x6
-#define GC_USB_DIEPTXF9_INEPNTXFDEP_DEFAULT      0x0
-#define GC_USB_DIEPTXF9_INEPNTXFDEP_OFFSET       0x124
-#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_LSB      0x0
-#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_MASK     0x7ff
-#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_SIZE     0xb
-#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_DEFAULT  0x0
-#define GC_USB_DIEPTXF10_INEPNTXFSTADDR_OFFSET   0x128
-#define GC_USB_DIEPTXF10_INEPNTXFDEP_LSB         0x10
-#define GC_USB_DIEPTXF10_INEPNTXFDEP_MASK        0x3f0000
-#define GC_USB_DIEPTXF10_INEPNTXFDEP_SIZE        0x6
-#define GC_USB_DIEPTXF10_INEPNTXFDEP_DEFAULT     0x0
-#define GC_USB_DIEPTXF10_INEPNTXFDEP_OFFSET      0x128
-#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_LSB      0x0
-#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_MASK     0x7ff
-#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_SIZE     0xb
-#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_DEFAULT  0x0
-#define GC_USB_DIEPTXF11_INEPNTXFSTADDR_OFFSET   0x12c
-#define GC_USB_DIEPTXF11_INEPNTXFDEP_LSB         0x10
-#define GC_USB_DIEPTXF11_INEPNTXFDEP_MASK        0x3f0000
-#define GC_USB_DIEPTXF11_INEPNTXFDEP_SIZE        0x6
-#define GC_USB_DIEPTXF11_INEPNTXFDEP_DEFAULT     0x0
-#define GC_USB_DIEPTXF11_INEPNTXFDEP_OFFSET      0x12c
-#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_LSB      0x0
-#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_MASK     0x7ff
-#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_SIZE     0xb
-#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_DEFAULT  0x0
-#define GC_USB_DIEPTXF12_INEPNTXFSTADDR_OFFSET   0x130
-#define GC_USB_DIEPTXF12_INEPNTXFDEP_LSB         0x10
-#define GC_USB_DIEPTXF12_INEPNTXFDEP_MASK        0x3f0000
-#define GC_USB_DIEPTXF12_INEPNTXFDEP_SIZE        0x6
-#define GC_USB_DIEPTXF12_INEPNTXFDEP_DEFAULT     0x0
-#define GC_USB_DIEPTXF12_INEPNTXFDEP_OFFSET      0x130
-#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_LSB      0x0
-#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_MASK     0x7ff
-#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_SIZE     0xb
-#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_DEFAULT  0x0
-#define GC_USB_DIEPTXF13_INEPNTXFSTADDR_OFFSET   0x134
-#define GC_USB_DIEPTXF13_INEPNTXFDEP_LSB         0x10
-#define GC_USB_DIEPTXF13_INEPNTXFDEP_MASK        0x3f0000
-#define GC_USB_DIEPTXF13_INEPNTXFDEP_SIZE        0x6
-#define GC_USB_DIEPTXF13_INEPNTXFDEP_DEFAULT     0x0
-#define GC_USB_DIEPTXF13_INEPNTXFDEP_OFFSET      0x134
-#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_LSB      0x0
-#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_MASK     0x7ff
-#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_SIZE     0xb
-#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_DEFAULT  0x0
-#define GC_USB_DIEPTXF14_INEPNTXFSTADDR_OFFSET   0x138
-#define GC_USB_DIEPTXF14_INEPNTXFDEP_LSB         0x10
-#define GC_USB_DIEPTXF14_INEPNTXFDEP_MASK        0x3f0000
-#define GC_USB_DIEPTXF14_INEPNTXFDEP_SIZE        0x6
-#define GC_USB_DIEPTXF14_INEPNTXFDEP_DEFAULT     0x0
-#define GC_USB_DIEPTXF14_INEPNTXFDEP_OFFSET      0x138
-#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_LSB      0x0
-#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_MASK     0x7ff
-#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_SIZE     0xb
-#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_DEFAULT  0x0
-#define GC_USB_DIEPTXF15_INEPNTXFSTADDR_OFFSET   0x13c
-#define GC_USB_DIEPTXF15_INEPNTXFDEP_LSB         0x10
-#define GC_USB_DIEPTXF15_INEPNTXFDEP_MASK        0x3f0000
-#define GC_USB_DIEPTXF15_INEPNTXFDEP_SIZE        0x6
-#define GC_USB_DIEPTXF15_INEPNTXFDEP_DEFAULT     0x0
-#define GC_USB_DIEPTXF15_INEPNTXFDEP_OFFSET      0x13c
-#define GC_USB_DCFG_DEVSPD_LSB                   0x0
-#define GC_USB_DCFG_DEVSPD_MASK                  0x3
-#define GC_USB_DCFG_DEVSPD_SIZE                  0x2
-#define GC_USB_DCFG_DEVSPD_DEFAULT               0x0
-#define GC_USB_DCFG_DEVSPD_OFFSET                0x800
-#define GC_USB_DCFG_NZSTSOUTHSHK_LSB             0x2
-#define GC_USB_DCFG_NZSTSOUTHSHK_MASK            0x4
-#define GC_USB_DCFG_NZSTSOUTHSHK_SIZE            0x1
-#define GC_USB_DCFG_NZSTSOUTHSHK_DEFAULT         0x0
-#define GC_USB_DCFG_NZSTSOUTHSHK_OFFSET          0x800
-#define GC_USB_DCFG_ENA32KHZSUSP_LSB             0x3
-#define GC_USB_DCFG_ENA32KHZSUSP_MASK            0x8
-#define GC_USB_DCFG_ENA32KHZSUSP_SIZE            0x1
-#define GC_USB_DCFG_ENA32KHZSUSP_DEFAULT         0x0
-#define GC_USB_DCFG_ENA32KHZSUSP_OFFSET          0x800
-#define GC_USB_DCFG_DEVADDR_LSB                  0x4
-#define GC_USB_DCFG_DEVADDR_MASK                 0x7f0
-#define GC_USB_DCFG_DEVADDR_SIZE                 0x7
-#define GC_USB_DCFG_DEVADDR_DEFAULT              0x0
-#define GC_USB_DCFG_DEVADDR_OFFSET               0x800
-#define GC_USB_DCFG_PERFRINT_LSB                 0xb
-#define GC_USB_DCFG_PERFRINT_MASK                0x1800
-#define GC_USB_DCFG_PERFRINT_SIZE                0x2
-#define GC_USB_DCFG_PERFRINT_DEFAULT             0x0
-#define GC_USB_DCFG_PERFRINT_OFFSET              0x800
-#define GC_USB_DCFG_ENDEVOUTNAK_LSB              0xd
-#define GC_USB_DCFG_ENDEVOUTNAK_MASK             0x2000
-#define GC_USB_DCFG_ENDEVOUTNAK_SIZE             0x1
-#define GC_USB_DCFG_ENDEVOUTNAK_DEFAULT          0x0
-#define GC_USB_DCFG_ENDEVOUTNAK_OFFSET           0x800
-#define GC_USB_DCFG_XCVRDLY_LSB                  0xe
-#define GC_USB_DCFG_XCVRDLY_MASK                 0x4000
-#define GC_USB_DCFG_XCVRDLY_SIZE                 0x1
-#define GC_USB_DCFG_XCVRDLY_DEFAULT              0x0
-#define GC_USB_DCFG_XCVRDLY_OFFSET               0x800
-#define GC_USB_DCFG_ERRATICINTMSK_LSB            0xf
-#define GC_USB_DCFG_ERRATICINTMSK_MASK           0x8000
-#define GC_USB_DCFG_ERRATICINTMSK_SIZE           0x1
-#define GC_USB_DCFG_ERRATICINTMSK_DEFAULT        0x0
-#define GC_USB_DCFG_ERRATICINTMSK_OFFSET         0x800
-#define GC_USB_DCFG_DESCDMA_LSB                  0x17
-#define GC_USB_DCFG_DESCDMA_MASK                 0x800000
-#define GC_USB_DCFG_DESCDMA_SIZE                 0x1
-#define GC_USB_DCFG_DESCDMA_DEFAULT              0x0
-#define GC_USB_DCFG_DESCDMA_OFFSET               0x800
-#define GC_USB_DCFG_PERSCHINTVL_LSB              0x18
-#define GC_USB_DCFG_PERSCHINTVL_MASK             0x3000000
-#define GC_USB_DCFG_PERSCHINTVL_SIZE             0x2
-#define GC_USB_DCFG_PERSCHINTVL_DEFAULT          0x0
-#define GC_USB_DCFG_PERSCHINTVL_OFFSET           0x800
-#define GC_USB_DCFG_RESVALID_LSB                 0x1a
-#define GC_USB_DCFG_RESVALID_MASK                0xfc000000
-#define GC_USB_DCFG_RESVALID_SIZE                0x6
-#define GC_USB_DCFG_RESVALID_DEFAULT             0x2
-#define GC_USB_DCFG_RESVALID_OFFSET              0x800
-#define GC_USB_DCTL_RMTWKUPSIG_LSB               0x0
-#define GC_USB_DCTL_RMTWKUPSIG_MASK              0x1
-#define GC_USB_DCTL_RMTWKUPSIG_SIZE              0x1
-#define GC_USB_DCTL_RMTWKUPSIG_DEFAULT           0x0
-#define GC_USB_DCTL_RMTWKUPSIG_OFFSET            0x804
-#define GC_USB_DCTL_SFTDISCON_LSB                0x1
-#define GC_USB_DCTL_SFTDISCON_MASK               0x2
-#define GC_USB_DCTL_SFTDISCON_SIZE               0x1
-#define GC_USB_DCTL_SFTDISCON_DEFAULT            0x0
-#define GC_USB_DCTL_SFTDISCON_OFFSET             0x804
-#define GC_USB_DCTL_GNPINNAKSTS_LSB              0x2
-#define GC_USB_DCTL_GNPINNAKSTS_MASK             0x4
-#define GC_USB_DCTL_GNPINNAKSTS_SIZE             0x1
-#define GC_USB_DCTL_GNPINNAKSTS_DEFAULT          0x0
-#define GC_USB_DCTL_GNPINNAKSTS_OFFSET           0x804
-#define GC_USB_DCTL_GOUTNAKSTS_LSB               0x3
-#define GC_USB_DCTL_GOUTNAKSTS_MASK              0x8
-#define GC_USB_DCTL_GOUTNAKSTS_SIZE              0x1
-#define GC_USB_DCTL_GOUTNAKSTS_DEFAULT           0x0
-#define GC_USB_DCTL_GOUTNAKSTS_OFFSET            0x804
-#define GC_USB_DCTL_TSTCTL_LSB                   0x4
-#define GC_USB_DCTL_TSTCTL_MASK                  0x70
-#define GC_USB_DCTL_TSTCTL_SIZE                  0x3
-#define GC_USB_DCTL_TSTCTL_DEFAULT               0x0
-#define GC_USB_DCTL_TSTCTL_OFFSET                0x804
-#define GC_USB_DCTL_SGNPINNAK_LSB                0x7
-#define GC_USB_DCTL_SGNPINNAK_MASK               0x80
-#define GC_USB_DCTL_SGNPINNAK_SIZE               0x1
-#define GC_USB_DCTL_SGNPINNAK_DEFAULT            0x0
-#define GC_USB_DCTL_SGNPINNAK_OFFSET             0x804
-#define GC_USB_DCTL_CGNPINNAK_LSB                0x8
-#define GC_USB_DCTL_CGNPINNAK_MASK               0x100
-#define GC_USB_DCTL_CGNPINNAK_SIZE               0x1
-#define GC_USB_DCTL_CGNPINNAK_DEFAULT            0x0
-#define GC_USB_DCTL_CGNPINNAK_OFFSET             0x804
-#define GC_USB_DCTL_SGOUTNAK_LSB                 0x9
-#define GC_USB_DCTL_SGOUTNAK_MASK                0x200
-#define GC_USB_DCTL_SGOUTNAK_SIZE                0x1
-#define GC_USB_DCTL_SGOUTNAK_DEFAULT             0x0
-#define GC_USB_DCTL_SGOUTNAK_OFFSET              0x804
-#define GC_USB_DCTL_CGOUTNAK_LSB                 0xa
-#define GC_USB_DCTL_CGOUTNAK_MASK                0x400
-#define GC_USB_DCTL_CGOUTNAK_SIZE                0x1
-#define GC_USB_DCTL_CGOUTNAK_DEFAULT             0x0
-#define GC_USB_DCTL_CGOUTNAK_OFFSET              0x804
-#define GC_USB_DCTL_PWRONPRGDONE_LSB             0xb
-#define GC_USB_DCTL_PWRONPRGDONE_MASK            0x800
-#define GC_USB_DCTL_PWRONPRGDONE_SIZE            0x1
-#define GC_USB_DCTL_PWRONPRGDONE_DEFAULT         0x0
-#define GC_USB_DCTL_PWRONPRGDONE_OFFSET          0x804
-#define GC_USB_DCTL_GMC_LSB                      0xd
-#define GC_USB_DCTL_GMC_MASK                     0x6000
-#define GC_USB_DCTL_GMC_SIZE                     0x2
-#define GC_USB_DCTL_GMC_DEFAULT                  0x0
-#define GC_USB_DCTL_GMC_OFFSET                   0x804
-#define GC_USB_DCTL_IGNRFRMNUM_LSB               0xf
-#define GC_USB_DCTL_IGNRFRMNUM_MASK              0x8000
-#define GC_USB_DCTL_IGNRFRMNUM_SIZE              0x1
-#define GC_USB_DCTL_IGNRFRMNUM_DEFAULT           0x0
-#define GC_USB_DCTL_IGNRFRMNUM_OFFSET            0x804
-#define GC_USB_DCTL_NAKONBBLE_LSB                0x10
-#define GC_USB_DCTL_NAKONBBLE_MASK               0x10000
-#define GC_USB_DCTL_NAKONBBLE_SIZE               0x1
-#define GC_USB_DCTL_NAKONBBLE_DEFAULT            0x0
-#define GC_USB_DCTL_NAKONBBLE_OFFSET             0x804
-#define GC_USB_DCTL_ENCONTONBNA_LSB              0x11
-#define GC_USB_DCTL_ENCONTONBNA_MASK             0x20000
-#define GC_USB_DCTL_ENCONTONBNA_SIZE             0x1
-#define GC_USB_DCTL_ENCONTONBNA_DEFAULT          0x0
-#define GC_USB_DCTL_ENCONTONBNA_OFFSET           0x804
-#define GC_USB_DSTS_SUSPSTS_LSB                  0x0
-#define GC_USB_DSTS_SUSPSTS_MASK                 0x1
-#define GC_USB_DSTS_SUSPSTS_SIZE                 0x1
-#define GC_USB_DSTS_SUSPSTS_DEFAULT              0x0
-#define GC_USB_DSTS_SUSPSTS_OFFSET               0x808
-#define GC_USB_DSTS_ENUMSPD_LSB                  0x1
-#define GC_USB_DSTS_ENUMSPD_MASK                 0x6
-#define GC_USB_DSTS_ENUMSPD_SIZE                 0x2
-#define GC_USB_DSTS_ENUMSPD_DEFAULT              0x0
-#define GC_USB_DSTS_ENUMSPD_OFFSET               0x808
-#define GC_USB_DSTS_ERRTICERR_LSB                0x3
-#define GC_USB_DSTS_ERRTICERR_MASK               0x8
-#define GC_USB_DSTS_ERRTICERR_SIZE               0x1
-#define GC_USB_DSTS_ERRTICERR_DEFAULT            0x0
-#define GC_USB_DSTS_ERRTICERR_OFFSET             0x808
-#define GC_USB_DSTS_SOFFN_LSB                    0x8
-#define GC_USB_DSTS_SOFFN_MASK                   0x3fff00
-#define GC_USB_DSTS_SOFFN_SIZE                   0xe
-#define GC_USB_DSTS_SOFFN_DEFAULT                0x0
-#define GC_USB_DSTS_SOFFN_OFFSET                 0x808
-#define GC_USB_DSTS_DEVLNSTS_LSB                 0x16
-#define GC_USB_DSTS_DEVLNSTS_MASK                0xc00000
-#define GC_USB_DSTS_DEVLNSTS_SIZE                0x2
-#define GC_USB_DSTS_DEVLNSTS_DEFAULT             0x0
-#define GC_USB_DSTS_DEVLNSTS_OFFSET              0x808
-#define GC_USB_DIEPMSK_XFERCOMPLMSK_LSB          0x0
-#define GC_USB_DIEPMSK_XFERCOMPLMSK_MASK         0x1
-#define GC_USB_DIEPMSK_XFERCOMPLMSK_SIZE         0x1
-#define GC_USB_DIEPMSK_XFERCOMPLMSK_DEFAULT      0x0
-#define GC_USB_DIEPMSK_XFERCOMPLMSK_OFFSET       0x810
-#define GC_USB_DIEPMSK_EPDISBLDMSK_LSB           0x1
-#define GC_USB_DIEPMSK_EPDISBLDMSK_MASK          0x2
-#define GC_USB_DIEPMSK_EPDISBLDMSK_SIZE          0x1
-#define GC_USB_DIEPMSK_EPDISBLDMSK_DEFAULT       0x0
-#define GC_USB_DIEPMSK_EPDISBLDMSK_OFFSET        0x810
-#define GC_USB_DIEPMSK_AHBERRMSK_LSB             0x2
-#define GC_USB_DIEPMSK_AHBERRMSK_MASK            0x4
-#define GC_USB_DIEPMSK_AHBERRMSK_SIZE            0x1
-#define GC_USB_DIEPMSK_AHBERRMSK_DEFAULT         0x0
-#define GC_USB_DIEPMSK_AHBERRMSK_OFFSET          0x810
-#define GC_USB_DIEPMSK_TIMEOUTMSK_LSB            0x3
-#define GC_USB_DIEPMSK_TIMEOUTMSK_MASK           0x8
-#define GC_USB_DIEPMSK_TIMEOUTMSK_SIZE           0x1
-#define GC_USB_DIEPMSK_TIMEOUTMSK_DEFAULT        0x0
-#define GC_USB_DIEPMSK_TIMEOUTMSK_OFFSET         0x810
-#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_LSB        0x4
-#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_MASK       0x10
-#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_SIZE       0x1
-#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_DEFAULT    0x0
-#define GC_USB_DIEPMSK_INTKNTXFEMPMSK_OFFSET     0x810
-#define GC_USB_DIEPMSK_INTKNEPMISMSK_LSB         0x5
-#define GC_USB_DIEPMSK_INTKNEPMISMSK_MASK        0x20
-#define GC_USB_DIEPMSK_INTKNEPMISMSK_SIZE        0x1
-#define GC_USB_DIEPMSK_INTKNEPMISMSK_DEFAULT     0x0
-#define GC_USB_DIEPMSK_INTKNEPMISMSK_OFFSET      0x810
-#define GC_USB_DIEPMSK_INEPNAKEFFMSK_LSB         0x6
-#define GC_USB_DIEPMSK_INEPNAKEFFMSK_MASK        0x40
-#define GC_USB_DIEPMSK_INEPNAKEFFMSK_SIZE        0x1
-#define GC_USB_DIEPMSK_INEPNAKEFFMSK_DEFAULT     0x0
-#define GC_USB_DIEPMSK_INEPNAKEFFMSK_OFFSET      0x810
-#define GC_USB_DIEPMSK_RESERVED7_LSB             0x7
-#define GC_USB_DIEPMSK_RESERVED7_MASK            0x80
-#define GC_USB_DIEPMSK_RESERVED7_SIZE            0x1
-#define GC_USB_DIEPMSK_RESERVED7_DEFAULT         0x1
-#define GC_USB_DIEPMSK_RESERVED7_OFFSET          0x810
-#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_LSB        0x8
-#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_MASK       0x100
-#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_SIZE       0x1
-#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_DEFAULT    0x0
-#define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_OFFSET     0x810
-#define GC_USB_DIEPMSK_BNAININTRMSK_LSB          0x9
-#define GC_USB_DIEPMSK_BNAININTRMSK_MASK         0x200
-#define GC_USB_DIEPMSK_BNAININTRMSK_SIZE         0x1
-#define GC_USB_DIEPMSK_BNAININTRMSK_DEFAULT      0x0
-#define GC_USB_DIEPMSK_BNAININTRMSK_OFFSET       0x810
-#define GC_USB_DIEPMSK_NAKMSK_LSB                0xd
-#define GC_USB_DIEPMSK_NAKMSK_MASK               0x2000
-#define GC_USB_DIEPMSK_NAKMSK_SIZE               0x1
-#define GC_USB_DIEPMSK_NAKMSK_DEFAULT            0x0
-#define GC_USB_DIEPMSK_NAKMSK_OFFSET             0x810
-#define GC_USB_DOEPMSK_XFERCOMPLMSK_LSB          0x0
-#define GC_USB_DOEPMSK_XFERCOMPLMSK_MASK         0x1
-#define GC_USB_DOEPMSK_XFERCOMPLMSK_SIZE         0x1
-#define GC_USB_DOEPMSK_XFERCOMPLMSK_DEFAULT      0x0
-#define GC_USB_DOEPMSK_XFERCOMPLMSK_OFFSET       0x814
-#define GC_USB_DOEPMSK_EPDISBLDMSK_LSB           0x1
-#define GC_USB_DOEPMSK_EPDISBLDMSK_MASK          0x2
-#define GC_USB_DOEPMSK_EPDISBLDMSK_SIZE          0x1
-#define GC_USB_DOEPMSK_EPDISBLDMSK_DEFAULT       0x0
-#define GC_USB_DOEPMSK_EPDISBLDMSK_OFFSET        0x814
-#define GC_USB_DOEPMSK_AHBERRMSK_LSB             0x2
-#define GC_USB_DOEPMSK_AHBERRMSK_MASK            0x4
-#define GC_USB_DOEPMSK_AHBERRMSK_SIZE            0x1
-#define GC_USB_DOEPMSK_AHBERRMSK_DEFAULT         0x0
-#define GC_USB_DOEPMSK_AHBERRMSK_OFFSET          0x814
-#define GC_USB_DOEPMSK_SETUPMSK_LSB              0x3
-#define GC_USB_DOEPMSK_SETUPMSK_MASK             0x8
-#define GC_USB_DOEPMSK_SETUPMSK_SIZE             0x1
-#define GC_USB_DOEPMSK_SETUPMSK_DEFAULT          0x0
-#define GC_USB_DOEPMSK_SETUPMSK_OFFSET           0x814
-#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_LSB        0x4
-#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_MASK       0x10
-#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_SIZE       0x1
-#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_DEFAULT    0x0
-#define GC_USB_DOEPMSK_OUTTKNEPDISMSK_OFFSET     0x814
-#define GC_USB_DOEPMSK_STSPHSERCVDMSK_LSB        0x5
-#define GC_USB_DOEPMSK_STSPHSERCVDMSK_MASK       0x20
-#define GC_USB_DOEPMSK_STSPHSERCVDMSK_SIZE       0x1
-#define GC_USB_DOEPMSK_STSPHSERCVDMSK_DEFAULT    0x0
-#define GC_USB_DOEPMSK_STSPHSERCVDMSK_OFFSET     0x814
-#define GC_USB_DOEPMSK_BACK2BACKSETUP_LSB        0x6
-#define GC_USB_DOEPMSK_BACK2BACKSETUP_MASK       0x40
-#define GC_USB_DOEPMSK_BACK2BACKSETUP_SIZE       0x1
-#define GC_USB_DOEPMSK_BACK2BACKSETUP_DEFAULT    0x0
-#define GC_USB_DOEPMSK_BACK2BACKSETUP_OFFSET     0x814
-#define GC_USB_DOEPMSK_OUTPKTERRMSK_LSB          0x8
-#define GC_USB_DOEPMSK_OUTPKTERRMSK_MASK         0x100
-#define GC_USB_DOEPMSK_OUTPKTERRMSK_SIZE         0x1
-#define GC_USB_DOEPMSK_OUTPKTERRMSK_DEFAULT      0x0
-#define GC_USB_DOEPMSK_OUTPKTERRMSK_OFFSET       0x814
-#define GC_USB_DOEPMSK_BNAOUTINTRMSK_LSB         0x9
-#define GC_USB_DOEPMSK_BNAOUTINTRMSK_MASK        0x200
-#define GC_USB_DOEPMSK_BNAOUTINTRMSK_SIZE        0x1
-#define GC_USB_DOEPMSK_BNAOUTINTRMSK_DEFAULT     0x0
-#define GC_USB_DOEPMSK_BNAOUTINTRMSK_OFFSET      0x814
-#define GC_USB_DOEPMSK_BBLEERRMSK_LSB            0xc
-#define GC_USB_DOEPMSK_BBLEERRMSK_MASK           0x1000
-#define GC_USB_DOEPMSK_BBLEERRMSK_SIZE           0x1
-#define GC_USB_DOEPMSK_BBLEERRMSK_DEFAULT        0x0
-#define GC_USB_DOEPMSK_BBLEERRMSK_OFFSET         0x814
-#define GC_USB_DOEPMSK_NAKMSK_LSB                0xd
-#define GC_USB_DOEPMSK_NAKMSK_MASK               0x2000
-#define GC_USB_DOEPMSK_NAKMSK_SIZE               0x1
-#define GC_USB_DOEPMSK_NAKMSK_DEFAULT            0x0
-#define GC_USB_DOEPMSK_NAKMSK_OFFSET             0x814
-#define GC_USB_DOEPMSK_NYETMSK_LSB               0xe
-#define GC_USB_DOEPMSK_NYETMSK_MASK              0x4000
-#define GC_USB_DOEPMSK_NYETMSK_SIZE              0x1
-#define GC_USB_DOEPMSK_NYETMSK_DEFAULT           0x0
-#define GC_USB_DOEPMSK_NYETMSK_OFFSET            0x814
-#define GC_USB_DAINT_INEPINT0_LSB                0x0
-#define GC_USB_DAINT_INEPINT0_MASK               0x1
-#define GC_USB_DAINT_INEPINT0_SIZE               0x1
-#define GC_USB_DAINT_INEPINT0_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT0_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT1_LSB                0x1
-#define GC_USB_DAINT_INEPINT1_MASK               0x2
-#define GC_USB_DAINT_INEPINT1_SIZE               0x1
-#define GC_USB_DAINT_INEPINT1_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT1_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT2_LSB                0x2
-#define GC_USB_DAINT_INEPINT2_MASK               0x4
-#define GC_USB_DAINT_INEPINT2_SIZE               0x1
-#define GC_USB_DAINT_INEPINT2_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT2_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT3_LSB                0x3
-#define GC_USB_DAINT_INEPINT3_MASK               0x8
-#define GC_USB_DAINT_INEPINT3_SIZE               0x1
-#define GC_USB_DAINT_INEPINT3_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT3_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT4_LSB                0x4
-#define GC_USB_DAINT_INEPINT4_MASK               0x10
-#define GC_USB_DAINT_INEPINT4_SIZE               0x1
-#define GC_USB_DAINT_INEPINT4_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT4_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT5_LSB                0x5
-#define GC_USB_DAINT_INEPINT5_MASK               0x20
-#define GC_USB_DAINT_INEPINT5_SIZE               0x1
-#define GC_USB_DAINT_INEPINT5_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT5_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT6_LSB                0x6
-#define GC_USB_DAINT_INEPINT6_MASK               0x40
-#define GC_USB_DAINT_INEPINT6_SIZE               0x1
-#define GC_USB_DAINT_INEPINT6_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT6_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT7_LSB                0x7
-#define GC_USB_DAINT_INEPINT7_MASK               0x80
-#define GC_USB_DAINT_INEPINT7_SIZE               0x1
-#define GC_USB_DAINT_INEPINT7_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT7_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT8_LSB                0x8
-#define GC_USB_DAINT_INEPINT8_MASK               0x100
-#define GC_USB_DAINT_INEPINT8_SIZE               0x1
-#define GC_USB_DAINT_INEPINT8_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT8_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT9_LSB                0x9
-#define GC_USB_DAINT_INEPINT9_MASK               0x200
-#define GC_USB_DAINT_INEPINT9_SIZE               0x1
-#define GC_USB_DAINT_INEPINT9_DEFAULT            0x0
-#define GC_USB_DAINT_INEPINT9_OFFSET             0x818
-#define GC_USB_DAINT_INEPINT10_LSB               0xa
-#define GC_USB_DAINT_INEPINT10_MASK              0x400
-#define GC_USB_DAINT_INEPINT10_SIZE              0x1
-#define GC_USB_DAINT_INEPINT10_DEFAULT           0x0
-#define GC_USB_DAINT_INEPINT10_OFFSET            0x818
-#define GC_USB_DAINT_INEPINT11_LSB               0xb
-#define GC_USB_DAINT_INEPINT11_MASK              0x800
-#define GC_USB_DAINT_INEPINT11_SIZE              0x1
-#define GC_USB_DAINT_INEPINT11_DEFAULT           0x0
-#define GC_USB_DAINT_INEPINT11_OFFSET            0x818
-#define GC_USB_DAINT_INEPINT12_LSB               0xc
-#define GC_USB_DAINT_INEPINT12_MASK              0x1000
-#define GC_USB_DAINT_INEPINT12_SIZE              0x1
-#define GC_USB_DAINT_INEPINT12_DEFAULT           0x0
-#define GC_USB_DAINT_INEPINT12_OFFSET            0x818
-#define GC_USB_DAINT_INEPINT13_LSB               0xd
-#define GC_USB_DAINT_INEPINT13_MASK              0x2000
-#define GC_USB_DAINT_INEPINT13_SIZE              0x1
-#define GC_USB_DAINT_INEPINT13_DEFAULT           0x0
-#define GC_USB_DAINT_INEPINT13_OFFSET            0x818
-#define GC_USB_DAINT_INEPINT14_LSB               0xe
-#define GC_USB_DAINT_INEPINT14_MASK              0x4000
-#define GC_USB_DAINT_INEPINT14_SIZE              0x1
-#define GC_USB_DAINT_INEPINT14_DEFAULT           0x0
-#define GC_USB_DAINT_INEPINT14_OFFSET            0x818
-#define GC_USB_DAINT_INEPINT15_LSB               0xf
-#define GC_USB_DAINT_INEPINT15_MASK              0x8000
-#define GC_USB_DAINT_INEPINT15_SIZE              0x1
-#define GC_USB_DAINT_INEPINT15_DEFAULT           0x0
-#define GC_USB_DAINT_INEPINT15_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT0_LSB               0x10
-#define GC_USB_DAINT_OUTEPINT0_MASK              0x10000
-#define GC_USB_DAINT_OUTEPINT0_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT0_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT0_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT1_LSB               0x11
-#define GC_USB_DAINT_OUTEPINT1_MASK              0x20000
-#define GC_USB_DAINT_OUTEPINT1_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT1_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT1_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT2_LSB               0x12
-#define GC_USB_DAINT_OUTEPINT2_MASK              0x40000
-#define GC_USB_DAINT_OUTEPINT2_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT2_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT2_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT3_LSB               0x13
-#define GC_USB_DAINT_OUTEPINT3_MASK              0x80000
-#define GC_USB_DAINT_OUTEPINT3_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT3_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT3_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT4_LSB               0x14
-#define GC_USB_DAINT_OUTEPINT4_MASK              0x100000
-#define GC_USB_DAINT_OUTEPINT4_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT4_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT4_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT5_LSB               0x15
-#define GC_USB_DAINT_OUTEPINT5_MASK              0x200000
-#define GC_USB_DAINT_OUTEPINT5_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT5_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT5_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT6_LSB               0x16
-#define GC_USB_DAINT_OUTEPINT6_MASK              0x400000
-#define GC_USB_DAINT_OUTEPINT6_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT6_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT6_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT7_LSB               0x17
-#define GC_USB_DAINT_OUTEPINT7_MASK              0x800000
-#define GC_USB_DAINT_OUTEPINT7_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT7_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT7_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT8_LSB               0x18
-#define GC_USB_DAINT_OUTEPINT8_MASK              0x1000000
-#define GC_USB_DAINT_OUTEPINT8_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT8_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT8_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT9_LSB               0x19
-#define GC_USB_DAINT_OUTEPINT9_MASK              0x2000000
-#define GC_USB_DAINT_OUTEPINT9_SIZE              0x1
-#define GC_USB_DAINT_OUTEPINT9_DEFAULT           0x0
-#define GC_USB_DAINT_OUTEPINT9_OFFSET            0x818
-#define GC_USB_DAINT_OUTEPINT10_LSB              0x1a
-#define GC_USB_DAINT_OUTEPINT10_MASK             0x4000000
-#define GC_USB_DAINT_OUTEPINT10_SIZE             0x1
-#define GC_USB_DAINT_OUTEPINT10_DEFAULT          0x0
-#define GC_USB_DAINT_OUTEPINT10_OFFSET           0x818
-#define GC_USB_DAINT_OUTEPINT11_LSB              0x1b
-#define GC_USB_DAINT_OUTEPINT11_MASK             0x8000000
-#define GC_USB_DAINT_OUTEPINT11_SIZE             0x1
-#define GC_USB_DAINT_OUTEPINT11_DEFAULT          0x0
-#define GC_USB_DAINT_OUTEPINT11_OFFSET           0x818
-#define GC_USB_DAINT_OUTEPINT12_LSB              0x1c
-#define GC_USB_DAINT_OUTEPINT12_MASK             0x10000000
-#define GC_USB_DAINT_OUTEPINT12_SIZE             0x1
-#define GC_USB_DAINT_OUTEPINT12_DEFAULT          0x0
-#define GC_USB_DAINT_OUTEPINT12_OFFSET           0x818
-#define GC_USB_DAINT_OUTEPINT13_LSB              0x1d
-#define GC_USB_DAINT_OUTEPINT13_MASK             0x20000000
-#define GC_USB_DAINT_OUTEPINT13_SIZE             0x1
-#define GC_USB_DAINT_OUTEPINT13_DEFAULT          0x0
-#define GC_USB_DAINT_OUTEPINT13_OFFSET           0x818
-#define GC_USB_DAINT_OUTEPINT14_LSB              0x1e
-#define GC_USB_DAINT_OUTEPINT14_MASK             0x40000000
-#define GC_USB_DAINT_OUTEPINT14_SIZE             0x1
-#define GC_USB_DAINT_OUTEPINT14_DEFAULT          0x0
-#define GC_USB_DAINT_OUTEPINT14_OFFSET           0x818
-#define GC_USB_DAINT_OUTEPINT15_LSB              0x1f
-#define GC_USB_DAINT_OUTEPINT15_MASK             0x80000000
-#define GC_USB_DAINT_OUTEPINT15_SIZE             0x1
-#define GC_USB_DAINT_OUTEPINT15_DEFAULT          0x0
-#define GC_USB_DAINT_OUTEPINT15_OFFSET           0x818
-#define GC_USB_DAINTMSK_INEPMSK0_LSB             0x0
-#define GC_USB_DAINTMSK_INEPMSK0_MASK            0x1
-#define GC_USB_DAINTMSK_INEPMSK0_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK0_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK0_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK1_LSB             0x1
-#define GC_USB_DAINTMSK_INEPMSK1_MASK            0x2
-#define GC_USB_DAINTMSK_INEPMSK1_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK1_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK1_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK2_LSB             0x2
-#define GC_USB_DAINTMSK_INEPMSK2_MASK            0x4
-#define GC_USB_DAINTMSK_INEPMSK2_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK2_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK2_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK3_LSB             0x3
-#define GC_USB_DAINTMSK_INEPMSK3_MASK            0x8
-#define GC_USB_DAINTMSK_INEPMSK3_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK3_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK3_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK4_LSB             0x4
-#define GC_USB_DAINTMSK_INEPMSK4_MASK            0x10
-#define GC_USB_DAINTMSK_INEPMSK4_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK4_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK4_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK5_LSB             0x5
-#define GC_USB_DAINTMSK_INEPMSK5_MASK            0x20
-#define GC_USB_DAINTMSK_INEPMSK5_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK5_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK5_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK6_LSB             0x6
-#define GC_USB_DAINTMSK_INEPMSK6_MASK            0x40
-#define GC_USB_DAINTMSK_INEPMSK6_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK6_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK6_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK7_LSB             0x7
-#define GC_USB_DAINTMSK_INEPMSK7_MASK            0x80
-#define GC_USB_DAINTMSK_INEPMSK7_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK7_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK7_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK8_LSB             0x8
-#define GC_USB_DAINTMSK_INEPMSK8_MASK            0x100
-#define GC_USB_DAINTMSK_INEPMSK8_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK8_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK8_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK9_LSB             0x9
-#define GC_USB_DAINTMSK_INEPMSK9_MASK            0x200
-#define GC_USB_DAINTMSK_INEPMSK9_SIZE            0x1
-#define GC_USB_DAINTMSK_INEPMSK9_DEFAULT         0x0
-#define GC_USB_DAINTMSK_INEPMSK9_OFFSET          0x81c
-#define GC_USB_DAINTMSK_INEPMSK10_LSB            0xa
-#define GC_USB_DAINTMSK_INEPMSK10_MASK           0x400
-#define GC_USB_DAINTMSK_INEPMSK10_SIZE           0x1
-#define GC_USB_DAINTMSK_INEPMSK10_DEFAULT        0x0
-#define GC_USB_DAINTMSK_INEPMSK10_OFFSET         0x81c
-#define GC_USB_DAINTMSK_INEPMSK11_LSB            0xb
-#define GC_USB_DAINTMSK_INEPMSK11_MASK           0x800
-#define GC_USB_DAINTMSK_INEPMSK11_SIZE           0x1
-#define GC_USB_DAINTMSK_INEPMSK11_DEFAULT        0x0
-#define GC_USB_DAINTMSK_INEPMSK11_OFFSET         0x81c
-#define GC_USB_DAINTMSK_INEPMSK12_LSB            0xc
-#define GC_USB_DAINTMSK_INEPMSK12_MASK           0x1000
-#define GC_USB_DAINTMSK_INEPMSK12_SIZE           0x1
-#define GC_USB_DAINTMSK_INEPMSK12_DEFAULT        0x0
-#define GC_USB_DAINTMSK_INEPMSK12_OFFSET         0x81c
-#define GC_USB_DAINTMSK_INEPMSK13_LSB            0xd
-#define GC_USB_DAINTMSK_INEPMSK13_MASK           0x2000
-#define GC_USB_DAINTMSK_INEPMSK13_SIZE           0x1
-#define GC_USB_DAINTMSK_INEPMSK13_DEFAULT        0x0
-#define GC_USB_DAINTMSK_INEPMSK13_OFFSET         0x81c
-#define GC_USB_DAINTMSK_INEPMSK14_LSB            0xe
-#define GC_USB_DAINTMSK_INEPMSK14_MASK           0x4000
-#define GC_USB_DAINTMSK_INEPMSK14_SIZE           0x1
-#define GC_USB_DAINTMSK_INEPMSK14_DEFAULT        0x0
-#define GC_USB_DAINTMSK_INEPMSK14_OFFSET         0x81c
-#define GC_USB_DAINTMSK_INEPMSK15_LSB            0xf
-#define GC_USB_DAINTMSK_INEPMSK15_MASK           0x8000
-#define GC_USB_DAINTMSK_INEPMSK15_SIZE           0x1
-#define GC_USB_DAINTMSK_INEPMSK15_DEFAULT        0x0
-#define GC_USB_DAINTMSK_INEPMSK15_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK0_LSB            0x10
-#define GC_USB_DAINTMSK_OUTEPMSK0_MASK           0x10000
-#define GC_USB_DAINTMSK_OUTEPMSK0_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK0_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK0_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK1_LSB            0x11
-#define GC_USB_DAINTMSK_OUTEPMSK1_MASK           0x20000
-#define GC_USB_DAINTMSK_OUTEPMSK1_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK1_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK1_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK2_LSB            0x12
-#define GC_USB_DAINTMSK_OUTEPMSK2_MASK           0x40000
-#define GC_USB_DAINTMSK_OUTEPMSK2_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK2_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK2_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK3_LSB            0x13
-#define GC_USB_DAINTMSK_OUTEPMSK3_MASK           0x80000
-#define GC_USB_DAINTMSK_OUTEPMSK3_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK3_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK3_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK4_LSB            0x14
-#define GC_USB_DAINTMSK_OUTEPMSK4_MASK           0x100000
-#define GC_USB_DAINTMSK_OUTEPMSK4_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK4_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK4_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK5_LSB            0x15
-#define GC_USB_DAINTMSK_OUTEPMSK5_MASK           0x200000
-#define GC_USB_DAINTMSK_OUTEPMSK5_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK5_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK5_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK6_LSB            0x16
-#define GC_USB_DAINTMSK_OUTEPMSK6_MASK           0x400000
-#define GC_USB_DAINTMSK_OUTEPMSK6_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK6_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK6_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK7_LSB            0x17
-#define GC_USB_DAINTMSK_OUTEPMSK7_MASK           0x800000
-#define GC_USB_DAINTMSK_OUTEPMSK7_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK7_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK7_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK8_LSB            0x18
-#define GC_USB_DAINTMSK_OUTEPMSK8_MASK           0x1000000
-#define GC_USB_DAINTMSK_OUTEPMSK8_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK8_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK8_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK9_LSB            0x19
-#define GC_USB_DAINTMSK_OUTEPMSK9_MASK           0x2000000
-#define GC_USB_DAINTMSK_OUTEPMSK9_SIZE           0x1
-#define GC_USB_DAINTMSK_OUTEPMSK9_DEFAULT        0x0
-#define GC_USB_DAINTMSK_OUTEPMSK9_OFFSET         0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK10_LSB           0x1a
-#define GC_USB_DAINTMSK_OUTEPMSK10_MASK          0x4000000
-#define GC_USB_DAINTMSK_OUTEPMSK10_SIZE          0x1
-#define GC_USB_DAINTMSK_OUTEPMSK10_DEFAULT       0x0
-#define GC_USB_DAINTMSK_OUTEPMSK10_OFFSET        0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK11_LSB           0x1b
-#define GC_USB_DAINTMSK_OUTEPMSK11_MASK          0x8000000
-#define GC_USB_DAINTMSK_OUTEPMSK11_SIZE          0x1
-#define GC_USB_DAINTMSK_OUTEPMSK11_DEFAULT       0x0
-#define GC_USB_DAINTMSK_OUTEPMSK11_OFFSET        0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK12_LSB           0x1c
-#define GC_USB_DAINTMSK_OUTEPMSK12_MASK          0x10000000
-#define GC_USB_DAINTMSK_OUTEPMSK12_SIZE          0x1
-#define GC_USB_DAINTMSK_OUTEPMSK12_DEFAULT       0x0
-#define GC_USB_DAINTMSK_OUTEPMSK12_OFFSET        0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK13_LSB           0x1d
-#define GC_USB_DAINTMSK_OUTEPMSK13_MASK          0x20000000
-#define GC_USB_DAINTMSK_OUTEPMSK13_SIZE          0x1
-#define GC_USB_DAINTMSK_OUTEPMSK13_DEFAULT       0x0
-#define GC_USB_DAINTMSK_OUTEPMSK13_OFFSET        0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK14_LSB           0x1e
-#define GC_USB_DAINTMSK_OUTEPMSK14_MASK          0x40000000
-#define GC_USB_DAINTMSK_OUTEPMSK14_SIZE          0x1
-#define GC_USB_DAINTMSK_OUTEPMSK14_DEFAULT       0x0
-#define GC_USB_DAINTMSK_OUTEPMSK14_OFFSET        0x81c
-#define GC_USB_DAINTMSK_OUTEPMSK15_LSB           0x1f
-#define GC_USB_DAINTMSK_OUTEPMSK15_MASK          0x80000000
-#define GC_USB_DAINTMSK_OUTEPMSK15_SIZE          0x1
-#define GC_USB_DAINTMSK_OUTEPMSK15_DEFAULT       0x0
-#define GC_USB_DAINTMSK_OUTEPMSK15_OFFSET        0x81c
-#define GC_USB_DVBUSDIS_DVBUSDIS_LSB             0x0
-#define GC_USB_DVBUSDIS_DVBUSDIS_MASK            0xffff
-#define GC_USB_DVBUSDIS_DVBUSDIS_SIZE            0x10
-#define GC_USB_DVBUSDIS_DVBUSDIS_DEFAULT         0x0
-#define GC_USB_DVBUSDIS_DVBUSDIS_OFFSET          0x828
-#define GC_USB_DVBUSPULSE_DVBUSPULSE_LSB         0x0
-#define GC_USB_DVBUSPULSE_DVBUSPULSE_MASK        0xfff
-#define GC_USB_DVBUSPULSE_DVBUSPULSE_SIZE        0xc
-#define GC_USB_DVBUSPULSE_DVBUSPULSE_DEFAULT     0x0
-#define GC_USB_DVBUSPULSE_DVBUSPULSE_OFFSET      0x82c
-#define GC_USB_DTHRCTL_NONISOTHREN_LSB           0x0
-#define GC_USB_DTHRCTL_NONISOTHREN_MASK          0x1
-#define GC_USB_DTHRCTL_NONISOTHREN_SIZE          0x1
-#define GC_USB_DTHRCTL_NONISOTHREN_DEFAULT       0x0
-#define GC_USB_DTHRCTL_NONISOTHREN_OFFSET        0x830
-#define GC_USB_DTHRCTL_ISOTHREN_LSB              0x1
-#define GC_USB_DTHRCTL_ISOTHREN_MASK             0x2
-#define GC_USB_DTHRCTL_ISOTHREN_SIZE             0x1
-#define GC_USB_DTHRCTL_ISOTHREN_DEFAULT          0x0
-#define GC_USB_DTHRCTL_ISOTHREN_OFFSET           0x830
-#define GC_USB_DTHRCTL_TXTHRLEN_LSB              0x2
-#define GC_USB_DTHRCTL_TXTHRLEN_MASK             0x7fc
-#define GC_USB_DTHRCTL_TXTHRLEN_SIZE             0x9
-#define GC_USB_DTHRCTL_TXTHRLEN_DEFAULT          0x0
-#define GC_USB_DTHRCTL_TXTHRLEN_OFFSET           0x830
-#define GC_USB_DTHRCTL_AHBTHRRATIO_LSB           0xb
-#define GC_USB_DTHRCTL_AHBTHRRATIO_MASK          0x1800
-#define GC_USB_DTHRCTL_AHBTHRRATIO_SIZE          0x2
-#define GC_USB_DTHRCTL_AHBTHRRATIO_DEFAULT       0x0
-#define GC_USB_DTHRCTL_AHBTHRRATIO_OFFSET        0x830
-#define GC_USB_DTHRCTL_RXTHREN_LSB               0x10
-#define GC_USB_DTHRCTL_RXTHREN_MASK              0x10000
-#define GC_USB_DTHRCTL_RXTHREN_SIZE              0x1
-#define GC_USB_DTHRCTL_RXTHREN_DEFAULT           0x0
-#define GC_USB_DTHRCTL_RXTHREN_OFFSET            0x830
-#define GC_USB_DTHRCTL_RXTHRLEN_LSB              0x11
-#define GC_USB_DTHRCTL_RXTHRLEN_MASK             0x3fe0000
-#define GC_USB_DTHRCTL_RXTHRLEN_SIZE             0x9
-#define GC_USB_DTHRCTL_RXTHRLEN_DEFAULT          0x0
-#define GC_USB_DTHRCTL_RXTHRLEN_OFFSET           0x830
-#define GC_USB_DTHRCTL_ARBPRKEN_LSB              0x1b
-#define GC_USB_DTHRCTL_ARBPRKEN_MASK             0x8000000
-#define GC_USB_DTHRCTL_ARBPRKEN_SIZE             0x1
-#define GC_USB_DTHRCTL_ARBPRKEN_DEFAULT          0x0
-#define GC_USB_DTHRCTL_ARBPRKEN_OFFSET           0x830
-#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_LSB      0x0
-#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_MASK     0xffff
-#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_SIZE     0x10
-#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_DEFAULT  0x0
-#define GC_USB_DIEPEMPMSK_INEPTXFEMPMSK_OFFSET   0x834
-#define GC_USB_DIEPCTL0_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL0_MPS_MASK                 0x3
-#define GC_USB_DIEPCTL0_MPS_SIZE                 0x2
-#define GC_USB_DIEPCTL0_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL0_MPS_OFFSET               0x900
-#define GC_USB_DIEPCTL0_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL0_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL0_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL0_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL0_USBACTEP_OFFSET          0x900
-#define GC_USB_DIEPCTL0_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL0_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL0_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL0_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL0_NAKSTS_OFFSET            0x900
-#define GC_USB_DIEPCTL0_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL0_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL0_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL0_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL0_EPTYPE_OFFSET            0x900
-#define GC_USB_DIEPCTL0_STALL_LSB                0x15
-#define GC_USB_DIEPCTL0_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL0_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL0_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL0_STALL_OFFSET             0x900
-#define GC_USB_DIEPCTL0_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL0_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL0_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL0_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL0_TXFNUM_OFFSET            0x900
-#define GC_USB_DIEPCTL0_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL0_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL0_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL0_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL0_CNAK_OFFSET              0x900
-#define GC_USB_DIEPCTL0_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL0_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL0_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL0_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL0_SNAK_OFFSET              0x900
-#define GC_USB_DIEPCTL0_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL0_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL0_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL0_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL0_EPDIS_OFFSET             0x900
-#define GC_USB_DIEPCTL0_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL0_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL0_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL0_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL0_EPENA_OFFSET             0x900
-#define GC_USB_DIEPINT0_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT0_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT0_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT0_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT0_XFERCOMPL_OFFSET         0x908
-#define GC_USB_DIEPINT0_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT0_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT0_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT0_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT0_EPDISBLD_OFFSET          0x908
-#define GC_USB_DIEPINT0_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT0_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT0_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT0_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT0_AHBERR_OFFSET            0x908
-#define GC_USB_DIEPINT0_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT0_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT0_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT0_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT0_TIMEOUT_OFFSET           0x908
-#define GC_USB_DIEPINT0_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT0_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT0_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT0_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT0_INTKNTXFEMP_OFFSET       0x908
-#define GC_USB_DIEPINT0_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT0_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT0_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT0_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT0_INTKNEPMIS_OFFSET        0x908
-#define GC_USB_DIEPINT0_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT0_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT0_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT0_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT0_INEPNAKEFF_OFFSET        0x908
-#define GC_USB_DIEPINT0_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT0_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT0_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT0_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT0_TXFEMP_OFFSET            0x908
-#define GC_USB_DIEPINT0_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT0_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT0_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT0_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT0_TXFIFOUNDRN_OFFSET       0x908
-#define GC_USB_DIEPINT0_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT0_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT0_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT0_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT0_BNAINTR_OFFSET           0x908
-#define GC_USB_DIEPINT0_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT0_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT0_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT0_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT0_PKTDRPSTS_OFFSET         0x908
-#define GC_USB_DIEPINT0_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT0_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT0_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT0_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT0_BBLEERR_OFFSET           0x908
-#define GC_USB_DIEPINT0_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT0_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT0_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT0_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT0_NAKINTRPT_OFFSET         0x908
-#define GC_USB_DIEPINT0_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT0_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT0_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT0_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT0_NYETINTRPT_OFFSET        0x908
-#define GC_USB_DIEPTSIZ0_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ0_XFERSIZE_MASK           0x7f
-#define GC_USB_DIEPTSIZ0_XFERSIZE_SIZE           0x7
-#define GC_USB_DIEPTSIZ0_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ0_XFERSIZE_OFFSET         0x910
-#define GC_USB_DIEPTSIZ0_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ0_PKTCNT_MASK             0x180000
-#define GC_USB_DIEPTSIZ0_PKTCNT_SIZE             0x2
-#define GC_USB_DIEPTSIZ0_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ0_PKTCNT_OFFSET           0x910
-#define GC_USB_DIEPDMA0_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA0_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA0_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA0_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA0_DMAADDR_OFFSET           0x914
-#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS0_INEPTXFSPCAVAIL_OFFSET   0x918
-#define GC_USB_DIEPDMAB0_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB0_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB0_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB0_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB0_DMABUFFERADDR_OFFSET    0x91c
-#define GC_USB_DIEPCTL1_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL1_MPS_MASK                 0x7ff
-#define GC_USB_DIEPCTL1_MPS_SIZE                 0xb
-#define GC_USB_DIEPCTL1_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL1_MPS_OFFSET               0x920
-#define GC_USB_DIEPCTL1_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL1_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL1_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL1_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL1_USBACTEP_OFFSET          0x920
-#define GC_USB_DIEPCTL1_DPID_LSB                 0x10
-#define GC_USB_DIEPCTL1_DPID_MASK                0x10000
-#define GC_USB_DIEPCTL1_DPID_SIZE                0x1
-#define GC_USB_DIEPCTL1_DPID_DEFAULT             0x0
-#define GC_USB_DIEPCTL1_DPID_OFFSET              0x920
-#define GC_USB_DIEPCTL1_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL1_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL1_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL1_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL1_NAKSTS_OFFSET            0x920
-#define GC_USB_DIEPCTL1_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL1_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL1_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL1_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL1_EPTYPE_OFFSET            0x920
-#define GC_USB_DIEPCTL1_STALL_LSB                0x15
-#define GC_USB_DIEPCTL1_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL1_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL1_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL1_STALL_OFFSET             0x920
-#define GC_USB_DIEPCTL1_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL1_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL1_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL1_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL1_TXFNUM_OFFSET            0x920
-#define GC_USB_DIEPCTL1_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL1_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL1_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL1_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL1_CNAK_OFFSET              0x920
-#define GC_USB_DIEPCTL1_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL1_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL1_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL1_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL1_SNAK_OFFSET              0x920
-#define GC_USB_DIEPCTL1_SETD0PID_LSB             0x1c
-#define GC_USB_DIEPCTL1_SETD0PID_MASK            0x10000000
-#define GC_USB_DIEPCTL1_SETD0PID_SIZE            0x1
-#define GC_USB_DIEPCTL1_SETD0PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL1_SETD0PID_OFFSET          0x920
-#define GC_USB_DIEPCTL1_SETD1PID_LSB             0x1d
-#define GC_USB_DIEPCTL1_SETD1PID_MASK            0x20000000
-#define GC_USB_DIEPCTL1_SETD1PID_SIZE            0x1
-#define GC_USB_DIEPCTL1_SETD1PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL1_SETD1PID_OFFSET          0x920
-#define GC_USB_DIEPCTL1_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL1_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL1_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL1_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL1_EPDIS_OFFSET             0x920
-#define GC_USB_DIEPCTL1_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL1_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL1_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL1_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL1_EPENA_OFFSET             0x920
-#define GC_USB_DIEPINT1_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT1_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT1_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT1_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT1_XFERCOMPL_OFFSET         0x928
-#define GC_USB_DIEPINT1_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT1_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT1_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT1_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT1_EPDISBLD_OFFSET          0x928
-#define GC_USB_DIEPINT1_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT1_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT1_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT1_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT1_AHBERR_OFFSET            0x928
-#define GC_USB_DIEPINT1_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT1_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT1_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT1_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT1_TIMEOUT_OFFSET           0x928
-#define GC_USB_DIEPINT1_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT1_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT1_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT1_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT1_INTKNTXFEMP_OFFSET       0x928
-#define GC_USB_DIEPINT1_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT1_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT1_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT1_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT1_INTKNEPMIS_OFFSET        0x928
-#define GC_USB_DIEPINT1_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT1_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT1_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT1_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT1_INEPNAKEFF_OFFSET        0x928
-#define GC_USB_DIEPINT1_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT1_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT1_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT1_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT1_TXFEMP_OFFSET            0x928
-#define GC_USB_DIEPINT1_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT1_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT1_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT1_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT1_TXFIFOUNDRN_OFFSET       0x928
-#define GC_USB_DIEPINT1_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT1_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT1_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT1_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT1_BNAINTR_OFFSET           0x928
-#define GC_USB_DIEPINT1_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT1_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT1_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT1_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT1_PKTDRPSTS_OFFSET         0x928
-#define GC_USB_DIEPINT1_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT1_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT1_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT1_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT1_BBLEERR_OFFSET           0x928
-#define GC_USB_DIEPINT1_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT1_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT1_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT1_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT1_NAKINTRPT_OFFSET         0x928
-#define GC_USB_DIEPINT1_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT1_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT1_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT1_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT1_NYETINTRPT_OFFSET        0x928
-#define GC_USB_DIEPTSIZ1_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ1_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DIEPTSIZ1_XFERSIZE_SIZE           0x13
-#define GC_USB_DIEPTSIZ1_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ1_XFERSIZE_OFFSET         0x930
-#define GC_USB_DIEPTSIZ1_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ1_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DIEPTSIZ1_PKTCNT_SIZE             0xa
-#define GC_USB_DIEPTSIZ1_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ1_PKTCNT_OFFSET           0x930
-#define GC_USB_DIEPTSIZ1_MC_LSB                  0x1d
-#define GC_USB_DIEPTSIZ1_MC_MASK                 0x60000000
-#define GC_USB_DIEPTSIZ1_MC_SIZE                 0x2
-#define GC_USB_DIEPTSIZ1_MC_DEFAULT              0x0
-#define GC_USB_DIEPTSIZ1_MC_OFFSET               0x930
-#define GC_USB_DIEPDMA1_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA1_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA1_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA1_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA1_DMAADDR_OFFSET           0x934
-#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS1_INEPTXFSPCAVAIL_OFFSET   0x938
-#define GC_USB_DIEPDMAB1_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB1_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB1_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB1_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB1_DMABUFFERADDR_OFFSET    0x93c
-#define GC_USB_DIEPCTL2_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL2_MPS_MASK                 0x7ff
-#define GC_USB_DIEPCTL2_MPS_SIZE                 0xb
-#define GC_USB_DIEPCTL2_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL2_MPS_OFFSET               0x940
-#define GC_USB_DIEPCTL2_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL2_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL2_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL2_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL2_USBACTEP_OFFSET          0x940
-#define GC_USB_DIEPCTL2_DPID_LSB                 0x10
-#define GC_USB_DIEPCTL2_DPID_MASK                0x10000
-#define GC_USB_DIEPCTL2_DPID_SIZE                0x1
-#define GC_USB_DIEPCTL2_DPID_DEFAULT             0x0
-#define GC_USB_DIEPCTL2_DPID_OFFSET              0x940
-#define GC_USB_DIEPCTL2_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL2_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL2_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL2_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL2_NAKSTS_OFFSET            0x940
-#define GC_USB_DIEPCTL2_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL2_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL2_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL2_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL2_EPTYPE_OFFSET            0x940
-#define GC_USB_DIEPCTL2_STALL_LSB                0x15
-#define GC_USB_DIEPCTL2_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL2_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL2_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL2_STALL_OFFSET             0x940
-#define GC_USB_DIEPCTL2_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL2_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL2_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL2_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL2_TXFNUM_OFFSET            0x940
-#define GC_USB_DIEPCTL2_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL2_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL2_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL2_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL2_CNAK_OFFSET              0x940
-#define GC_USB_DIEPCTL2_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL2_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL2_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL2_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL2_SNAK_OFFSET              0x940
-#define GC_USB_DIEPCTL2_SETD0PID_LSB             0x1c
-#define GC_USB_DIEPCTL2_SETD0PID_MASK            0x10000000
-#define GC_USB_DIEPCTL2_SETD0PID_SIZE            0x1
-#define GC_USB_DIEPCTL2_SETD0PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL2_SETD0PID_OFFSET          0x940
-#define GC_USB_DIEPCTL2_SETD1PID_LSB             0x1d
-#define GC_USB_DIEPCTL2_SETD1PID_MASK            0x20000000
-#define GC_USB_DIEPCTL2_SETD1PID_SIZE            0x1
-#define GC_USB_DIEPCTL2_SETD1PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL2_SETD1PID_OFFSET          0x940
-#define GC_USB_DIEPCTL2_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL2_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL2_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL2_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL2_EPDIS_OFFSET             0x940
-#define GC_USB_DIEPCTL2_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL2_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL2_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL2_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL2_EPENA_OFFSET             0x940
-#define GC_USB_DIEPINT2_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT2_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT2_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT2_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT2_XFERCOMPL_OFFSET         0x948
-#define GC_USB_DIEPINT2_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT2_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT2_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT2_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT2_EPDISBLD_OFFSET          0x948
-#define GC_USB_DIEPINT2_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT2_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT2_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT2_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT2_AHBERR_OFFSET            0x948
-#define GC_USB_DIEPINT2_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT2_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT2_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT2_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT2_TIMEOUT_OFFSET           0x948
-#define GC_USB_DIEPINT2_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT2_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT2_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT2_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT2_INTKNTXFEMP_OFFSET       0x948
-#define GC_USB_DIEPINT2_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT2_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT2_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT2_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT2_INTKNEPMIS_OFFSET        0x948
-#define GC_USB_DIEPINT2_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT2_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT2_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT2_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT2_INEPNAKEFF_OFFSET        0x948
-#define GC_USB_DIEPINT2_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT2_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT2_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT2_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT2_TXFEMP_OFFSET            0x948
-#define GC_USB_DIEPINT2_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT2_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT2_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT2_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT2_TXFIFOUNDRN_OFFSET       0x948
-#define GC_USB_DIEPINT2_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT2_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT2_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT2_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT2_BNAINTR_OFFSET           0x948
-#define GC_USB_DIEPINT2_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT2_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT2_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT2_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT2_PKTDRPSTS_OFFSET         0x948
-#define GC_USB_DIEPINT2_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT2_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT2_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT2_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT2_BBLEERR_OFFSET           0x948
-#define GC_USB_DIEPINT2_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT2_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT2_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT2_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT2_NAKINTRPT_OFFSET         0x948
-#define GC_USB_DIEPINT2_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT2_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT2_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT2_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT2_NYETINTRPT_OFFSET        0x948
-#define GC_USB_DIEPTSIZ2_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ2_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DIEPTSIZ2_XFERSIZE_SIZE           0x13
-#define GC_USB_DIEPTSIZ2_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ2_XFERSIZE_OFFSET         0x950
-#define GC_USB_DIEPTSIZ2_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ2_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DIEPTSIZ2_PKTCNT_SIZE             0xa
-#define GC_USB_DIEPTSIZ2_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ2_PKTCNT_OFFSET           0x950
-#define GC_USB_DIEPTSIZ2_MC_LSB                  0x1d
-#define GC_USB_DIEPTSIZ2_MC_MASK                 0x60000000
-#define GC_USB_DIEPTSIZ2_MC_SIZE                 0x2
-#define GC_USB_DIEPTSIZ2_MC_DEFAULT              0x0
-#define GC_USB_DIEPTSIZ2_MC_OFFSET               0x950
-#define GC_USB_DIEPDMA2_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA2_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA2_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA2_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA2_DMAADDR_OFFSET           0x954
-#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS2_INEPTXFSPCAVAIL_OFFSET   0x958
-#define GC_USB_DIEPDMAB2_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB2_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB2_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB2_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB2_DMABUFFERADDR_OFFSET    0x95c
-#define GC_USB_DIEPCTL3_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL3_MPS_MASK                 0x7ff
-#define GC_USB_DIEPCTL3_MPS_SIZE                 0xb
-#define GC_USB_DIEPCTL3_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL3_MPS_OFFSET               0x960
-#define GC_USB_DIEPCTL3_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL3_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL3_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL3_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL3_USBACTEP_OFFSET          0x960
-#define GC_USB_DIEPCTL3_DPID_LSB                 0x10
-#define GC_USB_DIEPCTL3_DPID_MASK                0x10000
-#define GC_USB_DIEPCTL3_DPID_SIZE                0x1
-#define GC_USB_DIEPCTL3_DPID_DEFAULT             0x0
-#define GC_USB_DIEPCTL3_DPID_OFFSET              0x960
-#define GC_USB_DIEPCTL3_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL3_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL3_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL3_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL3_NAKSTS_OFFSET            0x960
-#define GC_USB_DIEPCTL3_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL3_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL3_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL3_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL3_EPTYPE_OFFSET            0x960
-#define GC_USB_DIEPCTL3_STALL_LSB                0x15
-#define GC_USB_DIEPCTL3_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL3_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL3_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL3_STALL_OFFSET             0x960
-#define GC_USB_DIEPCTL3_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL3_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL3_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL3_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL3_TXFNUM_OFFSET            0x960
-#define GC_USB_DIEPCTL3_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL3_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL3_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL3_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL3_CNAK_OFFSET              0x960
-#define GC_USB_DIEPCTL3_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL3_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL3_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL3_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL3_SNAK_OFFSET              0x960
-#define GC_USB_DIEPCTL3_SETD0PID_LSB             0x1c
-#define GC_USB_DIEPCTL3_SETD0PID_MASK            0x10000000
-#define GC_USB_DIEPCTL3_SETD0PID_SIZE            0x1
-#define GC_USB_DIEPCTL3_SETD0PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL3_SETD0PID_OFFSET          0x960
-#define GC_USB_DIEPCTL3_SETD1PID_LSB             0x1d
-#define GC_USB_DIEPCTL3_SETD1PID_MASK            0x20000000
-#define GC_USB_DIEPCTL3_SETD1PID_SIZE            0x1
-#define GC_USB_DIEPCTL3_SETD1PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL3_SETD1PID_OFFSET          0x960
-#define GC_USB_DIEPCTL3_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL3_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL3_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL3_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL3_EPDIS_OFFSET             0x960
-#define GC_USB_DIEPCTL3_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL3_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL3_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL3_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL3_EPENA_OFFSET             0x960
-#define GC_USB_DIEPINT3_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT3_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT3_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT3_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT3_XFERCOMPL_OFFSET         0x968
-#define GC_USB_DIEPINT3_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT3_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT3_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT3_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT3_EPDISBLD_OFFSET          0x968
-#define GC_USB_DIEPINT3_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT3_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT3_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT3_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT3_AHBERR_OFFSET            0x968
-#define GC_USB_DIEPINT3_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT3_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT3_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT3_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT3_TIMEOUT_OFFSET           0x968
-#define GC_USB_DIEPINT3_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT3_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT3_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT3_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT3_INTKNTXFEMP_OFFSET       0x968
-#define GC_USB_DIEPINT3_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT3_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT3_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT3_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT3_INTKNEPMIS_OFFSET        0x968
-#define GC_USB_DIEPINT3_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT3_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT3_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT3_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT3_INEPNAKEFF_OFFSET        0x968
-#define GC_USB_DIEPINT3_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT3_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT3_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT3_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT3_TXFEMP_OFFSET            0x968
-#define GC_USB_DIEPINT3_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT3_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT3_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT3_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT3_TXFIFOUNDRN_OFFSET       0x968
-#define GC_USB_DIEPINT3_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT3_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT3_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT3_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT3_BNAINTR_OFFSET           0x968
-#define GC_USB_DIEPINT3_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT3_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT3_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT3_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT3_PKTDRPSTS_OFFSET         0x968
-#define GC_USB_DIEPINT3_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT3_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT3_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT3_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT3_BBLEERR_OFFSET           0x968
-#define GC_USB_DIEPINT3_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT3_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT3_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT3_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT3_NAKINTRPT_OFFSET         0x968
-#define GC_USB_DIEPINT3_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT3_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT3_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT3_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT3_NYETINTRPT_OFFSET        0x968
-#define GC_USB_DIEPTSIZ3_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ3_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DIEPTSIZ3_XFERSIZE_SIZE           0x13
-#define GC_USB_DIEPTSIZ3_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ3_XFERSIZE_OFFSET         0x970
-#define GC_USB_DIEPTSIZ3_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ3_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DIEPTSIZ3_PKTCNT_SIZE             0xa
-#define GC_USB_DIEPTSIZ3_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ3_PKTCNT_OFFSET           0x970
-#define GC_USB_DIEPTSIZ3_MC_LSB                  0x1d
-#define GC_USB_DIEPTSIZ3_MC_MASK                 0x60000000
-#define GC_USB_DIEPTSIZ3_MC_SIZE                 0x2
-#define GC_USB_DIEPTSIZ3_MC_DEFAULT              0x0
-#define GC_USB_DIEPTSIZ3_MC_OFFSET               0x970
-#define GC_USB_DIEPDMA3_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA3_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA3_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA3_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA3_DMAADDR_OFFSET           0x974
-#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS3_INEPTXFSPCAVAIL_OFFSET   0x978
-#define GC_USB_DIEPDMAB3_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB3_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB3_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB3_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB3_DMABUFFERADDR_OFFSET    0x97c
-#define GC_USB_DIEPCTL4_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL4_MPS_MASK                 0x7ff
-#define GC_USB_DIEPCTL4_MPS_SIZE                 0xb
-#define GC_USB_DIEPCTL4_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL4_MPS_OFFSET               0x980
-#define GC_USB_DIEPCTL4_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL4_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL4_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL4_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL4_USBACTEP_OFFSET          0x980
-#define GC_USB_DIEPCTL4_DPID_LSB                 0x10
-#define GC_USB_DIEPCTL4_DPID_MASK                0x10000
-#define GC_USB_DIEPCTL4_DPID_SIZE                0x1
-#define GC_USB_DIEPCTL4_DPID_DEFAULT             0x0
-#define GC_USB_DIEPCTL4_DPID_OFFSET              0x980
-#define GC_USB_DIEPCTL4_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL4_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL4_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL4_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL4_NAKSTS_OFFSET            0x980
-#define GC_USB_DIEPCTL4_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL4_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL4_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL4_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL4_EPTYPE_OFFSET            0x980
-#define GC_USB_DIEPCTL4_STALL_LSB                0x15
-#define GC_USB_DIEPCTL4_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL4_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL4_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL4_STALL_OFFSET             0x980
-#define GC_USB_DIEPCTL4_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL4_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL4_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL4_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL4_TXFNUM_OFFSET            0x980
-#define GC_USB_DIEPCTL4_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL4_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL4_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL4_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL4_CNAK_OFFSET              0x980
-#define GC_USB_DIEPCTL4_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL4_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL4_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL4_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL4_SNAK_OFFSET              0x980
-#define GC_USB_DIEPCTL4_SETD0PID_LSB             0x1c
-#define GC_USB_DIEPCTL4_SETD0PID_MASK            0x10000000
-#define GC_USB_DIEPCTL4_SETD0PID_SIZE            0x1
-#define GC_USB_DIEPCTL4_SETD0PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL4_SETD0PID_OFFSET          0x980
-#define GC_USB_DIEPCTL4_SETD1PID_LSB             0x1d
-#define GC_USB_DIEPCTL4_SETD1PID_MASK            0x20000000
-#define GC_USB_DIEPCTL4_SETD1PID_SIZE            0x1
-#define GC_USB_DIEPCTL4_SETD1PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL4_SETD1PID_OFFSET          0x980
-#define GC_USB_DIEPCTL4_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL4_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL4_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL4_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL4_EPDIS_OFFSET             0x980
-#define GC_USB_DIEPCTL4_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL4_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL4_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL4_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL4_EPENA_OFFSET             0x980
-#define GC_USB_DIEPINT4_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT4_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT4_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT4_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT4_XFERCOMPL_OFFSET         0x988
-#define GC_USB_DIEPINT4_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT4_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT4_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT4_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT4_EPDISBLD_OFFSET          0x988
-#define GC_USB_DIEPINT4_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT4_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT4_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT4_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT4_AHBERR_OFFSET            0x988
-#define GC_USB_DIEPINT4_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT4_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT4_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT4_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT4_TIMEOUT_OFFSET           0x988
-#define GC_USB_DIEPINT4_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT4_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT4_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT4_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT4_INTKNTXFEMP_OFFSET       0x988
-#define GC_USB_DIEPINT4_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT4_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT4_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT4_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT4_INTKNEPMIS_OFFSET        0x988
-#define GC_USB_DIEPINT4_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT4_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT4_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT4_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT4_INEPNAKEFF_OFFSET        0x988
-#define GC_USB_DIEPINT4_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT4_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT4_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT4_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT4_TXFEMP_OFFSET            0x988
-#define GC_USB_DIEPINT4_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT4_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT4_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT4_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT4_TXFIFOUNDRN_OFFSET       0x988
-#define GC_USB_DIEPINT4_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT4_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT4_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT4_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT4_BNAINTR_OFFSET           0x988
-#define GC_USB_DIEPINT4_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT4_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT4_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT4_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT4_PKTDRPSTS_OFFSET         0x988
-#define GC_USB_DIEPINT4_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT4_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT4_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT4_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT4_BBLEERR_OFFSET           0x988
-#define GC_USB_DIEPINT4_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT4_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT4_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT4_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT4_NAKINTRPT_OFFSET         0x988
-#define GC_USB_DIEPINT4_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT4_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT4_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT4_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT4_NYETINTRPT_OFFSET        0x988
-#define GC_USB_DIEPTSIZ4_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ4_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DIEPTSIZ4_XFERSIZE_SIZE           0x13
-#define GC_USB_DIEPTSIZ4_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ4_XFERSIZE_OFFSET         0x990
-#define GC_USB_DIEPTSIZ4_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ4_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DIEPTSIZ4_PKTCNT_SIZE             0xa
-#define GC_USB_DIEPTSIZ4_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ4_PKTCNT_OFFSET           0x990
-#define GC_USB_DIEPTSIZ4_MC_LSB                  0x1d
-#define GC_USB_DIEPTSIZ4_MC_MASK                 0x60000000
-#define GC_USB_DIEPTSIZ4_MC_SIZE                 0x2
-#define GC_USB_DIEPTSIZ4_MC_DEFAULT              0x0
-#define GC_USB_DIEPTSIZ4_MC_OFFSET               0x990
-#define GC_USB_DIEPDMA4_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA4_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA4_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA4_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA4_DMAADDR_OFFSET           0x994
-#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS4_INEPTXFSPCAVAIL_OFFSET   0x998
-#define GC_USB_DIEPDMAB4_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB4_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB4_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB4_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB4_DMABUFFERADDR_OFFSET    0x99c
-#define GC_USB_DIEPCTL5_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL5_MPS_MASK                 0x7ff
-#define GC_USB_DIEPCTL5_MPS_SIZE                 0xb
-#define GC_USB_DIEPCTL5_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL5_MPS_OFFSET               0x9a0
-#define GC_USB_DIEPCTL5_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL5_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL5_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL5_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL5_USBACTEP_OFFSET          0x9a0
-#define GC_USB_DIEPCTL5_DPID_LSB                 0x10
-#define GC_USB_DIEPCTL5_DPID_MASK                0x10000
-#define GC_USB_DIEPCTL5_DPID_SIZE                0x1
-#define GC_USB_DIEPCTL5_DPID_DEFAULT             0x0
-#define GC_USB_DIEPCTL5_DPID_OFFSET              0x9a0
-#define GC_USB_DIEPCTL5_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL5_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL5_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL5_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL5_NAKSTS_OFFSET            0x9a0
-#define GC_USB_DIEPCTL5_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL5_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL5_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL5_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL5_EPTYPE_OFFSET            0x9a0
-#define GC_USB_DIEPCTL5_STALL_LSB                0x15
-#define GC_USB_DIEPCTL5_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL5_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL5_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL5_STALL_OFFSET             0x9a0
-#define GC_USB_DIEPCTL5_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL5_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL5_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL5_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL5_TXFNUM_OFFSET            0x9a0
-#define GC_USB_DIEPCTL5_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL5_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL5_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL5_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL5_CNAK_OFFSET              0x9a0
-#define GC_USB_DIEPCTL5_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL5_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL5_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL5_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL5_SNAK_OFFSET              0x9a0
-#define GC_USB_DIEPCTL5_SETD0PID_LSB             0x1c
-#define GC_USB_DIEPCTL5_SETD0PID_MASK            0x10000000
-#define GC_USB_DIEPCTL5_SETD0PID_SIZE            0x1
-#define GC_USB_DIEPCTL5_SETD0PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL5_SETD0PID_OFFSET          0x9a0
-#define GC_USB_DIEPCTL5_SETD1PID_LSB             0x1d
-#define GC_USB_DIEPCTL5_SETD1PID_MASK            0x20000000
-#define GC_USB_DIEPCTL5_SETD1PID_SIZE            0x1
-#define GC_USB_DIEPCTL5_SETD1PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL5_SETD1PID_OFFSET          0x9a0
-#define GC_USB_DIEPCTL5_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL5_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL5_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL5_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL5_EPDIS_OFFSET             0x9a0
-#define GC_USB_DIEPCTL5_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL5_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL5_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL5_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL5_EPENA_OFFSET             0x9a0
-#define GC_USB_DIEPINT5_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT5_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT5_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT5_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT5_XFERCOMPL_OFFSET         0x9a8
-#define GC_USB_DIEPINT5_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT5_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT5_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT5_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT5_EPDISBLD_OFFSET          0x9a8
-#define GC_USB_DIEPINT5_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT5_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT5_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT5_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT5_AHBERR_OFFSET            0x9a8
-#define GC_USB_DIEPINT5_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT5_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT5_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT5_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT5_TIMEOUT_OFFSET           0x9a8
-#define GC_USB_DIEPINT5_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT5_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT5_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT5_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT5_INTKNTXFEMP_OFFSET       0x9a8
-#define GC_USB_DIEPINT5_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT5_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT5_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT5_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT5_INTKNEPMIS_OFFSET        0x9a8
-#define GC_USB_DIEPINT5_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT5_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT5_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT5_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT5_INEPNAKEFF_OFFSET        0x9a8
-#define GC_USB_DIEPINT5_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT5_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT5_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT5_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT5_TXFEMP_OFFSET            0x9a8
-#define GC_USB_DIEPINT5_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT5_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT5_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT5_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT5_TXFIFOUNDRN_OFFSET       0x9a8
-#define GC_USB_DIEPINT5_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT5_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT5_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT5_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT5_BNAINTR_OFFSET           0x9a8
-#define GC_USB_DIEPINT5_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT5_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT5_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT5_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT5_PKTDRPSTS_OFFSET         0x9a8
-#define GC_USB_DIEPINT5_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT5_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT5_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT5_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT5_BBLEERR_OFFSET           0x9a8
-#define GC_USB_DIEPINT5_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT5_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT5_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT5_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT5_NAKINTRPT_OFFSET         0x9a8
-#define GC_USB_DIEPINT5_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT5_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT5_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT5_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT5_NYETINTRPT_OFFSET        0x9a8
-#define GC_USB_DIEPTSIZ5_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ5_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DIEPTSIZ5_XFERSIZE_SIZE           0x13
-#define GC_USB_DIEPTSIZ5_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ5_XFERSIZE_OFFSET         0x9b0
-#define GC_USB_DIEPTSIZ5_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ5_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DIEPTSIZ5_PKTCNT_SIZE             0xa
-#define GC_USB_DIEPTSIZ5_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ5_PKTCNT_OFFSET           0x9b0
-#define GC_USB_DIEPTSIZ5_MC_LSB                  0x1d
-#define GC_USB_DIEPTSIZ5_MC_MASK                 0x60000000
-#define GC_USB_DIEPTSIZ5_MC_SIZE                 0x2
-#define GC_USB_DIEPTSIZ5_MC_DEFAULT              0x0
-#define GC_USB_DIEPTSIZ5_MC_OFFSET               0x9b0
-#define GC_USB_DIEPDMA5_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA5_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA5_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA5_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA5_DMAADDR_OFFSET           0x9b4
-#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS5_INEPTXFSPCAVAIL_OFFSET   0x9b8
-#define GC_USB_DIEPDMAB5_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB5_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB5_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB5_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB5_DMABUFFERADDR_OFFSET    0x9bc
-#define GC_USB_DIEPCTL6_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL6_MPS_MASK                 0x7ff
-#define GC_USB_DIEPCTL6_MPS_SIZE                 0xb
-#define GC_USB_DIEPCTL6_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL6_MPS_OFFSET               0x9c0
-#define GC_USB_DIEPCTL6_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL6_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL6_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL6_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL6_USBACTEP_OFFSET          0x9c0
-#define GC_USB_DIEPCTL6_DPID_LSB                 0x10
-#define GC_USB_DIEPCTL6_DPID_MASK                0x10000
-#define GC_USB_DIEPCTL6_DPID_SIZE                0x1
-#define GC_USB_DIEPCTL6_DPID_DEFAULT             0x0
-#define GC_USB_DIEPCTL6_DPID_OFFSET              0x9c0
-#define GC_USB_DIEPCTL6_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL6_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL6_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL6_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL6_NAKSTS_OFFSET            0x9c0
-#define GC_USB_DIEPCTL6_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL6_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL6_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL6_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL6_EPTYPE_OFFSET            0x9c0
-#define GC_USB_DIEPCTL6_STALL_LSB                0x15
-#define GC_USB_DIEPCTL6_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL6_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL6_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL6_STALL_OFFSET             0x9c0
-#define GC_USB_DIEPCTL6_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL6_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL6_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL6_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL6_TXFNUM_OFFSET            0x9c0
-#define GC_USB_DIEPCTL6_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL6_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL6_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL6_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL6_CNAK_OFFSET              0x9c0
-#define GC_USB_DIEPCTL6_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL6_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL6_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL6_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL6_SNAK_OFFSET              0x9c0
-#define GC_USB_DIEPCTL6_SETD0PID_LSB             0x1c
-#define GC_USB_DIEPCTL6_SETD0PID_MASK            0x10000000
-#define GC_USB_DIEPCTL6_SETD0PID_SIZE            0x1
-#define GC_USB_DIEPCTL6_SETD0PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL6_SETD0PID_OFFSET          0x9c0
-#define GC_USB_DIEPCTL6_SETD1PID_LSB             0x1d
-#define GC_USB_DIEPCTL6_SETD1PID_MASK            0x20000000
-#define GC_USB_DIEPCTL6_SETD1PID_SIZE            0x1
-#define GC_USB_DIEPCTL6_SETD1PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL6_SETD1PID_OFFSET          0x9c0
-#define GC_USB_DIEPCTL6_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL6_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL6_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL6_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL6_EPDIS_OFFSET             0x9c0
-#define GC_USB_DIEPCTL6_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL6_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL6_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL6_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL6_EPENA_OFFSET             0x9c0
-#define GC_USB_DIEPINT6_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT6_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT6_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT6_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT6_XFERCOMPL_OFFSET         0x9c8
-#define GC_USB_DIEPINT6_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT6_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT6_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT6_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT6_EPDISBLD_OFFSET          0x9c8
-#define GC_USB_DIEPINT6_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT6_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT6_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT6_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT6_AHBERR_OFFSET            0x9c8
-#define GC_USB_DIEPINT6_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT6_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT6_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT6_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT6_TIMEOUT_OFFSET           0x9c8
-#define GC_USB_DIEPINT6_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT6_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT6_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT6_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT6_INTKNTXFEMP_OFFSET       0x9c8
-#define GC_USB_DIEPINT6_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT6_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT6_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT6_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT6_INTKNEPMIS_OFFSET        0x9c8
-#define GC_USB_DIEPINT6_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT6_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT6_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT6_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT6_INEPNAKEFF_OFFSET        0x9c8
-#define GC_USB_DIEPINT6_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT6_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT6_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT6_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT6_TXFEMP_OFFSET            0x9c8
-#define GC_USB_DIEPINT6_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT6_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT6_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT6_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT6_TXFIFOUNDRN_OFFSET       0x9c8
-#define GC_USB_DIEPINT6_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT6_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT6_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT6_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT6_BNAINTR_OFFSET           0x9c8
-#define GC_USB_DIEPINT6_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT6_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT6_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT6_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT6_PKTDRPSTS_OFFSET         0x9c8
-#define GC_USB_DIEPINT6_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT6_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT6_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT6_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT6_BBLEERR_OFFSET           0x9c8
-#define GC_USB_DIEPINT6_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT6_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT6_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT6_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT6_NAKINTRPT_OFFSET         0x9c8
-#define GC_USB_DIEPINT6_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT6_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT6_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT6_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT6_NYETINTRPT_OFFSET        0x9c8
-#define GC_USB_DIEPTSIZ6_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ6_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DIEPTSIZ6_XFERSIZE_SIZE           0x13
-#define GC_USB_DIEPTSIZ6_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ6_XFERSIZE_OFFSET         0x9d0
-#define GC_USB_DIEPTSIZ6_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ6_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DIEPTSIZ6_PKTCNT_SIZE             0xa
-#define GC_USB_DIEPTSIZ6_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ6_PKTCNT_OFFSET           0x9d0
-#define GC_USB_DIEPTSIZ6_MC_LSB                  0x1d
-#define GC_USB_DIEPTSIZ6_MC_MASK                 0x60000000
-#define GC_USB_DIEPTSIZ6_MC_SIZE                 0x2
-#define GC_USB_DIEPTSIZ6_MC_DEFAULT              0x0
-#define GC_USB_DIEPTSIZ6_MC_OFFSET               0x9d0
-#define GC_USB_DIEPDMA6_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA6_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA6_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA6_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA6_DMAADDR_OFFSET           0x9d4
-#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS6_INEPTXFSPCAVAIL_OFFSET   0x9d8
-#define GC_USB_DIEPDMAB6_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB6_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB6_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB6_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB6_DMABUFFERADDR_OFFSET    0x9dc
-#define GC_USB_DIEPCTL7_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL7_MPS_MASK                 0x7ff
-#define GC_USB_DIEPCTL7_MPS_SIZE                 0xb
-#define GC_USB_DIEPCTL7_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL7_MPS_OFFSET               0x9e0
-#define GC_USB_DIEPCTL7_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL7_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL7_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL7_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL7_USBACTEP_OFFSET          0x9e0
-#define GC_USB_DIEPCTL7_DPID_LSB                 0x10
-#define GC_USB_DIEPCTL7_DPID_MASK                0x10000
-#define GC_USB_DIEPCTL7_DPID_SIZE                0x1
-#define GC_USB_DIEPCTL7_DPID_DEFAULT             0x0
-#define GC_USB_DIEPCTL7_DPID_OFFSET              0x9e0
-#define GC_USB_DIEPCTL7_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL7_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL7_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL7_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL7_NAKSTS_OFFSET            0x9e0
-#define GC_USB_DIEPCTL7_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL7_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL7_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL7_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL7_EPTYPE_OFFSET            0x9e0
-#define GC_USB_DIEPCTL7_STALL_LSB                0x15
-#define GC_USB_DIEPCTL7_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL7_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL7_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL7_STALL_OFFSET             0x9e0
-#define GC_USB_DIEPCTL7_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL7_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL7_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL7_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL7_TXFNUM_OFFSET            0x9e0
-#define GC_USB_DIEPCTL7_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL7_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL7_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL7_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL7_CNAK_OFFSET              0x9e0
-#define GC_USB_DIEPCTL7_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL7_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL7_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL7_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL7_SNAK_OFFSET              0x9e0
-#define GC_USB_DIEPCTL7_SETD0PID_LSB             0x1c
-#define GC_USB_DIEPCTL7_SETD0PID_MASK            0x10000000
-#define GC_USB_DIEPCTL7_SETD0PID_SIZE            0x1
-#define GC_USB_DIEPCTL7_SETD0PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL7_SETD0PID_OFFSET          0x9e0
-#define GC_USB_DIEPCTL7_SETD1PID_LSB             0x1d
-#define GC_USB_DIEPCTL7_SETD1PID_MASK            0x20000000
-#define GC_USB_DIEPCTL7_SETD1PID_SIZE            0x1
-#define GC_USB_DIEPCTL7_SETD1PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL7_SETD1PID_OFFSET          0x9e0
-#define GC_USB_DIEPCTL7_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL7_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL7_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL7_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL7_EPDIS_OFFSET             0x9e0
-#define GC_USB_DIEPCTL7_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL7_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL7_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL7_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL7_EPENA_OFFSET             0x9e0
-#define GC_USB_DIEPINT7_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT7_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT7_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT7_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT7_XFERCOMPL_OFFSET         0x9e8
-#define GC_USB_DIEPINT7_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT7_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT7_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT7_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT7_EPDISBLD_OFFSET          0x9e8
-#define GC_USB_DIEPINT7_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT7_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT7_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT7_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT7_AHBERR_OFFSET            0x9e8
-#define GC_USB_DIEPINT7_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT7_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT7_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT7_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT7_TIMEOUT_OFFSET           0x9e8
-#define GC_USB_DIEPINT7_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT7_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT7_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT7_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT7_INTKNTXFEMP_OFFSET       0x9e8
-#define GC_USB_DIEPINT7_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT7_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT7_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT7_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT7_INTKNEPMIS_OFFSET        0x9e8
-#define GC_USB_DIEPINT7_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT7_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT7_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT7_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT7_INEPNAKEFF_OFFSET        0x9e8
-#define GC_USB_DIEPINT7_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT7_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT7_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT7_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT7_TXFEMP_OFFSET            0x9e8
-#define GC_USB_DIEPINT7_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT7_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT7_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT7_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT7_TXFIFOUNDRN_OFFSET       0x9e8
-#define GC_USB_DIEPINT7_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT7_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT7_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT7_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT7_BNAINTR_OFFSET           0x9e8
-#define GC_USB_DIEPINT7_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT7_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT7_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT7_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT7_PKTDRPSTS_OFFSET         0x9e8
-#define GC_USB_DIEPINT7_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT7_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT7_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT7_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT7_BBLEERR_OFFSET           0x9e8
-#define GC_USB_DIEPINT7_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT7_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT7_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT7_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT7_NAKINTRPT_OFFSET         0x9e8
-#define GC_USB_DIEPINT7_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT7_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT7_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT7_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT7_NYETINTRPT_OFFSET        0x9e8
-#define GC_USB_DIEPTSIZ7_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ7_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DIEPTSIZ7_XFERSIZE_SIZE           0x13
-#define GC_USB_DIEPTSIZ7_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ7_XFERSIZE_OFFSET         0x9f0
-#define GC_USB_DIEPTSIZ7_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ7_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DIEPTSIZ7_PKTCNT_SIZE             0xa
-#define GC_USB_DIEPTSIZ7_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ7_PKTCNT_OFFSET           0x9f0
-#define GC_USB_DIEPTSIZ7_MC_LSB                  0x1d
-#define GC_USB_DIEPTSIZ7_MC_MASK                 0x60000000
-#define GC_USB_DIEPTSIZ7_MC_SIZE                 0x2
-#define GC_USB_DIEPTSIZ7_MC_DEFAULT              0x0
-#define GC_USB_DIEPTSIZ7_MC_OFFSET               0x9f0
-#define GC_USB_DIEPDMA7_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA7_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA7_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA7_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA7_DMAADDR_OFFSET           0x9f4
-#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS7_INEPTXFSPCAVAIL_OFFSET   0x9f8
-#define GC_USB_DIEPDMAB7_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB7_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB7_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB7_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB7_DMABUFFERADDR_OFFSET    0x9fc
-#define GC_USB_DIEPCTL8_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL8_MPS_MASK                 0x7ff
-#define GC_USB_DIEPCTL8_MPS_SIZE                 0xb
-#define GC_USB_DIEPCTL8_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL8_MPS_OFFSET               0xa00
-#define GC_USB_DIEPCTL8_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL8_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL8_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL8_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL8_USBACTEP_OFFSET          0xa00
-#define GC_USB_DIEPCTL8_DPID_LSB                 0x10
-#define GC_USB_DIEPCTL8_DPID_MASK                0x10000
-#define GC_USB_DIEPCTL8_DPID_SIZE                0x1
-#define GC_USB_DIEPCTL8_DPID_DEFAULT             0x0
-#define GC_USB_DIEPCTL8_DPID_OFFSET              0xa00
-#define GC_USB_DIEPCTL8_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL8_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL8_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL8_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL8_NAKSTS_OFFSET            0xa00
-#define GC_USB_DIEPCTL8_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL8_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL8_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL8_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL8_EPTYPE_OFFSET            0xa00
-#define GC_USB_DIEPCTL8_STALL_LSB                0x15
-#define GC_USB_DIEPCTL8_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL8_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL8_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL8_STALL_OFFSET             0xa00
-#define GC_USB_DIEPCTL8_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL8_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL8_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL8_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL8_TXFNUM_OFFSET            0xa00
-#define GC_USB_DIEPCTL8_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL8_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL8_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL8_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL8_CNAK_OFFSET              0xa00
-#define GC_USB_DIEPCTL8_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL8_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL8_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL8_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL8_SNAK_OFFSET              0xa00
-#define GC_USB_DIEPCTL8_SETD0PID_LSB             0x1c
-#define GC_USB_DIEPCTL8_SETD0PID_MASK            0x10000000
-#define GC_USB_DIEPCTL8_SETD0PID_SIZE            0x1
-#define GC_USB_DIEPCTL8_SETD0PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL8_SETD0PID_OFFSET          0xa00
-#define GC_USB_DIEPCTL8_SETD1PID_LSB             0x1d
-#define GC_USB_DIEPCTL8_SETD1PID_MASK            0x20000000
-#define GC_USB_DIEPCTL8_SETD1PID_SIZE            0x1
-#define GC_USB_DIEPCTL8_SETD1PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL8_SETD1PID_OFFSET          0xa00
-#define GC_USB_DIEPCTL8_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL8_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL8_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL8_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL8_EPDIS_OFFSET             0xa00
-#define GC_USB_DIEPCTL8_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL8_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL8_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL8_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL8_EPENA_OFFSET             0xa00
-#define GC_USB_DIEPINT8_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT8_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT8_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT8_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT8_XFERCOMPL_OFFSET         0xa08
-#define GC_USB_DIEPINT8_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT8_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT8_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT8_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT8_EPDISBLD_OFFSET          0xa08
-#define GC_USB_DIEPINT8_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT8_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT8_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT8_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT8_AHBERR_OFFSET            0xa08
-#define GC_USB_DIEPINT8_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT8_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT8_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT8_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT8_TIMEOUT_OFFSET           0xa08
-#define GC_USB_DIEPINT8_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT8_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT8_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT8_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT8_INTKNTXFEMP_OFFSET       0xa08
-#define GC_USB_DIEPINT8_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT8_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT8_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT8_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT8_INTKNEPMIS_OFFSET        0xa08
-#define GC_USB_DIEPINT8_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT8_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT8_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT8_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT8_INEPNAKEFF_OFFSET        0xa08
-#define GC_USB_DIEPINT8_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT8_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT8_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT8_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT8_TXFEMP_OFFSET            0xa08
-#define GC_USB_DIEPINT8_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT8_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT8_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT8_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT8_TXFIFOUNDRN_OFFSET       0xa08
-#define GC_USB_DIEPINT8_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT8_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT8_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT8_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT8_BNAINTR_OFFSET           0xa08
-#define GC_USB_DIEPINT8_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT8_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT8_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT8_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT8_PKTDRPSTS_OFFSET         0xa08
-#define GC_USB_DIEPINT8_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT8_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT8_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT8_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT8_BBLEERR_OFFSET           0xa08
-#define GC_USB_DIEPINT8_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT8_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT8_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT8_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT8_NAKINTRPT_OFFSET         0xa08
-#define GC_USB_DIEPINT8_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT8_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT8_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT8_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT8_NYETINTRPT_OFFSET        0xa08
-#define GC_USB_DIEPTSIZ8_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ8_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DIEPTSIZ8_XFERSIZE_SIZE           0x13
-#define GC_USB_DIEPTSIZ8_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ8_XFERSIZE_OFFSET         0xa10
-#define GC_USB_DIEPTSIZ8_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ8_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DIEPTSIZ8_PKTCNT_SIZE             0xa
-#define GC_USB_DIEPTSIZ8_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ8_PKTCNT_OFFSET           0xa10
-#define GC_USB_DIEPTSIZ8_MC_LSB                  0x1d
-#define GC_USB_DIEPTSIZ8_MC_MASK                 0x60000000
-#define GC_USB_DIEPTSIZ8_MC_SIZE                 0x2
-#define GC_USB_DIEPTSIZ8_MC_DEFAULT              0x0
-#define GC_USB_DIEPTSIZ8_MC_OFFSET               0xa10
-#define GC_USB_DIEPDMA8_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA8_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA8_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA8_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA8_DMAADDR_OFFSET           0xa14
-#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS8_INEPTXFSPCAVAIL_OFFSET   0xa18
-#define GC_USB_DIEPDMAB8_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB8_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB8_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB8_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB8_DMABUFFERADDR_OFFSET    0xa1c
-#define GC_USB_DIEPCTL9_MPS_LSB                  0x0
-#define GC_USB_DIEPCTL9_MPS_MASK                 0x7ff
-#define GC_USB_DIEPCTL9_MPS_SIZE                 0xb
-#define GC_USB_DIEPCTL9_MPS_DEFAULT              0x0
-#define GC_USB_DIEPCTL9_MPS_OFFSET               0xa20
-#define GC_USB_DIEPCTL9_USBACTEP_LSB             0xf
-#define GC_USB_DIEPCTL9_USBACTEP_MASK            0x8000
-#define GC_USB_DIEPCTL9_USBACTEP_SIZE            0x1
-#define GC_USB_DIEPCTL9_USBACTEP_DEFAULT         0x0
-#define GC_USB_DIEPCTL9_USBACTEP_OFFSET          0xa20
-#define GC_USB_DIEPCTL9_DPID_LSB                 0x10
-#define GC_USB_DIEPCTL9_DPID_MASK                0x10000
-#define GC_USB_DIEPCTL9_DPID_SIZE                0x1
-#define GC_USB_DIEPCTL9_DPID_DEFAULT             0x0
-#define GC_USB_DIEPCTL9_DPID_OFFSET              0xa20
-#define GC_USB_DIEPCTL9_NAKSTS_LSB               0x11
-#define GC_USB_DIEPCTL9_NAKSTS_MASK              0x20000
-#define GC_USB_DIEPCTL9_NAKSTS_SIZE              0x1
-#define GC_USB_DIEPCTL9_NAKSTS_DEFAULT           0x0
-#define GC_USB_DIEPCTL9_NAKSTS_OFFSET            0xa20
-#define GC_USB_DIEPCTL9_EPTYPE_LSB               0x12
-#define GC_USB_DIEPCTL9_EPTYPE_MASK              0xc0000
-#define GC_USB_DIEPCTL9_EPTYPE_SIZE              0x2
-#define GC_USB_DIEPCTL9_EPTYPE_DEFAULT           0x0
-#define GC_USB_DIEPCTL9_EPTYPE_OFFSET            0xa20
-#define GC_USB_DIEPCTL9_STALL_LSB                0x15
-#define GC_USB_DIEPCTL9_STALL_MASK               0x200000
-#define GC_USB_DIEPCTL9_STALL_SIZE               0x1
-#define GC_USB_DIEPCTL9_STALL_DEFAULT            0x0
-#define GC_USB_DIEPCTL9_STALL_OFFSET             0xa20
-#define GC_USB_DIEPCTL9_TXFNUM_LSB               0x16
-#define GC_USB_DIEPCTL9_TXFNUM_MASK              0x3c00000
-#define GC_USB_DIEPCTL9_TXFNUM_SIZE              0x4
-#define GC_USB_DIEPCTL9_TXFNUM_DEFAULT           0x0
-#define GC_USB_DIEPCTL9_TXFNUM_OFFSET            0xa20
-#define GC_USB_DIEPCTL9_CNAK_LSB                 0x1a
-#define GC_USB_DIEPCTL9_CNAK_MASK                0x4000000
-#define GC_USB_DIEPCTL9_CNAK_SIZE                0x1
-#define GC_USB_DIEPCTL9_CNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL9_CNAK_OFFSET              0xa20
-#define GC_USB_DIEPCTL9_SNAK_LSB                 0x1b
-#define GC_USB_DIEPCTL9_SNAK_MASK                0x8000000
-#define GC_USB_DIEPCTL9_SNAK_SIZE                0x1
-#define GC_USB_DIEPCTL9_SNAK_DEFAULT             0x0
-#define GC_USB_DIEPCTL9_SNAK_OFFSET              0xa20
-#define GC_USB_DIEPCTL9_SETD0PID_LSB             0x1c
-#define GC_USB_DIEPCTL9_SETD0PID_MASK            0x10000000
-#define GC_USB_DIEPCTL9_SETD0PID_SIZE            0x1
-#define GC_USB_DIEPCTL9_SETD0PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL9_SETD0PID_OFFSET          0xa20
-#define GC_USB_DIEPCTL9_SETD1PID_LSB             0x1d
-#define GC_USB_DIEPCTL9_SETD1PID_MASK            0x20000000
-#define GC_USB_DIEPCTL9_SETD1PID_SIZE            0x1
-#define GC_USB_DIEPCTL9_SETD1PID_DEFAULT         0x0
-#define GC_USB_DIEPCTL9_SETD1PID_OFFSET          0xa20
-#define GC_USB_DIEPCTL9_EPDIS_LSB                0x1e
-#define GC_USB_DIEPCTL9_EPDIS_MASK               0x40000000
-#define GC_USB_DIEPCTL9_EPDIS_SIZE               0x1
-#define GC_USB_DIEPCTL9_EPDIS_DEFAULT            0x0
-#define GC_USB_DIEPCTL9_EPDIS_OFFSET             0xa20
-#define GC_USB_DIEPCTL9_EPENA_LSB                0x1f
-#define GC_USB_DIEPCTL9_EPENA_MASK               0x80000000
-#define GC_USB_DIEPCTL9_EPENA_SIZE               0x1
-#define GC_USB_DIEPCTL9_EPENA_DEFAULT            0x0
-#define GC_USB_DIEPCTL9_EPENA_OFFSET             0xa20
-#define GC_USB_DIEPINT9_XFERCOMPL_LSB            0x0
-#define GC_USB_DIEPINT9_XFERCOMPL_MASK           0x1
-#define GC_USB_DIEPINT9_XFERCOMPL_SIZE           0x1
-#define GC_USB_DIEPINT9_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DIEPINT9_XFERCOMPL_OFFSET         0xa28
-#define GC_USB_DIEPINT9_EPDISBLD_LSB             0x1
-#define GC_USB_DIEPINT9_EPDISBLD_MASK            0x2
-#define GC_USB_DIEPINT9_EPDISBLD_SIZE            0x1
-#define GC_USB_DIEPINT9_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DIEPINT9_EPDISBLD_OFFSET          0xa28
-#define GC_USB_DIEPINT9_AHBERR_LSB               0x2
-#define GC_USB_DIEPINT9_AHBERR_MASK              0x4
-#define GC_USB_DIEPINT9_AHBERR_SIZE              0x1
-#define GC_USB_DIEPINT9_AHBERR_DEFAULT           0x0
-#define GC_USB_DIEPINT9_AHBERR_OFFSET            0xa28
-#define GC_USB_DIEPINT9_TIMEOUT_LSB              0x3
-#define GC_USB_DIEPINT9_TIMEOUT_MASK             0x8
-#define GC_USB_DIEPINT9_TIMEOUT_SIZE             0x1
-#define GC_USB_DIEPINT9_TIMEOUT_DEFAULT          0x0
-#define GC_USB_DIEPINT9_TIMEOUT_OFFSET           0xa28
-#define GC_USB_DIEPINT9_INTKNTXFEMP_LSB          0x4
-#define GC_USB_DIEPINT9_INTKNTXFEMP_MASK         0x10
-#define GC_USB_DIEPINT9_INTKNTXFEMP_SIZE         0x1
-#define GC_USB_DIEPINT9_INTKNTXFEMP_DEFAULT      0x0
-#define GC_USB_DIEPINT9_INTKNTXFEMP_OFFSET       0xa28
-#define GC_USB_DIEPINT9_INTKNEPMIS_LSB           0x5
-#define GC_USB_DIEPINT9_INTKNEPMIS_MASK          0x20
-#define GC_USB_DIEPINT9_INTKNEPMIS_SIZE          0x1
-#define GC_USB_DIEPINT9_INTKNEPMIS_DEFAULT       0x0
-#define GC_USB_DIEPINT9_INTKNEPMIS_OFFSET        0xa28
-#define GC_USB_DIEPINT9_INEPNAKEFF_LSB           0x6
-#define GC_USB_DIEPINT9_INEPNAKEFF_MASK          0x40
-#define GC_USB_DIEPINT9_INEPNAKEFF_SIZE          0x1
-#define GC_USB_DIEPINT9_INEPNAKEFF_DEFAULT       0x0
-#define GC_USB_DIEPINT9_INEPNAKEFF_OFFSET        0xa28
-#define GC_USB_DIEPINT9_TXFEMP_LSB               0x7
-#define GC_USB_DIEPINT9_TXFEMP_MASK              0x80
-#define GC_USB_DIEPINT9_TXFEMP_SIZE              0x1
-#define GC_USB_DIEPINT9_TXFEMP_DEFAULT           0x0
-#define GC_USB_DIEPINT9_TXFEMP_OFFSET            0xa28
-#define GC_USB_DIEPINT9_TXFIFOUNDRN_LSB          0x8
-#define GC_USB_DIEPINT9_TXFIFOUNDRN_MASK         0x100
-#define GC_USB_DIEPINT9_TXFIFOUNDRN_SIZE         0x1
-#define GC_USB_DIEPINT9_TXFIFOUNDRN_DEFAULT      0x0
-#define GC_USB_DIEPINT9_TXFIFOUNDRN_OFFSET       0xa28
-#define GC_USB_DIEPINT9_BNAINTR_LSB              0x9
-#define GC_USB_DIEPINT9_BNAINTR_MASK             0x200
-#define GC_USB_DIEPINT9_BNAINTR_SIZE             0x1
-#define GC_USB_DIEPINT9_BNAINTR_DEFAULT          0x0
-#define GC_USB_DIEPINT9_BNAINTR_OFFSET           0xa28
-#define GC_USB_DIEPINT9_PKTDRPSTS_LSB            0xb
-#define GC_USB_DIEPINT9_PKTDRPSTS_MASK           0x800
-#define GC_USB_DIEPINT9_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DIEPINT9_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DIEPINT9_PKTDRPSTS_OFFSET         0xa28
-#define GC_USB_DIEPINT9_BBLEERR_LSB              0xc
-#define GC_USB_DIEPINT9_BBLEERR_MASK             0x1000
-#define GC_USB_DIEPINT9_BBLEERR_SIZE             0x1
-#define GC_USB_DIEPINT9_BBLEERR_DEFAULT          0x0
-#define GC_USB_DIEPINT9_BBLEERR_OFFSET           0xa28
-#define GC_USB_DIEPINT9_NAKINTRPT_LSB            0xd
-#define GC_USB_DIEPINT9_NAKINTRPT_MASK           0x2000
-#define GC_USB_DIEPINT9_NAKINTRPT_SIZE           0x1
-#define GC_USB_DIEPINT9_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DIEPINT9_NAKINTRPT_OFFSET         0xa28
-#define GC_USB_DIEPINT9_NYETINTRPT_LSB           0xe
-#define GC_USB_DIEPINT9_NYETINTRPT_MASK          0x4000
-#define GC_USB_DIEPINT9_NYETINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT9_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT9_NYETINTRPT_OFFSET        0xa28
-#define GC_USB_DIEPTSIZ9_XFERSIZE_LSB            0x0
-#define GC_USB_DIEPTSIZ9_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DIEPTSIZ9_XFERSIZE_SIZE           0x13
-#define GC_USB_DIEPTSIZ9_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DIEPTSIZ9_XFERSIZE_OFFSET         0xa30
-#define GC_USB_DIEPTSIZ9_PKTCNT_LSB              0x13
-#define GC_USB_DIEPTSIZ9_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DIEPTSIZ9_PKTCNT_SIZE             0xa
-#define GC_USB_DIEPTSIZ9_PKTCNT_DEFAULT          0x0
-#define GC_USB_DIEPTSIZ9_PKTCNT_OFFSET           0xa30
-#define GC_USB_DIEPTSIZ9_MC_LSB                  0x1d
-#define GC_USB_DIEPTSIZ9_MC_MASK                 0x60000000
-#define GC_USB_DIEPTSIZ9_MC_SIZE                 0x2
-#define GC_USB_DIEPTSIZ9_MC_DEFAULT              0x0
-#define GC_USB_DIEPTSIZ9_MC_OFFSET               0xa30
-#define GC_USB_DIEPDMA9_DMAADDR_LSB              0x0
-#define GC_USB_DIEPDMA9_DMAADDR_MASK             0xffffffff
-#define GC_USB_DIEPDMA9_DMAADDR_SIZE             0x20
-#define GC_USB_DIEPDMA9_DMAADDR_DEFAULT          0x0
-#define GC_USB_DIEPDMA9_DMAADDR_OFFSET           0xa34
-#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_LSB      0x0
-#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_MASK     0xffff
-#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_SIZE     0x10
-#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_DEFAULT  0x0
-#define GC_USB_DTXFSTS9_INEPTXFSPCAVAIL_OFFSET   0xa38
-#define GC_USB_DIEPDMAB9_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DIEPDMAB9_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DIEPDMAB9_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DIEPDMAB9_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DIEPDMAB9_DMABUFFERADDR_OFFSET    0xa3c
-#define GC_USB_DIEPCTL10_MPS_LSB                 0x0
-#define GC_USB_DIEPCTL10_MPS_MASK                0x7ff
-#define GC_USB_DIEPCTL10_MPS_SIZE                0xb
-#define GC_USB_DIEPCTL10_MPS_DEFAULT             0x0
-#define GC_USB_DIEPCTL10_MPS_OFFSET              0xa40
-#define GC_USB_DIEPCTL10_USBACTEP_LSB            0xf
-#define GC_USB_DIEPCTL10_USBACTEP_MASK           0x8000
-#define GC_USB_DIEPCTL10_USBACTEP_SIZE           0x1
-#define GC_USB_DIEPCTL10_USBACTEP_DEFAULT        0x0
-#define GC_USB_DIEPCTL10_USBACTEP_OFFSET         0xa40
-#define GC_USB_DIEPCTL10_DPID_LSB                0x10
-#define GC_USB_DIEPCTL10_DPID_MASK               0x10000
-#define GC_USB_DIEPCTL10_DPID_SIZE               0x1
-#define GC_USB_DIEPCTL10_DPID_DEFAULT            0x0
-#define GC_USB_DIEPCTL10_DPID_OFFSET             0xa40
-#define GC_USB_DIEPCTL10_NAKSTS_LSB              0x11
-#define GC_USB_DIEPCTL10_NAKSTS_MASK             0x20000
-#define GC_USB_DIEPCTL10_NAKSTS_SIZE             0x1
-#define GC_USB_DIEPCTL10_NAKSTS_DEFAULT          0x0
-#define GC_USB_DIEPCTL10_NAKSTS_OFFSET           0xa40
-#define GC_USB_DIEPCTL10_EPTYPE_LSB              0x12
-#define GC_USB_DIEPCTL10_EPTYPE_MASK             0xc0000
-#define GC_USB_DIEPCTL10_EPTYPE_SIZE             0x2
-#define GC_USB_DIEPCTL10_EPTYPE_DEFAULT          0x0
-#define GC_USB_DIEPCTL10_EPTYPE_OFFSET           0xa40
-#define GC_USB_DIEPCTL10_STALL_LSB               0x15
-#define GC_USB_DIEPCTL10_STALL_MASK              0x200000
-#define GC_USB_DIEPCTL10_STALL_SIZE              0x1
-#define GC_USB_DIEPCTL10_STALL_DEFAULT           0x0
-#define GC_USB_DIEPCTL10_STALL_OFFSET            0xa40
-#define GC_USB_DIEPCTL10_TXFNUM_LSB              0x16
-#define GC_USB_DIEPCTL10_TXFNUM_MASK             0x3c00000
-#define GC_USB_DIEPCTL10_TXFNUM_SIZE             0x4
-#define GC_USB_DIEPCTL10_TXFNUM_DEFAULT          0x0
-#define GC_USB_DIEPCTL10_TXFNUM_OFFSET           0xa40
-#define GC_USB_DIEPCTL10_CNAK_LSB                0x1a
-#define GC_USB_DIEPCTL10_CNAK_MASK               0x4000000
-#define GC_USB_DIEPCTL10_CNAK_SIZE               0x1
-#define GC_USB_DIEPCTL10_CNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL10_CNAK_OFFSET             0xa40
-#define GC_USB_DIEPCTL10_SNAK_LSB                0x1b
-#define GC_USB_DIEPCTL10_SNAK_MASK               0x8000000
-#define GC_USB_DIEPCTL10_SNAK_SIZE               0x1
-#define GC_USB_DIEPCTL10_SNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL10_SNAK_OFFSET             0xa40
-#define GC_USB_DIEPCTL10_SETD0PID_LSB            0x1c
-#define GC_USB_DIEPCTL10_SETD0PID_MASK           0x10000000
-#define GC_USB_DIEPCTL10_SETD0PID_SIZE           0x1
-#define GC_USB_DIEPCTL10_SETD0PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL10_SETD0PID_OFFSET         0xa40
-#define GC_USB_DIEPCTL10_SETD1PID_LSB            0x1d
-#define GC_USB_DIEPCTL10_SETD1PID_MASK           0x20000000
-#define GC_USB_DIEPCTL10_SETD1PID_SIZE           0x1
-#define GC_USB_DIEPCTL10_SETD1PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL10_SETD1PID_OFFSET         0xa40
-#define GC_USB_DIEPCTL10_EPDIS_LSB               0x1e
-#define GC_USB_DIEPCTL10_EPDIS_MASK              0x40000000
-#define GC_USB_DIEPCTL10_EPDIS_SIZE              0x1
-#define GC_USB_DIEPCTL10_EPDIS_DEFAULT           0x0
-#define GC_USB_DIEPCTL10_EPDIS_OFFSET            0xa40
-#define GC_USB_DIEPCTL10_EPENA_LSB               0x1f
-#define GC_USB_DIEPCTL10_EPENA_MASK              0x80000000
-#define GC_USB_DIEPCTL10_EPENA_SIZE              0x1
-#define GC_USB_DIEPCTL10_EPENA_DEFAULT           0x0
-#define GC_USB_DIEPCTL10_EPENA_OFFSET            0xa40
-#define GC_USB_DIEPINT10_XFERCOMPL_LSB           0x0
-#define GC_USB_DIEPINT10_XFERCOMPL_MASK          0x1
-#define GC_USB_DIEPINT10_XFERCOMPL_SIZE          0x1
-#define GC_USB_DIEPINT10_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DIEPINT10_XFERCOMPL_OFFSET        0xa48
-#define GC_USB_DIEPINT10_EPDISBLD_LSB            0x1
-#define GC_USB_DIEPINT10_EPDISBLD_MASK           0x2
-#define GC_USB_DIEPINT10_EPDISBLD_SIZE           0x1
-#define GC_USB_DIEPINT10_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DIEPINT10_EPDISBLD_OFFSET         0xa48
-#define GC_USB_DIEPINT10_AHBERR_LSB              0x2
-#define GC_USB_DIEPINT10_AHBERR_MASK             0x4
-#define GC_USB_DIEPINT10_AHBERR_SIZE             0x1
-#define GC_USB_DIEPINT10_AHBERR_DEFAULT          0x0
-#define GC_USB_DIEPINT10_AHBERR_OFFSET           0xa48
-#define GC_USB_DIEPINT10_TIMEOUT_LSB             0x3
-#define GC_USB_DIEPINT10_TIMEOUT_MASK            0x8
-#define GC_USB_DIEPINT10_TIMEOUT_SIZE            0x1
-#define GC_USB_DIEPINT10_TIMEOUT_DEFAULT         0x0
-#define GC_USB_DIEPINT10_TIMEOUT_OFFSET          0xa48
-#define GC_USB_DIEPINT10_INTKNTXFEMP_LSB         0x4
-#define GC_USB_DIEPINT10_INTKNTXFEMP_MASK        0x10
-#define GC_USB_DIEPINT10_INTKNTXFEMP_SIZE        0x1
-#define GC_USB_DIEPINT10_INTKNTXFEMP_DEFAULT     0x0
-#define GC_USB_DIEPINT10_INTKNTXFEMP_OFFSET      0xa48
-#define GC_USB_DIEPINT10_INTKNEPMIS_LSB          0x5
-#define GC_USB_DIEPINT10_INTKNEPMIS_MASK         0x20
-#define GC_USB_DIEPINT10_INTKNEPMIS_SIZE         0x1
-#define GC_USB_DIEPINT10_INTKNEPMIS_DEFAULT      0x0
-#define GC_USB_DIEPINT10_INTKNEPMIS_OFFSET       0xa48
-#define GC_USB_DIEPINT10_INEPNAKEFF_LSB          0x6
-#define GC_USB_DIEPINT10_INEPNAKEFF_MASK         0x40
-#define GC_USB_DIEPINT10_INEPNAKEFF_SIZE         0x1
-#define GC_USB_DIEPINT10_INEPNAKEFF_DEFAULT      0x0
-#define GC_USB_DIEPINT10_INEPNAKEFF_OFFSET       0xa48
-#define GC_USB_DIEPINT10_TXFEMP_LSB              0x7
-#define GC_USB_DIEPINT10_TXFEMP_MASK             0x80
-#define GC_USB_DIEPINT10_TXFEMP_SIZE             0x1
-#define GC_USB_DIEPINT10_TXFEMP_DEFAULT          0x0
-#define GC_USB_DIEPINT10_TXFEMP_OFFSET           0xa48
-#define GC_USB_DIEPINT10_TXFIFOUNDRN_LSB         0x8
-#define GC_USB_DIEPINT10_TXFIFOUNDRN_MASK        0x100
-#define GC_USB_DIEPINT10_TXFIFOUNDRN_SIZE        0x1
-#define GC_USB_DIEPINT10_TXFIFOUNDRN_DEFAULT     0x0
-#define GC_USB_DIEPINT10_TXFIFOUNDRN_OFFSET      0xa48
-#define GC_USB_DIEPINT10_BNAINTR_LSB             0x9
-#define GC_USB_DIEPINT10_BNAINTR_MASK            0x200
-#define GC_USB_DIEPINT10_BNAINTR_SIZE            0x1
-#define GC_USB_DIEPINT10_BNAINTR_DEFAULT         0x0
-#define GC_USB_DIEPINT10_BNAINTR_OFFSET          0xa48
-#define GC_USB_DIEPINT10_PKTDRPSTS_LSB           0xb
-#define GC_USB_DIEPINT10_PKTDRPSTS_MASK          0x800
-#define GC_USB_DIEPINT10_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DIEPINT10_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DIEPINT10_PKTDRPSTS_OFFSET        0xa48
-#define GC_USB_DIEPINT10_BBLEERR_LSB             0xc
-#define GC_USB_DIEPINT10_BBLEERR_MASK            0x1000
-#define GC_USB_DIEPINT10_BBLEERR_SIZE            0x1
-#define GC_USB_DIEPINT10_BBLEERR_DEFAULT         0x0
-#define GC_USB_DIEPINT10_BBLEERR_OFFSET          0xa48
-#define GC_USB_DIEPINT10_NAKINTRPT_LSB           0xd
-#define GC_USB_DIEPINT10_NAKINTRPT_MASK          0x2000
-#define GC_USB_DIEPINT10_NAKINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT10_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT10_NAKINTRPT_OFFSET        0xa48
-#define GC_USB_DIEPINT10_NYETINTRPT_LSB          0xe
-#define GC_USB_DIEPINT10_NYETINTRPT_MASK         0x4000
-#define GC_USB_DIEPINT10_NYETINTRPT_SIZE         0x1
-#define GC_USB_DIEPINT10_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DIEPINT10_NYETINTRPT_OFFSET       0xa48
-#define GC_USB_DIEPTSIZ10_XFERSIZE_LSB           0x0
-#define GC_USB_DIEPTSIZ10_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DIEPTSIZ10_XFERSIZE_SIZE          0x13
-#define GC_USB_DIEPTSIZ10_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DIEPTSIZ10_XFERSIZE_OFFSET        0xa50
-#define GC_USB_DIEPTSIZ10_PKTCNT_LSB             0x13
-#define GC_USB_DIEPTSIZ10_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DIEPTSIZ10_PKTCNT_SIZE            0xa
-#define GC_USB_DIEPTSIZ10_PKTCNT_DEFAULT         0x0
-#define GC_USB_DIEPTSIZ10_PKTCNT_OFFSET          0xa50
-#define GC_USB_DIEPTSIZ10_MC_LSB                 0x1d
-#define GC_USB_DIEPTSIZ10_MC_MASK                0x60000000
-#define GC_USB_DIEPTSIZ10_MC_SIZE                0x2
-#define GC_USB_DIEPTSIZ10_MC_DEFAULT             0x0
-#define GC_USB_DIEPTSIZ10_MC_OFFSET              0xa50
-#define GC_USB_DIEPDMA10_DMAADDR_LSB             0x0
-#define GC_USB_DIEPDMA10_DMAADDR_MASK            0xffffffff
-#define GC_USB_DIEPDMA10_DMAADDR_SIZE            0x20
-#define GC_USB_DIEPDMA10_DMAADDR_DEFAULT         0x0
-#define GC_USB_DIEPDMA10_DMAADDR_OFFSET          0xa54
-#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_LSB     0x0
-#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_MASK    0xffff
-#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_SIZE    0x10
-#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_DEFAULT 0x0
-#define GC_USB_DTXFSTS10_INEPTXFSPCAVAIL_OFFSET  0xa58
-#define GC_USB_DIEPDMAB10_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DIEPDMAB10_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DIEPDMAB10_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DIEPDMAB10_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DIEPDMAB10_DMABUFFERADDR_OFFSET   0xa5c
-#define GC_USB_DIEPCTL11_MPS_LSB                 0x0
-#define GC_USB_DIEPCTL11_MPS_MASK                0x7ff
-#define GC_USB_DIEPCTL11_MPS_SIZE                0xb
-#define GC_USB_DIEPCTL11_MPS_DEFAULT             0x0
-#define GC_USB_DIEPCTL11_MPS_OFFSET              0xa60
-#define GC_USB_DIEPCTL11_USBACTEP_LSB            0xf
-#define GC_USB_DIEPCTL11_USBACTEP_MASK           0x8000
-#define GC_USB_DIEPCTL11_USBACTEP_SIZE           0x1
-#define GC_USB_DIEPCTL11_USBACTEP_DEFAULT        0x0
-#define GC_USB_DIEPCTL11_USBACTEP_OFFSET         0xa60
-#define GC_USB_DIEPCTL11_DPID_LSB                0x10
-#define GC_USB_DIEPCTL11_DPID_MASK               0x10000
-#define GC_USB_DIEPCTL11_DPID_SIZE               0x1
-#define GC_USB_DIEPCTL11_DPID_DEFAULT            0x0
-#define GC_USB_DIEPCTL11_DPID_OFFSET             0xa60
-#define GC_USB_DIEPCTL11_NAKSTS_LSB              0x11
-#define GC_USB_DIEPCTL11_NAKSTS_MASK             0x20000
-#define GC_USB_DIEPCTL11_NAKSTS_SIZE             0x1
-#define GC_USB_DIEPCTL11_NAKSTS_DEFAULT          0x0
-#define GC_USB_DIEPCTL11_NAKSTS_OFFSET           0xa60
-#define GC_USB_DIEPCTL11_EPTYPE_LSB              0x12
-#define GC_USB_DIEPCTL11_EPTYPE_MASK             0xc0000
-#define GC_USB_DIEPCTL11_EPTYPE_SIZE             0x2
-#define GC_USB_DIEPCTL11_EPTYPE_DEFAULT          0x0
-#define GC_USB_DIEPCTL11_EPTYPE_OFFSET           0xa60
-#define GC_USB_DIEPCTL11_STALL_LSB               0x15
-#define GC_USB_DIEPCTL11_STALL_MASK              0x200000
-#define GC_USB_DIEPCTL11_STALL_SIZE              0x1
-#define GC_USB_DIEPCTL11_STALL_DEFAULT           0x0
-#define GC_USB_DIEPCTL11_STALL_OFFSET            0xa60
-#define GC_USB_DIEPCTL11_TXFNUM_LSB              0x16
-#define GC_USB_DIEPCTL11_TXFNUM_MASK             0x3c00000
-#define GC_USB_DIEPCTL11_TXFNUM_SIZE             0x4
-#define GC_USB_DIEPCTL11_TXFNUM_DEFAULT          0x0
-#define GC_USB_DIEPCTL11_TXFNUM_OFFSET           0xa60
-#define GC_USB_DIEPCTL11_CNAK_LSB                0x1a
-#define GC_USB_DIEPCTL11_CNAK_MASK               0x4000000
-#define GC_USB_DIEPCTL11_CNAK_SIZE               0x1
-#define GC_USB_DIEPCTL11_CNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL11_CNAK_OFFSET             0xa60
-#define GC_USB_DIEPCTL11_SNAK_LSB                0x1b
-#define GC_USB_DIEPCTL11_SNAK_MASK               0x8000000
-#define GC_USB_DIEPCTL11_SNAK_SIZE               0x1
-#define GC_USB_DIEPCTL11_SNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL11_SNAK_OFFSET             0xa60
-#define GC_USB_DIEPCTL11_SETD0PID_LSB            0x1c
-#define GC_USB_DIEPCTL11_SETD0PID_MASK           0x10000000
-#define GC_USB_DIEPCTL11_SETD0PID_SIZE           0x1
-#define GC_USB_DIEPCTL11_SETD0PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL11_SETD0PID_OFFSET         0xa60
-#define GC_USB_DIEPCTL11_SETD1PID_LSB            0x1d
-#define GC_USB_DIEPCTL11_SETD1PID_MASK           0x20000000
-#define GC_USB_DIEPCTL11_SETD1PID_SIZE           0x1
-#define GC_USB_DIEPCTL11_SETD1PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL11_SETD1PID_OFFSET         0xa60
-#define GC_USB_DIEPCTL11_EPDIS_LSB               0x1e
-#define GC_USB_DIEPCTL11_EPDIS_MASK              0x40000000
-#define GC_USB_DIEPCTL11_EPDIS_SIZE              0x1
-#define GC_USB_DIEPCTL11_EPDIS_DEFAULT           0x0
-#define GC_USB_DIEPCTL11_EPDIS_OFFSET            0xa60
-#define GC_USB_DIEPCTL11_EPENA_LSB               0x1f
-#define GC_USB_DIEPCTL11_EPENA_MASK              0x80000000
-#define GC_USB_DIEPCTL11_EPENA_SIZE              0x1
-#define GC_USB_DIEPCTL11_EPENA_DEFAULT           0x0
-#define GC_USB_DIEPCTL11_EPENA_OFFSET            0xa60
-#define GC_USB_DIEPINT11_XFERCOMPL_LSB           0x0
-#define GC_USB_DIEPINT11_XFERCOMPL_MASK          0x1
-#define GC_USB_DIEPINT11_XFERCOMPL_SIZE          0x1
-#define GC_USB_DIEPINT11_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DIEPINT11_XFERCOMPL_OFFSET        0xa68
-#define GC_USB_DIEPINT11_EPDISBLD_LSB            0x1
-#define GC_USB_DIEPINT11_EPDISBLD_MASK           0x2
-#define GC_USB_DIEPINT11_EPDISBLD_SIZE           0x1
-#define GC_USB_DIEPINT11_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DIEPINT11_EPDISBLD_OFFSET         0xa68
-#define GC_USB_DIEPINT11_AHBERR_LSB              0x2
-#define GC_USB_DIEPINT11_AHBERR_MASK             0x4
-#define GC_USB_DIEPINT11_AHBERR_SIZE             0x1
-#define GC_USB_DIEPINT11_AHBERR_DEFAULT          0x0
-#define GC_USB_DIEPINT11_AHBERR_OFFSET           0xa68
-#define GC_USB_DIEPINT11_TIMEOUT_LSB             0x3
-#define GC_USB_DIEPINT11_TIMEOUT_MASK            0x8
-#define GC_USB_DIEPINT11_TIMEOUT_SIZE            0x1
-#define GC_USB_DIEPINT11_TIMEOUT_DEFAULT         0x0
-#define GC_USB_DIEPINT11_TIMEOUT_OFFSET          0xa68
-#define GC_USB_DIEPINT11_INTKNTXFEMP_LSB         0x4
-#define GC_USB_DIEPINT11_INTKNTXFEMP_MASK        0x10
-#define GC_USB_DIEPINT11_INTKNTXFEMP_SIZE        0x1
-#define GC_USB_DIEPINT11_INTKNTXFEMP_DEFAULT     0x0
-#define GC_USB_DIEPINT11_INTKNTXFEMP_OFFSET      0xa68
-#define GC_USB_DIEPINT11_INTKNEPMIS_LSB          0x5
-#define GC_USB_DIEPINT11_INTKNEPMIS_MASK         0x20
-#define GC_USB_DIEPINT11_INTKNEPMIS_SIZE         0x1
-#define GC_USB_DIEPINT11_INTKNEPMIS_DEFAULT      0x0
-#define GC_USB_DIEPINT11_INTKNEPMIS_OFFSET       0xa68
-#define GC_USB_DIEPINT11_INEPNAKEFF_LSB          0x6
-#define GC_USB_DIEPINT11_INEPNAKEFF_MASK         0x40
-#define GC_USB_DIEPINT11_INEPNAKEFF_SIZE         0x1
-#define GC_USB_DIEPINT11_INEPNAKEFF_DEFAULT      0x0
-#define GC_USB_DIEPINT11_INEPNAKEFF_OFFSET       0xa68
-#define GC_USB_DIEPINT11_TXFEMP_LSB              0x7
-#define GC_USB_DIEPINT11_TXFEMP_MASK             0x80
-#define GC_USB_DIEPINT11_TXFEMP_SIZE             0x1
-#define GC_USB_DIEPINT11_TXFEMP_DEFAULT          0x0
-#define GC_USB_DIEPINT11_TXFEMP_OFFSET           0xa68
-#define GC_USB_DIEPINT11_TXFIFOUNDRN_LSB         0x8
-#define GC_USB_DIEPINT11_TXFIFOUNDRN_MASK        0x100
-#define GC_USB_DIEPINT11_TXFIFOUNDRN_SIZE        0x1
-#define GC_USB_DIEPINT11_TXFIFOUNDRN_DEFAULT     0x0
-#define GC_USB_DIEPINT11_TXFIFOUNDRN_OFFSET      0xa68
-#define GC_USB_DIEPINT11_BNAINTR_LSB             0x9
-#define GC_USB_DIEPINT11_BNAINTR_MASK            0x200
-#define GC_USB_DIEPINT11_BNAINTR_SIZE            0x1
-#define GC_USB_DIEPINT11_BNAINTR_DEFAULT         0x0
-#define GC_USB_DIEPINT11_BNAINTR_OFFSET          0xa68
-#define GC_USB_DIEPINT11_PKTDRPSTS_LSB           0xb
-#define GC_USB_DIEPINT11_PKTDRPSTS_MASK          0x800
-#define GC_USB_DIEPINT11_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DIEPINT11_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DIEPINT11_PKTDRPSTS_OFFSET        0xa68
-#define GC_USB_DIEPINT11_BBLEERR_LSB             0xc
-#define GC_USB_DIEPINT11_BBLEERR_MASK            0x1000
-#define GC_USB_DIEPINT11_BBLEERR_SIZE            0x1
-#define GC_USB_DIEPINT11_BBLEERR_DEFAULT         0x0
-#define GC_USB_DIEPINT11_BBLEERR_OFFSET          0xa68
-#define GC_USB_DIEPINT11_NAKINTRPT_LSB           0xd
-#define GC_USB_DIEPINT11_NAKINTRPT_MASK          0x2000
-#define GC_USB_DIEPINT11_NAKINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT11_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT11_NAKINTRPT_OFFSET        0xa68
-#define GC_USB_DIEPINT11_NYETINTRPT_LSB          0xe
-#define GC_USB_DIEPINT11_NYETINTRPT_MASK         0x4000
-#define GC_USB_DIEPINT11_NYETINTRPT_SIZE         0x1
-#define GC_USB_DIEPINT11_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DIEPINT11_NYETINTRPT_OFFSET       0xa68
-#define GC_USB_DIEPTSIZ11_XFERSIZE_LSB           0x0
-#define GC_USB_DIEPTSIZ11_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DIEPTSIZ11_XFERSIZE_SIZE          0x13
-#define GC_USB_DIEPTSIZ11_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DIEPTSIZ11_XFERSIZE_OFFSET        0xa70
-#define GC_USB_DIEPTSIZ11_PKTCNT_LSB             0x13
-#define GC_USB_DIEPTSIZ11_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DIEPTSIZ11_PKTCNT_SIZE            0xa
-#define GC_USB_DIEPTSIZ11_PKTCNT_DEFAULT         0x0
-#define GC_USB_DIEPTSIZ11_PKTCNT_OFFSET          0xa70
-#define GC_USB_DIEPTSIZ11_MC_LSB                 0x1d
-#define GC_USB_DIEPTSIZ11_MC_MASK                0x60000000
-#define GC_USB_DIEPTSIZ11_MC_SIZE                0x2
-#define GC_USB_DIEPTSIZ11_MC_DEFAULT             0x0
-#define GC_USB_DIEPTSIZ11_MC_OFFSET              0xa70
-#define GC_USB_DIEPDMA11_DMAADDR_LSB             0x0
-#define GC_USB_DIEPDMA11_DMAADDR_MASK            0xffffffff
-#define GC_USB_DIEPDMA11_DMAADDR_SIZE            0x20
-#define GC_USB_DIEPDMA11_DMAADDR_DEFAULT         0x0
-#define GC_USB_DIEPDMA11_DMAADDR_OFFSET          0xa74
-#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_LSB     0x0
-#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_MASK    0xffff
-#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_SIZE    0x10
-#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_DEFAULT 0x0
-#define GC_USB_DTXFSTS11_INEPTXFSPCAVAIL_OFFSET  0xa78
-#define GC_USB_DIEPDMAB11_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DIEPDMAB11_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DIEPDMAB11_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DIEPDMAB11_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DIEPDMAB11_DMABUFFERADDR_OFFSET   0xa7c
-#define GC_USB_DIEPCTL12_MPS_LSB                 0x0
-#define GC_USB_DIEPCTL12_MPS_MASK                0x7ff
-#define GC_USB_DIEPCTL12_MPS_SIZE                0xb
-#define GC_USB_DIEPCTL12_MPS_DEFAULT             0x0
-#define GC_USB_DIEPCTL12_MPS_OFFSET              0xa80
-#define GC_USB_DIEPCTL12_USBACTEP_LSB            0xf
-#define GC_USB_DIEPCTL12_USBACTEP_MASK           0x8000
-#define GC_USB_DIEPCTL12_USBACTEP_SIZE           0x1
-#define GC_USB_DIEPCTL12_USBACTEP_DEFAULT        0x0
-#define GC_USB_DIEPCTL12_USBACTEP_OFFSET         0xa80
-#define GC_USB_DIEPCTL12_DPID_LSB                0x10
-#define GC_USB_DIEPCTL12_DPID_MASK               0x10000
-#define GC_USB_DIEPCTL12_DPID_SIZE               0x1
-#define GC_USB_DIEPCTL12_DPID_DEFAULT            0x0
-#define GC_USB_DIEPCTL12_DPID_OFFSET             0xa80
-#define GC_USB_DIEPCTL12_NAKSTS_LSB              0x11
-#define GC_USB_DIEPCTL12_NAKSTS_MASK             0x20000
-#define GC_USB_DIEPCTL12_NAKSTS_SIZE             0x1
-#define GC_USB_DIEPCTL12_NAKSTS_DEFAULT          0x0
-#define GC_USB_DIEPCTL12_NAKSTS_OFFSET           0xa80
-#define GC_USB_DIEPCTL12_EPTYPE_LSB              0x12
-#define GC_USB_DIEPCTL12_EPTYPE_MASK             0xc0000
-#define GC_USB_DIEPCTL12_EPTYPE_SIZE             0x2
-#define GC_USB_DIEPCTL12_EPTYPE_DEFAULT          0x0
-#define GC_USB_DIEPCTL12_EPTYPE_OFFSET           0xa80
-#define GC_USB_DIEPCTL12_STALL_LSB               0x15
-#define GC_USB_DIEPCTL12_STALL_MASK              0x200000
-#define GC_USB_DIEPCTL12_STALL_SIZE              0x1
-#define GC_USB_DIEPCTL12_STALL_DEFAULT           0x0
-#define GC_USB_DIEPCTL12_STALL_OFFSET            0xa80
-#define GC_USB_DIEPCTL12_TXFNUM_LSB              0x16
-#define GC_USB_DIEPCTL12_TXFNUM_MASK             0x3c00000
-#define GC_USB_DIEPCTL12_TXFNUM_SIZE             0x4
-#define GC_USB_DIEPCTL12_TXFNUM_DEFAULT          0x0
-#define GC_USB_DIEPCTL12_TXFNUM_OFFSET           0xa80
-#define GC_USB_DIEPCTL12_CNAK_LSB                0x1a
-#define GC_USB_DIEPCTL12_CNAK_MASK               0x4000000
-#define GC_USB_DIEPCTL12_CNAK_SIZE               0x1
-#define GC_USB_DIEPCTL12_CNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL12_CNAK_OFFSET             0xa80
-#define GC_USB_DIEPCTL12_SNAK_LSB                0x1b
-#define GC_USB_DIEPCTL12_SNAK_MASK               0x8000000
-#define GC_USB_DIEPCTL12_SNAK_SIZE               0x1
-#define GC_USB_DIEPCTL12_SNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL12_SNAK_OFFSET             0xa80
-#define GC_USB_DIEPCTL12_SETD0PID_LSB            0x1c
-#define GC_USB_DIEPCTL12_SETD0PID_MASK           0x10000000
-#define GC_USB_DIEPCTL12_SETD0PID_SIZE           0x1
-#define GC_USB_DIEPCTL12_SETD0PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL12_SETD0PID_OFFSET         0xa80
-#define GC_USB_DIEPCTL12_SETD1PID_LSB            0x1d
-#define GC_USB_DIEPCTL12_SETD1PID_MASK           0x20000000
-#define GC_USB_DIEPCTL12_SETD1PID_SIZE           0x1
-#define GC_USB_DIEPCTL12_SETD1PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL12_SETD1PID_OFFSET         0xa80
-#define GC_USB_DIEPCTL12_EPDIS_LSB               0x1e
-#define GC_USB_DIEPCTL12_EPDIS_MASK              0x40000000
-#define GC_USB_DIEPCTL12_EPDIS_SIZE              0x1
-#define GC_USB_DIEPCTL12_EPDIS_DEFAULT           0x0
-#define GC_USB_DIEPCTL12_EPDIS_OFFSET            0xa80
-#define GC_USB_DIEPCTL12_EPENA_LSB               0x1f
-#define GC_USB_DIEPCTL12_EPENA_MASK              0x80000000
-#define GC_USB_DIEPCTL12_EPENA_SIZE              0x1
-#define GC_USB_DIEPCTL12_EPENA_DEFAULT           0x0
-#define GC_USB_DIEPCTL12_EPENA_OFFSET            0xa80
-#define GC_USB_DIEPINT12_XFERCOMPL_LSB           0x0
-#define GC_USB_DIEPINT12_XFERCOMPL_MASK          0x1
-#define GC_USB_DIEPINT12_XFERCOMPL_SIZE          0x1
-#define GC_USB_DIEPINT12_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DIEPINT12_XFERCOMPL_OFFSET        0xa88
-#define GC_USB_DIEPINT12_EPDISBLD_LSB            0x1
-#define GC_USB_DIEPINT12_EPDISBLD_MASK           0x2
-#define GC_USB_DIEPINT12_EPDISBLD_SIZE           0x1
-#define GC_USB_DIEPINT12_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DIEPINT12_EPDISBLD_OFFSET         0xa88
-#define GC_USB_DIEPINT12_AHBERR_LSB              0x2
-#define GC_USB_DIEPINT12_AHBERR_MASK             0x4
-#define GC_USB_DIEPINT12_AHBERR_SIZE             0x1
-#define GC_USB_DIEPINT12_AHBERR_DEFAULT          0x0
-#define GC_USB_DIEPINT12_AHBERR_OFFSET           0xa88
-#define GC_USB_DIEPINT12_TIMEOUT_LSB             0x3
-#define GC_USB_DIEPINT12_TIMEOUT_MASK            0x8
-#define GC_USB_DIEPINT12_TIMEOUT_SIZE            0x1
-#define GC_USB_DIEPINT12_TIMEOUT_DEFAULT         0x0
-#define GC_USB_DIEPINT12_TIMEOUT_OFFSET          0xa88
-#define GC_USB_DIEPINT12_INTKNTXFEMP_LSB         0x4
-#define GC_USB_DIEPINT12_INTKNTXFEMP_MASK        0x10
-#define GC_USB_DIEPINT12_INTKNTXFEMP_SIZE        0x1
-#define GC_USB_DIEPINT12_INTKNTXFEMP_DEFAULT     0x0
-#define GC_USB_DIEPINT12_INTKNTXFEMP_OFFSET      0xa88
-#define GC_USB_DIEPINT12_INTKNEPMIS_LSB          0x5
-#define GC_USB_DIEPINT12_INTKNEPMIS_MASK         0x20
-#define GC_USB_DIEPINT12_INTKNEPMIS_SIZE         0x1
-#define GC_USB_DIEPINT12_INTKNEPMIS_DEFAULT      0x0
-#define GC_USB_DIEPINT12_INTKNEPMIS_OFFSET       0xa88
-#define GC_USB_DIEPINT12_INEPNAKEFF_LSB          0x6
-#define GC_USB_DIEPINT12_INEPNAKEFF_MASK         0x40
-#define GC_USB_DIEPINT12_INEPNAKEFF_SIZE         0x1
-#define GC_USB_DIEPINT12_INEPNAKEFF_DEFAULT      0x0
-#define GC_USB_DIEPINT12_INEPNAKEFF_OFFSET       0xa88
-#define GC_USB_DIEPINT12_TXFEMP_LSB              0x7
-#define GC_USB_DIEPINT12_TXFEMP_MASK             0x80
-#define GC_USB_DIEPINT12_TXFEMP_SIZE             0x1
-#define GC_USB_DIEPINT12_TXFEMP_DEFAULT          0x0
-#define GC_USB_DIEPINT12_TXFEMP_OFFSET           0xa88
-#define GC_USB_DIEPINT12_TXFIFOUNDRN_LSB         0x8
-#define GC_USB_DIEPINT12_TXFIFOUNDRN_MASK        0x100
-#define GC_USB_DIEPINT12_TXFIFOUNDRN_SIZE        0x1
-#define GC_USB_DIEPINT12_TXFIFOUNDRN_DEFAULT     0x0
-#define GC_USB_DIEPINT12_TXFIFOUNDRN_OFFSET      0xa88
-#define GC_USB_DIEPINT12_BNAINTR_LSB             0x9
-#define GC_USB_DIEPINT12_BNAINTR_MASK            0x200
-#define GC_USB_DIEPINT12_BNAINTR_SIZE            0x1
-#define GC_USB_DIEPINT12_BNAINTR_DEFAULT         0x0
-#define GC_USB_DIEPINT12_BNAINTR_OFFSET          0xa88
-#define GC_USB_DIEPINT12_PKTDRPSTS_LSB           0xb
-#define GC_USB_DIEPINT12_PKTDRPSTS_MASK          0x800
-#define GC_USB_DIEPINT12_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DIEPINT12_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DIEPINT12_PKTDRPSTS_OFFSET        0xa88
-#define GC_USB_DIEPINT12_BBLEERR_LSB             0xc
-#define GC_USB_DIEPINT12_BBLEERR_MASK            0x1000
-#define GC_USB_DIEPINT12_BBLEERR_SIZE            0x1
-#define GC_USB_DIEPINT12_BBLEERR_DEFAULT         0x0
-#define GC_USB_DIEPINT12_BBLEERR_OFFSET          0xa88
-#define GC_USB_DIEPINT12_NAKINTRPT_LSB           0xd
-#define GC_USB_DIEPINT12_NAKINTRPT_MASK          0x2000
-#define GC_USB_DIEPINT12_NAKINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT12_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT12_NAKINTRPT_OFFSET        0xa88
-#define GC_USB_DIEPINT12_NYETINTRPT_LSB          0xe
-#define GC_USB_DIEPINT12_NYETINTRPT_MASK         0x4000
-#define GC_USB_DIEPINT12_NYETINTRPT_SIZE         0x1
-#define GC_USB_DIEPINT12_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DIEPINT12_NYETINTRPT_OFFSET       0xa88
-#define GC_USB_DIEPTSIZ12_XFERSIZE_LSB           0x0
-#define GC_USB_DIEPTSIZ12_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DIEPTSIZ12_XFERSIZE_SIZE          0x13
-#define GC_USB_DIEPTSIZ12_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DIEPTSIZ12_XFERSIZE_OFFSET        0xa90
-#define GC_USB_DIEPTSIZ12_PKTCNT_LSB             0x13
-#define GC_USB_DIEPTSIZ12_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DIEPTSIZ12_PKTCNT_SIZE            0xa
-#define GC_USB_DIEPTSIZ12_PKTCNT_DEFAULT         0x0
-#define GC_USB_DIEPTSIZ12_PKTCNT_OFFSET          0xa90
-#define GC_USB_DIEPTSIZ12_MC_LSB                 0x1d
-#define GC_USB_DIEPTSIZ12_MC_MASK                0x60000000
-#define GC_USB_DIEPTSIZ12_MC_SIZE                0x2
-#define GC_USB_DIEPTSIZ12_MC_DEFAULT             0x0
-#define GC_USB_DIEPTSIZ12_MC_OFFSET              0xa90
-#define GC_USB_DIEPDMA12_DMAADDR_LSB             0x0
-#define GC_USB_DIEPDMA12_DMAADDR_MASK            0xffffffff
-#define GC_USB_DIEPDMA12_DMAADDR_SIZE            0x20
-#define GC_USB_DIEPDMA12_DMAADDR_DEFAULT         0x0
-#define GC_USB_DIEPDMA12_DMAADDR_OFFSET          0xa94
-#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_LSB     0x0
-#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_MASK    0xffff
-#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_SIZE    0x10
-#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_DEFAULT 0x0
-#define GC_USB_DTXFSTS12_INEPTXFSPCAVAIL_OFFSET  0xa98
-#define GC_USB_DIEPDMAB12_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DIEPDMAB12_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DIEPDMAB12_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DIEPDMAB12_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DIEPDMAB12_DMABUFFERADDR_OFFSET   0xa9c
-#define GC_USB_DIEPCTL13_MPS_LSB                 0x0
-#define GC_USB_DIEPCTL13_MPS_MASK                0x7ff
-#define GC_USB_DIEPCTL13_MPS_SIZE                0xb
-#define GC_USB_DIEPCTL13_MPS_DEFAULT             0x0
-#define GC_USB_DIEPCTL13_MPS_OFFSET              0xaa0
-#define GC_USB_DIEPCTL13_USBACTEP_LSB            0xf
-#define GC_USB_DIEPCTL13_USBACTEP_MASK           0x8000
-#define GC_USB_DIEPCTL13_USBACTEP_SIZE           0x1
-#define GC_USB_DIEPCTL13_USBACTEP_DEFAULT        0x0
-#define GC_USB_DIEPCTL13_USBACTEP_OFFSET         0xaa0
-#define GC_USB_DIEPCTL13_DPID_LSB                0x10
-#define GC_USB_DIEPCTL13_DPID_MASK               0x10000
-#define GC_USB_DIEPCTL13_DPID_SIZE               0x1
-#define GC_USB_DIEPCTL13_DPID_DEFAULT            0x0
-#define GC_USB_DIEPCTL13_DPID_OFFSET             0xaa0
-#define GC_USB_DIEPCTL13_NAKSTS_LSB              0x11
-#define GC_USB_DIEPCTL13_NAKSTS_MASK             0x20000
-#define GC_USB_DIEPCTL13_NAKSTS_SIZE             0x1
-#define GC_USB_DIEPCTL13_NAKSTS_DEFAULT          0x0
-#define GC_USB_DIEPCTL13_NAKSTS_OFFSET           0xaa0
-#define GC_USB_DIEPCTL13_EPTYPE_LSB              0x12
-#define GC_USB_DIEPCTL13_EPTYPE_MASK             0xc0000
-#define GC_USB_DIEPCTL13_EPTYPE_SIZE             0x2
-#define GC_USB_DIEPCTL13_EPTYPE_DEFAULT          0x0
-#define GC_USB_DIEPCTL13_EPTYPE_OFFSET           0xaa0
-#define GC_USB_DIEPCTL13_STALL_LSB               0x15
-#define GC_USB_DIEPCTL13_STALL_MASK              0x200000
-#define GC_USB_DIEPCTL13_STALL_SIZE              0x1
-#define GC_USB_DIEPCTL13_STALL_DEFAULT           0x0
-#define GC_USB_DIEPCTL13_STALL_OFFSET            0xaa0
-#define GC_USB_DIEPCTL13_TXFNUM_LSB              0x16
-#define GC_USB_DIEPCTL13_TXFNUM_MASK             0x3c00000
-#define GC_USB_DIEPCTL13_TXFNUM_SIZE             0x4
-#define GC_USB_DIEPCTL13_TXFNUM_DEFAULT          0x0
-#define GC_USB_DIEPCTL13_TXFNUM_OFFSET           0xaa0
-#define GC_USB_DIEPCTL13_CNAK_LSB                0x1a
-#define GC_USB_DIEPCTL13_CNAK_MASK               0x4000000
-#define GC_USB_DIEPCTL13_CNAK_SIZE               0x1
-#define GC_USB_DIEPCTL13_CNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL13_CNAK_OFFSET             0xaa0
-#define GC_USB_DIEPCTL13_SNAK_LSB                0x1b
-#define GC_USB_DIEPCTL13_SNAK_MASK               0x8000000
-#define GC_USB_DIEPCTL13_SNAK_SIZE               0x1
-#define GC_USB_DIEPCTL13_SNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL13_SNAK_OFFSET             0xaa0
-#define GC_USB_DIEPCTL13_SETD0PID_LSB            0x1c
-#define GC_USB_DIEPCTL13_SETD0PID_MASK           0x10000000
-#define GC_USB_DIEPCTL13_SETD0PID_SIZE           0x1
-#define GC_USB_DIEPCTL13_SETD0PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL13_SETD0PID_OFFSET         0xaa0
-#define GC_USB_DIEPCTL13_SETD1PID_LSB            0x1d
-#define GC_USB_DIEPCTL13_SETD1PID_MASK           0x20000000
-#define GC_USB_DIEPCTL13_SETD1PID_SIZE           0x1
-#define GC_USB_DIEPCTL13_SETD1PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL13_SETD1PID_OFFSET         0xaa0
-#define GC_USB_DIEPCTL13_EPDIS_LSB               0x1e
-#define GC_USB_DIEPCTL13_EPDIS_MASK              0x40000000
-#define GC_USB_DIEPCTL13_EPDIS_SIZE              0x1
-#define GC_USB_DIEPCTL13_EPDIS_DEFAULT           0x0
-#define GC_USB_DIEPCTL13_EPDIS_OFFSET            0xaa0
-#define GC_USB_DIEPCTL13_EPENA_LSB               0x1f
-#define GC_USB_DIEPCTL13_EPENA_MASK              0x80000000
-#define GC_USB_DIEPCTL13_EPENA_SIZE              0x1
-#define GC_USB_DIEPCTL13_EPENA_DEFAULT           0x0
-#define GC_USB_DIEPCTL13_EPENA_OFFSET            0xaa0
-#define GC_USB_DIEPINT13_XFERCOMPL_LSB           0x0
-#define GC_USB_DIEPINT13_XFERCOMPL_MASK          0x1
-#define GC_USB_DIEPINT13_XFERCOMPL_SIZE          0x1
-#define GC_USB_DIEPINT13_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DIEPINT13_XFERCOMPL_OFFSET        0xaa8
-#define GC_USB_DIEPINT13_EPDISBLD_LSB            0x1
-#define GC_USB_DIEPINT13_EPDISBLD_MASK           0x2
-#define GC_USB_DIEPINT13_EPDISBLD_SIZE           0x1
-#define GC_USB_DIEPINT13_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DIEPINT13_EPDISBLD_OFFSET         0xaa8
-#define GC_USB_DIEPINT13_AHBERR_LSB              0x2
-#define GC_USB_DIEPINT13_AHBERR_MASK             0x4
-#define GC_USB_DIEPINT13_AHBERR_SIZE             0x1
-#define GC_USB_DIEPINT13_AHBERR_DEFAULT          0x0
-#define GC_USB_DIEPINT13_AHBERR_OFFSET           0xaa8
-#define GC_USB_DIEPINT13_TIMEOUT_LSB             0x3
-#define GC_USB_DIEPINT13_TIMEOUT_MASK            0x8
-#define GC_USB_DIEPINT13_TIMEOUT_SIZE            0x1
-#define GC_USB_DIEPINT13_TIMEOUT_DEFAULT         0x0
-#define GC_USB_DIEPINT13_TIMEOUT_OFFSET          0xaa8
-#define GC_USB_DIEPINT13_INTKNTXFEMP_LSB         0x4
-#define GC_USB_DIEPINT13_INTKNTXFEMP_MASK        0x10
-#define GC_USB_DIEPINT13_INTKNTXFEMP_SIZE        0x1
-#define GC_USB_DIEPINT13_INTKNTXFEMP_DEFAULT     0x0
-#define GC_USB_DIEPINT13_INTKNTXFEMP_OFFSET      0xaa8
-#define GC_USB_DIEPINT13_INTKNEPMIS_LSB          0x5
-#define GC_USB_DIEPINT13_INTKNEPMIS_MASK         0x20
-#define GC_USB_DIEPINT13_INTKNEPMIS_SIZE         0x1
-#define GC_USB_DIEPINT13_INTKNEPMIS_DEFAULT      0x0
-#define GC_USB_DIEPINT13_INTKNEPMIS_OFFSET       0xaa8
-#define GC_USB_DIEPINT13_INEPNAKEFF_LSB          0x6
-#define GC_USB_DIEPINT13_INEPNAKEFF_MASK         0x40
-#define GC_USB_DIEPINT13_INEPNAKEFF_SIZE         0x1
-#define GC_USB_DIEPINT13_INEPNAKEFF_DEFAULT      0x0
-#define GC_USB_DIEPINT13_INEPNAKEFF_OFFSET       0xaa8
-#define GC_USB_DIEPINT13_TXFEMP_LSB              0x7
-#define GC_USB_DIEPINT13_TXFEMP_MASK             0x80
-#define GC_USB_DIEPINT13_TXFEMP_SIZE             0x1
-#define GC_USB_DIEPINT13_TXFEMP_DEFAULT          0x0
-#define GC_USB_DIEPINT13_TXFEMP_OFFSET           0xaa8
-#define GC_USB_DIEPINT13_TXFIFOUNDRN_LSB         0x8
-#define GC_USB_DIEPINT13_TXFIFOUNDRN_MASK        0x100
-#define GC_USB_DIEPINT13_TXFIFOUNDRN_SIZE        0x1
-#define GC_USB_DIEPINT13_TXFIFOUNDRN_DEFAULT     0x0
-#define GC_USB_DIEPINT13_TXFIFOUNDRN_OFFSET      0xaa8
-#define GC_USB_DIEPINT13_BNAINTR_LSB             0x9
-#define GC_USB_DIEPINT13_BNAINTR_MASK            0x200
-#define GC_USB_DIEPINT13_BNAINTR_SIZE            0x1
-#define GC_USB_DIEPINT13_BNAINTR_DEFAULT         0x0
-#define GC_USB_DIEPINT13_BNAINTR_OFFSET          0xaa8
-#define GC_USB_DIEPINT13_PKTDRPSTS_LSB           0xb
-#define GC_USB_DIEPINT13_PKTDRPSTS_MASK          0x800
-#define GC_USB_DIEPINT13_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DIEPINT13_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DIEPINT13_PKTDRPSTS_OFFSET        0xaa8
-#define GC_USB_DIEPINT13_BBLEERR_LSB             0xc
-#define GC_USB_DIEPINT13_BBLEERR_MASK            0x1000
-#define GC_USB_DIEPINT13_BBLEERR_SIZE            0x1
-#define GC_USB_DIEPINT13_BBLEERR_DEFAULT         0x0
-#define GC_USB_DIEPINT13_BBLEERR_OFFSET          0xaa8
-#define GC_USB_DIEPINT13_NAKINTRPT_LSB           0xd
-#define GC_USB_DIEPINT13_NAKINTRPT_MASK          0x2000
-#define GC_USB_DIEPINT13_NAKINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT13_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT13_NAKINTRPT_OFFSET        0xaa8
-#define GC_USB_DIEPINT13_NYETINTRPT_LSB          0xe
-#define GC_USB_DIEPINT13_NYETINTRPT_MASK         0x4000
-#define GC_USB_DIEPINT13_NYETINTRPT_SIZE         0x1
-#define GC_USB_DIEPINT13_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DIEPINT13_NYETINTRPT_OFFSET       0xaa8
-#define GC_USB_DIEPTSIZ13_XFERSIZE_LSB           0x0
-#define GC_USB_DIEPTSIZ13_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DIEPTSIZ13_XFERSIZE_SIZE          0x13
-#define GC_USB_DIEPTSIZ13_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DIEPTSIZ13_XFERSIZE_OFFSET        0xab0
-#define GC_USB_DIEPTSIZ13_PKTCNT_LSB             0x13
-#define GC_USB_DIEPTSIZ13_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DIEPTSIZ13_PKTCNT_SIZE            0xa
-#define GC_USB_DIEPTSIZ13_PKTCNT_DEFAULT         0x0
-#define GC_USB_DIEPTSIZ13_PKTCNT_OFFSET          0xab0
-#define GC_USB_DIEPTSIZ13_MC_LSB                 0x1d
-#define GC_USB_DIEPTSIZ13_MC_MASK                0x60000000
-#define GC_USB_DIEPTSIZ13_MC_SIZE                0x2
-#define GC_USB_DIEPTSIZ13_MC_DEFAULT             0x0
-#define GC_USB_DIEPTSIZ13_MC_OFFSET              0xab0
-#define GC_USB_DIEPDMA13_DMAADDR_LSB             0x0
-#define GC_USB_DIEPDMA13_DMAADDR_MASK            0xffffffff
-#define GC_USB_DIEPDMA13_DMAADDR_SIZE            0x20
-#define GC_USB_DIEPDMA13_DMAADDR_DEFAULT         0x0
-#define GC_USB_DIEPDMA13_DMAADDR_OFFSET          0xab4
-#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_LSB     0x0
-#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_MASK    0xffff
-#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_SIZE    0x10
-#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_DEFAULT 0x0
-#define GC_USB_DTXFSTS13_INEPTXFSPCAVAIL_OFFSET  0xab8
-#define GC_USB_DIEPDMAB13_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DIEPDMAB13_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DIEPDMAB13_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DIEPDMAB13_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DIEPDMAB13_DMABUFFERADDR_OFFSET   0xabc
-#define GC_USB_DIEPCTL14_MPS_LSB                 0x0
-#define GC_USB_DIEPCTL14_MPS_MASK                0x7ff
-#define GC_USB_DIEPCTL14_MPS_SIZE                0xb
-#define GC_USB_DIEPCTL14_MPS_DEFAULT             0x0
-#define GC_USB_DIEPCTL14_MPS_OFFSET              0xac0
-#define GC_USB_DIEPCTL14_USBACTEP_LSB            0xf
-#define GC_USB_DIEPCTL14_USBACTEP_MASK           0x8000
-#define GC_USB_DIEPCTL14_USBACTEP_SIZE           0x1
-#define GC_USB_DIEPCTL14_USBACTEP_DEFAULT        0x0
-#define GC_USB_DIEPCTL14_USBACTEP_OFFSET         0xac0
-#define GC_USB_DIEPCTL14_DPID_LSB                0x10
-#define GC_USB_DIEPCTL14_DPID_MASK               0x10000
-#define GC_USB_DIEPCTL14_DPID_SIZE               0x1
-#define GC_USB_DIEPCTL14_DPID_DEFAULT            0x0
-#define GC_USB_DIEPCTL14_DPID_OFFSET             0xac0
-#define GC_USB_DIEPCTL14_NAKSTS_LSB              0x11
-#define GC_USB_DIEPCTL14_NAKSTS_MASK             0x20000
-#define GC_USB_DIEPCTL14_NAKSTS_SIZE             0x1
-#define GC_USB_DIEPCTL14_NAKSTS_DEFAULT          0x0
-#define GC_USB_DIEPCTL14_NAKSTS_OFFSET           0xac0
-#define GC_USB_DIEPCTL14_EPTYPE_LSB              0x12
-#define GC_USB_DIEPCTL14_EPTYPE_MASK             0xc0000
-#define GC_USB_DIEPCTL14_EPTYPE_SIZE             0x2
-#define GC_USB_DIEPCTL14_EPTYPE_DEFAULT          0x0
-#define GC_USB_DIEPCTL14_EPTYPE_OFFSET           0xac0
-#define GC_USB_DIEPCTL14_STALL_LSB               0x15
-#define GC_USB_DIEPCTL14_STALL_MASK              0x200000
-#define GC_USB_DIEPCTL14_STALL_SIZE              0x1
-#define GC_USB_DIEPCTL14_STALL_DEFAULT           0x0
-#define GC_USB_DIEPCTL14_STALL_OFFSET            0xac0
-#define GC_USB_DIEPCTL14_TXFNUM_LSB              0x16
-#define GC_USB_DIEPCTL14_TXFNUM_MASK             0x3c00000
-#define GC_USB_DIEPCTL14_TXFNUM_SIZE             0x4
-#define GC_USB_DIEPCTL14_TXFNUM_DEFAULT          0x0
-#define GC_USB_DIEPCTL14_TXFNUM_OFFSET           0xac0
-#define GC_USB_DIEPCTL14_CNAK_LSB                0x1a
-#define GC_USB_DIEPCTL14_CNAK_MASK               0x4000000
-#define GC_USB_DIEPCTL14_CNAK_SIZE               0x1
-#define GC_USB_DIEPCTL14_CNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL14_CNAK_OFFSET             0xac0
-#define GC_USB_DIEPCTL14_SNAK_LSB                0x1b
-#define GC_USB_DIEPCTL14_SNAK_MASK               0x8000000
-#define GC_USB_DIEPCTL14_SNAK_SIZE               0x1
-#define GC_USB_DIEPCTL14_SNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL14_SNAK_OFFSET             0xac0
-#define GC_USB_DIEPCTL14_SETD0PID_LSB            0x1c
-#define GC_USB_DIEPCTL14_SETD0PID_MASK           0x10000000
-#define GC_USB_DIEPCTL14_SETD0PID_SIZE           0x1
-#define GC_USB_DIEPCTL14_SETD0PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL14_SETD0PID_OFFSET         0xac0
-#define GC_USB_DIEPCTL14_SETD1PID_LSB            0x1d
-#define GC_USB_DIEPCTL14_SETD1PID_MASK           0x20000000
-#define GC_USB_DIEPCTL14_SETD1PID_SIZE           0x1
-#define GC_USB_DIEPCTL14_SETD1PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL14_SETD1PID_OFFSET         0xac0
-#define GC_USB_DIEPCTL14_EPDIS_LSB               0x1e
-#define GC_USB_DIEPCTL14_EPDIS_MASK              0x40000000
-#define GC_USB_DIEPCTL14_EPDIS_SIZE              0x1
-#define GC_USB_DIEPCTL14_EPDIS_DEFAULT           0x0
-#define GC_USB_DIEPCTL14_EPDIS_OFFSET            0xac0
-#define GC_USB_DIEPCTL14_EPENA_LSB               0x1f
-#define GC_USB_DIEPCTL14_EPENA_MASK              0x80000000
-#define GC_USB_DIEPCTL14_EPENA_SIZE              0x1
-#define GC_USB_DIEPCTL14_EPENA_DEFAULT           0x0
-#define GC_USB_DIEPCTL14_EPENA_OFFSET            0xac0
-#define GC_USB_DIEPINT14_XFERCOMPL_LSB           0x0
-#define GC_USB_DIEPINT14_XFERCOMPL_MASK          0x1
-#define GC_USB_DIEPINT14_XFERCOMPL_SIZE          0x1
-#define GC_USB_DIEPINT14_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DIEPINT14_XFERCOMPL_OFFSET        0xac8
-#define GC_USB_DIEPINT14_EPDISBLD_LSB            0x1
-#define GC_USB_DIEPINT14_EPDISBLD_MASK           0x2
-#define GC_USB_DIEPINT14_EPDISBLD_SIZE           0x1
-#define GC_USB_DIEPINT14_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DIEPINT14_EPDISBLD_OFFSET         0xac8
-#define GC_USB_DIEPINT14_AHBERR_LSB              0x2
-#define GC_USB_DIEPINT14_AHBERR_MASK             0x4
-#define GC_USB_DIEPINT14_AHBERR_SIZE             0x1
-#define GC_USB_DIEPINT14_AHBERR_DEFAULT          0x0
-#define GC_USB_DIEPINT14_AHBERR_OFFSET           0xac8
-#define GC_USB_DIEPINT14_TIMEOUT_LSB             0x3
-#define GC_USB_DIEPINT14_TIMEOUT_MASK            0x8
-#define GC_USB_DIEPINT14_TIMEOUT_SIZE            0x1
-#define GC_USB_DIEPINT14_TIMEOUT_DEFAULT         0x0
-#define GC_USB_DIEPINT14_TIMEOUT_OFFSET          0xac8
-#define GC_USB_DIEPINT14_INTKNTXFEMP_LSB         0x4
-#define GC_USB_DIEPINT14_INTKNTXFEMP_MASK        0x10
-#define GC_USB_DIEPINT14_INTKNTXFEMP_SIZE        0x1
-#define GC_USB_DIEPINT14_INTKNTXFEMP_DEFAULT     0x0
-#define GC_USB_DIEPINT14_INTKNTXFEMP_OFFSET      0xac8
-#define GC_USB_DIEPINT14_INTKNEPMIS_LSB          0x5
-#define GC_USB_DIEPINT14_INTKNEPMIS_MASK         0x20
-#define GC_USB_DIEPINT14_INTKNEPMIS_SIZE         0x1
-#define GC_USB_DIEPINT14_INTKNEPMIS_DEFAULT      0x0
-#define GC_USB_DIEPINT14_INTKNEPMIS_OFFSET       0xac8
-#define GC_USB_DIEPINT14_INEPNAKEFF_LSB          0x6
-#define GC_USB_DIEPINT14_INEPNAKEFF_MASK         0x40
-#define GC_USB_DIEPINT14_INEPNAKEFF_SIZE         0x1
-#define GC_USB_DIEPINT14_INEPNAKEFF_DEFAULT      0x0
-#define GC_USB_DIEPINT14_INEPNAKEFF_OFFSET       0xac8
-#define GC_USB_DIEPINT14_TXFEMP_LSB              0x7
-#define GC_USB_DIEPINT14_TXFEMP_MASK             0x80
-#define GC_USB_DIEPINT14_TXFEMP_SIZE             0x1
-#define GC_USB_DIEPINT14_TXFEMP_DEFAULT          0x0
-#define GC_USB_DIEPINT14_TXFEMP_OFFSET           0xac8
-#define GC_USB_DIEPINT14_TXFIFOUNDRN_LSB         0x8
-#define GC_USB_DIEPINT14_TXFIFOUNDRN_MASK        0x100
-#define GC_USB_DIEPINT14_TXFIFOUNDRN_SIZE        0x1
-#define GC_USB_DIEPINT14_TXFIFOUNDRN_DEFAULT     0x0
-#define GC_USB_DIEPINT14_TXFIFOUNDRN_OFFSET      0xac8
-#define GC_USB_DIEPINT14_BNAINTR_LSB             0x9
-#define GC_USB_DIEPINT14_BNAINTR_MASK            0x200
-#define GC_USB_DIEPINT14_BNAINTR_SIZE            0x1
-#define GC_USB_DIEPINT14_BNAINTR_DEFAULT         0x0
-#define GC_USB_DIEPINT14_BNAINTR_OFFSET          0xac8
-#define GC_USB_DIEPINT14_PKTDRPSTS_LSB           0xb
-#define GC_USB_DIEPINT14_PKTDRPSTS_MASK          0x800
-#define GC_USB_DIEPINT14_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DIEPINT14_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DIEPINT14_PKTDRPSTS_OFFSET        0xac8
-#define GC_USB_DIEPINT14_BBLEERR_LSB             0xc
-#define GC_USB_DIEPINT14_BBLEERR_MASK            0x1000
-#define GC_USB_DIEPINT14_BBLEERR_SIZE            0x1
-#define GC_USB_DIEPINT14_BBLEERR_DEFAULT         0x0
-#define GC_USB_DIEPINT14_BBLEERR_OFFSET          0xac8
-#define GC_USB_DIEPINT14_NAKINTRPT_LSB           0xd
-#define GC_USB_DIEPINT14_NAKINTRPT_MASK          0x2000
-#define GC_USB_DIEPINT14_NAKINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT14_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT14_NAKINTRPT_OFFSET        0xac8
-#define GC_USB_DIEPINT14_NYETINTRPT_LSB          0xe
-#define GC_USB_DIEPINT14_NYETINTRPT_MASK         0x4000
-#define GC_USB_DIEPINT14_NYETINTRPT_SIZE         0x1
-#define GC_USB_DIEPINT14_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DIEPINT14_NYETINTRPT_OFFSET       0xac8
-#define GC_USB_DIEPTSIZ14_XFERSIZE_LSB           0x0
-#define GC_USB_DIEPTSIZ14_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DIEPTSIZ14_XFERSIZE_SIZE          0x13
-#define GC_USB_DIEPTSIZ14_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DIEPTSIZ14_XFERSIZE_OFFSET        0xad0
-#define GC_USB_DIEPTSIZ14_PKTCNT_LSB             0x13
-#define GC_USB_DIEPTSIZ14_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DIEPTSIZ14_PKTCNT_SIZE            0xa
-#define GC_USB_DIEPTSIZ14_PKTCNT_DEFAULT         0x0
-#define GC_USB_DIEPTSIZ14_PKTCNT_OFFSET          0xad0
-#define GC_USB_DIEPTSIZ14_MC_LSB                 0x1d
-#define GC_USB_DIEPTSIZ14_MC_MASK                0x60000000
-#define GC_USB_DIEPTSIZ14_MC_SIZE                0x2
-#define GC_USB_DIEPTSIZ14_MC_DEFAULT             0x0
-#define GC_USB_DIEPTSIZ14_MC_OFFSET              0xad0
-#define GC_USB_DIEPDMA14_DMAADDR_LSB             0x0
-#define GC_USB_DIEPDMA14_DMAADDR_MASK            0xffffffff
-#define GC_USB_DIEPDMA14_DMAADDR_SIZE            0x20
-#define GC_USB_DIEPDMA14_DMAADDR_DEFAULT         0x0
-#define GC_USB_DIEPDMA14_DMAADDR_OFFSET          0xad4
-#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_LSB     0x0
-#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_MASK    0xffff
-#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_SIZE    0x10
-#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_DEFAULT 0x0
-#define GC_USB_DTXFSTS14_INEPTXFSPCAVAIL_OFFSET  0xad8
-#define GC_USB_DIEPDMAB14_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DIEPDMAB14_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DIEPDMAB14_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DIEPDMAB14_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DIEPDMAB14_DMABUFFERADDR_OFFSET   0xadc
-#define GC_USB_DIEPCTL15_MPS_LSB                 0x0
-#define GC_USB_DIEPCTL15_MPS_MASK                0x7ff
-#define GC_USB_DIEPCTL15_MPS_SIZE                0xb
-#define GC_USB_DIEPCTL15_MPS_DEFAULT             0x0
-#define GC_USB_DIEPCTL15_MPS_OFFSET              0xae0
-#define GC_USB_DIEPCTL15_USBACTEP_LSB            0xf
-#define GC_USB_DIEPCTL15_USBACTEP_MASK           0x8000
-#define GC_USB_DIEPCTL15_USBACTEP_SIZE           0x1
-#define GC_USB_DIEPCTL15_USBACTEP_DEFAULT        0x0
-#define GC_USB_DIEPCTL15_USBACTEP_OFFSET         0xae0
-#define GC_USB_DIEPCTL15_DPID_LSB                0x10
-#define GC_USB_DIEPCTL15_DPID_MASK               0x10000
-#define GC_USB_DIEPCTL15_DPID_SIZE               0x1
-#define GC_USB_DIEPCTL15_DPID_DEFAULT            0x0
-#define GC_USB_DIEPCTL15_DPID_OFFSET             0xae0
-#define GC_USB_DIEPCTL15_NAKSTS_LSB              0x11
-#define GC_USB_DIEPCTL15_NAKSTS_MASK             0x20000
-#define GC_USB_DIEPCTL15_NAKSTS_SIZE             0x1
-#define GC_USB_DIEPCTL15_NAKSTS_DEFAULT          0x0
-#define GC_USB_DIEPCTL15_NAKSTS_OFFSET           0xae0
-#define GC_USB_DIEPCTL15_EPTYPE_LSB              0x12
-#define GC_USB_DIEPCTL15_EPTYPE_MASK             0xc0000
-#define GC_USB_DIEPCTL15_EPTYPE_SIZE             0x2
-#define GC_USB_DIEPCTL15_EPTYPE_DEFAULT          0x0
-#define GC_USB_DIEPCTL15_EPTYPE_OFFSET           0xae0
-#define GC_USB_DIEPCTL15_STALL_LSB               0x15
-#define GC_USB_DIEPCTL15_STALL_MASK              0x200000
-#define GC_USB_DIEPCTL15_STALL_SIZE              0x1
-#define GC_USB_DIEPCTL15_STALL_DEFAULT           0x0
-#define GC_USB_DIEPCTL15_STALL_OFFSET            0xae0
-#define GC_USB_DIEPCTL15_TXFNUM_LSB              0x16
-#define GC_USB_DIEPCTL15_TXFNUM_MASK             0x3c00000
-#define GC_USB_DIEPCTL15_TXFNUM_SIZE             0x4
-#define GC_USB_DIEPCTL15_TXFNUM_DEFAULT          0x0
-#define GC_USB_DIEPCTL15_TXFNUM_OFFSET           0xae0
-#define GC_USB_DIEPCTL15_CNAK_LSB                0x1a
-#define GC_USB_DIEPCTL15_CNAK_MASK               0x4000000
-#define GC_USB_DIEPCTL15_CNAK_SIZE               0x1
-#define GC_USB_DIEPCTL15_CNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL15_CNAK_OFFSET             0xae0
-#define GC_USB_DIEPCTL15_SNAK_LSB                0x1b
-#define GC_USB_DIEPCTL15_SNAK_MASK               0x8000000
-#define GC_USB_DIEPCTL15_SNAK_SIZE               0x1
-#define GC_USB_DIEPCTL15_SNAK_DEFAULT            0x0
-#define GC_USB_DIEPCTL15_SNAK_OFFSET             0xae0
-#define GC_USB_DIEPCTL15_SETD0PID_LSB            0x1c
-#define GC_USB_DIEPCTL15_SETD0PID_MASK           0x10000000
-#define GC_USB_DIEPCTL15_SETD0PID_SIZE           0x1
-#define GC_USB_DIEPCTL15_SETD0PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL15_SETD0PID_OFFSET         0xae0
-#define GC_USB_DIEPCTL15_SETD1PID_LSB            0x1d
-#define GC_USB_DIEPCTL15_SETD1PID_MASK           0x20000000
-#define GC_USB_DIEPCTL15_SETD1PID_SIZE           0x1
-#define GC_USB_DIEPCTL15_SETD1PID_DEFAULT        0x0
-#define GC_USB_DIEPCTL15_SETD1PID_OFFSET         0xae0
-#define GC_USB_DIEPCTL15_EPDIS_LSB               0x1e
-#define GC_USB_DIEPCTL15_EPDIS_MASK              0x40000000
-#define GC_USB_DIEPCTL15_EPDIS_SIZE              0x1
-#define GC_USB_DIEPCTL15_EPDIS_DEFAULT           0x0
-#define GC_USB_DIEPCTL15_EPDIS_OFFSET            0xae0
-#define GC_USB_DIEPCTL15_EPENA_LSB               0x1f
-#define GC_USB_DIEPCTL15_EPENA_MASK              0x80000000
-#define GC_USB_DIEPCTL15_EPENA_SIZE              0x1
-#define GC_USB_DIEPCTL15_EPENA_DEFAULT           0x0
-#define GC_USB_DIEPCTL15_EPENA_OFFSET            0xae0
-#define GC_USB_DIEPINT15_XFERCOMPL_LSB           0x0
-#define GC_USB_DIEPINT15_XFERCOMPL_MASK          0x1
-#define GC_USB_DIEPINT15_XFERCOMPL_SIZE          0x1
-#define GC_USB_DIEPINT15_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DIEPINT15_XFERCOMPL_OFFSET        0xae8
-#define GC_USB_DIEPINT15_EPDISBLD_LSB            0x1
-#define GC_USB_DIEPINT15_EPDISBLD_MASK           0x2
-#define GC_USB_DIEPINT15_EPDISBLD_SIZE           0x1
-#define GC_USB_DIEPINT15_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DIEPINT15_EPDISBLD_OFFSET         0xae8
-#define GC_USB_DIEPINT15_AHBERR_LSB              0x2
-#define GC_USB_DIEPINT15_AHBERR_MASK             0x4
-#define GC_USB_DIEPINT15_AHBERR_SIZE             0x1
-#define GC_USB_DIEPINT15_AHBERR_DEFAULT          0x0
-#define GC_USB_DIEPINT15_AHBERR_OFFSET           0xae8
-#define GC_USB_DIEPINT15_TIMEOUT_LSB             0x3
-#define GC_USB_DIEPINT15_TIMEOUT_MASK            0x8
-#define GC_USB_DIEPINT15_TIMEOUT_SIZE            0x1
-#define GC_USB_DIEPINT15_TIMEOUT_DEFAULT         0x0
-#define GC_USB_DIEPINT15_TIMEOUT_OFFSET          0xae8
-#define GC_USB_DIEPINT15_INTKNTXFEMP_LSB         0x4
-#define GC_USB_DIEPINT15_INTKNTXFEMP_MASK        0x10
-#define GC_USB_DIEPINT15_INTKNTXFEMP_SIZE        0x1
-#define GC_USB_DIEPINT15_INTKNTXFEMP_DEFAULT     0x0
-#define GC_USB_DIEPINT15_INTKNTXFEMP_OFFSET      0xae8
-#define GC_USB_DIEPINT15_INTKNEPMIS_LSB          0x5
-#define GC_USB_DIEPINT15_INTKNEPMIS_MASK         0x20
-#define GC_USB_DIEPINT15_INTKNEPMIS_SIZE         0x1
-#define GC_USB_DIEPINT15_INTKNEPMIS_DEFAULT      0x0
-#define GC_USB_DIEPINT15_INTKNEPMIS_OFFSET       0xae8
-#define GC_USB_DIEPINT15_INEPNAKEFF_LSB          0x6
-#define GC_USB_DIEPINT15_INEPNAKEFF_MASK         0x40
-#define GC_USB_DIEPINT15_INEPNAKEFF_SIZE         0x1
-#define GC_USB_DIEPINT15_INEPNAKEFF_DEFAULT      0x0
-#define GC_USB_DIEPINT15_INEPNAKEFF_OFFSET       0xae8
-#define GC_USB_DIEPINT15_TXFEMP_LSB              0x7
-#define GC_USB_DIEPINT15_TXFEMP_MASK             0x80
-#define GC_USB_DIEPINT15_TXFEMP_SIZE             0x1
-#define GC_USB_DIEPINT15_TXFEMP_DEFAULT          0x0
-#define GC_USB_DIEPINT15_TXFEMP_OFFSET           0xae8
-#define GC_USB_DIEPINT15_TXFIFOUNDRN_LSB         0x8
-#define GC_USB_DIEPINT15_TXFIFOUNDRN_MASK        0x100
-#define GC_USB_DIEPINT15_TXFIFOUNDRN_SIZE        0x1
-#define GC_USB_DIEPINT15_TXFIFOUNDRN_DEFAULT     0x0
-#define GC_USB_DIEPINT15_TXFIFOUNDRN_OFFSET      0xae8
-#define GC_USB_DIEPINT15_BNAINTR_LSB             0x9
-#define GC_USB_DIEPINT15_BNAINTR_MASK            0x200
-#define GC_USB_DIEPINT15_BNAINTR_SIZE            0x1
-#define GC_USB_DIEPINT15_BNAINTR_DEFAULT         0x0
-#define GC_USB_DIEPINT15_BNAINTR_OFFSET          0xae8
-#define GC_USB_DIEPINT15_PKTDRPSTS_LSB           0xb
-#define GC_USB_DIEPINT15_PKTDRPSTS_MASK          0x800
-#define GC_USB_DIEPINT15_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DIEPINT15_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DIEPINT15_PKTDRPSTS_OFFSET        0xae8
-#define GC_USB_DIEPINT15_BBLEERR_LSB             0xc
-#define GC_USB_DIEPINT15_BBLEERR_MASK            0x1000
-#define GC_USB_DIEPINT15_BBLEERR_SIZE            0x1
-#define GC_USB_DIEPINT15_BBLEERR_DEFAULT         0x0
-#define GC_USB_DIEPINT15_BBLEERR_OFFSET          0xae8
-#define GC_USB_DIEPINT15_NAKINTRPT_LSB           0xd
-#define GC_USB_DIEPINT15_NAKINTRPT_MASK          0x2000
-#define GC_USB_DIEPINT15_NAKINTRPT_SIZE          0x1
-#define GC_USB_DIEPINT15_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DIEPINT15_NAKINTRPT_OFFSET        0xae8
-#define GC_USB_DIEPINT15_NYETINTRPT_LSB          0xe
-#define GC_USB_DIEPINT15_NYETINTRPT_MASK         0x4000
-#define GC_USB_DIEPINT15_NYETINTRPT_SIZE         0x1
-#define GC_USB_DIEPINT15_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DIEPINT15_NYETINTRPT_OFFSET       0xae8
-#define GC_USB_DIEPTSIZ15_XFERSIZE_LSB           0x0
-#define GC_USB_DIEPTSIZ15_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DIEPTSIZ15_XFERSIZE_SIZE          0x13
-#define GC_USB_DIEPTSIZ15_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DIEPTSIZ15_XFERSIZE_OFFSET        0xaf0
-#define GC_USB_DIEPTSIZ15_PKTCNT_LSB             0x13
-#define GC_USB_DIEPTSIZ15_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DIEPTSIZ15_PKTCNT_SIZE            0xa
-#define GC_USB_DIEPTSIZ15_PKTCNT_DEFAULT         0x0
-#define GC_USB_DIEPTSIZ15_PKTCNT_OFFSET          0xaf0
-#define GC_USB_DIEPTSIZ15_MC_LSB                 0x1d
-#define GC_USB_DIEPTSIZ15_MC_MASK                0x60000000
-#define GC_USB_DIEPTSIZ15_MC_SIZE                0x2
-#define GC_USB_DIEPTSIZ15_MC_DEFAULT             0x0
-#define GC_USB_DIEPTSIZ15_MC_OFFSET              0xaf0
-#define GC_USB_DIEPDMA15_DMAADDR_LSB             0x0
-#define GC_USB_DIEPDMA15_DMAADDR_MASK            0xffffffff
-#define GC_USB_DIEPDMA15_DMAADDR_SIZE            0x20
-#define GC_USB_DIEPDMA15_DMAADDR_DEFAULT         0x0
-#define GC_USB_DIEPDMA15_DMAADDR_OFFSET          0xaf4
-#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_LSB     0x0
-#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_MASK    0xffff
-#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_SIZE    0x10
-#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_DEFAULT 0x0
-#define GC_USB_DTXFSTS15_INEPTXFSPCAVAIL_OFFSET  0xaf8
-#define GC_USB_DIEPDMAB15_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DIEPDMAB15_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DIEPDMAB15_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DIEPDMAB15_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DIEPDMAB15_DMABUFFERADDR_OFFSET   0xafc
-#define GC_USB_DOEPCTL0_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL0_MPS_MASK                 0x3
-#define GC_USB_DOEPCTL0_MPS_SIZE                 0x2
-#define GC_USB_DOEPCTL0_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL0_MPS_OFFSET               0xb00
-#define GC_USB_DOEPCTL0_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL0_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL0_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL0_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL0_USBACTEP_OFFSET          0xb00
-#define GC_USB_DOEPCTL0_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL0_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL0_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL0_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL0_NAKSTS_OFFSET            0xb00
-#define GC_USB_DOEPCTL0_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL0_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL0_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL0_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL0_EPTYPE_OFFSET            0xb00
-#define GC_USB_DOEPCTL0_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL0_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL0_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL0_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL0_SNP_OFFSET               0xb00
-#define GC_USB_DOEPCTL0_STALL_LSB                0x15
-#define GC_USB_DOEPCTL0_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL0_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL0_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL0_STALL_OFFSET             0xb00
-#define GC_USB_DOEPCTL0_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL0_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL0_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL0_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL0_CNAK_OFFSET              0xb00
-#define GC_USB_DOEPCTL0_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL0_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL0_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL0_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL0_SNAK_OFFSET              0xb00
-#define GC_USB_DOEPCTL0_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL0_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL0_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL0_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL0_EPDIS_OFFSET             0xb00
-#define GC_USB_DOEPCTL0_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL0_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL0_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL0_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL0_EPENA_OFFSET             0xb00
-#define GC_USB_DOEPINT0_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT0_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT0_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT0_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT0_XFERCOMPL_OFFSET         0xb08
-#define GC_USB_DOEPINT0_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT0_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT0_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT0_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT0_EPDISBLD_OFFSET          0xb08
-#define GC_USB_DOEPINT0_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT0_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT0_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT0_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT0_AHBERR_OFFSET            0xb08
-#define GC_USB_DOEPINT0_SETUP_LSB                0x3
-#define GC_USB_DOEPINT0_SETUP_MASK               0x8
-#define GC_USB_DOEPINT0_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT0_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT0_SETUP_OFFSET             0xb08
-#define GC_USB_DOEPINT0_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT0_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT0_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT0_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT0_OUTTKNEPDIS_OFFSET       0xb08
-#define GC_USB_DOEPINT0_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT0_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT0_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT0_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT0_STSPHSERCVD_OFFSET       0xb08
-#define GC_USB_DOEPINT0_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT0_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT0_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT0_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT0_BACK2BACKSETUP_OFFSET    0xb08
-#define GC_USB_DOEPINT0_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT0_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT0_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT0_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT0_OUTPKTERR_OFFSET         0xb08
-#define GC_USB_DOEPINT0_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT0_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT0_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT0_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT0_BNAINTR_OFFSET           0xb08
-#define GC_USB_DOEPINT0_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT0_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT0_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT0_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT0_PKTDRPSTS_OFFSET         0xb08
-#define GC_USB_DOEPINT0_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT0_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT0_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT0_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT0_BBLEERR_OFFSET           0xb08
-#define GC_USB_DOEPINT0_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT0_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT0_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT0_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT0_NAKINTRPT_OFFSET         0xb08
-#define GC_USB_DOEPINT0_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT0_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT0_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT0_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT0_NYETINTRPT_OFFSET        0xb08
-#define GC_USB_DOEPINT0_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT0_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT0_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT0_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT0_STUPPKTRCVD_OFFSET       0xb08
-#define GC_USB_DOEPTSIZ0_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ0_XFERSIZE_MASK           0x7f
-#define GC_USB_DOEPTSIZ0_XFERSIZE_SIZE           0x7
-#define GC_USB_DOEPTSIZ0_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ0_XFERSIZE_OFFSET         0xb10
-#define GC_USB_DOEPTSIZ0_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ0_PKTCNT_MASK             0x80000
-#define GC_USB_DOEPTSIZ0_PKTCNT_SIZE             0x1
-#define GC_USB_DOEPTSIZ0_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ0_PKTCNT_OFFSET           0xb10
-#define GC_USB_DOEPTSIZ0_SUPCNT_LSB              0x1d
-#define GC_USB_DOEPTSIZ0_SUPCNT_MASK             0x60000000
-#define GC_USB_DOEPTSIZ0_SUPCNT_SIZE             0x2
-#define GC_USB_DOEPTSIZ0_SUPCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ0_SUPCNT_OFFSET           0xb10
-#define GC_USB_DOEPDMA0_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA0_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA0_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA0_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA0_DMAADDR_OFFSET           0xb14
-#define GC_USB_DOEPDMAB0_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB0_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB0_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB0_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB0_DMABUFFERADDR_OFFSET    0xb1c
-#define GC_USB_DOEPCTL1_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL1_MPS_MASK                 0x7ff
-#define GC_USB_DOEPCTL1_MPS_SIZE                 0xb
-#define GC_USB_DOEPCTL1_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL1_MPS_OFFSET               0xb20
-#define GC_USB_DOEPCTL1_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL1_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL1_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL1_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL1_USBACTEP_OFFSET          0xb20
-#define GC_USB_DOEPCTL1_DPID_LSB                 0x10
-#define GC_USB_DOEPCTL1_DPID_MASK                0x10000
-#define GC_USB_DOEPCTL1_DPID_SIZE                0x1
-#define GC_USB_DOEPCTL1_DPID_DEFAULT             0x0
-#define GC_USB_DOEPCTL1_DPID_OFFSET              0xb20
-#define GC_USB_DOEPCTL1_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL1_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL1_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL1_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL1_NAKSTS_OFFSET            0xb20
-#define GC_USB_DOEPCTL1_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL1_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL1_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL1_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL1_EPTYPE_OFFSET            0xb20
-#define GC_USB_DOEPCTL1_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL1_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL1_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL1_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL1_SNP_OFFSET               0xb20
-#define GC_USB_DOEPCTL1_STALL_LSB                0x15
-#define GC_USB_DOEPCTL1_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL1_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL1_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL1_STALL_OFFSET             0xb20
-#define GC_USB_DOEPCTL1_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL1_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL1_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL1_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL1_CNAK_OFFSET              0xb20
-#define GC_USB_DOEPCTL1_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL1_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL1_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL1_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL1_SNAK_OFFSET              0xb20
-#define GC_USB_DOEPCTL1_SETD0PID_LSB             0x1c
-#define GC_USB_DOEPCTL1_SETD0PID_MASK            0x10000000
-#define GC_USB_DOEPCTL1_SETD0PID_SIZE            0x1
-#define GC_USB_DOEPCTL1_SETD0PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL1_SETD0PID_OFFSET          0xb20
-#define GC_USB_DOEPCTL1_SETD1PID_LSB             0x1d
-#define GC_USB_DOEPCTL1_SETD1PID_MASK            0x20000000
-#define GC_USB_DOEPCTL1_SETD1PID_SIZE            0x1
-#define GC_USB_DOEPCTL1_SETD1PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL1_SETD1PID_OFFSET          0xb20
-#define GC_USB_DOEPCTL1_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL1_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL1_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL1_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL1_EPDIS_OFFSET             0xb20
-#define GC_USB_DOEPCTL1_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL1_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL1_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL1_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL1_EPENA_OFFSET             0xb20
-#define GC_USB_DOEPINT1_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT1_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT1_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT1_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT1_XFERCOMPL_OFFSET         0xb28
-#define GC_USB_DOEPINT1_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT1_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT1_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT1_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT1_EPDISBLD_OFFSET          0xb28
-#define GC_USB_DOEPINT1_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT1_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT1_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT1_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT1_AHBERR_OFFSET            0xb28
-#define GC_USB_DOEPINT1_SETUP_LSB                0x3
-#define GC_USB_DOEPINT1_SETUP_MASK               0x8
-#define GC_USB_DOEPINT1_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT1_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT1_SETUP_OFFSET             0xb28
-#define GC_USB_DOEPINT1_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT1_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT1_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT1_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT1_OUTTKNEPDIS_OFFSET       0xb28
-#define GC_USB_DOEPINT1_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT1_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT1_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT1_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT1_STSPHSERCVD_OFFSET       0xb28
-#define GC_USB_DOEPINT1_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT1_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT1_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT1_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT1_BACK2BACKSETUP_OFFSET    0xb28
-#define GC_USB_DOEPINT1_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT1_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT1_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT1_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT1_OUTPKTERR_OFFSET         0xb28
-#define GC_USB_DOEPINT1_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT1_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT1_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT1_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT1_BNAINTR_OFFSET           0xb28
-#define GC_USB_DOEPINT1_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT1_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT1_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT1_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT1_PKTDRPSTS_OFFSET         0xb28
-#define GC_USB_DOEPINT1_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT1_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT1_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT1_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT1_BBLEERR_OFFSET           0xb28
-#define GC_USB_DOEPINT1_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT1_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT1_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT1_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT1_NAKINTRPT_OFFSET         0xb28
-#define GC_USB_DOEPINT1_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT1_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT1_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT1_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT1_NYETINTRPT_OFFSET        0xb28
-#define GC_USB_DOEPINT1_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT1_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT1_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT1_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT1_STUPPKTRCVD_OFFSET       0xb28
-#define GC_USB_DOEPTSIZ1_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ1_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DOEPTSIZ1_XFERSIZE_SIZE           0x13
-#define GC_USB_DOEPTSIZ1_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ1_XFERSIZE_OFFSET         0xb30
-#define GC_USB_DOEPTSIZ1_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ1_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DOEPTSIZ1_PKTCNT_SIZE             0xa
-#define GC_USB_DOEPTSIZ1_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ1_PKTCNT_OFFSET           0xb30
-#define GC_USB_DOEPTSIZ1_RXDPID_LSB              0x1d
-#define GC_USB_DOEPTSIZ1_RXDPID_MASK             0x60000000
-#define GC_USB_DOEPTSIZ1_RXDPID_SIZE             0x2
-#define GC_USB_DOEPTSIZ1_RXDPID_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ1_RXDPID_OFFSET           0xb30
-#define GC_USB_DOEPDMA1_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA1_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA1_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA1_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA1_DMAADDR_OFFSET           0xb34
-#define GC_USB_DOEPDMAB1_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB1_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB1_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB1_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB1_DMABUFFERADDR_OFFSET    0xb3c
-#define GC_USB_DOEPCTL2_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL2_MPS_MASK                 0x7ff
-#define GC_USB_DOEPCTL2_MPS_SIZE                 0xb
-#define GC_USB_DOEPCTL2_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL2_MPS_OFFSET               0xb40
-#define GC_USB_DOEPCTL2_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL2_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL2_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL2_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL2_USBACTEP_OFFSET          0xb40
-#define GC_USB_DOEPCTL2_DPID_LSB                 0x10
-#define GC_USB_DOEPCTL2_DPID_MASK                0x10000
-#define GC_USB_DOEPCTL2_DPID_SIZE                0x1
-#define GC_USB_DOEPCTL2_DPID_DEFAULT             0x0
-#define GC_USB_DOEPCTL2_DPID_OFFSET              0xb40
-#define GC_USB_DOEPCTL2_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL2_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL2_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL2_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL2_NAKSTS_OFFSET            0xb40
-#define GC_USB_DOEPCTL2_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL2_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL2_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL2_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL2_EPTYPE_OFFSET            0xb40
-#define GC_USB_DOEPCTL2_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL2_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL2_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL2_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL2_SNP_OFFSET               0xb40
-#define GC_USB_DOEPCTL2_STALL_LSB                0x15
-#define GC_USB_DOEPCTL2_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL2_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL2_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL2_STALL_OFFSET             0xb40
-#define GC_USB_DOEPCTL2_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL2_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL2_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL2_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL2_CNAK_OFFSET              0xb40
-#define GC_USB_DOEPCTL2_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL2_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL2_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL2_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL2_SNAK_OFFSET              0xb40
-#define GC_USB_DOEPCTL2_SETD0PID_LSB             0x1c
-#define GC_USB_DOEPCTL2_SETD0PID_MASK            0x10000000
-#define GC_USB_DOEPCTL2_SETD0PID_SIZE            0x1
-#define GC_USB_DOEPCTL2_SETD0PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL2_SETD0PID_OFFSET          0xb40
-#define GC_USB_DOEPCTL2_SETD1PID_LSB             0x1d
-#define GC_USB_DOEPCTL2_SETD1PID_MASK            0x20000000
-#define GC_USB_DOEPCTL2_SETD1PID_SIZE            0x1
-#define GC_USB_DOEPCTL2_SETD1PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL2_SETD1PID_OFFSET          0xb40
-#define GC_USB_DOEPCTL2_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL2_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL2_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL2_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL2_EPDIS_OFFSET             0xb40
-#define GC_USB_DOEPCTL2_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL2_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL2_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL2_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL2_EPENA_OFFSET             0xb40
-#define GC_USB_DOEPINT2_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT2_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT2_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT2_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT2_XFERCOMPL_OFFSET         0xb48
-#define GC_USB_DOEPINT2_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT2_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT2_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT2_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT2_EPDISBLD_OFFSET          0xb48
-#define GC_USB_DOEPINT2_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT2_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT2_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT2_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT2_AHBERR_OFFSET            0xb48
-#define GC_USB_DOEPINT2_SETUP_LSB                0x3
-#define GC_USB_DOEPINT2_SETUP_MASK               0x8
-#define GC_USB_DOEPINT2_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT2_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT2_SETUP_OFFSET             0xb48
-#define GC_USB_DOEPINT2_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT2_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT2_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT2_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT2_OUTTKNEPDIS_OFFSET       0xb48
-#define GC_USB_DOEPINT2_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT2_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT2_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT2_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT2_STSPHSERCVD_OFFSET       0xb48
-#define GC_USB_DOEPINT2_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT2_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT2_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT2_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT2_BACK2BACKSETUP_OFFSET    0xb48
-#define GC_USB_DOEPINT2_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT2_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT2_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT2_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT2_OUTPKTERR_OFFSET         0xb48
-#define GC_USB_DOEPINT2_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT2_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT2_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT2_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT2_BNAINTR_OFFSET           0xb48
-#define GC_USB_DOEPINT2_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT2_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT2_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT2_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT2_PKTDRPSTS_OFFSET         0xb48
-#define GC_USB_DOEPINT2_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT2_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT2_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT2_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT2_BBLEERR_OFFSET           0xb48
-#define GC_USB_DOEPINT2_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT2_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT2_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT2_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT2_NAKINTRPT_OFFSET         0xb48
-#define GC_USB_DOEPINT2_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT2_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT2_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT2_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT2_NYETINTRPT_OFFSET        0xb48
-#define GC_USB_DOEPINT2_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT2_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT2_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT2_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT2_STUPPKTRCVD_OFFSET       0xb48
-#define GC_USB_DOEPTSIZ2_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ2_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DOEPTSIZ2_XFERSIZE_SIZE           0x13
-#define GC_USB_DOEPTSIZ2_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ2_XFERSIZE_OFFSET         0xb50
-#define GC_USB_DOEPTSIZ2_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ2_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DOEPTSIZ2_PKTCNT_SIZE             0xa
-#define GC_USB_DOEPTSIZ2_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ2_PKTCNT_OFFSET           0xb50
-#define GC_USB_DOEPTSIZ2_RXDPID_LSB              0x1d
-#define GC_USB_DOEPTSIZ2_RXDPID_MASK             0x60000000
-#define GC_USB_DOEPTSIZ2_RXDPID_SIZE             0x2
-#define GC_USB_DOEPTSIZ2_RXDPID_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ2_RXDPID_OFFSET           0xb50
-#define GC_USB_DOEPDMA2_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA2_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA2_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA2_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA2_DMAADDR_OFFSET           0xb54
-#define GC_USB_DOEPDMAB2_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB2_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB2_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB2_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB2_DMABUFFERADDR_OFFSET    0xb5c
-#define GC_USB_DOEPCTL3_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL3_MPS_MASK                 0x7ff
-#define GC_USB_DOEPCTL3_MPS_SIZE                 0xb
-#define GC_USB_DOEPCTL3_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL3_MPS_OFFSET               0xb60
-#define GC_USB_DOEPCTL3_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL3_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL3_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL3_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL3_USBACTEP_OFFSET          0xb60
-#define GC_USB_DOEPCTL3_DPID_LSB                 0x10
-#define GC_USB_DOEPCTL3_DPID_MASK                0x10000
-#define GC_USB_DOEPCTL3_DPID_SIZE                0x1
-#define GC_USB_DOEPCTL3_DPID_DEFAULT             0x0
-#define GC_USB_DOEPCTL3_DPID_OFFSET              0xb60
-#define GC_USB_DOEPCTL3_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL3_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL3_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL3_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL3_NAKSTS_OFFSET            0xb60
-#define GC_USB_DOEPCTL3_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL3_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL3_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL3_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL3_EPTYPE_OFFSET            0xb60
-#define GC_USB_DOEPCTL3_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL3_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL3_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL3_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL3_SNP_OFFSET               0xb60
-#define GC_USB_DOEPCTL3_STALL_LSB                0x15
-#define GC_USB_DOEPCTL3_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL3_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL3_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL3_STALL_OFFSET             0xb60
-#define GC_USB_DOEPCTL3_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL3_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL3_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL3_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL3_CNAK_OFFSET              0xb60
-#define GC_USB_DOEPCTL3_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL3_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL3_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL3_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL3_SNAK_OFFSET              0xb60
-#define GC_USB_DOEPCTL3_SETD0PID_LSB             0x1c
-#define GC_USB_DOEPCTL3_SETD0PID_MASK            0x10000000
-#define GC_USB_DOEPCTL3_SETD0PID_SIZE            0x1
-#define GC_USB_DOEPCTL3_SETD0PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL3_SETD0PID_OFFSET          0xb60
-#define GC_USB_DOEPCTL3_SETD1PID_LSB             0x1d
-#define GC_USB_DOEPCTL3_SETD1PID_MASK            0x20000000
-#define GC_USB_DOEPCTL3_SETD1PID_SIZE            0x1
-#define GC_USB_DOEPCTL3_SETD1PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL3_SETD1PID_OFFSET          0xb60
-#define GC_USB_DOEPCTL3_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL3_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL3_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL3_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL3_EPDIS_OFFSET             0xb60
-#define GC_USB_DOEPCTL3_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL3_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL3_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL3_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL3_EPENA_OFFSET             0xb60
-#define GC_USB_DOEPINT3_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT3_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT3_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT3_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT3_XFERCOMPL_OFFSET         0xb68
-#define GC_USB_DOEPINT3_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT3_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT3_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT3_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT3_EPDISBLD_OFFSET          0xb68
-#define GC_USB_DOEPINT3_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT3_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT3_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT3_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT3_AHBERR_OFFSET            0xb68
-#define GC_USB_DOEPINT3_SETUP_LSB                0x3
-#define GC_USB_DOEPINT3_SETUP_MASK               0x8
-#define GC_USB_DOEPINT3_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT3_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT3_SETUP_OFFSET             0xb68
-#define GC_USB_DOEPINT3_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT3_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT3_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT3_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT3_OUTTKNEPDIS_OFFSET       0xb68
-#define GC_USB_DOEPINT3_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT3_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT3_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT3_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT3_STSPHSERCVD_OFFSET       0xb68
-#define GC_USB_DOEPINT3_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT3_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT3_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT3_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT3_BACK2BACKSETUP_OFFSET    0xb68
-#define GC_USB_DOEPINT3_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT3_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT3_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT3_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT3_OUTPKTERR_OFFSET         0xb68
-#define GC_USB_DOEPINT3_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT3_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT3_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT3_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT3_BNAINTR_OFFSET           0xb68
-#define GC_USB_DOEPINT3_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT3_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT3_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT3_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT3_PKTDRPSTS_OFFSET         0xb68
-#define GC_USB_DOEPINT3_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT3_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT3_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT3_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT3_BBLEERR_OFFSET           0xb68
-#define GC_USB_DOEPINT3_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT3_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT3_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT3_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT3_NAKINTRPT_OFFSET         0xb68
-#define GC_USB_DOEPINT3_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT3_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT3_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT3_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT3_NYETINTRPT_OFFSET        0xb68
-#define GC_USB_DOEPINT3_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT3_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT3_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT3_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT3_STUPPKTRCVD_OFFSET       0xb68
-#define GC_USB_DOEPTSIZ3_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ3_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DOEPTSIZ3_XFERSIZE_SIZE           0x13
-#define GC_USB_DOEPTSIZ3_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ3_XFERSIZE_OFFSET         0xb70
-#define GC_USB_DOEPTSIZ3_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ3_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DOEPTSIZ3_PKTCNT_SIZE             0xa
-#define GC_USB_DOEPTSIZ3_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ3_PKTCNT_OFFSET           0xb70
-#define GC_USB_DOEPTSIZ3_RXDPID_LSB              0x1d
-#define GC_USB_DOEPTSIZ3_RXDPID_MASK             0x60000000
-#define GC_USB_DOEPTSIZ3_RXDPID_SIZE             0x2
-#define GC_USB_DOEPTSIZ3_RXDPID_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ3_RXDPID_OFFSET           0xb70
-#define GC_USB_DOEPDMA3_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA3_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA3_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA3_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA3_DMAADDR_OFFSET           0xb74
-#define GC_USB_DOEPDMAB3_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB3_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB3_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB3_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB3_DMABUFFERADDR_OFFSET    0xb7c
-#define GC_USB_DOEPCTL4_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL4_MPS_MASK                 0x7ff
-#define GC_USB_DOEPCTL4_MPS_SIZE                 0xb
-#define GC_USB_DOEPCTL4_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL4_MPS_OFFSET               0xb80
-#define GC_USB_DOEPCTL4_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL4_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL4_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL4_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL4_USBACTEP_OFFSET          0xb80
-#define GC_USB_DOEPCTL4_DPID_LSB                 0x10
-#define GC_USB_DOEPCTL4_DPID_MASK                0x10000
-#define GC_USB_DOEPCTL4_DPID_SIZE                0x1
-#define GC_USB_DOEPCTL4_DPID_DEFAULT             0x0
-#define GC_USB_DOEPCTL4_DPID_OFFSET              0xb80
-#define GC_USB_DOEPCTL4_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL4_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL4_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL4_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL4_NAKSTS_OFFSET            0xb80
-#define GC_USB_DOEPCTL4_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL4_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL4_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL4_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL4_EPTYPE_OFFSET            0xb80
-#define GC_USB_DOEPCTL4_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL4_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL4_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL4_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL4_SNP_OFFSET               0xb80
-#define GC_USB_DOEPCTL4_STALL_LSB                0x15
-#define GC_USB_DOEPCTL4_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL4_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL4_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL4_STALL_OFFSET             0xb80
-#define GC_USB_DOEPCTL4_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL4_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL4_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL4_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL4_CNAK_OFFSET              0xb80
-#define GC_USB_DOEPCTL4_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL4_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL4_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL4_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL4_SNAK_OFFSET              0xb80
-#define GC_USB_DOEPCTL4_SETD0PID_LSB             0x1c
-#define GC_USB_DOEPCTL4_SETD0PID_MASK            0x10000000
-#define GC_USB_DOEPCTL4_SETD0PID_SIZE            0x1
-#define GC_USB_DOEPCTL4_SETD0PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL4_SETD0PID_OFFSET          0xb80
-#define GC_USB_DOEPCTL4_SETD1PID_LSB             0x1d
-#define GC_USB_DOEPCTL4_SETD1PID_MASK            0x20000000
-#define GC_USB_DOEPCTL4_SETD1PID_SIZE            0x1
-#define GC_USB_DOEPCTL4_SETD1PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL4_SETD1PID_OFFSET          0xb80
-#define GC_USB_DOEPCTL4_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL4_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL4_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL4_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL4_EPDIS_OFFSET             0xb80
-#define GC_USB_DOEPCTL4_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL4_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL4_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL4_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL4_EPENA_OFFSET             0xb80
-#define GC_USB_DOEPINT4_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT4_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT4_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT4_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT4_XFERCOMPL_OFFSET         0xb88
-#define GC_USB_DOEPINT4_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT4_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT4_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT4_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT4_EPDISBLD_OFFSET          0xb88
-#define GC_USB_DOEPINT4_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT4_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT4_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT4_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT4_AHBERR_OFFSET            0xb88
-#define GC_USB_DOEPINT4_SETUP_LSB                0x3
-#define GC_USB_DOEPINT4_SETUP_MASK               0x8
-#define GC_USB_DOEPINT4_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT4_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT4_SETUP_OFFSET             0xb88
-#define GC_USB_DOEPINT4_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT4_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT4_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT4_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT4_OUTTKNEPDIS_OFFSET       0xb88
-#define GC_USB_DOEPINT4_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT4_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT4_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT4_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT4_STSPHSERCVD_OFFSET       0xb88
-#define GC_USB_DOEPINT4_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT4_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT4_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT4_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT4_BACK2BACKSETUP_OFFSET    0xb88
-#define GC_USB_DOEPINT4_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT4_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT4_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT4_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT4_OUTPKTERR_OFFSET         0xb88
-#define GC_USB_DOEPINT4_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT4_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT4_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT4_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT4_BNAINTR_OFFSET           0xb88
-#define GC_USB_DOEPINT4_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT4_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT4_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT4_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT4_PKTDRPSTS_OFFSET         0xb88
-#define GC_USB_DOEPINT4_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT4_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT4_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT4_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT4_BBLEERR_OFFSET           0xb88
-#define GC_USB_DOEPINT4_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT4_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT4_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT4_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT4_NAKINTRPT_OFFSET         0xb88
-#define GC_USB_DOEPINT4_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT4_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT4_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT4_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT4_NYETINTRPT_OFFSET        0xb88
-#define GC_USB_DOEPINT4_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT4_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT4_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT4_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT4_STUPPKTRCVD_OFFSET       0xb88
-#define GC_USB_DOEPTSIZ4_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ4_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DOEPTSIZ4_XFERSIZE_SIZE           0x13
-#define GC_USB_DOEPTSIZ4_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ4_XFERSIZE_OFFSET         0xb90
-#define GC_USB_DOEPTSIZ4_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ4_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DOEPTSIZ4_PKTCNT_SIZE             0xa
-#define GC_USB_DOEPTSIZ4_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ4_PKTCNT_OFFSET           0xb90
-#define GC_USB_DOEPTSIZ4_RXDPID_LSB              0x1d
-#define GC_USB_DOEPTSIZ4_RXDPID_MASK             0x60000000
-#define GC_USB_DOEPTSIZ4_RXDPID_SIZE             0x2
-#define GC_USB_DOEPTSIZ4_RXDPID_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ4_RXDPID_OFFSET           0xb90
-#define GC_USB_DOEPDMA4_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA4_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA4_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA4_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA4_DMAADDR_OFFSET           0xb94
-#define GC_USB_DOEPDMAB4_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB4_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB4_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB4_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB4_DMABUFFERADDR_OFFSET    0xb9c
-#define GC_USB_DOEPCTL5_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL5_MPS_MASK                 0x7ff
-#define GC_USB_DOEPCTL5_MPS_SIZE                 0xb
-#define GC_USB_DOEPCTL5_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL5_MPS_OFFSET               0xba0
-#define GC_USB_DOEPCTL5_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL5_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL5_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL5_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL5_USBACTEP_OFFSET          0xba0
-#define GC_USB_DOEPCTL5_DPID_LSB                 0x10
-#define GC_USB_DOEPCTL5_DPID_MASK                0x10000
-#define GC_USB_DOEPCTL5_DPID_SIZE                0x1
-#define GC_USB_DOEPCTL5_DPID_DEFAULT             0x0
-#define GC_USB_DOEPCTL5_DPID_OFFSET              0xba0
-#define GC_USB_DOEPCTL5_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL5_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL5_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL5_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL5_NAKSTS_OFFSET            0xba0
-#define GC_USB_DOEPCTL5_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL5_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL5_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL5_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL5_EPTYPE_OFFSET            0xba0
-#define GC_USB_DOEPCTL5_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL5_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL5_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL5_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL5_SNP_OFFSET               0xba0
-#define GC_USB_DOEPCTL5_STALL_LSB                0x15
-#define GC_USB_DOEPCTL5_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL5_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL5_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL5_STALL_OFFSET             0xba0
-#define GC_USB_DOEPCTL5_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL5_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL5_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL5_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL5_CNAK_OFFSET              0xba0
-#define GC_USB_DOEPCTL5_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL5_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL5_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL5_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL5_SNAK_OFFSET              0xba0
-#define GC_USB_DOEPCTL5_SETD0PID_LSB             0x1c
-#define GC_USB_DOEPCTL5_SETD0PID_MASK            0x10000000
-#define GC_USB_DOEPCTL5_SETD0PID_SIZE            0x1
-#define GC_USB_DOEPCTL5_SETD0PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL5_SETD0PID_OFFSET          0xba0
-#define GC_USB_DOEPCTL5_SETD1PID_LSB             0x1d
-#define GC_USB_DOEPCTL5_SETD1PID_MASK            0x20000000
-#define GC_USB_DOEPCTL5_SETD1PID_SIZE            0x1
-#define GC_USB_DOEPCTL5_SETD1PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL5_SETD1PID_OFFSET          0xba0
-#define GC_USB_DOEPCTL5_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL5_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL5_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL5_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL5_EPDIS_OFFSET             0xba0
-#define GC_USB_DOEPCTL5_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL5_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL5_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL5_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL5_EPENA_OFFSET             0xba0
-#define GC_USB_DOEPINT5_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT5_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT5_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT5_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT5_XFERCOMPL_OFFSET         0xba8
-#define GC_USB_DOEPINT5_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT5_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT5_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT5_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT5_EPDISBLD_OFFSET          0xba8
-#define GC_USB_DOEPINT5_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT5_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT5_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT5_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT5_AHBERR_OFFSET            0xba8
-#define GC_USB_DOEPINT5_SETUP_LSB                0x3
-#define GC_USB_DOEPINT5_SETUP_MASK               0x8
-#define GC_USB_DOEPINT5_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT5_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT5_SETUP_OFFSET             0xba8
-#define GC_USB_DOEPINT5_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT5_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT5_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT5_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT5_OUTTKNEPDIS_OFFSET       0xba8
-#define GC_USB_DOEPINT5_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT5_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT5_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT5_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT5_STSPHSERCVD_OFFSET       0xba8
-#define GC_USB_DOEPINT5_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT5_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT5_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT5_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT5_BACK2BACKSETUP_OFFSET    0xba8
-#define GC_USB_DOEPINT5_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT5_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT5_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT5_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT5_OUTPKTERR_OFFSET         0xba8
-#define GC_USB_DOEPINT5_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT5_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT5_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT5_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT5_BNAINTR_OFFSET           0xba8
-#define GC_USB_DOEPINT5_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT5_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT5_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT5_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT5_PKTDRPSTS_OFFSET         0xba8
-#define GC_USB_DOEPINT5_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT5_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT5_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT5_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT5_BBLEERR_OFFSET           0xba8
-#define GC_USB_DOEPINT5_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT5_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT5_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT5_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT5_NAKINTRPT_OFFSET         0xba8
-#define GC_USB_DOEPINT5_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT5_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT5_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT5_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT5_NYETINTRPT_OFFSET        0xba8
-#define GC_USB_DOEPINT5_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT5_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT5_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT5_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT5_STUPPKTRCVD_OFFSET       0xba8
-#define GC_USB_DOEPTSIZ5_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ5_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DOEPTSIZ5_XFERSIZE_SIZE           0x13
-#define GC_USB_DOEPTSIZ5_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ5_XFERSIZE_OFFSET         0xbb0
-#define GC_USB_DOEPTSIZ5_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ5_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DOEPTSIZ5_PKTCNT_SIZE             0xa
-#define GC_USB_DOEPTSIZ5_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ5_PKTCNT_OFFSET           0xbb0
-#define GC_USB_DOEPTSIZ5_RXDPID_LSB              0x1d
-#define GC_USB_DOEPTSIZ5_RXDPID_MASK             0x60000000
-#define GC_USB_DOEPTSIZ5_RXDPID_SIZE             0x2
-#define GC_USB_DOEPTSIZ5_RXDPID_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ5_RXDPID_OFFSET           0xbb0
-#define GC_USB_DOEPDMA5_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA5_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA5_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA5_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA5_DMAADDR_OFFSET           0xbb4
-#define GC_USB_DOEPDMAB5_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB5_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB5_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB5_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB5_DMABUFFERADDR_OFFSET    0xbbc
-#define GC_USB_DOEPCTL6_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL6_MPS_MASK                 0x7ff
-#define GC_USB_DOEPCTL6_MPS_SIZE                 0xb
-#define GC_USB_DOEPCTL6_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL6_MPS_OFFSET               0xbc0
-#define GC_USB_DOEPCTL6_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL6_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL6_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL6_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL6_USBACTEP_OFFSET          0xbc0
-#define GC_USB_DOEPCTL6_DPID_LSB                 0x10
-#define GC_USB_DOEPCTL6_DPID_MASK                0x10000
-#define GC_USB_DOEPCTL6_DPID_SIZE                0x1
-#define GC_USB_DOEPCTL6_DPID_DEFAULT             0x0
-#define GC_USB_DOEPCTL6_DPID_OFFSET              0xbc0
-#define GC_USB_DOEPCTL6_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL6_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL6_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL6_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL6_NAKSTS_OFFSET            0xbc0
-#define GC_USB_DOEPCTL6_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL6_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL6_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL6_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL6_EPTYPE_OFFSET            0xbc0
-#define GC_USB_DOEPCTL6_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL6_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL6_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL6_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL6_SNP_OFFSET               0xbc0
-#define GC_USB_DOEPCTL6_STALL_LSB                0x15
-#define GC_USB_DOEPCTL6_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL6_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL6_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL6_STALL_OFFSET             0xbc0
-#define GC_USB_DOEPCTL6_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL6_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL6_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL6_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL6_CNAK_OFFSET              0xbc0
-#define GC_USB_DOEPCTL6_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL6_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL6_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL6_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL6_SNAK_OFFSET              0xbc0
-#define GC_USB_DOEPCTL6_SETD0PID_LSB             0x1c
-#define GC_USB_DOEPCTL6_SETD0PID_MASK            0x10000000
-#define GC_USB_DOEPCTL6_SETD0PID_SIZE            0x1
-#define GC_USB_DOEPCTL6_SETD0PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL6_SETD0PID_OFFSET          0xbc0
-#define GC_USB_DOEPCTL6_SETD1PID_LSB             0x1d
-#define GC_USB_DOEPCTL6_SETD1PID_MASK            0x20000000
-#define GC_USB_DOEPCTL6_SETD1PID_SIZE            0x1
-#define GC_USB_DOEPCTL6_SETD1PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL6_SETD1PID_OFFSET          0xbc0
-#define GC_USB_DOEPCTL6_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL6_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL6_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL6_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL6_EPDIS_OFFSET             0xbc0
-#define GC_USB_DOEPCTL6_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL6_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL6_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL6_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL6_EPENA_OFFSET             0xbc0
-#define GC_USB_DOEPINT6_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT6_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT6_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT6_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT6_XFERCOMPL_OFFSET         0xbc8
-#define GC_USB_DOEPINT6_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT6_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT6_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT6_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT6_EPDISBLD_OFFSET          0xbc8
-#define GC_USB_DOEPINT6_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT6_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT6_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT6_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT6_AHBERR_OFFSET            0xbc8
-#define GC_USB_DOEPINT6_SETUP_LSB                0x3
-#define GC_USB_DOEPINT6_SETUP_MASK               0x8
-#define GC_USB_DOEPINT6_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT6_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT6_SETUP_OFFSET             0xbc8
-#define GC_USB_DOEPINT6_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT6_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT6_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT6_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT6_OUTTKNEPDIS_OFFSET       0xbc8
-#define GC_USB_DOEPINT6_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT6_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT6_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT6_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT6_STSPHSERCVD_OFFSET       0xbc8
-#define GC_USB_DOEPINT6_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT6_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT6_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT6_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT6_BACK2BACKSETUP_OFFSET    0xbc8
-#define GC_USB_DOEPINT6_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT6_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT6_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT6_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT6_OUTPKTERR_OFFSET         0xbc8
-#define GC_USB_DOEPINT6_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT6_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT6_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT6_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT6_BNAINTR_OFFSET           0xbc8
-#define GC_USB_DOEPINT6_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT6_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT6_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT6_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT6_PKTDRPSTS_OFFSET         0xbc8
-#define GC_USB_DOEPINT6_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT6_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT6_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT6_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT6_BBLEERR_OFFSET           0xbc8
-#define GC_USB_DOEPINT6_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT6_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT6_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT6_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT6_NAKINTRPT_OFFSET         0xbc8
-#define GC_USB_DOEPINT6_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT6_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT6_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT6_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT6_NYETINTRPT_OFFSET        0xbc8
-#define GC_USB_DOEPINT6_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT6_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT6_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT6_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT6_STUPPKTRCVD_OFFSET       0xbc8
-#define GC_USB_DOEPTSIZ6_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ6_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DOEPTSIZ6_XFERSIZE_SIZE           0x13
-#define GC_USB_DOEPTSIZ6_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ6_XFERSIZE_OFFSET         0xbd0
-#define GC_USB_DOEPTSIZ6_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ6_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DOEPTSIZ6_PKTCNT_SIZE             0xa
-#define GC_USB_DOEPTSIZ6_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ6_PKTCNT_OFFSET           0xbd0
-#define GC_USB_DOEPTSIZ6_RXDPID_LSB              0x1d
-#define GC_USB_DOEPTSIZ6_RXDPID_MASK             0x60000000
-#define GC_USB_DOEPTSIZ6_RXDPID_SIZE             0x2
-#define GC_USB_DOEPTSIZ6_RXDPID_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ6_RXDPID_OFFSET           0xbd0
-#define GC_USB_DOEPDMA6_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA6_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA6_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA6_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA6_DMAADDR_OFFSET           0xbd4
-#define GC_USB_DOEPDMAB6_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB6_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB6_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB6_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB6_DMABUFFERADDR_OFFSET    0xbdc
-#define GC_USB_DOEPCTL7_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL7_MPS_MASK                 0x7ff
-#define GC_USB_DOEPCTL7_MPS_SIZE                 0xb
-#define GC_USB_DOEPCTL7_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL7_MPS_OFFSET               0xbe0
-#define GC_USB_DOEPCTL7_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL7_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL7_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL7_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL7_USBACTEP_OFFSET          0xbe0
-#define GC_USB_DOEPCTL7_DPID_LSB                 0x10
-#define GC_USB_DOEPCTL7_DPID_MASK                0x10000
-#define GC_USB_DOEPCTL7_DPID_SIZE                0x1
-#define GC_USB_DOEPCTL7_DPID_DEFAULT             0x0
-#define GC_USB_DOEPCTL7_DPID_OFFSET              0xbe0
-#define GC_USB_DOEPCTL7_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL7_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL7_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL7_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL7_NAKSTS_OFFSET            0xbe0
-#define GC_USB_DOEPCTL7_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL7_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL7_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL7_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL7_EPTYPE_OFFSET            0xbe0
-#define GC_USB_DOEPCTL7_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL7_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL7_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL7_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL7_SNP_OFFSET               0xbe0
-#define GC_USB_DOEPCTL7_STALL_LSB                0x15
-#define GC_USB_DOEPCTL7_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL7_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL7_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL7_STALL_OFFSET             0xbe0
-#define GC_USB_DOEPCTL7_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL7_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL7_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL7_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL7_CNAK_OFFSET              0xbe0
-#define GC_USB_DOEPCTL7_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL7_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL7_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL7_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL7_SNAK_OFFSET              0xbe0
-#define GC_USB_DOEPCTL7_SETD0PID_LSB             0x1c
-#define GC_USB_DOEPCTL7_SETD0PID_MASK            0x10000000
-#define GC_USB_DOEPCTL7_SETD0PID_SIZE            0x1
-#define GC_USB_DOEPCTL7_SETD0PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL7_SETD0PID_OFFSET          0xbe0
-#define GC_USB_DOEPCTL7_SETD1PID_LSB             0x1d
-#define GC_USB_DOEPCTL7_SETD1PID_MASK            0x20000000
-#define GC_USB_DOEPCTL7_SETD1PID_SIZE            0x1
-#define GC_USB_DOEPCTL7_SETD1PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL7_SETD1PID_OFFSET          0xbe0
-#define GC_USB_DOEPCTL7_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL7_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL7_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL7_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL7_EPDIS_OFFSET             0xbe0
-#define GC_USB_DOEPCTL7_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL7_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL7_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL7_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL7_EPENA_OFFSET             0xbe0
-#define GC_USB_DOEPINT7_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT7_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT7_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT7_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT7_XFERCOMPL_OFFSET         0xbe8
-#define GC_USB_DOEPINT7_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT7_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT7_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT7_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT7_EPDISBLD_OFFSET          0xbe8
-#define GC_USB_DOEPINT7_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT7_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT7_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT7_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT7_AHBERR_OFFSET            0xbe8
-#define GC_USB_DOEPINT7_SETUP_LSB                0x3
-#define GC_USB_DOEPINT7_SETUP_MASK               0x8
-#define GC_USB_DOEPINT7_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT7_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT7_SETUP_OFFSET             0xbe8
-#define GC_USB_DOEPINT7_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT7_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT7_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT7_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT7_OUTTKNEPDIS_OFFSET       0xbe8
-#define GC_USB_DOEPINT7_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT7_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT7_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT7_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT7_STSPHSERCVD_OFFSET       0xbe8
-#define GC_USB_DOEPINT7_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT7_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT7_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT7_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT7_BACK2BACKSETUP_OFFSET    0xbe8
-#define GC_USB_DOEPINT7_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT7_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT7_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT7_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT7_OUTPKTERR_OFFSET         0xbe8
-#define GC_USB_DOEPINT7_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT7_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT7_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT7_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT7_BNAINTR_OFFSET           0xbe8
-#define GC_USB_DOEPINT7_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT7_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT7_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT7_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT7_PKTDRPSTS_OFFSET         0xbe8
-#define GC_USB_DOEPINT7_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT7_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT7_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT7_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT7_BBLEERR_OFFSET           0xbe8
-#define GC_USB_DOEPINT7_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT7_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT7_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT7_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT7_NAKINTRPT_OFFSET         0xbe8
-#define GC_USB_DOEPINT7_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT7_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT7_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT7_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT7_NYETINTRPT_OFFSET        0xbe8
-#define GC_USB_DOEPINT7_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT7_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT7_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT7_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT7_STUPPKTRCVD_OFFSET       0xbe8
-#define GC_USB_DOEPTSIZ7_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ7_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DOEPTSIZ7_XFERSIZE_SIZE           0x13
-#define GC_USB_DOEPTSIZ7_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ7_XFERSIZE_OFFSET         0xbf0
-#define GC_USB_DOEPTSIZ7_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ7_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DOEPTSIZ7_PKTCNT_SIZE             0xa
-#define GC_USB_DOEPTSIZ7_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ7_PKTCNT_OFFSET           0xbf0
-#define GC_USB_DOEPTSIZ7_RXDPID_LSB              0x1d
-#define GC_USB_DOEPTSIZ7_RXDPID_MASK             0x60000000
-#define GC_USB_DOEPTSIZ7_RXDPID_SIZE             0x2
-#define GC_USB_DOEPTSIZ7_RXDPID_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ7_RXDPID_OFFSET           0xbf0
-#define GC_USB_DOEPDMA7_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA7_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA7_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA7_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA7_DMAADDR_OFFSET           0xbf4
-#define GC_USB_DOEPDMAB7_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB7_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB7_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB7_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB7_DMABUFFERADDR_OFFSET    0xbfc
-#define GC_USB_DOEPCTL8_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL8_MPS_MASK                 0x7ff
-#define GC_USB_DOEPCTL8_MPS_SIZE                 0xb
-#define GC_USB_DOEPCTL8_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL8_MPS_OFFSET               0xc00
-#define GC_USB_DOEPCTL8_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL8_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL8_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL8_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL8_USBACTEP_OFFSET          0xc00
-#define GC_USB_DOEPCTL8_DPID_LSB                 0x10
-#define GC_USB_DOEPCTL8_DPID_MASK                0x10000
-#define GC_USB_DOEPCTL8_DPID_SIZE                0x1
-#define GC_USB_DOEPCTL8_DPID_DEFAULT             0x0
-#define GC_USB_DOEPCTL8_DPID_OFFSET              0xc00
-#define GC_USB_DOEPCTL8_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL8_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL8_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL8_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL8_NAKSTS_OFFSET            0xc00
-#define GC_USB_DOEPCTL8_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL8_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL8_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL8_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL8_EPTYPE_OFFSET            0xc00
-#define GC_USB_DOEPCTL8_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL8_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL8_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL8_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL8_SNP_OFFSET               0xc00
-#define GC_USB_DOEPCTL8_STALL_LSB                0x15
-#define GC_USB_DOEPCTL8_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL8_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL8_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL8_STALL_OFFSET             0xc00
-#define GC_USB_DOEPCTL8_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL8_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL8_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL8_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL8_CNAK_OFFSET              0xc00
-#define GC_USB_DOEPCTL8_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL8_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL8_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL8_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL8_SNAK_OFFSET              0xc00
-#define GC_USB_DOEPCTL8_SETD0PID_LSB             0x1c
-#define GC_USB_DOEPCTL8_SETD0PID_MASK            0x10000000
-#define GC_USB_DOEPCTL8_SETD0PID_SIZE            0x1
-#define GC_USB_DOEPCTL8_SETD0PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL8_SETD0PID_OFFSET          0xc00
-#define GC_USB_DOEPCTL8_SETD1PID_LSB             0x1d
-#define GC_USB_DOEPCTL8_SETD1PID_MASK            0x20000000
-#define GC_USB_DOEPCTL8_SETD1PID_SIZE            0x1
-#define GC_USB_DOEPCTL8_SETD1PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL8_SETD1PID_OFFSET          0xc00
-#define GC_USB_DOEPCTL8_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL8_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL8_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL8_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL8_EPDIS_OFFSET             0xc00
-#define GC_USB_DOEPCTL8_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL8_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL8_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL8_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL8_EPENA_OFFSET             0xc00
-#define GC_USB_DOEPINT8_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT8_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT8_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT8_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT8_XFERCOMPL_OFFSET         0xc08
-#define GC_USB_DOEPINT8_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT8_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT8_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT8_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT8_EPDISBLD_OFFSET          0xc08
-#define GC_USB_DOEPINT8_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT8_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT8_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT8_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT8_AHBERR_OFFSET            0xc08
-#define GC_USB_DOEPINT8_SETUP_LSB                0x3
-#define GC_USB_DOEPINT8_SETUP_MASK               0x8
-#define GC_USB_DOEPINT8_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT8_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT8_SETUP_OFFSET             0xc08
-#define GC_USB_DOEPINT8_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT8_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT8_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT8_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT8_OUTTKNEPDIS_OFFSET       0xc08
-#define GC_USB_DOEPINT8_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT8_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT8_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT8_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT8_STSPHSERCVD_OFFSET       0xc08
-#define GC_USB_DOEPINT8_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT8_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT8_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT8_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT8_BACK2BACKSETUP_OFFSET    0xc08
-#define GC_USB_DOEPINT8_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT8_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT8_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT8_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT8_OUTPKTERR_OFFSET         0xc08
-#define GC_USB_DOEPINT8_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT8_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT8_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT8_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT8_BNAINTR_OFFSET           0xc08
-#define GC_USB_DOEPINT8_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT8_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT8_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT8_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT8_PKTDRPSTS_OFFSET         0xc08
-#define GC_USB_DOEPINT8_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT8_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT8_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT8_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT8_BBLEERR_OFFSET           0xc08
-#define GC_USB_DOEPINT8_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT8_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT8_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT8_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT8_NAKINTRPT_OFFSET         0xc08
-#define GC_USB_DOEPINT8_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT8_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT8_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT8_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT8_NYETINTRPT_OFFSET        0xc08
-#define GC_USB_DOEPINT8_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT8_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT8_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT8_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT8_STUPPKTRCVD_OFFSET       0xc08
-#define GC_USB_DOEPTSIZ8_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ8_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DOEPTSIZ8_XFERSIZE_SIZE           0x13
-#define GC_USB_DOEPTSIZ8_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ8_XFERSIZE_OFFSET         0xc10
-#define GC_USB_DOEPTSIZ8_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ8_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DOEPTSIZ8_PKTCNT_SIZE             0xa
-#define GC_USB_DOEPTSIZ8_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ8_PKTCNT_OFFSET           0xc10
-#define GC_USB_DOEPTSIZ8_RXDPID_LSB              0x1d
-#define GC_USB_DOEPTSIZ8_RXDPID_MASK             0x60000000
-#define GC_USB_DOEPTSIZ8_RXDPID_SIZE             0x2
-#define GC_USB_DOEPTSIZ8_RXDPID_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ8_RXDPID_OFFSET           0xc10
-#define GC_USB_DOEPDMA8_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA8_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA8_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA8_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA8_DMAADDR_OFFSET           0xc14
-#define GC_USB_DOEPDMAB8_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB8_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB8_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB8_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB8_DMABUFFERADDR_OFFSET    0xc1c
-#define GC_USB_DOEPCTL9_MPS_LSB                  0x0
-#define GC_USB_DOEPCTL9_MPS_MASK                 0x7ff
-#define GC_USB_DOEPCTL9_MPS_SIZE                 0xb
-#define GC_USB_DOEPCTL9_MPS_DEFAULT              0x0
-#define GC_USB_DOEPCTL9_MPS_OFFSET               0xc20
-#define GC_USB_DOEPCTL9_USBACTEP_LSB             0xf
-#define GC_USB_DOEPCTL9_USBACTEP_MASK            0x8000
-#define GC_USB_DOEPCTL9_USBACTEP_SIZE            0x1
-#define GC_USB_DOEPCTL9_USBACTEP_DEFAULT         0x0
-#define GC_USB_DOEPCTL9_USBACTEP_OFFSET          0xc20
-#define GC_USB_DOEPCTL9_DPID_LSB                 0x10
-#define GC_USB_DOEPCTL9_DPID_MASK                0x10000
-#define GC_USB_DOEPCTL9_DPID_SIZE                0x1
-#define GC_USB_DOEPCTL9_DPID_DEFAULT             0x0
-#define GC_USB_DOEPCTL9_DPID_OFFSET              0xc20
-#define GC_USB_DOEPCTL9_NAKSTS_LSB               0x11
-#define GC_USB_DOEPCTL9_NAKSTS_MASK              0x20000
-#define GC_USB_DOEPCTL9_NAKSTS_SIZE              0x1
-#define GC_USB_DOEPCTL9_NAKSTS_DEFAULT           0x0
-#define GC_USB_DOEPCTL9_NAKSTS_OFFSET            0xc20
-#define GC_USB_DOEPCTL9_EPTYPE_LSB               0x12
-#define GC_USB_DOEPCTL9_EPTYPE_MASK              0xc0000
-#define GC_USB_DOEPCTL9_EPTYPE_SIZE              0x2
-#define GC_USB_DOEPCTL9_EPTYPE_DEFAULT           0x0
-#define GC_USB_DOEPCTL9_EPTYPE_OFFSET            0xc20
-#define GC_USB_DOEPCTL9_SNP_LSB                  0x14
-#define GC_USB_DOEPCTL9_SNP_MASK                 0x100000
-#define GC_USB_DOEPCTL9_SNP_SIZE                 0x1
-#define GC_USB_DOEPCTL9_SNP_DEFAULT              0x0
-#define GC_USB_DOEPCTL9_SNP_OFFSET               0xc20
-#define GC_USB_DOEPCTL9_STALL_LSB                0x15
-#define GC_USB_DOEPCTL9_STALL_MASK               0x200000
-#define GC_USB_DOEPCTL9_STALL_SIZE               0x1
-#define GC_USB_DOEPCTL9_STALL_DEFAULT            0x0
-#define GC_USB_DOEPCTL9_STALL_OFFSET             0xc20
-#define GC_USB_DOEPCTL9_CNAK_LSB                 0x1a
-#define GC_USB_DOEPCTL9_CNAK_MASK                0x4000000
-#define GC_USB_DOEPCTL9_CNAK_SIZE                0x1
-#define GC_USB_DOEPCTL9_CNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL9_CNAK_OFFSET              0xc20
-#define GC_USB_DOEPCTL9_SNAK_LSB                 0x1b
-#define GC_USB_DOEPCTL9_SNAK_MASK                0x8000000
-#define GC_USB_DOEPCTL9_SNAK_SIZE                0x1
-#define GC_USB_DOEPCTL9_SNAK_DEFAULT             0x0
-#define GC_USB_DOEPCTL9_SNAK_OFFSET              0xc20
-#define GC_USB_DOEPCTL9_SETD0PID_LSB             0x1c
-#define GC_USB_DOEPCTL9_SETD0PID_MASK            0x10000000
-#define GC_USB_DOEPCTL9_SETD0PID_SIZE            0x1
-#define GC_USB_DOEPCTL9_SETD0PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL9_SETD0PID_OFFSET          0xc20
-#define GC_USB_DOEPCTL9_SETD1PID_LSB             0x1d
-#define GC_USB_DOEPCTL9_SETD1PID_MASK            0x20000000
-#define GC_USB_DOEPCTL9_SETD1PID_SIZE            0x1
-#define GC_USB_DOEPCTL9_SETD1PID_DEFAULT         0x0
-#define GC_USB_DOEPCTL9_SETD1PID_OFFSET          0xc20
-#define GC_USB_DOEPCTL9_EPDIS_LSB                0x1e
-#define GC_USB_DOEPCTL9_EPDIS_MASK               0x40000000
-#define GC_USB_DOEPCTL9_EPDIS_SIZE               0x1
-#define GC_USB_DOEPCTL9_EPDIS_DEFAULT            0x0
-#define GC_USB_DOEPCTL9_EPDIS_OFFSET             0xc20
-#define GC_USB_DOEPCTL9_EPENA_LSB                0x1f
-#define GC_USB_DOEPCTL9_EPENA_MASK               0x80000000
-#define GC_USB_DOEPCTL9_EPENA_SIZE               0x1
-#define GC_USB_DOEPCTL9_EPENA_DEFAULT            0x0
-#define GC_USB_DOEPCTL9_EPENA_OFFSET             0xc20
-#define GC_USB_DOEPINT9_XFERCOMPL_LSB            0x0
-#define GC_USB_DOEPINT9_XFERCOMPL_MASK           0x1
-#define GC_USB_DOEPINT9_XFERCOMPL_SIZE           0x1
-#define GC_USB_DOEPINT9_XFERCOMPL_DEFAULT        0x0
-#define GC_USB_DOEPINT9_XFERCOMPL_OFFSET         0xc28
-#define GC_USB_DOEPINT9_EPDISBLD_LSB             0x1
-#define GC_USB_DOEPINT9_EPDISBLD_MASK            0x2
-#define GC_USB_DOEPINT9_EPDISBLD_SIZE            0x1
-#define GC_USB_DOEPINT9_EPDISBLD_DEFAULT         0x0
-#define GC_USB_DOEPINT9_EPDISBLD_OFFSET          0xc28
-#define GC_USB_DOEPINT9_AHBERR_LSB               0x2
-#define GC_USB_DOEPINT9_AHBERR_MASK              0x4
-#define GC_USB_DOEPINT9_AHBERR_SIZE              0x1
-#define GC_USB_DOEPINT9_AHBERR_DEFAULT           0x0
-#define GC_USB_DOEPINT9_AHBERR_OFFSET            0xc28
-#define GC_USB_DOEPINT9_SETUP_LSB                0x3
-#define GC_USB_DOEPINT9_SETUP_MASK               0x8
-#define GC_USB_DOEPINT9_SETUP_SIZE               0x1
-#define GC_USB_DOEPINT9_SETUP_DEFAULT            0x0
-#define GC_USB_DOEPINT9_SETUP_OFFSET             0xc28
-#define GC_USB_DOEPINT9_OUTTKNEPDIS_LSB          0x4
-#define GC_USB_DOEPINT9_OUTTKNEPDIS_MASK         0x10
-#define GC_USB_DOEPINT9_OUTTKNEPDIS_SIZE         0x1
-#define GC_USB_DOEPINT9_OUTTKNEPDIS_DEFAULT      0x0
-#define GC_USB_DOEPINT9_OUTTKNEPDIS_OFFSET       0xc28
-#define GC_USB_DOEPINT9_STSPHSERCVD_LSB          0x5
-#define GC_USB_DOEPINT9_STSPHSERCVD_MASK         0x20
-#define GC_USB_DOEPINT9_STSPHSERCVD_SIZE         0x1
-#define GC_USB_DOEPINT9_STSPHSERCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT9_STSPHSERCVD_OFFSET       0xc28
-#define GC_USB_DOEPINT9_BACK2BACKSETUP_LSB       0x6
-#define GC_USB_DOEPINT9_BACK2BACKSETUP_MASK      0x40
-#define GC_USB_DOEPINT9_BACK2BACKSETUP_SIZE      0x1
-#define GC_USB_DOEPINT9_BACK2BACKSETUP_DEFAULT   0x0
-#define GC_USB_DOEPINT9_BACK2BACKSETUP_OFFSET    0xc28
-#define GC_USB_DOEPINT9_OUTPKTERR_LSB            0x8
-#define GC_USB_DOEPINT9_OUTPKTERR_MASK           0x100
-#define GC_USB_DOEPINT9_OUTPKTERR_SIZE           0x1
-#define GC_USB_DOEPINT9_OUTPKTERR_DEFAULT        0x0
-#define GC_USB_DOEPINT9_OUTPKTERR_OFFSET         0xc28
-#define GC_USB_DOEPINT9_BNAINTR_LSB              0x9
-#define GC_USB_DOEPINT9_BNAINTR_MASK             0x200
-#define GC_USB_DOEPINT9_BNAINTR_SIZE             0x1
-#define GC_USB_DOEPINT9_BNAINTR_DEFAULT          0x0
-#define GC_USB_DOEPINT9_BNAINTR_OFFSET           0xc28
-#define GC_USB_DOEPINT9_PKTDRPSTS_LSB            0xb
-#define GC_USB_DOEPINT9_PKTDRPSTS_MASK           0x800
-#define GC_USB_DOEPINT9_PKTDRPSTS_SIZE           0x1
-#define GC_USB_DOEPINT9_PKTDRPSTS_DEFAULT        0x0
-#define GC_USB_DOEPINT9_PKTDRPSTS_OFFSET         0xc28
-#define GC_USB_DOEPINT9_BBLEERR_LSB              0xc
-#define GC_USB_DOEPINT9_BBLEERR_MASK             0x1000
-#define GC_USB_DOEPINT9_BBLEERR_SIZE             0x1
-#define GC_USB_DOEPINT9_BBLEERR_DEFAULT          0x0
-#define GC_USB_DOEPINT9_BBLEERR_OFFSET           0xc28
-#define GC_USB_DOEPINT9_NAKINTRPT_LSB            0xd
-#define GC_USB_DOEPINT9_NAKINTRPT_MASK           0x2000
-#define GC_USB_DOEPINT9_NAKINTRPT_SIZE           0x1
-#define GC_USB_DOEPINT9_NAKINTRPT_DEFAULT        0x0
-#define GC_USB_DOEPINT9_NAKINTRPT_OFFSET         0xc28
-#define GC_USB_DOEPINT9_NYETINTRPT_LSB           0xe
-#define GC_USB_DOEPINT9_NYETINTRPT_MASK          0x4000
-#define GC_USB_DOEPINT9_NYETINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT9_NYETINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT9_NYETINTRPT_OFFSET        0xc28
-#define GC_USB_DOEPINT9_STUPPKTRCVD_LSB          0xf
-#define GC_USB_DOEPINT9_STUPPKTRCVD_MASK         0x8000
-#define GC_USB_DOEPINT9_STUPPKTRCVD_SIZE         0x1
-#define GC_USB_DOEPINT9_STUPPKTRCVD_DEFAULT      0x0
-#define GC_USB_DOEPINT9_STUPPKTRCVD_OFFSET       0xc28
-#define GC_USB_DOEPTSIZ9_XFERSIZE_LSB            0x0
-#define GC_USB_DOEPTSIZ9_XFERSIZE_MASK           0x7ffff
-#define GC_USB_DOEPTSIZ9_XFERSIZE_SIZE           0x13
-#define GC_USB_DOEPTSIZ9_XFERSIZE_DEFAULT        0x0
-#define GC_USB_DOEPTSIZ9_XFERSIZE_OFFSET         0xc30
-#define GC_USB_DOEPTSIZ9_PKTCNT_LSB              0x13
-#define GC_USB_DOEPTSIZ9_PKTCNT_MASK             0x1ff80000
-#define GC_USB_DOEPTSIZ9_PKTCNT_SIZE             0xa
-#define GC_USB_DOEPTSIZ9_PKTCNT_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ9_PKTCNT_OFFSET           0xc30
-#define GC_USB_DOEPTSIZ9_RXDPID_LSB              0x1d
-#define GC_USB_DOEPTSIZ9_RXDPID_MASK             0x60000000
-#define GC_USB_DOEPTSIZ9_RXDPID_SIZE             0x2
-#define GC_USB_DOEPTSIZ9_RXDPID_DEFAULT          0x0
-#define GC_USB_DOEPTSIZ9_RXDPID_OFFSET           0xc30
-#define GC_USB_DOEPDMA9_DMAADDR_LSB              0x0
-#define GC_USB_DOEPDMA9_DMAADDR_MASK             0xffffffff
-#define GC_USB_DOEPDMA9_DMAADDR_SIZE             0x20
-#define GC_USB_DOEPDMA9_DMAADDR_DEFAULT          0x0
-#define GC_USB_DOEPDMA9_DMAADDR_OFFSET           0xc34
-#define GC_USB_DOEPDMAB9_DMABUFFERADDR_LSB       0x0
-#define GC_USB_DOEPDMAB9_DMABUFFERADDR_MASK      0xffffffff
-#define GC_USB_DOEPDMAB9_DMABUFFERADDR_SIZE      0x20
-#define GC_USB_DOEPDMAB9_DMABUFFERADDR_DEFAULT   0x0
-#define GC_USB_DOEPDMAB9_DMABUFFERADDR_OFFSET    0xc3c
-#define GC_USB_DOEPCTL10_MPS_LSB                 0x0
-#define GC_USB_DOEPCTL10_MPS_MASK                0x7ff
-#define GC_USB_DOEPCTL10_MPS_SIZE                0xb
-#define GC_USB_DOEPCTL10_MPS_DEFAULT             0x0
-#define GC_USB_DOEPCTL10_MPS_OFFSET              0xc40
-#define GC_USB_DOEPCTL10_USBACTEP_LSB            0xf
-#define GC_USB_DOEPCTL10_USBACTEP_MASK           0x8000
-#define GC_USB_DOEPCTL10_USBACTEP_SIZE           0x1
-#define GC_USB_DOEPCTL10_USBACTEP_DEFAULT        0x0
-#define GC_USB_DOEPCTL10_USBACTEP_OFFSET         0xc40
-#define GC_USB_DOEPCTL10_DPID_LSB                0x10
-#define GC_USB_DOEPCTL10_DPID_MASK               0x10000
-#define GC_USB_DOEPCTL10_DPID_SIZE               0x1
-#define GC_USB_DOEPCTL10_DPID_DEFAULT            0x0
-#define GC_USB_DOEPCTL10_DPID_OFFSET             0xc40
-#define GC_USB_DOEPCTL10_NAKSTS_LSB              0x11
-#define GC_USB_DOEPCTL10_NAKSTS_MASK             0x20000
-#define GC_USB_DOEPCTL10_NAKSTS_SIZE             0x1
-#define GC_USB_DOEPCTL10_NAKSTS_DEFAULT          0x0
-#define GC_USB_DOEPCTL10_NAKSTS_OFFSET           0xc40
-#define GC_USB_DOEPCTL10_EPTYPE_LSB              0x12
-#define GC_USB_DOEPCTL10_EPTYPE_MASK             0xc0000
-#define GC_USB_DOEPCTL10_EPTYPE_SIZE             0x2
-#define GC_USB_DOEPCTL10_EPTYPE_DEFAULT          0x0
-#define GC_USB_DOEPCTL10_EPTYPE_OFFSET           0xc40
-#define GC_USB_DOEPCTL10_SNP_LSB                 0x14
-#define GC_USB_DOEPCTL10_SNP_MASK                0x100000
-#define GC_USB_DOEPCTL10_SNP_SIZE                0x1
-#define GC_USB_DOEPCTL10_SNP_DEFAULT             0x0
-#define GC_USB_DOEPCTL10_SNP_OFFSET              0xc40
-#define GC_USB_DOEPCTL10_STALL_LSB               0x15
-#define GC_USB_DOEPCTL10_STALL_MASK              0x200000
-#define GC_USB_DOEPCTL10_STALL_SIZE              0x1
-#define GC_USB_DOEPCTL10_STALL_DEFAULT           0x0
-#define GC_USB_DOEPCTL10_STALL_OFFSET            0xc40
-#define GC_USB_DOEPCTL10_CNAK_LSB                0x1a
-#define GC_USB_DOEPCTL10_CNAK_MASK               0x4000000
-#define GC_USB_DOEPCTL10_CNAK_SIZE               0x1
-#define GC_USB_DOEPCTL10_CNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL10_CNAK_OFFSET             0xc40
-#define GC_USB_DOEPCTL10_SNAK_LSB                0x1b
-#define GC_USB_DOEPCTL10_SNAK_MASK               0x8000000
-#define GC_USB_DOEPCTL10_SNAK_SIZE               0x1
-#define GC_USB_DOEPCTL10_SNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL10_SNAK_OFFSET             0xc40
-#define GC_USB_DOEPCTL10_SETD0PID_LSB            0x1c
-#define GC_USB_DOEPCTL10_SETD0PID_MASK           0x10000000
-#define GC_USB_DOEPCTL10_SETD0PID_SIZE           0x1
-#define GC_USB_DOEPCTL10_SETD0PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL10_SETD0PID_OFFSET         0xc40
-#define GC_USB_DOEPCTL10_SETD1PID_LSB            0x1d
-#define GC_USB_DOEPCTL10_SETD1PID_MASK           0x20000000
-#define GC_USB_DOEPCTL10_SETD1PID_SIZE           0x1
-#define GC_USB_DOEPCTL10_SETD1PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL10_SETD1PID_OFFSET         0xc40
-#define GC_USB_DOEPCTL10_EPDIS_LSB               0x1e
-#define GC_USB_DOEPCTL10_EPDIS_MASK              0x40000000
-#define GC_USB_DOEPCTL10_EPDIS_SIZE              0x1
-#define GC_USB_DOEPCTL10_EPDIS_DEFAULT           0x0
-#define GC_USB_DOEPCTL10_EPDIS_OFFSET            0xc40
-#define GC_USB_DOEPCTL10_EPENA_LSB               0x1f
-#define GC_USB_DOEPCTL10_EPENA_MASK              0x80000000
-#define GC_USB_DOEPCTL10_EPENA_SIZE              0x1
-#define GC_USB_DOEPCTL10_EPENA_DEFAULT           0x0
-#define GC_USB_DOEPCTL10_EPENA_OFFSET            0xc40
-#define GC_USB_DOEPINT10_XFERCOMPL_LSB           0x0
-#define GC_USB_DOEPINT10_XFERCOMPL_MASK          0x1
-#define GC_USB_DOEPINT10_XFERCOMPL_SIZE          0x1
-#define GC_USB_DOEPINT10_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DOEPINT10_XFERCOMPL_OFFSET        0xc48
-#define GC_USB_DOEPINT10_EPDISBLD_LSB            0x1
-#define GC_USB_DOEPINT10_EPDISBLD_MASK           0x2
-#define GC_USB_DOEPINT10_EPDISBLD_SIZE           0x1
-#define GC_USB_DOEPINT10_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DOEPINT10_EPDISBLD_OFFSET         0xc48
-#define GC_USB_DOEPINT10_AHBERR_LSB              0x2
-#define GC_USB_DOEPINT10_AHBERR_MASK             0x4
-#define GC_USB_DOEPINT10_AHBERR_SIZE             0x1
-#define GC_USB_DOEPINT10_AHBERR_DEFAULT          0x0
-#define GC_USB_DOEPINT10_AHBERR_OFFSET           0xc48
-#define GC_USB_DOEPINT10_SETUP_LSB               0x3
-#define GC_USB_DOEPINT10_SETUP_MASK              0x8
-#define GC_USB_DOEPINT10_SETUP_SIZE              0x1
-#define GC_USB_DOEPINT10_SETUP_DEFAULT           0x0
-#define GC_USB_DOEPINT10_SETUP_OFFSET            0xc48
-#define GC_USB_DOEPINT10_OUTTKNEPDIS_LSB         0x4
-#define GC_USB_DOEPINT10_OUTTKNEPDIS_MASK        0x10
-#define GC_USB_DOEPINT10_OUTTKNEPDIS_SIZE        0x1
-#define GC_USB_DOEPINT10_OUTTKNEPDIS_DEFAULT     0x0
-#define GC_USB_DOEPINT10_OUTTKNEPDIS_OFFSET      0xc48
-#define GC_USB_DOEPINT10_STSPHSERCVD_LSB         0x5
-#define GC_USB_DOEPINT10_STSPHSERCVD_MASK        0x20
-#define GC_USB_DOEPINT10_STSPHSERCVD_SIZE        0x1
-#define GC_USB_DOEPINT10_STSPHSERCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT10_STSPHSERCVD_OFFSET      0xc48
-#define GC_USB_DOEPINT10_BACK2BACKSETUP_LSB      0x6
-#define GC_USB_DOEPINT10_BACK2BACKSETUP_MASK     0x40
-#define GC_USB_DOEPINT10_BACK2BACKSETUP_SIZE     0x1
-#define GC_USB_DOEPINT10_BACK2BACKSETUP_DEFAULT  0x0
-#define GC_USB_DOEPINT10_BACK2BACKSETUP_OFFSET   0xc48
-#define GC_USB_DOEPINT10_OUTPKTERR_LSB           0x8
-#define GC_USB_DOEPINT10_OUTPKTERR_MASK          0x100
-#define GC_USB_DOEPINT10_OUTPKTERR_SIZE          0x1
-#define GC_USB_DOEPINT10_OUTPKTERR_DEFAULT       0x0
-#define GC_USB_DOEPINT10_OUTPKTERR_OFFSET        0xc48
-#define GC_USB_DOEPINT10_BNAINTR_LSB             0x9
-#define GC_USB_DOEPINT10_BNAINTR_MASK            0x200
-#define GC_USB_DOEPINT10_BNAINTR_SIZE            0x1
-#define GC_USB_DOEPINT10_BNAINTR_DEFAULT         0x0
-#define GC_USB_DOEPINT10_BNAINTR_OFFSET          0xc48
-#define GC_USB_DOEPINT10_PKTDRPSTS_LSB           0xb
-#define GC_USB_DOEPINT10_PKTDRPSTS_MASK          0x800
-#define GC_USB_DOEPINT10_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DOEPINT10_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DOEPINT10_PKTDRPSTS_OFFSET        0xc48
-#define GC_USB_DOEPINT10_BBLEERR_LSB             0xc
-#define GC_USB_DOEPINT10_BBLEERR_MASK            0x1000
-#define GC_USB_DOEPINT10_BBLEERR_SIZE            0x1
-#define GC_USB_DOEPINT10_BBLEERR_DEFAULT         0x0
-#define GC_USB_DOEPINT10_BBLEERR_OFFSET          0xc48
-#define GC_USB_DOEPINT10_NAKINTRPT_LSB           0xd
-#define GC_USB_DOEPINT10_NAKINTRPT_MASK          0x2000
-#define GC_USB_DOEPINT10_NAKINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT10_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT10_NAKINTRPT_OFFSET        0xc48
-#define GC_USB_DOEPINT10_NYETINTRPT_LSB          0xe
-#define GC_USB_DOEPINT10_NYETINTRPT_MASK         0x4000
-#define GC_USB_DOEPINT10_NYETINTRPT_SIZE         0x1
-#define GC_USB_DOEPINT10_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DOEPINT10_NYETINTRPT_OFFSET       0xc48
-#define GC_USB_DOEPINT10_STUPPKTRCVD_LSB         0xf
-#define GC_USB_DOEPINT10_STUPPKTRCVD_MASK        0x8000
-#define GC_USB_DOEPINT10_STUPPKTRCVD_SIZE        0x1
-#define GC_USB_DOEPINT10_STUPPKTRCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT10_STUPPKTRCVD_OFFSET      0xc48
-#define GC_USB_DOEPTSIZ10_XFERSIZE_LSB           0x0
-#define GC_USB_DOEPTSIZ10_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DOEPTSIZ10_XFERSIZE_SIZE          0x13
-#define GC_USB_DOEPTSIZ10_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DOEPTSIZ10_XFERSIZE_OFFSET        0xc50
-#define GC_USB_DOEPTSIZ10_PKTCNT_LSB             0x13
-#define GC_USB_DOEPTSIZ10_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DOEPTSIZ10_PKTCNT_SIZE            0xa
-#define GC_USB_DOEPTSIZ10_PKTCNT_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ10_PKTCNT_OFFSET          0xc50
-#define GC_USB_DOEPTSIZ10_RXDPID_LSB             0x1d
-#define GC_USB_DOEPTSIZ10_RXDPID_MASK            0x60000000
-#define GC_USB_DOEPTSIZ10_RXDPID_SIZE            0x2
-#define GC_USB_DOEPTSIZ10_RXDPID_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ10_RXDPID_OFFSET          0xc50
-#define GC_USB_DOEPDMA10_DMAADDR_LSB             0x0
-#define GC_USB_DOEPDMA10_DMAADDR_MASK            0xffffffff
-#define GC_USB_DOEPDMA10_DMAADDR_SIZE            0x20
-#define GC_USB_DOEPDMA10_DMAADDR_DEFAULT         0x0
-#define GC_USB_DOEPDMA10_DMAADDR_OFFSET          0xc54
-#define GC_USB_DOEPDMAB10_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DOEPDMAB10_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DOEPDMAB10_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DOEPDMAB10_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DOEPDMAB10_DMABUFFERADDR_OFFSET   0xc5c
-#define GC_USB_DOEPCTL11_MPS_LSB                 0x0
-#define GC_USB_DOEPCTL11_MPS_MASK                0x7ff
-#define GC_USB_DOEPCTL11_MPS_SIZE                0xb
-#define GC_USB_DOEPCTL11_MPS_DEFAULT             0x0
-#define GC_USB_DOEPCTL11_MPS_OFFSET              0xc60
-#define GC_USB_DOEPCTL11_USBACTEP_LSB            0xf
-#define GC_USB_DOEPCTL11_USBACTEP_MASK           0x8000
-#define GC_USB_DOEPCTL11_USBACTEP_SIZE           0x1
-#define GC_USB_DOEPCTL11_USBACTEP_DEFAULT        0x0
-#define GC_USB_DOEPCTL11_USBACTEP_OFFSET         0xc60
-#define GC_USB_DOEPCTL11_DPID_LSB                0x10
-#define GC_USB_DOEPCTL11_DPID_MASK               0x10000
-#define GC_USB_DOEPCTL11_DPID_SIZE               0x1
-#define GC_USB_DOEPCTL11_DPID_DEFAULT            0x0
-#define GC_USB_DOEPCTL11_DPID_OFFSET             0xc60
-#define GC_USB_DOEPCTL11_NAKSTS_LSB              0x11
-#define GC_USB_DOEPCTL11_NAKSTS_MASK             0x20000
-#define GC_USB_DOEPCTL11_NAKSTS_SIZE             0x1
-#define GC_USB_DOEPCTL11_NAKSTS_DEFAULT          0x0
-#define GC_USB_DOEPCTL11_NAKSTS_OFFSET           0xc60
-#define GC_USB_DOEPCTL11_EPTYPE_LSB              0x12
-#define GC_USB_DOEPCTL11_EPTYPE_MASK             0xc0000
-#define GC_USB_DOEPCTL11_EPTYPE_SIZE             0x2
-#define GC_USB_DOEPCTL11_EPTYPE_DEFAULT          0x0
-#define GC_USB_DOEPCTL11_EPTYPE_OFFSET           0xc60
-#define GC_USB_DOEPCTL11_SNP_LSB                 0x14
-#define GC_USB_DOEPCTL11_SNP_MASK                0x100000
-#define GC_USB_DOEPCTL11_SNP_SIZE                0x1
-#define GC_USB_DOEPCTL11_SNP_DEFAULT             0x0
-#define GC_USB_DOEPCTL11_SNP_OFFSET              0xc60
-#define GC_USB_DOEPCTL11_STALL_LSB               0x15
-#define GC_USB_DOEPCTL11_STALL_MASK              0x200000
-#define GC_USB_DOEPCTL11_STALL_SIZE              0x1
-#define GC_USB_DOEPCTL11_STALL_DEFAULT           0x0
-#define GC_USB_DOEPCTL11_STALL_OFFSET            0xc60
-#define GC_USB_DOEPCTL11_CNAK_LSB                0x1a
-#define GC_USB_DOEPCTL11_CNAK_MASK               0x4000000
-#define GC_USB_DOEPCTL11_CNAK_SIZE               0x1
-#define GC_USB_DOEPCTL11_CNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL11_CNAK_OFFSET             0xc60
-#define GC_USB_DOEPCTL11_SNAK_LSB                0x1b
-#define GC_USB_DOEPCTL11_SNAK_MASK               0x8000000
-#define GC_USB_DOEPCTL11_SNAK_SIZE               0x1
-#define GC_USB_DOEPCTL11_SNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL11_SNAK_OFFSET             0xc60
-#define GC_USB_DOEPCTL11_SETD0PID_LSB            0x1c
-#define GC_USB_DOEPCTL11_SETD0PID_MASK           0x10000000
-#define GC_USB_DOEPCTL11_SETD0PID_SIZE           0x1
-#define GC_USB_DOEPCTL11_SETD0PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL11_SETD0PID_OFFSET         0xc60
-#define GC_USB_DOEPCTL11_SETD1PID_LSB            0x1d
-#define GC_USB_DOEPCTL11_SETD1PID_MASK           0x20000000
-#define GC_USB_DOEPCTL11_SETD1PID_SIZE           0x1
-#define GC_USB_DOEPCTL11_SETD1PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL11_SETD1PID_OFFSET         0xc60
-#define GC_USB_DOEPCTL11_EPDIS_LSB               0x1e
-#define GC_USB_DOEPCTL11_EPDIS_MASK              0x40000000
-#define GC_USB_DOEPCTL11_EPDIS_SIZE              0x1
-#define GC_USB_DOEPCTL11_EPDIS_DEFAULT           0x0
-#define GC_USB_DOEPCTL11_EPDIS_OFFSET            0xc60
-#define GC_USB_DOEPCTL11_EPENA_LSB               0x1f
-#define GC_USB_DOEPCTL11_EPENA_MASK              0x80000000
-#define GC_USB_DOEPCTL11_EPENA_SIZE              0x1
-#define GC_USB_DOEPCTL11_EPENA_DEFAULT           0x0
-#define GC_USB_DOEPCTL11_EPENA_OFFSET            0xc60
-#define GC_USB_DOEPINT11_XFERCOMPL_LSB           0x0
-#define GC_USB_DOEPINT11_XFERCOMPL_MASK          0x1
-#define GC_USB_DOEPINT11_XFERCOMPL_SIZE          0x1
-#define GC_USB_DOEPINT11_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DOEPINT11_XFERCOMPL_OFFSET        0xc68
-#define GC_USB_DOEPINT11_EPDISBLD_LSB            0x1
-#define GC_USB_DOEPINT11_EPDISBLD_MASK           0x2
-#define GC_USB_DOEPINT11_EPDISBLD_SIZE           0x1
-#define GC_USB_DOEPINT11_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DOEPINT11_EPDISBLD_OFFSET         0xc68
-#define GC_USB_DOEPINT11_AHBERR_LSB              0x2
-#define GC_USB_DOEPINT11_AHBERR_MASK             0x4
-#define GC_USB_DOEPINT11_AHBERR_SIZE             0x1
-#define GC_USB_DOEPINT11_AHBERR_DEFAULT          0x0
-#define GC_USB_DOEPINT11_AHBERR_OFFSET           0xc68
-#define GC_USB_DOEPINT11_SETUP_LSB               0x3
-#define GC_USB_DOEPINT11_SETUP_MASK              0x8
-#define GC_USB_DOEPINT11_SETUP_SIZE              0x1
-#define GC_USB_DOEPINT11_SETUP_DEFAULT           0x0
-#define GC_USB_DOEPINT11_SETUP_OFFSET            0xc68
-#define GC_USB_DOEPINT11_OUTTKNEPDIS_LSB         0x4
-#define GC_USB_DOEPINT11_OUTTKNEPDIS_MASK        0x10
-#define GC_USB_DOEPINT11_OUTTKNEPDIS_SIZE        0x1
-#define GC_USB_DOEPINT11_OUTTKNEPDIS_DEFAULT     0x0
-#define GC_USB_DOEPINT11_OUTTKNEPDIS_OFFSET      0xc68
-#define GC_USB_DOEPINT11_STSPHSERCVD_LSB         0x5
-#define GC_USB_DOEPINT11_STSPHSERCVD_MASK        0x20
-#define GC_USB_DOEPINT11_STSPHSERCVD_SIZE        0x1
-#define GC_USB_DOEPINT11_STSPHSERCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT11_STSPHSERCVD_OFFSET      0xc68
-#define GC_USB_DOEPINT11_BACK2BACKSETUP_LSB      0x6
-#define GC_USB_DOEPINT11_BACK2BACKSETUP_MASK     0x40
-#define GC_USB_DOEPINT11_BACK2BACKSETUP_SIZE     0x1
-#define GC_USB_DOEPINT11_BACK2BACKSETUP_DEFAULT  0x0
-#define GC_USB_DOEPINT11_BACK2BACKSETUP_OFFSET   0xc68
-#define GC_USB_DOEPINT11_OUTPKTERR_LSB           0x8
-#define GC_USB_DOEPINT11_OUTPKTERR_MASK          0x100
-#define GC_USB_DOEPINT11_OUTPKTERR_SIZE          0x1
-#define GC_USB_DOEPINT11_OUTPKTERR_DEFAULT       0x0
-#define GC_USB_DOEPINT11_OUTPKTERR_OFFSET        0xc68
-#define GC_USB_DOEPINT11_BNAINTR_LSB             0x9
-#define GC_USB_DOEPINT11_BNAINTR_MASK            0x200
-#define GC_USB_DOEPINT11_BNAINTR_SIZE            0x1
-#define GC_USB_DOEPINT11_BNAINTR_DEFAULT         0x0
-#define GC_USB_DOEPINT11_BNAINTR_OFFSET          0xc68
-#define GC_USB_DOEPINT11_PKTDRPSTS_LSB           0xb
-#define GC_USB_DOEPINT11_PKTDRPSTS_MASK          0x800
-#define GC_USB_DOEPINT11_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DOEPINT11_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DOEPINT11_PKTDRPSTS_OFFSET        0xc68
-#define GC_USB_DOEPINT11_BBLEERR_LSB             0xc
-#define GC_USB_DOEPINT11_BBLEERR_MASK            0x1000
-#define GC_USB_DOEPINT11_BBLEERR_SIZE            0x1
-#define GC_USB_DOEPINT11_BBLEERR_DEFAULT         0x0
-#define GC_USB_DOEPINT11_BBLEERR_OFFSET          0xc68
-#define GC_USB_DOEPINT11_NAKINTRPT_LSB           0xd
-#define GC_USB_DOEPINT11_NAKINTRPT_MASK          0x2000
-#define GC_USB_DOEPINT11_NAKINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT11_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT11_NAKINTRPT_OFFSET        0xc68
-#define GC_USB_DOEPINT11_NYETINTRPT_LSB          0xe
-#define GC_USB_DOEPINT11_NYETINTRPT_MASK         0x4000
-#define GC_USB_DOEPINT11_NYETINTRPT_SIZE         0x1
-#define GC_USB_DOEPINT11_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DOEPINT11_NYETINTRPT_OFFSET       0xc68
-#define GC_USB_DOEPINT11_STUPPKTRCVD_LSB         0xf
-#define GC_USB_DOEPINT11_STUPPKTRCVD_MASK        0x8000
-#define GC_USB_DOEPINT11_STUPPKTRCVD_SIZE        0x1
-#define GC_USB_DOEPINT11_STUPPKTRCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT11_STUPPKTRCVD_OFFSET      0xc68
-#define GC_USB_DOEPTSIZ11_XFERSIZE_LSB           0x0
-#define GC_USB_DOEPTSIZ11_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DOEPTSIZ11_XFERSIZE_SIZE          0x13
-#define GC_USB_DOEPTSIZ11_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DOEPTSIZ11_XFERSIZE_OFFSET        0xc70
-#define GC_USB_DOEPTSIZ11_PKTCNT_LSB             0x13
-#define GC_USB_DOEPTSIZ11_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DOEPTSIZ11_PKTCNT_SIZE            0xa
-#define GC_USB_DOEPTSIZ11_PKTCNT_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ11_PKTCNT_OFFSET          0xc70
-#define GC_USB_DOEPTSIZ11_RXDPID_LSB             0x1d
-#define GC_USB_DOEPTSIZ11_RXDPID_MASK            0x60000000
-#define GC_USB_DOEPTSIZ11_RXDPID_SIZE            0x2
-#define GC_USB_DOEPTSIZ11_RXDPID_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ11_RXDPID_OFFSET          0xc70
-#define GC_USB_DOEPDMA11_DMAADDR_LSB             0x0
-#define GC_USB_DOEPDMA11_DMAADDR_MASK            0xffffffff
-#define GC_USB_DOEPDMA11_DMAADDR_SIZE            0x20
-#define GC_USB_DOEPDMA11_DMAADDR_DEFAULT         0x0
-#define GC_USB_DOEPDMA11_DMAADDR_OFFSET          0xc74
-#define GC_USB_DOEPDMAB11_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DOEPDMAB11_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DOEPDMAB11_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DOEPDMAB11_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DOEPDMAB11_DMABUFFERADDR_OFFSET   0xc7c
-#define GC_USB_DOEPCTL12_MPS_LSB                 0x0
-#define GC_USB_DOEPCTL12_MPS_MASK                0x7ff
-#define GC_USB_DOEPCTL12_MPS_SIZE                0xb
-#define GC_USB_DOEPCTL12_MPS_DEFAULT             0x0
-#define GC_USB_DOEPCTL12_MPS_OFFSET              0xc80
-#define GC_USB_DOEPCTL12_USBACTEP_LSB            0xf
-#define GC_USB_DOEPCTL12_USBACTEP_MASK           0x8000
-#define GC_USB_DOEPCTL12_USBACTEP_SIZE           0x1
-#define GC_USB_DOEPCTL12_USBACTEP_DEFAULT        0x0
-#define GC_USB_DOEPCTL12_USBACTEP_OFFSET         0xc80
-#define GC_USB_DOEPCTL12_DPID_LSB                0x10
-#define GC_USB_DOEPCTL12_DPID_MASK               0x10000
-#define GC_USB_DOEPCTL12_DPID_SIZE               0x1
-#define GC_USB_DOEPCTL12_DPID_DEFAULT            0x0
-#define GC_USB_DOEPCTL12_DPID_OFFSET             0xc80
-#define GC_USB_DOEPCTL12_NAKSTS_LSB              0x11
-#define GC_USB_DOEPCTL12_NAKSTS_MASK             0x20000
-#define GC_USB_DOEPCTL12_NAKSTS_SIZE             0x1
-#define GC_USB_DOEPCTL12_NAKSTS_DEFAULT          0x0
-#define GC_USB_DOEPCTL12_NAKSTS_OFFSET           0xc80
-#define GC_USB_DOEPCTL12_EPTYPE_LSB              0x12
-#define GC_USB_DOEPCTL12_EPTYPE_MASK             0xc0000
-#define GC_USB_DOEPCTL12_EPTYPE_SIZE             0x2
-#define GC_USB_DOEPCTL12_EPTYPE_DEFAULT          0x0
-#define GC_USB_DOEPCTL12_EPTYPE_OFFSET           0xc80
-#define GC_USB_DOEPCTL12_SNP_LSB                 0x14
-#define GC_USB_DOEPCTL12_SNP_MASK                0x100000
-#define GC_USB_DOEPCTL12_SNP_SIZE                0x1
-#define GC_USB_DOEPCTL12_SNP_DEFAULT             0x0
-#define GC_USB_DOEPCTL12_SNP_OFFSET              0xc80
-#define GC_USB_DOEPCTL12_STALL_LSB               0x15
-#define GC_USB_DOEPCTL12_STALL_MASK              0x200000
-#define GC_USB_DOEPCTL12_STALL_SIZE              0x1
-#define GC_USB_DOEPCTL12_STALL_DEFAULT           0x0
-#define GC_USB_DOEPCTL12_STALL_OFFSET            0xc80
-#define GC_USB_DOEPCTL12_CNAK_LSB                0x1a
-#define GC_USB_DOEPCTL12_CNAK_MASK               0x4000000
-#define GC_USB_DOEPCTL12_CNAK_SIZE               0x1
-#define GC_USB_DOEPCTL12_CNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL12_CNAK_OFFSET             0xc80
-#define GC_USB_DOEPCTL12_SNAK_LSB                0x1b
-#define GC_USB_DOEPCTL12_SNAK_MASK               0x8000000
-#define GC_USB_DOEPCTL12_SNAK_SIZE               0x1
-#define GC_USB_DOEPCTL12_SNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL12_SNAK_OFFSET             0xc80
-#define GC_USB_DOEPCTL12_SETD0PID_LSB            0x1c
-#define GC_USB_DOEPCTL12_SETD0PID_MASK           0x10000000
-#define GC_USB_DOEPCTL12_SETD0PID_SIZE           0x1
-#define GC_USB_DOEPCTL12_SETD0PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL12_SETD0PID_OFFSET         0xc80
-#define GC_USB_DOEPCTL12_SETD1PID_LSB            0x1d
-#define GC_USB_DOEPCTL12_SETD1PID_MASK           0x20000000
-#define GC_USB_DOEPCTL12_SETD1PID_SIZE           0x1
-#define GC_USB_DOEPCTL12_SETD1PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL12_SETD1PID_OFFSET         0xc80
-#define GC_USB_DOEPCTL12_EPDIS_LSB               0x1e
-#define GC_USB_DOEPCTL12_EPDIS_MASK              0x40000000
-#define GC_USB_DOEPCTL12_EPDIS_SIZE              0x1
-#define GC_USB_DOEPCTL12_EPDIS_DEFAULT           0x0
-#define GC_USB_DOEPCTL12_EPDIS_OFFSET            0xc80
-#define GC_USB_DOEPCTL12_EPENA_LSB               0x1f
-#define GC_USB_DOEPCTL12_EPENA_MASK              0x80000000
-#define GC_USB_DOEPCTL12_EPENA_SIZE              0x1
-#define GC_USB_DOEPCTL12_EPENA_DEFAULT           0x0
-#define GC_USB_DOEPCTL12_EPENA_OFFSET            0xc80
-#define GC_USB_DOEPINT12_XFERCOMPL_LSB           0x0
-#define GC_USB_DOEPINT12_XFERCOMPL_MASK          0x1
-#define GC_USB_DOEPINT12_XFERCOMPL_SIZE          0x1
-#define GC_USB_DOEPINT12_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DOEPINT12_XFERCOMPL_OFFSET        0xc88
-#define GC_USB_DOEPINT12_EPDISBLD_LSB            0x1
-#define GC_USB_DOEPINT12_EPDISBLD_MASK           0x2
-#define GC_USB_DOEPINT12_EPDISBLD_SIZE           0x1
-#define GC_USB_DOEPINT12_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DOEPINT12_EPDISBLD_OFFSET         0xc88
-#define GC_USB_DOEPINT12_AHBERR_LSB              0x2
-#define GC_USB_DOEPINT12_AHBERR_MASK             0x4
-#define GC_USB_DOEPINT12_AHBERR_SIZE             0x1
-#define GC_USB_DOEPINT12_AHBERR_DEFAULT          0x0
-#define GC_USB_DOEPINT12_AHBERR_OFFSET           0xc88
-#define GC_USB_DOEPINT12_SETUP_LSB               0x3
-#define GC_USB_DOEPINT12_SETUP_MASK              0x8
-#define GC_USB_DOEPINT12_SETUP_SIZE              0x1
-#define GC_USB_DOEPINT12_SETUP_DEFAULT           0x0
-#define GC_USB_DOEPINT12_SETUP_OFFSET            0xc88
-#define GC_USB_DOEPINT12_OUTTKNEPDIS_LSB         0x4
-#define GC_USB_DOEPINT12_OUTTKNEPDIS_MASK        0x10
-#define GC_USB_DOEPINT12_OUTTKNEPDIS_SIZE        0x1
-#define GC_USB_DOEPINT12_OUTTKNEPDIS_DEFAULT     0x0
-#define GC_USB_DOEPINT12_OUTTKNEPDIS_OFFSET      0xc88
-#define GC_USB_DOEPINT12_STSPHSERCVD_LSB         0x5
-#define GC_USB_DOEPINT12_STSPHSERCVD_MASK        0x20
-#define GC_USB_DOEPINT12_STSPHSERCVD_SIZE        0x1
-#define GC_USB_DOEPINT12_STSPHSERCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT12_STSPHSERCVD_OFFSET      0xc88
-#define GC_USB_DOEPINT12_BACK2BACKSETUP_LSB      0x6
-#define GC_USB_DOEPINT12_BACK2BACKSETUP_MASK     0x40
-#define GC_USB_DOEPINT12_BACK2BACKSETUP_SIZE     0x1
-#define GC_USB_DOEPINT12_BACK2BACKSETUP_DEFAULT  0x0
-#define GC_USB_DOEPINT12_BACK2BACKSETUP_OFFSET   0xc88
-#define GC_USB_DOEPINT12_OUTPKTERR_LSB           0x8
-#define GC_USB_DOEPINT12_OUTPKTERR_MASK          0x100
-#define GC_USB_DOEPINT12_OUTPKTERR_SIZE          0x1
-#define GC_USB_DOEPINT12_OUTPKTERR_DEFAULT       0x0
-#define GC_USB_DOEPINT12_OUTPKTERR_OFFSET        0xc88
-#define GC_USB_DOEPINT12_BNAINTR_LSB             0x9
-#define GC_USB_DOEPINT12_BNAINTR_MASK            0x200
-#define GC_USB_DOEPINT12_BNAINTR_SIZE            0x1
-#define GC_USB_DOEPINT12_BNAINTR_DEFAULT         0x0
-#define GC_USB_DOEPINT12_BNAINTR_OFFSET          0xc88
-#define GC_USB_DOEPINT12_PKTDRPSTS_LSB           0xb
-#define GC_USB_DOEPINT12_PKTDRPSTS_MASK          0x800
-#define GC_USB_DOEPINT12_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DOEPINT12_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DOEPINT12_PKTDRPSTS_OFFSET        0xc88
-#define GC_USB_DOEPINT12_BBLEERR_LSB             0xc
-#define GC_USB_DOEPINT12_BBLEERR_MASK            0x1000
-#define GC_USB_DOEPINT12_BBLEERR_SIZE            0x1
-#define GC_USB_DOEPINT12_BBLEERR_DEFAULT         0x0
-#define GC_USB_DOEPINT12_BBLEERR_OFFSET          0xc88
-#define GC_USB_DOEPINT12_NAKINTRPT_LSB           0xd
-#define GC_USB_DOEPINT12_NAKINTRPT_MASK          0x2000
-#define GC_USB_DOEPINT12_NAKINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT12_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT12_NAKINTRPT_OFFSET        0xc88
-#define GC_USB_DOEPINT12_NYETINTRPT_LSB          0xe
-#define GC_USB_DOEPINT12_NYETINTRPT_MASK         0x4000
-#define GC_USB_DOEPINT12_NYETINTRPT_SIZE         0x1
-#define GC_USB_DOEPINT12_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DOEPINT12_NYETINTRPT_OFFSET       0xc88
-#define GC_USB_DOEPINT12_STUPPKTRCVD_LSB         0xf
-#define GC_USB_DOEPINT12_STUPPKTRCVD_MASK        0x8000
-#define GC_USB_DOEPINT12_STUPPKTRCVD_SIZE        0x1
-#define GC_USB_DOEPINT12_STUPPKTRCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT12_STUPPKTRCVD_OFFSET      0xc88
-#define GC_USB_DOEPTSIZ12_XFERSIZE_LSB           0x0
-#define GC_USB_DOEPTSIZ12_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DOEPTSIZ12_XFERSIZE_SIZE          0x13
-#define GC_USB_DOEPTSIZ12_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DOEPTSIZ12_XFERSIZE_OFFSET        0xc90
-#define GC_USB_DOEPTSIZ12_PKTCNT_LSB             0x13
-#define GC_USB_DOEPTSIZ12_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DOEPTSIZ12_PKTCNT_SIZE            0xa
-#define GC_USB_DOEPTSIZ12_PKTCNT_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ12_PKTCNT_OFFSET          0xc90
-#define GC_USB_DOEPTSIZ12_RXDPID_LSB             0x1d
-#define GC_USB_DOEPTSIZ12_RXDPID_MASK            0x60000000
-#define GC_USB_DOEPTSIZ12_RXDPID_SIZE            0x2
-#define GC_USB_DOEPTSIZ12_RXDPID_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ12_RXDPID_OFFSET          0xc90
-#define GC_USB_DOEPDMA12_DMAADDR_LSB             0x0
-#define GC_USB_DOEPDMA12_DMAADDR_MASK            0xffffffff
-#define GC_USB_DOEPDMA12_DMAADDR_SIZE            0x20
-#define GC_USB_DOEPDMA12_DMAADDR_DEFAULT         0x0
-#define GC_USB_DOEPDMA12_DMAADDR_OFFSET          0xc94
-#define GC_USB_DOEPDMAB12_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DOEPDMAB12_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DOEPDMAB12_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DOEPDMAB12_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DOEPDMAB12_DMABUFFERADDR_OFFSET   0xc9c
-#define GC_USB_DOEPCTL13_MPS_LSB                 0x0
-#define GC_USB_DOEPCTL13_MPS_MASK                0x7ff
-#define GC_USB_DOEPCTL13_MPS_SIZE                0xb
-#define GC_USB_DOEPCTL13_MPS_DEFAULT             0x0
-#define GC_USB_DOEPCTL13_MPS_OFFSET              0xca0
-#define GC_USB_DOEPCTL13_USBACTEP_LSB            0xf
-#define GC_USB_DOEPCTL13_USBACTEP_MASK           0x8000
-#define GC_USB_DOEPCTL13_USBACTEP_SIZE           0x1
-#define GC_USB_DOEPCTL13_USBACTEP_DEFAULT        0x0
-#define GC_USB_DOEPCTL13_USBACTEP_OFFSET         0xca0
-#define GC_USB_DOEPCTL13_DPID_LSB                0x10
-#define GC_USB_DOEPCTL13_DPID_MASK               0x10000
-#define GC_USB_DOEPCTL13_DPID_SIZE               0x1
-#define GC_USB_DOEPCTL13_DPID_DEFAULT            0x0
-#define GC_USB_DOEPCTL13_DPID_OFFSET             0xca0
-#define GC_USB_DOEPCTL13_NAKSTS_LSB              0x11
-#define GC_USB_DOEPCTL13_NAKSTS_MASK             0x20000
-#define GC_USB_DOEPCTL13_NAKSTS_SIZE             0x1
-#define GC_USB_DOEPCTL13_NAKSTS_DEFAULT          0x0
-#define GC_USB_DOEPCTL13_NAKSTS_OFFSET           0xca0
-#define GC_USB_DOEPCTL13_EPTYPE_LSB              0x12
-#define GC_USB_DOEPCTL13_EPTYPE_MASK             0xc0000
-#define GC_USB_DOEPCTL13_EPTYPE_SIZE             0x2
-#define GC_USB_DOEPCTL13_EPTYPE_DEFAULT          0x0
-#define GC_USB_DOEPCTL13_EPTYPE_OFFSET           0xca0
-#define GC_USB_DOEPCTL13_SNP_LSB                 0x14
-#define GC_USB_DOEPCTL13_SNP_MASK                0x100000
-#define GC_USB_DOEPCTL13_SNP_SIZE                0x1
-#define GC_USB_DOEPCTL13_SNP_DEFAULT             0x0
-#define GC_USB_DOEPCTL13_SNP_OFFSET              0xca0
-#define GC_USB_DOEPCTL13_STALL_LSB               0x15
-#define GC_USB_DOEPCTL13_STALL_MASK              0x200000
-#define GC_USB_DOEPCTL13_STALL_SIZE              0x1
-#define GC_USB_DOEPCTL13_STALL_DEFAULT           0x0
-#define GC_USB_DOEPCTL13_STALL_OFFSET            0xca0
-#define GC_USB_DOEPCTL13_CNAK_LSB                0x1a
-#define GC_USB_DOEPCTL13_CNAK_MASK               0x4000000
-#define GC_USB_DOEPCTL13_CNAK_SIZE               0x1
-#define GC_USB_DOEPCTL13_CNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL13_CNAK_OFFSET             0xca0
-#define GC_USB_DOEPCTL13_SNAK_LSB                0x1b
-#define GC_USB_DOEPCTL13_SNAK_MASK               0x8000000
-#define GC_USB_DOEPCTL13_SNAK_SIZE               0x1
-#define GC_USB_DOEPCTL13_SNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL13_SNAK_OFFSET             0xca0
-#define GC_USB_DOEPCTL13_SETD0PID_LSB            0x1c
-#define GC_USB_DOEPCTL13_SETD0PID_MASK           0x10000000
-#define GC_USB_DOEPCTL13_SETD0PID_SIZE           0x1
-#define GC_USB_DOEPCTL13_SETD0PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL13_SETD0PID_OFFSET         0xca0
-#define GC_USB_DOEPCTL13_SETD1PID_LSB            0x1d
-#define GC_USB_DOEPCTL13_SETD1PID_MASK           0x20000000
-#define GC_USB_DOEPCTL13_SETD1PID_SIZE           0x1
-#define GC_USB_DOEPCTL13_SETD1PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL13_SETD1PID_OFFSET         0xca0
-#define GC_USB_DOEPCTL13_EPDIS_LSB               0x1e
-#define GC_USB_DOEPCTL13_EPDIS_MASK              0x40000000
-#define GC_USB_DOEPCTL13_EPDIS_SIZE              0x1
-#define GC_USB_DOEPCTL13_EPDIS_DEFAULT           0x0
-#define GC_USB_DOEPCTL13_EPDIS_OFFSET            0xca0
-#define GC_USB_DOEPCTL13_EPENA_LSB               0x1f
-#define GC_USB_DOEPCTL13_EPENA_MASK              0x80000000
-#define GC_USB_DOEPCTL13_EPENA_SIZE              0x1
-#define GC_USB_DOEPCTL13_EPENA_DEFAULT           0x0
-#define GC_USB_DOEPCTL13_EPENA_OFFSET            0xca0
-#define GC_USB_DOEPINT13_XFERCOMPL_LSB           0x0
-#define GC_USB_DOEPINT13_XFERCOMPL_MASK          0x1
-#define GC_USB_DOEPINT13_XFERCOMPL_SIZE          0x1
-#define GC_USB_DOEPINT13_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DOEPINT13_XFERCOMPL_OFFSET        0xca8
-#define GC_USB_DOEPINT13_EPDISBLD_LSB            0x1
-#define GC_USB_DOEPINT13_EPDISBLD_MASK           0x2
-#define GC_USB_DOEPINT13_EPDISBLD_SIZE           0x1
-#define GC_USB_DOEPINT13_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DOEPINT13_EPDISBLD_OFFSET         0xca8
-#define GC_USB_DOEPINT13_AHBERR_LSB              0x2
-#define GC_USB_DOEPINT13_AHBERR_MASK             0x4
-#define GC_USB_DOEPINT13_AHBERR_SIZE             0x1
-#define GC_USB_DOEPINT13_AHBERR_DEFAULT          0x0
-#define GC_USB_DOEPINT13_AHBERR_OFFSET           0xca8
-#define GC_USB_DOEPINT13_SETUP_LSB               0x3
-#define GC_USB_DOEPINT13_SETUP_MASK              0x8
-#define GC_USB_DOEPINT13_SETUP_SIZE              0x1
-#define GC_USB_DOEPINT13_SETUP_DEFAULT           0x0
-#define GC_USB_DOEPINT13_SETUP_OFFSET            0xca8
-#define GC_USB_DOEPINT13_OUTTKNEPDIS_LSB         0x4
-#define GC_USB_DOEPINT13_OUTTKNEPDIS_MASK        0x10
-#define GC_USB_DOEPINT13_OUTTKNEPDIS_SIZE        0x1
-#define GC_USB_DOEPINT13_OUTTKNEPDIS_DEFAULT     0x0
-#define GC_USB_DOEPINT13_OUTTKNEPDIS_OFFSET      0xca8
-#define GC_USB_DOEPINT13_STSPHSERCVD_LSB         0x5
-#define GC_USB_DOEPINT13_STSPHSERCVD_MASK        0x20
-#define GC_USB_DOEPINT13_STSPHSERCVD_SIZE        0x1
-#define GC_USB_DOEPINT13_STSPHSERCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT13_STSPHSERCVD_OFFSET      0xca8
-#define GC_USB_DOEPINT13_BACK2BACKSETUP_LSB      0x6
-#define GC_USB_DOEPINT13_BACK2BACKSETUP_MASK     0x40
-#define GC_USB_DOEPINT13_BACK2BACKSETUP_SIZE     0x1
-#define GC_USB_DOEPINT13_BACK2BACKSETUP_DEFAULT  0x0
-#define GC_USB_DOEPINT13_BACK2BACKSETUP_OFFSET   0xca8
-#define GC_USB_DOEPINT13_OUTPKTERR_LSB           0x8
-#define GC_USB_DOEPINT13_OUTPKTERR_MASK          0x100
-#define GC_USB_DOEPINT13_OUTPKTERR_SIZE          0x1
-#define GC_USB_DOEPINT13_OUTPKTERR_DEFAULT       0x0
-#define GC_USB_DOEPINT13_OUTPKTERR_OFFSET        0xca8
-#define GC_USB_DOEPINT13_BNAINTR_LSB             0x9
-#define GC_USB_DOEPINT13_BNAINTR_MASK            0x200
-#define GC_USB_DOEPINT13_BNAINTR_SIZE            0x1
-#define GC_USB_DOEPINT13_BNAINTR_DEFAULT         0x0
-#define GC_USB_DOEPINT13_BNAINTR_OFFSET          0xca8
-#define GC_USB_DOEPINT13_PKTDRPSTS_LSB           0xb
-#define GC_USB_DOEPINT13_PKTDRPSTS_MASK          0x800
-#define GC_USB_DOEPINT13_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DOEPINT13_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DOEPINT13_PKTDRPSTS_OFFSET        0xca8
-#define GC_USB_DOEPINT13_BBLEERR_LSB             0xc
-#define GC_USB_DOEPINT13_BBLEERR_MASK            0x1000
-#define GC_USB_DOEPINT13_BBLEERR_SIZE            0x1
-#define GC_USB_DOEPINT13_BBLEERR_DEFAULT         0x0
-#define GC_USB_DOEPINT13_BBLEERR_OFFSET          0xca8
-#define GC_USB_DOEPINT13_NAKINTRPT_LSB           0xd
-#define GC_USB_DOEPINT13_NAKINTRPT_MASK          0x2000
-#define GC_USB_DOEPINT13_NAKINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT13_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT13_NAKINTRPT_OFFSET        0xca8
-#define GC_USB_DOEPINT13_NYETINTRPT_LSB          0xe
-#define GC_USB_DOEPINT13_NYETINTRPT_MASK         0x4000
-#define GC_USB_DOEPINT13_NYETINTRPT_SIZE         0x1
-#define GC_USB_DOEPINT13_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DOEPINT13_NYETINTRPT_OFFSET       0xca8
-#define GC_USB_DOEPINT13_STUPPKTRCVD_LSB         0xf
-#define GC_USB_DOEPINT13_STUPPKTRCVD_MASK        0x8000
-#define GC_USB_DOEPINT13_STUPPKTRCVD_SIZE        0x1
-#define GC_USB_DOEPINT13_STUPPKTRCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT13_STUPPKTRCVD_OFFSET      0xca8
-#define GC_USB_DOEPTSIZ13_XFERSIZE_LSB           0x0
-#define GC_USB_DOEPTSIZ13_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DOEPTSIZ13_XFERSIZE_SIZE          0x13
-#define GC_USB_DOEPTSIZ13_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DOEPTSIZ13_XFERSIZE_OFFSET        0xcb0
-#define GC_USB_DOEPTSIZ13_PKTCNT_LSB             0x13
-#define GC_USB_DOEPTSIZ13_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DOEPTSIZ13_PKTCNT_SIZE            0xa
-#define GC_USB_DOEPTSIZ13_PKTCNT_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ13_PKTCNT_OFFSET          0xcb0
-#define GC_USB_DOEPTSIZ13_RXDPID_LSB             0x1d
-#define GC_USB_DOEPTSIZ13_RXDPID_MASK            0x60000000
-#define GC_USB_DOEPTSIZ13_RXDPID_SIZE            0x2
-#define GC_USB_DOEPTSIZ13_RXDPID_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ13_RXDPID_OFFSET          0xcb0
-#define GC_USB_DOEPDMA13_DMAADDR_LSB             0x0
-#define GC_USB_DOEPDMA13_DMAADDR_MASK            0xffffffff
-#define GC_USB_DOEPDMA13_DMAADDR_SIZE            0x20
-#define GC_USB_DOEPDMA13_DMAADDR_DEFAULT         0x0
-#define GC_USB_DOEPDMA13_DMAADDR_OFFSET          0xcb4
-#define GC_USB_DOEPDMAB13_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DOEPDMAB13_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DOEPDMAB13_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DOEPDMAB13_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DOEPDMAB13_DMABUFFERADDR_OFFSET   0xcbc
-#define GC_USB_DOEPCTL14_MPS_LSB                 0x0
-#define GC_USB_DOEPCTL14_MPS_MASK                0x7ff
-#define GC_USB_DOEPCTL14_MPS_SIZE                0xb
-#define GC_USB_DOEPCTL14_MPS_DEFAULT             0x0
-#define GC_USB_DOEPCTL14_MPS_OFFSET              0xcc0
-#define GC_USB_DOEPCTL14_USBACTEP_LSB            0xf
-#define GC_USB_DOEPCTL14_USBACTEP_MASK           0x8000
-#define GC_USB_DOEPCTL14_USBACTEP_SIZE           0x1
-#define GC_USB_DOEPCTL14_USBACTEP_DEFAULT        0x0
-#define GC_USB_DOEPCTL14_USBACTEP_OFFSET         0xcc0
-#define GC_USB_DOEPCTL14_DPID_LSB                0x10
-#define GC_USB_DOEPCTL14_DPID_MASK               0x10000
-#define GC_USB_DOEPCTL14_DPID_SIZE               0x1
-#define GC_USB_DOEPCTL14_DPID_DEFAULT            0x0
-#define GC_USB_DOEPCTL14_DPID_OFFSET             0xcc0
-#define GC_USB_DOEPCTL14_NAKSTS_LSB              0x11
-#define GC_USB_DOEPCTL14_NAKSTS_MASK             0x20000
-#define GC_USB_DOEPCTL14_NAKSTS_SIZE             0x1
-#define GC_USB_DOEPCTL14_NAKSTS_DEFAULT          0x0
-#define GC_USB_DOEPCTL14_NAKSTS_OFFSET           0xcc0
-#define GC_USB_DOEPCTL14_EPTYPE_LSB              0x12
-#define GC_USB_DOEPCTL14_EPTYPE_MASK             0xc0000
-#define GC_USB_DOEPCTL14_EPTYPE_SIZE             0x2
-#define GC_USB_DOEPCTL14_EPTYPE_DEFAULT          0x0
-#define GC_USB_DOEPCTL14_EPTYPE_OFFSET           0xcc0
-#define GC_USB_DOEPCTL14_SNP_LSB                 0x14
-#define GC_USB_DOEPCTL14_SNP_MASK                0x100000
-#define GC_USB_DOEPCTL14_SNP_SIZE                0x1
-#define GC_USB_DOEPCTL14_SNP_DEFAULT             0x0
-#define GC_USB_DOEPCTL14_SNP_OFFSET              0xcc0
-#define GC_USB_DOEPCTL14_STALL_LSB               0x15
-#define GC_USB_DOEPCTL14_STALL_MASK              0x200000
-#define GC_USB_DOEPCTL14_STALL_SIZE              0x1
-#define GC_USB_DOEPCTL14_STALL_DEFAULT           0x0
-#define GC_USB_DOEPCTL14_STALL_OFFSET            0xcc0
-#define GC_USB_DOEPCTL14_CNAK_LSB                0x1a
-#define GC_USB_DOEPCTL14_CNAK_MASK               0x4000000
-#define GC_USB_DOEPCTL14_CNAK_SIZE               0x1
-#define GC_USB_DOEPCTL14_CNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL14_CNAK_OFFSET             0xcc0
-#define GC_USB_DOEPCTL14_SNAK_LSB                0x1b
-#define GC_USB_DOEPCTL14_SNAK_MASK               0x8000000
-#define GC_USB_DOEPCTL14_SNAK_SIZE               0x1
-#define GC_USB_DOEPCTL14_SNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL14_SNAK_OFFSET             0xcc0
-#define GC_USB_DOEPCTL14_SETD0PID_LSB            0x1c
-#define GC_USB_DOEPCTL14_SETD0PID_MASK           0x10000000
-#define GC_USB_DOEPCTL14_SETD0PID_SIZE           0x1
-#define GC_USB_DOEPCTL14_SETD0PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL14_SETD0PID_OFFSET         0xcc0
-#define GC_USB_DOEPCTL14_SETD1PID_LSB            0x1d
-#define GC_USB_DOEPCTL14_SETD1PID_MASK           0x20000000
-#define GC_USB_DOEPCTL14_SETD1PID_SIZE           0x1
-#define GC_USB_DOEPCTL14_SETD1PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL14_SETD1PID_OFFSET         0xcc0
-#define GC_USB_DOEPCTL14_EPDIS_LSB               0x1e
-#define GC_USB_DOEPCTL14_EPDIS_MASK              0x40000000
-#define GC_USB_DOEPCTL14_EPDIS_SIZE              0x1
-#define GC_USB_DOEPCTL14_EPDIS_DEFAULT           0x0
-#define GC_USB_DOEPCTL14_EPDIS_OFFSET            0xcc0
-#define GC_USB_DOEPCTL14_EPENA_LSB               0x1f
-#define GC_USB_DOEPCTL14_EPENA_MASK              0x80000000
-#define GC_USB_DOEPCTL14_EPENA_SIZE              0x1
-#define GC_USB_DOEPCTL14_EPENA_DEFAULT           0x0
-#define GC_USB_DOEPCTL14_EPENA_OFFSET            0xcc0
-#define GC_USB_DOEPINT14_XFERCOMPL_LSB           0x0
-#define GC_USB_DOEPINT14_XFERCOMPL_MASK          0x1
-#define GC_USB_DOEPINT14_XFERCOMPL_SIZE          0x1
-#define GC_USB_DOEPINT14_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DOEPINT14_XFERCOMPL_OFFSET        0xcc8
-#define GC_USB_DOEPINT14_EPDISBLD_LSB            0x1
-#define GC_USB_DOEPINT14_EPDISBLD_MASK           0x2
-#define GC_USB_DOEPINT14_EPDISBLD_SIZE           0x1
-#define GC_USB_DOEPINT14_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DOEPINT14_EPDISBLD_OFFSET         0xcc8
-#define GC_USB_DOEPINT14_AHBERR_LSB              0x2
-#define GC_USB_DOEPINT14_AHBERR_MASK             0x4
-#define GC_USB_DOEPINT14_AHBERR_SIZE             0x1
-#define GC_USB_DOEPINT14_AHBERR_DEFAULT          0x0
-#define GC_USB_DOEPINT14_AHBERR_OFFSET           0xcc8
-#define GC_USB_DOEPINT14_SETUP_LSB               0x3
-#define GC_USB_DOEPINT14_SETUP_MASK              0x8
-#define GC_USB_DOEPINT14_SETUP_SIZE              0x1
-#define GC_USB_DOEPINT14_SETUP_DEFAULT           0x0
-#define GC_USB_DOEPINT14_SETUP_OFFSET            0xcc8
-#define GC_USB_DOEPINT14_OUTTKNEPDIS_LSB         0x4
-#define GC_USB_DOEPINT14_OUTTKNEPDIS_MASK        0x10
-#define GC_USB_DOEPINT14_OUTTKNEPDIS_SIZE        0x1
-#define GC_USB_DOEPINT14_OUTTKNEPDIS_DEFAULT     0x0
-#define GC_USB_DOEPINT14_OUTTKNEPDIS_OFFSET      0xcc8
-#define GC_USB_DOEPINT14_STSPHSERCVD_LSB         0x5
-#define GC_USB_DOEPINT14_STSPHSERCVD_MASK        0x20
-#define GC_USB_DOEPINT14_STSPHSERCVD_SIZE        0x1
-#define GC_USB_DOEPINT14_STSPHSERCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT14_STSPHSERCVD_OFFSET      0xcc8
-#define GC_USB_DOEPINT14_BACK2BACKSETUP_LSB      0x6
-#define GC_USB_DOEPINT14_BACK2BACKSETUP_MASK     0x40
-#define GC_USB_DOEPINT14_BACK2BACKSETUP_SIZE     0x1
-#define GC_USB_DOEPINT14_BACK2BACKSETUP_DEFAULT  0x0
-#define GC_USB_DOEPINT14_BACK2BACKSETUP_OFFSET   0xcc8
-#define GC_USB_DOEPINT14_OUTPKTERR_LSB           0x8
-#define GC_USB_DOEPINT14_OUTPKTERR_MASK          0x100
-#define GC_USB_DOEPINT14_OUTPKTERR_SIZE          0x1
-#define GC_USB_DOEPINT14_OUTPKTERR_DEFAULT       0x0
-#define GC_USB_DOEPINT14_OUTPKTERR_OFFSET        0xcc8
-#define GC_USB_DOEPINT14_BNAINTR_LSB             0x9
-#define GC_USB_DOEPINT14_BNAINTR_MASK            0x200
-#define GC_USB_DOEPINT14_BNAINTR_SIZE            0x1
-#define GC_USB_DOEPINT14_BNAINTR_DEFAULT         0x0
-#define GC_USB_DOEPINT14_BNAINTR_OFFSET          0xcc8
-#define GC_USB_DOEPINT14_PKTDRPSTS_LSB           0xb
-#define GC_USB_DOEPINT14_PKTDRPSTS_MASK          0x800
-#define GC_USB_DOEPINT14_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DOEPINT14_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DOEPINT14_PKTDRPSTS_OFFSET        0xcc8
-#define GC_USB_DOEPINT14_BBLEERR_LSB             0xc
-#define GC_USB_DOEPINT14_BBLEERR_MASK            0x1000
-#define GC_USB_DOEPINT14_BBLEERR_SIZE            0x1
-#define GC_USB_DOEPINT14_BBLEERR_DEFAULT         0x0
-#define GC_USB_DOEPINT14_BBLEERR_OFFSET          0xcc8
-#define GC_USB_DOEPINT14_NAKINTRPT_LSB           0xd
-#define GC_USB_DOEPINT14_NAKINTRPT_MASK          0x2000
-#define GC_USB_DOEPINT14_NAKINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT14_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT14_NAKINTRPT_OFFSET        0xcc8
-#define GC_USB_DOEPINT14_NYETINTRPT_LSB          0xe
-#define GC_USB_DOEPINT14_NYETINTRPT_MASK         0x4000
-#define GC_USB_DOEPINT14_NYETINTRPT_SIZE         0x1
-#define GC_USB_DOEPINT14_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DOEPINT14_NYETINTRPT_OFFSET       0xcc8
-#define GC_USB_DOEPINT14_STUPPKTRCVD_LSB         0xf
-#define GC_USB_DOEPINT14_STUPPKTRCVD_MASK        0x8000
-#define GC_USB_DOEPINT14_STUPPKTRCVD_SIZE        0x1
-#define GC_USB_DOEPINT14_STUPPKTRCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT14_STUPPKTRCVD_OFFSET      0xcc8
-#define GC_USB_DOEPTSIZ14_XFERSIZE_LSB           0x0
-#define GC_USB_DOEPTSIZ14_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DOEPTSIZ14_XFERSIZE_SIZE          0x13
-#define GC_USB_DOEPTSIZ14_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DOEPTSIZ14_XFERSIZE_OFFSET        0xcd0
-#define GC_USB_DOEPTSIZ14_PKTCNT_LSB             0x13
-#define GC_USB_DOEPTSIZ14_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DOEPTSIZ14_PKTCNT_SIZE            0xa
-#define GC_USB_DOEPTSIZ14_PKTCNT_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ14_PKTCNT_OFFSET          0xcd0
-#define GC_USB_DOEPTSIZ14_RXDPID_LSB             0x1d
-#define GC_USB_DOEPTSIZ14_RXDPID_MASK            0x60000000
-#define GC_USB_DOEPTSIZ14_RXDPID_SIZE            0x2
-#define GC_USB_DOEPTSIZ14_RXDPID_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ14_RXDPID_OFFSET          0xcd0
-#define GC_USB_DOEPDMA14_DMAADDR_LSB             0x0
-#define GC_USB_DOEPDMA14_DMAADDR_MASK            0xffffffff
-#define GC_USB_DOEPDMA14_DMAADDR_SIZE            0x20
-#define GC_USB_DOEPDMA14_DMAADDR_DEFAULT         0x0
-#define GC_USB_DOEPDMA14_DMAADDR_OFFSET          0xcd4
-#define GC_USB_DOEPDMAB14_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DOEPDMAB14_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DOEPDMAB14_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DOEPDMAB14_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DOEPDMAB14_DMABUFFERADDR_OFFSET   0xcdc
-#define GC_USB_DOEPCTL15_MPS_LSB                 0x0
-#define GC_USB_DOEPCTL15_MPS_MASK                0x7ff
-#define GC_USB_DOEPCTL15_MPS_SIZE                0xb
-#define GC_USB_DOEPCTL15_MPS_DEFAULT             0x0
-#define GC_USB_DOEPCTL15_MPS_OFFSET              0xce0
-#define GC_USB_DOEPCTL15_USBACTEP_LSB            0xf
-#define GC_USB_DOEPCTL15_USBACTEP_MASK           0x8000
-#define GC_USB_DOEPCTL15_USBACTEP_SIZE           0x1
-#define GC_USB_DOEPCTL15_USBACTEP_DEFAULT        0x0
-#define GC_USB_DOEPCTL15_USBACTEP_OFFSET         0xce0
-#define GC_USB_DOEPCTL15_DPID_LSB                0x10
-#define GC_USB_DOEPCTL15_DPID_MASK               0x10000
-#define GC_USB_DOEPCTL15_DPID_SIZE               0x1
-#define GC_USB_DOEPCTL15_DPID_DEFAULT            0x0
-#define GC_USB_DOEPCTL15_DPID_OFFSET             0xce0
-#define GC_USB_DOEPCTL15_NAKSTS_LSB              0x11
-#define GC_USB_DOEPCTL15_NAKSTS_MASK             0x20000
-#define GC_USB_DOEPCTL15_NAKSTS_SIZE             0x1
-#define GC_USB_DOEPCTL15_NAKSTS_DEFAULT          0x0
-#define GC_USB_DOEPCTL15_NAKSTS_OFFSET           0xce0
-#define GC_USB_DOEPCTL15_EPTYPE_LSB              0x12
-#define GC_USB_DOEPCTL15_EPTYPE_MASK             0xc0000
-#define GC_USB_DOEPCTL15_EPTYPE_SIZE             0x2
-#define GC_USB_DOEPCTL15_EPTYPE_DEFAULT          0x0
-#define GC_USB_DOEPCTL15_EPTYPE_OFFSET           0xce0
-#define GC_USB_DOEPCTL15_SNP_LSB                 0x14
-#define GC_USB_DOEPCTL15_SNP_MASK                0x100000
-#define GC_USB_DOEPCTL15_SNP_SIZE                0x1
-#define GC_USB_DOEPCTL15_SNP_DEFAULT             0x0
-#define GC_USB_DOEPCTL15_SNP_OFFSET              0xce0
-#define GC_USB_DOEPCTL15_STALL_LSB               0x15
-#define GC_USB_DOEPCTL15_STALL_MASK              0x200000
-#define GC_USB_DOEPCTL15_STALL_SIZE              0x1
-#define GC_USB_DOEPCTL15_STALL_DEFAULT           0x0
-#define GC_USB_DOEPCTL15_STALL_OFFSET            0xce0
-#define GC_USB_DOEPCTL15_CNAK_LSB                0x1a
-#define GC_USB_DOEPCTL15_CNAK_MASK               0x4000000
-#define GC_USB_DOEPCTL15_CNAK_SIZE               0x1
-#define GC_USB_DOEPCTL15_CNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL15_CNAK_OFFSET             0xce0
-#define GC_USB_DOEPCTL15_SNAK_LSB                0x1b
-#define GC_USB_DOEPCTL15_SNAK_MASK               0x8000000
-#define GC_USB_DOEPCTL15_SNAK_SIZE               0x1
-#define GC_USB_DOEPCTL15_SNAK_DEFAULT            0x0
-#define GC_USB_DOEPCTL15_SNAK_OFFSET             0xce0
-#define GC_USB_DOEPCTL15_SETD0PID_LSB            0x1c
-#define GC_USB_DOEPCTL15_SETD0PID_MASK           0x10000000
-#define GC_USB_DOEPCTL15_SETD0PID_SIZE           0x1
-#define GC_USB_DOEPCTL15_SETD0PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL15_SETD0PID_OFFSET         0xce0
-#define GC_USB_DOEPCTL15_SETD1PID_LSB            0x1d
-#define GC_USB_DOEPCTL15_SETD1PID_MASK           0x20000000
-#define GC_USB_DOEPCTL15_SETD1PID_SIZE           0x1
-#define GC_USB_DOEPCTL15_SETD1PID_DEFAULT        0x0
-#define GC_USB_DOEPCTL15_SETD1PID_OFFSET         0xce0
-#define GC_USB_DOEPCTL15_EPDIS_LSB               0x1e
-#define GC_USB_DOEPCTL15_EPDIS_MASK              0x40000000
-#define GC_USB_DOEPCTL15_EPDIS_SIZE              0x1
-#define GC_USB_DOEPCTL15_EPDIS_DEFAULT           0x0
-#define GC_USB_DOEPCTL15_EPDIS_OFFSET            0xce0
-#define GC_USB_DOEPCTL15_EPENA_LSB               0x1f
-#define GC_USB_DOEPCTL15_EPENA_MASK              0x80000000
-#define GC_USB_DOEPCTL15_EPENA_SIZE              0x1
-#define GC_USB_DOEPCTL15_EPENA_DEFAULT           0x0
-#define GC_USB_DOEPCTL15_EPENA_OFFSET            0xce0
-#define GC_USB_DOEPINT15_XFERCOMPL_LSB           0x0
-#define GC_USB_DOEPINT15_XFERCOMPL_MASK          0x1
-#define GC_USB_DOEPINT15_XFERCOMPL_SIZE          0x1
-#define GC_USB_DOEPINT15_XFERCOMPL_DEFAULT       0x0
-#define GC_USB_DOEPINT15_XFERCOMPL_OFFSET        0xce8
-#define GC_USB_DOEPINT15_EPDISBLD_LSB            0x1
-#define GC_USB_DOEPINT15_EPDISBLD_MASK           0x2
-#define GC_USB_DOEPINT15_EPDISBLD_SIZE           0x1
-#define GC_USB_DOEPINT15_EPDISBLD_DEFAULT        0x0
-#define GC_USB_DOEPINT15_EPDISBLD_OFFSET         0xce8
-#define GC_USB_DOEPINT15_AHBERR_LSB              0x2
-#define GC_USB_DOEPINT15_AHBERR_MASK             0x4
-#define GC_USB_DOEPINT15_AHBERR_SIZE             0x1
-#define GC_USB_DOEPINT15_AHBERR_DEFAULT          0x0
-#define GC_USB_DOEPINT15_AHBERR_OFFSET           0xce8
-#define GC_USB_DOEPINT15_SETUP_LSB               0x3
-#define GC_USB_DOEPINT15_SETUP_MASK              0x8
-#define GC_USB_DOEPINT15_SETUP_SIZE              0x1
-#define GC_USB_DOEPINT15_SETUP_DEFAULT           0x0
-#define GC_USB_DOEPINT15_SETUP_OFFSET            0xce8
-#define GC_USB_DOEPINT15_OUTTKNEPDIS_LSB         0x4
-#define GC_USB_DOEPINT15_OUTTKNEPDIS_MASK        0x10
-#define GC_USB_DOEPINT15_OUTTKNEPDIS_SIZE        0x1
-#define GC_USB_DOEPINT15_OUTTKNEPDIS_DEFAULT     0x0
-#define GC_USB_DOEPINT15_OUTTKNEPDIS_OFFSET      0xce8
-#define GC_USB_DOEPINT15_STSPHSERCVD_LSB         0x5
-#define GC_USB_DOEPINT15_STSPHSERCVD_MASK        0x20
-#define GC_USB_DOEPINT15_STSPHSERCVD_SIZE        0x1
-#define GC_USB_DOEPINT15_STSPHSERCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT15_STSPHSERCVD_OFFSET      0xce8
-#define GC_USB_DOEPINT15_BACK2BACKSETUP_LSB      0x6
-#define GC_USB_DOEPINT15_BACK2BACKSETUP_MASK     0x40
-#define GC_USB_DOEPINT15_BACK2BACKSETUP_SIZE     0x1
-#define GC_USB_DOEPINT15_BACK2BACKSETUP_DEFAULT  0x0
-#define GC_USB_DOEPINT15_BACK2BACKSETUP_OFFSET   0xce8
-#define GC_USB_DOEPINT15_OUTPKTERR_LSB           0x8
-#define GC_USB_DOEPINT15_OUTPKTERR_MASK          0x100
-#define GC_USB_DOEPINT15_OUTPKTERR_SIZE          0x1
-#define GC_USB_DOEPINT15_OUTPKTERR_DEFAULT       0x0
-#define GC_USB_DOEPINT15_OUTPKTERR_OFFSET        0xce8
-#define GC_USB_DOEPINT15_BNAINTR_LSB             0x9
-#define GC_USB_DOEPINT15_BNAINTR_MASK            0x200
-#define GC_USB_DOEPINT15_BNAINTR_SIZE            0x1
-#define GC_USB_DOEPINT15_BNAINTR_DEFAULT         0x0
-#define GC_USB_DOEPINT15_BNAINTR_OFFSET          0xce8
-#define GC_USB_DOEPINT15_PKTDRPSTS_LSB           0xb
-#define GC_USB_DOEPINT15_PKTDRPSTS_MASK          0x800
-#define GC_USB_DOEPINT15_PKTDRPSTS_SIZE          0x1
-#define GC_USB_DOEPINT15_PKTDRPSTS_DEFAULT       0x0
-#define GC_USB_DOEPINT15_PKTDRPSTS_OFFSET        0xce8
-#define GC_USB_DOEPINT15_BBLEERR_LSB             0xc
-#define GC_USB_DOEPINT15_BBLEERR_MASK            0x1000
-#define GC_USB_DOEPINT15_BBLEERR_SIZE            0x1
-#define GC_USB_DOEPINT15_BBLEERR_DEFAULT         0x0
-#define GC_USB_DOEPINT15_BBLEERR_OFFSET          0xce8
-#define GC_USB_DOEPINT15_NAKINTRPT_LSB           0xd
-#define GC_USB_DOEPINT15_NAKINTRPT_MASK          0x2000
-#define GC_USB_DOEPINT15_NAKINTRPT_SIZE          0x1
-#define GC_USB_DOEPINT15_NAKINTRPT_DEFAULT       0x0
-#define GC_USB_DOEPINT15_NAKINTRPT_OFFSET        0xce8
-#define GC_USB_DOEPINT15_NYETINTRPT_LSB          0xe
-#define GC_USB_DOEPINT15_NYETINTRPT_MASK         0x4000
-#define GC_USB_DOEPINT15_NYETINTRPT_SIZE         0x1
-#define GC_USB_DOEPINT15_NYETINTRPT_DEFAULT      0x0
-#define GC_USB_DOEPINT15_NYETINTRPT_OFFSET       0xce8
-#define GC_USB_DOEPINT15_STUPPKTRCVD_LSB         0xf
-#define GC_USB_DOEPINT15_STUPPKTRCVD_MASK        0x8000
-#define GC_USB_DOEPINT15_STUPPKTRCVD_SIZE        0x1
-#define GC_USB_DOEPINT15_STUPPKTRCVD_DEFAULT     0x0
-#define GC_USB_DOEPINT15_STUPPKTRCVD_OFFSET      0xce8
-#define GC_USB_DOEPTSIZ15_XFERSIZE_LSB           0x0
-#define GC_USB_DOEPTSIZ15_XFERSIZE_MASK          0x7ffff
-#define GC_USB_DOEPTSIZ15_XFERSIZE_SIZE          0x13
-#define GC_USB_DOEPTSIZ15_XFERSIZE_DEFAULT       0x0
-#define GC_USB_DOEPTSIZ15_XFERSIZE_OFFSET        0xcf0
-#define GC_USB_DOEPTSIZ15_PKTCNT_LSB             0x13
-#define GC_USB_DOEPTSIZ15_PKTCNT_MASK            0x1ff80000
-#define GC_USB_DOEPTSIZ15_PKTCNT_SIZE            0xa
-#define GC_USB_DOEPTSIZ15_PKTCNT_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ15_PKTCNT_OFFSET          0xcf0
-#define GC_USB_DOEPTSIZ15_RXDPID_LSB             0x1d
-#define GC_USB_DOEPTSIZ15_RXDPID_MASK            0x60000000
-#define GC_USB_DOEPTSIZ15_RXDPID_SIZE            0x2
-#define GC_USB_DOEPTSIZ15_RXDPID_DEFAULT         0x0
-#define GC_USB_DOEPTSIZ15_RXDPID_OFFSET          0xcf0
-#define GC_USB_DOEPDMA15_DMAADDR_LSB             0x0
-#define GC_USB_DOEPDMA15_DMAADDR_MASK            0xffffffff
-#define GC_USB_DOEPDMA15_DMAADDR_SIZE            0x20
-#define GC_USB_DOEPDMA15_DMAADDR_DEFAULT         0x0
-#define GC_USB_DOEPDMA15_DMAADDR_OFFSET          0xcf4
-#define GC_USB_DOEPDMAB15_DMABUFFERADDR_LSB      0x0
-#define GC_USB_DOEPDMAB15_DMABUFFERADDR_MASK     0xffffffff
-#define GC_USB_DOEPDMAB15_DMABUFFERADDR_SIZE     0x20
-#define GC_USB_DOEPDMAB15_DMABUFFERADDR_DEFAULT  0x0
-#define GC_USB_DOEPDMAB15_DMABUFFERADDR_OFFSET   0xcfc
-#define GC_USB_PCGCCTL_STOPPCLK_LSB              0x0
-#define GC_USB_PCGCCTL_STOPPCLK_MASK             0x1
-#define GC_USB_PCGCCTL_STOPPCLK_SIZE             0x1
-#define GC_USB_PCGCCTL_STOPPCLK_DEFAULT          0x0
-#define GC_USB_PCGCCTL_STOPPCLK_OFFSET           0xe00
-#define GC_USB_PCGCCTL_GATEHCLK_LSB              0x1
-#define GC_USB_PCGCCTL_GATEHCLK_MASK             0x2
-#define GC_USB_PCGCCTL_GATEHCLK_SIZE             0x1
-#define GC_USB_PCGCCTL_GATEHCLK_DEFAULT          0x0
-#define GC_USB_PCGCCTL_GATEHCLK_OFFSET           0xe00
-#define GC_USB_PCGCCTL_PWRCLMP_LSB               0x2
-#define GC_USB_PCGCCTL_PWRCLMP_MASK              0x4
-#define GC_USB_PCGCCTL_PWRCLMP_SIZE              0x1
-#define GC_USB_PCGCCTL_PWRCLMP_DEFAULT           0x0
-#define GC_USB_PCGCCTL_PWRCLMP_OFFSET            0xe00
-#define GC_USB_PCGCCTL_RSTPDWNMODULE_LSB         0x3
-#define GC_USB_PCGCCTL_RSTPDWNMODULE_MASK        0x8
-#define GC_USB_PCGCCTL_RSTPDWNMODULE_SIZE        0x1
-#define GC_USB_PCGCCTL_RSTPDWNMODULE_DEFAULT     0x0
-#define GC_USB_PCGCCTL_RSTPDWNMODULE_OFFSET      0xe00
-#define GC_USB_PCGCCTL_PHYSLEEP_LSB              0x6
-#define GC_USB_PCGCCTL_PHYSLEEP_MASK             0x40
-#define GC_USB_PCGCCTL_PHYSLEEP_SIZE             0x1
-#define GC_USB_PCGCCTL_PHYSLEEP_DEFAULT          0x0
-#define GC_USB_PCGCCTL_PHYSLEEP_OFFSET           0xe00
-#define GC_USB_PCGCCTL_L1SUSPENDED_LSB           0x7
-#define GC_USB_PCGCCTL_L1SUSPENDED_MASK          0x80
-#define GC_USB_PCGCCTL_L1SUSPENDED_SIZE          0x1
-#define GC_USB_PCGCCTL_L1SUSPENDED_DEFAULT       0x0
-#define GC_USB_PCGCCTL_L1SUSPENDED_OFFSET        0xe00
-#define GC_VOLT_VERSION_CHANGE_LSB               0x0
-#define GC_VOLT_VERSION_CHANGE_MASK              0xffffff
-#define GC_VOLT_VERSION_CHANGE_SIZE              0x18
-#define GC_VOLT_VERSION_CHANGE_DEFAULT           0x14125
-#define GC_VOLT_VERSION_CHANGE_OFFSET            0x0
-#define GC_VOLT_VERSION_REVISION_LSB             0x18
-#define GC_VOLT_VERSION_REVISION_MASK            0xff000000
-#define GC_VOLT_VERSION_REVISION_SIZE            0x8
-#define GC_VOLT_VERSION_REVISION_DEFAULT         0x1
-#define GC_VOLT_VERSION_REVISION_OFFSET          0x0
-#define GC_VOLT_ANALOG_CONTROL_VSEN_RSTB_LSB     0x0
-#define GC_VOLT_ANALOG_CONTROL_VSEN_RSTB_MASK    0x1
-#define GC_VOLT_ANALOG_CONTROL_VSEN_RSTB_SIZE    0x1
-#define GC_VOLT_ANALOG_CONTROL_VSEN_RSTB_DEFAULT 0x0
-#define GC_VOLT_ANALOG_CONTROL_VSEN_RSTB_OFFSET  0x8
-#define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_INPUTDC_NEG_LSB 0x1
-#define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_INPUTDC_NEG_MASK 0x3e
-#define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_INPUTDC_NEG_SIZE 0x5
-#define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_INPUTDC_NEG_DEFAULT 0xb
-#define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_INPUTDC_NEG_OFFSET 0x8
-#define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_INPUTDC_POS_LSB 0x6
-#define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_INPUTDC_POS_MASK 0x1c0
-#define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_INPUTDC_POS_SIZE 0x3
-#define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_INPUTDC_POS_DEFAULT 0x4
-#define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_INPUTDC_POS_OFFSET 0x8
-#define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_TH_NEG_LSB 0x9
-#define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_TH_NEG_MASK 0xe00
-#define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_TH_NEG_SIZE 0x3
-#define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_TH_NEG_DEFAULT 0x4
-#define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_TH_NEG_OFFSET 0x8
-#define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_TH_POS_LSB 0xc
-#define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_TH_POS_MASK 0x1f000
-#define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_TH_POS_SIZE 0x5
-#define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_TH_POS_DEFAULT 0xb
-#define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_TH_POS_OFFSET 0x8
-#define GC_VOLT_CONFIG_SERIAL_TEST_EN_LSB        0x0
-#define GC_VOLT_CONFIG_SERIAL_TEST_EN_MASK       0x1
-#define GC_VOLT_CONFIG_SERIAL_TEST_EN_SIZE       0x1
-#define GC_VOLT_CONFIG_SERIAL_TEST_EN_DEFAULT    0x0
-#define GC_VOLT_CONFIG_SERIAL_TEST_EN_OFFSET     0xc
-#define GC_WATCHDOG_WDOGCONTROL_INTEN_LSB        0x0
-#define GC_WATCHDOG_WDOGCONTROL_INTEN_MASK       0x1
-#define GC_WATCHDOG_WDOGCONTROL_INTEN_SIZE       0x1
-#define GC_WATCHDOG_WDOGCONTROL_INTEN_DEFAULT    0x0
-#define GC_WATCHDOG_WDOGCONTROL_INTEN_OFFSET     0x8
-#define GC_WATCHDOG_WDOGCONTROL_RESEN_LSB        0x1
-#define GC_WATCHDOG_WDOGCONTROL_RESEN_MASK       0x2
-#define GC_WATCHDOG_WDOGCONTROL_RESEN_SIZE       0x1
-#define GC_WATCHDOG_WDOGCONTROL_RESEN_DEFAULT    0x0
-#define GC_WATCHDOG_WDOGCONTROL_RESEN_OFFSET     0x8
-#define GC_WATCHDOG_WDOGITOP_WDOGRES_LSB         0x0
-#define GC_WATCHDOG_WDOGITOP_WDOGRES_MASK        0x1
-#define GC_WATCHDOG_WDOGITOP_WDOGRES_SIZE        0x1
-#define GC_WATCHDOG_WDOGITOP_WDOGRES_DEFAULT     0x0
-#define GC_WATCHDOG_WDOGITOP_WDOGRES_OFFSET      0xf04
-#define GC_WATCHDOG_WDOGITOP_WDOGINT_LSB         0x1
-#define GC_WATCHDOG_WDOGITOP_WDOGINT_MASK        0x2
-#define GC_WATCHDOG_WDOGITOP_WDOGINT_SIZE        0x1
-#define GC_WATCHDOG_WDOGITOP_WDOGINT_DEFAULT     0x0
-#define GC_WATCHDOG_WDOGITOP_WDOGINT_OFFSET      0xf04
-#define GC_XO_VERSION_CHANGE_LSB                 0x0
-#define GC_XO_VERSION_CHANGE_MASK                0xffffff
-#define GC_XO_VERSION_CHANGE_SIZE                0x18
-#define GC_XO_VERSION_CHANGE_DEFAULT             0x1424a
-#define GC_XO_VERSION_CHANGE_OFFSET              0x0
-#define GC_XO_VERSION_REVISION_LSB               0x18
-#define GC_XO_VERSION_REVISION_MASK              0xff000000
-#define GC_XO_VERSION_REVISION_SIZE              0x8
-#define GC_XO_VERSION_REVISION_DEFAULT           0x1
-#define GC_XO_VERSION_REVISION_OFFSET            0x0
-#define GC_XO_CLK_JTR_CTRL_HS_SEL_LSB            0x0
-#define GC_XO_CLK_JTR_CTRL_HS_SEL_MASK           0x1
-#define GC_XO_CLK_JTR_CTRL_HS_SEL_SIZE           0x1
-#define GC_XO_CLK_JTR_CTRL_HS_SEL_DEFAULT        0x1
-#define GC_XO_CLK_JTR_CTRL_HS_SEL_OFFSET         0xc
-#define GC_XO_CLK_JTR_CTRL_SEL_LSB               0x1
-#define GC_XO_CLK_JTR_CTRL_SEL_MASK              0x2
-#define GC_XO_CLK_JTR_CTRL_SEL_SIZE              0x1
-#define GC_XO_CLK_JTR_CTRL_SEL_DEFAULT           0x1
-#define GC_XO_CLK_JTR_CTRL_SEL_OFFSET            0xc
-#define GC_XO_CLK_JTR_CURRENT_COARSE_TRIM_LSB    0x0
-#define GC_XO_CLK_JTR_CURRENT_COARSE_TRIM_MASK   0xff
-#define GC_XO_CLK_JTR_CURRENT_COARSE_TRIM_SIZE   0x8
-#define GC_XO_CLK_JTR_CURRENT_COARSE_TRIM_DEFAULT 0x0
-#define GC_XO_CLK_JTR_CURRENT_COARSE_TRIM_OFFSET 0x18
-#define GC_XO_CLK_JTR_CURRENT_FINE_TRIM_LSB      0x8
-#define GC_XO_CLK_JTR_CURRENT_FINE_TRIM_MASK     0xff00
-#define GC_XO_CLK_JTR_CURRENT_FINE_TRIM_SIZE     0x8
-#define GC_XO_CLK_JTR_CURRENT_FINE_TRIM_DEFAULT  0x0
-#define GC_XO_CLK_JTR_CURRENT_FINE_TRIM_OFFSET   0x18
-#define GC_XO_CLK_JTR_TRIM_CTRL_RC_TRIM_EN_LSB   0x0
-#define GC_XO_CLK_JTR_TRIM_CTRL_RC_TRIM_EN_MASK  0x1
-#define GC_XO_CLK_JTR_TRIM_CTRL_RC_TRIM_EN_SIZE  0x1
-#define GC_XO_CLK_JTR_TRIM_CTRL_RC_TRIM_EN_DEFAULT 0x0
-#define GC_XO_CLK_JTR_TRIM_CTRL_RC_TRIM_EN_OFFSET 0x20
-#define GC_XO_CLK_JTR_TRIM_CTRL_RC_INITIAL_TRIM_PERIOD_LSB 0x1
-#define GC_XO_CLK_JTR_TRIM_CTRL_RC_INITIAL_TRIM_PERIOD_MASK 0x1fe
-#define GC_XO_CLK_JTR_TRIM_CTRL_RC_INITIAL_TRIM_PERIOD_SIZE 0x8
-#define GC_XO_CLK_JTR_TRIM_CTRL_RC_INITIAL_TRIM_PERIOD_DEFAULT 0xf
-#define GC_XO_CLK_JTR_TRIM_CTRL_RC_INITIAL_TRIM_PERIOD_OFFSET 0x20
-#define GC_XO_CLK_JTR_TRIM_CTRL_RC_FINE_TRIM_SRC_LSB 0x9
-#define GC_XO_CLK_JTR_TRIM_CTRL_RC_FINE_TRIM_SRC_MASK 0x200
-#define GC_XO_CLK_JTR_TRIM_CTRL_RC_FINE_TRIM_SRC_SIZE 0x1
-#define GC_XO_CLK_JTR_TRIM_CTRL_RC_FINE_TRIM_SRC_DEFAULT 0x0
-#define GC_XO_CLK_JTR_TRIM_CTRL_RC_FINE_TRIM_SRC_OFFSET 0x20
-#define GC_XO_CLK_JTR_TRIM_CTRL_RC_COARSE_TRIM_SRC_LSB 0xa
-#define GC_XO_CLK_JTR_TRIM_CTRL_RC_COARSE_TRIM_SRC_MASK 0xc00
-#define GC_XO_CLK_JTR_TRIM_CTRL_RC_COARSE_TRIM_SRC_SIZE 0x2
-#define GC_XO_CLK_JTR_TRIM_CTRL_RC_COARSE_TRIM_SRC_DEFAULT 0x0
-#define GC_XO_CLK_JTR_TRIM_CTRL_RC_COARSE_TRIM_SRC_OFFSET 0x20
-#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_ENABLE_FAST_LSB 0x0
-#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_ENABLE_FAST_MASK 0x1
-#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_ENABLE_FAST_SIZE 0x1
-#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_ENABLE_FAST_DEFAULT 0x0
-#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_ENABLE_FAST_OFFSET 0x74
-#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_ENABLE_SLOW_LSB 0x1
-#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_ENABLE_SLOW_MASK 0x2
-#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_ENABLE_SLOW_SIZE 0x1
-#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_ENABLE_SLOW_DEFAULT 0x0
-#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_ENABLE_SLOW_OFFSET 0x74
-#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_SLOW_MODE_SEL_LSB 0x2
-#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_SLOW_MODE_SEL_MASK 0x4
-#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_SLOW_MODE_SEL_SIZE 0x1
-#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_SLOW_MODE_SEL_DEFAULT 0x0
-#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_SLOW_MODE_SEL_OFFSET 0x74
-#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_MAX_TRIM_SEL_LSB 0x3
-#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_MAX_TRIM_SEL_MASK 0x8
-#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_MAX_TRIM_SEL_SIZE 0x1
-#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_MAX_TRIM_SEL_DEFAULT 0x0
-#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_MAX_TRIM_SEL_OFFSET 0x74
-#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_STOP_ON_NOP_LSB 0x4
-#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_STOP_ON_NOP_MASK 0x10
-#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_STOP_ON_NOP_SIZE 0x1
-#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_STOP_ON_NOP_DEFAULT 0x0
-#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_STOP_ON_NOP_OFFSET 0x74
-#define GC_XO_CLK_JTR_FAST_CALIB0_UPPER_COUNT_LSB 0x0
-#define GC_XO_CLK_JTR_FAST_CALIB0_UPPER_COUNT_MASK 0xffff
-#define GC_XO_CLK_JTR_FAST_CALIB0_UPPER_COUNT_SIZE 0x10
-#define GC_XO_CLK_JTR_FAST_CALIB0_UPPER_COUNT_DEFAULT 0x0
-#define GC_XO_CLK_JTR_FAST_CALIB0_UPPER_COUNT_OFFSET 0x84
-#define GC_XO_CLK_JTR_FAST_CALIB1_UPPER_COUNT_LSB 0x0
-#define GC_XO_CLK_JTR_FAST_CALIB1_UPPER_COUNT_MASK 0xffff
-#define GC_XO_CLK_JTR_FAST_CALIB1_UPPER_COUNT_SIZE 0x10
-#define GC_XO_CLK_JTR_FAST_CALIB1_UPPER_COUNT_DEFAULT 0x0
-#define GC_XO_CLK_JTR_FAST_CALIB1_UPPER_COUNT_OFFSET 0x88
-#define GC_XO_CLK_JTR_FAST_CALIB2_UPPER_COUNT_LSB 0x0
-#define GC_XO_CLK_JTR_FAST_CALIB2_UPPER_COUNT_MASK 0xffff
-#define GC_XO_CLK_JTR_FAST_CALIB2_UPPER_COUNT_SIZE 0x10
-#define GC_XO_CLK_JTR_FAST_CALIB2_UPPER_COUNT_DEFAULT 0x0
-#define GC_XO_CLK_JTR_FAST_CALIB2_UPPER_COUNT_OFFSET 0x8c
-#define GC_XO_CLK_JTR_FAST_CALIB3_UPPER_COUNT_LSB 0x0
-#define GC_XO_CLK_JTR_FAST_CALIB3_UPPER_COUNT_MASK 0xffff
-#define GC_XO_CLK_JTR_FAST_CALIB3_UPPER_COUNT_SIZE 0x10
-#define GC_XO_CLK_JTR_FAST_CALIB3_UPPER_COUNT_DEFAULT 0x0
-#define GC_XO_CLK_JTR_FAST_CALIB3_UPPER_COUNT_OFFSET 0x90
-#define GC_XO_CLK_JTR_FAST_CALIB4_UPPER_COUNT_LSB 0x0
-#define GC_XO_CLK_JTR_FAST_CALIB4_UPPER_COUNT_MASK 0xffff
-#define GC_XO_CLK_JTR_FAST_CALIB4_UPPER_COUNT_SIZE 0x10
-#define GC_XO_CLK_JTR_FAST_CALIB4_UPPER_COUNT_DEFAULT 0x0
-#define GC_XO_CLK_JTR_FAST_CALIB4_UPPER_COUNT_OFFSET 0x94
-#define GC_XO_CLK_JTR_FAST_CALIB5_UPPER_COUNT_LSB 0x0
-#define GC_XO_CLK_JTR_FAST_CALIB5_UPPER_COUNT_MASK 0xffff
-#define GC_XO_CLK_JTR_FAST_CALIB5_UPPER_COUNT_SIZE 0x10
-#define GC_XO_CLK_JTR_FAST_CALIB5_UPPER_COUNT_DEFAULT 0x0
-#define GC_XO_CLK_JTR_FAST_CALIB5_UPPER_COUNT_OFFSET 0x98
-#define GC_XO_CLK_JTR_FAST_CALIB6_UPPER_COUNT_LSB 0x0
-#define GC_XO_CLK_JTR_FAST_CALIB6_UPPER_COUNT_MASK 0xffff
-#define GC_XO_CLK_JTR_FAST_CALIB6_UPPER_COUNT_SIZE 0x10
-#define GC_XO_CLK_JTR_FAST_CALIB6_UPPER_COUNT_DEFAULT 0x0
-#define GC_XO_CLK_JTR_FAST_CALIB6_UPPER_COUNT_OFFSET 0x9c
-#define GC_XO_CLK_JTR_FAST_CALIB7_UPPER_COUNT_LSB 0x0
-#define GC_XO_CLK_JTR_FAST_CALIB7_UPPER_COUNT_MASK 0xffff
-#define GC_XO_CLK_JTR_FAST_CALIB7_UPPER_COUNT_SIZE 0x10
-#define GC_XO_CLK_JTR_FAST_CALIB7_UPPER_COUNT_DEFAULT 0x0
-#define GC_XO_CLK_JTR_FAST_CALIB7_UPPER_COUNT_OFFSET 0xa0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OP_LSB    0x0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OP_MASK   0xf
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OP_SIZE   0x4
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OP_DEFAULT 0x0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OP_OFFSET 0xa4
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OPERAND_LSB 0x4
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OPERAND_MASK 0xf0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OPERAND_SIZE 0x4
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OPERAND_DEFAULT 0x0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OPERAND_OFFSET 0xa4
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OP_LSB    0x0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OP_MASK   0xf
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OP_SIZE   0x4
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OP_DEFAULT 0x0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OP_OFFSET 0xa8
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OPERAND_LSB 0x4
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OPERAND_MASK 0xf0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OPERAND_SIZE 0x4
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OPERAND_DEFAULT 0x0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OPERAND_OFFSET 0xa8
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OP_LSB    0x0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OP_MASK   0xf
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OP_SIZE   0x4
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OP_DEFAULT 0x0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OP_OFFSET 0xac
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OPERAND_LSB 0x4
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OPERAND_MASK 0xf0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OPERAND_SIZE 0x4
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OPERAND_DEFAULT 0x0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OPERAND_OFFSET 0xac
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OP_LSB    0x0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OP_MASK   0xf
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OP_SIZE   0x4
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OP_DEFAULT 0x0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OP_OFFSET 0xb0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OPERAND_LSB 0x4
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OPERAND_MASK 0xf0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OPERAND_SIZE 0x4
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OPERAND_DEFAULT 0x0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OPERAND_OFFSET 0xb0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OP_LSB    0x0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OP_MASK   0xf
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OP_SIZE   0x4
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OP_DEFAULT 0x0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OP_OFFSET 0xb4
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OPERAND_LSB 0x4
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OPERAND_MASK 0xf0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OPERAND_SIZE 0x4
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OPERAND_DEFAULT 0x0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OPERAND_OFFSET 0xb4
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OP_LSB    0x0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OP_MASK   0xf
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OP_SIZE   0x4
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OP_DEFAULT 0x0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OP_OFFSET 0xb8
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OPERAND_LSB 0x4
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OPERAND_MASK 0xf0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OPERAND_SIZE 0x4
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OPERAND_DEFAULT 0x0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OPERAND_OFFSET 0xb8
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OP_LSB    0x0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OP_MASK   0xf
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OP_SIZE   0x4
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OP_DEFAULT 0x0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OP_OFFSET 0xbc
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OPERAND_LSB 0x4
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OPERAND_MASK 0xf0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OPERAND_SIZE 0x4
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OPERAND_DEFAULT 0x0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OPERAND_OFFSET 0xbc
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OP_LSB    0x0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OP_MASK   0xf
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OP_SIZE   0x4
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OP_DEFAULT 0x0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OP_OFFSET 0xc0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OPERAND_LSB 0x4
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OPERAND_MASK 0xf0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OPERAND_SIZE 0x4
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OPERAND_DEFAULT 0x0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OPERAND_OFFSET 0xc0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OP_LSB    0x0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OP_MASK   0xf
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OP_SIZE   0x4
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OP_DEFAULT 0x0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OP_OFFSET 0xc4
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OPERAND_LSB 0x4
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OPERAND_MASK 0xf0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OPERAND_SIZE 0x4
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OPERAND_DEFAULT 0x0
-#define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OPERAND_OFFSET 0xc4
-#define GC_XO_CLK_JTR_SLOW_CALIB0_UPPER_COUNT_LSB 0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB0_UPPER_COUNT_MASK 0xffff
-#define GC_XO_CLK_JTR_SLOW_CALIB0_UPPER_COUNT_SIZE 0x10
-#define GC_XO_CLK_JTR_SLOW_CALIB0_UPPER_COUNT_DEFAULT 0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB0_UPPER_COUNT_OFFSET 0xc8
-#define GC_XO_CLK_JTR_SLOW_CALIB1_UPPER_COUNT_LSB 0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB1_UPPER_COUNT_MASK 0xffff
-#define GC_XO_CLK_JTR_SLOW_CALIB1_UPPER_COUNT_SIZE 0x10
-#define GC_XO_CLK_JTR_SLOW_CALIB1_UPPER_COUNT_DEFAULT 0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB1_UPPER_COUNT_OFFSET 0xcc
-#define GC_XO_CLK_JTR_SLOW_CALIB2_UPPER_COUNT_LSB 0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB2_UPPER_COUNT_MASK 0xffff
-#define GC_XO_CLK_JTR_SLOW_CALIB2_UPPER_COUNT_SIZE 0x10
-#define GC_XO_CLK_JTR_SLOW_CALIB2_UPPER_COUNT_DEFAULT 0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB2_UPPER_COUNT_OFFSET 0xd0
-#define GC_XO_CLK_JTR_SLOW_CALIB3_UPPER_COUNT_LSB 0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB3_UPPER_COUNT_MASK 0xffff
-#define GC_XO_CLK_JTR_SLOW_CALIB3_UPPER_COUNT_SIZE 0x10
-#define GC_XO_CLK_JTR_SLOW_CALIB3_UPPER_COUNT_DEFAULT 0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB3_UPPER_COUNT_OFFSET 0xd4
-#define GC_XO_CLK_JTR_SLOW_CALIB4_UPPER_COUNT_LSB 0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB4_UPPER_COUNT_MASK 0xffff
-#define GC_XO_CLK_JTR_SLOW_CALIB4_UPPER_COUNT_SIZE 0x10
-#define GC_XO_CLK_JTR_SLOW_CALIB4_UPPER_COUNT_DEFAULT 0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB4_UPPER_COUNT_OFFSET 0xd8
-#define GC_XO_CLK_JTR_SLOW_CALIB5_UPPER_COUNT_LSB 0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB5_UPPER_COUNT_MASK 0xffff
-#define GC_XO_CLK_JTR_SLOW_CALIB5_UPPER_COUNT_SIZE 0x10
-#define GC_XO_CLK_JTR_SLOW_CALIB5_UPPER_COUNT_DEFAULT 0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB5_UPPER_COUNT_OFFSET 0xdc
-#define GC_XO_CLK_JTR_SLOW_CALIB6_UPPER_COUNT_LSB 0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB6_UPPER_COUNT_MASK 0xffff
-#define GC_XO_CLK_JTR_SLOW_CALIB6_UPPER_COUNT_SIZE 0x10
-#define GC_XO_CLK_JTR_SLOW_CALIB6_UPPER_COUNT_DEFAULT 0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB6_UPPER_COUNT_OFFSET 0xe0
-#define GC_XO_CLK_JTR_SLOW_CALIB7_UPPER_COUNT_LSB 0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB7_UPPER_COUNT_MASK 0xffff
-#define GC_XO_CLK_JTR_SLOW_CALIB7_UPPER_COUNT_SIZE 0x10
-#define GC_XO_CLK_JTR_SLOW_CALIB7_UPPER_COUNT_DEFAULT 0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB7_UPPER_COUNT_OFFSET 0xe4
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OP_LSB    0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OP_MASK   0xf
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OP_SIZE   0x4
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OP_DEFAULT 0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OP_OFFSET 0xe8
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OPERAND_LSB 0x4
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OPERAND_MASK 0xf0
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OPERAND_SIZE 0x4
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OPERAND_DEFAULT 0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OPERAND_OFFSET 0xe8
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OP_LSB    0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OP_MASK   0xf
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OP_SIZE   0x4
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OP_DEFAULT 0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OP_OFFSET 0xec
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OPERAND_LSB 0x4
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OPERAND_MASK 0xf0
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OPERAND_SIZE 0x4
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OPERAND_DEFAULT 0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OPERAND_OFFSET 0xec
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OP_LSB    0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OP_MASK   0xf
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OP_SIZE   0x4
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OP_DEFAULT 0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OP_OFFSET 0xf0
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OPERAND_LSB 0x4
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OPERAND_MASK 0xf0
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OPERAND_SIZE 0x4
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OPERAND_DEFAULT 0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OPERAND_OFFSET 0xf0
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OP_LSB    0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OP_MASK   0xf
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OP_SIZE   0x4
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OP_DEFAULT 0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OP_OFFSET 0xf4
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OPERAND_LSB 0x4
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OPERAND_MASK 0xf0
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OPERAND_SIZE 0x4
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OPERAND_DEFAULT 0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OPERAND_OFFSET 0xf4
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OP_LSB    0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OP_MASK   0xf
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OP_SIZE   0x4
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OP_DEFAULT 0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OP_OFFSET 0xf8
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OPERAND_LSB 0x4
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OPERAND_MASK 0xf0
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OPERAND_SIZE 0x4
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OPERAND_DEFAULT 0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OPERAND_OFFSET 0xf8
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OP_LSB    0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OP_MASK   0xf
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OP_SIZE   0x4
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OP_DEFAULT 0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OP_OFFSET 0xfc
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OPERAND_LSB 0x4
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OPERAND_MASK 0xf0
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OPERAND_SIZE 0x4
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OPERAND_DEFAULT 0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OPERAND_OFFSET 0xfc
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OP_LSB    0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OP_MASK   0xf
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OP_SIZE   0x4
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OP_DEFAULT 0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OP_OFFSET 0x100
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OPERAND_LSB 0x4
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OPERAND_MASK 0xf0
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OPERAND_SIZE 0x4
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OPERAND_DEFAULT 0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OPERAND_OFFSET 0x100
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OP_LSB    0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OP_MASK   0xf
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OP_SIZE   0x4
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OP_DEFAULT 0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OP_OFFSET 0x104
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OPERAND_LSB 0x4
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OPERAND_MASK 0xf0
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OPERAND_SIZE 0x4
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OPERAND_DEFAULT 0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OPERAND_OFFSET 0x104
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OP_LSB    0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OP_MASK   0xf
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OP_SIZE   0x4
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OP_DEFAULT 0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OP_OFFSET 0x108
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OPERAND_LSB 0x4
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OPERAND_MASK 0xf0
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OPERAND_SIZE 0x4
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OPERAND_DEFAULT 0x0
-#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OPERAND_OFFSET 0x108
-#define GC_XO_CLK_JTR_SW_TRIM_COUNTER_VALUE_LSB  0x0
-#define GC_XO_CLK_JTR_SW_TRIM_COUNTER_VALUE_MASK 0xffffff
-#define GC_XO_CLK_JTR_SW_TRIM_COUNTER_VALUE_SIZE 0x18
-#define GC_XO_CLK_JTR_SW_TRIM_COUNTER_VALUE_DEFAULT 0x0
-#define GC_XO_CLK_JTR_SW_TRIM_COUNTER_VALUE_OFFSET 0x110
-#define GC_XO_CLK_JTR_SW_TRIM_COUNTER_DONE_LSB   0x18
-#define GC_XO_CLK_JTR_SW_TRIM_COUNTER_DONE_MASK  0x1000000
-#define GC_XO_CLK_JTR_SW_TRIM_COUNTER_DONE_SIZE  0x1
-#define GC_XO_CLK_JTR_SW_TRIM_COUNTER_DONE_DEFAULT 0x0
-#define GC_XO_CLK_JTR_SW_TRIM_COUNTER_DONE_OFFSET 0x110
-#define GC_XO_CLK_TIMER_CTRL_HS_SEL_LSB          0x0
-#define GC_XO_CLK_TIMER_CTRL_HS_SEL_MASK         0x1
-#define GC_XO_CLK_TIMER_CTRL_HS_SEL_SIZE         0x1
-#define GC_XO_CLK_TIMER_CTRL_HS_SEL_DEFAULT      0x1
-#define GC_XO_CLK_TIMER_CTRL_HS_SEL_OFFSET       0x114
-#define GC_XO_CLK_TIMER_CTRL_SEL_LSB             0x1
-#define GC_XO_CLK_TIMER_CTRL_SEL_MASK            0x2
-#define GC_XO_CLK_TIMER_CTRL_SEL_SIZE            0x1
-#define GC_XO_CLK_TIMER_CTRL_SEL_DEFAULT         0x1
-#define GC_XO_CLK_TIMER_CTRL_SEL_OFFSET          0x114
-#define GC_XO_CLK_TIMER_CURRENT_COARSE_TRIM_LSB  0x0
-#define GC_XO_CLK_TIMER_CURRENT_COARSE_TRIM_MASK 0xff
-#define GC_XO_CLK_TIMER_CURRENT_COARSE_TRIM_SIZE 0x8
-#define GC_XO_CLK_TIMER_CURRENT_COARSE_TRIM_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_CURRENT_COARSE_TRIM_OFFSET 0x120
-#define GC_XO_CLK_TIMER_CURRENT_FINE_TRIM_LSB    0x8
-#define GC_XO_CLK_TIMER_CURRENT_FINE_TRIM_MASK   0xff00
-#define GC_XO_CLK_TIMER_CURRENT_FINE_TRIM_SIZE   0x8
-#define GC_XO_CLK_TIMER_CURRENT_FINE_TRIM_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_CURRENT_FINE_TRIM_OFFSET 0x120
-#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_TRIM_EN_LSB 0x0
-#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_TRIM_EN_MASK 0x1
-#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_TRIM_EN_SIZE 0x1
-#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_TRIM_EN_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_TRIM_EN_OFFSET 0x128
-#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_INITIAL_TRIM_PERIOD_LSB 0x1
-#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_INITIAL_TRIM_PERIOD_MASK 0x1fe
-#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_INITIAL_TRIM_PERIOD_SIZE 0x8
-#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_INITIAL_TRIM_PERIOD_DEFAULT 0xf
-#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_INITIAL_TRIM_PERIOD_OFFSET 0x128
-#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_FINE_TRIM_SRC_LSB 0x9
-#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_FINE_TRIM_SRC_MASK 0x200
-#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_FINE_TRIM_SRC_SIZE 0x1
-#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_FINE_TRIM_SRC_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_FINE_TRIM_SRC_OFFSET 0x128
-#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_COARSE_TRIM_SRC_LSB 0xa
-#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_COARSE_TRIM_SRC_MASK 0xc00
-#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_COARSE_TRIM_SRC_SIZE 0x2
-#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_COARSE_TRIM_SRC_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_COARSE_TRIM_SRC_OFFSET 0x128
-#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_ENABLE_FAST_LSB 0x0
-#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_ENABLE_FAST_MASK 0x1
-#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_ENABLE_FAST_SIZE 0x1
-#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_ENABLE_FAST_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_ENABLE_FAST_OFFSET 0x12c
-#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_ENABLE_SLOW_LSB 0x1
-#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_ENABLE_SLOW_MASK 0x2
-#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_ENABLE_SLOW_SIZE 0x1
-#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_ENABLE_SLOW_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_ENABLE_SLOW_OFFSET 0x12c
-#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_SLOW_MODE_SEL_LSB 0x2
-#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_SLOW_MODE_SEL_MASK 0x4
-#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_SLOW_MODE_SEL_SIZE 0x1
-#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_SLOW_MODE_SEL_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_SLOW_MODE_SEL_OFFSET 0x12c
-#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_MAX_TRIM_SEL_LSB 0x3
-#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_MAX_TRIM_SEL_MASK 0x8
-#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_MAX_TRIM_SEL_SIZE 0x1
-#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_MAX_TRIM_SEL_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_MAX_TRIM_SEL_OFFSET 0x12c
-#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_STOP_ON_NOP_LSB 0x4
-#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_STOP_ON_NOP_MASK 0x10
-#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_STOP_ON_NOP_SIZE 0x1
-#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_STOP_ON_NOP_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_STOP_ON_NOP_OFFSET 0x12c
-#define GC_XO_CLK_TIMER_FAST_CALIB0_UPPER_COUNT_LSB 0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB0_UPPER_COUNT_MASK 0xffff
-#define GC_XO_CLK_TIMER_FAST_CALIB0_UPPER_COUNT_SIZE 0x10
-#define GC_XO_CLK_TIMER_FAST_CALIB0_UPPER_COUNT_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB0_UPPER_COUNT_OFFSET 0x13c
-#define GC_XO_CLK_TIMER_FAST_CALIB1_UPPER_COUNT_LSB 0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB1_UPPER_COUNT_MASK 0xffff
-#define GC_XO_CLK_TIMER_FAST_CALIB1_UPPER_COUNT_SIZE 0x10
-#define GC_XO_CLK_TIMER_FAST_CALIB1_UPPER_COUNT_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB1_UPPER_COUNT_OFFSET 0x140
-#define GC_XO_CLK_TIMER_FAST_CALIB2_UPPER_COUNT_LSB 0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB2_UPPER_COUNT_MASK 0xffff
-#define GC_XO_CLK_TIMER_FAST_CALIB2_UPPER_COUNT_SIZE 0x10
-#define GC_XO_CLK_TIMER_FAST_CALIB2_UPPER_COUNT_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB2_UPPER_COUNT_OFFSET 0x144
-#define GC_XO_CLK_TIMER_FAST_CALIB3_UPPER_COUNT_LSB 0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB3_UPPER_COUNT_MASK 0xffff
-#define GC_XO_CLK_TIMER_FAST_CALIB3_UPPER_COUNT_SIZE 0x10
-#define GC_XO_CLK_TIMER_FAST_CALIB3_UPPER_COUNT_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB3_UPPER_COUNT_OFFSET 0x148
-#define GC_XO_CLK_TIMER_FAST_CALIB4_UPPER_COUNT_LSB 0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB4_UPPER_COUNT_MASK 0xffff
-#define GC_XO_CLK_TIMER_FAST_CALIB4_UPPER_COUNT_SIZE 0x10
-#define GC_XO_CLK_TIMER_FAST_CALIB4_UPPER_COUNT_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB4_UPPER_COUNT_OFFSET 0x14c
-#define GC_XO_CLK_TIMER_FAST_CALIB5_UPPER_COUNT_LSB 0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB5_UPPER_COUNT_MASK 0xffff
-#define GC_XO_CLK_TIMER_FAST_CALIB5_UPPER_COUNT_SIZE 0x10
-#define GC_XO_CLK_TIMER_FAST_CALIB5_UPPER_COUNT_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB5_UPPER_COUNT_OFFSET 0x150
-#define GC_XO_CLK_TIMER_FAST_CALIB6_UPPER_COUNT_LSB 0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB6_UPPER_COUNT_MASK 0xffff
-#define GC_XO_CLK_TIMER_FAST_CALIB6_UPPER_COUNT_SIZE 0x10
-#define GC_XO_CLK_TIMER_FAST_CALIB6_UPPER_COUNT_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB6_UPPER_COUNT_OFFSET 0x154
-#define GC_XO_CLK_TIMER_FAST_CALIB7_UPPER_COUNT_LSB 0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB7_UPPER_COUNT_MASK 0xffff
-#define GC_XO_CLK_TIMER_FAST_CALIB7_UPPER_COUNT_SIZE 0x10
-#define GC_XO_CLK_TIMER_FAST_CALIB7_UPPER_COUNT_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB7_UPPER_COUNT_OFFSET 0x158
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OP_LSB  0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OP_MASK 0xf
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OP_SIZE 0x4
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OP_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OP_OFFSET 0x15c
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OPERAND_LSB 0x4
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OPERAND_MASK 0xf0
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OPERAND_SIZE 0x4
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OPERAND_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OPERAND_OFFSET 0x15c
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OP_LSB  0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OP_MASK 0xf
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OP_SIZE 0x4
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OP_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OP_OFFSET 0x160
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OPERAND_LSB 0x4
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OPERAND_MASK 0xf0
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OPERAND_SIZE 0x4
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OPERAND_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OPERAND_OFFSET 0x160
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OP_LSB  0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OP_MASK 0xf
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OP_SIZE 0x4
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OP_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OP_OFFSET 0x164
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OPERAND_LSB 0x4
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OPERAND_MASK 0xf0
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OPERAND_SIZE 0x4
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OPERAND_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OPERAND_OFFSET 0x164
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OP_LSB  0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OP_MASK 0xf
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OP_SIZE 0x4
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OP_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OP_OFFSET 0x168
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OPERAND_LSB 0x4
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OPERAND_MASK 0xf0
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OPERAND_SIZE 0x4
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OPERAND_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OPERAND_OFFSET 0x168
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OP_LSB  0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OP_MASK 0xf
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OP_SIZE 0x4
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OP_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OP_OFFSET 0x16c
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OPERAND_LSB 0x4
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OPERAND_MASK 0xf0
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OPERAND_SIZE 0x4
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OPERAND_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OPERAND_OFFSET 0x16c
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OP_LSB  0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OP_MASK 0xf
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OP_SIZE 0x4
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OP_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OP_OFFSET 0x170
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OPERAND_LSB 0x4
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OPERAND_MASK 0xf0
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OPERAND_SIZE 0x4
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OPERAND_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OPERAND_OFFSET 0x170
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OP_LSB  0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OP_MASK 0xf
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OP_SIZE 0x4
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OP_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OP_OFFSET 0x174
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OPERAND_LSB 0x4
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OPERAND_MASK 0xf0
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OPERAND_SIZE 0x4
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OPERAND_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OPERAND_OFFSET 0x174
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OP_LSB  0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OP_MASK 0xf
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OP_SIZE 0x4
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OP_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OP_OFFSET 0x178
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OPERAND_LSB 0x4
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OPERAND_MASK 0xf0
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OPERAND_SIZE 0x4
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OPERAND_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OPERAND_OFFSET 0x178
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OP_LSB  0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OP_MASK 0xf
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OP_SIZE 0x4
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OP_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OP_OFFSET 0x17c
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OPERAND_LSB 0x4
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OPERAND_MASK 0xf0
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OPERAND_SIZE 0x4
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OPERAND_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OPERAND_OFFSET 0x17c
-#define GC_XO_CLK_TIMER_SLOW_CALIB0_UPPER_COUNT_LSB 0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB0_UPPER_COUNT_MASK 0xffff
-#define GC_XO_CLK_TIMER_SLOW_CALIB0_UPPER_COUNT_SIZE 0x10
-#define GC_XO_CLK_TIMER_SLOW_CALIB0_UPPER_COUNT_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB0_UPPER_COUNT_OFFSET 0x180
-#define GC_XO_CLK_TIMER_SLOW_CALIB1_UPPER_COUNT_LSB 0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB1_UPPER_COUNT_MASK 0xffff
-#define GC_XO_CLK_TIMER_SLOW_CALIB1_UPPER_COUNT_SIZE 0x10
-#define GC_XO_CLK_TIMER_SLOW_CALIB1_UPPER_COUNT_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB1_UPPER_COUNT_OFFSET 0x184
-#define GC_XO_CLK_TIMER_SLOW_CALIB2_UPPER_COUNT_LSB 0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB2_UPPER_COUNT_MASK 0xffff
-#define GC_XO_CLK_TIMER_SLOW_CALIB2_UPPER_COUNT_SIZE 0x10
-#define GC_XO_CLK_TIMER_SLOW_CALIB2_UPPER_COUNT_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB2_UPPER_COUNT_OFFSET 0x188
-#define GC_XO_CLK_TIMER_SLOW_CALIB3_UPPER_COUNT_LSB 0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB3_UPPER_COUNT_MASK 0xffff
-#define GC_XO_CLK_TIMER_SLOW_CALIB3_UPPER_COUNT_SIZE 0x10
-#define GC_XO_CLK_TIMER_SLOW_CALIB3_UPPER_COUNT_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB3_UPPER_COUNT_OFFSET 0x18c
-#define GC_XO_CLK_TIMER_SLOW_CALIB4_UPPER_COUNT_LSB 0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB4_UPPER_COUNT_MASK 0xffff
-#define GC_XO_CLK_TIMER_SLOW_CALIB4_UPPER_COUNT_SIZE 0x10
-#define GC_XO_CLK_TIMER_SLOW_CALIB4_UPPER_COUNT_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB4_UPPER_COUNT_OFFSET 0x190
-#define GC_XO_CLK_TIMER_SLOW_CALIB5_UPPER_COUNT_LSB 0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB5_UPPER_COUNT_MASK 0xffff
-#define GC_XO_CLK_TIMER_SLOW_CALIB5_UPPER_COUNT_SIZE 0x10
-#define GC_XO_CLK_TIMER_SLOW_CALIB5_UPPER_COUNT_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB5_UPPER_COUNT_OFFSET 0x194
-#define GC_XO_CLK_TIMER_SLOW_CALIB6_UPPER_COUNT_LSB 0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB6_UPPER_COUNT_MASK 0xffff
-#define GC_XO_CLK_TIMER_SLOW_CALIB6_UPPER_COUNT_SIZE 0x10
-#define GC_XO_CLK_TIMER_SLOW_CALIB6_UPPER_COUNT_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB6_UPPER_COUNT_OFFSET 0x198
-#define GC_XO_CLK_TIMER_SLOW_CALIB7_UPPER_COUNT_LSB 0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB7_UPPER_COUNT_MASK 0xffff
-#define GC_XO_CLK_TIMER_SLOW_CALIB7_UPPER_COUNT_SIZE 0x10
-#define GC_XO_CLK_TIMER_SLOW_CALIB7_UPPER_COUNT_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB7_UPPER_COUNT_OFFSET 0x19c
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OP_LSB  0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OP_MASK 0xf
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OP_SIZE 0x4
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OP_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OP_OFFSET 0x1a0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OPERAND_LSB 0x4
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OPERAND_MASK 0xf0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OPERAND_SIZE 0x4
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OPERAND_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OPERAND_OFFSET 0x1a0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OP_LSB  0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OP_MASK 0xf
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OP_SIZE 0x4
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OP_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OP_OFFSET 0x1a4
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OPERAND_LSB 0x4
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OPERAND_MASK 0xf0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OPERAND_SIZE 0x4
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OPERAND_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OPERAND_OFFSET 0x1a4
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OP_LSB  0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OP_MASK 0xf
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OP_SIZE 0x4
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OP_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OP_OFFSET 0x1a8
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OPERAND_LSB 0x4
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OPERAND_MASK 0xf0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OPERAND_SIZE 0x4
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OPERAND_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OPERAND_OFFSET 0x1a8
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OP_LSB  0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OP_MASK 0xf
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OP_SIZE 0x4
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OP_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OP_OFFSET 0x1ac
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OPERAND_LSB 0x4
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OPERAND_MASK 0xf0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OPERAND_SIZE 0x4
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OPERAND_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OPERAND_OFFSET 0x1ac
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OP_LSB  0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OP_MASK 0xf
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OP_SIZE 0x4
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OP_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OP_OFFSET 0x1b0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OPERAND_LSB 0x4
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OPERAND_MASK 0xf0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OPERAND_SIZE 0x4
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OPERAND_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OPERAND_OFFSET 0x1b0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OP_LSB  0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OP_MASK 0xf
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OP_SIZE 0x4
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OP_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OP_OFFSET 0x1b4
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OPERAND_LSB 0x4
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OPERAND_MASK 0xf0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OPERAND_SIZE 0x4
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OPERAND_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OPERAND_OFFSET 0x1b4
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OP_LSB  0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OP_MASK 0xf
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OP_SIZE 0x4
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OP_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OP_OFFSET 0x1b8
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OPERAND_LSB 0x4
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OPERAND_MASK 0xf0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OPERAND_SIZE 0x4
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OPERAND_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OPERAND_OFFSET 0x1b8
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OP_LSB  0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OP_MASK 0xf
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OP_SIZE 0x4
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OP_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OP_OFFSET 0x1bc
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OPERAND_LSB 0x4
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OPERAND_MASK 0xf0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OPERAND_SIZE 0x4
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OPERAND_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OPERAND_OFFSET 0x1bc
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OP_LSB  0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OP_MASK 0xf
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OP_SIZE 0x4
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OP_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OP_OFFSET 0x1c0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OPERAND_LSB 0x4
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OPERAND_MASK 0xf0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OPERAND_SIZE 0x4
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OPERAND_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OPERAND_OFFSET 0x1c0
-#define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_VALUE_LSB 0x0
-#define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_VALUE_MASK 0xffffff
-#define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_VALUE_SIZE 0x18
-#define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_VALUE_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_VALUE_OFFSET 0x1c8
-#define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_DONE_LSB 0x18
-#define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_DONE_MASK 0x1000000
-#define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_DONE_SIZE 0x1
-#define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_DONE_DEFAULT 0x0
-#define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_DONE_OFFSET 0x1c8
-#define GC_XO_OSC_XTL_FREQ2X_CAL_CNTL_LSB        0x0
-#define GC_XO_OSC_XTL_FREQ2X_CAL_CNTL_MASK       0xf
-#define GC_XO_OSC_XTL_FREQ2X_CAL_CNTL_SIZE       0x4
-#define GC_XO_OSC_XTL_FREQ2X_CAL_CNTL_DEFAULT    0x7
-#define GC_XO_OSC_XTL_FREQ2X_CAL_CNTL_OFFSET     0x1cc
-#define GC_XO_OSC_XTL_FREQ2X_CAL_EN_LSB          0x4
-#define GC_XO_OSC_XTL_FREQ2X_CAL_EN_MASK         0x10
-#define GC_XO_OSC_XTL_FREQ2X_CAL_EN_SIZE         0x1
-#define GC_XO_OSC_XTL_FREQ2X_CAL_EN_DEFAULT      0x0
-#define GC_XO_OSC_XTL_FREQ2X_CAL_EN_OFFSET       0x1cc
-#define GC_XO_OSC_XTL_FREQ2X_SELB_LSB            0x5
-#define GC_XO_OSC_XTL_FREQ2X_SELB_MASK           0x20
-#define GC_XO_OSC_XTL_FREQ2X_SELB_SIZE           0x1
-#define GC_XO_OSC_XTL_FREQ2X_SELB_DEFAULT        0x0
-#define GC_XO_OSC_XTL_FREQ2X_SELB_OFFSET         0x1cc
-#define GC_XO_OSC_XTL_FREQ2X_STAT_CAL_CNTL_LSB   0x0
-#define GC_XO_OSC_XTL_FREQ2X_STAT_CAL_CNTL_MASK  0xf
-#define GC_XO_OSC_XTL_FREQ2X_STAT_CAL_CNTL_SIZE  0x4
-#define GC_XO_OSC_XTL_FREQ2X_STAT_CAL_CNTL_DEFAULT 0x6
-#define GC_XO_OSC_XTL_FREQ2X_STAT_CAL_CNTL_OFFSET 0x1d0
-#define GC_XO_OSC_XTL_FREQ2X_STAT_CAL_EN_LSB     0x4
-#define GC_XO_OSC_XTL_FREQ2X_STAT_CAL_EN_MASK    0x10
-#define GC_XO_OSC_XTL_FREQ2X_STAT_CAL_EN_SIZE    0x1
-#define GC_XO_OSC_XTL_FREQ2X_STAT_CAL_EN_DEFAULT 0x0
-#define GC_XO_OSC_XTL_FREQ2X_STAT_CAL_EN_OFFSET  0x1d0
-#define GC_XO_OSC_XTL_FREQ2X_STAT_SELB_LSB       0x5
-#define GC_XO_OSC_XTL_FREQ2X_STAT_SELB_MASK      0x20
-#define GC_XO_OSC_XTL_FREQ2X_STAT_SELB_SIZE      0x1
-#define GC_XO_OSC_XTL_FREQ2X_STAT_SELB_DEFAULT   0x0
-#define GC_XO_OSC_XTL_FREQ2X_STAT_SELB_OFFSET    0x1d0
-#define GC_XO_OSC_XTL_RC_FLTR_TRIM_LSB           0x0
-#define GC_XO_OSC_XTL_RC_FLTR_TRIM_MASK          0xf
-#define GC_XO_OSC_XTL_RC_FLTR_TRIM_SIZE          0x4
-#define GC_XO_OSC_XTL_RC_FLTR_TRIM_DEFAULT       0x5
-#define GC_XO_OSC_XTL_RC_FLTR_TRIM_OFFSET        0x1e0
-#define GC_XO_OSC_XTL_RC_FLTR_BYPASS_LSB         0x4
-#define GC_XO_OSC_XTL_RC_FLTR_BYPASS_MASK        0x10
-#define GC_XO_OSC_XTL_RC_FLTR_BYPASS_SIZE        0x1
-#define GC_XO_OSC_XTL_RC_FLTR_BYPASS_DEFAULT     0x1
-#define GC_XO_OSC_XTL_RC_FLTR_BYPASS_OFFSET      0x1e0
-#define GC_XO_OSC_XTL_OVRD_TRIM_LSB              0x0
-#define GC_XO_OSC_XTL_OVRD_TRIM_MASK             0xf
-#define GC_XO_OSC_XTL_OVRD_TRIM_SIZE             0x4
-#define GC_XO_OSC_XTL_OVRD_TRIM_DEFAULT          0x7
-#define GC_XO_OSC_XTL_OVRD_TRIM_OFFSET           0x1e4
-#define GC_XO_OSC_XTL_OVRD_ENB_LSB               0x4
-#define GC_XO_OSC_XTL_OVRD_ENB_MASK              0x10
-#define GC_XO_OSC_XTL_OVRD_ENB_SIZE              0x1
-#define GC_XO_OSC_XTL_OVRD_ENB_DEFAULT           0x1
-#define GC_XO_OSC_XTL_OVRD_ENB_OFFSET            0x1e4
-#define GC_XO_OSC_XTL_TRIM_CODE_LSB              0x0
-#define GC_XO_OSC_XTL_TRIM_CODE_MASK             0xf
-#define GC_XO_OSC_XTL_TRIM_CODE_SIZE             0x4
-#define GC_XO_OSC_XTL_TRIM_CODE_DEFAULT          0x0
-#define GC_XO_OSC_XTL_TRIM_CODE_OFFSET           0x1ec
-#define GC_XO_OSC_XTL_TRIM_EN_LSB                0x4
-#define GC_XO_OSC_XTL_TRIM_EN_MASK               0x10
-#define GC_XO_OSC_XTL_TRIM_EN_SIZE               0x1
-#define GC_XO_OSC_XTL_TRIM_EN_DEFAULT            0x0
-#define GC_XO_OSC_XTL_TRIM_EN_OFFSET             0x1ec
-#define GC_XO_OSC_XTL_TRIM_STAT_CODE_LSB         0x0
-#define GC_XO_OSC_XTL_TRIM_STAT_CODE_MASK        0xf
-#define GC_XO_OSC_XTL_TRIM_STAT_CODE_SIZE        0x4
-#define GC_XO_OSC_XTL_TRIM_STAT_CODE_DEFAULT     0x0
-#define GC_XO_OSC_XTL_TRIM_STAT_CODE_OFFSET      0x1f0
-#define GC_XO_OSC_XTL_TRIM_STAT_EN_LSB           0x4
-#define GC_XO_OSC_XTL_TRIM_STAT_EN_MASK          0x10
-#define GC_XO_OSC_XTL_TRIM_STAT_EN_SIZE          0x1
-#define GC_XO_OSC_XTL_TRIM_STAT_EN_DEFAULT       0x0
-#define GC_XO_OSC_XTL_TRIM_STAT_EN_OFFSET        0x1f0
-#define GC_XO_OSC_XTL_FSM_DONE_LSB               0x0
-#define GC_XO_OSC_XTL_FSM_DONE_MASK              0x1
-#define GC_XO_OSC_XTL_FSM_DONE_SIZE              0x1
-#define GC_XO_OSC_XTL_FSM_DONE_DEFAULT           0x0
-#define GC_XO_OSC_XTL_FSM_DONE_OFFSET            0x1fc
-#define GC_XO_OSC_XTL_FSM_TRIM_LSB               0x1
-#define GC_XO_OSC_XTL_FSM_TRIM_MASK              0x1e
-#define GC_XO_OSC_XTL_FSM_TRIM_SIZE              0x4
-#define GC_XO_OSC_XTL_FSM_TRIM_DEFAULT           0x0
-#define GC_XO_OSC_XTL_FSM_TRIM_OFFSET            0x1fc
-#define GC_XO_OSC_XTL_FSM_STATUS_LSB             0x5
-#define GC_XO_OSC_XTL_FSM_STATUS_MASK            0x20
-#define GC_XO_OSC_XTL_FSM_STATUS_SIZE            0x1
-#define GC_XO_OSC_XTL_FSM_STATUS_DEFAULT         0x0
-#define GC_XO_OSC_XTL_FSM_STATUS_OFFSET          0x1fc
-#define GC_XO_OSC_XTL_FSM_STATE_LSB              0x6
-#define GC_XO_OSC_XTL_FSM_STATE_MASK             0x3c0
-#define GC_XO_OSC_XTL_FSM_STATE_SIZE             0x4
-#define GC_XO_OSC_XTL_FSM_STATE_DEFAULT          0x0
-#define GC_XO_OSC_XTL_FSM_STATE_OFFSET           0x1fc
-#define GC_XO_OSC_XTL_FSM_LVL_DET_SYNC_LSB       0xa
-#define GC_XO_OSC_XTL_FSM_LVL_DET_SYNC_MASK      0x400
-#define GC_XO_OSC_XTL_FSM_LVL_DET_SYNC_SIZE      0x1
-#define GC_XO_OSC_XTL_FSM_LVL_DET_SYNC_DEFAULT   0x0
-#define GC_XO_OSC_XTL_FSM_LVL_DET_SYNC_OFFSET    0x1fc
-#define GC_XO_OSC_XTL_FSM_CFG_TRIM_MAX_LSB       0x0
-#define GC_XO_OSC_XTL_FSM_CFG_TRIM_MAX_MASK      0xf
-#define GC_XO_OSC_XTL_FSM_CFG_TRIM_MAX_SIZE      0x4
-#define GC_XO_OSC_XTL_FSM_CFG_TRIM_MAX_DEFAULT   0x8
-#define GC_XO_OSC_XTL_FSM_CFG_TRIM_MAX_OFFSET    0x200
-#define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SNIFF_LSB  0x4
-#define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SNIFF_MASK 0x30
-#define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SNIFF_SIZE 0x2
-#define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SNIFF_DEFAULT 0x0
-#define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SNIFF_OFFSET 0x200
-#define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SENSE_LSB  0x6
-#define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SENSE_MASK 0xc0
-#define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SENSE_SIZE 0x2
-#define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SENSE_DEFAULT 0x2
-#define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SENSE_OFFSET 0x200
-#define GC_XO_OSC_XTL_FSM_CFG_PWRUP_REG_MAX_LSB  0x8
-#define GC_XO_OSC_XTL_FSM_CFG_PWRUP_REG_MAX_MASK 0x700
-#define GC_XO_OSC_XTL_FSM_CFG_PWRUP_REG_MAX_SIZE 0x3
-#define GC_XO_OSC_XTL_FSM_CFG_PWRUP_REG_MAX_DEFAULT 0x4
-#define GC_XO_OSC_XTL_FSM_CFG_PWRUP_REG_MAX_OFFSET 0x200
-#define GC_XO_OSC_XTL_FSM_CFG_SNIFF_REG_MAX_LSB  0xb
-#define GC_XO_OSC_XTL_FSM_CFG_SNIFF_REG_MAX_MASK 0xf800
-#define GC_XO_OSC_XTL_FSM_CFG_SNIFF_REG_MAX_SIZE 0x5
-#define GC_XO_OSC_XTL_FSM_CFG_SNIFF_REG_MAX_DEFAULT 0xe
-#define GC_XO_OSC_XTL_FSM_CFG_SNIFF_REG_MAX_OFFSET 0x200
-#define GC_XO_OSC_XTL_FSM_CFG_SENSE_REG_MAX_LSB  0x10
-#define GC_XO_OSC_XTL_FSM_CFG_SENSE_REG_MAX_MASK 0x1f0000
-#define GC_XO_OSC_XTL_FSM_CFG_SENSE_REG_MAX_SIZE 0x5
-#define GC_XO_OSC_XTL_FSM_CFG_SENSE_REG_MAX_DEFAULT 0xd
-#define GC_XO_OSC_XTL_FSM_CFG_SENSE_REG_MAX_OFFSET 0x200
-#define GC_XO_OSC_TEST_CLK2X_EN_LSB              0x0
-#define GC_XO_OSC_TEST_CLK2X_EN_MASK             0x1
-#define GC_XO_OSC_TEST_CLK2X_EN_SIZE             0x1
-#define GC_XO_OSC_TEST_CLK2X_EN_DEFAULT          0x0
-#define GC_XO_OSC_TEST_CLK2X_EN_OFFSET           0x204
-#define GC_XO_OSC_TEST_CLK_JTR_EN_LSB            0x1
-#define GC_XO_OSC_TEST_CLK_JTR_EN_MASK           0x2
-#define GC_XO_OSC_TEST_CLK_JTR_EN_SIZE           0x1
-#define GC_XO_OSC_TEST_CLK_JTR_EN_DEFAULT        0x0
-#define GC_XO_OSC_TEST_CLK_JTR_EN_OFFSET         0x204
-#define GC_XO_OSC_TEST_CLK_TIMER_EN_LSB          0x2
-#define GC_XO_OSC_TEST_CLK_TIMER_EN_MASK         0x4
-#define GC_XO_OSC_TEST_CLK_TIMER_EN_SIZE         0x1
-#define GC_XO_OSC_TEST_CLK_TIMER_EN_DEFAULT      0x0
-#define GC_XO_OSC_TEST_CLK_TIMER_EN_OFFSET       0x204
-#define GC_XO_ANTEST_CTRL_LDO_EN_LSB             0x0
-#define GC_XO_ANTEST_CTRL_LDO_EN_MASK            0x1
-#define GC_XO_ANTEST_CTRL_LDO_EN_SIZE            0x1
-#define GC_XO_ANTEST_CTRL_LDO_EN_DEFAULT         0x0
-#define GC_XO_ANTEST_CTRL_LDO_EN_OFFSET          0x214
-#define GC_XO_DXO_INT_ENABLE_FAST_CALIB_OVERFLOW_LSB 0x0
-#define GC_XO_DXO_INT_ENABLE_FAST_CALIB_OVERFLOW_MASK 0x1
-#define GC_XO_DXO_INT_ENABLE_FAST_CALIB_OVERFLOW_SIZE 0x1
-#define GC_XO_DXO_INT_ENABLE_FAST_CALIB_OVERFLOW_DEFAULT 0x0
-#define GC_XO_DXO_INT_ENABLE_FAST_CALIB_OVERFLOW_OFFSET 0x218
-#define GC_XO_DXO_INT_ENABLE_FAST_CALIB_UNDERRUN_LSB 0x1
-#define GC_XO_DXO_INT_ENABLE_FAST_CALIB_UNDERRUN_MASK 0x2
-#define GC_XO_DXO_INT_ENABLE_FAST_CALIB_UNDERRUN_SIZE 0x1
-#define GC_XO_DXO_INT_ENABLE_FAST_CALIB_UNDERRUN_DEFAULT 0x0
-#define GC_XO_DXO_INT_ENABLE_FAST_CALIB_UNDERRUN_OFFSET 0x218
-#define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_OVERFLOW_LSB 0x2
-#define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_OVERFLOW_MASK 0x4
-#define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_OVERFLOW_SIZE 0x1
-#define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_OVERFLOW_DEFAULT 0x0
-#define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_OVERFLOW_OFFSET 0x218
-#define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_UNDERRUN_LSB 0x3
-#define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_UNDERRUN_MASK 0x8
-#define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_UNDERRUN_SIZE 0x1
-#define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_UNDERRUN_DEFAULT 0x0
-#define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_UNDERRUN_OFFSET 0x218
-#define GC_XO_DXO_INT_ENABLE_CLK_JTR_NOP_SEEN_LSB 0x4
-#define GC_XO_DXO_INT_ENABLE_CLK_JTR_NOP_SEEN_MASK 0x10
-#define GC_XO_DXO_INT_ENABLE_CLK_JTR_NOP_SEEN_SIZE 0x1
-#define GC_XO_DXO_INT_ENABLE_CLK_JTR_NOP_SEEN_DEFAULT 0x0
-#define GC_XO_DXO_INT_ENABLE_CLK_JTR_NOP_SEEN_OFFSET 0x218
-#define GC_XO_DXO_INT_ENABLE_CLK_TIMER_NOP_SEEN_LSB 0x5
-#define GC_XO_DXO_INT_ENABLE_CLK_TIMER_NOP_SEEN_MASK 0x20
-#define GC_XO_DXO_INT_ENABLE_CLK_TIMER_NOP_SEEN_SIZE 0x1
-#define GC_XO_DXO_INT_ENABLE_CLK_TIMER_NOP_SEEN_DEFAULT 0x0
-#define GC_XO_DXO_INT_ENABLE_CLK_TIMER_NOP_SEEN_OFFSET 0x218
-#define GC_XO_DXO_INT_ENABLE_CLK_JTR_SW_TRIM_DONE_LSB 0x6
-#define GC_XO_DXO_INT_ENABLE_CLK_JTR_SW_TRIM_DONE_MASK 0x40
-#define GC_XO_DXO_INT_ENABLE_CLK_JTR_SW_TRIM_DONE_SIZE 0x1
-#define GC_XO_DXO_INT_ENABLE_CLK_JTR_SW_TRIM_DONE_DEFAULT 0x0
-#define GC_XO_DXO_INT_ENABLE_CLK_JTR_SW_TRIM_DONE_OFFSET 0x218
-#define GC_XO_DXO_INT_ENABLE_CLK_TIMER_SW_TRIM_DONE_LSB 0x7
-#define GC_XO_DXO_INT_ENABLE_CLK_TIMER_SW_TRIM_DONE_MASK 0x80
-#define GC_XO_DXO_INT_ENABLE_CLK_TIMER_SW_TRIM_DONE_SIZE 0x1
-#define GC_XO_DXO_INT_ENABLE_CLK_TIMER_SW_TRIM_DONE_DEFAULT 0x0
-#define GC_XO_DXO_INT_ENABLE_CLK_TIMER_SW_TRIM_DONE_OFFSET 0x218
-#define GC_XO_DXO_INT_STATE_FAST_CALIB_OVERFLOW_LSB 0x0
-#define GC_XO_DXO_INT_STATE_FAST_CALIB_OVERFLOW_MASK 0x1
-#define GC_XO_DXO_INT_STATE_FAST_CALIB_OVERFLOW_SIZE 0x1
-#define GC_XO_DXO_INT_STATE_FAST_CALIB_OVERFLOW_DEFAULT 0x0
-#define GC_XO_DXO_INT_STATE_FAST_CALIB_OVERFLOW_OFFSET 0x21c
-#define GC_XO_DXO_INT_STATE_FAST_CALIB_UNDERRUN_LSB 0x1
-#define GC_XO_DXO_INT_STATE_FAST_CALIB_UNDERRUN_MASK 0x2
-#define GC_XO_DXO_INT_STATE_FAST_CALIB_UNDERRUN_SIZE 0x1
-#define GC_XO_DXO_INT_STATE_FAST_CALIB_UNDERRUN_DEFAULT 0x0
-#define GC_XO_DXO_INT_STATE_FAST_CALIB_UNDERRUN_OFFSET 0x21c
-#define GC_XO_DXO_INT_STATE_SLOW_CALIB_OVERFLOW_LSB 0x2
-#define GC_XO_DXO_INT_STATE_SLOW_CALIB_OVERFLOW_MASK 0x4
-#define GC_XO_DXO_INT_STATE_SLOW_CALIB_OVERFLOW_SIZE 0x1
-#define GC_XO_DXO_INT_STATE_SLOW_CALIB_OVERFLOW_DEFAULT 0x0
-#define GC_XO_DXO_INT_STATE_SLOW_CALIB_OVERFLOW_OFFSET 0x21c
-#define GC_XO_DXO_INT_STATE_SLOW_CALIB_UNDERRUN_LSB 0x3
-#define GC_XO_DXO_INT_STATE_SLOW_CALIB_UNDERRUN_MASK 0x8
-#define GC_XO_DXO_INT_STATE_SLOW_CALIB_UNDERRUN_SIZE 0x1
-#define GC_XO_DXO_INT_STATE_SLOW_CALIB_UNDERRUN_DEFAULT 0x0
-#define GC_XO_DXO_INT_STATE_SLOW_CALIB_UNDERRUN_OFFSET 0x21c
-#define GC_XO_DXO_INT_STATE_CLK_JTR_NOP_SEEN_LSB 0x4
-#define GC_XO_DXO_INT_STATE_CLK_JTR_NOP_SEEN_MASK 0x10
-#define GC_XO_DXO_INT_STATE_CLK_JTR_NOP_SEEN_SIZE 0x1
-#define GC_XO_DXO_INT_STATE_CLK_JTR_NOP_SEEN_DEFAULT 0x0
-#define GC_XO_DXO_INT_STATE_CLK_JTR_NOP_SEEN_OFFSET 0x21c
-#define GC_XO_DXO_INT_STATE_CLK_TIMER_NOP_SEEN_LSB 0x5
-#define GC_XO_DXO_INT_STATE_CLK_TIMER_NOP_SEEN_MASK 0x20
-#define GC_XO_DXO_INT_STATE_CLK_TIMER_NOP_SEEN_SIZE 0x1
-#define GC_XO_DXO_INT_STATE_CLK_TIMER_NOP_SEEN_DEFAULT 0x0
-#define GC_XO_DXO_INT_STATE_CLK_TIMER_NOP_SEEN_OFFSET 0x21c
-#define GC_XO_DXO_INT_STATE_CLK_JTR_SW_TRIM_DONE_LSB 0x6
-#define GC_XO_DXO_INT_STATE_CLK_JTR_SW_TRIM_DONE_MASK 0x40
-#define GC_XO_DXO_INT_STATE_CLK_JTR_SW_TRIM_DONE_SIZE 0x1
-#define GC_XO_DXO_INT_STATE_CLK_JTR_SW_TRIM_DONE_DEFAULT 0x0
-#define GC_XO_DXO_INT_STATE_CLK_JTR_SW_TRIM_DONE_OFFSET 0x21c
-#define GC_XO_DXO_INT_STATE_CLK_TIMER_SW_TRIM_DONE_LSB 0x7
-#define GC_XO_DXO_INT_STATE_CLK_TIMER_SW_TRIM_DONE_MASK 0x80
-#define GC_XO_DXO_INT_STATE_CLK_TIMER_SW_TRIM_DONE_SIZE 0x1
-#define GC_XO_DXO_INT_STATE_CLK_TIMER_SW_TRIM_DONE_DEFAULT 0x0
-#define GC_XO_DXO_INT_STATE_CLK_TIMER_SW_TRIM_DONE_OFFSET 0x21c
-#define GC_XO_DXO_INT_TEST_FAST_CALIB_OVERFLOW_LSB 0x0
-#define GC_XO_DXO_INT_TEST_FAST_CALIB_OVERFLOW_MASK 0x1
-#define GC_XO_DXO_INT_TEST_FAST_CALIB_OVERFLOW_SIZE 0x1
-#define GC_XO_DXO_INT_TEST_FAST_CALIB_OVERFLOW_DEFAULT 0x0
-#define GC_XO_DXO_INT_TEST_FAST_CALIB_OVERFLOW_OFFSET 0x220
-#define GC_XO_DXO_INT_TEST_FAST_CALIB_UNDERRUN_LSB 0x1
-#define GC_XO_DXO_INT_TEST_FAST_CALIB_UNDERRUN_MASK 0x2
-#define GC_XO_DXO_INT_TEST_FAST_CALIB_UNDERRUN_SIZE 0x1
-#define GC_XO_DXO_INT_TEST_FAST_CALIB_UNDERRUN_DEFAULT 0x0
-#define GC_XO_DXO_INT_TEST_FAST_CALIB_UNDERRUN_OFFSET 0x220
-#define GC_XO_DXO_INT_TEST_SLOW_CALIB_OVERFLOW_LSB 0x2
-#define GC_XO_DXO_INT_TEST_SLOW_CALIB_OVERFLOW_MASK 0x4
-#define GC_XO_DXO_INT_TEST_SLOW_CALIB_OVERFLOW_SIZE 0x1
-#define GC_XO_DXO_INT_TEST_SLOW_CALIB_OVERFLOW_DEFAULT 0x0
-#define GC_XO_DXO_INT_TEST_SLOW_CALIB_OVERFLOW_OFFSET 0x220
-#define GC_XO_DXO_INT_TEST_SLOW_CALIB_UNDERRUN_LSB 0x3
-#define GC_XO_DXO_INT_TEST_SLOW_CALIB_UNDERRUN_MASK 0x8
-#define GC_XO_DXO_INT_TEST_SLOW_CALIB_UNDERRUN_SIZE 0x1
-#define GC_XO_DXO_INT_TEST_SLOW_CALIB_UNDERRUN_DEFAULT 0x0
-#define GC_XO_DXO_INT_TEST_SLOW_CALIB_UNDERRUN_OFFSET 0x220
-#define GC_XO_DXO_INT_TEST_CLK_JTR_NOP_SEEN_LSB  0x4
-#define GC_XO_DXO_INT_TEST_CLK_JTR_NOP_SEEN_MASK 0x10
-#define GC_XO_DXO_INT_TEST_CLK_JTR_NOP_SEEN_SIZE 0x1
-#define GC_XO_DXO_INT_TEST_CLK_JTR_NOP_SEEN_DEFAULT 0x0
-#define GC_XO_DXO_INT_TEST_CLK_JTR_NOP_SEEN_OFFSET 0x220
-#define GC_XO_DXO_INT_TEST_CLK_TIMER_NOP_SEEN_LSB 0x5
-#define GC_XO_DXO_INT_TEST_CLK_TIMER_NOP_SEEN_MASK 0x20
-#define GC_XO_DXO_INT_TEST_CLK_TIMER_NOP_SEEN_SIZE 0x1
-#define GC_XO_DXO_INT_TEST_CLK_TIMER_NOP_SEEN_DEFAULT 0x0
-#define GC_XO_DXO_INT_TEST_CLK_TIMER_NOP_SEEN_OFFSET 0x220
-#define GC_XO_DXO_INT_TEST_CLK_JTR_SW_TRIM_DONE_LSB 0x6
-#define GC_XO_DXO_INT_TEST_CLK_JTR_SW_TRIM_DONE_MASK 0x40
-#define GC_XO_DXO_INT_TEST_CLK_JTR_SW_TRIM_DONE_SIZE 0x1
-#define GC_XO_DXO_INT_TEST_CLK_JTR_SW_TRIM_DONE_DEFAULT 0x0
-#define GC_XO_DXO_INT_TEST_CLK_JTR_SW_TRIM_DONE_OFFSET 0x220
-#define GC_XO_DXO_INT_TEST_CLK_TIMER_SW_TRIM_DONE_LSB 0x7
-#define GC_XO_DXO_INT_TEST_CLK_TIMER_SW_TRIM_DONE_MASK 0x80
-#define GC_XO_DXO_INT_TEST_CLK_TIMER_SW_TRIM_DONE_SIZE 0x1
-#define GC_XO_DXO_INT_TEST_CLK_TIMER_SW_TRIM_DONE_DEFAULT 0x0
-#define GC_XO_DXO_INT_TEST_CLK_TIMER_SW_TRIM_DONE_OFFSET 0x220
-#define GC_M3_ITM_TCR_ITMENA_LSB                 0x0
-#define GC_M3_ITM_TCR_ITMENA_MASK                0x1
-#define GC_M3_ITM_TCR_ITMENA_SIZE                0x1
-#define GC_M3_ITM_TCR_ITMENA_DEFAULT             0x0
-#define GC_M3_ITM_TCR_ITMENA_OFFSET              0xe80
-#define GC_M3_ITM_TCR_TSENA_LSB                  0x1
-#define GC_M3_ITM_TCR_TSENA_MASK                 0x2
-#define GC_M3_ITM_TCR_TSENA_SIZE                 0x1
-#define GC_M3_ITM_TCR_TSENA_DEFAULT              0x0
-#define GC_M3_ITM_TCR_TSENA_OFFSET               0xe80
-#define GC_M3_ITM_TCR_SYNCENA_LSB                0x2
-#define GC_M3_ITM_TCR_SYNCENA_MASK               0x4
-#define GC_M3_ITM_TCR_SYNCENA_SIZE               0x1
-#define GC_M3_ITM_TCR_SYNCENA_DEFAULT            0x0
-#define GC_M3_ITM_TCR_SYNCENA_OFFSET             0xe80
-#define GC_M3_ITM_TCR_DWTENA_LSB                 0x3
-#define GC_M3_ITM_TCR_DWTENA_MASK                0x8
-#define GC_M3_ITM_TCR_DWTENA_SIZE                0x1
-#define GC_M3_ITM_TCR_DWTENA_DEFAULT             0x0
-#define GC_M3_ITM_TCR_DWTENA_OFFSET              0xe80
-#define GC_M3_ITM_TCR_SWOENA_LSB                 0x4
-#define GC_M3_ITM_TCR_SWOENA_MASK                0x10
-#define GC_M3_ITM_TCR_SWOENA_SIZE                0x1
-#define GC_M3_ITM_TCR_SWOENA_DEFAULT             0x0
-#define GC_M3_ITM_TCR_SWOENA_OFFSET              0xe80
-#define GC_M3_ITM_TCR_TSPRESCALE_LSB             0x8
-#define GC_M3_ITM_TCR_TSPRESCALE_MASK            0x300
-#define GC_M3_ITM_TCR_TSPRESCALE_SIZE            0x2
-#define GC_M3_ITM_TCR_TSPRESCALE_DEFAULT         0x0
-#define GC_M3_ITM_TCR_TSPRESCALE_OFFSET          0xe80
-#define GC_M3_ITM_TCR_ATBID_LSB                  0x10
-#define GC_M3_ITM_TCR_ATBID_MASK                 0x7f0000
-#define GC_M3_ITM_TCR_ATBID_SIZE                 0x7
-#define GC_M3_ITM_TCR_ATBID_DEFAULT              0x0
-#define GC_M3_ITM_TCR_ATBID_OFFSET               0xe80
-#define GC_M3_ITM_TCR_BUSY_LSB                   0x17
-#define GC_M3_ITM_TCR_BUSY_MASK                  0x800000
-#define GC_M3_ITM_TCR_BUSY_SIZE                  0x1
-#define GC_M3_ITM_TCR_BUSY_DEFAULT               0x0
-#define GC_M3_ITM_TCR_BUSY_OFFSET                0xe80
-#define GC_M3_ITM_LOCKSREG_PRESENT_LSB           0x0
-#define GC_M3_ITM_LOCKSREG_PRESENT_MASK          0x1
-#define GC_M3_ITM_LOCKSREG_PRESENT_SIZE          0x1
-#define GC_M3_ITM_LOCKSREG_PRESENT_DEFAULT       0x0
-#define GC_M3_ITM_LOCKSREG_PRESENT_OFFSET        0xfb4
-#define GC_M3_ITM_LOCKSREG_ACCESS_LSB            0x1
-#define GC_M3_ITM_LOCKSREG_ACCESS_MASK           0x2
-#define GC_M3_ITM_LOCKSREG_ACCESS_SIZE           0x1
-#define GC_M3_ITM_LOCKSREG_ACCESS_DEFAULT        0x0
-#define GC_M3_ITM_LOCKSREG_ACCESS_OFFSET         0xfb4
-#define GC_M3_ITM_LOCKSREG_BYTEACC_LSB           0x2
-#define GC_M3_ITM_LOCKSREG_BYTEACC_MASK          0x4
-#define GC_M3_ITM_LOCKSREG_BYTEACC_SIZE          0x1
-#define GC_M3_ITM_LOCKSREG_BYTEACC_DEFAULT       0x0
-#define GC_M3_ITM_LOCKSREG_BYTEACC_OFFSET        0xfb4
-#define GC_M3_DWT_CTRL_CYCCNTENA_LSB             0x0
-#define GC_M3_DWT_CTRL_CYCCNTENA_MASK            0x1
-#define GC_M3_DWT_CTRL_CYCCNTENA_SIZE            0x1
-#define GC_M3_DWT_CTRL_CYCCNTENA_DEFAULT         0x0
-#define GC_M3_DWT_CTRL_CYCCNTENA_OFFSET          0x1000
-#define GC_M3_DWT_CTRL_POSTRESET_LSB             0x1
-#define GC_M3_DWT_CTRL_POSTRESET_MASK            0x1e
-#define GC_M3_DWT_CTRL_POSTRESET_SIZE            0x4
-#define GC_M3_DWT_CTRL_POSTRESET_DEFAULT         0x0
-#define GC_M3_DWT_CTRL_POSTRESET_OFFSET          0x1000
-#define GC_M3_DWT_CTRL_POSTCNT_LSB               0x5
-#define GC_M3_DWT_CTRL_POSTCNT_MASK              0x1e0
-#define GC_M3_DWT_CTRL_POSTCNT_SIZE              0x4
-#define GC_M3_DWT_CTRL_POSTCNT_DEFAULT           0x0
-#define GC_M3_DWT_CTRL_POSTCNT_OFFSET            0x1000
-#define GC_M3_DWT_CTRL_CYCTAP_LSB                0x9
-#define GC_M3_DWT_CTRL_CYCTAP_MASK               0x200
-#define GC_M3_DWT_CTRL_CYCTAP_SIZE               0x1
-#define GC_M3_DWT_CTRL_CYCTAP_DEFAULT            0x0
-#define GC_M3_DWT_CTRL_CYCTAP_OFFSET             0x1000
-#define GC_M3_DWT_CTRL_SYNCTAP_LSB               0xa
-#define GC_M3_DWT_CTRL_SYNCTAP_MASK              0xc00
-#define GC_M3_DWT_CTRL_SYNCTAP_SIZE              0x2
-#define GC_M3_DWT_CTRL_SYNCTAP_DEFAULT           0x0
-#define GC_M3_DWT_CTRL_SYNCTAP_OFFSET            0x1000
-#define GC_M3_DWT_CTRL_PCSAMPLENA_LSB            0xc
-#define GC_M3_DWT_CTRL_PCSAMPLENA_MASK           0x1000
-#define GC_M3_DWT_CTRL_PCSAMPLENA_SIZE           0x1
-#define GC_M3_DWT_CTRL_PCSAMPLENA_DEFAULT        0x0
-#define GC_M3_DWT_CTRL_PCSAMPLENA_OFFSET         0x1000
-#define GC_M3_DWT_CTRL_EXCTRCENA_LSB             0x10
-#define GC_M3_DWT_CTRL_EXCTRCENA_MASK            0x10000
-#define GC_M3_DWT_CTRL_EXCTRCENA_SIZE            0x1
-#define GC_M3_DWT_CTRL_EXCTRCENA_DEFAULT         0x0
-#define GC_M3_DWT_CTRL_EXCTRCENA_OFFSET          0x1000
-#define GC_M3_DWT_CTRL_CPIEVTENA_LSB             0x11
-#define GC_M3_DWT_CTRL_CPIEVTENA_MASK            0x20000
-#define GC_M3_DWT_CTRL_CPIEVTENA_SIZE            0x1
-#define GC_M3_DWT_CTRL_CPIEVTENA_DEFAULT         0x0
-#define GC_M3_DWT_CTRL_CPIEVTENA_OFFSET          0x1000
-#define GC_M3_DWT_CTRL_EXCEVTENA_LSB             0x12
-#define GC_M3_DWT_CTRL_EXCEVTENA_MASK            0x40000
-#define GC_M3_DWT_CTRL_EXCEVTENA_SIZE            0x1
-#define GC_M3_DWT_CTRL_EXCEVTENA_DEFAULT         0x0
-#define GC_M3_DWT_CTRL_EXCEVTENA_OFFSET          0x1000
-#define GC_M3_DWT_CTRL_SLEEPEVTENA_LSB           0x13
-#define GC_M3_DWT_CTRL_SLEEPEVTENA_MASK          0x80000
-#define GC_M3_DWT_CTRL_SLEEPEVTENA_SIZE          0x1
-#define GC_M3_DWT_CTRL_SLEEPEVTENA_DEFAULT       0x0
-#define GC_M3_DWT_CTRL_SLEEPEVTENA_OFFSET        0x1000
-#define GC_M3_DWT_CTRL_LSUEVTENA_LSB             0x14
-#define GC_M3_DWT_CTRL_LSUEVTENA_MASK            0x100000
-#define GC_M3_DWT_CTRL_LSUEVTENA_SIZE            0x1
-#define GC_M3_DWT_CTRL_LSUEVTENA_DEFAULT         0x0
-#define GC_M3_DWT_CTRL_LSUEVTENA_OFFSET          0x1000
-#define GC_M3_DWT_CTRL_FOLDEVTENA_LSB            0x15
-#define GC_M3_DWT_CTRL_FOLDEVTENA_MASK           0x200000
-#define GC_M3_DWT_CTRL_FOLDEVTENA_SIZE           0x1
-#define GC_M3_DWT_CTRL_FOLDEVTENA_DEFAULT        0x0
-#define GC_M3_DWT_CTRL_FOLDEVTENA_OFFSET         0x1000
-#define GC_M3_DWT_CTRL_CYCEVTENA_LSB             0x16
-#define GC_M3_DWT_CTRL_CYCEVTENA_MASK            0x400000
-#define GC_M3_DWT_CTRL_CYCEVTENA_SIZE            0x1
-#define GC_M3_DWT_CTRL_CYCEVTENA_DEFAULT         0x0
-#define GC_M3_DWT_CTRL_CYCEVTENA_OFFSET          0x1000
-#define GC_M3_DWT_CTRL_NUMCOMP_LSB               0x1c
-#define GC_M3_DWT_CTRL_NUMCOMP_MASK              0xf0000000
-#define GC_M3_DWT_CTRL_NUMCOMP_SIZE              0x4
-#define GC_M3_DWT_CTRL_NUMCOMP_DEFAULT           0x4
-#define GC_M3_DWT_CTRL_NUMCOMP_OFFSET            0x1000
-#define GC_M3_DWT_FUNCTION0_FUNCTION_LSB         0x0
-#define GC_M3_DWT_FUNCTION0_FUNCTION_MASK        0xf
-#define GC_M3_DWT_FUNCTION0_FUNCTION_SIZE        0x4
-#define GC_M3_DWT_FUNCTION0_FUNCTION_DEFAULT     0x0
-#define GC_M3_DWT_FUNCTION0_FUNCTION_OFFSET      0x1028
-#define GC_M3_DWT_FUNCTION0_EMITRANGE_LSB        0x5
-#define GC_M3_DWT_FUNCTION0_EMITRANGE_MASK       0x20
-#define GC_M3_DWT_FUNCTION0_EMITRANGE_SIZE       0x1
-#define GC_M3_DWT_FUNCTION0_EMITRANGE_DEFAULT    0x0
-#define GC_M3_DWT_FUNCTION0_EMITRANGE_OFFSET     0x1028
-#define GC_M3_DWT_FUNCTION0_CYCMATCH_LSB         0x7
-#define GC_M3_DWT_FUNCTION0_CYCMATCH_MASK        0x80
-#define GC_M3_DWT_FUNCTION0_CYCMATCH_SIZE        0x1
-#define GC_M3_DWT_FUNCTION0_CYCMATCH_DEFAULT     0x0
-#define GC_M3_DWT_FUNCTION0_CYCMATCH_OFFSET      0x1028
-#define GC_M3_DWT_FUNCTION0_LNK1ENA_LSB          0x9
-#define GC_M3_DWT_FUNCTION0_LNK1ENA_MASK         0x200
-#define GC_M3_DWT_FUNCTION0_LNK1ENA_SIZE         0x1
-#define GC_M3_DWT_FUNCTION0_LNK1ENA_DEFAULT      0x0
-#define GC_M3_DWT_FUNCTION0_LNK1ENA_OFFSET       0x1028
-#define GC_M3_DWT_FUNCTION0_DATAVSIZE_LSB        0xa
-#define GC_M3_DWT_FUNCTION0_DATAVSIZE_MASK       0xc00
-#define GC_M3_DWT_FUNCTION0_DATAVSIZE_SIZE       0x2
-#define GC_M3_DWT_FUNCTION0_DATAVSIZE_DEFAULT    0x0
-#define GC_M3_DWT_FUNCTION0_DATAVSIZE_OFFSET     0x1028
-#define GC_M3_DWT_FUNCTION0_MATCHED_LSB          0x18
-#define GC_M3_DWT_FUNCTION0_MATCHED_MASK         0x1000000
-#define GC_M3_DWT_FUNCTION0_MATCHED_SIZE         0x1
-#define GC_M3_DWT_FUNCTION0_MATCHED_DEFAULT      0x0
-#define GC_M3_DWT_FUNCTION0_MATCHED_OFFSET       0x1028
-#define GC_M3_DWT_FUNCTION1_FUNCTION_LSB         0x0
-#define GC_M3_DWT_FUNCTION1_FUNCTION_MASK        0xf
-#define GC_M3_DWT_FUNCTION1_FUNCTION_SIZE        0x4
-#define GC_M3_DWT_FUNCTION1_FUNCTION_DEFAULT     0x0
-#define GC_M3_DWT_FUNCTION1_FUNCTION_OFFSET      0x1038
-#define GC_M3_DWT_FUNCTION1_EMITRANGE_LSB        0x5
-#define GC_M3_DWT_FUNCTION1_EMITRANGE_MASK       0x20
-#define GC_M3_DWT_FUNCTION1_EMITRANGE_SIZE       0x1
-#define GC_M3_DWT_FUNCTION1_EMITRANGE_DEFAULT    0x0
-#define GC_M3_DWT_FUNCTION1_EMITRANGE_OFFSET     0x1038
-#define GC_M3_DWT_FUNCTION1_DATAVMATCH_LSB       0x8
-#define GC_M3_DWT_FUNCTION1_DATAVMATCH_MASK      0x100
-#define GC_M3_DWT_FUNCTION1_DATAVMATCH_SIZE      0x1
-#define GC_M3_DWT_FUNCTION1_DATAVMATCH_DEFAULT   0x0
-#define GC_M3_DWT_FUNCTION1_DATAVMATCH_OFFSET    0x1038
-#define GC_M3_DWT_FUNCTION1_LNK1ENA_LSB          0x9
-#define GC_M3_DWT_FUNCTION1_LNK1ENA_MASK         0x200
-#define GC_M3_DWT_FUNCTION1_LNK1ENA_SIZE         0x1
-#define GC_M3_DWT_FUNCTION1_LNK1ENA_DEFAULT      0x0
-#define GC_M3_DWT_FUNCTION1_LNK1ENA_OFFSET       0x1038
-#define GC_M3_DWT_FUNCTION1_DATAVSIZE_LSB        0xa
-#define GC_M3_DWT_FUNCTION1_DATAVSIZE_MASK       0xc00
-#define GC_M3_DWT_FUNCTION1_DATAVSIZE_SIZE       0x2
-#define GC_M3_DWT_FUNCTION1_DATAVSIZE_DEFAULT    0x0
-#define GC_M3_DWT_FUNCTION1_DATAVSIZE_OFFSET     0x1038
-#define GC_M3_DWT_FUNCTION1_DATAVADDR0_LSB       0xc
-#define GC_M3_DWT_FUNCTION1_DATAVADDR0_MASK      0xf000
-#define GC_M3_DWT_FUNCTION1_DATAVADDR0_SIZE      0x4
-#define GC_M3_DWT_FUNCTION1_DATAVADDR0_DEFAULT   0x0
-#define GC_M3_DWT_FUNCTION1_DATAVADDR0_OFFSET    0x1038
-#define GC_M3_DWT_FUNCTION1_DATAVADDR1_LSB       0x10
-#define GC_M3_DWT_FUNCTION1_DATAVADDR1_MASK      0xf0000
-#define GC_M3_DWT_FUNCTION1_DATAVADDR1_SIZE      0x4
-#define GC_M3_DWT_FUNCTION1_DATAVADDR1_DEFAULT   0x0
-#define GC_M3_DWT_FUNCTION1_DATAVADDR1_OFFSET    0x1038
-#define GC_M3_DWT_FUNCTION1_MATCHED_LSB          0x18
-#define GC_M3_DWT_FUNCTION1_MATCHED_MASK         0x1000000
-#define GC_M3_DWT_FUNCTION1_MATCHED_SIZE         0x1
-#define GC_M3_DWT_FUNCTION1_MATCHED_DEFAULT      0x0
-#define GC_M3_DWT_FUNCTION1_MATCHED_OFFSET       0x1038
-#define GC_M3_DWT_FUNCTION2_FUNCTION_LSB         0x0
-#define GC_M3_DWT_FUNCTION2_FUNCTION_MASK        0xf
-#define GC_M3_DWT_FUNCTION2_FUNCTION_SIZE        0x4
-#define GC_M3_DWT_FUNCTION2_FUNCTION_DEFAULT     0x0
-#define GC_M3_DWT_FUNCTION2_FUNCTION_OFFSET      0x1048
-#define GC_M3_DWT_FUNCTION2_EMITRANGE_LSB        0x5
-#define GC_M3_DWT_FUNCTION2_EMITRANGE_MASK       0x20
-#define GC_M3_DWT_FUNCTION2_EMITRANGE_SIZE       0x1
-#define GC_M3_DWT_FUNCTION2_EMITRANGE_DEFAULT    0x0
-#define GC_M3_DWT_FUNCTION2_EMITRANGE_OFFSET     0x1048
-#define GC_M3_DWT_FUNCTION2_LNK1ENA_LSB          0x9
-#define GC_M3_DWT_FUNCTION2_LNK1ENA_MASK         0x200
-#define GC_M3_DWT_FUNCTION2_LNK1ENA_SIZE         0x1
-#define GC_M3_DWT_FUNCTION2_LNK1ENA_DEFAULT      0x0
-#define GC_M3_DWT_FUNCTION2_LNK1ENA_OFFSET       0x1048
-#define GC_M3_DWT_FUNCTION2_DATAVSIZE_LSB        0xa
-#define GC_M3_DWT_FUNCTION2_DATAVSIZE_MASK       0xc00
-#define GC_M3_DWT_FUNCTION2_DATAVSIZE_SIZE       0x2
-#define GC_M3_DWT_FUNCTION2_DATAVSIZE_DEFAULT    0x0
-#define GC_M3_DWT_FUNCTION2_DATAVSIZE_OFFSET     0x1048
-#define GC_M3_DWT_FUNCTION2_MATCHED_LSB          0x18
-#define GC_M3_DWT_FUNCTION2_MATCHED_MASK         0x1000000
-#define GC_M3_DWT_FUNCTION2_MATCHED_SIZE         0x1
-#define GC_M3_DWT_FUNCTION2_MATCHED_DEFAULT      0x0
-#define GC_M3_DWT_FUNCTION2_MATCHED_OFFSET       0x1048
-#define GC_M3_DWT_FUNCTION3_FUNCTION_LSB         0x0
-#define GC_M3_DWT_FUNCTION3_FUNCTION_MASK        0xf
-#define GC_M3_DWT_FUNCTION3_FUNCTION_SIZE        0x4
-#define GC_M3_DWT_FUNCTION3_FUNCTION_DEFAULT     0x0
-#define GC_M3_DWT_FUNCTION3_FUNCTION_OFFSET      0x1058
-#define GC_M3_DWT_FUNCTION3_EMITRANGE_LSB        0x5
-#define GC_M3_DWT_FUNCTION3_EMITRANGE_MASK       0x20
-#define GC_M3_DWT_FUNCTION3_EMITRANGE_SIZE       0x1
-#define GC_M3_DWT_FUNCTION3_EMITRANGE_DEFAULT    0x0
-#define GC_M3_DWT_FUNCTION3_EMITRANGE_OFFSET     0x1058
-#define GC_M3_DWT_FUNCTION3_LNK1ENA_LSB          0x9
-#define GC_M3_DWT_FUNCTION3_LNK1ENA_MASK         0x200
-#define GC_M3_DWT_FUNCTION3_LNK1ENA_SIZE         0x1
-#define GC_M3_DWT_FUNCTION3_LNK1ENA_DEFAULT      0x0
-#define GC_M3_DWT_FUNCTION3_LNK1ENA_OFFSET       0x1058
-#define GC_M3_DWT_FUNCTION3_DATAVSIZE_LSB        0xa
-#define GC_M3_DWT_FUNCTION3_DATAVSIZE_MASK       0xc00
-#define GC_M3_DWT_FUNCTION3_DATAVSIZE_SIZE       0x2
-#define GC_M3_DWT_FUNCTION3_DATAVSIZE_DEFAULT    0x0
-#define GC_M3_DWT_FUNCTION3_DATAVSIZE_OFFSET     0x1058
-#define GC_M3_DWT_FUNCTION3_MATCHED_LSB          0x18
-#define GC_M3_DWT_FUNCTION3_MATCHED_MASK         0x1000000
-#define GC_M3_DWT_FUNCTION3_MATCHED_SIZE         0x1
-#define GC_M3_DWT_FUNCTION3_MATCHED_DEFAULT      0x0
-#define GC_M3_DWT_FUNCTION3_MATCHED_OFFSET       0x1058
-#define GC_M3_FP_CTRL_ENABLE_LSB                 0x0
-#define GC_M3_FP_CTRL_ENABLE_MASK                0x1
-#define GC_M3_FP_CTRL_ENABLE_SIZE                0x1
-#define GC_M3_FP_CTRL_ENABLE_DEFAULT             0x0
-#define GC_M3_FP_CTRL_ENABLE_OFFSET              0x2000
-#define GC_M3_FP_CTRL_KEY_LSB                    0x1
-#define GC_M3_FP_CTRL_KEY_MASK                   0x2
-#define GC_M3_FP_CTRL_KEY_SIZE                   0x1
-#define GC_M3_FP_CTRL_KEY_DEFAULT                0x0
-#define GC_M3_FP_CTRL_KEY_OFFSET                 0x2000
-#define GC_M3_FP_CTRL_NUM_CODE1_LSB              0x4
-#define GC_M3_FP_CTRL_NUM_CODE1_MASK             0xf0
-#define GC_M3_FP_CTRL_NUM_CODE1_SIZE             0x4
-#define GC_M3_FP_CTRL_NUM_CODE1_DEFAULT          0x6
-#define GC_M3_FP_CTRL_NUM_CODE1_OFFSET           0x2000
-#define GC_M3_FP_CTRL_NUM_LIT_LSB                0x8
-#define GC_M3_FP_CTRL_NUM_LIT_MASK               0xf00
-#define GC_M3_FP_CTRL_NUM_LIT_SIZE               0x4
-#define GC_M3_FP_CTRL_NUM_LIT_DEFAULT            0x2
-#define GC_M3_FP_CTRL_NUM_LIT_OFFSET             0x2000
-#define GC_M3_FP_CTRL_NUM_CODE2_LSB              0xc
-#define GC_M3_FP_CTRL_NUM_CODE2_MASK             0x3000
-#define GC_M3_FP_CTRL_NUM_CODE2_SIZE             0x2
-#define GC_M3_FP_CTRL_NUM_CODE2_DEFAULT          0x0
-#define GC_M3_FP_CTRL_NUM_CODE2_OFFSET           0x2000
-#define GC_M3_FP_REMAP_REMAP_LSB                 0x5
-#define GC_M3_FP_REMAP_REMAP_MASK                0x1fffffe0
-#define GC_M3_FP_REMAP_REMAP_SIZE                0x18
-#define GC_M3_FP_REMAP_REMAP_DEFAULT             0x0
-#define GC_M3_FP_REMAP_REMAP_OFFSET              0x2004
-#define GC_M3_FP_COMP0_ENABLE_LSB                0x0
-#define GC_M3_FP_COMP0_ENABLE_MASK               0x1
-#define GC_M3_FP_COMP0_ENABLE_SIZE               0x1
-#define GC_M3_FP_COMP0_ENABLE_DEFAULT            0x0
-#define GC_M3_FP_COMP0_ENABLE_OFFSET             0x2008
-#define GC_M3_FP_COMP0_COMP_LSB                  0x2
-#define GC_M3_FP_COMP0_COMP_MASK                 0x1ffffffc
-#define GC_M3_FP_COMP0_COMP_SIZE                 0x1b
-#define GC_M3_FP_COMP0_COMP_DEFAULT              0x0
-#define GC_M3_FP_COMP0_COMP_OFFSET               0x2008
-#define GC_M3_FP_COMP0_REPLACE_LSB               0x1e
-#define GC_M3_FP_COMP0_REPLACE_MASK              0xc0000000
-#define GC_M3_FP_COMP0_REPLACE_SIZE              0x2
-#define GC_M3_FP_COMP0_REPLACE_DEFAULT           0x0
-#define GC_M3_FP_COMP0_REPLACE_OFFSET            0x2008
-#define GC_M3_FP_COMP1_ENABLE_LSB                0x0
-#define GC_M3_FP_COMP1_ENABLE_MASK               0x1
-#define GC_M3_FP_COMP1_ENABLE_SIZE               0x1
-#define GC_M3_FP_COMP1_ENABLE_DEFAULT            0x0
-#define GC_M3_FP_COMP1_ENABLE_OFFSET             0x200c
-#define GC_M3_FP_COMP1_COMP_LSB                  0x2
-#define GC_M3_FP_COMP1_COMP_MASK                 0x1ffffffc
-#define GC_M3_FP_COMP1_COMP_SIZE                 0x1b
-#define GC_M3_FP_COMP1_COMP_DEFAULT              0x0
-#define GC_M3_FP_COMP1_COMP_OFFSET               0x200c
-#define GC_M3_FP_COMP1_REPLACE_LSB               0x1e
-#define GC_M3_FP_COMP1_REPLACE_MASK              0xc0000000
-#define GC_M3_FP_COMP1_REPLACE_SIZE              0x2
-#define GC_M3_FP_COMP1_REPLACE_DEFAULT           0x0
-#define GC_M3_FP_COMP1_REPLACE_OFFSET            0x200c
-#define GC_M3_FP_COMP2_ENABLE_LSB                0x0
-#define GC_M3_FP_COMP2_ENABLE_MASK               0x1
-#define GC_M3_FP_COMP2_ENABLE_SIZE               0x1
-#define GC_M3_FP_COMP2_ENABLE_DEFAULT            0x0
-#define GC_M3_FP_COMP2_ENABLE_OFFSET             0x2010
-#define GC_M3_FP_COMP2_COMP_LSB                  0x2
-#define GC_M3_FP_COMP2_COMP_MASK                 0x1ffffffc
-#define GC_M3_FP_COMP2_COMP_SIZE                 0x1b
-#define GC_M3_FP_COMP2_COMP_DEFAULT              0x0
-#define GC_M3_FP_COMP2_COMP_OFFSET               0x2010
-#define GC_M3_FP_COMP2_REPLACE_LSB               0x1e
-#define GC_M3_FP_COMP2_REPLACE_MASK              0xc0000000
-#define GC_M3_FP_COMP2_REPLACE_SIZE              0x2
-#define GC_M3_FP_COMP2_REPLACE_DEFAULT           0x0
-#define GC_M3_FP_COMP2_REPLACE_OFFSET            0x2010
-#define GC_M3_FP_COMP3_ENABLE_LSB                0x0
-#define GC_M3_FP_COMP3_ENABLE_MASK               0x1
-#define GC_M3_FP_COMP3_ENABLE_SIZE               0x1
-#define GC_M3_FP_COMP3_ENABLE_DEFAULT            0x0
-#define GC_M3_FP_COMP3_ENABLE_OFFSET             0x2014
-#define GC_M3_FP_COMP3_COMP_LSB                  0x2
-#define GC_M3_FP_COMP3_COMP_MASK                 0x1ffffffc
-#define GC_M3_FP_COMP3_COMP_SIZE                 0x1b
-#define GC_M3_FP_COMP3_COMP_DEFAULT              0x0
-#define GC_M3_FP_COMP3_COMP_OFFSET               0x2014
-#define GC_M3_FP_COMP3_REPLACE_LSB               0x1e
-#define GC_M3_FP_COMP3_REPLACE_MASK              0xc0000000
-#define GC_M3_FP_COMP3_REPLACE_SIZE              0x2
-#define GC_M3_FP_COMP3_REPLACE_DEFAULT           0x0
-#define GC_M3_FP_COMP3_REPLACE_OFFSET            0x2014
-#define GC_M3_FP_COMP4_ENABLE_LSB                0x0
-#define GC_M3_FP_COMP4_ENABLE_MASK               0x1
-#define GC_M3_FP_COMP4_ENABLE_SIZE               0x1
-#define GC_M3_FP_COMP4_ENABLE_DEFAULT            0x0
-#define GC_M3_FP_COMP4_ENABLE_OFFSET             0x2018
-#define GC_M3_FP_COMP4_COMP_LSB                  0x2
-#define GC_M3_FP_COMP4_COMP_MASK                 0x1ffffffc
-#define GC_M3_FP_COMP4_COMP_SIZE                 0x1b
-#define GC_M3_FP_COMP4_COMP_DEFAULT              0x0
-#define GC_M3_FP_COMP4_COMP_OFFSET               0x2018
-#define GC_M3_FP_COMP4_REPLACE_LSB               0x1e
-#define GC_M3_FP_COMP4_REPLACE_MASK              0xc0000000
-#define GC_M3_FP_COMP4_REPLACE_SIZE              0x2
-#define GC_M3_FP_COMP4_REPLACE_DEFAULT           0x0
-#define GC_M3_FP_COMP4_REPLACE_OFFSET            0x2018
-#define GC_M3_FP_COMP5_ENABLE_LSB                0x0
-#define GC_M3_FP_COMP5_ENABLE_MASK               0x1
-#define GC_M3_FP_COMP5_ENABLE_SIZE               0x1
-#define GC_M3_FP_COMP5_ENABLE_DEFAULT            0x0
-#define GC_M3_FP_COMP5_ENABLE_OFFSET             0x201c
-#define GC_M3_FP_COMP5_COMP_LSB                  0x2
-#define GC_M3_FP_COMP5_COMP_MASK                 0x1ffffffc
-#define GC_M3_FP_COMP5_COMP_SIZE                 0x1b
-#define GC_M3_FP_COMP5_COMP_DEFAULT              0x0
-#define GC_M3_FP_COMP5_COMP_OFFSET               0x201c
-#define GC_M3_FP_COMP5_REPLACE_LSB               0x1e
-#define GC_M3_FP_COMP5_REPLACE_MASK              0xc0000000
-#define GC_M3_FP_COMP5_REPLACE_SIZE              0x2
-#define GC_M3_FP_COMP5_REPLACE_DEFAULT           0x0
-#define GC_M3_FP_COMP5_REPLACE_OFFSET            0x201c
-#define GC_M3_FP_COMP6_ENABLE_LSB                0x0
-#define GC_M3_FP_COMP6_ENABLE_MASK               0x1
-#define GC_M3_FP_COMP6_ENABLE_SIZE               0x1
-#define GC_M3_FP_COMP6_ENABLE_DEFAULT            0x0
-#define GC_M3_FP_COMP6_ENABLE_OFFSET             0x2020
-#define GC_M3_FP_COMP6_COMP_LSB                  0x2
-#define GC_M3_FP_COMP6_COMP_MASK                 0x1ffffffc
-#define GC_M3_FP_COMP6_COMP_SIZE                 0x1b
-#define GC_M3_FP_COMP6_COMP_DEFAULT              0x0
-#define GC_M3_FP_COMP6_COMP_OFFSET               0x2020
-#define GC_M3_FP_COMP6_REPLACE_LSB               0x1e
-#define GC_M3_FP_COMP6_REPLACE_MASK              0xc0000000
-#define GC_M3_FP_COMP6_REPLACE_SIZE              0x2
-#define GC_M3_FP_COMP6_REPLACE_DEFAULT           0x0
-#define GC_M3_FP_COMP6_REPLACE_OFFSET            0x2020
-#define GC_M3_FP_COMP7_ENABLE_LSB                0x0
-#define GC_M3_FP_COMP7_ENABLE_MASK               0x1
-#define GC_M3_FP_COMP7_ENABLE_SIZE               0x1
-#define GC_M3_FP_COMP7_ENABLE_DEFAULT            0x0
-#define GC_M3_FP_COMP7_ENABLE_OFFSET             0x2024
-#define GC_M3_FP_COMP7_COMP_LSB                  0x2
-#define GC_M3_FP_COMP7_COMP_MASK                 0x1ffffffc
-#define GC_M3_FP_COMP7_COMP_SIZE                 0x1b
-#define GC_M3_FP_COMP7_COMP_DEFAULT              0x0
-#define GC_M3_FP_COMP7_COMP_OFFSET               0x2024
-#define GC_M3_FP_COMP7_REPLACE_LSB               0x1e
-#define GC_M3_FP_COMP7_REPLACE_MASK              0xc0000000
-#define GC_M3_FP_COMP7_REPLACE_SIZE              0x2
-#define GC_M3_FP_COMP7_REPLACE_DEFAULT           0x0
-#define GC_M3_FP_COMP7_REPLACE_OFFSET            0x2024
-#define GC_M3_ICTR_INTLINESNUM_LSB               0x0
-#define GC_M3_ICTR_INTLINESNUM_MASK              0xf
-#define GC_M3_ICTR_INTLINESNUM_SIZE              0x4
-#define GC_M3_ICTR_INTLINESNUM_DEFAULT           0x7
-#define GC_M3_ICTR_INTLINESNUM_OFFSET            0xe004
-#define GC_M3_SYST_CSR_ENABLE_LSB                0x0
-#define GC_M3_SYST_CSR_ENABLE_MASK               0x1
-#define GC_M3_SYST_CSR_ENABLE_SIZE               0x1
-#define GC_M3_SYST_CSR_ENABLE_DEFAULT            0x0
-#define GC_M3_SYST_CSR_ENABLE_OFFSET             0xe010
-#define GC_M3_SYST_CSR_TICKINT_LSB               0x1
-#define GC_M3_SYST_CSR_TICKINT_MASK              0x2
-#define GC_M3_SYST_CSR_TICKINT_SIZE              0x1
-#define GC_M3_SYST_CSR_TICKINT_DEFAULT           0x0
-#define GC_M3_SYST_CSR_TICKINT_OFFSET            0xe010
-#define GC_M3_SYST_CSR_CLKSOURCE_LSB             0x2
-#define GC_M3_SYST_CSR_CLKSOURCE_MASK            0x4
-#define GC_M3_SYST_CSR_CLKSOURCE_SIZE            0x1
-#define GC_M3_SYST_CSR_CLKSOURCE_DEFAULT         0x1
-#define GC_M3_SYST_CSR_CLKSOURCE_OFFSET          0xe010
-#define GC_M3_SYST_CSR_COUNTFLAG_LSB             0x10
-#define GC_M3_SYST_CSR_COUNTFLAG_MASK            0x10000
-#define GC_M3_SYST_CSR_COUNTFLAG_SIZE            0x1
-#define GC_M3_SYST_CSR_COUNTFLAG_DEFAULT         0x0
-#define GC_M3_SYST_CSR_COUNTFLAG_OFFSET          0xe010
-#define GC_M3_SYST_RVR_RELOAD_LSB                0x0
-#define GC_M3_SYST_RVR_RELOAD_MASK               0xffffff
-#define GC_M3_SYST_RVR_RELOAD_SIZE               0x18
-#define GC_M3_SYST_RVR_RELOAD_DEFAULT            0x0
-#define GC_M3_SYST_RVR_RELOAD_OFFSET             0xe014
-#define GC_M3_SYST_CVR_CURRENT_LSB               0x0
-#define GC_M3_SYST_CVR_CURRENT_MASK              0xffffffff
-#define GC_M3_SYST_CVR_CURRENT_SIZE              0x20
-#define GC_M3_SYST_CVR_CURRENT_DEFAULT           0x0
-#define GC_M3_SYST_CVR_CURRENT_OFFSET            0xe018
-#define GC_M3_SYST_CALIB_TENMS_LSB               0x0
-#define GC_M3_SYST_CALIB_TENMS_MASK              0xffffff
-#define GC_M3_SYST_CALIB_TENMS_SIZE              0x18
-#define GC_M3_SYST_CALIB_TENMS_DEFAULT           0x3f79f
-#define GC_M3_SYST_CALIB_TENMS_OFFSET            0xe01c
-#define GC_M3_SYST_CALIB_SKEW_LSB                0x1e
-#define GC_M3_SYST_CALIB_SKEW_MASK               0x40000000
-#define GC_M3_SYST_CALIB_SKEW_SIZE               0x1
-#define GC_M3_SYST_CALIB_SKEW_DEFAULT            0x0
-#define GC_M3_SYST_CALIB_SKEW_OFFSET             0xe01c
-#define GC_M3_SYST_CALIB_NOREF_LSB               0x1f
-#define GC_M3_SYST_CALIB_NOREF_MASK              0x80000000
-#define GC_M3_SYST_CALIB_NOREF_SIZE              0x1
-#define GC_M3_SYST_CALIB_NOREF_DEFAULT           0x0
-#define GC_M3_SYST_CALIB_NOREF_OFFSET            0xe01c
-#define GC_M3_CPUID_REVISION_LSB                 0x0
-#define GC_M3_CPUID_REVISION_MASK                0xf
-#define GC_M3_CPUID_REVISION_SIZE                0x4
-#define GC_M3_CPUID_REVISION_DEFAULT             0x1
-#define GC_M3_CPUID_REVISION_OFFSET              0xed00
-#define GC_M3_CPUID_PARTNO_LSB                   0x4
-#define GC_M3_CPUID_PARTNO_MASK                  0xfff0
-#define GC_M3_CPUID_PARTNO_SIZE                  0xc
-#define GC_M3_CPUID_PARTNO_DEFAULT               0xc23
-#define GC_M3_CPUID_PARTNO_OFFSET                0xed00
-#define GC_M3_CPUID_CONSTANT_LSB                 0x10
-#define GC_M3_CPUID_CONSTANT_MASK                0xf0000
-#define GC_M3_CPUID_CONSTANT_SIZE                0x4
-#define GC_M3_CPUID_CONSTANT_DEFAULT             0xf
-#define GC_M3_CPUID_CONSTANT_OFFSET              0xed00
-#define GC_M3_CPUID_VARIANT_LSB                  0x14
-#define GC_M3_CPUID_VARIANT_MASK                 0xf00000
-#define GC_M3_CPUID_VARIANT_SIZE                 0x4
-#define GC_M3_CPUID_VARIANT_DEFAULT              0x2
-#define GC_M3_CPUID_VARIANT_OFFSET               0xed00
-#define GC_M3_CPUID_IMPLEMENTER_LSB              0x18
-#define GC_M3_CPUID_IMPLEMENTER_MASK             0xff000000
-#define GC_M3_CPUID_IMPLEMENTER_SIZE             0x8
-#define GC_M3_CPUID_IMPLEMENTER_DEFAULT          0x41
-#define GC_M3_CPUID_IMPLEMENTER_OFFSET           0xed00
-#define GC_M3_ICSR_VECTACTIVE_LSB                0x0
-#define GC_M3_ICSR_VECTACTIVE_MASK               0x1ff
-#define GC_M3_ICSR_VECTACTIVE_SIZE               0x9
-#define GC_M3_ICSR_VECTACTIVE_DEFAULT            0x0
-#define GC_M3_ICSR_VECTACTIVE_OFFSET             0xed04
-#define GC_M3_ICSR_RETTOBASE_LSB                 0xb
-#define GC_M3_ICSR_RETTOBASE_MASK                0x800
-#define GC_M3_ICSR_RETTOBASE_SIZE                0x1
-#define GC_M3_ICSR_RETTOBASE_DEFAULT             0x0
-#define GC_M3_ICSR_RETTOBASE_OFFSET              0xed04
-#define GC_M3_ICSR_VECTPENDING_LSB               0xc
-#define GC_M3_ICSR_VECTPENDING_MASK              0x3ff000
-#define GC_M3_ICSR_VECTPENDING_SIZE              0xa
-#define GC_M3_ICSR_VECTPENDING_DEFAULT           0x0
-#define GC_M3_ICSR_VECTPENDING_OFFSET            0xed04
-#define GC_M3_ICSR_ISRPENDING_LSB                0x16
-#define GC_M3_ICSR_ISRPENDING_MASK               0x400000
-#define GC_M3_ICSR_ISRPENDING_SIZE               0x1
-#define GC_M3_ICSR_ISRPENDING_DEFAULT            0x0
-#define GC_M3_ICSR_ISRPENDING_OFFSET             0xed04
-#define GC_M3_ICSR_ISRPREEMPT_LSB                0x17
-#define GC_M3_ICSR_ISRPREEMPT_MASK               0x800000
-#define GC_M3_ICSR_ISRPREEMPT_SIZE               0x1
-#define GC_M3_ICSR_ISRPREEMPT_DEFAULT            0x0
-#define GC_M3_ICSR_ISRPREEMPT_OFFSET             0xed04
-#define GC_M3_ICSR_PENDSTCLR_LSB                 0x19
-#define GC_M3_ICSR_PENDSTCLR_MASK                0x2000000
-#define GC_M3_ICSR_PENDSTCLR_SIZE                0x1
-#define GC_M3_ICSR_PENDSTCLR_DEFAULT             0x0
-#define GC_M3_ICSR_PENDSTCLR_OFFSET              0xed04
-#define GC_M3_ICSR_PENDSTSET_LSB                 0x1a
-#define GC_M3_ICSR_PENDSTSET_MASK                0x4000000
-#define GC_M3_ICSR_PENDSTSET_SIZE                0x1
-#define GC_M3_ICSR_PENDSTSET_DEFAULT             0x0
-#define GC_M3_ICSR_PENDSTSET_OFFSET              0xed04
-#define GC_M3_ICSR_PENDSVCLR_LSB                 0x1b
-#define GC_M3_ICSR_PENDSVCLR_MASK                0x8000000
-#define GC_M3_ICSR_PENDSVCLR_SIZE                0x1
-#define GC_M3_ICSR_PENDSVCLR_DEFAULT             0x0
-#define GC_M3_ICSR_PENDSVCLR_OFFSET              0xed04
-#define GC_M3_ICSR_PENDSVSET_LSB                 0x1c
-#define GC_M3_ICSR_PENDSVSET_MASK                0x10000000
-#define GC_M3_ICSR_PENDSVSET_SIZE                0x1
-#define GC_M3_ICSR_PENDSVSET_DEFAULT             0x0
-#define GC_M3_ICSR_PENDSVSET_OFFSET              0xed04
-#define GC_M3_ICSR_NMIPENDSET_LSB                0x1f
-#define GC_M3_ICSR_NMIPENDSET_MASK               0x80000000
-#define GC_M3_ICSR_NMIPENDSET_SIZE               0x1
-#define GC_M3_ICSR_NMIPENDSET_DEFAULT            0x0
-#define GC_M3_ICSR_NMIPENDSET_OFFSET             0xed04
-#define GC_M3_SCR_SLEEPONEXIT_LSB                0x1
-#define GC_M3_SCR_SLEEPONEXIT_MASK               0x2
-#define GC_M3_SCR_SLEEPONEXIT_SIZE               0x1
-#define GC_M3_SCR_SLEEPONEXIT_DEFAULT            0x0
-#define GC_M3_SCR_SLEEPONEXIT_OFFSET             0xed10
-#define GC_M3_SCR_SLEEPDEEP_LSB                  0x2
-#define GC_M3_SCR_SLEEPDEEP_MASK                 0x4
-#define GC_M3_SCR_SLEEPDEEP_SIZE                 0x1
-#define GC_M3_SCR_SLEEPDEEP_DEFAULT              0x0
-#define GC_M3_SCR_SLEEPDEEP_OFFSET               0xed10
-#define GC_M3_SCR_SEVONPEND_LSB                  0x4
-#define GC_M3_SCR_SEVONPEND_MASK                 0x10
-#define GC_M3_SCR_SEVONPEND_SIZE                 0x1
-#define GC_M3_SCR_SEVONPEND_DEFAULT              0x0
-#define GC_M3_SCR_SEVONPEND_OFFSET               0xed10
-#define GC_M3_CCR_NONEBASETHRDENA_LSB            0x0
-#define GC_M3_CCR_NONEBASETHRDENA_MASK           0x1
-#define GC_M3_CCR_NONEBASETHRDENA_SIZE           0x1
-#define GC_M3_CCR_NONEBASETHRDENA_DEFAULT        0x0
-#define GC_M3_CCR_NONEBASETHRDENA_OFFSET         0xed14
-#define GC_M3_CCR_USERSETMPEND_LSB               0x1
-#define GC_M3_CCR_USERSETMPEND_MASK              0x2
-#define GC_M3_CCR_USERSETMPEND_SIZE              0x1
-#define GC_M3_CCR_USERSETMPEND_DEFAULT           0x0
-#define GC_M3_CCR_USERSETMPEND_OFFSET            0xed14
-#define GC_M3_CCR_UNALIGN_TRP_LSB                0x3
-#define GC_M3_CCR_UNALIGN_TRP_MASK               0x8
-#define GC_M3_CCR_UNALIGN_TRP_SIZE               0x1
-#define GC_M3_CCR_UNALIGN_TRP_DEFAULT            0x0
-#define GC_M3_CCR_UNALIGN_TRP_OFFSET             0xed14
-#define GC_M3_CCR_DIV_0_TRP_LSB                  0x4
-#define GC_M3_CCR_DIV_0_TRP_MASK                 0x10
-#define GC_M3_CCR_DIV_0_TRP_SIZE                 0x1
-#define GC_M3_CCR_DIV_0_TRP_DEFAULT              0x0
-#define GC_M3_CCR_DIV_0_TRP_OFFSET               0xed14
-#define GC_M3_CCR_BFHFNMIGN_LSB                  0x8
-#define GC_M3_CCR_BFHFNMIGN_MASK                 0x100
-#define GC_M3_CCR_BFHFNMIGN_SIZE                 0x1
-#define GC_M3_CCR_BFHFNMIGN_DEFAULT              0x0
-#define GC_M3_CCR_BFHFNMIGN_OFFSET               0xed14
-#define GC_M3_CCR_STKALIGN_LSB                   0x9
-#define GC_M3_CCR_STKALIGN_MASK                  0x200
-#define GC_M3_CCR_STKALIGN_SIZE                  0x1
-#define GC_M3_CCR_STKALIGN_DEFAULT               0x0
-#define GC_M3_CCR_STKALIGN_OFFSET                0xed14
-#define GC_M3_DEMCR_VC_CORERESET_LSB             0x0
-#define GC_M3_DEMCR_VC_CORERESET_MASK            0x1
-#define GC_M3_DEMCR_VC_CORERESET_SIZE            0x1
-#define GC_M3_DEMCR_VC_CORERESET_DEFAULT         0x0
-#define GC_M3_DEMCR_VC_CORERESET_OFFSET          0xedfc
-#define GC_M3_DEMCR_VC_MMERR_LSB                 0x4
-#define GC_M3_DEMCR_VC_MMERR_MASK                0x10
-#define GC_M3_DEMCR_VC_MMERR_SIZE                0x1
-#define GC_M3_DEMCR_VC_MMERR_DEFAULT             0x0
-#define GC_M3_DEMCR_VC_MMERR_OFFSET              0xedfc
-#define GC_M3_DEMCR_VC_NOCPERR_LSB               0x5
-#define GC_M3_DEMCR_VC_NOCPERR_MASK              0x20
-#define GC_M3_DEMCR_VC_NOCPERR_SIZE              0x1
-#define GC_M3_DEMCR_VC_NOCPERR_DEFAULT           0x0
-#define GC_M3_DEMCR_VC_NOCPERR_OFFSET            0xedfc
-#define GC_M3_DEMCR_VC_CHKERR_LSB                0x6
-#define GC_M3_DEMCR_VC_CHKERR_MASK               0x40
-#define GC_M3_DEMCR_VC_CHKERR_SIZE               0x1
-#define GC_M3_DEMCR_VC_CHKERR_DEFAULT            0x0
-#define GC_M3_DEMCR_VC_CHKERR_OFFSET             0xedfc
-#define GC_M3_DEMCR_VC_STATERR_LSB               0x7
-#define GC_M3_DEMCR_VC_STATERR_MASK              0x80
-#define GC_M3_DEMCR_VC_STATERR_SIZE              0x1
-#define GC_M3_DEMCR_VC_STATERR_DEFAULT           0x0
-#define GC_M3_DEMCR_VC_STATERR_OFFSET            0xedfc
-#define GC_M3_DEMCR_VC_BUSERR_LSB                0x8
-#define GC_M3_DEMCR_VC_BUSERR_MASK               0x100
-#define GC_M3_DEMCR_VC_BUSERR_SIZE               0x1
-#define GC_M3_DEMCR_VC_BUSERR_DEFAULT            0x0
-#define GC_M3_DEMCR_VC_BUSERR_OFFSET             0xedfc
-#define GC_M3_DEMCR_VC_INTERR_LSB                0x9
-#define GC_M3_DEMCR_VC_INTERR_MASK               0x200
-#define GC_M3_DEMCR_VC_INTERR_SIZE               0x1
-#define GC_M3_DEMCR_VC_INTERR_DEFAULT            0x0
-#define GC_M3_DEMCR_VC_INTERR_OFFSET             0xedfc
-#define GC_M3_DEMCR_VC_HARDERR_LSB               0xa
-#define GC_M3_DEMCR_VC_HARDERR_MASK              0x400
-#define GC_M3_DEMCR_VC_HARDERR_SIZE              0x1
-#define GC_M3_DEMCR_VC_HARDERR_DEFAULT           0x0
-#define GC_M3_DEMCR_VC_HARDERR_OFFSET            0xedfc
-#define GC_M3_DEMCR_MON_EN_LSB                   0x10
-#define GC_M3_DEMCR_MON_EN_MASK                  0x10000
-#define GC_M3_DEMCR_MON_EN_SIZE                  0x1
-#define GC_M3_DEMCR_MON_EN_DEFAULT               0x0
-#define GC_M3_DEMCR_MON_EN_OFFSET                0xedfc
-#define GC_M3_DEMCR_MON_PEND_LSB                 0x11
-#define GC_M3_DEMCR_MON_PEND_MASK                0x20000
-#define GC_M3_DEMCR_MON_PEND_SIZE                0x1
-#define GC_M3_DEMCR_MON_PEND_DEFAULT             0x0
-#define GC_M3_DEMCR_MON_PEND_OFFSET              0xedfc
-#define GC_M3_DEMCR_MON_STEP_LSB                 0x12
-#define GC_M3_DEMCR_MON_STEP_MASK                0x40000
-#define GC_M3_DEMCR_MON_STEP_SIZE                0x1
-#define GC_M3_DEMCR_MON_STEP_DEFAULT             0x0
-#define GC_M3_DEMCR_MON_STEP_OFFSET              0xedfc
-#define GC_M3_DEMCR_MON_REQ_LSB                  0x13
-#define GC_M3_DEMCR_MON_REQ_MASK                 0x80000
-#define GC_M3_DEMCR_MON_REQ_SIZE                 0x1
-#define GC_M3_DEMCR_MON_REQ_DEFAULT              0x0
-#define GC_M3_DEMCR_MON_REQ_OFFSET               0xedfc
-#define GC_M3_DEMCR_TRCENA_LSB                   0x18
-#define GC_M3_DEMCR_TRCENA_MASK                  0x1000000
-#define GC_M3_DEMCR_TRCENA_SIZE                  0x1
-#define GC_M3_DEMCR_TRCENA_DEFAULT               0x0
-#define GC_M3_DEMCR_TRCENA_OFFSET                0xedfc
-#define GC_CRYPTO_DMEM_DUMMY_SIZE                0x1000
-#define GC_CRYPTO_IMEM_DUMMY_SIZE                0x1000
-#define GC_SPI_DATA_SIZE                         0x100
-#define GC_SPS_DATA_SIZE                         0x800
-#define GC_SPS_ROM_CMD_SIZE                      0x200
-#define GC_USB_DFIFO_SIZE                        0x1000
-#ifdef GC__ENABLE_FLASH_DFT_DEFINITIONS__
-#define GC_FLASH_DFT_REGS_ADDR_WIDTH 4
-#define GC_FLASH_DFT_R_PIN_ADDR 0
-#define GC_FLASH_DFT_R_PIN_WIDTH 7
-#define GC_FLASH_DFT_R_XADR_ADDR 1
-#define GC_FLASH_DFT_R_XADR_WIDTH 10
-#define GC_FLASH_DFT_R_YADR_ADDR 2
-#define GC_FLASH_DFT_R_YADR_WIDTH 6
-#define GC_FLASH_DFT_R_DATA_ADDR 3
-#define GC_FLASH_DFT_R_DATA_WIDTH 32
-#define GC_FLASH_DFT_R_CTRL_ADDR 4
-#define GC_FLASH_DFT_R_CTRL_WIDTH 16
-#define GC_FLASH_DFT_R_GRPSEL_ADDR 5
-#define GC_FLASH_DFT_R_GRPSEL_WIDTH 1
-#define GC_FLASH_DFT_R_OPMODE_ADDR 6
-#define GC_FLASH_DFT_R_OPMODE_WIDTH 5
-#define GC_FLASH_DFT_R_IPSEL_ADDR 7
-#define GC_FLASH_DFT_R_IPSEL_WIDTH 4
-#define GC_FLASH_DFT_R_STATUS_ADDR 8
-#define GC_FLASH_DFT_R_STATUS_WIDTH 2
-#define GC_FLASH_DFT_R_BITSEL_ADDR 9
-#define GC_FLASH_DFT_R_BITSEL_WIDTH 6
-#define GC_FLASH_DFT_R_REPAIR_0_ADDR 10
-#define GC_FLASH_DFT_R_REPAIR_0_WIDTH 8
-#define GC_FLASH_DFT_R_REPAIR_1_ADDR 11
-#define GC_FLASH_DFT_R_REPAIR_1_WIDTH 8
-#define GC_FLASH_DFT_R_SMW_ADDR 12
-#define GC_FLASH_DFT_R_SMW_WIDTH 2
-#define GC_FLASH_DFT_WIDTH_BY_ADDR(addr) \
-  (addr == GC_FLASH_DFT_R_PIN_ADDR) ? 7 : \
-  (addr == GC_FLASH_DFT_R_XADR_ADDR) ? 10 : \
-  (addr == GC_FLASH_DFT_R_YADR_ADDR) ? 6 : \
-  (addr == GC_FLASH_DFT_R_DATA_ADDR) ? 32 : \
-  (addr == GC_FLASH_DFT_R_CTRL_ADDR) ? 16 : \
-  (addr == GC_FLASH_DFT_R_GRPSEL_ADDR) ? 1 : \
-  (addr == GC_FLASH_DFT_R_OPMODE_ADDR) ? 5 : \
-  (addr == GC_FLASH_DFT_R_IPSEL_ADDR) ? 4 : \
-  (addr == GC_FLASH_DFT_R_STATUS_ADDR) ? 2 : \
-  (addr == GC_FLASH_DFT_R_BITSEL_ADDR) ? 6 : \
-  (addr == GC_FLASH_DFT_R_REPAIR_0_ADDR) ? 8 : \
-  (addr == GC_FLASH_DFT_R_REPAIR_1_ADDR) ? 8 : \
-  (addr == GC_FLASH_DFT_R_SMW_ADDR) ? 2 : \
-  -1
-#endif /* GC__ENABLE_FLASH_DFT_DEFINITIONS__ */
-
-#define GC_CONST_FSH_PE_CONTROL_BULKERASE        0x1d1e2bad
-#define GC_CONST_FSH_PE_CONTROL_ERASE            0x31415927
-#define GC_CONST_FSH_PE_CONTROL_PROGRAM          0x27182818
-#define GC_CONST_FSH_PE_EN                       0xb11924e1
-#define GC_CONST_FSH_PE_CONTROL_READ             0x16021765
-#define GC_CONST_FSH_OVRD_UNLOCK                 0x13806488
-#endif /* __EC_CHIP_G_CR50_FPGA_REGDEFS_H */
diff --git a/chip/g/hwtimer.c b/chip/g/hwtimer.c
deleted file mode 100644
index 9fbe3f0920..0000000000
--- a/chip/g/hwtimer.c
+++ /dev/null
@@ -1,213 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "init_chip.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#define SOURCE(field) TIMER0_##field
-#define EVENT(field) TIMER1_##field
-
-/* The frequency of timerls is 8 * 32768 Hz. */
-#define TIMER_FREQ_HZ (8 * 32768)
-
-/*
- * GCD(SECOND, TIMER_FREQ_HZ) = 64. We'll need to use reduced terms to prevent
- * overflow of our intermediate uint32_t type in some calculations.
- */
-#define GCD 64
-#define TIMER_FREQ_GCD (TIMER_FREQ_HZ / GCD)
-#define TIME_GCD (SECOND / GCD)
-
-/*
- * Scale the maximum number of ticks so that it will only count up to the
- * equivalent of approximately 0xffffffff usecs. Note that we lose 3us on
- * timer wrap due to loss of precision during division.
- */
-#define TIMELS_MAX (usecs_to_ticks(0xffffffff))
-
-/*
- * The below calculation is lightweight and can be implemented using
- * umull + shift on 32-bit ARM.
- */
-static inline uint32_t ticks_to_usecs(uint32_t ticks)
-{
-	return (uint64_t)ticks * SECOND / TIMER_FREQ_HZ;
-}
-
-/*
- * The below calulation is more tricky, this is very inefficient and requires
- * 64-bit division:
- * return ((uint64_t)(usecs) * TIMER_FREQ_HZ / SECOND);
- * Instead use 32 bit vals, divide first, and add back the loss of precision.
- */
-static inline uint32_t usecs_to_ticks(uint32_t usecs)
-{
-	return (usecs / TIME_GCD * TIMER_FREQ_GCD) +
-	       ((usecs % TIME_GCD) * TIMER_FREQ_GCD / TIME_GCD);
-}
-
-uint32_t __hw_clock_event_get(void)
-{
-	/* At what time will the next event fire? */
-	return __hw_clock_source_read() +
-		ticks_to_usecs(GREG32(TIMELS, EVENT(VALUE)));
-}
-
-void __hw_clock_event_clear(void)
-{
-	/* one-shot, 32-bit, timer & interrupts disabled, 1:1 prescale */
-	GWRITE_FIELD(TIMELS, EVENT(CONTROL), ENABLE, 0);
-
-	/* Disable interrupts */
-	GWRITE(TIMELS, EVENT(IER), 0);
-
-	/* Clear any pending interrupts */
-	GWRITE(TIMELS, EVENT(WAKEUP_ACK), 1);
-	GWRITE(TIMELS, EVENT(IAR), 1);
-}
-
-void __hw_clock_event_set(uint32_t deadline)
-{
-	uint32_t event_time;
-
-	__hw_clock_event_clear();
-
-	/* How long from the current time to the deadline? */
-	event_time = (deadline - __hw_clock_source_read());
-
-	/* Convert event_time to ticks rounding up */
-	GREG32(TIMELS, EVENT(LOAD)) = usecs_to_ticks(event_time) + 1;
-
-	/* Enable the timer & interrupts */
-	GWRITE(TIMELS, EVENT(IER), 1);
-	GWRITE_FIELD(TIMELS, EVENT(CONTROL), ENABLE, 1);
-}
-
-/*
- * Handle event matches. It's priority matches the HW rollover irq to prevent
- * a race condition that could lead to a watchdog timeout if preempted after
- * the get_time() call in process_timers().
- */
-void __hw_clock_event_irq(void)
-{
-	__hw_clock_event_clear();
-	process_timers(0);
-}
-DECLARE_IRQ(GC_IRQNUM_TIMELS0_TIMINT1, __hw_clock_event_irq, 1);
-
-uint32_t __hw_clock_source_read(void)
-{
-	/*
-	 * Return the current time in usecs. Since the counter counts down,
-	 * we have to invert the value.
-	 */
-	return ticks_to_usecs(TIMELS_MAX - GREG32(TIMELS, SOURCE(VALUE)));
-}
-
-void __hw_clock_source_set(uint32_t ts)
-{
-	GREG32(TIMELS, SOURCE(LOAD)) = usecs_to_ticks(0xffffffff - ts);
-}
-
-/* This handles rollover in the HW timer */
-void __hw_clock_source_irq(void)
-{
-	/* Clear the interrupt */
-	GWRITE(TIMELS, SOURCE(WAKEUP_ACK), 1);
-	GWRITE(TIMELS, SOURCE(IAR), 1);
-
-	/* Reset the load value */
-	GREG32(TIMELS, SOURCE(LOAD)) = TIMELS_MAX;
-
-	process_timers(1);
-}
-DECLARE_IRQ(GC_IRQNUM_TIMELS0_TIMINT0, __hw_clock_source_irq, 1);
-
-int __hw_clock_source_init(uint32_t start_t)
-{
-
-	if (runlevel_is_high()) {
-		/* Verify the contents of CC_TRIM are valid */
-		ASSERT(GR_FUSE(RC_RTC_OSC256K_CC_EN) == 0x5);
-
-		/* Initialize RTC to 256kHz */
-		GWRITE_FIELD(RTC, CTRL, X_RTC_RC_CTRL,
-			GR_FUSE(RC_RTC_OSC256K_CC_TRIM));
-	}
-
-	/* Configure timer1 */
-	GREG32(TIMELS, EVENT(LOAD)) = TIMELS_MAX;
-	GREG32(TIMELS, EVENT(RELOADVAL)) = TIMELS_MAX;
-	GWRITE_FIELD(TIMELS, EVENT(CONTROL), WRAP, 1);
-	GWRITE_FIELD(TIMELS, EVENT(CONTROL), RELOAD, 0);
-	GWRITE_FIELD(TIMELS, EVENT(CONTROL), ENABLE, 0);
-
-	/* Configure timer0 */
-	GREG32(TIMELS, SOURCE(RELOADVAL)) = TIMELS_MAX;
-	GWRITE_FIELD(TIMELS, SOURCE(CONTROL), WRAP, 1);
-	GWRITE_FIELD(TIMELS, SOURCE(CONTROL), RELOAD, 1);
-
-	/* Event timer disabled */
-	__hw_clock_event_clear();
-
-	/* Clear any pending interrupts */
-	GWRITE(TIMELS, SOURCE(WAKEUP_ACK), 1);
-
-	/* Force the time to whatever we're told it is */
-	__hw_clock_source_set(start_t);
-
-	/* HW Timer enabled, periodic, interrupt enabled, 32-bit, wrapping */
-	GWRITE_FIELD(TIMELS, SOURCE(CONTROL), ENABLE, 1);
-
-	/* Enable source timer interrupts */
-	GWRITE(TIMELS, SOURCE(IER), 1);
-
-	/* Here we go... */
-	task_enable_irq(GC_IRQNUM_TIMELS0_TIMINT0);
-	task_enable_irq(GC_IRQNUM_TIMELS0_TIMINT1);
-
-	/* Return the Event timer IRQ number (NOT the HW timer IRQ) */
-	return GC_IRQNUM_TIMELS0_TIMINT1;
-}
-
-#ifdef CONFIG_HW_SPECIFIC_UDELAY
-/*
- * Custom chip/g udelay(), guaranteed to delay for at least us microseconds.
- *
- * Lost time during timer wrap is not taken into account since interrupt latency
- * and __hw_clock_source_irq() execution time likely exceeds the lost 3us.
- */
-void udelay(unsigned us)
-{
-	unsigned t0 = __hw_clock_source_read();
-
-	/*
-	 * The timer will tick either 3 us or 4 us, every ~3.8us in realtime.
-	 * To ensure we meet the minimum delay, we must wait out a full
-	 * longest-case timer tick (4 us), since a tick may have occurred
-	 * immediately after sampling t0.
-	 */
-	us += ticks_to_usecs(1) + 1;
-
-	/*
-	 * udelay() may be called with interrupts disabled, so we can't rely on
-	 * process_timers() updating the top 32 bits.  So handle wraparound
-	 * ourselves rather than calling get_time() and comparing with a
-	 * deadline.
-	 *
-	 * This may fail for delays close to 2^32 us (~4000 sec), because the
-	 * subtraction below can overflow.  That's acceptable, because the
-	 * watchdog timer would have tripped long before that anyway.
-	 */
-	while (__hw_clock_source_read() - t0 <= us)
-		;
-}
-#endif /* CONFIG_HW_SPECIFIC_UDELAY */
diff --git a/chip/g/i2cm.c b/chip/g/i2cm.c
deleted file mode 100644
index 4959cdbba0..0000000000
--- a/chip/g/i2cm.c
+++ /dev/null
@@ -1,471 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * This is a driver for the I2C Master controller (i2cm) of the g chip.
- *
- * The g chip i2cm module supports 3 modes of operation, disabled, bit-banging,
- * and instruction based. These modes are selected via the I2C_CTRL
- * register. Selecting disabled mode can be used as a soft reset where the i2cm
- * hw state machine is reset, but the register values remain unchanged. In
- * bit-banging mode the signals SDA/SCL are controlled by the lower two bits of
- * the INST register. I2C_INST[1:0] = SCL|SDA. In this mode the value of SDA is
- * read every clock cycle.
- *
- * The main operation mode is instruction mode. A 32 bit instruction register
- * (I2C_INST) is used to describe a sequence of operations. The I2C transaction
- * is initiated when this register is written. The I2C module contains a status
- * register which in real-time tracks the progress of the I2C sequence that was
- * configured in the INST register. If enabled, an interrupt is generated when
- * the transaction is completed. If not using interrupts then bit 24 (INTB) of
- * the status register can be polled for 0. INTB is the inverse of the i2cm
- * interrupt status.
- *
- * The i2cm module provides a 64 byte fifo (RWBYTES) for both write and read
- * transactions. In addition there is a 4 byte fifo (FWBYTES) that can be used
- * for writes, for the register write of portion of a read transaction. By
- * default the pointer to RWBYTES fifo resets back 0 following each
- * transaction.
- *
- * As mentioned, i2c transactions are configured via the I2C_INST register.
- * A 2 byte register write would create the following bitmap to define the
- * compound instruction for the transaction:
- *
- * I2C_INST_START = 1         -> send start bit
- * I2C_INST_FWDEVADDR = 1     -> first send the slave device address
- * I2C_INST_FWBYTESCOUNT = 3  -> 3 bytes in FWBYTES (register + 16 bit value)
- * I2C_INST_FINALSTOP = 1     -> send stop bit
- * I2C_INST_DEVADDRVAL = slave address
- *
- * I2C_FWBYTES[b7:b0]   = out[0]  -> register address
- * I2C_FWBYTES[b15:b8]  = out[1]  -> first byte of value
- * I2C_FWBYTES[b23:b16] = out[2]  -> 2nd byte of value
- *
- * A 2 byte register read would create the following bitmap to define the
- * compound instruction for the transaction:
- *
- * I2C_INST_START = 1         -> send start bit
- * I2C_INST_FWDEVADDR = 1     -> first send the slave device address
- * I2C_INST_FWBYTESCOUNT = 1  -> 1 byte in FWBYTES (register address)
- * I2C_INST_REPEATEDSTART = 1 -> send start bit following write
- * I2C_INST_RWDEVADDR = 1     -> send slave address in read mode
- * I2C_INST_RWDEVADDR_RWB = 1 -> read bytes following slave address
- * I2C_INST_FINALNA = 1       -> ACK read bytes, NACK last byte read
- * I2C_INST_FINALSTOP = 1     -> send stop bit
- * I2C_INST_DEVADDRVAL = slave address
- * I2C_FWBYTES[b7:b0] = out[0] -> register address byte
- *
- * Once transaction is complete:
- * in[0] = I2C_RW0[b7:b0]     -> copy first byte of read into destination
- * in[1] = I2C_RW0[b15:b8]    -> copy 2nd byte of read into destination
- *
- * Once the register I2C_INST is written with the instruction words constructed
- * as shown, the transaction on the bus will commence. When I2C_INST is written,
- * I2C_STATUS[b23:b0] is updated to reflect the transaction
- * details and I2C_STATUS[b24] is set to 1. The transaction is complete when
- * I2C_STATUS[b24] is 0. If interrupts are enabled, then an interrupt would be
- * generated at this same point. The values of I2C_STATUS[b23:b0] are updated as
- * the transaction progresses. Upon a completion of a successful transaction
- * I2C_STATUS will be 0. If there was an error, the error details are contained
- * in the upper bits of of I2C_STATUS, specifically [b31:b25].
- */
-
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "pmu.h"
-#include "registers.h"
-#include "system.h"
-#include "timer.h"
-
-#define CPRINTS(format, args...) cprints(CC_I2C, format, ## args)
-
-/*
- * Limits for polling I2C transaction. The time limit of 25 msec is a
- * conservative value for the worst case (68 byte transfer) at 100 kHz clock
- * speed.
- */
-#define I2CM_POLL_WAIT_US 25
-#define I2CM_MAX_POLL_ITERATIONS (25000 / I2CM_POLL_WAIT_US)
-
-/* Sizes for first write (FW) and read/write (RW) fifos */
-#define I2CM_FW_BYTES_MAX 4
-#define I2CM_RW_BYTES_MAX 64
-
-/* Macros to set bits/fields of the INST word for sequences*/
-#define INST_START GFIELD_MASK(I2C, INST, START)
-#define INST_STOP GFIELD_MASK(I2C, INST, FINALSTOP)
-#define INST_RPT_START GFIELD_MASK(I2C, INST, REPEATEDSTART)
-#define INST_FWDEVADDR GFIELD_MASK(I2C, INST, FWDEVADDR)
-#define INST_DEVADDRVAL(addr) (addr << GFIELD_LSB(I2C, INST, \
-						  DEVADDRVAL))
-#define INST_RWDEVADDR GFIELD_MASK(I2C, INST, RWDEVADDR)
-#define INST_RWDEVADDR_RWB GFIELD_MASK(I2C, INST, RWDEVADDR_RWB)
-#define INST_NA GFIELD_MASK(I2C, INST, FINALNA)
-#define INST_RWBYTES(size) (size << GFIELD_LSB(I2C, INST, \
-					       RWBYTESCOUNT))
-
-/* Mask for b31:INTB of STATUS register */
-#define I2CM_ERROR_MASK (~((1 << GFIELD_LSB(I2C, STATUS, INTB)) - 1))
-
-enum i2cm_control_mode {
-	i2c_mode_disabled = 0,
-	i2c_mode_bit_bang = 1,
-	i2c_mode_instruction = 2,
-	i2c_mode_reserved = 3,
-};
-
-#define I2C_NUM_PHASESTEPS 4
-struct i2c_xfer_mode {
-	uint8_t clk_div;
-	uint8_t phase_steps[I2C_NUM_PHASESTEPS];
-};
-
-/*
- * TODO (crosbug.com/p/58355): For 100 and 400 kHz speed, phasestep0 has been
- * adjusted longer that what should be required due to slow rise times on both
- * Reef and Gru boards. In addition, the suggested values from the H1 chip spec
- * were based off a 26 MHz clock. Have an ask to get suggested values for the
- * actual 24 MHz bus speed.
- */
-const struct i2c_xfer_mode i2c_timing[I2C_FREQ_COUNT] = {
-	/* 1000 kHz */
-	{
-		.clk_div = 1,
-		.phase_steps = {5, 5, 5, 11},
-	},
-	/* 400 kHz */
-	{
-		.clk_div = 1,
-		.phase_steps = {15, 12, 12, 21},
-	},
-	/* 100 kHz */
-	{
-		.clk_div = 10,
-		.phase_steps = {9, 6, 5, 4},
-	},
-};
-
-static void i2cm_config_xfer_mode(int port, enum i2c_freq freq)
-{
-	/* Set the control mode to disabled (soft reset) */
-	GWRITE_I(I2C, port, CTRL_MODE, i2c_mode_disabled);
-
-	/* Set the phasesteps register for the requested bus frequency */
-	GWRITE_FIELD_I(I2C, port, CTRL_PHASESTEPS, P0,
-		       i2c_timing[freq].phase_steps[0]);
-	GWRITE_FIELD_I(I2C, port, CTRL_PHASESTEPS, P1,
-		       i2c_timing[freq].phase_steps[1]);
-	GWRITE_FIELD_I(I2C, port, CTRL_PHASESTEPS, P2,
-		       i2c_timing[freq].phase_steps[2]);
-	GWRITE_FIELD_I(I2C, port, CTRL_PHASESTEPS, P3,
-		       i2c_timing[freq].phase_steps[3]);
-
-	/* Set the clock divide control register */
-	GWRITE_I(I2C, port, CTRL_CLKDIV, i2c_timing[freq].clk_div);
-	/* Ensure that INST register is reset */
-	GWRITE_I(I2C, port, INST, 0);
-	/* Set the control mode register to instruction */
-	GWRITE_I(I2C, port, CTRL_MODE, i2c_mode_instruction);
-}
-
-static void i2cm_write_rwbytes(int port, const uint8_t *out, int size)
-{
-	volatile uint32_t *rw_ptr;
-	int rw_count;
-	int i;
-
-	/* Calculate number of RW register writes required */
-	rw_count = (size + 3) >> 2;
-	/* Get pointer to RW0 register (start of fifo) */
-	rw_ptr = GREG32_ADDR_I(I2C, port, RW0);
-
-	/*
-	 * Get write data from source buffer one byte at a time and write up to
-	 * 4 bytes at a time in to the RW fifo.
-	 */
-	for (i = 0; i < rw_count; i++) {
-		int byte_count;
-		int j;
-		uint32_t rw_data = 0;
-
-		byte_count = MIN(4, size);
-		for (j = 0; j < byte_count; j++)
-			rw_data |= *out++ << (j * 8);
-		size -= byte_count;
-		*rw_ptr++ = rw_data;
-	}
-}
-
-static void i2cm_read_rwbytes(int port, uint8_t *in, int size)
-{
-	int rw_count;
-	int i;
-	volatile uint32_t *rw_ptr;
-
-	/* Calculate number of RW register writes required */
-	rw_count = (size + 3) >> 2;
-	/* Get pointer to RW0 register (start of fifo) */
-	rw_ptr = GREG32_ADDR_I(I2C, port, RW0);
-
-	/*
-	 * Read data from fifo up to 4 bytes at a time and copy into
-	 * destination buffer 1 byte at a time.
-	 */
-	for (i = 0; i < rw_count; i++) {
-		int byte_count;
-		int j;
-		uint32_t rw_data;
-
-		rw_data = *rw_ptr++;
-		byte_count = MIN(4, size);
-		for (j = 0; j < byte_count; j++) {
-			*in++ = rw_data;
-			rw_data >>= 8;
-		}
-		size -= byte_count;
-	}
-}
-
-static int i2cm_poll_for_complete(int port)
-{
-	int poll_count = 0;
-
-	while (poll_count < I2CM_MAX_POLL_ITERATIONS) {
-		/* Check if the sequence is complete */
-		if (!GREAD_FIELD_I(I2C, port, STATUS, INTB))
-			return EC_SUCCESS;
-		/* Not done yet, sleep */
-		usleep(I2CM_POLL_WAIT_US);
-		poll_count++;
-	};
-
-	return EC_ERROR_TIMEOUT;
-}
-
-static uint32_t i2cm_create_inst(int slave_addr_flags, int is_write,
-				 size_t size, uint32_t flags)
-{
-	uint32_t inst = 0;
-
-	if (flags & I2C_XFER_START) {
-		/*
-		 * Start sequence will have to be issued, slave address needs
-		 * to be included.
-		 */
-		inst |= INST_START;
-		inst |= INST_DEVADDRVAL(I2C_GET_ADDR(slave_addr_flags));
-		inst |= INST_RWDEVADDR;
-	}
-
-	if (!is_write)
-		inst |= INST_RWDEVADDR_RWB;
-
-	inst |= INST_RWBYTES(size);
-
-	if (flags & I2C_XFER_STOP) {
-		inst |= INST_STOP;
-		if (!is_write)
-			inst |= INST_NA;
-	}
-
-	return inst;
-}
-
-static int i2cm_execute_sequence(int port, int slave_addr_flags,
-				 const uint8_t *out, int out_size,
-				 uint8_t *in, int in_size,
-				 int flags)
-{
-	int rv;
-	uint32_t inst;
-	uint32_t status;
-	size_t size;
-	int is_write;
-	size_t done_so_far;
-	uint32_t seq_flags;
-
-	size = in_size ? in_size : out_size;
-	done_so_far = 0;
-	is_write = !!out_size;
-
-	while (done_so_far < size) {
-		size_t batch_size;
-
-		seq_flags = flags;
-
-		batch_size = MIN(size - done_so_far, I2CM_RW_BYTES_MAX);
-
-		if (done_so_far)
-			/* No need to generate start. */
-			seq_flags &= ~I2C_XFER_START;
-
-		if ((batch_size + done_so_far) != size)
-			/* No need to generate stop. */
-			seq_flags &= ~I2C_XFER_STOP;
-
-		/* Build sequence instruction */
-		inst = i2cm_create_inst(slave_addr_flags, is_write,
-					batch_size, seq_flags);
-
-		/* If this is a write - copy data into the FIFO. */
-		if (is_write)
-			i2cm_write_rwbytes(port, out + done_so_far, batch_size);
-
-		/* Start transaction */
-		GWRITE_I(I2C, port, INST, inst);
-
-		/* Wait for transaction to be complete */
-		rv = i2cm_poll_for_complete(port);
-		/* Handle timeout case */
-		if (rv)
-			return rv;
-
-		/* Check status value for errors */
-		status = GREAD_I(I2C, port, STATUS);
-		if (status & I2CM_ERROR_MASK) {
-			if (status & GFIELD_MASK(I2C, STATUS, FINALSTOP)) {
-				/*
-				 * A stop was requested but not generated,
-				 * let's make sure the bus is brought back to
-				 * the idle state.
-				 */
-				GWRITE_I(I2C, port, INST, INST_STOP);
-				i2cm_poll_for_complete(port);
-			}
-			/* Clear INST register after processing failure(s). */
-			GWRITE_I(I2C, port, INST, 0);
-			return EC_ERROR_UNKNOWN;
-		}
-
-		if (!is_write)
-			i2cm_read_rwbytes(port, in + done_so_far, batch_size);
-
-		done_so_far += batch_size;
-	}
-
-	return EC_SUCCESS;
-}
-
-
-/* Perform an i2c transaction. */
-int chip_i2c_xfer(const int port, const uint16_t slave_addr_flags,
-		  const uint8_t *out, int out_size,
-		  uint8_t *in, int in_size, int flags)
-{
-	int rv;
-
-	if (!in_size && !out_size)
-		/* Nothing to do */
-		return EC_SUCCESS;
-
-	if (in_size && out_size &&
-	    ((flags & I2C_XFER_SINGLE) != I2C_XFER_SINGLE)) {
-		/*
-		 * Not clear what to do: this is not a complete transaction,
-		 * but it has both receive and transmit parts.
-		 */
-		CPRINTS("%s: error: in %d, out %d, flags 0x%x",
-			__func__, in_size, out_size, flags);
-		return EC_ERROR_INVAL;
-	}
-
-	if (out_size) {
-		/* Process write before read. */
-		rv = i2cm_execute_sequence(port, slave_addr_flags, out,
-					   out_size, NULL, 0, flags);
-		if (rv != EC_SUCCESS)
-			return rv;
-	}
-
-	if (in_size)
-		rv = i2cm_execute_sequence(port, slave_addr_flags,
-					   NULL, 0, in, in_size, flags);
-
-	return rv;
-}
-
-int i2c_raw_get_scl(int port)
-{
-	enum gpio_signal pin;
-
-	if (get_scl_from_i2c_port(port, &pin) == EC_SUCCESS)
-		return gpio_get_level(pin);
-
-	/* If no SCL pin defined for this port, then return 1 to appear idle. */
-	return 1;
-}
-
-int i2c_raw_get_sda(int port)
-{
-	enum gpio_signal pin;
-
-	if (get_sda_from_i2c_port(port, &pin) == EC_SUCCESS)
-		return gpio_get_level(pin);
-
-	/* If no SDA pin defined for this port, then return 1 to appear idle. */
-	return 1;
-}
-
-int i2c_get_line_levels(int port)
-{
-	return (i2c_raw_get_sda(port) ? I2C_LINE_SDA_HIGH : 0) |
-		(i2c_raw_get_scl(port) ? I2C_LINE_SCL_HIGH : 0);
-
-}
-
-static void i2cm_init_port(const struct i2c_port_t *p)
-{
-	enum i2c_freq freq;
-
-	/* Enable clock for I2C Master */
-	pmu_clock_en(p->port ? PERIPH_I2C1 : PERIPH_I2C0);
-
-	/* Set operation speed. */
-	switch (p->kbps) {
-	case 1000: /* Fast-mode Plus */
-		freq = I2C_FREQ_1000KHZ;
-		break;
-	case 400: /* Fast-mode */
-		freq = I2C_FREQ_400KHZ;
-		break;
-	case 100: /* Standard-mode */
-		freq = I2C_FREQ_100KHZ;
-		break;
-	default: /* unknown speed, default to 100kBps */
-		CPRINTS("I2C bad speed %d kBps.  Defaulting to 100kbps.",
-			p->kbps);
-		freq = I2C_FREQ_100KHZ;
-	}
-
-	/* Configure the transfer clocks and mode */
-	i2cm_config_xfer_mode(p->port, freq);
-
-	CPRINTS("Initialized I2C port %d, freq = %d kHz", p->port, p->kbps);
-}
-
-/**
- * Initialize the i2c module for all supported ports.
- */
-void i2cm_init(void)
-{
-	const struct i2c_port_t *p = i2c_ports;
-	int i;
-
-	for (i = 0; i < i2c_ports_used; i++, p++)
-		i2cm_init_port(p);
-
-}
-
-void i2c_init(void)
-{
-	/*
-	 * Stub init function to be called at boot.
-	 * We only want this controller active in certain cases,
-	 * but we still need to let main.c call something.
-	 */
-}
diff --git a/chip/g/i2cs.c b/chip/g/i2cs.c
deleted file mode 100644
index 1992784c0b..0000000000
--- a/chip/g/i2cs.c
+++ /dev/null
@@ -1,469 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/*
- * This is a driver for the I2C Slave controller (i2cs) of the g chip.
- *
- * The controller is has two register files, 64 bytes each, one for storing
- * data received from the master, and one for storing data to be transmitted
- * to the master. Both files are accessed only as 4 byte quantities, so the
- * driver must provide adaptation to concatenate messages with sizes not
- * divisible by 4 and or not properly aligned.
- *
- * The file holding data written by the master has associated with it a
- * register showing where the controller accessed the file last, comparing it
- * with its previous value tells the driver how many bytes recently written by
- * the master are there.
- *
- * The file holding data to be read by the master has a register associated
- * with it showing where was the latest BIT the controller transmitted.
- *
- * The controller can generate interrupts on three different conditions:
- *  - beginning of a read cycle
- *  - end of a read cycle
- *  - end of a write cycle
- *
- * Since this driver's major role is to serve as a TPM interface, it is safe
- * to assume that the master will always write first, even when it needs to
- * read data from the device.
- *
- * Each write or read access will be started by the master writing the one
- * byte address of the TPM register to access.
- *
- * If the master needs to read this register, the originating write
- * transaction will be limited to a single byte payload, a read transaction
- * would follow immediately.
- *
- * If the master needs to write into this register, the data to be written
- * will be included in the same i2c transaction immediately following the one
- * byte register address.
- *
- * This protocol allows to keep the driver simple: the only interrupt the
- * driver enables is the 'end a write cycle'. The number of bytes received
- * from the master gives the callback function a hint as of what the master
- * intention is, to read or to write.
- *
- * In both cases the same callback function is called. On write accesses the
- * callback function converts the data as necessary and passes it to the TPM.
- * On read accesses the callback function retrieves data from the TPM and puts
- * it into the read register file to be available to the master to retrieve in
- * the following read access. In both cases the callback function completes
- * processing on the invoking interrupt context.
- *
- * The driver API consists of two functions, one to register the callback to
- * process interrupts, another one - to add a byte to the master read register
- * file. See the accompanying .h file for details.
- *
- * TODO:
- * - figure out flow control - clock stretching can be challenging with this
- *   controller.
- * - detect and recover from overflow/underflow situations
- */
-
-#include "common.h"
-#include "console.h"
-#include "flash_log.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "i2cs.h"
-#include "pmu.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-
-#define REGISTER_FILE_SIZE BIT(6) /* 64 bytes. */
-#define REGISTER_FILE_MASK (REGISTER_FILE_SIZE - 1)
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_I2C, outstr)
-#define CPRINTF(format, args...) cprints(CC_I2C, format, ## args)
-
-/* Pointer to the function to invoke on the write complete interrupts. */
-static wr_complete_handler_f write_complete_handler_;
-
-/* A buffer to normalize the received data to pass it to the user. */
-static uint8_t i2cs_buffer[REGISTER_FILE_SIZE];
-
-/*
- * Pointer where the CPU stopped retrieving the write data sent by the master
- * last time the write access was processed.
- */
-static uint16_t last_write_pointer;
-
-/*
- * Pointer where the CPU stopped writing data for the master to read last time
- * the read data was prepared.
- */
-static uint16_t last_read_pointer;
-
-/*
- * Keep track number of times the "hosed slave" condition was encountered.
- */
-static uint16_t i2cs_read_recovery_count;
-static uint16_t i2cs_sda_low_count;
-
-static void check_i2cs_state(void)
-{
-	if (gpio_get_level(GPIO_MONITOR_I2CS_SDA))
-		return;
-
-	/*
-	 * The bus might be stuck;
-	 * Generate a stop sequence to unwedge.
-	 */
-	board_unwedge_i2cs();
-}
-
-static void i2cs_init(void)
-{
-
-	/* First decide if i2c is even needed for this platform. */
-	/* if (i2cs is not needed) return; */
-	if (!board_tpm_uses_i2c())
-		return;
-
-	pmu_clock_en(PERIPH_I2CS);
-
-	memset(i2cs_buffer, 0, sizeof(i2cs_buffer));
-
-	i2cs_set_pinmux();
-
-	check_i2cs_state();
-
-	/* Reset read and write pointers. */
-	last_write_pointer = 0;
-	last_read_pointer = 0;
-	i2cs_sda_low_count = 0;
-	GWRITE(I2CS, READ_PTR, 0);
-	GWRITE(I2CS, WRITE_PTR, 0);
-
-	/* Just in case we were wedged and the master starts with a read. */
-	*GREG32_ADDR(I2CS, READ_BUFFER0) = ~0;
-
-	/* Enable I2CS interrupt */
-	GWRITE_FIELD(I2CS, INT_ENABLE, INTR_WRITE_COMPLETE, 1);
-
-	/* Slave address is hardcoded to 0x50. */
-	GWRITE(I2CS, SLAVE_DEVADDRVAL, 0x50);
-}
-
-/* Forward declaration of the hook function. */
-static void poll_read_state(void);
-DECLARE_DEFERRED(poll_read_state);
-
-/* Interval to poll SDA line when detecting the "hosed" condition. This value
- * must be larger then the maximum i2c transaction time. They are normally less
- * than 1 ms. The value multiplied by the threshold must also be larger than
- * the ap_is_on debounce time, which is 2 seconds.
- */
-#define READ_STATUS_CHECK_INTERVAL (700 * MSEC)
-
-/* Number of times SDA must be low between i2c writes before the i2cs controller
- * is restarted.
- *
- * Three was chosen because we can have two i2c transactions in between write
- * complete interrupts.
- *
- * Consider the following timeline:
- * 1) START <i2c_addr|W> <reg> STOP
- * 2) Write complete handler runs (i2cs_sda_low_count = 0)
- * 3) START <i2c_addr|R> <data>+ STOP (i2cs_sda_low_count++)
- * 4) START <i2c_addr|W> <reg> <data>+ STOP (i2cs_sda_low_count++)
- * 5) Write complete handler runs
- *
- * If the poller happened to run during time 3 and time 4 while SDA was low,
- * i2cs_sda_low_count would = 2. This is not considered an error case. If we
- * were to see a third low value before time 5, we can assume the bus is stuck,
- * or the master performed multiple reads between writes (which is not
- * expected).
- *
- * If we were to enable the read complete interrupt and use it to clear
- * i2cs_sda_low_count we could get away with a threshold of two. This would also
- * support multiple reads after a write.
- *
- * We could in theory use the FIFO read/write pointers to determine if the bus
- * is stuck. This was not chosen because we would need to take the following
- * into account:
- * 1) The poller could run at time 3 between the final ACK bit being asserted
- *    and the stop condition happening. This would not increment any pointers.
- * 2) The poller could run at time 4 between the start condition and the first
- *    data byte being ACKed. The write pointer can only address full bytes,
- *    unlike the read pointer.
- * These two edge cases would force us to poll at least three times.
- */
-#define READ_STATUS_CHECK_THRESHOLD 3
-
-/*
- * Restart the i2cs controller if the controller gets stuck transmitting a 0 on
- * SDA.
- *
- * This can happen anytime the i2cs controller has control of SDA and the master
- * happens to fail and stops clocking.
- *
- * For example when the i2cs controller is:
- * 1) Transmitting an ACK for the slave address byte.
- * 2) Transmitting an ACK for a write transaction.
- * 3) Transmitting byte data for a read transaction.
- *
- * The reason this is problematic is because the master can't recover the bus
- * by issuing a new transaction. A start condition is defined as the master
- * pulling SDA low while SCL is high. The master can only initiate the start
- * condition when the bus is free (i.e., SDA is high), otherwise the master
- * thinks that it lost arbitration.
- *
- * We don't have to deal with the scenario where the controller gets stuck
- * transmitting a 1 on SDA since the master can recover the bus by issuing a
- * normal transaction. The master will at minimum clock 9 times on any
- * transaction. This is enough for the slave to complete its current operation
- * and NACK.
- */
-static void poll_read_state(void)
-{
-	if (!ap_is_on() || gpio_get_level(GPIO_I2CS_SDA)) {
-		/*
-		 * When the AP is off, the SDA line might drop low since the
-		 * pull ups might not be powered.
-		 *
-		 * If the AP is on, the bus is either idle, the master has
-		 * stopped clocking while SDA is high, or we have polled in the
-		 * middle of a transaction where SDA happens to be high.
-		 */
-		i2cs_sda_low_count = 0;
-	} else {
-		/*
-		 * The master has stopped clocking while the slave is holding
-		 * SDA low, or we have polled in the middle of a transaction
-		 * where SDA happens to be low.
-		 */
-		i2cs_sda_low_count++;
-
-		/*
-		 * SDA line has been stuck low without any write transactions
-		 * occurring. We will assume the controller is stuck.
-		 * Reinitialize the i2c interface (which will also restart this
-		 * polling function).
-		 */
-		if (i2cs_sda_low_count == READ_STATUS_CHECK_THRESHOLD) {
-			i2cs_sda_low_count = 0;
-			i2cs_read_recovery_count++;
-			CPRINTF("I2CS bus is stuck");
-			/*
-			 * i2cs_register_write_complete_handler will call
-			 * hook_call_deferred.
-			 */
-			i2cs_register_write_complete_handler(
-				write_complete_handler_);
-
-#ifdef CONFIG_FLASH_LOG
-			flash_log_add_event(FE_TPM_I2C_ERROR, 0, NULL);
-#endif
-			return;
-		}
-	}
-
-	hook_call_deferred(&poll_read_state_data, READ_STATUS_CHECK_INTERVAL);
-}
-
-/* Process the 'end of a write cycle' interrupt. */
-void __attribute__((used)) _i2cs_write_complete_int(void)
-{
-	/* Reset the IRQ condition. */
-	GWRITE_FIELD(I2CS, INT_STATE, INTR_WRITE_COMPLETE, 1);
-
-	/* We're receiving some bytes, so don't sleep */
-	disable_sleep(SLEEP_MASK_I2C_SLAVE);
-
-	if (write_complete_handler_) {
-		uint16_t bytes_written;
-		uint16_t bytes_processed;
-		uint32_t word_in_value = 0;
-
-		/* How many bytes has the master just written. */
-		bytes_written = ((uint16_t)GREAD(I2CS, WRITE_PTR) -
-				 last_write_pointer) & REGISTER_FILE_MASK;
-
-		/* How many have been processed yet. */
-		bytes_processed = 0;
-
-		/* Make sure we start with something. */
-		if (last_write_pointer & 3)
-			word_in_value = *(GREG32_ADDR(I2CS, WRITE_BUFFER0) +
-					  (last_write_pointer >> 2));
-		while (bytes_written != bytes_processed) {
-			/*
-			 * This loop iterates over bytes retrieved from the
-			 * master write register file in 4 byte quantities.
-			 * Each time the ever incrementing last_write_pointer
-			 * is aligned at 4 bytes, a new value needs to be
-			 * retrieved from the next register, indexed by
-			 * last_write_pointer/4.
-			 */
-
-			if (!(last_write_pointer & 3))
-				/* Time to get a new value. */
-				word_in_value = *(GREG32_ADDR(
-					I2CS, WRITE_BUFFER0) +
-						  (last_write_pointer >> 2));
-
-			/* Save the next byte in the adaptation buffer. */
-			i2cs_buffer[bytes_processed] =
-				word_in_value >> (8 * (last_write_pointer & 3));
-
-			/* The pointer wraps at the register file size. */
-			last_write_pointer = (last_write_pointer + 1) &
-				REGISTER_FILE_MASK;
-			bytes_processed++;
-		}
-
-		/* Invoke the callback to process the message. */
-		write_complete_handler_(i2cs_buffer, bytes_processed);
-	}
-
-	/* The transaction is complete so the slave has released SDA. */
-	i2cs_sda_low_count = 0;
-
-	/*
-	 * Could be the end of a TPM trasaction. Set sleep to be reenabled in 1
-	 * second. If this is not the end of a TPM response, then sleep will be
-	 * disabled again in the next I2CS interrupt.
-	 */
-	delay_sleep_by(1 * SECOND);
-	enable_sleep(SLEEP_MASK_I2C_SLAVE);
-}
-DECLARE_IRQ(GC_IRQNUM_I2CS0_INTR_WRITE_COMPLETE_INT,
-	    _i2cs_write_complete_int, 1);
-
-void i2cs_post_read_data(uint8_t byte_to_read)
-{
-	volatile uint32_t *value_addr;
-	uint32_t word_out_value;
-	uint32_t shift;
-
-	/*
-	 * Find out which register of the register file the byte needs to go
-	 * to.
-	 */
-	value_addr = GREG32_ADDR(I2CS, READ_BUFFER0) + (last_read_pointer >> 2);
-
-	/* Read-modify-write the register adding the new byte there. */
-	word_out_value = *value_addr;
-	shift = (last_read_pointer & 3) * 8;
-	word_out_value = (word_out_value & ~(0xff << shift)) |
-		(((uint32_t)byte_to_read) << shift);
-	*value_addr = word_out_value;
-	last_read_pointer = (last_read_pointer + 1) & REGISTER_FILE_MASK;
-}
-
-void i2cs_post_read_fill_fifo(uint8_t *buffer, size_t len)
-{
-	volatile uint32_t *value_addr;
-	uint32_t word_out_value;
-	uint32_t addr_offset;
-	uint32_t remainder_bytes;
-	uint32_t start_offset;
-	uint32_t num_words;
-	int i, j;
-
-	/* Get offset into 1st fifo word*/
-	start_offset = last_read_pointer & 0x3;
-	/* Number of bytes to fill out 1st word */
-	remainder_bytes = (4 - start_offset) & 0x3;
-	/* Get pointer to base of fifo and offset */
-	addr_offset = last_read_pointer >> 2;
-	value_addr = GREG32_ADDR(I2CS, READ_BUFFER0);
-	/* Update read_pointer to reflect final value */
-	last_read_pointer = (last_read_pointer + len) &
-		REGISTER_FILE_MASK;
-
-	/* Insert bytes until fifo is word aligned */
-	if (remainder_bytes) {
-		/* mask the bytes to be kept */
-		word_out_value = value_addr[addr_offset];
-		word_out_value &= (1 << (8 * start_offset)) - 1;
-		/* Write in remainder bytes */
-		for (i = 0; i < remainder_bytes; i++)
-			word_out_value |= *buffer++ << (8 * (start_offset + i));
-		/* Write to fifo register */
-		value_addr[addr_offset] = word_out_value;
-		addr_offset = (addr_offset + 1) & (REGISTER_FILE_MASK >> 2);
-		/* Account for bytes consumed */
-		len -= remainder_bytes;
-	}
-
-	/* HW fifo is now word aligned */
-	num_words = len >> 2;
-	for (i = 0; i < num_words; i++) {
-		word_out_value = 0;
-		for (j = 0; j < 4; j++)
-			word_out_value |= *buffer++ << (j * 8);
-		/* Write word to fifo and update fifo offset */
-		value_addr[addr_offset] = word_out_value;
-		addr_offset = (addr_offset + 1) & (REGISTER_FILE_MASK >> 2);
-	}
-	len -= (num_words << 2);
-
-	/* Now process remaining bytes (if any), will be <= 3 at this point */
-	remainder_bytes = len;
-	if (remainder_bytes) {
-		/* read from HW fifo */
-		word_out_value = value_addr[addr_offset];
-		/* Mask bytes that need to be kept */
-		word_out_value &= (0xffffffff << (8 * remainder_bytes));
-		for (i = 0; i < remainder_bytes; i++)
-			word_out_value |= *buffer++ << (8 * i);
-		value_addr[addr_offset] = word_out_value;
-	}
-}
-
-int i2cs_register_write_complete_handler(wr_complete_handler_f wc_handler)
-{
-	task_disable_irq(GC_IRQNUM_I2CS0_INTR_WRITE_COMPLETE_INT);
-
-	if (!wc_handler)
-		return 0;
-
-	i2cs_init();
-	write_complete_handler_ = wc_handler;
-	task_enable_irq(GC_IRQNUM_I2CS0_INTR_WRITE_COMPLETE_INT);
-
-	/*
-	 * Start a self perpetuating polling function to check for 'hosed'
-	 * condition periodically.
-	 */
-	hook_call_deferred(&poll_read_state_data, READ_STATUS_CHECK_INTERVAL);
-
-	return 0;
-}
-
-size_t i2cs_zero_read_fifo_buffer_depth(void)
-{
-	uint32_t hw_read_pointer;
-	size_t depth;
-
-	/*
-	 * Get the current value of the HW I2CS read pointer. Note that the read
-	 * pointer is b8:b3 of the I2CS_READ_PTR register. The lower 3 bits of
-	 * this register are used to support bit accesses by a host.
-	 */
-	hw_read_pointer = GREAD(I2CS, READ_PTR) >> 3;
-	/* Determine the number of bytes buffered in the HW fifo */
-	depth = (last_read_pointer - hw_read_pointer) & REGISTER_FILE_MASK;
-	/*
-	 * If queue depth is not zero, force it to 0 by adjusting
-	 * last_read_pointer to where the hw read pointer is.
-	 */
-	if (depth)
-		last_read_pointer = (uint16_t)hw_read_pointer;
-	/*
-	 * Return number of bytes queued when this funciton is called so it can
-	 * be tracked or logged by caller if desired.
-	 */
-	return depth;
-}
-
-void i2cs_get_status(struct i2cs_status *status)
-{
-	status->read_recovery_count = i2cs_read_recovery_count;
-}
diff --git a/chip/g/i2cs.h b/chip/g/i2cs.h
deleted file mode 100644
index 8fbc28187f..0000000000
--- a/chip/g/i2cs.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#ifndef __CHIP_G_I2CS_H
-#define __CHIP_G_I2CS_H
-
-#include <stddef.h>
-
-/*
- * Write complete interrupt callback function prototype. This function expects
- * two parameters: the address of the buffer containing received data and
- * number of bytes in the buffer.
- */
-typedef void (*wr_complete_handler_f)(void *i2cs_data, size_t i2cs_data_size);
-
-/* Register the write complete interrupt handler. */
-int i2cs_register_write_complete_handler(wr_complete_handler_f wc_handler);
-
-/*
- * Post a byte for the master to read. Blend the byte into the appropriate
- * 4byte register of the master read register file.
- */
-void i2cs_post_read_data(uint8_t byte_to_read);
-
-/*
- * Configure the pinmux registers required to connect the I2CS interface. This
- * function is board specific and so it exists in the associated board.c file.
- */
-void i2cs_set_pinmux(void);
-
-/*
- * Ensure no bytes are currently buffered in the I2CS READ fifo. This
- * value is calculated by finding the difference between read pointer that's
- * used by FW to add bytes to the HW fifo and the current value of the
- * I2CS_READ_PTR register.
- *
- * @returns: the number of bytes buffered when the function is called
- */
-size_t i2cs_zero_read_fifo_buffer_depth(void);
-
-/*
- * Write buffer of data into the I2CS HW read fifo. The function will operate a
- * byte at a time until the fifo write pointer is word aligned. Then it will
- * consume all remaining words of input data. There is another stage to handle
- * any excess bytes. The efficiency benefits relative the byte at a time
- * function diminish as the buffer size gets smaller and therefore not intended
- * to be used for <= 4 byte buffers.
- */
-void i2cs_post_read_fill_fifo(uint8_t *buffer, size_t len);
-
-/*
- * Provide upper layers with information with the I2CS interface
- * status/statistics. The only piece of information currently provided is the
- * counter of "hosed" i2c interface occurences, where i2c clocking stopped
- * while slave was transmitting a zero.
- */
-struct i2cs_status {
-	uint16_t read_recovery_count;
-};
-void i2cs_get_status(struct i2cs_status *status);
-
-#endif /* ! __CHIP_G_I2CS_H */
diff --git a/chip/g/idle.c b/chip/g/idle.c
deleted file mode 100644
index ae7760ced6..0000000000
--- a/chip/g/idle.c
+++ /dev/null
@@ -1,269 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "case_closed_debug.h"
-#include "clock.h"
-#include "common.h"
-#include "console.h"
-#include "hooks.h"
-#include "hwtimer.h"
-#include "init_chip.h"
-#include "rdd.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "usb_api.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
-
-/* What to do when we're just waiting */
-static enum {
-	DONT_KNOW,
-	IDLE_WFI,
-	IDLE_SLEEP,
-	IDLE_DEEP_SLEEP,
-	NUM_CHOICES
-} idle_action;
-
-#define EVENT_MIN 500
-
-static int idle_default;
-
-static const char *const idle_name[] = {
-	"invalid",
-	"wfi",
-	"sleep",
-	"deep sleep",
-};
-BUILD_ASSERT(ARRAY_SIZE(idle_name) == NUM_CHOICES);
-
-static int command_idle(int argc, char **argv)
-{
-	int i;
-
-	if (argc > 1) {
-		if (!strncasecmp("c", argv[1], 1)) {
-			GREG32(PMU, PWRDN_SCRATCH17) = 0;
-		} else if (console_is_restricted()) {
-			ccprintf("Console is locked, cannot set idle state\n");
-			return EC_ERROR_INVAL;
-		} else {
-			for (i = 1; i < ARRAY_SIZE(idle_name); i++)
-				if (!strncasecmp(idle_name[i], argv[1], 1)) {
-					idle_action = i;
-					break;
-				}
-		}
-	}
-
-	ccprintf("idle action: %s\n", idle_name[idle_action]);
-	ccprintf("deep sleep count: %u\n", GREG32(PMU, PWRDN_SCRATCH17));
-
-	return EC_SUCCESS;
-}
-DECLARE_SAFE_CONSOLE_COMMAND(idle, command_idle,
-			     "[w|s|d|c]",
-			     "Set idle action: wfi, sleep, deep sleep or "
-			     "Clear the deep sleep count");
-
-static int utmi_wakeup_is_enabled(void)
-{
-#ifdef CONFIG_RDD
-	/*
-	 * USB is only used for CCD, so only enable UTMI wakeups when RDD
-	 * detects that a debug accessory is attached.
-	 */
-	return ccd_ext_is_enabled();
-#else
-	/* USB is used for the host interface, so always enable UTMI wakeups */
-	return 1;
-#endif
-}
-
-static void prepare_to_sleep(void)
-{
-	/* No task switching! */
-	interrupt_disable();
-
-	/* Enable all possible internal wake sources */
-	GR_PMU_EXITPD_MASK =
-		GC_PMU_EXITPD_MASK_PIN_PD_EXIT_MASK |
-		GC_PMU_EXITPD_MASK_RDD0_PD_EXIT_TIMER_MASK |
-		GC_PMU_EXITPD_MASK_RBOX_WAKEUP_MASK |
-		GC_PMU_EXITPD_MASK_TIMELS0_PD_EXIT_TIMER0_MASK |
-		GC_PMU_EXITPD_MASK_TIMELS0_PD_EXIT_TIMER1_MASK;
-
-#ifdef CONFIG_RBOX_WAKEUP
-	/*
-	 * Enable RBOX wakeup. It will immediately be disabled on resume in
-	 * rbox_init or pmu_wakeup_interrupt.
-	 */
-	GREG32(RBOX, WAKEUP) = GC_RBOX_WAKEUP_ENABLE_MASK;
-#endif
-
-	if (utmi_wakeup_is_enabled() && idle_action != IDLE_DEEP_SLEEP)
-		GR_PMU_EXITPD_MASK |=
-			GC_PMU_EXITPD_MASK_UTMI_SUSPEND_N_MASK;
-
-	/* Which rails should we turn off? */
-	GR_PMU_LOW_POWER_DIS =
-		GC_PMU_LOW_POWER_DIS_VDDIOF_MASK |
-		GC_PMU_LOW_POWER_DIS_VDDXO_MASK |
-		GC_PMU_LOW_POWER_DIS_JTR_RC_MASK;
-
-	/*
-	 * Deep sleep should only be enabled when the AP is off otherwise the
-	 * TPM state will lost.
-	 */
-	if (idle_action == IDLE_DEEP_SLEEP) {
-		/* Clear upcoming events. They don't matter in deep sleep */
-		__hw_clock_event_clear();
-
-		/* Configure pins for deep sleep */
-		board_configure_deep_sleep_wakepins();
-
-		/* Make sure the usb clock is enabled */
-		clock_enable_module(MODULE_USB, 1);
-		/* Preserve some state from USB hardware prior to deep sleep. */
-		if (!GREAD_FIELD(USB, PCGCCTL, RSTPDWNMODULE))
-			usb_save_suspended_state();
-
-		/* Increment the deep sleep count */
-		GREG32(PMU, PWRDN_SCRATCH17) =
-			GREG32(PMU, PWRDN_SCRATCH17) + 1;
-
-#ifndef CONFIG_NO_PINHOLD
-		/* Latch the pinmux values */
-		GREG32(PINMUX, HOLD) = 1;
-#endif
-
-		/* Clamp the USB pins and shut the PHY down. We have to do this
-		 * in three separate steps, or Bad Things happen. */
-		GWRITE_FIELD(USB, PCGCCTL, PWRCLMP, 1);
-		GWRITE_FIELD(USB, PCGCCTL, RSTPDWNMODULE, 1);
-		GWRITE_FIELD(USB, PCGCCTL, STOPPCLK, 1);
-
-		/* Shut down one more power rail for deep sleep */
-		GR_PMU_LOW_POWER_DIS |=
-			GC_PMU_LOW_POWER_DIS_VDDL_MASK;
-	}
-
-	/* The next "wfi" will trigger it */
-	GR_PMU_LOW_POWER_DIS |= GC_PMU_LOW_POWER_DIS_START_MASK;
-}
-
-/* This is for normal sleep only. Deep sleep resumes with a warm boot. */
-static void resume_from_sleep(void)
-{
-	/* Prevent accidental reentry */
-	GR_PMU_LOW_POWER_DIS = 0;
-
-	/* Allow task switching again */
-	interrupt_enable();
-}
-
-
-/* The time in the future at which sleeping will be allowed. */
-static timestamp_t next_sleep_time;
-
-/* Update the future sleep time. */
-void delay_sleep_by(uint32_t us)
-{
-	timestamp_t tmp = get_time();
-
-	tmp.val += us;
-	if (tmp.val > next_sleep_time.val)
-		next_sleep_time = tmp;
-}
-
-/* Wait a good long time after any console input, in case there's more. */
-void clock_refresh_console_in_use(void)
-{
-	delay_sleep_by(10 * SECOND);
-}
-
-void disable_deep_sleep(void)
-{
-	idle_action = idle_default;
-}
-
-void enable_deep_sleep(void)
-{
-	idle_action = IDLE_DEEP_SLEEP;
-}
-
-static void idle_init(void)
-{
-	/*
-	 * If bus obfuscation is enabled disable sleep.
-	 */
-	if ((GR_FUSE(OBFUSCATION_EN) == 5) ||
-	    (GR_FUSE(FW_DEFINED_BROM_APPLYSEC) & BIT(3)) ||
-	    (runlevel_is_high() && GREAD(GLOBALSEC, OBFS_SW_EN))) {
-		CPRINTS("bus obfuscation enabled disabling sleep");
-		idle_default = IDLE_WFI;
-	} else {
-		idle_default = IDLE_SLEEP;
-	}
-}
-DECLARE_HOOK(HOOK_INIT, idle_init, HOOK_PRIO_DEFAULT - 1);
-
-/* Custom idle task, executed when no tasks are ready to be scheduled. */
-void __idle(void)
-{
-	int sleep_ok, sleep_delay_passed, next_evt_us;
-
-	/*
-	 * On init or resume from deep sleep set the idle action to default. If
-	 * it should be something else it will be determined during runtime.
-	 *
-	 * Before changing idle_action check that it is not already set. It is
-	 * possible that HOOK_CHIPSET_RESUME or SHUTDOWN were triggered before
-	 * this and set the idle_action.
-	 */
-	if (!idle_action)
-		idle_action = idle_default;
-
-	/* Disable sleep for 20 seconds after init */
-	delay_sleep_by(20 * SECOND);
-
-	while (1) {
-
-		/* Anyone still busy?  (this checks sleep_mask) */
-		sleep_ok = DEEP_SLEEP_ALLOWED;
-
-		/* Wait a bit, just in case */
-		sleep_delay_passed = timestamp_expired(next_sleep_time, 0);
-
-		/* Don't enable sleep if there is about to be an event */
-		next_evt_us = __hw_clock_event_get() - __hw_clock_source_read();
-
-		/* If it hasn't yet been long enough, check again when it is */
-		if (!sleep_delay_passed)
-			timer_arm(next_sleep_time, TASK_ID_IDLE);
-
-		/* We're allowed to sleep now, so set it up. */
-		if (sleep_ok && sleep_delay_passed && next_evt_us > EVENT_MIN)
-			if (idle_action != IDLE_WFI)
-				prepare_to_sleep();
-
-		/* Wait for the next irq event. This stops the CPU clock and
-		 * may trigger sleep or deep sleep if enabled. */
-		asm("wfi");
-
-		/*
-		 * Note: After resuming from normal sleep we should clear
-		 * PMU_LOW_POWER_DIS to prevent sleeping again by accident.
-		 * Normal sleep eventually resumes here after the waking
-		 * interrupt has been handled, but since all the other tasks
-		 * will get a chance to run first it might be some time before
-		 * that happens. If we find ourselves going back into sleep
-		 * unexpectedly, that might be why.
-		 */
-		resume_from_sleep();
-	}
-}
diff --git a/chip/g/init_chip.h b/chip/g/init_chip.h
deleted file mode 100644
index 506dfeab21..0000000000
--- a/chip/g/init_chip.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_INIT_CHIP_H
-#define __CROS_EC_INIT_CHIP_H
-
-/**
- * This is the current state of the PMU persistent registers. There are two
- * types: long life and pwrdn scratch. Long life will persist through any
- * reset other than POR. PWRDN scratch only survives deep sleep.
- *
- * LONG_LIFE_SCRATCH 0 - 2
- *	SCRATCH0 - Rollback counter
- *	SCRATCH1 - Board properties
- *	SCRATCH2
- *
- * PWRDN_SCRATCH  0 - 15 - Locked
- *
- * PWRDN_SCRATCH 16 - 27 - Can be used by RW
- *	SCRATCH16 - Indicator that firmware is running for debug purposes
- *	SCRATCH17 - deep sleep count
- *	SCRATCH18 - Preserving USB_DCFG through deep sleep
- *	SCRATCH19 - Preserving USB data sequencing PID through deep sleep
- *
- * PWRDN_SCRATCH 28 - 31 - Reserved for boot rom
- */
-
-
-enum permission_level {
-	PERMISSION_LOW = 0x00,
-	PERMISSION_MEDIUM = 0x33,    /* APPS run at medium */
-	PERMISSION_HIGH = 0x3C,
-	PERMISSION_HIGHEST = 0x55
-};
-
-int runlevel_is_high(void);
-void init_runlevel(const enum permission_level desired_level);
-
-void init_jittery_clock(int highsec);
-void init_jittery_clock_locking_optional(int highsec,
-					 int enable, int lock_required);
-void init_sof_clock(void);
-
-#endif	/* __CROS_EC_INIT_CHIP_H */
diff --git a/chip/g/ite_flash.c b/chip/g/ite_flash.c
deleted file mode 100644
index b4e1699a08..0000000000
--- a/chip/g/ite_flash.c
+++ /dev/null
@@ -1,127 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "ccd_config.h"
-#include "config.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "hooks.h"
-#include "i2c.h"
-#include "init_chip.h"
-#include "ite_sync.h"
-#include "registers.h"
-#include "scratch_reg1.h"
-#include "system.h"
-#include "timer.h"
-#include "usb_i2c.h"
-
-#define ITE_SYNC_TIME  (50 * MSEC)
-#define ITE_PERIOD_TIME 5  /* This is 200 kHz */
-#define TIMEUS_CLK_FREQ 24 /* units: MHz */
-#define HALF_PERIOD_TICKS 8
-
-/* Register controlling CPU clock mode among other things. */
-#define PROC_CONTROL_REGISTER 0x4009A6D0
-
-void generate_ite_sync(void)
-{
-	uint16_t *gpio_addr;
-	uint32_t cycle_count;
-	uint16_t both_zero;
-	uint16_t both_one;
-	uint16_t one_zero;
-	uint16_t zero_one;
-	uint32_t saved_setting;
-
-	/* Let's pulse EC reset while preparing to sync up. */
-	assert_ec_rst();
-	msleep(1);
-	deassert_ec_rst();
-	msleep(5);
-
-	/*
-	 * Values to write to set SCL and SDA to various combinations of 0 and
-	 * 1 to be able to generate two necessary waveforms.
-	 */
-	both_zero = 0;
-	one_zero = BIT(13);
-	zero_one = BIT(12);
-	both_one = one_zero | zero_one;
-
-	/* Address of the mask byte register to use to set both pins. */
-	gpio_addr = (uint16_t *) (GC_GPIO0_BASE_ADDR +
-				  GC_GPIO_MASKHIGHBYTE_800_OFFSET +
-				  (both_one >> 8) * 4);
-
-	/*
-	 * Let's take over the i2c master pins. Connect pads DIOB0(aka i2c
-	 * scl) to gpio0.12 and DIOB1(aka sda) to gpio0.13. I2c master
-	 * controller is disconnected from the pads.
-	 */
-	REG32(GBASE(PINMUX) + GOFFSET(PINMUX, DIOB0_SEL)) =
-		GC_PINMUX_GPIO0_GPIO12_SEL;
-	REG32(GBASE(PINMUX) + GOFFSET(PINMUX, DIOB1_SEL)) =
-		GC_PINMUX_GPIO0_GPIO13_SEL;
-
-	gpio_set_flags(GPIO_I2C_SCL_INA, GPIO_OUTPUT | GPIO_HIGH);
-	gpio_set_flags(GPIO_I2C_SDA_INA, GPIO_OUTPUT | GPIO_HIGH);
-
-	cycle_count = 2 * ITE_SYNC_TIME / ITE_PERIOD_TIME;
-
-	interrupt_disable();
-
-	init_jittery_clock_locking_optional(1, 0, 0);
-
-	saved_setting = REG32(0x4009A6D0);
-	REG32(0x4009A6D0) = 0;
-
-	/* Call assembler function to generate ITE SYNC sequence. */
-	ite_sync(gpio_addr, both_zero, one_zero, zero_one, both_one,
-		 HALF_PERIOD_TICKS, HALF_PERIOD_TICKS * cycle_count);
-
-	REG32(0x4009A6D0) = saved_setting;
-
-	interrupt_enable();
-
-	/*
-	 * Restore I2C configuration, re-attach i2c master controller to the
-	 * pads.
-	 */
-	REG32(GBASE(PINMUX) + GOFFSET(PINMUX, DIOB0_SEL)) =
-		GC_PINMUX_I2C0_SCL_SEL;
-	REG32(GBASE(PINMUX) + GOFFSET(PINMUX, DIOB1_SEL)) =
-		GC_PINMUX_I2C0_SDA_SEL;
-}
-
-/*
- * Callback invoked by usb_i2c bridge when a write to a special I2C address is
- * requested.
- */
-#define CROS_CMD_ITE_SYNC    0
-static int ite_sync_preparer(void *data_in, size_t in_size,
-			     void *data_out, size_t out_size)
-{
-
-	if (in_size != 1)
-		return USB_I2C_WRITE_COUNT_INVALID;
-
-	if (*((uint8_t *)data_in) != CROS_CMD_ITE_SYNC)
-		return USB_I2C_UNSUPPORTED_COMMAND;
-
-	if (!ccd_is_cap_enabled(CCD_CAP_EC_FLASH))
-		return USB_I2C_DISABLED;
-
-	board_start_ite_sync();
-
-	return 0;
-}
-
-static void register_ite_sync(void)
-{
-	usb_i2c_register_cros_cmd_handler(ite_sync_preparer);
-}
-
-DECLARE_HOOK(HOOK_INIT, register_ite_sync, HOOK_PRIO_DEFAULT);
diff --git a/chip/g/ite_sync.S b/chip/g/ite_sync.S
deleted file mode 100644
index 0c3d303dd2..0000000000
--- a/chip/g/ite_sync.S
+++ /dev/null
@@ -1,122 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-.text
-
-.syntax unified
-.code 16
-
-.global ite_sync
-.thumb_func
-
-/*
- * The logic shown by the following C code is implemented in assembly below.
- *
- * Two square wave sequences are generated, one oscillating twice as fast as
- * the other. The ite_sync_clock() function implements tick counter. The higher
- * frequency sequence's half period time takes 'half_period_ticks' cycles of
- * the ite_sync_clock() inner loop. So, to generate two sequences, one half
- * the frequency of the other four half cycles are required.
- *
- * Two GPIOs used as who outputs of the two clocks. Luckily both GPIOs can be
- * controlled by the same SOC register, the input values of 'both_zero',
- * 'one_zero', 'zero_one', and 'both_one' are the values to be written
- * into the register to set the two GPIOs to the respecitve values.
- *
-
-static uint32_t tick;               # Free running tick counter, runs from
-	                            # 0 to 'total_ticks_required'
-static uint32_t next_tick;          # Deadline for the next half period
-static uint32_t half_period_ticks;  # Number of ticks per half period.
-
-static void ite_sync_clock(void)
-{
-	while (tick++ < next_tick)
-		;
-	next_tick += half_period_ticks ;
-}
-
-void ite_sync(volatile uint16_t *gpio_addr, uint16_t both_zero,
-	uint16_t one_zero, uint16_t zero_one, uint16_t both_one,
-	uint32_t half_period, uint32_t total_ticks_required)
-{
-	uint32_t tick = 0;
-	uint32_t next_tick = half_period_ticks = half_period;
-
-	while (tick < total_ticks_required) {
-		ite_sync_clock() ;
-		*gpio_addr = both_zero;
-
-		ite_sync_clock() ;
-		*gpio_addr = one_zero;
-
-		ite_sync_clock() ;
-		*gpio_addr = zero_one;
-
-		ite_sync_clock() ;
-		*gpio_addr = both_one;
-	}
-}
-*/
-
-.thumb_func
-ite_sync_clock:
-	@ ip tick
-	@ r7 next_tick
-	@ r5 half_period_ticks
-	add  ip, ip, #1
-	cmp  ip, r7
-	bcc  ite_sync_clock
-	add  r7, r7, r5
-	mov  r8, r8        @ a few NOOPs to fine tune the period.
-	mov  r8, r8
-	bx   lr
-
-.thumb_func
-.global ite_sync
-ite_sync:
-	@ vvvvvv passed in registers: vvvvv
-	@ r0 gpio_addr
-	@ r1 both_zero
-	@ r2 one_zero
-	@ r3 zero_one
-	@ vvvvvv passed on the stack, moved to registers: vvvvv
-	@ r4 both_one
-	@ r5 half_period
-	@ r6 total_ticks_required
-	@ vvvvvv local variables: vvvvv
-	@ r7 next_tick
-	@ ip tick
-
-	push	{r4, r5, r6, r7, lr}
-
-	ldr  r4, [sp, #20]   @ both one
-	ldr  r5, [sp, #24]   @ half_period_ticks
-	ldr  r6, [sp, #28]   @ total_ticks_required
-
-	mov  ip, #0          @ tick counter
-	mov  r7, r5          @ next tick
-
-sync_loop:
-	bl   ite_sync_clock
-	strh r1, [r0]        @ both_zero
-	add  ip, ip, 1       @ cycle counter increment
-
-	bl   ite_sync_clock
-	strh r2, [r0]        @ one_zero
-	mov  r8, r8
-
-	bl   ite_sync_clock
-	strh r3, [r0]        @ zero_one
-	mov  r8, r8
-
-	bl   ite_sync_clock
-	strh r4, [r0]        @ both_one
-
-	cmp  ip, r6
-	bcc  sync_loop
-
-	pop  {r4, r5, r6, r7, pc}
-
diff --git a/chip/g/ite_sync.h b/chip/g/ite_sync.h
deleted file mode 100644
index c25dc57bc4..0000000000
--- a/chip/g/ite_sync.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CHIP_G_ITE_SYNC_H
-#define __CHIP_G_ITE_SYNC_H
-
-#include "util.h"
-
-/*
- * Assembler function to generates ITE EC sync sequence, which requires two
- * lines generating phase locked 200 KHz and 100 KHz clocks. This is achieved
- * by directly togging two GPIOs.
- *
- * gpio_addr: address of the register to write to drive the GPIOs
- * both_zero:
- * one_zero:
- * zero_one:
- * both_one: values to write at gpio_addr to set the tow lines to these
- *          stattes
- * half_period_ticks: number of interations of the tight loop to last for half
- *          the period of the higher frequency
- * total_ticks_required: total ticks required to generate the sequence of the
- *          necessary duration.
- */
-void ite_sync(volatile uint16_t *gpio_addr, uint16_t both_zero,
-	      uint16_t one_zero, uint16_t zero_one, uint16_t both_one,
-	      uint32_t half_period_ticks, uint32_t total_ticks_required);
-
-
-/* Generate ITE SYNC sequence on the I2C interface controlling the EC. */
-void generate_ite_sync(void);
-
-#endif
diff --git a/chip/g/jitter.c b/chip/g/jitter.c
deleted file mode 100644
index bb6edaa805..0000000000
--- a/chip/g/jitter.c
+++ /dev/null
@@ -1,245 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "init_chip.h"
-#include "registers.h"
-#include "task.h"
-
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
-
-void init_jittery_clock_locking_optional(int highsec, int enable,
-					 int lock_required)
-{
-	int rl = runlevel_is_high();
-
-	if (lock_required) {
-		CPRINTS("%s: run level %s, request to %sable",	__func__,
-			rl ? "high" : "low", enable ? "en" : "dis");
-	}
-
-	if (rl) {
-		uint32_t trimfast = GR_FUSE(RC_JTR_OSC60_CC_TRIM);
-		uint32_t trim48 = GR_FUSE(RC_JTR_OSC48_CC_TRIM);
-		uint32_t delta = (trim48 - trimfast);
-		/*
-		 * For metastability reasons, avoid clk_jtr ~= clk_timer, make
-		 * a keepout region around 24MHz of about 0.75MHz, about 3/16
-		 * of the the delta from trimfast and trim48
-		 */
-		uint32_t skiplow = (trim48 << 4) - (delta * 6);
-		uint32_t skiphigh = (trim48 << 4) + (delta * 6);
-		uint32_t setting = trimfast << 4;
-		uint32_t stepx16;
-		uint32_t bankval;
-		int bank;
-
-		if (highsec)
-			stepx16 = (delta * 7) >> 1;
-		else
-			stepx16 = 2 * (trim48 - trimfast);
-
-		for (bank = 0; bank < 16; bank++) {
-
-			if (!enable) {
-				/*
-				 * Jitter should not be enabled, set all trims
-				 * to the same value retrieved from the fuses.
-				 * It is supposed to ensure that the internal
-				 * clock runs at 48MHz.
-				 */
-				GR_XO_JTR_JITTERY_TRIM_BANK(bank) = trim48;
-				continue;
-			}
-			/* saturate at 0xff */
-			bankval = (setting > 0xfff) ? 0xff : (setting >> 4);
-
-			GR_XO_JTR_JITTERY_TRIM_BANK(bank) = bankval;
-
-			setting += stepx16;
-			if ((setting > skiplow) && (setting < skiphigh))
-				setting = skiphigh;
-		}
-	}
-
-	GWRITE_FIELD(XO, CLK_JTR_TRIM_CTRL, RC_COARSE_TRIM_SRC, 2);
-	GWRITE_FIELD(XO, CLK_JTR_TRIM_CTRL, RC_INITIAL_TRIM_PERIOD, 100);
-	GWRITE_FIELD(XO, CLK_JTR_TRIM_CTRL, RC_TRIM_EN, 1);
-	GREG32(XO, CLK_JTR_JITTERY_TRIM_EN) = 1;
-	GREG32(XO, CLK_JTR_SYNC_CONTENTS) = 0;
-
-	if (lock_required) {
-		/* Writing any value locks things until the next hard reboot */
-		GREG32(XO, CFG_WR_EN) = 0;
-		GREG32(XO, JTR_CTRL_EN) = 0;
-	}
-}
-
-void init_jittery_clock(int highsec)
-{
-	init_jittery_clock_locking_optional(highsec, 1, 1);
-}
-
-void init_sof_clock(void)
-{
-	/* Copy fuse value into software registers, both coarse and fine */
-	unsigned coarseTrimVal = GR_FUSE(RC_TIMER_OSC48_CC_TRIM);
-	unsigned fineTrimVal = GR_FUSE(RC_TIMER_OSC48_FC_TRIM);
-
-	/* We think SOF toggle happens once every mS, or ~24000 clock ticks */
-	unsigned targetCnt = PCLK_FREQ / 1000;
-
-	/* The possible operations of a particular calibration bucket */
-	unsigned binaryDnOp = 0x1 | 0x1 << 4;
-	unsigned binaryUpOp = 0x1 | 0x0 << 4;
-	unsigned subOp      = 0x3 | 0x1 << 4;
-	unsigned addOp      = 0x2 | 0x1 << 4;
-	unsigned nop        = 0;
-
-	GREG32(XO, CLK_TIMER_RC_COARSE_ATE_TRIM) = coarseTrimVal;
-	GREG32(XO, CLK_TIMER_RC_FINE_ATE_TRIM) = fineTrimVal;
-
-	/* Coarse trim values come from software */
-	GWRITE_FIELD(XO, CLK_TIMER_TRIM_CTRL, RC_COARSE_TRIM_SRC, 0);
-
-	/* enable error interrupts
-	 * This enables underrun and overflow interrupts */
-	GREG32(XO, DXO_INT_ENABLE) = 0xC;
-
-	/* Setup SOF calibration buckets and associated operations */
-	GREG32(XO, CLK_TIMER_SLOW_CALIB0) = targetCnt * 70 / 100;
-	GREG32(XO, CLK_TIMER_SLOW_CALIB1) = targetCnt * 80 / 100;
-	GREG32(XO, CLK_TIMER_SLOW_CALIB2) = targetCnt * 90 / 100;
-	GREG32(XO, CLK_TIMER_SLOW_CALIB3) =
-		targetCnt * (1000000 - 1250) / 1000000;
-	GREG32(XO, CLK_TIMER_SLOW_CALIB4) = targetCnt;
-	GREG32(XO, CLK_TIMER_SLOW_CALIB5) =
-		targetCnt * (1000000 + 1250) / 1000000;
-	GREG32(XO, CLK_TIMER_SLOW_CALIB6) = targetCnt * 110 / 100;
-	GREG32(XO, CLK_TIMER_SLOW_CALIB7) = targetCnt * 120 / 100;
-
-	/* This is a work-around for the screwy SOF */
-	GREG32(XO, CLK_TIMER_SLOW_CALIB_CTRL0) = nop;
-	GREG32(XO, CLK_TIMER_SLOW_CALIB_CTRL1) = binaryDnOp;
-	GREG32(XO, CLK_TIMER_SLOW_CALIB_CTRL2) = binaryDnOp;
-	GREG32(XO, CLK_TIMER_SLOW_CALIB_CTRL3) = subOp;
-	GREG32(XO, CLK_TIMER_SLOW_CALIB_CTRL4) = nop;
-	GREG32(XO, CLK_TIMER_SLOW_CALIB_CTRL5) = nop;
-	GREG32(XO, CLK_TIMER_SLOW_CALIB_CTRL6) = addOp;
-	GREG32(XO, CLK_TIMER_SLOW_CALIB_CTRL7) = binaryUpOp;
-	GREG32(XO, CLK_TIMER_SLOW_CALIB_CTRL8) = binaryUpOp;
-
-	/* Set the calibration mode */
-	GWRITE_FIELD(XO, CLK_TIMER_CALIB_TRIM_CTRL, ENABLE_FAST, 0);
-	GWRITE_FIELD(XO, CLK_TIMER_CALIB_TRIM_CTRL, ENABLE_SLOW, 1);
-	GWRITE_FIELD(XO, CLK_TIMER_CALIB_TRIM_CTRL, SLOW_MODE_SEL, 0); /* SOF */
-	GWRITE_FIELD(XO, CLK_TIMER_CALIB_TRIM_CTRL, MAX_TRIM_SEL, 1);
-	/* Don't stop when a NOP operation is seen, keep on calibrating */
-	GWRITE_FIELD(XO, CLK_TIMER_CALIB_TRIM_CTRL, STOP_ON_NOP, 0);
-
-	/* Set source of trim codes:
-	 * coarse trim comes from software
-	 * fine trim comes from calibration engine */
-	GWRITE_FIELD(XO, CLK_TIMER_TRIM_CTRL, RC_COARSE_TRIM_SRC, 0);
-	GWRITE_FIELD(XO, CLK_TIMER_TRIM_CTRL, RC_FINE_TRIM_SRC, 1);
-
-	/* Enable dynamic trim */
-	GWRITE_FIELD(XO, CLK_TIMER_TRIM_CTRL, RC_TRIM_EN, 1);
-
-	/* Sync everything! */
-	GREG32(XO, CLK_TIMER_SYNC_CONTENTS) = 1;
-
-	/* Enable interrupts */
-	task_enable_irq(GC_IRQNUM_XO0_SLOW_CALIB_UNDERRUN_INT);
-	task_enable_irq(GC_IRQNUM_XO0_SLOW_CALIB_OVERFLOW_INT);
-}
-
-/* When the calibration under runs, it means the fine trim code
- * has reached 0, but the clock is still too slow.  Thus,
- * software must reduce the coarse trim code by 1 */
-static void timer_sof_calibration_underrun_int(void)
-{
-	unsigned coarseTrimValue = GREG32(XO, CLK_TIMER_RC_COARSE_ATE_TRIM);
-
-	if (coarseTrimValue > 0x00) {
-		CPRINTS("%s: 0x%02x", __func__, coarseTrimValue);
-		GREG32(XO, CLK_TIMER_RC_COARSE_ATE_TRIM) = coarseTrimValue - 1;
-	}
-
-	GREG32(XO, DXO_INT_STATE) =
-		GC_XO_DXO_INT_STATE_SLOW_CALIB_UNDERRUN_MASK;
-}
-DECLARE_IRQ(GC_IRQNUM_XO0_SLOW_CALIB_UNDERRUN_INT,
-	    timer_sof_calibration_underrun_int, 1);
-
-/* When the calibration overflows, it means the fine trim code
- * has reached 0x1F, but the clock is still too fast.  Thus,
- * software must increase the coarse trim code by 1 */
-static void timer_sof_calibration_overflow_int(void)
-{
-	unsigned coarseTrimValue = GREG32(XO, CLK_TIMER_RC_COARSE_ATE_TRIM);
-
-	/* Coarse trim range is 0..0xff. */
-	if (coarseTrimValue < 0xff) {
-		CPRINTS("%s: 0x%02x", __func__, coarseTrimValue);
-		GREG32(XO, CLK_TIMER_RC_COARSE_ATE_TRIM) = coarseTrimValue + 1;
-	}
-
-	GREG32(XO, DXO_INT_STATE) =
-		GC_XO_DXO_INT_STATE_SLOW_CALIB_OVERFLOW_MASK;
-}
-DECLARE_IRQ(GC_IRQNUM_XO0_SLOW_CALIB_OVERFLOW_INT,
-	    timer_sof_calibration_overflow_int, 1);
-
-#ifdef DEBUG_ME
-static int command_sof(int argc, char **argv)
-{
-	ccprintf("FUSE_RC_TIMER_OSC48_CC_TRIM) 0x%08x\n",
-		 GR_FUSE(RC_TIMER_OSC48_CC_TRIM));
-	ccprintf("FUSE_RC_TIMER_OSC48_FC_TRIM) 0x%08x\n",
-		 GR_FUSE(RC_TIMER_OSC48_FC_TRIM));
-
-	ccprintf("CLK_TIMER_RC_COARSE_ATE_TRIM 0x%08x\n",
-		 GREG32(XO, CLK_TIMER_RC_COARSE_ATE_TRIM));
-	ccprintf("CLK_TIMER_RC_FINE_ATE_TRIM   0x%08x\n",
-		 GREG32(XO, CLK_TIMER_RC_FINE_ATE_TRIM));
-
-	ccprintf("CLK_TIMER_TRIM_CTRL          0x%08x\n",
-		 GREG32(XO, CLK_TIMER_TRIM_CTRL));
-
-	ccprintf("CLK_TIMER_CALIB_TRIM_CTRL    0x%08x\n",
-		 GREG32(XO, CLK_TIMER_CALIB_TRIM_CTRL));
-
-	ccprintf("DXO_INT_ENABLE               0x%08x\n",
-		 GREG32(XO, DXO_INT_ENABLE));
-
-	ccprintf("CLK_TIMER_SLOW_CALIB\n");
-	ccprintf("  0: 0x%04x\n", GREG32(XO, CLK_TIMER_SLOW_CALIB0));
-	ccprintf("  1: 0x%04x\n", GREG32(XO, CLK_TIMER_SLOW_CALIB1));
-	ccprintf("  2: 0x%04x\n", GREG32(XO, CLK_TIMER_SLOW_CALIB2));
-	ccprintf("  3: 0x%04x\n", GREG32(XO, CLK_TIMER_SLOW_CALIB3));
-	ccprintf("  4: 0x%04x\n", GREG32(XO, CLK_TIMER_SLOW_CALIB4));
-	ccprintf("  5: 0x%04x\n", GREG32(XO, CLK_TIMER_SLOW_CALIB5));
-	ccprintf("  6: 0x%04x\n", GREG32(XO, CLK_TIMER_SLOW_CALIB6));
-	ccprintf("  7: 0x%04x\n", GREG32(XO, CLK_TIMER_SLOW_CALIB7));
-
-	ccprintf("CLK_TIMER_SLOW_CALIB_CTRL\n");
-	ccprintf("  0: 0x%02x\n", GREG32(XO, CLK_TIMER_SLOW_CALIB_CTRL0));
-	ccprintf("  1: 0x%02x\n", GREG32(XO, CLK_TIMER_SLOW_CALIB_CTRL1));
-	ccprintf("  2: 0x%02x\n", GREG32(XO, CLK_TIMER_SLOW_CALIB_CTRL2));
-	ccprintf("  3: 0x%02x\n", GREG32(XO, CLK_TIMER_SLOW_CALIB_CTRL3));
-	ccprintf("  4: 0x%02x\n", GREG32(XO, CLK_TIMER_SLOW_CALIB_CTRL4));
-	ccprintf("  5: 0x%02x\n", GREG32(XO, CLK_TIMER_SLOW_CALIB_CTRL5));
-	ccprintf("  6: 0x%02x\n", GREG32(XO, CLK_TIMER_SLOW_CALIB_CTRL6));
-	ccprintf("  7: 0x%02x\n", GREG32(XO, CLK_TIMER_SLOW_CALIB_CTRL7));
-	ccprintf("  8: 0x%02x\n", GREG32(XO, CLK_TIMER_SLOW_CALIB_CTRL8));
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(sof, command_sof,
-			"",
-			"Display the SoF clock stuff");
-#endif	/* DEBUG_ME */
diff --git a/chip/g/loader/debug_printf.c b/chip/g/loader/debug_printf.c
deleted file mode 100644
index 4d7e67b7ec..0000000000
--- a/chip/g/loader/debug_printf.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#include "debug_printf.h"
-
-#include "printf.h"
-#include "uart.h"
-
-#include "stddef.h"
-
-static int printchar(void *context, int c)
-{
-	if (c == '\n')
-		uart_write_char('\r');
-	uart_write_char(c);
-
-	return 0;
-}
-
-void debug_printf(const char *format, ...)
-{
-	va_list args;
-
-	va_start(args, format);
-	vfnprintf(printchar, NULL, format, args);
-	va_end(args);
-}
diff --git a/chip/g/loader/debug_printf.h b/chip/g/loader/debug_printf.h
deleted file mode 100644
index d34a18c9ba..0000000000
--- a/chip/g/loader/debug_printf.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#ifndef __EC_CHIP_G_LOADER_DEBUG_PRINTF_H
-#define __EC_CHIP_G_LOADER_DEBUG_PRINTF_H
-
-__attribute__((__format__(__printf__, 1, 2)))
-void debug_printf(const char *format, ...);
-
-#ifdef DEBUG
-#define VERBOSE debug_printf
-#else
-#define VERBOSE(...)
-#endif
-
-#endif /* __EC_CHIP_G_LOADER_DEBUG_PRINTF_H */
diff --git a/chip/g/loader/key_ladder.c b/chip/g/loader/key_ladder.c
deleted file mode 100644
index 71ed200ef2..0000000000
--- a/chip/g/loader/key_ladder.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "key_ladder.h"
-#include "debug_printf.h"
-#include "registers.h"
-/* #include "setup.h" */
-
-#include "dcrypto.h"
-
-void key_ladder_step(uint32_t cert, const uint32_t *input)
-{
-	uint32_t flags;
-
-	GREG32(KEYMGR, SHA_ITOP) = 0;  /* Clear status. */
-
-	VERBOSE("Cert %2u: ", cert);
-
-	GWRITE_FIELD(KEYMGR, SHA_USE_CERT, INDEX, cert);
-	GWRITE_FIELD(KEYMGR, SHA_USE_CERT, ENABLE, 1);
-	GWRITE_FIELD(KEYMGR, SHA_CFG_EN, INT_EN_DONE, 1);
-	GWRITE_FIELD(KEYMGR, SHA_TRIG, TRIG_GO, 1);
-
-	if (input) {
-		int i;
-
-		for (i = 0; i < 8; ++i)
-			GREG32(KEYMGR, SHA_INPUT_FIFO) = *input++;
-
-		GWRITE_FIELD(KEYMGR, SHA_TRIG, TRIG_STOP, 1);
-	}
-
-	while (!GREG32(KEYMGR, SHA_ITOP))
-		;
-
-	GREG32(KEYMGR, SHA_ITOP) = 0;  /* Clear status. */
-
-	flags = GREG32(KEYMGR, HKEY_ERR_FLAGS);
-	if (flags)
-		debug_printf("Cert %2u: fail %x\n", cert, flags);
-	else
-		VERBOSE("flags %x\n", flags);
-}
diff --git a/chip/g/loader/key_ladder.h b/chip/g/loader/key_ladder.h
deleted file mode 100644
index 094dcf8940..0000000000
--- a/chip/g/loader/key_ladder.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __EC_CHIP_G_LOADER_KEY_LADDER_H
-#define __EC_CHIP_G_LOADER_KEY_LADDER_H
-
-#include <stdint.h>
-#include <stddef.h>
-
-void key_ladder_step(uint32_t certificate, const uint32_t *input);
-
-#endif  /* ! __EC_CHIP_G_LOADER_KEY_LADDER_H */
diff --git a/chip/g/loader/launch.c b/chip/g/loader/launch.c
deleted file mode 100644
index 077961fc67..0000000000
--- a/chip/g/loader/launch.c
+++ /dev/null
@@ -1,233 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "dcrypto.h"
-#include "debug_printf.h"
-#include "key_ladder.h"
-#include "registers.h"
-#include "rom_flash.h"
-#include "setup.h"
-#include "signed_header.h"
-#include "uart.h"
-#include "verify.h"
-
-static int unlockedForExecution(void)
-{
-	return GREAD_FIELD(GLOBALSEC, SB_COMP_STATUS, SB_BL_SIG_MATCH);
-}
-
-void _jump_to_address(const void *addr)
-{
-	REG32(GC_M3_VTOR_ADDR) = (unsigned)addr;  /* Set vector base. */
-
-	__asm__ volatile("ldr sp, [%0]; \
-			ldr pc, [%0, #4];"
-			 : : "r"(addr)
-			 : "memory");
-
-	__builtin_unreachable();
-}
-
-void tryLaunch(uint32_t adr, size_t max_size)
-{
-	static struct {
-		uint32_t img_hash[SHA256_DIGEST_WORDS];
-		uint32_t fuses_hash[SHA256_DIGEST_WORDS];
-		uint32_t info_hash[SHA256_DIGEST_WORDS];
-	} hashes;
-	static uint32_t hash[SHA256_DIGEST_WORDS];
-	static uint32_t fuses[FUSE_MAX];
-	static uint32_t info[INFO_MAX];
-	int i;
-	uint32_t major;
-	const uint32_t FAKE_rom_hash[8] = {1, 2, 3, 4, 5, 6, 7, 8};
-	const struct SignedHeader *hdr = (const struct SignedHeader *)(adr);
-
-	memset(&hashes, 0, sizeof(hashes));
-
-	/* Sanity check image header. */
-	if (hdr->magic != -1)
-		return;
-	if (hdr->image_size > max_size)
-		return;
-
-	/* Sanity checks that image belongs at adr. */
-	if (hdr->ro_base < adr)
-		return;
-	if (hdr->ro_max > adr + max_size)
-		return;
-	if (hdr->rx_base < adr)
-		return;
-	if (hdr->rx_max > adr + max_size)
-		return;
-
-	VERBOSE("considering image at 0x%8x\n", hdr);
-	VERBOSE("image size 0x%8x\n", hdr->image_size);
-	VERBOSE("hashing from 0x%8x to 0x%8x\n",
-		&hdr->tag, adr + hdr->image_size);
-
-	/* Setup candidate execution region 1 based on header information. */
-	/* TODO: harden against glitching: multi readback, check? */
-	GREG32(GLOBALSEC, CPU0_I_STAGING_REGION1_BASE_ADDR) = hdr->rx_base;
-	GREG32(GLOBALSEC, CPU0_I_STAGING_REGION1_SIZE) =
-		hdr->rx_max - hdr->rx_base - 1;
-	GWRITE_FIELD(GLOBALSEC, CPU0_I_STAGING_REGION1_CTRL, EN, 1);
-	GWRITE_FIELD(GLOBALSEC, CPU0_I_STAGING_REGION1_CTRL, RD_EN, 1);
-	DCRYPTO_SHA256_hash((uint8_t *) &hdr->tag,
-			hdr->image_size - offsetof(struct SignedHeader, tag),
-			(uint8_t *) hashes.img_hash);
-
-	VERBOSE("img_hash  : %ph\n", HEX_BUF(hashes.img_hash, 32));
-
-	/* Sense fuses into RAM array; hash array. */
-	/* TODO: is this glitch resistant enough? Certainly is simple.. */
-	for (i = 0; i < FUSE_MAX; ++i)
-		fuses[i] = FUSE_IGNORE;
-
-	for (i = 0; i < FUSE_MAX; ++i) {
-		/*
-		 * For the fuses the header cares about, read their values
-		 * into the map.
-		 */
-		if (hdr->fusemap[i>>5] & (1 << (i&31))) {
-			/*
-			 * BNK0_INTG_CHKSUM is the first fuse and as such the
-			 * best reference to the base address of the fuse
-			 * memory map.
-			 */
-			fuses[i] = GREG32_ADDR(FUSE, BNK0_INTG_CHKSUM)[i];
-		}
-	}
-
-	DCRYPTO_SHA256_hash((uint8_t *) fuses, sizeof(fuses),
-			(uint8_t *) hashes.fuses_hash);
-
-	VERBOSE("fuses_hash: %ph\n", HEX_BUF(hashes.fuses_hash, 32));
-
-	/* Sense info into RAM array; hash array. */
-	for (i = 0; i < INFO_MAX; ++i)
-		info[i] = INFO_IGNORE;
-
-	for (i = 0; i < INFO_MAX; ++i) {
-		if (hdr->infomap[i>>5] & (1 << (i&31))) {
-			uint32_t val = 0;
-			/* read 2nd bank of info */
-			int retval = flash_info_read(i + INFO_MAX, &val);
-
-			info[i] ^= val ^ retval;
-		}
-	}
-
-	DCRYPTO_SHA256_hash((uint8_t *) info, sizeof(info),
-			(uint8_t *) hashes.info_hash);
-	VERBOSE("info_hash : %ph\n", HEX_BUF(hashes.info_hash, 32));
-
-	/* Hash our set of hashes to get final hash. */
-	DCRYPTO_SHA256_hash((uint8_t *) &hashes, sizeof(hashes),
-			(uint8_t *) hash);
-
-	/*
-	 * Write measured hash to unlock register to try and unlock execution.
-	 * This would match when doing warm-boot from suspend, so we can avoid
-	 * the slow RSA verify.
-	 */
-	for (i = 0; i < SHA256_DIGEST_WORDS; ++i)
-		GREG32_ADDR(GLOBALSEC, SB_BL_SIG0)[i] = hash[i];
-
-	/*
-	 * Unlock attempt. Value written is irrelevant, as long as something
-	 * is written.
-	 */
-	GREG32(GLOBALSEC, SIG_UNLOCK) = 1;
-
-	if (!unlockedForExecution()) {
-		/* Assume warm-boot failed; do full RSA verify. */
-		LOADERKEY_verify(&hdr->keyid, hdr->signature, hash);
-		/*
-		 * PWRDN_SCRATCH* should be write-locked, tied to successful
-		 * SIG_MATCH. Thus ARM is only able to write this hash if
-		 * signature was correct.
-		 */
-		for (i = 0; i < SHA256_DIGEST_WORDS; ++i)
-			/* TODO: verify written values as glitch protection? */
-			GREG32_ADDR(PMU, PWRDN_SCRATCH8)[i] = hash[i];
-	}
-
-
-	if (!unlockedForExecution()) {
-		debug_printf("Failed to unlock for execution image at 0x%08x\n",
-			     adr);
-		return;
-	}
-
-	/*
-	 * Write PMU_PWRDN_SCRATCH_LOCK1_OFFSET to lock against rewrites.
-	 * TODO: glitch resist
-	 */
-	GREG32(PMU, PWRDN_SCRATCH_LOCK1) = 1;
-
-	/*
-	 * Drop software level to stop SIG_MATCH from future write-unlocks.
-	 * TODO: glitch detect / verify?
-	 */
-	GREG32(GLOBALSEC, SOFTWARE_LVL) = 0x33;
-
-	/* Write hdr->tag, hdr->epoch_ to KDF engine FWR[0..7] */
-	for (i = 0; i < ARRAY_SIZE(hdr->tag); ++i)
-		GREG32_ADDR(KEYMGR, HKEY_FWR0)[i] = hdr->tag[i];
-
-	GREG32(KEYMGR, HKEY_FWR7) = hdr->epoch_;
-
-	/* Crank keyladder */
-	if (!(GREAD(FUSE, FLASH_PERSO_PAGE_LOCK) &
-	      (GC_FUSE_HIK_CREATE_LOCK_VAL_MASK <<
-	       GC_FUSE_HIK_CREATE_LOCK_VAL_LSB))) {
-		VERBOSE("Re-reading INFO0\n");
-		/*
-		 * Needed because FUSE_FLASH_PERSO_PAGE_LOCK_OFFSET isn't
-		 * blown) wipe out the flash secrets saved in keymgr and
-		 * re-read info0
-		 */
-		GREG32(KEYMGR, FLASH_RCV_WIPE) = 1;
-		GREG32(FLASH, FSH_ENABLE_INFO0_SHADOW_READ) = 1;
-	}
-
-	/* Turn up random stalls for SHA */
-	GREG32(KEYMGR, SHA_RAND_STALL_CTL_FREQ) = 0;  /* 0:50% */
-
-	major = hdr->major_;
-	GREG32(KEYMGR, FW_MAJOR_VERSION) = major;
-
-	/*
-	 * Lock FWR (NOTE: needs to happen after writing major!) TODO: glitch
-	 * protect?
-	 */
-	GREG32(KEYMGR, FWR_VLD) = 2;
-	GREG32(KEYMGR, FWR_LOCK) = 1;
-
-	key_ladder_step(40, FAKE_rom_hash);
-
-	/* TODO: do cert #40 and lock in ROM? */
-	GREG32(GLOBALSEC, HIDE_ROM) = 1;
-
-	/* TODO: bump runlevel(s) according to signature header */
-	/*
-	 * Flash write protect entire image area (to guard signed blob)
-	 * REGION0 protects boot_loader, use REGION1 to protect app
-	 */
-	GREG32(GLOBALSEC, FLASH_REGION1_BASE_ADDR) = adr;
-	GREG32(GLOBALSEC, FLASH_REGION1_SIZE) = hdr->image_size - 1;
-	GWRITE_FIELD(GLOBALSEC, FLASH_REGION1_CTRL, EN, 1);
-	GWRITE_FIELD(GLOBALSEC, FLASH_REGION1_CTRL, RD_EN, 1);
-	GWRITE_FIELD(GLOBALSEC, FLASH_REGION1_CTRL, WR_EN, 0);
-
-	/* TODO: lock FLASH_REGION 1? */
-	disarmRAMGuards();
-
-	debug_printf("Valid image found at 0x%pP, jumping", hdr);
-	uart_tx_flush();
-
-	_jump_to_address(&hdr[1]);
-}
diff --git a/chip/g/loader/main.c b/chip/g/loader/main.c
deleted file mode 100644
index e304c30a49..0000000000
--- a/chip/g/loader/main.c
+++ /dev/null
@@ -1,133 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "debug_printf.h"
-#include "printf.h"
-#include "registers.h"
-#include "setup.h"
-#include "signed_header.h"
-#include "system.h"
-#include "trng.h"
-#include "uart.h"
-
-/*
- * This file is a proof of concept stub which will be extended and split into
- * appropriate pieces shortly, when full blown support for cr50 bootrom is
- * introduced.
- */
-uint32_t sleep_mask;
-
-timestamp_t get_time(void)
-{
-	timestamp_t ret;
-
-	ret.val = 0;
-
-	return ret;
-}
-
-static int panic_txchar(void *context, int c)
-{
-	if (c == '\n')
-		panic_txchar(context, '\r');
-
-	/* Wait for space in transmit FIFO */
-	while (!uart_tx_ready())
-		;
-
-	/* Write the character directly to the transmit FIFO */
-	uart_write_char(c);
-
-	return 0;
-}
-
-void panic_puts(const char *outstr)
-{
-	/* Put all characters in the output buffer */
-	while (*outstr)
-		panic_txchar(NULL, *outstr++);
-}
-
-void panic_printf(const char *format, ...)
-{
-	va_list args;
-
-	va_start(args, format);
-	vfnprintf(panic_txchar, NULL, format, args);
-	va_end(args);
-}
-
-/* Returns 1 if version a is newer, 0 otherwise. */
-int is_newer_than(const struct SignedHeader *a, const struct SignedHeader *b)
-{
-	if (a->epoch_ != b->epoch_)
-		return a->epoch_ > b->epoch_;
-	if (a->major_ != b->major_)
-		return a->major_ > b->major_;
-	if (a->minor_ != b->minor_)
-		return a->minor_ > b->minor_;
-	if (a->timestamp_ != b->timestamp_)
-		return a->timestamp_ > b->timestamp_;
-
-	return 1; /* All else being equal, consider A to be newer. */
-}
-
-int main(void)
-{
-	const struct SignedHeader *a, *b, *first, *second;
-	init_trng();
-	uart_init();
-	debug_printf("\n\n%s bootloader, %8u_%u@%u\n",
-		     STRINGIFY(BOARD), GREG32(SWDP, BUILD_DATE),
-		     GREG32(SWDP, BUILD_TIME), GREG32(SWDP, P4_LAST_SYNC));
-	unlockFlashForRW();
-
-	a = (const struct SignedHeader *)(CONFIG_PROGRAM_MEMORY_BASE +
-					  CONFIG_RW_MEM_OFF);
-	b = (const struct SignedHeader *)(CONFIG_PROGRAM_MEMORY_BASE +
-					  CONFIG_RW_B_MEM_OFF);
-	/* Default to loading the older version first.
-	 * Run from bank a if the versions are equal.
-	 */
-	if (is_newer_than(a, b)) {
-		first = a;
-		second = b;
-	} else {
-		first = b;
-		second = a;
-	}
-	if (GREG32(PMU, PWRDN_SCRATCH30) == 0xcafebabe) {
-		/* Launch from the alternate bank first.
-		 * This knob will be used to attempt to load the newer version
-		 * after an update and to run from bank b in the face of flash
-		 * integrity issues.
-		 */
-		debug_printf("PWRDN_SCRATCH30 set to magic value\n");
-		GREG32(PMU, PWRDN_SCRATCH30) = 0x0;
-		a = first;
-		first = second;
-		second = a;
-	}
-	tryLaunch((uint32_t)first, CONFIG_RW_SIZE);
-	debug_printf("Failed to launch.\n");
-	debug_printf("Attempting to load the alternate image.\n");
-	tryLaunch((uint32_t)second, CONFIG_RW_SIZE);
-	debug_printf("No valid image found, not sure what to do...\n");
-	/* TODO: Some applications might want to reboot instead. */
-	halt();
-	return 1;
-}
-
-void panic_reboot(void)
-{
-	panic_puts("\n\nRebooting...\n");
-	system_reset(0);
-}
-
-void interrupt_disable(void)
-{
-	asm("cpsid i");
-}
diff --git a/chip/g/loader/rom_flash.c b/chip/g/loader/rom_flash.c
deleted file mode 100644
index 9666f2464a..0000000000
--- a/chip/g/loader/rom_flash.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "debug_printf.h"
-#include "setup.h"
-#include "rom_flash.h"
-
-static int _flash_error(void)
-{
-	int retval = GREG32(FLASH, FSH_ERROR);
-
-	if (!retval)
-		return 0;
-
-	debug_printf("Register FLASH_FSH_ERROR is not zero (found %x).\n",
-		retval);
-	debug_printf("Will read again to verify FSH_ERROR was cleared ");
-	debug_printf("and then continue...\n");
-
-	retval = GREG32(FLASH, FSH_ERROR);
-	if (retval) {
-		debug_printf("ERROR: Read to FLASH_FSH_ERROR (%x) "
-			     "did not clear it\n", retval);
-	}
-
-	return retval;
-}
-
-/* Verify the flash controller is awake. */
-static int _check_flash_is_awake(void)
-{
-	int retval;
-
-	GREG32(FLASH, FSH_TRANS) = 0xFFFFFFFF;
-	retval = GREG32(FLASH, FSH_TRANS);
-	GREG32(FLASH, FSH_TRANS) =  0x0;
-
-	if (retval == 0) {
-		debug_printf("ERROR:FLASH Controller seems unresponsive. ");
-		debug_printf("Did you make sure to run 'reseth'?\n");
-		return E_FL_NOT_AWAKE;
-	}
-
-	return 0;
-}
-
-/* Send cmd to flash controller. */
-static int _flash_cmd(uint32_t fidx, uint32_t cmd)
-{
-	int cnt, retval;
-
-	/* Activate controller. */
-	GREG32(FLASH, FSH_PE_EN) = FSH_OP_ENABLE;
-	GREG32_ADDR(FLASH, FSH_PE_CONTROL0)[fidx] = cmd;
-
-	/* wait on FSH_PE_EN (means the operation started) */
-	cnt = 500;  /* TODO(mschilder): pick sane value. */
-
-	do {
-		retval = GREG32(FLASH, FSH_PE_EN);
-	} while (retval && cnt--);
-
-	if (retval) {
-		debug_printf("ERROR: FLASH_FSH_PE_EN never went to 0, is ");
-		debug_printf("0x%x after timeout\n", retval);
-		return E_FL_TIMEOUT;
-	}
-
-	/*
-	 * wait 100us before checking FSH_PE_CONTROL (means the operation
-	 * ended)
-	 */
-	cnt = 1000000;
-	do {
-		retval = GREG32_ADDR(FLASH, FSH_PE_CONTROL0)[fidx];
-	} while (retval && --cnt);
-
-	if (retval) {
-		debug_printf
-		    ("ERROR: FLASH_FSH_PE_CONTROL%d is 0x%x after timeout\n",
-		     fidx, retval);
-		GREG32_ADDR(FLASH, FSH_PE_CONTROL0)[fidx] = 0;
-		return E_FL_TIMEOUT;
-	}
-
-	return 0;
-}
-
-int flash_info_read(uint32_t offset, uint32_t *dst)
-{
-	int retval;
-
-	/* Make sure flash controller is awake. */
-	retval = _check_flash_is_awake();
-	if (retval)
-		return retval;
-
-	GWRITE_FIELD(FLASH, FSH_TRANS, OFFSET, offset);
-	GWRITE_FIELD(FLASH, FSH_TRANS, MAINB, 1);
-	GWRITE_FIELD(FLASH, FSH_TRANS, SIZE, 1);
-
-	retval = _flash_cmd(1, FSH_OP_READ);
-	if (retval)
-		return retval;
-
-	if (_flash_error())
-		return E_FL_ERROR;
-
-	if (!retval)
-		*dst = GREG32(FLASH, FSH_DOUT_VAL1);
-
-	return retval;
-}
diff --git a/chip/g/loader/rom_flash.h b/chip/g/loader/rom_flash.h
deleted file mode 100644
index 7895d14af2..0000000000
--- a/chip/g/loader/rom_flash.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __EC_CHIP_G_LOADER_ROM_FLASH_H
-#define __EC_CHIP_G_LOADER_ROM_FLASH_H
-
-#include "registers.h"
-
-#define FSH_OP_BULKERASE GC_CONST_FSH_PE_CONTROL_BULKERASE
-#define FSH_OP_ENABLE    GC_CONST_FSH_PE_EN
-#define FSH_OP_ERASE     GC_CONST_FSH_PE_CONTROL_ERASE
-#define FSH_OP_PROGRAM   GC_CONST_FSH_PE_CONTROL_PROGRAM
-#define FSH_OP_READ      GC_CONST_FSH_PE_CONTROL_READ
-
-#if 0
-#define num_flashes 2
-/*
- * FIX ME: words_per_row = m.get_flash_param("FlashWordsPerRow")
- * FIX ME: rows_per_page = m.get_flash_param("FlashRowsPerPage")
- * FIX ME: words_per_page = int(words_per_row)*int(rows_per_page)
- */
-#define words_per_page 512
-/* This is BAD... This number is based on the TSMC spec Nmp=Tprog/Tsmp */
-#define _max_prog_cycles 9
-/* This is BAD... This number is based on the TSMC spec Nme=Terase/Tsme */
-#define _max_erase_cycles 45
-/* This is BAD... This number is based on the TSMC spec Nme=Terase/Tsme */
-#define _max_bulkerase_cycles 45
-#define _debug_flash 0
-
-/* write words to flash */
-int flash_write(uint32_t fidx, uint32_t offset,
-		const uint32_t *data, uint32_t size);
-
-/* erase one page */
-int flash_erase(uint32_t fidx, uint32_t page);
-
-/* erase entire bank */
-int flash_wipe(uint32_t fidx);
-#endif
-
-#define E_FL_NOT_AWAKE 1
-#define E_FL_TIMEOUT 2
-#define E_FL_BAD_MAINB 3
-#define E_FL_BAD_SIZE 4
-#define E_FL_BAD_PTR 5
-#define E_FL_BAD_BANK 6
-#define E_FL_WRITE_FAIL 7
-#define E_FL_ERASE_FAIL 8
-#define E_FL_WIPE_FAIL 9
-#define E_FL_ERROR 10
-
-/* read single word from info block */
-int flash_info_read(uint32_t offset, uint32_t *dst);
-
-
-#endif  /* __EC_CHIP_G_LOADER_ROM_FLASH_H */
diff --git a/chip/g/loader/setup.c b/chip/g/loader/setup.c
deleted file mode 100644
index 4d016aa5f6..0000000000
--- a/chip/g/loader/setup.c
+++ /dev/null
@@ -1,54 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "debug_printf.h"
-#include "link_defs.h"
-#include "registers.h"
-#include "setup.h"
-
-/* Is there a system wide function for this? */
-void halt(void)
-{
-	while (1)
-		;
-}
-
-void checkBuildVersion(void)
-{
-	uint32_t last_sync = GREG32(SWDP, P4_LAST_SYNC);
-
-	if (last_sync == GC_SWDP_P4_LAST_SYNC_DEFAULT)
-		return;
-
-	debug_printf("compiled for %u, not willing to run on %u\n",
-		     GC_SWDP_P4_LAST_SYNC_DEFAULT, last_sync);
-	halt();
-}
-
-void unlockFlashForRW(void)
-{
-	uint32_t text_end = ((uint32_t)(&__data_lma_start) +
-			     (uint32_t)(&__data_end) -
-			     (uint32_t)(&__data_start) +
-			     CONFIG_FLASH_BANK_SIZE)
-		& ~(CONFIG_FLASH_BANK_SIZE - 1);
-
-	GREG32(GLOBALSEC, FLASH_REGION1_BASE_ADDR) = text_end;
-	GREG32(GLOBALSEC, FLASH_REGION1_SIZE) =
-		CONFIG_FLASH_SIZE - text_end - 1;
-	GWRITE_FIELD(GLOBALSEC, FLASH_REGION1_CTRL, EN, 1);
-	GWRITE_FIELD(GLOBALSEC, FLASH_REGION1_CTRL, RD_EN, 1);
-	GWRITE_FIELD(GLOBALSEC, FLASH_REGION1_CTRL, WR_EN, 0);
-}
-
-void disarmRAMGuards(void)
-{
-	GWRITE_FIELD(GLOBALSEC, CPU0_D_REGION0_CTRL, EN, 1);
-	GWRITE_FIELD(GLOBALSEC, CPU0_D_REGION0_CTRL, RD_EN, 1);
-	GWRITE_FIELD(GLOBALSEC, CPU0_D_REGION0_CTRL, WR_EN, 1);
-	GWRITE_FIELD(GLOBALSEC, CPU0_D_REGION1_CTRL, EN, 1);
-	GWRITE_FIELD(GLOBALSEC, CPU0_D_REGION1_CTRL, RD_EN, 1);
-	GWRITE_FIELD(GLOBALSEC, CPU0_D_REGION1_CTRL, WR_EN, 1);
-}
diff --git a/chip/g/loader/setup.h b/chip/g/loader/setup.h
deleted file mode 100644
index 4244696ef5..0000000000
--- a/chip/g/loader/setup.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __EC_CHIP_G_LOADER_SETUP_H
-#define __EC_CHIP_G_LOADER_SETUP_H
-
-#include <stddef.h>
-#include <stdint.h>
-
-void checkBuildVersion(void);
-void disarmRAMGuards(void);
-void halt(void);
-void tryLaunch(uint32_t adr, size_t max_size);
-void unlockFlashForRW(void);
-
-#endif  /* __EC_CHIP_G_LOADER_SETUP_H */
diff --git a/chip/g/loader/verify.c b/chip/g/loader/verify.c
deleted file mode 100644
index 54be724f10..0000000000
--- a/chip/g/loader/verify.c
+++ /dev/null
@@ -1,165 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "dcrypto.h"
-#include "debug_printf.h"
-#include "registers.h"
-#include "setup.h"
-#include "trng.h"
-
-#define LOADERKEYEXP 3
-#define RSA_NUM_WORDS 96
-#define RSA_NUM_BYTES (RSA_NUM_WORDS * 4)
-
-#define RANDOM_STEP 5
-
-inline uint32_t bswap(uint32_t a)
-{
-	uint32_t result;
-
-	__asm__ volatile("rev %0, %1;" : "=r"(result) : "r"(a));
-
-	return result;
-}
-
-/* Montgomery c[] += a * b[] / R % key. */
-static void montMulAdd(const uint32_t *key,
-		       uint32_t *c, const uint32_t a,
-		       const uint32_t *b)
-{
-	register uint64_t tmp;
-	uint32_t i, A, B, d0;
-
-	{
-
-		tmp = c[0] + (uint64_t)a * b[0];
-		A = tmp >> 32;
-		d0 = (uint32_t)tmp * *key++;
-		tmp = (uint32_t)tmp + (uint64_t)d0 * *key++;
-		B = tmp >> 32;
-	}
-
-	for (i = 0; i < RSA_NUM_WORDS - 1; ++i) {
-		tmp = A + (uint64_t)a * b[i + 1] + c[i + 1];
-		A = tmp >> 32;
-		tmp = B + (uint64_t)d0 * *key++ + (uint32_t)tmp;
-		c[i] = (uint32_t)tmp;
-		B = tmp >> 32;
-	}
-
-	c[RSA_NUM_WORDS - 1] = A + B;
-}
-
-/* Montgomery c[] = a[] * b[] / R % key. */
-static void montMul(const uint32_t *key,
-		    uint32_t *c, const uint32_t *a,
-		    const uint32_t *b)
-{
-	int i;
-
-	for (i = 0; i < RSA_NUM_WORDS; ++i)
-		c[i] = 0;
-
-	for (i = 0; i < RSA_NUM_WORDS; ++i)
-		montMulAdd(key, c, a[i], b);
-}
-
-/* Montgomery c[] = a[] * 1 / R % key. */
-static void montMul1(const uint32_t *key,
-		     uint32_t *c, const uint32_t *a)
-{
-	int i;
-
-	for (i = 0; i < RSA_NUM_WORDS; ++i)
-		c[i] = 0;
-
-	montMulAdd(key, c, 1, a);
-	for (i = 1; i < RSA_NUM_WORDS; ++i)
-		montMulAdd(key, c, 0, a);
-}
-
-/* In-place exponentiation to power 3 % key. */
-static void modpow3(const uint32_t *key,
-		    const uint32_t *signature, uint32_t *out)
-{
-	static uint32_t aaR[RSA_NUM_WORDS];
-	static uint32_t aaaR[RSA_NUM_WORDS];
-
-	montMul(key, aaR, signature, signature);
-	montMul(key, aaaR, aaR, signature);
-	montMul1(key, out, aaaR);
-}
-
-void LOADERKEY_verify(const uint32_t *key, const uint32_t *signature,
-		      const uint32_t *sha256)
-{
-	static uint32_t buf[RSA_NUM_WORDS]
-		__attribute__((section(".guarded_data")));
-	static uint32_t hash[SHA256_DIGEST_WORDS]
-		__attribute__((section(".guarded_data")));
-	uint32_t step, offset;
-	int i;
-
-	modpow3(key, signature, buf);
-	VERBOSE("sig %ph\n", HEX_BUF(buf, 384));
-
-	/*
-	 * If key was not 3Kb, assume 2Kb and expand for subsequent
-	 * padding + hash verification mangling.
-	 */
-	if (key[96] == 0) {
-		buf[95] ^= buf[63];
-		buf[63] ^= 0x1ffff;
-		for (i = 63; i < 95; ++i)
-			buf[i] ^= -1;
-	}
-
-	/*
-	 * XOR in offsets across buf. Mostly to get rid of all those -1 words
-	 * in there.
-	 */
-	offset = rand() % RSA_NUM_WORDS;
-	step = (RANDOM_STEP % RSA_NUM_WORDS) || 1;
-
-	for (i = 0; i < RSA_NUM_WORDS; ++i) {
-		buf[offset] ^= (0x1000u + offset);
-		offset = (offset + step) % RSA_NUM_WORDS;
-	}
-
-	/*
-	 * Xor digest location, so all words becomes 0 only iff equal.
-	 *
-	 * Also XOR in offset and non-zero const. This to avoid repeat
-	 * glitches to zero be able to produce the right result.
-	 */
-	offset = rand() % SHA256_DIGEST_WORDS;
-	step = (RANDOM_STEP % SHA256_DIGEST_WORDS) || 1;
-	for (i = 0; i < SHA256_DIGEST_WORDS; ++i) {
-		buf[offset] ^= bswap(sha256[SHA256_DIGEST_WORDS - 1 - offset])
-			^ (offset + 0x10u);
-		offset = (offset + step) % SHA256_DIGEST_WORDS;
-	}
-
-	VERBOSE("\nsig^ %ph\n\n", HEX_BUF(buf, 384));
-
-	/* Hash resulting buffer. */
-	DCRYPTO_SHA256_hash((uint8_t *) buf, RSA_NUM_BYTES, (uint8_t *) hash);
-
-	VERBOSE("hash %ph\n", HEX_BUF(hash, 32));
-
-	/*
-	 * Write computed hash to unlock register to unlock execution, iff
-	 * right. Idea is that this flow cannot be glitched to have correct
-	 * values with any probability.
-	 */
-	for (i = 0; i < SHA256_DIGEST_WORDS; ++i)
-		GREG32_ADDR(GLOBALSEC, SB_BL_SIG0)[i] = hash[i];
-
-	/*
-	 * Make an unlock attempt. Value written is irrelevant, as long as
-	 * something is written.
-	 */
-	GREG32(GLOBALSEC, SIG_UNLOCK) = 1;
-}
diff --git a/chip/g/loader/verify.h b/chip/g/loader/verify.h
deleted file mode 100644
index fe279e46c0..0000000000
--- a/chip/g/loader/verify.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __EC_CHIP_G_LOADER_VERIFY_H
-#define __EC_CHIP_G_LOADER_VERIFY_H
-
-/*
- * Verify a RSA PKCS1.5 signature against an expected sha256. Unlocks for
- * execution upon success.
- */
-void LOADERKEY_verify(const uint32_t *key,
-		      const uint32_t *signature, const uint32_t *sha256);
-
-#endif  /* __EC_CHIP_G_LOADER_VERIFY_H */
diff --git a/chip/g/pmu.c b/chip/g/pmu.c
deleted file mode 100644
index afd5906b63..0000000000
--- a/chip/g/pmu.c
+++ /dev/null
@@ -1,116 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "pmu.h"
-#include "task.h"
-
-/*
- * RC Trim constants
- */
-#define RCTRIM_RESOLUTION       (12)
-#define RCTRIM_LOAD_VAL	        BIT(11)
-#define RCTRIM_RANGE_MAX	(7 * 7)
-#define RCTRIM_RANGE_MIN	(-8 * 7)
-#define RCTRIM_RANGE		(RCTRIM_RANGE_MAX - RCTRIM_RANGE_MIN + 1)
-
-/*
- * Enable peripheral clock
- * @param perih Peripheral from @ref uint32_t
- */
-void pmu_clock_en(uint32_t periph)
-{
-	if (periph <= 31)
-		GR_PMU_PERICLKSET0 = BIT(periph);
-	else
-		GR_PMU_PERICLKSET1 = (1 << (periph - 32));
-}
-
-/*
- * Disable peripheral clock
- * @param perih Peripheral from @ref uint32_t
- */
-void pmu_clock_dis(uint32_t periph)
-{
-	if (periph <= 31)
-		GR_PMU_PERICLKCLR0 = BIT(periph);
-	else
-		GR_PMU_PERICLKCLR1 = (1 << (periph - 32));
-}
-
-/*
- * Peripheral reset
- * @param periph Peripheral from @ref uint32_t
- */
-void pmu_peripheral_rst(uint32_t periph)
-{
-	/* Reset high */
-	if (periph <= 31)
-		GR_PMU_RST0 = 1 << periph;
-	else
-		GR_PMU_RST1 = 1 << (periph - 32);
-}
-
-
-/*
- * enable clock doubler for USB purposes
- */
-void pmu_enable_clock_doubler(void)
-{
-}
-/*
- * Switch system clock to XO
- * @returns The value of XO_OSC_XTL_FSM_STATUS.	0 = okay, 1 = error.
- */
-uint32_t pmu_clock_switch_xo(void)
-{
-	return 0;
-}
-
-/*
- * Enter sleep mode and handle exiting from sleep mode
- * @warning The CPU must be in RC no trim mode before calling this function
- */
-void pmu_sleep(void)
-{
-}
-
-/*
- * Exit hibernate mode
- * This function should be called after a powerdown exit event.
- * It handles turning the power domains back on.
- * Clocks will be left in RC no trim.
- */
-void pmu_hibernate_exit(void)
-{
-}
-
-/*
- * Enter powerdown mode
- * This function does not return. The powerdown exit event will
- * cause the CPU to begin executing the system / app bootloader.
- * @warning The CPU must be in RC no trim mode
- */
-void pmu_powerdown(void)
-{
-}
-
-/*
- * Exit powerdown mode
- * This function should be called after a powerdown exit event.
- * It handles turning the power domains back on.
- * Clocks will be left in RC no trim.
- */
-void pmu_powerdown_exit(void)
-{
-}
-
-/**
- * Handle PMU interrupt
- */
-void pmu_interrupt(void)
-{
-	/* TBD */
-}
-/* DECLARE_IRQ(GC_IRQNUM_PMU_PMUINT, pmu_interrupt, 1); */
diff --git a/chip/g/pmu.h b/chip/g/pmu.h
deleted file mode 100644
index b84fab3fd5..0000000000
--- a/chip/g/pmu.h
+++ /dev/null
@@ -1,144 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_PMU_H
-#define __CROS_EC_PMU_H
-
-#include "common.h"
-#include "registers.h"
-
-enum {
-	/* RO */
-	PERIPH_CAMO             = 0x0,
-	PERIPH_CAMO0            = 0x0,
-
-	PERIPH_CRYPTO           = 0x1,
-	PERIPH_CRYPTO0          = 0x1,
-
-	PERIPH_DMA              = 0x2,
-	PERIPH_DMA0             = 0x2,
-
-	PERIPH_FLASH            = 0x3,
-	PERIPH_FLASH0           = 0x3,
-
-	PERIPH_FUSE             = 0x4,
-	PERIPH_FUSE0            = 0x4,
-
-	/* RO */
-	PERIPH_GLOBALSEC        = 0x5,
-	PERIPH_GLOBALSEC_TIMER  = 0x6,
-	PERIPH_GLOBALSEC_HS     = 0x7,
-
-	PERIPH_GPIO             = 0x8,
-	PERIPH_GPIO0            = 0x8,
-	PERIPH_GPIO1            = 0x9,
-
-	PERIPH_I2C              = 0xa,
-	PERIPH_I2C0             = 0xa,
-	PERIPH_I2C1             = 0xb,
-
-	PERIPH_I2CS             = 0xc,
-	PERIPH_I2CS0            = 0xc,
-
-	PERIPH_KEYMGR           = 0xd,
-	PERIPH_KEYMGR0          = 0xd,
-
-	/* RO */
-	PERIPH_APB0             = 0xe,
-	PERIPH_APB1             = 0xf,
-	PERIPH_APB2             = 0x10,
-	PERIPH_APB2_TIMER       = 0x11,
-	PERIPH_APB3             = 0x12,
-	PERIPH_APB3_HS          = 0x13,
-
-	PERIPH_PINMUX           = 0x14,
-
-	PERIPH_PMU              = 0x15,
-
-	PERIPH_RBOX             = 0x16,
-	PERIPH_RBOX0            = 0x16,
-
-	PERIPH_RDD              = 0x17,
-	PERIPH_RDD0             = 0x17,
-
-	PERIPH_RTC              = 0x18,
-	PERIPH_RTC0             = 0x18,
-	PERIPH_RTC_TIMER        = 0x19,
-	PERIPH_RTC0_TIMER       = 0x19,
-
-	PERIPH_SPI              = 0x1a,
-	PERIPH_SPI0             = 0x1a,
-	PERIPH_SPI1             = 0x1b,
-
-	PERIPH_SPS              = 0x1c,
-	PERIPH_SPS0             = 0x1c,
-	PERIPH_SPS0_TIMER       = 0x1d,
-
-	PERIPH_SWDP             = 0x1e,
-	PERIPH_SWDP0            = 0x1e,
-
-	/* RO */
-	PERIPH_TEMP             = 0x1f,
-	PERIPH_TEMP0            = 0x1f,
-
-	PERIPH_TIMEHS           = 0x20,
-	PERIPH_TIMEHS0          = 0x20,
-	PERIPH_TIMEHS1          = 0x21,
-
-	PERIPH_TIMELS           = 0x22,
-	PERIPH_TIMELS0          = 0x22,
-
-	PERIPH_TIMEUS           = 0x23,
-	PERIPH_TIMEUS0          = 0x23,
-
-	PERIPH_TRNG             = 0x24,
-	PERIPH_TRNG0            = 0x24,
-
-	PERIPH_UART             = 0x25,
-	PERIPH_UART0            = 0x25,
-	PERIPH_UART1            = 0x26,
-	PERIPH_UART2            = 0x27,
-
-	PERIPH_USB              = 0x28,
-	PERIPH_USB0             = 0x28,
-	PERIPH_USB0_USB_PHY     = 0x29,
-
-	/* RO */
-	PERIPH_VOLT             = 0x2a,
-	PERIPH_VOLT0            = 0x2a,
-
-	/* RO */
-	PERIPH_WATCHDOG         = 0x2b,
-	PERIPH_WATCHDOG0        = 0x2b,
-
-	PERIPH_XO               = 0x2c,
-	PERIPH_XO0              = 0x2c,
-	PERIPH_XO_TIMER         = 0x2d,
-	PERIPH_XO0_TIMER        = 0x2d,
-
-	/* RO */
-	PERIPH_MASTER_MATRIX    = 0x2e,
-	PERIPH_MATRIX           = 0x2f,
-};
-
-typedef void (*pmu_clock_func)(uint32_t periph);
-extern void pmu_clock_en(uint32_t periph);
-extern void pmu_clock_dis(uint32_t periph);
-extern void pmu_peripheral_rst(uint32_t periph);
-extern uint32_t pmu_calibrate_rc_trim(void);
-extern uint32_t pmu_clock_switch_rc_notrim(void);
-extern uint32_t pmu_clock_switch_rc_trim(uint32_t skip_calibration);
-extern uint32_t pmu_clock_switch_xo(void);
-extern void pmu_sleep(void);
-extern void pmu_hibernate(void);
-extern void pmu_hibernate_exit(void);
-extern void pmu_powerdown(void);
-extern void pmu_powerdown_exit(void);
-
-/*
- * enable clock doubler for USB purposes
- */
-void pmu_enable_clock_doubler(void);
-#endif /* __CROS_EC_PMU_H */
diff --git a/chip/g/polling_uart.c b/chip/g/polling_uart.c
deleted file mode 100644
index e28abc2344..0000000000
--- a/chip/g/polling_uart.c
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#include "common.h"
-#include "registers.h"
-#include "uart.h"
-
-#define UART_NCO ((16 * BIT(UART_NCO_WIDTH) *				\
-		   (long long)CONFIG_UART_BAUD_RATE) / PCLK_FREQ)
-
-/* 115200N81 uart0, TX on A0, RX on A1 */
-void uart_init(void)
-{
-	/* Pinmux init also turns on all clocks. */
-	GREG32(PMU, PERICLKSET0) = 0xffffffff;
-	GREG32(PMU, PERICLKSET1) = 0xffffffff;
-
-	/*
-	 * hardwire clocks to some value... just to get going
-	 * Set source of trim to calibration logic during dynamic trim
-	 */
-	GWRITE_FIELD(XO, CLK_TIMER_TRIM_CTRL, RC_COARSE_TRIM_SRC, 0);
-
-	/* Set initial coarse trim value (slowest) */
-	GREG32(XO, CLK_TIMER_RC_COARSE_ATE_TRIM) = 100;
-
-	/* Set initial trim stabilization period */
-	GWRITE_FIELD(XO, CLK_TIMER_TRIM_CTRL, RC_INITIAL_TRIM_PERIOD, 10);
-
-	/* enable trim */
-	GWRITE_FIELD(XO, CLK_TIMER_TRIM_CTRL, RC_TRIM_EN, 1);
-
-	/* domain crossing sync */
-	GREG32(XO, CLK_TIMER_SYNC_CONTENTS) =  0x1;
-
-
-	GREG32(PINMUX, DIOA0_SEL) = GC_PINMUX_UART0_TX_SEL;
-	GREG32(PINMUX, UART0_RX_SEL) = GC_PINMUX_DIOA1_SEL;
-	GREG32(PINMUX, DIOA1_CTL) =
-		GC_PINMUX_DIOA1_CTL_DS_MASK  | GC_PINMUX_DIOA1_CTL_IE_MASK;
-
-	GREG32(PMU, PWRDN_SCRATCH3) = 0xbeefcafe;
-
-	GREG32(UART, FIFO) = 3;  /* clear RX,TX FIFO */
-
-	GREG32(UART, NCO) = UART_NCO;  /* 115200N81 */
-
-	GREG32(UART, CTRL) = 3;  /* TX,RX enable */
-	uart_write_char('\n');
-	uart_write_char('\r');
-}
-
-int uart_tx_ready(void)
-{
-	/*
-	 * This makes sure that transmit FIFO is fully flashed, so that TX
-	 * FIFO is not used.
-	 */
-	return GREAD_FIELD(UART, STATE, TXIDLE);
-}
-
-void uart_tx_flush(void)
-{
-}
-
-int uart_init_done(void)
-{
-	return 1;
-}
-void uart_tx_start(void)
-{
-}
-void uart_tx_stop(void)
-{
-}
-
-void uart_write_char(char c)
-{
-	while (!uart_tx_ready())
-		;
-	GREG32(UART, WDATA) = c;
-}
diff --git a/chip/g/post_reset.c b/chip/g/post_reset.c
deleted file mode 100644
index 323cde05f3..0000000000
--- a/chip/g/post_reset.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-
-#include "config.h"
-#include "board.h"
-#include "console.h"
-#include "endian.h"
-#include "extension.h"
-#include "hooks.h"
-#include "system.h"
-#include "util.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-
-static void post_reset_command_handler(void *body,
-				size_t cmd_size,
-				size_t *response_size)
-{
-	*response_size = 1;
-	((uint8_t *)body)[0] = 0;
-	post_reboot_request();
-}
-DECLARE_EXTENSION_COMMAND(EXTENSION_POST_RESET, post_reset_command_handler);
-
-static void deferred_reset(void)
-{
-	system_reset(SYSTEM_RESET_MANUALLY_TRIGGERED | SYSTEM_RESET_HARD);
-}
-DECLARE_DEFERRED(deferred_reset);
-
-#define MAX_REBOOT_TIMEOUT_MS 1000
-
-static enum vendor_cmd_rc immediate_reset(enum vendor_cmd_cc code,
-					  void *buf,
-					  size_t input_size,
-					  size_t *response_size)
-{
-	uint16_t timeout = 0;
-
-	*response_size = 0;
-	if (input_size) {
-		if (input_size != sizeof(uint16_t)) {
-			CPRINTS("%s: incorrect request size %d",
-				__func__, input_size);
-			return VENDOR_RC_BOGUS_ARGS;
-		}
-
-		/* Retrieve the requested timeout. */
-		memcpy(&timeout, buf, sizeof(timeout));
-		timeout = be16toh(timeout);
-
-		if (timeout > MAX_REBOOT_TIMEOUT_MS) {
-			CPRINTS("%s: incorrect timeout value %d",
-				__func__, timeout);
-			return VENDOR_RC_BOGUS_ARGS;
-		}
-	}
-
-	CPRINTS("%s: rebooting on host's request in %d ms", __func__, timeout);
-	cflush(); /* Let the console drain. */
-
-	if (timeout)
-		hook_call_deferred(&deferred_reset_data, timeout * MSEC);
-	else
-		deferred_reset();
-
-	return VENDOR_RC_SUCCESS;
-}
-DECLARE_VENDOR_COMMAND(VENDOR_CC_IMMEDIATE_RESET, immediate_reset);
diff --git a/chip/g/pre_init.c b/chip/g/pre_init.c
deleted file mode 100644
index 0fe7a7dbe8..0000000000
--- a/chip/g/pre_init.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "board_config.h"
-#include "registers.h"
-
-void chip_pre_init(void)
-{
-	/*
-	 * If we're resuming from deep sleep we need to undo some stuff as soon
-	 * as possible and this is the first init function that's called.
-	 *
-	 * It doesn't hurt anything if this setup is not needed, but we don't
-	 * investigate the reset cause until much later (and doing so is
-	 * destructive), so we'll just do the post-deep-sleep setup every time.
-	 */
-
-	/* Disable the deep sleep triggers */
-	GR_PMU_LOW_POWER_DIS = 0;
-	GR_PMU_EXITPD_MASK = 0;
-
-	/* Unfreeze the USB module */
-	GWRITE_FIELD(USB, PCGCCTL, STOPPCLK, 0);
-	GWRITE_FIELD(USB, PCGCCTL, RSTPDWNMODULE, 0);
-	GWRITE_FIELD(USB, PCGCCTL, PWRCLMP, 0);
-}
diff --git a/chip/g/rbox.c b/chip/g/rbox.c
deleted file mode 100644
index 6aaa0206eb..0000000000
--- a/chip/g/rbox.c
+++ /dev/null
@@ -1,155 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "clock.h"
-#include "ec_commands.h"
-#include "hooks.h"
-#include "rdd.h"
-#include "registers.h"
-#include "system.h"
-#include "timer.h"
-
-
-void rbox_clear_wakeup(void)
-{
-	int i = 0;
-
-	/* Clear the wakeup interrupt */
-	GREG32(RBOX, WAKEUP) = GC_RBOX_WAKEUP_CLEAR_MASK;
-	/*
-	 * Wait until the interrupt status register is cleared, since RBOX runs
-	 * off of RTC instead of the core clock. Wait a max of 50 iterations.
-	 * Experimentally, 15 iterations is usually sufficient. We don't want to
-	 * wait here forever.
-	 */
-	while (GREAD(RBOX, WAKEUP_INTR) && i < 50)
-		i++;
-}
-
-int rbox_powerbtn_is_pressed(void)
-{
-	return !GREAD_FIELD(RBOX, CHECK_OUTPUT, PWRB_OUT);
-}
-
-/*
- * This is 4X as RDD_MAX_WAIT_TIME_COUNTER default value, which should be
- *  long enough for rdd_is_detected() to represent a stable RDD status
- */
-#define RDD_WAIT_TIME		(40 * MSEC)
-
-/*
- * Delay EC_RST_L release if RDD cable is connected, or release EC_RST_L
- * otherwise.
- */
-static void rbox_check_rdd(void)
-{
-#ifdef CR50_DEV
-	print_rdd_state();
-#endif
-	if (rbox_powerbtn_is_pressed() && rdd_is_detected()) {
-		power_button_release_enable_interrupt(1);
-		return;
-	}
-
-	deassert_ec_rst();
-}
-DECLARE_DEFERRED(rbox_check_rdd);
-
-static void rbox_release_ec_reset(void)
-{
-	/* Unfreeze the PINMUX */
-	GREG32(PINMUX, HOLD) = 0;
-
-	/*
-	 * If the board uses closed loop reset, the short EC_RST_L pulse may
-	 * not actually put the system in reset. Don't release EC_RST_L here.
-	 * Let ap_state.c handle it once it sees the system is reset.
-	 *
-	 * Release PINMUX HOLD, so the board can detect changes on TPM_RST_L.
-	 */
-	if (!(system_get_reset_flags() & EC_RESET_FLAG_HIBERNATE) &&
-	    board_uses_closed_loop_reset()) {
-		return;
-	}
-
-	/*
-	 * After a POR, if the power button is held, then delay releasing
-	 * EC_RST_L.
-	 */
-	if ((system_get_reset_flags() & EC_RESET_FLAG_POWER_ON) &&
-	    rbox_powerbtn_is_pressed()) {
-		hook_call_deferred(&rbox_check_rdd_data, RDD_WAIT_TIME);
-		return;
-	}
-
-	/* Allow some time for outputs to stabilize. */
-	usleep(500);
-
-	/* Let the EC go (the RO bootloader asserts it ASAP after POR) */
-	deassert_ec_rst();
-}
-DECLARE_HOOK(HOOK_INIT, rbox_release_ec_reset, HOOK_PRIO_LAST);
-
-static void rbox_init(void)
-{
-	/* Enable RBOX */
-	clock_enable_module(MODULE_RBOX, 1);
-
-	/* Clear any interrupt bits (write 1's to clear) */
-	GREG32(RBOX, INT_STATE) = 0xffffffff;
-
-	/* Clear any wakeup bits */
-	rbox_clear_wakeup();
-
-	/* Disable rbox wakeup. It will be reenabled before entering sleep. */
-	GREG32(RBOX, WAKEUP) = 0;
-
-	/* Override rbox fuses and setup correct behavior */
-	GWRITE(RBOX, DEBUG_CLK10HZ_COUNT, 0x63ff);
-	GWRITE(RBOX, DEBUG_SHORT_DELAY_COUNT, 0x4ff);
-	GWRITE(RBOX, DEBUG_LONG_DELAY_COUNT, 0x31);
-	GWRITE(RBOX, DEBUG_DEBOUNCE, 0x4);
-	GWRITE(RBOX, DEBUG_KEY_COMBO0, 0xC0);
-	GWRITE(RBOX, DEBUG_KEY_COMBO1, 0x0);
-	GWRITE(RBOX, DEBUG_KEY_COMBO2, 0x0);
-	/* DEBUG_BLOCK_OUTPUT value should be 0x7 */
-	GWRITE(RBOX, DEBUG_BLOCK_OUTPUT,
-	       GC_RBOX_DEBUG_BLOCK_OUTPUT_KEY0_SEL_MASK |
-	       GC_RBOX_DEBUG_BLOCK_OUTPUT_KEY1_SEL_MASK |
-	       GC_RBOX_DEBUG_BLOCK_OUTPUT_KEY0_VAL_MASK);
-	/* DEBUG_POL value should be 0x21 */
-	GWRITE(RBOX, DEBUG_POL,
-	       0x1 << GC_RBOX_DEBUG_POL_AC_PRESENT_LSB |
-	       0x0 << GC_RBOX_DEBUG_POL_PWRB_IN_LSB |
-	       0x0 << GC_RBOX_DEBUG_POL_PWRB_OUT_LSB |
-	       0x0 << GC_RBOX_DEBUG_POL_KEY0_IN_LSB |
-	       0x0 << GC_RBOX_DEBUG_POL_KEY0_OUT_LSB |
-	       0x1 << GC_RBOX_DEBUG_POL_KEY1_IN_LSB |
-	       0x0 << GC_RBOX_DEBUG_POL_KEY1_OUT_LSB |
-	       0x0 << GC_RBOX_DEBUG_POL_EC_RST_LSB |
-	       0x0 << GC_RBOX_DEBUG_POL_BATT_DISABLE_LSB);
-	/* DEBUG_TERM value should be 0x1204 */
-	GWRITE(RBOX, DEBUG_TERM,
-	       0x0 << GC_RBOX_DEBUG_TERM_AC_PRESENT_LSB |
-	       0x1 << GC_RBOX_DEBUG_TERM_ENTERING_RW_LSB |
-	       0x0 << GC_RBOX_DEBUG_TERM_PWRB_IN_LSB |
-	       0x0 << GC_RBOX_DEBUG_TERM_PWRB_OUT_LSB |
-	       0x2 << GC_RBOX_DEBUG_TERM_KEY0_IN_LSB |
-	       0x0 << GC_RBOX_DEBUG_TERM_KEY0_OUT_LSB |
-	       0x1 << GC_RBOX_DEBUG_TERM_KEY1_IN_LSB |
-	       0x0 << GC_RBOX_DEBUG_TERM_KEY1_OUT_LSB);
-	/* DEBUG_DRIVE value should be 0x157 */
-	GWRITE(RBOX, DEBUG_DRIVE,
-	       0x3 << GC_RBOX_DEBUG_DRIVE_PWRB_OUT_LSB |
-	       0x1 << GC_RBOX_DEBUG_DRIVE_KEY0_OUT_LSB |
-	       0x1 << GC_RBOX_DEBUG_DRIVE_KEY1_OUT_LSB |
-	       0x1 << GC_RBOX_DEBUG_DRIVE_EC_RST_LSB |
-	       0x1 << GC_RBOX_DEBUG_DRIVE_BATT_DISABLE_LSB);
-	/* FUSE_CTRL value should be 0x3 */
-	GWRITE(RBOX, FUSE_CTRL,
-	       GC_RBOX_FUSE_CTRL_OVERRIDE_FUSE_MASK |
-	       GC_RBOX_FUSE_CTRL_OVERRIDE_FUSE_READY_MASK);
-}
-DECLARE_HOOK(HOOK_INIT, rbox_init, HOOK_PRIO_DEFAULT - 1);
diff --git a/chip/g/rbox.h b/chip/g/rbox.h
deleted file mode 100644
index 5ceeb81953..0000000000
--- a/chip/g/rbox.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_RBOX_H
-#define __CROS_RBOX_H
-
-/**
- * Return true if the power button output shows it is pressed
- */
-int rbox_powerbtn_is_pressed(void);
-
-/**
- * Clear the wakeup interrupts
- */
-void rbox_clear_wakeup(void);
-#endif  /* __CROS_RBOX_H */
diff --git a/chip/g/rdd.c b/chip/g/rdd.c
deleted file mode 100644
index c58dce4806..0000000000
--- a/chip/g/rdd.c
+++ /dev/null
@@ -1,233 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "clock.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "rdd.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "usb_api.h"
-
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
-
-/*
- * The default PROG_DEBUG_STATE_MAP value. Used to tell the to controller send
- * an interrupt when CC1/2 are detected to be in the defined voltage range of a
- * debug accessory.
- */
-#define DETECT_DEBUG 0x420
-
-/*
- * The interrupt only triggers when the debug state is detected.  If we want to
- * trigger an interrupt when the debug state is *not* detected, we need to
- * program the bit-inverse.
- */
-#define DETECT_DISCONNECT (~DETECT_DEBUG & 0xffff)
-
-/* State of RDD CC detection */
-static enum device_state state = DEVICE_STATE_DISCONNECTED;
-
-/* Force detecting a debug accessory (ignore RDD CC detect hardware) */
-static int force_detected;
-
-/*
- * The Rdd state. This is saved in the rdd_interrupt to make sure the state is
- * stable.
- */
-static uint8_t rdd_is_detected_shadow;
-
-/**
- * Get instantaneous cable detect state
- *
- * @return 1 if debug accessory is detected, 0 if not detected
- */
-uint8_t rdd_is_detected(void)
-{
-	return rdd_is_detected_shadow;
-}
-
-void print_rdd_state(void)
-{
-	ccprintf("Rdd:     %s\n",
-		 force_detected ? "keepalive" : device_state_name(state));
-}
-
-/**
- * Handle debug accessory disconnecting
- */
-static void rdd_disconnect(void)
-{
-	CPRINTS("Rdd disconnect");
-	state = DEVICE_STATE_DISCONNECTED;
-
-	/*
-	 * Stop pulling CCD_MODE_L low.  The internal pullup configured in the
-	 * pinmux will pull the signal back high, unless the EC is also pulling
-	 * it low.
-	 *
-	 * This disables the SBUx muxes, if we were the only one driving
-	 * CCD_MODE_L.
-	 */
-	gpio_set_level(GPIO_CCD_MODE_L, 1);
-}
-DECLARE_DEFERRED(rdd_disconnect);
-
-/**
- * Handle debug accessory connecting
- *
- * This can be deferred from both rdd_detect() and the interrupt handler, so
- * it needs to check the current state to determine whether we're already
- * connected.
- */
-static void rdd_connect(void)
-{
-	/* If we were debouncing, we're done, and still connected */
-	if (state == DEVICE_STATE_DEBOUNCING)
-		state = DEVICE_STATE_CONNECTED;
-
-	/* If we're already connected, done */
-	if (state == DEVICE_STATE_CONNECTED)
-		return;
-
-	/* We were previously disconnected, so connect */
-	CPRINTS("Rdd connect");
-	state = DEVICE_STATE_CONNECTED;
-
-	/* Assert CCD_MODE_L to enable the SBUx muxes */
-	gpio_set_level(GPIO_CCD_MODE_L, 0);
-}
-DECLARE_DEFERRED(rdd_connect);
-
-/**
- * Debug accessory detect interrupt
- */
-static void rdd_interrupt(void)
-{
-	uint8_t cc1 = GREAD_FIELD(RDD, INPUT_PIN_VALUES, CC1);
-	uint8_t cc2 = GREAD_FIELD(RDD, INPUT_PIN_VALUES, CC2);
-
-	/* Save the rdd state while the cc lines are stable. */
-	rdd_is_detected_shadow = (cc1 == cc2 && (cc1 == 3 || cc1 == 1));
-
-	/*
-	 * The Rdd detector is level-sensitive with debounce.  That is, it
-	 * samples the RDCCx pin states.  If they're different, it resets the
-	 * wait counter.  If they're the same, it decrements the wait counter.
-	 * Then if the counter is zero, and the state we're looking for matches
-	 * the map, it fires the interrupt.
-	 *
-	 * Note that the counter *remains* zero until the pin states change.
-	 *
-	 * If we want to be able to wake on Rdd change, then interrupts need to
-	 * remain enabled.  Each time we get an interrupt, we'll toggle the map
-	 * we're looking for to the opposite state.  That stops the interrupt
-	 * from continuing to fire on the current state.  When the pins settle
-	 * into a new state, we'll fire the interrupt again.
-	 *
-	 * Even with that, we can still get a double interrupt now and then,
-	 * because the Rdd module runs on a different clock than we do.  So the
-	 * write we do to change the state map may not be picked up until the
-	 * next clock, when the Rdd module has already generated its next
-	 * interrupt based on the old map.  This is harmless, because we're
-	 * unlikely to actually trigger the deferred function twice, and it
-	 * doesn't care if we do anyway because on the second call it'll
-	 * already be in the connected state.
-	 */
-	if (rdd_is_detected()) {
-		/* Accessory detected; toggle to looking for disconnect */
-		GWRITE(RDD, PROG_DEBUG_STATE_MAP, DETECT_DISCONNECT);
-
-		/* Cancel any pending disconnects */
-		hook_call_deferred(&rdd_disconnect_data, -1);
-		/*
-		 * Trigger the deferred handler so that we move back into the
-		 * connected state before our debounce interval expires.
-		 */
-		hook_call_deferred(&rdd_connect_data, 0);
-	} else {
-		/*
-		 * Skip disconnecting Rdd, if rdd is force detected. If Rdd is
-		 * already disconnected, no need to do it again.
-		 */
-		if (!force_detected && state != DEVICE_STATE_DISCONNECTED) {
-			/* Debounce disconnect for 1 second */
-			state = DEVICE_STATE_DEBOUNCING;
-			hook_call_deferred(&rdd_disconnect_data, SECOND);
-		}
-		/* Not detected; toggle to looking for connect. */
-		GWRITE(RDD, PROG_DEBUG_STATE_MAP, DETECT_DEBUG);
-	}
-
-	/* Make sure we stay awake long enough to advance the state machine */
-	delay_sleep_by(1 * SECOND);
-
-	/* Clear the interrupt */
-	GWRITE_FIELD(RDD, INT_STATE, INTR_DEBUG_STATE_DETECTED, 1);
-}
-DECLARE_IRQ(GC_IRQNUM_RDD0_INTR_DEBUG_STATE_DETECTED_INT, rdd_interrupt, 1);
-
-void init_rdd_state(void)
-{
-	/* Enable RDD hardware */
-	clock_enable_module(MODULE_RDD, 1);
-	GWRITE(RDD, POWER_DOWN_B, 1);
-
-	/*
-	 * Note that there is currently (ha, see what I did there) a leakage
-	 * path out of Cr50 into the CC lines.  On some systems, this can cause
-	 * false Rdd detection when the TCPCs are turned off.  This may require
-	 * a software workaround where RDD hardware must be powered down
-	 * whenever the TCPCs are off, and can only be powered up for brief
-	 * periods to do a quick check.  See b/38019839 and b/64582597.
-	 */
-
-	/* Configure to detect accessory connected */
-	GWRITE(RDD, PROG_DEBUG_STATE_MAP, DETECT_DEBUG);
-
-	/*
-	 * Set the 0.4V comparator reference to 0.3V instead.  The voltage is
-	 * marginal near 0.4V for example with VBUS at 4.75V and a SuzyQable See
-	 * b/64847312.
-	 */
-	GWRITE_FIELD(RDD, REF_ADJ, LVL0P4V, 0x2);
-
-	/*
-	 * Enable interrupt for detecting CC.  This minimizes the time before
-	 * we transition to cable-detected at boot, and will cause us to wake
-	 * from deep sleep if a cable is plugged in.
-	 */
-	task_enable_irq(GC_IRQNUM_RDD0_INTR_DEBUG_STATE_DETECTED_INT);
-	GWRITE_FIELD(RDD, INT_STATE, INTR_DEBUG_STATE_DETECTED, 1);
-	GWRITE_FIELD(RDD, INT_ENABLE, INTR_DEBUG_STATE_DETECTED, 1);
-}
-
-static int command_rdd_keepalive(int argc, char **argv)
-{
-	if (argc == 1) {
-		print_rdd_state();
-		return EC_SUCCESS;
-	}
-
-	if (!parse_bool(argv[1], &force_detected))
-		return EC_ERROR_PARAM1;
-
-	if (force_detected) {
-		/* Force Rdd detect */
-		ccprintf("Forcing Rdd detect keepalive\n");
-		hook_call_deferred(&rdd_connect_data, 0);
-	} else {
-		/* Go back to actual hardware state */
-		ccprintf("Using actual Rdd state\n");
-	}
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(rddkeepalive, command_rdd_keepalive,
-			"[BOOLEAN]",
-			"Get Rdd state or force keepalive");
diff --git a/chip/g/rdd.h b/chip/g/rdd.h
deleted file mode 100644
index e30dc0c80f..0000000000
--- a/chip/g/rdd.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_RDD_H
-#define __CROS_RDD_H
-
-/**
- * Initialize RDD module
- */
-void init_rdd_state(void);
-
-/**
- * Print debug accessory detect state
- */
-void print_rdd_state(void);
-
-/**
- * Get instantaneous cable detect state
- *
- * @return 1 if debug accessory is detected, 0 if not detected.
- */
-uint8_t rdd_is_detected(void);
-
-#endif  /* __CROS_RDD_H */
diff --git a/chip/g/registers.h b/chip/g/registers.h
deleted file mode 100644
index e928e01650..0000000000
--- a/chip/g/registers.h
+++ /dev/null
@@ -1,557 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_REGISTERS_H
-#define __CROS_EC_REGISTERS_H
-
-#include "common.h"
-#include "hw_regdefs.h"
-#include "util.h"
-
-/* Constants for setting baud rate */
-#define DEFAULT_UART_FREQ 1000000
-#define UART_NCO_WIDTH 16
-
-/*
- * Added Alias Module Family Base Address to 0-instance Module Base Address
- * Simplify GBASE(mname) macro
- */
-#define GC_MODULE_OFFSET         0x10000
-
-#define GBASE(mname)      \
-	GC_ ## mname ## _BASE_ADDR
-#define GOFFSET(mname, rname)  \
-	GC_ ## mname ## _ ## rname ## _OFFSET
-
-#define GREG8(mname, rname) \
-	REG8(GBASE(mname) + GOFFSET(mname, rname))
-#define GREG32(mname, rname) \
-	REG32(GBASE(mname) + GOFFSET(mname, rname))
-#define GREG32_ADDR(mname, rname) \
-	REG32_ADDR(GBASE(mname) + GOFFSET(mname, rname))
-#define GWRITE(mname, rname, value) (GREG32(mname, rname) = (value))
-#define GREAD(mname, rname)	    GREG32(mname, rname)
-
-#define GFIELD_MASK(mname, rname, fname) \
-	GC_ ## mname ## _ ## rname ## _ ## fname ## _MASK
-
-#define GFIELD_LSB(mname, rname, fname)  \
-	GC_ ## mname ## _ ## rname ## _ ## fname ## _LSB
-
-#define GREAD_FIELD(mname, rname, fname) \
-	((GREG32(mname, rname) & GFIELD_MASK(mname, rname, fname)) \
-		>> GFIELD_LSB(mname, rname, fname))
-
-#define GWRITE_FIELD(mname, rname, fname, fval) \
-	(GREG32(mname, rname) = \
-	((GREG32(mname, rname) & (~GFIELD_MASK(mname, rname, fname))) | \
-	(((fval) << GFIELD_LSB(mname, rname, fname)) & \
-		GFIELD_MASK(mname, rname, fname))))
-
-
-#define GBASE_I(mname, i)     (GBASE(mname) + i*GC_MODULE_OFFSET)
-
-#define GREG32_I(mname, i, rname) \
-		REG32(GBASE_I(mname, i) + GOFFSET(mname, rname))
-
-#define GREG32_ADDR_I(mname, i, rname) \
-		REG32_ADDR(GBASE_I(mname, i) + GOFFSET(mname, rname))
-
-#define GWRITE_I(mname, i, rname, value) (GREG32_I(mname, i, rname) = (value))
-#define GREAD_I(mname, i, rname)	        GREG32_I(mname, i, rname)
-
-#define GREAD_FIELD_I(mname, i, rname, fname) \
-	((GREG32_I(mname, i, rname) & GFIELD_MASK(mname, rname, fname)) \
-		>> GFIELD_LSB(mname, rname, fname))
-
-#define GWRITE_FIELD_I(mname, i, rname, fname, fval) \
-	(GREG32_I(mname, i, rname) = \
-	((GREG32_I(mname, i, rname) & (~GFIELD_MASK(mname, rname, fname))) | \
-	(((fval) << GFIELD_LSB(mname, rname, fname)) & \
-		GFIELD_MASK(mname, rname, fname))))
-
-/* Replace masked bits with val << lsb */
-#define REG_WRITE_MLV(reg, mask, lsb, val) \
-		(reg = ((reg & ~mask) | ((val << lsb) & mask)))
-
-/* Revision registers */
-#define GR_SWDP_BUILD_DATE  \
-	REG32(GC_SWDP0_BASE_ADDR + GC_SWDP_BUILD_DATE_OFFSET)
-#define GR_SWDP_BUILD_TIME  \
-	REG32(GC_SWDP0_BASE_ADDR + GC_SWDP_BUILD_TIME_OFFSET)
-
-/* Power Management Unit */
-#define GR_PMU_REG(off)               REG32(GC_PMU_BASE_ADDR + (off))
-
-#define GR_PMU_RESET                  GR_PMU_REG(GC_PMU_RESET_OFFSET)
-#define GR_PMU_SETRST                 GR_PMU_REG(GC_PMU_SETRST_OFFSET)
-#define GR_PMU_CLRRST                 GR_PMU_REG(GC_PMU_CLRRST_OFFSET)
-#define GR_PMU_RSTSRC                 GR_PMU_REG(GC_PMU_RSTSRC_OFFSET)
-#define GR_PMU_GLOBAL_RESET           GR_PMU_REG(GC_PMU_GLOBAL_RESET_OFFSET)
-#define GR_PMU_LOW_POWER_DIS          GR_PMU_REG(GC_PMU_LOW_POWER_DIS_OFFSET)
-#define GR_PMU_SETDIS                 GR_PMU_REG(GC_PMU_SETDIS_OFFSET)
-#define GR_PMU_CLRDIS                 GR_PMU_REG(GC_PMU_CLRDIS_OFFSET)
-#define GR_PMU_STATDIS                GR_PMU_REG(GC_PMU_STATDIS_OFFSET)
-#define GR_PMU_SETWIC                 GR_PMU_REG(GC_PMU_SETWIC_OFFSET)
-#define GR_PMU_CLRWIC                 GR_PMU_REG(GC_PMU_CLRWIC_OFFSET)
-#define GR_PMU_SYSVTOR                GR_PMU_REG(GC_PMU_SYSVTOR_OFFSET)
-#define GR_PMU_EXCLUSIVE              GR_PMU_REG(GC_PMU_EXCLUSIVE_OFFSET)
-#define GR_PMU_DAP_ID0                GR_PMU_REG(GC_PMU_DAP_ID0_OFFSET)
-#define GR_PMU_DAP_EN                 GR_PMU_REG(GC_PMU_DAP_EN_OFFSET)
-#define GR_PMU_DAP_LOCK               GR_PMU_REG(GC_PMU_DAP_LOCK_OFFSET)
-#define GR_PMU_DAP_UNLOCK             GR_PMU_REG(GC_PMU_DAP_UNLOCK_OFFSET)
-#define GR_PMU_NAP_EN                 GR_PMU_REG(GC_PMU_NAP_EN_OFFSET)
-#define GR_PMU_VREF                   GR_PMU_REG(GC_PMU_VREF_OFFSET)
-#define GR_PMU_VREFCMP                GR_PMU_REG(GC_PMU_VREFCMP_OFFSET)
-#define GR_PMU_RBIAS                  GR_PMU_REG(GC_PMU_RBIAS_OFFSET)
-#define GR_PMU_RBIASLO                GR_PMU_REG(GC_PMU_RBIASLO_OFFSET)
-#define GR_PMU_RBIASHI                GR_PMU_REG(GC_PMU_RBIASHI_OFFSET)
-#define GR_PMU_SETHOLDVREF            GR_PMU_REG(GC_PMU_SETHOLDVREF_OFFSET)
-#define GR_PMU_CLRHOLDVREF            GR_PMU_REG(GC_PMU_CLRHOLDVREF_OFFSET)
-#define GR_PMU_BAT_LVL_OK             GR_PMU_REG(GC_PMU_BAT_LVL_OK_OFFSET)
-#define GR_PMU_B_REG_DIG_CTRL         GR_PMU_REG(GC_PMU_B_REG_DIG_CTRL_OFFSET)
-#define GR_PMU_B_REG_DIG_LATCH_CTRL   GR_PMU_REG(GC_PMU_B_REG_DIG_LATCH_CTRL_OFFSET)
-#define GR_PMU_EXITPD_HOLD_SET        GR_PMU_REG(GC_PMU_EXITPD_HOLD_SET_OFFSET)
-#define GR_PMU_EXITPD_HOLD_CLR        GR_PMU_REG(GC_PMU_EXITPD_HOLD_CLR_OFFSET)
-#define GR_PMU_EXITPD_MASK            GR_PMU_REG(GC_PMU_EXITPD_MASK_OFFSET)
-#define GR_PMU_EXITPD_SRC             GR_PMU_REG(GC_PMU_EXITPD_SRC_OFFSET)
-#define GR_PMU_EXITPD_MON             GR_PMU_REG(GC_PMU_EXITPD_MON_OFFSET)
-#define GR_PMU_OSC_HOLD_SET           GR_PMU_REG(GC_PMU_OSC_HOLD_SET_OFFSET)
-#define GR_PMU_OSC_HOLD_CLR           GR_PMU_REG(GC_PMU_OSC_HOLD_CLR_OFFSET)
-#define GR_PMU_OSC_SELECT             GR_PMU_REG(GC_PMU_OSC_SELECT_OFFSET)
-#define GR_PMU_OSC_SELECT_STAT        GR_PMU_REG(GC_PMU_OSC_SELECT_STAT_OFFSET)
-#define GR_PMU_OSC_CTRL               GR_PMU_REG(GC_PMU_OSC_CTRL_OFFSET)
-#define GR_PMU_MEMCLKSET              GR_PMU_REG(GC_PMU_MEMCLKSET_OFFSET)
-#define GR_PMU_MEMCLKCLR              GR_PMU_REG(GC_PMU_MEMCLKCLR_OFFSET)
-#define GR_PMU_PERICLKSET0            GR_PMU_REG(GC_PMU_PERICLKSET0_OFFSET)
-#define GR_PMU_PERICLKCLR0            GR_PMU_REG(GC_PMU_PERICLKCLR0_OFFSET)
-#define GR_PMU_PERICLKSET1            GR_PMU_REG(GC_PMU_PERICLKSET1_OFFSET)
-#define GR_PMU_PERICLKCLR1            GR_PMU_REG(GC_PMU_PERICLKCLR1_OFFSET)
-#define GR_PMU_PERIGATEONSLEEPSET0    GR_PMU_REG(GC_PMU_PERIGATEONSLEEPSET0_OFFSET)
-#define GR_PMU_PERIGATEONSLEEPCLR0    GR_PMU_REG(GC_PMU_PERIGATEONSLEEPCLR0_OFFSET)
-#define GR_PMU_PERIGATEONSLEEPSET1    GR_PMU_REG(GC_PMU_PERIGATEONSLEEPSET1_OFFSET)
-#define GR_PMU_PERIGATEONSLEEPCLR1    GR_PMU_REG(GC_PMU_PERIGATEONSLEEPCLR1_OFFSET)
-#define GR_PMU_CLK0                   GR_PMU_REG(GC_PMU_CLK0_OFFSET)
-#define GR_PMU_CLK1                   GR_PMU_REG(GC_PMU_CLK1_OFFSET)
-#define GR_PMU_RST0                   GR_PMU_REG(GC_PMU_RST0_OFFSET)
-#define GR_PMU_RST1                   GR_PMU_REG(GC_PMU_RST1_OFFSET)
-#define GR_PMU_PWRDN_SCRATCH_HOLD_SET GR_PMU_REG(GC_PMU_PWRDN_SCRATCH_HOLD_SET_OFFSET)
-#define GR_PMU_PWRDN_SCRATCH_HOLD_CLR GR_PMU_REG(GC_PMU_PWRDN_SCRATCH_HOLD_CLR_OFFSET)
-#define GR_PMU_PWRDN_SCRATCH0         GR_PMU_REG(GC_PMU_PWRDN_SCRATCH0_OFFSET)
-#define GR_PMU_PWRDN_SCRATCH1         GR_PMU_REG(GC_PMU_PWRDN_SCRATCH1_OFFSET)
-#define GR_PMU_PWRDN_SCRATCH2         GR_PMU_REG(GC_PMU_PWRDN_SCRATCH2_OFFSET)
-#define GR_PMU_PWRDN_SCRATCH3         GR_PMU_REG(GC_PMU_PWRDN_SCRATCH3_OFFSET)
-
-#define GR_PMU_FUSE_RD_RC_OSC_26MHZ   GR_PMU_REG(GC_PMU_FUSE_RD_RC_OSC_26MHZ_OFFSET)
-#define GR_PMU_FUSE_RD_XTL_OSC_26MHZ  GR_PMU_REG(GC_PMU_FUSE_RD_XTL_OSC_26MHZ_OFFSET)
-
-/* More than one UART */
-BUILD_ASSERT(GC_UART1_BASE_ADDR - GC_UART0_BASE_ADDR == GC_UART2_BASE_ADDR - GC_UART1_BASE_ADDR);
-#define X_UART_BASE_ADDR_SEP   (GC_UART1_BASE_ADDR - GC_UART0_BASE_ADDR)
-static inline int x_uart_addr(int ch, int offset)
-{
-	return offset + GC_UART0_BASE_ADDR + X_UART_BASE_ADDR_SEP * ch;
-}
-#define X_UARTREG(ch, offset)         REG32(x_uart_addr(ch, offset))
-#define GR_UART_RDATA(ch)             X_UARTREG(ch, GC_UART_RDATA_OFFSET)
-#define GR_UART_WDATA(ch)             X_UARTREG(ch, GC_UART_WDATA_OFFSET)
-#define GR_UART_NCO(ch)               X_UARTREG(ch, GC_UART_NCO_OFFSET)
-#define GR_UART_CTRL(ch)              X_UARTREG(ch, GC_UART_CTRL_OFFSET)
-#define GR_UART_ICTRL(ch)             X_UARTREG(ch, GC_UART_ICTRL_OFFSET)
-#define GR_UART_STATE(ch)             X_UARTREG(ch, GC_UART_STATE_OFFSET)
-#define GR_UART_STATECLR(ch)          X_UARTREG(ch, GC_UART_STATECLR_OFFSET)
-#define GR_UART_ISTATE(ch)            X_UARTREG(ch, GC_UART_ISTATE_OFFSET)
-#define GR_UART_ISTATECLR(ch)         X_UARTREG(ch, GC_UART_ISTATECLR_OFFSET)
-#define GR_UART_FIFO(ch)              X_UARTREG(ch, GC_UART_FIFO_OFFSET)
-#define GR_UART_RFIFO(ch)             X_UARTREG(ch, GC_UART_RFIFO_OFFSET)
-#define GR_UART_VAL(ch)               X_UARTREG(ch, GC_UART_VAL_OFFSET)
-
-/*
- * Our ARM core doesn't have GPIO alternate functions, but it does have a full
- * NxM crossbar called the pinmux, which connects internal peripherals
- * including GPIOs to external pins.
- */
-
-/* Flags to indicate the direction and type of the signal-to-pin connection */
-#define DIO_INPUT               0x0001
-#define DIO_OUTPUT              0x0002
-#define DIO_ENABLE_DIRECT_INPUT 0x0004
-#define DIO_TO_PERIPHERAL       0x0008
-/* Bits to indicate pinmux wake-from-sleep controls */
-#define DIO_WAKE_INV0           0x0010
-#define DIO_WAKE_EDGE0          0x0020
-#define DIO_WAKE_EN0            0x0040
-/* Use these combinations in gpio.inc for clarity */
-#define DIO_WAKE_HIGH           (DIO_WAKE_EN0)
-#define DIO_WAKE_LOW            (DIO_WAKE_EN0 | DIO_WAKE_INV0)
-#define DIO_WAKE_RISING         (DIO_WAKE_EN0 | DIO_WAKE_EDGE0)
-#define DIO_WAKE_FALLING        (DIO_WAKE_EN0 | DIO_WAKE_EDGE0 | DIO_WAKE_INV0)
-/* Flags for pullup/pulldowns */
-#define DIO_PULL_UP             0x0080
-#define DIO_PULL_DOWN           0x0100
-
-/* Generate the MUX selector register address for the DIO */
-#define DIO_SEL_REG(offset) REG32(GC_PINMUX_BASE_ADDR + offset)
-/* Generate the control register address for this MUX */
-#define DIO_CTL_REG(offset) REG32(GC_PINMUX_BASE_ADDR + 0x4 + offset)
-
-/* Map a GPIO <port,bitnum> to a selector value or register */
-#define GET_GPIO_FUNC(port, bitnum) \
-	(GC_PINMUX_GPIO0_GPIO0_SEL + 16 * port + bitnum)
-
-#define GET_GPIO_SEL_REG(port, bitnum) \
-	REG32(GC_PINMUX_BASE_ADDR + \
-	       GC_PINMUX_GPIO0_GPIO0_SEL_OFFSET + 64 * port + 4 * bitnum)
-
-/* Constants for setting MUX control bits (same bits for all DIO pins) */
-#define DIO_CTL_IE_LSB  GC_PINMUX_DIOA0_CTL_IE_LSB
-#define DIO_CTL_IE_MASK GC_PINMUX_DIOA0_CTL_IE_MASK
-#define DIO_CTL_PD_LSB  GC_PINMUX_DIOA0_CTL_PD_LSB
-#define DIO_CTL_PD_MASK GC_PINMUX_DIOA0_CTL_PD_MASK
-#define DIO_CTL_PU_LSB  GC_PINMUX_DIOA0_CTL_PU_LSB
-#define DIO_CTL_PU_MASK GC_PINMUX_DIOA0_CTL_PU_MASK
-
-/* Registers controlling the ARM core GPIOs */
-#define GR_GPIO_REG(n, off)         REG16(GC_GPIO0_BASE_ADDR + (n) * 0x10000 + (off))
-#define GR_GPIO_DATAIN(n)           GR_GPIO_REG(n, GC_GPIO_DATAIN_OFFSET)
-#define GR_GPIO_DOUT(n)             GR_GPIO_REG(n, GC_GPIO_DOUT_OFFSET)
-#define GR_GPIO_SETDOUTEN(n)        GR_GPIO_REG(n, GC_GPIO_SETDOUTEN_OFFSET)
-#define GR_GPIO_CLRDOUTEN(n)        GR_GPIO_REG(n, GC_GPIO_CLRDOUTEN_OFFSET)
-#define GR_GPIO_SETINTEN(n)         GR_GPIO_REG(n, GC_GPIO_SETINTEN_OFFSET)
-#define GR_GPIO_CLRINTEN(n)         GR_GPIO_REG(n, GC_GPIO_CLRINTEN_OFFSET)
-#define GR_GPIO_SETINTTYPE(n)       GR_GPIO_REG(n, GC_GPIO_SETINTTYPE_OFFSET)
-#define GR_GPIO_CLRINTTYPE(n)       GR_GPIO_REG(n, GC_GPIO_CLRINTTYPE_OFFSET)
-#define GR_GPIO_SETINTPOL(n)        GR_GPIO_REG(n, GC_GPIO_SETINTPOL_OFFSET)
-#define GR_GPIO_CLRINTPOL(n)        GR_GPIO_REG(n, GC_GPIO_CLRINTPOL_OFFSET)
-#define GR_GPIO_CLRINTSTAT(n)       GR_GPIO_REG(n, GC_GPIO_CLRINTSTAT_OFFSET)
-
-#define GR_GPIO_MASKLOWBYTE(n, mask)  GR_GPIO_REG(n, GC_GPIO_MASKLOWBYTE_400_OFFSET + (mask) * 4)
-#define GR_GPIO_MASKHIGHBYTE(n, mask) GR_GPIO_REG(n, GC_GPIO_MASKHIGHBYTE_800_OFFSET + (mask) * 4)
-
-/*
- * High-speed timers. Two modules with two timers each; four timers total.
- */
-#define X_TIMEHS_BASE_ADDR_SEP    (GC_TIMEHS1_BASE_ADDR - GC_TIMEHS0_BASE_ADDR)
-#define X_TIMEHSX_TIMER_OFS_SEP   (GC_TIMEHS_TIMER2LOAD_OFFSET - GC_TIMEHS_TIMER1LOAD_OFFSET)
-/* NOTE: module is 0-1, timer is 1-2 */
-static inline int x_timehs_addr(unsigned int module, unsigned int timer,
-				int offset)
-{
-	return GC_TIMEHS0_BASE_ADDR + X_TIMEHS_BASE_ADDR_SEP * module
-		+ GC_TIMEHS_TIMER1LOAD_OFFSET + X_TIMEHSX_TIMER_OFS_SEP * (timer - 1)
-		+ offset;
-}
-/* Per-timer registers */
-#define X_TIMEHSREG(m, t, ofs)        REG32(x_timehs_addr(m, t, ofs))
-#define GR_TIMEHS_LOAD(m, t)          X_TIMEHSREG(m, t, GC_TIMEHS_TIMER1LOAD_OFFSET)
-#define GR_TIMEHS_VALUE(m, t)         X_TIMEHSREG(m, t, GC_TIMEHS_TIMER1VALUE_OFFSET)
-#define GR_TIMEHS_CONTROL(m, t)       X_TIMEHSREG(m, t, GC_TIMEHS_TIMER1CONTROL_OFFSET)
-#define GR_TIMEHS_INTCLR(m, t)        X_TIMEHSREG(m, t, GC_TIMEHS_TIMER1INTCLR_OFFSET)
-#define GR_TIMEHS_RIS(m, t)           X_TIMEHSREG(m, t, GC_TIMEHS_TIMER1RIS_OFFSET)
-#define GR_TIMEHS_MIS(m, t)           X_TIMEHSREG(m, t, GC_TIMEHS_TIMER1MIS_OFFSET)
-#define GR_TIMEHS_BGLOAD(m, t)        X_TIMEHSREG(m, t, GC_TIMEHS_TIMER1BGLOAD_OFFSET)
-
-/* Microsecond timer registers */
-/* NOTE: module is always 0, timer is 0-3 */
-#define GR_TIMEUS_EN(t) REG32(GC_TIMEUS_BASE_ADDR + \
-			      GC_TIMEUS_ENABLE_CNTR##t##_OFFSET)
-#define GR_TIMEUS_ONESHOT_MODE(t) REG32(GC_TIMEUS_BASE_ADDR + \
-					GC_TIMEUS_ONESHOT_MODE_CNTR##t##_OFFSET)
-#define GR_TIMEUS_MAXVAL(t) REG32(GC_TIMEUS_BASE_ADDR + \
-				  GC_TIMEUS_MAXVAL_CNTR##t##_OFFSET)
-#define GR_TIMEUS_PROGVAL(t) REG32(GC_TIMEUS_BASE_ADDR + \
-				   GC_TIMEUS_PROGVAL_CNTR##t##_OFFSET)
-#define GR_TIMEUS_DIVIDER(t) REG32(GC_TIMEUS_BASE_ADDR + \
-				   GC_TIMEUS_DIVIDER_CNTR##t##_OFFSET)
-#define GR_TIMEUS_CUR_MAJOR(t) REG32(GC_TIMEUS_BASE_ADDR + \
-				     GC_TIMEUS_CUR_MAJOR_CNTR##t##_OFFSET)
-#define GR_TIMEUS_CUR_MINOR(t)  REG32(GC_TIMEUS_BASE_ADDR + \
-				      GC_TIMEUS_CUR_MINOR_CNTR##t##_OFFSET)
-
-/* Watchdog */
-#define GR_WDOG_REG(off)              REG32(GC_WATCHDOG0_BASE_ADDR + (off))
-#define GR_WATCHDOG_LOAD              GR_WDOG_REG(GC_WATCHDOG_WDOGLOAD_OFFSET)
-#define GR_WATCHDOG_VALUE             GR_WDOG_REG(GC_WATCHDOG_WDOGVALUE_OFFSET)
-#define GR_WATCHDOG_CTL               GR_WDOG_REG(GC_WATCHDOG_WDOGCONTROL_OFFSET)
-#define GR_WATCHDOG_ICR               GR_WDOG_REG(GC_WATCHDOG_WDOGINTCLR_OFFSET)
-#define GR_WATCHDOG_RIS               GR_WDOG_REG(GC_WATCHDOG_WDOGRIS_OFFSET)
-#define GR_WATCHDOG_LOCK              GR_WDOG_REG(GC_WATCHDOG_WDOGLOCK_OFFSET)
-#define GR_WATCHDOG_ITCR              GR_WDOG_REG(GC_WATCHDOG_WDOGITCR_OFFSET)
-#define GR_WATCHDOG_ITOP              GR_WDOG_REG(GC_WATCHDOG_WDOGITOP_OFFSET)
-
-/* Oscillator */
-#define GR_XO_REG(off)               REG32(GC_XO0_BASE_ADDR + (off))
-#define GR_XO_JTR_JITTERY_TRIM_BANK(n)					\
-	GR_XO_REG(GC_XO_CLK_JTR_JITTERY_TRIM_BANK0_OFFSET + (n) * 4)
-#define GR_XO_OSC_CLKOUT              REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_CLKOUT_OFFSET)
-#define GR_XO_OSC_ADC_CAL_FREQ2X      REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_ADC_CAL_FREQ2X_OFFSET)
-#define GR_XO_OSC_ADC_CAL_FREQ2X_STAT REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_ADC_CAL_FREQ2X_STAT_OFFSET)
-#define GR_XO_OSC_24_48B_SEL          REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_24_48B_SEL_OFFSET)
-#define GR_XO_OSC_TEST                REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_TEST_OFFSET)
-#define GR_XO_OSC_RC_CAL_RSTB         REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_RC_CAL_RSTB_OFFSET)
-#define GR_XO_OSC_RC_CAL_LOAD         REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_RC_CAL_LOAD_OFFSET)
-#define GR_XO_OSC_RC_CAL_START        REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_RC_CAL_START_OFFSET)
-#define GR_XO_OSC_RC_CAL_DONE         REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_RC_CAL_DONE_OFFSET)
-#define GR_XO_OSC_RC_CAL_COUNT        REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_RC_CAL_COUNT_OFFSET)
-#define GR_XO_OSC_RC                  REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_RC_OFFSET)
-#define GR_XO_OSC_RC_STATUS           REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_RC_STATUS_OFFSET)
-#define GR_XO_OSC_XTL_TRIMD           REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_XTL_TRIMD_OFFSET)
-#define GR_XO_OSC_XTL_TRIMG           REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_XTL_TRIMG_OFFSET)
-#define GR_XO_OSC_XTL_CTRL            REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_XTL_CTRL_OFFSET)
-#define GR_XO_OSC_XTL_RC_FLTR         REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_XTL_RC_FLTR_OFFSET)
-#define GR_XO_OSC_XTL_OVRD            REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_XTL_OVRD_OFFSET)
-#define GR_XO_OSC_XTL_OVRD_HOLDB      REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_XTL_OVRD_HOLDB_OFFSET)
-#define GR_XO_OSC_XTL_TRIM            REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_XTL_TRIM_OFFSET)
-#define GR_XO_OSC_XTL_TRIM_STAT       REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_XTL_TRIM_STAT_OFFSET)
-#define GR_XO_OSC_XTL_FSM_EN          REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_XTL_FSM_EN_OFFSET)
-#define GR_XO_OSC_XTL_FSM             REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_XTL_FSM_OFFSET)
-#define GR_XO_OSC_XTL_FSM_CFG         REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_XTL_FSM_CFG_OFFSET)
-#define GR_XO_OSC_SETHOLD             REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_SETHOLD_OFFSET)
-#define GR_XO_OSC_CLRHOLD             REG32(GC_XO0_BASE_ADDR + GC_XO_OSC_CLRHOLD_OFFSET)
-
-/* Fuses (shadowed) */
-#define GR_FUSE(rname) (GREG32(FUSE, rname) & GFIELD_MASK(FUSE, rname, VAL))
-
-/* Key manager */
-#define GR_KEYMGR_AES_KEY(n)     REG32(GREG32_ADDR(KEYMGR, AES_KEY0) + (n))
-#define GR_KEYMGR_AES_CTR(n)     REG32(GREG32_ADDR(KEYMGR, AES_CTR0) + (n))
-#define GR_KEYMGR_GCM_H(n)       REG32(GREG32_ADDR(KEYMGR, GCM_H0) + (n))
-#define GR_KEYMGR_GCM_HASH_IN(n) REG32(GREG32_ADDR(KEYMGR, GCM_HASH_IN0) + (n))
-#define GR_KEYMGR_GCM_MAC(n)     REG32(GREG32_ADDR(KEYMGR, GCM_MAC0) + (n))
-#define GR_KEYMGR_SHA_HASH(n)    REG32(GREG32_ADDR(KEYMGR, SHA_STS_H0) + (n))
-#define GR_KEYMGR_HKEY_FRR(n)    REG32(GREG32_ADDR(KEYMGR, HKEY_FRR0) + (n))
-
-/* USB device controller */
-#define GR_USB_REG(off)               REG32(GC_USB0_BASE_ADDR + (off))
-#define GR_USB_GAHBCFG                GR_USB_REG(GC_USB_GAHBCFG_OFFSET)
-#define GR_USB_GUSBCFG                GR_USB_REG(GC_USB_GUSBCFG_OFFSET)
-#define GR_USB_GRSTCTL                GR_USB_REG(GC_USB_GRSTCTL_OFFSET)
-#define GR_USB_GINTSTS                GR_USB_REG(GC_USB_GINTSTS_OFFSET)
-#define   GINTSTS(bit)                (1 << GC_USB_GINTSTS_ ## bit ## _LSB)
-#define GR_USB_GINTMSK                GR_USB_REG(GC_USB_GINTMSK_OFFSET)
-#define   GINTMSK(bit)                (1 << GC_USB_GINTMSK_ ## bit ## MSK_LSB)
-#define GR_USB_GRXSTSR                GR_USB_REG(GC_USB_GRXSTSR_OFFSET)
-#define GR_USB_GRXSTSP                GR_USB_REG(GC_USB_GRXSTSP_OFFSET)
-#define GR_USB_GRXFSIZ                GR_USB_REG(GC_USB_GRXFSIZ_OFFSET)
-#define GR_USB_GNPTXFSIZ              GR_USB_REG(GC_USB_GNPTXFSIZ_OFFSET)
-#define GR_USB_GGPIO                  GR_USB_REG(GC_USB_GGPIO_OFFSET)
-#define GR_USB_GSNPSID                GR_USB_REG(GC_USB_GSNPSID_OFFSET)
-#define GR_USB_GHWCFG1                GR_USB_REG(GC_USB_GHWCFG1_OFFSET)
-#define GR_USB_GHWCFG2                GR_USB_REG(GC_USB_GHWCFG2_OFFSET)
-#define GR_USB_GHWCFG3                GR_USB_REG(GC_USB_GHWCFG3_OFFSET)
-#define GR_USB_GHWCFG4                GR_USB_REG(GC_USB_GHWCFG4_OFFSET)
-#define GR_USB_GDFIFOCFG              GR_USB_REG(GC_USB_GDFIFOCFG_OFFSET)
-#define GR_USB_DIEPTXF(n)             GR_USB_REG(GC_USB_DIEPTXF1_OFFSET - 4 + (n)*4)
-#define GR_USB_DCFG                   GR_USB_REG(GC_USB_DCFG_OFFSET)
-#define GR_USB_DCTL                   GR_USB_REG(GC_USB_DCTL_OFFSET)
-#define GR_USB_DSTS                   GR_USB_REG(GC_USB_DSTS_OFFSET)
-#define GR_USB_DIEPMSK                GR_USB_REG(GC_USB_DIEPMSK_OFFSET)
-#define GR_USB_DOEPMSK                GR_USB_REG(GC_USB_DOEPMSK_OFFSET)
-#define GR_USB_DAINT                  GR_USB_REG(GC_USB_DAINT_OFFSET)
-#define GR_USB_DAINTMSK               GR_USB_REG(GC_USB_DAINTMSK_OFFSET)
-#define  DAINT_INEP(ep)               (1 << (ep + GC_USB_DAINTMSK_INEPMSK0_LSB))
-#define  DAINT_OUTEP(ep)              (1 << (ep + GC_USB_DAINTMSK_OUTEPMSK0_LSB))
-#define GR_USB_DTHRCTL                GR_USB_REG(GC_USB_DTHRCTL_OFFSET)
-#define GR_USB_DIEPEMPMSK             GR_USB_REG(GC_USB_DIEPEMPMSK_OFFSET)
-
-#define GR_USB_EPIREG(off, n)         GR_USB_REG(0x900 + (n) * 0x20 + (off))
-#define GR_USB_EPOREG(off, n)         GR_USB_REG(0xb00 + (n) * 0x20 + (off))
-#define GR_USB_DIEPCTL(n)             GR_USB_EPIREG(0x00, n)
-#define GR_USB_DIEPINT(n)             GR_USB_EPIREG(0x08, n)
-#define GR_USB_DIEPTSIZ(n)            GR_USB_EPIREG(0x10, n)
-#define GR_USB_DIEPDMA(n)             GR_USB_EPIREG(0x14, n)
-#define GR_USB_DTXFSTS(n)             GR_USB_EPIREG(0x18, n)
-#define GR_USB_DIEPDMAB(n)            GR_USB_EPIREG(0x1c, n)
-#define GR_USB_DOEPCTL(n)             GR_USB_EPOREG(0x00, n)
-#define GR_USB_DOEPINT(n)             GR_USB_EPOREG(0x08, n)
-#define GR_USB_DOEPTSIZ(n)            GR_USB_EPOREG(0x10, n)
-#define GR_USB_DOEPDMA(n)             GR_USB_EPOREG(0x14, n)
-#define GR_USB_DOEPDMAB(n)            GR_USB_EPOREG(0x1c, n)
-
-/*
- * GR_USB_GGPIO is a portal to a set of custom 8-bit registers. Logically it is
- * split into a GP_OUT part and a GP_IN part. Writing to a custom register can
- * be done in a single operation, with all data transferred in GP_OUT. Reading
- * requires a GP_OUT write to select the register to read, then a read or GP_IN
- * to see what the register holds.
- *   GP_OUT:
- *    bit  15     direction: 1=write, 0=read
- *    bits 11:4   value to write to register when bit 15 is set
- *    bits 3:0    custom register to access
- *   GP_IN:
- *    bits 7:0    value read back from register when GP_OUT[15] is clear
- *
- * The GP_OUT bit fields aren't defined elsewhere, so we'll define them here
- */
-#define GP_OUT(v) (GC_USB_GGPIO_GPO_MASK & ((v) << GC_USB_GGPIO_GPO_LSB))
-#define GP_IN(v) (GC_USB_GGPIO_GPI_MASK & ((v) << GC_USB_GGPIO_GPI_LSB))
-#define GGPIO_WRITE(reg, val) GP_OUT((BIT(15) |	      /* write bit */ \
-				      (((val) & 0xFF) << 4) | /* value */ \
-				      ((reg) & 0x0F)))	      /* register */
-#define GGPIO_READ(reg) GP_OUT((reg) & 0x0F)		      /* register */
-
-/* Further, the custom config registers for the USB module are: */
-#define USB_CUSTOM_CFG_REG    0			/* register number */
-#define  USB_PHY_ACTIVE  0x04			/* bit 2 */
-#define  USB_TESTMODE    0x02			/* bit 1 */
-#define  USB_SEL_PHY0    0x00			/* bit 0 */
-#define  USB_SEL_PHY1    0x01			/* bit 0 */
-#define USB_IDLE_PHY_CTRL_REG 1			/* register number */
-#define  USB_FS_SUSPENDB    BIT(7)
-#define  USB_FS_EDGE_SEL    BIT(6)
-#define  USB_DM_PULLUP_EN   BIT(5)
-#define  USB_DP_RPU2_ENB    BIT(4)
-#define  USB_DP_RPU1_ENB    BIT(3)
-#define  USB_TX_OEB         BIT(2)
-#define  USB_TX_DPO         BIT(1)
-#define  USB_TX_DMO         BIT(0)
-
-#define GAHBCFG_DMA_EN                BIT(GC_USB_GAHBCFG_DMAEN_LSB)
-#define GAHBCFG_GLB_INTR_EN           BIT(GC_USB_GAHBCFG_GLBLINTRMSK_LSB)
-#define GAHBCFG_HBSTLEN_INCR4         (3 << GC_USB_GAHBCFG_HBSTLEN_LSB)
-#define GAHBCFG_NP_TXF_EMP_LVL        (1 <<  GC_USB_GAHBCFG_NPTXFEMPLVL_LSB)
-
-#define GUSBCFG_TOUTCAL(n)            (((n) << GC_USB_GUSBCFG_TOUTCAL_LSB) \
-				       & GC_USB_GUSBCFG_TOUTCAL_MASK)
-#define GUSBCFG_USBTRDTIM(n)          (((n) << GC_USB_GUSBCFG_USBTRDTIM_LSB) \
-				       & GC_USB_GUSBCFG_USBTRDTIM_MASK)
-#define GUSBCFG_PHYSEL_HS             (0 << GC_USB_GUSBCFG_PHYSEL_LSB)
-#define GUSBCFG_PHYSEL_FS             BIT(GC_USB_GUSBCFG_PHYSEL_LSB)
-#define GUSBCFG_FSINTF_6PIN           (0 << GC_USB_GUSBCFG_FSINTF_LSB)
-#define GUSBCFG_FSINTF_3PIN           BIT(GC_USB_GUSBCFG_FSINTF_LSB)
-#define GUSBCFG_PHYIF16               BIT(GC_USB_GUSBCFG_PHYIF_LSB)
-#define GUSBCFG_PHYIF8                (0 << GC_USB_GUSBCFG_PHYIF_LSB)
-#define GUSBCFG_ULPI                  BIT(GC_USB_GUSBCFG_ULPI_UTMI_SEL_LSB)
-#define GUSBCFG_UTMI                  (0 << GC_USB_GUSBCFG_ULPI_UTMI_SEL_LSB)
-
-#define GRSTCTL_CSFTRST               BIT(GC_USB_GRSTCTL_CSFTRST_LSB)
-#define GRSTCTL_AHBIDLE               BIT(GC_USB_GRSTCTL_AHBIDLE_LSB)
-#define GRSTCTL_TXFFLSH               BIT(GC_USB_GRSTCTL_TXFFLSH_LSB)
-#define GRSTCTL_RXFFLSH               BIT(GC_USB_GRSTCTL_RXFFLSH_LSB)
-#define GRSTCTL_TXFNUM(n)             (((n) << GC_USB_GRSTCTL_TXFNUM_LSB) & GC_USB_GRSTCTL_TXFNUM_MASK)
-
-#define DCFG_DEVSPD_FS                BIT(GC_USB_DCFG_DEVSPD_LSB)
-#define DCFG_DEVSPD_FS48              (3 << GC_USB_DCFG_DEVSPD_LSB)
-#define DCFG_DEVADDR(a)               (((a) << GC_USB_DCFG_DEVADDR_LSB) & GC_USB_DCFG_DEVADDR_MASK)
-#define DCFG_DESCDMA                  BIT(GC_USB_DCFG_DESCDMA_LSB)
-
-#define DCTL_SFTDISCON                BIT(GC_USB_DCTL_SFTDISCON_LSB)
-#define DCTL_CGOUTNAK                 BIT(GC_USB_DCTL_CGOUTNAK_LSB)
-#define DCTL_CGNPINNAK                BIT(GC_USB_DCTL_CGNPINNAK_LSB)
-#define DCTL_PWRONPRGDONE             BIT(GC_USB_DCTL_PWRONPRGDONE_LSB)
-
-/* Device Endpoint Common IN Interrupt Mask bits */
-#define DIEPMSK_AHBERRMSK             BIT(GC_USB_DIEPMSK_AHBERRMSK_LSB)
-#define DIEPMSK_BNAININTRMSK          BIT(GC_USB_DIEPMSK_BNAININTRMSK_LSB)
-#define DIEPMSK_EPDISBLDMSK           BIT(GC_USB_DIEPMSK_EPDISBLDMSK_LSB)
-#define DIEPMSK_INEPNAKEFFMSK         BIT(GC_USB_DIEPMSK_INEPNAKEFFMSK_LSB)
-#define DIEPMSK_INTKNEPMISMSK         BIT(GC_USB_DIEPMSK_INTKNEPMISMSK_LSB)
-#define DIEPMSK_INTKNTXFEMPMSK        BIT(GC_USB_DIEPMSK_INTKNTXFEMPMSK_LSB)
-#define DIEPMSK_NAKMSK                BIT(GC_USB_DIEPMSK_NAKMSK_LSB)
-#define DIEPMSK_TIMEOUTMSK            BIT(GC_USB_DIEPMSK_TIMEOUTMSK_LSB)
-#define DIEPMSK_TXFIFOUNDRNMSK        BIT(GC_USB_DIEPMSK_TXFIFOUNDRNMSK_LSB)
-#define DIEPMSK_XFERCOMPLMSK          BIT(GC_USB_DIEPMSK_XFERCOMPLMSK_LSB)
-
-/* Device Endpoint Common OUT Interrupt Mask bits */
-#define DOEPMSK_AHBERRMSK             BIT(GC_USB_DOEPMSK_AHBERRMSK_LSB)
-#define DOEPMSK_BBLEERRMSK            BIT(GC_USB_DOEPMSK_BBLEERRMSK_LSB)
-#define DOEPMSK_BNAOUTINTRMSK         BIT(GC_USB_DOEPMSK_BNAOUTINTRMSK_LSB)
-#define DOEPMSK_EPDISBLDMSK           BIT(GC_USB_DOEPMSK_EPDISBLDMSK_LSB)
-#define DOEPMSK_NAKMSK                BIT(GC_USB_DOEPMSK_NAKMSK_LSB)
-#define DOEPMSK_NYETMSK               BIT(GC_USB_DOEPMSK_NYETMSK_LSB)
-#define DOEPMSK_OUTPKTERRMSK          BIT(GC_USB_DOEPMSK_OUTPKTERRMSK_LSB)
-#define DOEPMSK_OUTTKNEPDISMSK        BIT(GC_USB_DOEPMSK_OUTTKNEPDISMSK_LSB)
-#define DOEPMSK_SETUPMSK              BIT(GC_USB_DOEPMSK_SETUPMSK_LSB)
-#define DOEPMSK_STSPHSERCVDMSK        BIT(GC_USB_DOEPMSK_STSPHSERCVDMSK_LSB)
-#define DOEPMSK_XFERCOMPLMSK          BIT(GC_USB_DOEPMSK_XFERCOMPLMSK_LSB)
-
-/* Device Endpoint-n IN Interrupt Register bits */
-#define DIEPINT_AHBERR             BIT(GC_USB_DIEPINT0_AHBERR_LSB)
-#define DIEPINT_BBLEERR            BIT(GC_USB_DIEPINT0_BBLEERR_LSB)
-#define DIEPINT_BNAINTR            BIT(GC_USB_DIEPINT0_BNAINTR_LSB)
-#define DIEPINT_EPDISBLD           BIT(GC_USB_DIEPINT0_EPDISBLD_LSB)
-#define DIEPINT_INEPNAKEFF         BIT(GC_USB_DIEPINT0_INEPNAKEFF_LSB)
-#define DIEPINT_INTKNEPMIS         BIT(GC_USB_DIEPINT0_INTKNEPMIS_LSB)
-#define DIEPINT_INTKNTXFEMP        BIT(GC_USB_DIEPINT0_INTKNTXFEMP_LSB)
-#define DIEPINT_NAKINTRPT          BIT(GC_USB_DIEPINT0_NAKINTRPT_LSB)
-#define DIEPINT_NYETINTRPT         BIT(GC_USB_DIEPINT0_NYETINTRPT_LSB)
-#define DIEPINT_PKTDRPSTS          BIT(GC_USB_DIEPINT0_PKTDRPSTS_LSB)
-#define DIEPINT_TIMEOUT            BIT(GC_USB_DIEPINT0_TIMEOUT_LSB)
-#define DIEPINT_TXFEMP             BIT(GC_USB_DIEPINT0_TXFEMP_LSB)
-#define DIEPINT_TXFIFOUNDRN        BIT(GC_USB_DIEPINT0_TXFIFOUNDRN_LSB)
-#define DIEPINT_XFERCOMPL          BIT(GC_USB_DIEPINT0_XFERCOMPL_LSB)
-
-/* Device Endpoint-n OUT Interrupt Register bits */
-#define DOEPINT_AHBERR             BIT(GC_USB_DOEPINT0_AHBERR_LSB)
-#define DOEPINT_BACK2BACKSETUP     BIT(GC_USB_DOEPINT0_BACK2BACKSETUP_LSB)
-#define DOEPINT_BBLEERR            BIT(GC_USB_DOEPINT0_BBLEERR_LSB)
-#define DOEPINT_BNAINTR            BIT(GC_USB_DOEPINT0_BNAINTR_LSB)
-#define DOEPINT_EPDISBLD           BIT(GC_USB_DOEPINT0_EPDISBLD_LSB)
-#define DOEPINT_NAKINTRPT          BIT(GC_USB_DOEPINT0_NAKINTRPT_LSB)
-#define DOEPINT_NYETINTRPT         BIT(GC_USB_DOEPINT0_NYETINTRPT_LSB)
-#define DOEPINT_OUTPKTERR          BIT(GC_USB_DOEPINT0_OUTPKTERR_LSB)
-#define DOEPINT_OUTTKNEPDIS        BIT(GC_USB_DOEPINT0_OUTTKNEPDIS_LSB)
-#define DOEPINT_PKTDRPSTS          BIT(GC_USB_DOEPINT0_PKTDRPSTS_LSB)
-#define DOEPINT_SETUP              BIT(GC_USB_DOEPINT0_SETUP_LSB)
-#define DOEPINT_STSPHSERCVD        BIT(GC_USB_DOEPINT0_STSPHSERCVD_LSB)
-#define DOEPINT_STUPPKTRCVD        BIT(GC_USB_DOEPINT0_STUPPKTRCVD_LSB)
-#define DOEPINT_XFERCOMPL          BIT(GC_USB_DOEPINT0_XFERCOMPL_LSB)
-
-#define DXEPCTL_EPTYPE_CTRL           (0 << GC_USB_DIEPCTL0_EPTYPE_LSB)
-#define DXEPCTL_EPTYPE_ISO            (1 << GC_USB_DIEPCTL0_EPTYPE_LSB)
-#define DXEPCTL_EPTYPE_BULK           (2 << GC_USB_DIEPCTL0_EPTYPE_LSB)
-#define DXEPCTL_EPTYPE_INT            (3 << GC_USB_DIEPCTL0_EPTYPE_LSB)
-#define DXEPCTL_EPTYPE_MASK           GC_USB_DIEPCTL0_EPTYPE_MASK
-#define DXEPCTL_TXFNUM(n)             ((n) << GC_USB_DIEPCTL1_TXFNUM_LSB)
-#define DXEPCTL_STALL                 BIT(GC_USB_DIEPCTL0_STALL_LSB)
-#define DXEPCTL_CNAK                  BIT(GC_USB_DIEPCTL0_CNAK_LSB)
-#define DXEPCTL_DPID                  BIT(GC_USB_DIEPCTL1_DPID_LSB)
-#define DXEPCTL_SNAK                  BIT(GC_USB_DIEPCTL0_SNAK_LSB)
-#define DXEPCTL_NAKSTS                BIT(GC_USB_DIEPCTL0_NAKSTS_LSB)
-#define DXEPCTL_EPENA                 BIT(GC_USB_DIEPCTL0_EPENA_LSB)
-#define DXEPCTL_EPDIS                 BIT(GC_USB_DIEPCTL0_EPDIS_LSB)
-#define DXEPCTL_USBACTEP              BIT(GC_USB_DIEPCTL0_USBACTEP_LSB)
-#define DXEPCTL_MPS64                 (0 << GC_USB_DIEPCTL0_MPS_LSB)
-#define DXEPCTL_MPS(cnt)              ((cnt) << GC_USB_DIEPCTL1_MPS_LSB)
-#define DXEPCTL_SET_D0PID             BIT(28)
-#define DXEPCTL_SET_D1PID             BIT(29)
-
-#define DXEPTSIZ_SUPCNT(n)            ((n) << GC_USB_DOEPTSIZ0_SUPCNT_LSB)
-#define DXEPTSIZ_PKTCNT(n)            ((n) << GC_USB_DIEPTSIZ0_PKTCNT_LSB)
-#define DXEPTSIZ_XFERSIZE(n)          ((n) << GC_USB_DIEPTSIZ0_XFERSIZE_LSB)
-
-#define DOEPDMA_BS_HOST_RDY           (0 << 30)
-#define DOEPDMA_BS_DMA_BSY            (1 << 30)
-#define DOEPDMA_BS_DMA_DONE           (2 << 30)
-#define DOEPDMA_BS_HOST_BSY           (3 << 30)
-#define DOEPDMA_BS_MASK               (3 << 30)
-#define DOEPDMA_RXSTS_MASK            (3 << 28)
-#define DOEPDMA_LAST                  BIT(27)
-#define DOEPDMA_SP                    BIT(26)
-#define DOEPDMA_IOC                   BIT(25)
-#define DOEPDMA_SR                    BIT(24)
-#define DOEPDMA_MTRF                  BIT(23)
-#define DOEPDMA_NAK                   BIT(16)
-#define DOEPDMA_RXBYTES(n)            (((n) & 0xFFFF) << 0)
-#define DOEPDMA_RXBYTES_MASK          (0xFFFF << 0)
-
-#define DIEPDMA_BS_HOST_RDY           (0 << 30)
-#define DIEPDMA_BS_DMA_BSY            (1 << 30)
-#define DIEPDMA_BS_DMA_DONE           (2 << 30)
-#define DIEPDMA_BS_HOST_BSY           (3 << 30)
-#define DIEPDMA_BS_MASK               (3 << 30)
-#define DIEPDMA_TXSTS_MASK            (3 << 28)
-#define DIEPDMA_LAST                  BIT(27)
-#define DIEPDMA_SP                    BIT(26)
-#define DIEPDMA_IOC                   BIT(25)
-#define DIEPDMA_TXBYTES(n)            (((n) & 0xFFFF) << 0)
-#define DIEPDMA_TXBYTES_MASK          (0xFFFF << 0)
-
-struct g_usb_desc {
-	uint32_t flags;
-	void *addr;
-};
-
-#endif	/* __CROS_EC_REGISTERS_H */
diff --git a/chip/g/runlevel.c b/chip/g/runlevel.c
deleted file mode 100644
index 13e215e3de..0000000000
--- a/chip/g/runlevel.c
+++ /dev/null
@@ -1,49 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "init_chip.h"
-#include "registers.h"
-
-/* Drop run level to at least medium. */
-void init_runlevel(const enum permission_level desired_level)
-{
-	volatile uint32_t *const reg_addrs[] = {
-		/* CPU's use of the system peripheral bus */
-		GREG32_ADDR(GLOBALSEC, CPU0_S_PERMISSION),
-		/* CPU's use of the system bus via the debug access port */
-		GREG32_ADDR(GLOBALSEC, CPU0_S_DAP_PERMISSION),
-		/* DMA's use of the system peripheral bus */
-		GREG32_ADDR(GLOBALSEC, DDMA0_PERMISSION),
-		/*
-		 * Current software level affects which (if any) scratch
-		 * registers can be used for a warm boot hardware-verified
-		 * jump.
-		 */
-		GREG32_ADDR(GLOBALSEC, SOFTWARE_LVL),
-	};
-	int i;
-
-	/* Permission registers drop by 1 level (e.g. HIGHEST -> HIGH)
-	 * each time a write is encountered (the value written does
-	 * not matter).  So we repeat writes and reads, until the
-	 * desired level is reached.
-	 */
-	for (i = 0; i < ARRAY_SIZE(reg_addrs); i++) {
-		uint32_t current_level;
-
-		while (1) {
-			current_level = *reg_addrs[i];
-			if (current_level <= desired_level)
-				break;
-			*reg_addrs[i] = desired_level;
-		}
-	}
-}
-
-int runlevel_is_high(void)
-{
-	return ((GREAD(GLOBALSEC, CPU0_S_PERMISSION) == PERMISSION_HIGH) ||
-		(GREAD(GLOBALSEC, CPU0_S_PERMISSION) == PERMISSION_HIGHEST));
-}
diff --git a/chip/g/signed_header.h b/chip/g/signed_header.h
deleted file mode 100644
index 6096350a54..0000000000
--- a/chip/g/signed_header.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#ifndef __CROS_EC_SIGNED_HEADER_H
-#define __CROS_EC_SIGNED_HEADER_H
-
-#include "compile_time_macros.h"
-#include "stdint.h"
-
-#define FUSE_PADDING 0x55555555  /* baked in hw! */
-#define FUSE_IGNORE 0xa3badaac   /* baked in rom! */
-#define FUSE_MAX 128             /* baked in rom! */
-
-#define INFO_MAX 128             /* baked in rom! */
-#define INFO_IGNORE 0xaa3c55c3   /* baked in rom! */
-
-/* Default value for _pad[] words */
-#define SIGNED_HEADER_PADDING 0x33333333
-
-struct SignedHeader {
-	uint32_t magic;       /* -1 (thanks, boot_sys!) */
-	uint32_t signature[96];
-	uint32_t img_chk_;    /* top 32 bit of expected img_hash */
-	/* --------------------- everything below is part of img_hash */
-	uint32_t tag[7];      /* words 0-6 of RWR/FWR */
-	uint32_t keyid;       /* word 7 of RWR */
-	uint32_t key[96];     /* public key to verify signature with */
-	uint32_t image_size;
-	uint32_t ro_base;     /* readonly region */
-	uint32_t ro_max;
-	uint32_t rx_base;     /* executable region */
-	uint32_t rx_max;
-	uint32_t fusemap[FUSE_MAX / (8 * sizeof(uint32_t))];
-	uint32_t infomap[INFO_MAX / (8 * sizeof(uint32_t))];
-	uint32_t epoch_;      /* word 7 of FWR */
-	uint32_t major_;      /* keyladder count */
-	uint32_t minor_;
-	uint64_t timestamp_;  /* time of signing */
-	uint32_t p4cl_;
-	/* bits to and with FUSE_FW_DEFINED_BROM_APPLYSEC */
-	uint32_t applysec_;
-	/* bits to mesh with FUSE_FW_DEFINED_BROM_CONFIG1 */
-	uint32_t config1_;
-	/* bits to or with FUSE_FW_DEFINED_BROM_ERR_RESPONSE */
-	uint32_t err_response_;
-	/* action to take when expectation is violated */
-	uint32_t expect_response_;
-
-	union {
-		// 2nd FIPS signature (gnubby RW / Cr51)
-		struct {
-			uint32_t keyid;
-			uint32_t r[8];
-			uint32_t s[8];
-		} ext_sig;
-
-		// FLASH trim override (Dauntless RO)
-		// iff config1_ & 65536
-		struct {
-			uint32_t FSH_SMW_SETTING_OPTION3;
-			uint32_t FSH_SMW_SETTING_OPTION2;
-			uint32_t FSH_SMW_SETTING_OPTIONA;
-			uint32_t FSH_SMW_SETTING_OPTIONB;
-			uint32_t FSH_SMW_SMP_WHV_OPTION1;
-			uint32_t FSH_SMW_SMP_WHV_OPTION0;
-			uint32_t FSH_SMW_SME_WHV_OPTION1;
-			uint32_t FSH_SMW_SME_WHV_OPTION0;
-		} fsh;
-	} u;
-
-	/* Padding to bring the total structure size to 1K. */
-	uint32_t _pad[5];
-	struct {
-		unsigned size:12;
-		unsigned offset:20;
-	} swap_mark;
-
-	/* Field for managing updates between RW product families. */
-	uint32_t rw_product_family_;
-	/* Board ID type, mask, flags (stored ^SIGNED_HEADER_PADDING) */
-	uint32_t board_id_type;
-	uint32_t board_id_type_mask;
-	uint32_t board_id_flags;
-	uint32_t dev_id0_;    /* node id, if locked */
-	uint32_t dev_id1_;
-	uint32_t fuses_chk_;  /* top 32 bit of expected fuses hash */
-	uint32_t info_chk_;   /* top 32 bit of expected info hash */
-};
-
-BUILD_ASSERT(sizeof(struct SignedHeader) == 1024);
-BUILD_ASSERT(offsetof(struct SignedHeader, info_chk_) == 1020);
-#define TOP_IMAGE_SIZE_BIT (1 <<			\
-	    (sizeof(((struct SignedHeader *)0)->image_size) * 8 - 1))
-
-/*
- * It is a mere convention, but all prod keys are required to have key IDs
- * such, that bit D2 is set, and all dev keys are required to have key IDs
- * such, that bit D2 is not set.
- *
- * This convention is enforced at the key generation time.
- */
-#define G_SIGNED_FOR_PROD(h) ((h)->keyid & BIT(2))
-
-
-#endif /* __CROS_EC_SIGNED_HEADER_H */
diff --git a/chip/g/sn_bits.c b/chip/g/sn_bits.c
deleted file mode 100644
index 6783133d52..0000000000
--- a/chip/g/sn_bits.c
+++ /dev/null
@@ -1,269 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "board_id.h"
-#include "board_space.h"
-#include "console.h"
-#include "extension.h"
-#include "flash_info.h"
-#include "util.h"
-#include "wp.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
-
-int read_sn_data(struct sn_data *sn)
-{
-	uint32_t *id_p;
-	int i;
-
-	/*
-	 * SN Bits structure size is guaranteed to be divisible by 4, and it
-	 * is guaranteed to be aligned at 4 bytes.
-	 */
-
-	id_p = (uint32_t *)sn;
-
-	for (i = 0; i < sizeof(*sn); i += sizeof(uint32_t)) {
-		int rv;
-
-		rv = flash_physical_info_read_word
-			(INFO_SN_DATA_OFFSET + i, id_p);
-		if (rv != EC_SUCCESS) {
-			CPRINTF("%s: failed to read word %d, error %d\n",
-				__func__, i, rv);
-			return rv;
-		}
-		id_p++;
-	}
-	return EC_SUCCESS;
-}
-
-static int write_sn_data(struct sn_data *sn_data, int header_only)
-{
-	int rv = EC_SUCCESS;
-
-	/* Enable write access */
-	flash_info_write_enable();
-
-	/* Write sn bits */
-	rv = flash_info_physical_write(INFO_SN_DATA_OFFSET,
-				       header_only ?
-				       SN_HEADER_SIZE : sizeof(*sn_data),
-				       (const char *)sn_data);
-	if (rv != EC_SUCCESS)
-		CPRINTS("%s: write failed", __func__);
-
-	/* Disable write access */
-	flash_info_write_disable();
-
-	return rv;
-}
-
-/**
- * Initialize SN data space in flash INFO1, and write sn hash. This can only
- * be called once per device; subsequent calls on a device that has already
- * had the sn hash written will fail.
- *
- * @param id	Pointer to a SN  structure to copy into INFO1
- *
- * @return EC_SUCCESS or an error code in cases of various failures to read or
- *		if the space has been already initialized.
- */
-static int write_sn_hash(const uint32_t sn_hash[3])
-{
-	int rv = EC_ERROR_PARAM_COUNT;
-	int i;
-	struct sn_data sn_data;
-
-	rv = read_sn_data(&sn_data);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	/* Check the sn data space is currently uninitialized */
-	for (i = 0; i < (sizeof(sn_data) / sizeof(uint32_t)); i++)
-		if (((uint32_t *) &sn_data)[i] != 0xffffffff)
-			return EC_ERROR_INVALID_CONFIG;
-
-	sn_data.version = SN_DATA_VERSION;
-	memcpy(sn_data.sn_hash, sn_hash, sizeof(sn_data.sn_hash));
-
-	rv = write_sn_data(&sn_data, 0);
-
-	return rv;
-}
-
-static int increment_rma_count(uint8_t inc)
-{
-	int rv = EC_ERROR_PARAM_COUNT;
-	struct sn_data sn_data;
-
-	rv = read_sn_data(&sn_data);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	/* Make sure we know how to update this data */
-	if (sn_data.version != SN_DATA_VERSION)
-		return EC_ERROR_INVALID_CONFIG;
-
-	/* Don't allow incrementing more than the number of bits */
-	if (inc > RMA_COUNT_BITS)
-		return EC_ERROR_INVAL;
-
-	/*
-	 * The RMA status is initially set to 0xff. We set bit 7
-	 * to 0 to indicate the device has been RMA'd at least once,
-	 * and use the remaining bits as a count of how many times
-	 * the device has been RMA'd. The number of 0s represents
-	 * the number of RMAs. As there are only 7 bits available
-	 * for the count, a value of 0x00 means the device has
-	 * been RMA'd at least 7 times (but we do not know how many).
-	 *
-	 * We allow incrementing by 0 or n (rather than 0 or 1) so
-	 * that a device in any state can be put into the RMA'd with
-	 * unknown count (0x00) state with a single call to this
-	 * function.
-	 */
-	sn_data.rma_status <<= inc;
-	sn_data.rma_status &= RMA_INDICATOR;
-
-	rv = write_sn_data(&sn_data, 1);
-
-	return rv;
-}
-
-static enum vendor_cmd_rc vc_sn_set_hash(enum vendor_cmd_cc code,
-					 void *buf,
-					 size_t input_size,
-					 size_t *response_size)
-{
-	struct board_id bid;
-	uint32_t sn_hash[3];
-	uint8_t *pbuf = buf;
-
-	*response_size = 1;
-
-	if (input_size != sizeof(sn_hash)) {
-		*pbuf = VENDOR_RC_BOGUS_ARGS;
-		return VENDOR_RC_BOGUS_ARGS;
-	}
-
-	/*
-	 * Only allow writing sn bits if we can successfully verify
-	 * that the board ID type has not been writen yet.
-	 */
-	if (read_board_id(&bid) != EC_SUCCESS ||
-	    !board_id_type_is_blank(&bid)) {
-		*pbuf = EC_ERROR_ACCESS_DENIED;
-		return VENDOR_RC_NOT_ALLOWED;
-	}
-
-	memcpy(&sn_hash, pbuf, sizeof(sn_hash));
-
-	/* We care about the LSB only. */
-	*pbuf = (uint8_t) write_sn_hash(sn_hash);
-
-	return *pbuf;
-}
-DECLARE_VENDOR_COMMAND(VENDOR_CC_SN_SET_HASH, vc_sn_set_hash);
-
-static enum vendor_cmd_rc vc_sn_inc_rma(enum vendor_cmd_cc code,
-					void *buf,
-					size_t input_size,
-					size_t *response_size)
-{
-	uint8_t *pbuf = buf;
-
-	if (wp_is_asserted())
-		return EC_ERROR_ACCESS_DENIED;
-
-	*response_size = 1;
-
-	if (input_size != sizeof(*pbuf)) {
-		*pbuf = VENDOR_RC_BOGUS_ARGS;
-		return VENDOR_RC_BOGUS_ARGS;
-	}
-
-	/* We care about the LSB only. */
-	*pbuf = (uint8_t) increment_rma_count(*pbuf);
-
-	return *pbuf;
-}
-DECLARE_VENDOR_COMMAND(VENDOR_CC_SN_INC_RMA, vc_sn_inc_rma);
-
-static int command_sn(int argc, char **argv)
-{
-	int rv = EC_ERROR_PARAM_COUNT;
-	struct sn_data sn;
-
-	switch (argc) {
-#ifdef CR50_DEV
-	case 4:
-	{
-		char *e;
-
-		sn.sn_hash[0] = strtoi(argv[1], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM1;
-
-		sn.sn_hash[1] = strtoi(argv[2], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM2;
-
-		sn.sn_hash[2] = strtoi(argv[3], &e, 0);
-		if (*e)
-			return EC_ERROR_PARAM3;
-
-		rv = write_sn_hash(sn.sn_hash);
-		if (rv != EC_SUCCESS)
-			return rv;
-
-		goto print_sn_data;
-	}
-	case 3:
-	{
-		int count;
-		char *e;
-
-		if (strcasecmp(argv[1], "rmainc") != 0)
-			return EC_ERROR_PARAM1;
-
-		count = strtoi(argv[2], &e, 0);
-		if (*e || count > 7)
-			return EC_ERROR_PARAM2;
-
-		rv = increment_rma_count(count);
-		if (rv != EC_SUCCESS)
-			return rv;
-	}
-	/* fall through */
-print_sn_data:
-#endif
-	case 1:
-		rv = read_sn_data(&sn);
-		if (rv == EC_SUCCESS)
-			CPRINTF("Version: %02x\n"
-				"RMA: %02x\n"
-				"SN: %08x %08x %08x\n",
-				sn.version, sn.rma_status,
-				sn.sn_hash[0], sn.sn_hash[1], sn.sn_hash[2]);
-
-		break;
-	default:
-		rv = EC_ERROR_PARAM_COUNT;
-	}
-
-	return rv;
-}
-DECLARE_SAFE_CONSOLE_COMMAND(sn,
-			     command_sn, ""
-#ifdef CR50_DEV
-			     "[(sn0 sn1 sn2) | (rmainc n)]"
-#endif
-			     , "Get"
-#ifdef CR50_DEV
-			     "/Set"
-#endif
-			     " Serial Number Data");
diff --git a/chip/g/sn_bits.h b/chip/g/sn_bits.h
deleted file mode 100644
index 547ac1b938..0000000000
--- a/chip/g/sn_bits.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __EC_CHIP_G_SN_BITS_H
-#define __EC_CHIP_G_SN_BITS_H
-
-#include "board_space.h"
-
-/**
- * Reads the SN data from the flash INFO1 space.
- *
- * @param id    Pointer to a sn_data structure to fill
- *
- * @return      EC_SUCCESS or an error code in case of failure.
- */
-int read_sn_data(struct sn_data *sn);
-
-#endif  /* ! __EC_CHIP_G_SN_BITS_H */
diff --git a/chip/g/spi_master.c b/chip/g/spi_master.c
deleted file mode 100644
index 96acfa4315..0000000000
--- a/chip/g/spi_master.c
+++ /dev/null
@@ -1,264 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "registers.h"
-#include "spi.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-
-#ifdef CONFIG_STREAM_SIGNATURE
-#include "signing.h"
-#endif
-
-/* Not defined in the hardware register spec, the RX and TX buffers are 128B. */
-#define SPI_BUF_SIZE 0x80
-
-/* This timeout should allow a full buffer transaction at the lowest SPI speed
- * by using the largest uint8_t clock divider of 256 (~235kHz). */
-#define SPI_TRANSACTION_TIMEOUT_USEC (5 * MSEC)
-
-/* There are two SPI masters or ports on this chip. */
-#define SPI_NUM_PORTS 2
-
-static struct mutex spi_mutex[SPI_NUM_PORTS];
-static enum spi_clock_mode clock_mode[SPI_NUM_PORTS];
-
-/* The Cr50 SPI master is not DMA auto-fill/drain capable, so async and flush
- * are not defined on purpose. */
-int spi_transaction(const struct spi_device_t *spi_device,
-		    const uint8_t *txdata, int txlen,
-		    uint8_t *rxdata, int rxlen)
-{
-	int port = spi_device->port;
-	int rv = EC_SUCCESS;
-	timestamp_t timeout;
-	int transaction_size = 0;
-	int rxoffset = 0;
-
-	/* If SPI0's passthrough is enabled, SPI0 is not available unless the
-	 * SPS's BUSY bit is set. */
-	if (port == 0) {
-		if (GREAD_FIELD_I(SPI, port, CTRL, ENPASSTHRU) &&
-		    !GREAD(SPS, EEPROM_BUSY_STATUS))
-			return EC_ERROR_BUSY;
-	}
-
-	if (rxlen == SPI_READBACK_ALL) {
-		/* Bidirectional SPI sends and receives a bit for each clock.
-		 * We'll need to make sure the buffers for RX and TX are equal
-		 * and return a bit received for every bit sent.
-		 */
-		if (txlen > SPI_BUF_SIZE)
-			return EC_ERROR_INVAL;
-		rxlen = txlen;
-		transaction_size = txlen;
-		rxoffset = 0;
-	} else {
-		/* Ensure it'll fit inside of the RX and TX buffers. Note that
-		 * although the buffers are separate, the total transmission
-		 * size must fit in the rx buffer.
-		 */
-		if (txlen + rxlen > SPI_BUF_SIZE)
-			return EC_ERROR_INVAL;
-		transaction_size = rxlen + txlen;
-		rxoffset = txlen;
-	}
-
-	/* Grab the port's mutex. */
-	mutex_lock(&spi_mutex[port]);
-
-#ifdef CONFIG_STREAM_SIGNATURE
-	/*
-	 * This hook allows mn50 to sniff data written to target
-	 * manufactured H1 devices.
-	 */
-	sig_append(stream_spiflash, txdata, txlen);
-#endif
-
-	/* Copy the txdata into the 128B Transmit Buffer. */
-	memmove((uint8_t *)GREG32_ADDR_I(SPI, port, TX_DATA), txdata, txlen);
-
-#ifndef CONFIG_SPI_MASTER_NO_CS_GPIOS
-	/* Drive chip select low. */
-	gpio_set_level(spi_device->gpio_cs, 0);
-#endif  /* CONFIG_SPI_MASTER_NO_CS_GPIOS */
-
-	/* Initiate the transaction. */
-	GWRITE_FIELD_I(SPI, port, ISTATE_CLR, TXDONE, 1);
-	GWRITE_FIELD_I(SPI, port, XACT, SIZE, transaction_size - 1);
-	GWRITE_FIELD_I(SPI, port, XACT, START, 1);
-
-	/* Wait for the SPI master to finish the transaction. */
-	timeout.val = get_time().val + SPI_TRANSACTION_TIMEOUT_USEC;
-	while (!GREAD_FIELD_I(SPI, port, ISTATE, TXDONE)) {
-		/* Give up if the deadline has been exceeded. */
-		if (get_time().val > timeout.val) {
-			/* Might have been pre-empted by other task.
-			 * Check ISTATE.TXDONE again for legit timeout.
-			 */
-			if (GREAD_FIELD_I(SPI, port, ISTATE, TXDONE))
-				break;
-			rv = EC_ERROR_TIMEOUT;
-			goto err_cs_high;
-		}
-	}
-	GWRITE_FIELD_I(SPI, port, ISTATE_CLR, TXDONE, 1);
-
-	/* Copy the result. */
-	memmove(rxdata,
-		&((uint8_t *)GREG32_ADDR_I(SPI, port, RX_DATA))[rxoffset],
-		rxlen);
-
-err_cs_high:
-#ifndef CONFIG_SPI_MASTER_NO_CS_GPIOS
-	/* Drive chip select high. */
-	gpio_set_level(spi_device->gpio_cs, 1);
-#endif  /* CONFIG_SPI_MASTER_NO_CS_GPIOS */
-
-	/* Release the port's mutex. */
-	mutex_unlock(&spi_mutex[port]);
-	return rv;
-}
-
-/*
- * Configure the SPI port's clock mode. The SPI port must be re-enabled after
- * changing the clocking mode.
- */
-void set_spi_clock_mode(int port, enum spi_clock_mode mode)
-{
-	clock_mode[port] = mode;
-}
-
-/*
- * Configure the SPI0 master's passthrough mode. Note:
- * 1) This must be called after the SPI port is enabled.
- * 2) Passthrough cannot be safely disabled while the SPI slave port is active
- *    and the SPI slave port's status register's BUSY bit is not set.
- */
-void configure_spi0_passthrough(int enable)
-{
-	int port = 0;
-
-	/* Grab the port's mutex. */
-	mutex_lock(&spi_mutex[port]);
-
-	GWRITE_FIELD_I(SPI, port, CTRL, ENPASSTHRU, enable);
-
-	/* Release the port's mutex. */
-	mutex_unlock(&spi_mutex[port]);
-}
-
-int spi_enable(int port, int enable)
-{
-	int i;
-
-	if (enable) {
-		int spi_device_found = 0;
-		uint8_t max_div = 0;
-
-#ifndef CONFIG_SPI_MASTER_NO_CS_GPIOS
-		gpio_config_module(MODULE_SPI, 1);
-#endif  /* CONFIG_SPI_MASTER_NO_CS_GPIOS */
-		for (i = 0; i < spi_devices_used; i++) {
-			if (spi_devices[i].port != port)
-				continue;
-
-			spi_device_found = 1;
-
-#ifndef CONFIG_SPI_MASTER_NO_CS_GPIOS
-			/* Deassert CS# */
-			gpio_set_flags(spi_devices[i].gpio_cs, GPIO_OUTPUT);
-			gpio_set_level(spi_devices[i].gpio_cs, 1);
-#endif  /* CONFIG_SPI_MASTER_NO_CS_GPIOS */
-
-			/* Find the port's largest DIV (lowest frequency). */
-			if (spi_devices[i].div > max_div)
-				max_div = spi_devices[i].div;
-		}
-
-		/* Ensure there is at least one device behind the SPI port. */
-		if (!spi_device_found)
-			return EC_ERROR_INVAL;
-
-		/* configure the SPI clock mode */
-		GWRITE_FIELD_I(SPI, port, CTRL, CPOL,
-			       (clock_mode[port] == SPI_CLOCK_MODE2) ||
-			       (clock_mode[port] == SPI_CLOCK_MODE3));
-		GWRITE_FIELD_I(SPI, port, CTRL, CPHA,
-			       (clock_mode[port] == SPI_CLOCK_MODE1) ||
-			       (clock_mode[port] == SPI_CLOCK_MODE3));
-
-		/* Enforce the default setup and hold times. */
-		GWRITE_FIELD_I(SPI, port, CTRL, CSBSU, 0);
-		GWRITE_FIELD_I(SPI, port, CTRL, CSBHLD, 0);
-
-		/* Set the clock divider, where freq / (div + 1). */
-		GWRITE_FIELD_I(SPI, port, CTRL, IDIV, max_div);
-
-		/* Master's CS is active low. */
-		GWRITE_FIELD_I(SPI, port, CTRL, CSBPOL, 0);
-
-		/* Byte 0 bit 7 is first in each double word in the buffers. */
-		GWRITE_FIELD_I(SPI, port, CTRL, TXBITOR, 1);
-		GWRITE_FIELD_I(SPI, port, CTRL, TXBYTOR, 0);
-		GWRITE_FIELD_I(SPI, port, CTRL, RXBITOR, 1);
-		GWRITE_FIELD_I(SPI, port, CTRL, RXBYTOR, 0);
-
-		/* Disable passthrough by default. */
-		if (port == 0)
-			configure_spi0_passthrough(0);
-
-		/* Disable the TXDONE interrupt, we'll busy poll instead. */
-		GWRITE_FIELD_I(SPI, port, ICTRL, TXDONE, 0);
-
-	} else {
-		for (i = 0; i < spi_devices_used; i++) {
-			if (spi_devices[i].port != port)
-				continue;
-
-#ifndef CONFIG_SPI_MASTER_NO_CS_GPIOS
-			/* Make sure CS# is deasserted and disabled. */
-			gpio_set_level(spi_devices[i].gpio_cs, 1);
-			gpio_set_flags(spi_devices[i].gpio_cs, GPIO_ODR_HIGH);
-#endif  /* CONFIG_SPI_MASTER_NO_CS_GPIOS */
-		}
-
-		/* Disable passthrough. */
-		if (port == 0)
-			configure_spi0_passthrough(0);
-
-		gpio_config_module(MODULE_SPI, 1);
-	}
-
-	return EC_SUCCESS;
-}
-
-/******************************************************************************/
-/* Hooks */
-
-static void spi_init(void)
-{
-	size_t i;
-
-#ifdef CONFIG_SPI_MASTER_CONFIGURE_GPIOS
-	/* Set SPI_MISO as an input */
-	GWRITE_FIELD(PINMUX, DIOA11_CTL, IE, 1); /* SPI_MISO */
-#endif
-
-	for (i = 0; i < SPI_NUM_PORTS; i++) {
-		/* Configure the SPI ports to default to mode0. */
-		set_spi_clock_mode(i, SPI_CLOCK_MODE0);
-
-		/* Ensure the SPI ports are disabled to prevent us from
-		 * interfering with the main chipset when we're not explicitly
-		 * using the SPI bus. */
-		spi_enable(i, 0);
-	}
-}
-DECLARE_HOOK(HOOK_INIT, spi_init, HOOK_PRIO_DEFAULT);
diff --git a/chip/g/spi_master.h b/chip/g/spi_master.h
deleted file mode 100644
index 42441886f8..0000000000
--- a/chip/g/spi_master.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_INCLUDE_SPI_MASTER_H
-#define __CROS_EC_INCLUDE_SPI_MASTER_H
-
-#include "spi.h"
-
-void configure_spi0_passthrough(int enable);
-void set_spi_clock_mode(int port, enum spi_clock_mode mode);
-
-#endif
diff --git a/chip/g/sps.c b/chip/g/sps.c
deleted file mode 100644
index 5fd6735dd8..0000000000
--- a/chip/g/sps.c
+++ /dev/null
@@ -1,561 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "pmu.h"
-#include "registers.h"
-#include "sps.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "watchdog.h"
-
-/*
- * This file is a driver for the CR50 SPS (SPI slave) controller. The
- * controller deploys a 2KB buffer split evenly between receive and transmit
- * directions.
- *
- * Each one kilobyte of memory is organized into a FIFO with read
- * and write pointers. RX FIFO write and TX FIFO read pointers are managed by
- * hardware. RX FIFO read and TX FIFO write pointers are managed by
- * software.
- *
- * As of time of writing, TX fifo allows only 32 bit wide write accesses,
- * which makes the function feeding the FIFO unnecessarily complicated.
- *
- * Even though both FIFOs are 1KByte in size, the hardware pointers
- * controlling access to the FIFOs are 11 bits in size, this is another issue
- * requiring special software handling.
- *
- * The driver API includes three functions:
- *
- * - transmit a packet of a certain size, runs on the task context and can
- *   exit before the entire packet is transmitted.,
- *
- * - register a receive callback. The callback is running in interrupt
- *   context. Registering the callback (re)initializes the interface.
- *
- * - unregister receive callback.
- */
-
-/*
- * Hardware pointers use one extra bit, which means that indexing FIFO and
- * values written into the pointers have to have different sizes. Tracked under
- * http://b/20894690
- */
-#define SPS_FIFO_PTR_MASK	((SPS_FIFO_MASK << 1) | 1)
-
-#define SPS_TX_FIFO_BASE_ADDR (GBASE(SPS) + 0x1000)
-#define SPS_RX_FIFO_BASE_ADDR (SPS_TX_FIFO_BASE_ADDR + SPS_FIFO_SIZE)
-
-/* SPS Statistic Counters */
-static uint32_t sps_tx_count, sps_rx_count, tx_empty_count, max_rx_batch;
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_SPS, outstr)
-#define CPRINTS(format, args...) cprints(CC_SPS, format, ## args)
-
-/* Flag indicating if there has been any data received while CS was asserted. */
-static uint8_t seen_data;
-
-void sps_tx_status(uint8_t byte)
-{
-	GREG32(SPS, DUMMY_WORD) = byte;
-}
-
-/*
- * Push data to the SPS TX FIFO
- * @param data Pointer to 8-bit data
- * @param data_size Number of bytes to transmit
- * @return : actual number of bytes placed into tx fifo
- */
-int sps_transmit(uint8_t *data, size_t data_size)
-{
-	volatile uint32_t *sps_tx_fifo;
-	uint32_t rptr;
-	uint32_t wptr;
-	uint32_t fifo_room;
-	int bytes_sent;
-	int inst = 0;
-
-	if (GREAD_FIELD_I(SPS, inst, ISTATE, TXFIFO_EMPTY))
-		tx_empty_count++; /* Inside packet this means underrun. */
-
-	sps_tx_fifo = (volatile uint32_t *)SPS_TX_FIFO_BASE_ADDR;
-
-	wptr = GREG32_I(SPS, inst, TXFIFO_WPTR);
-	rptr = GREG32_I(SPS, inst, TXFIFO_RPTR);
-	fifo_room = (rptr - wptr - 1) & SPS_FIFO_MASK;
-
-	if (fifo_room < data_size) {
-		bytes_sent = fifo_room;
-		data_size = fifo_room;
-	} else {
-		bytes_sent = data_size;
-	}
-
-	sps_tx_fifo += (wptr & SPS_FIFO_MASK) / sizeof(*sps_tx_fifo);
-
-	while (data_size) {
-
-		if ((wptr & 3) || (data_size < 4) || ((uintptr_t)data & 3)) {
-			/*
-			 * Either we have less then 4 bytes to send, or one of
-			 * the pointers is not 4 byte aligned. Need to go byte
-			 * by byte.
-			 */
-			uint32_t fifo_contents;
-			int bit_shift;
-
-			fifo_contents = *sps_tx_fifo;
-			do {
-				/*
-				 * CR50 SPS controller does not allow byte
-				 * accesses for writes into the FIFO, so read
-				 * modify/write is required. Tracked under
-				 * http://b/20894727
-				 */
-				bit_shift = 8 * (wptr & 3);
-				fifo_contents &= ~(0xff << bit_shift);
-				fifo_contents |=
-					(((uint32_t)(*data++)) << bit_shift);
-				data_size--;
-				wptr++;
-
-			} while (data_size && (wptr & 3));
-
-			*sps_tx_fifo++ = fifo_contents;
-		} else {
-			/*
-			 * Both fifo wptr and data are aligned and there is
-			 * plenty to send.
-			 */
-			*sps_tx_fifo++ = *((uint32_t *)data);
-			data += 4;
-			data_size -= 4;
-			wptr += 4;
-		}
-		GREG32_I(SPS, inst, TXFIFO_WPTR) = wptr & SPS_FIFO_PTR_MASK;
-
-		/* Make sure FIFO pointer wraps along with the index. */
-		if (!(wptr & SPS_FIFO_MASK))
-			sps_tx_fifo = (volatile uint32_t *)
-				SPS_TX_FIFO_BASE_ADDR;
-	}
-
-	/*
-	 * Start TX if necessary. This happens after FIFO is primed, which
-	 * helps alleviate TX underrun problems but introduces delay before
-	 * data starts coming out.
-	 */
-	if (!GREAD_FIELD(SPS, FIFO_CTRL, TXFIFO_EN))
-		GWRITE_FIELD(SPS, FIFO_CTRL, TXFIFO_EN, 1);
-
-	sps_tx_count += bytes_sent;
-	return bytes_sent;
-}
-
-static int sps_cs_asserted(void)
-{
-	/*
-	 * Read the current value on the SPS CS line and return the iversion
-	 * of it (CS is active low).
-	 */
-	return !GREAD_FIELD(SPS, VAL, CSB);
-}
-
-/** Configure the data transmission format
- *
- *  @param mode Clock polarity and phase mode (0 - 3)
- *
- */
-static void sps_configure(enum sps_mode mode, enum spi_clock_mode clk_mode,
-			  unsigned rx_fifo_threshold)
-{
-	/* Disable All Interrupts */
-	GREG32(SPS, ICTRL) = 0;
-
-	GWRITE_FIELD(SPS, CTRL, MODE, mode);
-	GWRITE_FIELD(SPS, CTRL, IDLE_LVL, 0);
-	GWRITE_FIELD(SPS, CTRL, CPHA, clk_mode & 1);
-	GWRITE_FIELD(SPS, CTRL, CPOL, (clk_mode >> 1) & 1);
-	GWRITE_FIELD(SPS, CTRL, TXBITOR, 1); /* MSB first */
-	GWRITE_FIELD(SPS, CTRL, RXBITOR, 1); /* MSB first */
-	/* xfer 0xff when tx fifo is empty */
-	GREG32(SPS, DUMMY_WORD) = GC_SPS_DUMMY_WORD_DEFAULT;
-
-	/* [5,4,3]           [2,1,0]
-	 * RX{DIS, EN, RST} TX{DIS, EN, RST}
-	 */
-	GREG32(SPS, FIFO_CTRL) = 0x9;
-
-	/* wait for reset to self clear. */
-	while (GREG32(SPS, FIFO_CTRL) & 9)
-		;
-
-	/* Do not enable TX FIFO until we have something to send. */
-	GWRITE_FIELD(SPS, FIFO_CTRL, RXFIFO_EN, 1);
-
-	GREG32(SPS, RXFIFO_THRESHOLD) = rx_fifo_threshold;
-
-	GWRITE_FIELD(SPS, ICTRL, RXFIFO_LVL, 1);
-
-	seen_data = 0;
-
-	/* Use CS_DEASSERT to retrieve all remaining bytes from RX FIFO. */
-	GWRITE_FIELD(SPS, ISTATE_CLR, CS_DEASSERT, 1);
-	GWRITE_FIELD(SPS, ICTRL, CS_DEASSERT, 1);
-}
-
-/*
- * Register and unregister rx_handler. Side effects of registering the handler
- * is reinitializing the interface.
- */
-static rx_handler_f sps_rx_handler;
-
-int sps_register_rx_handler(enum sps_mode mode, rx_handler_f rx_handler,
-			    unsigned rx_fifo_threshold)
-{
-	task_disable_irq(GC_IRQNUM_SPS0_RXFIFO_LVL_INTR);
-	task_disable_irq(GC_IRQNUM_SPS0_CS_DEASSERT_INTR);
-
-	if (!rx_handler)
-		return 0;
-
-	if (!rx_fifo_threshold)
-		rx_fifo_threshold = 8;  /* This is a sensible default. */
-	sps_rx_handler = rx_handler;
-
-	sps_configure(mode, SPI_CLOCK_MODE0, rx_fifo_threshold);
-	task_enable_irq(GC_IRQNUM_SPS0_RXFIFO_LVL_INTR);
-	task_enable_irq(GC_IRQNUM_SPS0_CS_DEASSERT_INTR);
-
-	return 0;
-}
-
-static void sps_init(void)
-{
-	/*
-	 * Check to see if slave SPI interface is required by the board before
-	 * initializing it. If SPI option is not set, then just return.
-	 */
-	if (!board_tpm_uses_spi())
-		return;
-
-	pmu_clock_en(PERIPH_SPS);
-
-	/* The pinmux connections are preset, but we have to set IN/OUT */
-	GWRITE_FIELD(PINMUX, DIOA2_CTL, IE, 1);	 /* SPS_MOSI */
-	GWRITE_FIELD(PINMUX, DIOA6_CTL, IE, 1);	 /* SPS_CLK */
-	GWRITE_FIELD(PINMUX, DIOA10_CTL, IE, 0); /* SPS_MISO */
-	GWRITE_FIELD(PINMUX, DIOA12_CTL, IE, 1); /* SPS_CS_L */
-
-	/* Allow SPS_CS_L to wake from sleep */
-	GWRITE_FIELD(PINMUX, EXITEN0, DIOA12, 1);   /* enable powerdown exit */
-	GWRITE_FIELD(PINMUX, EXITEDGE0, DIOA12, 1); /* edge sensitive */
-	GWRITE_FIELD(PINMUX, EXITINV0, DIOA12, 1);  /* wake on low */
-}
-DECLARE_HOOK(HOOK_INIT, sps_init, HOOK_PRIO_DEFAULT);
-
-
-
-/*****************************************************************************/
-/* Interrupt handler stuff */
-
-/*
- * Check how much data is available in RX FIFO and return pointer to the
- * available data and its size.
- *
- * @param inst Interface number
- * @param data - pointer to set to the beginning of data in the fifo
- * @return number of available bytes and the sets the pointer if number of
- *         bytes is non zero
- */
-static int sps_check_rx(uint32_t inst, uint8_t **data)
-{
-	uint32_t write_ptr = GREG32_I(SPS, inst, RXFIFO_WPTR) & SPS_FIFO_MASK;
-	uint32_t read_ptr = GREG32_I(SPS, inst, RXFIFO_RPTR) & SPS_FIFO_MASK;
-
-	if (read_ptr == write_ptr)
-		return 0;
-
-	*data = (uint8_t *)(SPS_RX_FIFO_BASE_ADDR + read_ptr);
-
-	if (read_ptr > write_ptr)
-		return SPS_FIFO_SIZE - read_ptr;
-
-	return write_ptr - read_ptr;
-}
-
-/* Advance RX FIFO read pointer after data has been read from the FIFO. */
-static void sps_advance_rx(int port, int data_size)
-{
-	uint32_t read_ptr = GREG32_I(SPS, port, RXFIFO_RPTR) + data_size;
-
-	GREG32_I(SPS, port, RXFIFO_RPTR) = read_ptr & SPS_FIFO_PTR_MASK;
-}
-
-/*
- * Actual receive interrupt processing function. Invokes the callback passing
- * it a pointer to the linear space in the RX FIFO and the number of bytes
- * available at that address.
- *
- * If RX fifo is wrapping around, the callback will be called twice with two
- * flat pointers.
- *
- * If the CS has been deasserted, after all remaining RX FIFO data has been
- * passed to the callback, the callback is called one last time with zero data
- * size and the CS indication, this allows the client to delineate received
- * packets.
- */
-static void sps_rx_interrupt(uint32_t port, int cs_deasserted)
-{
-	for (;;) {
-		uint8_t *received_data = NULL;
-		size_t data_size;
-
-		data_size = sps_check_rx(port, &received_data);
-		if (!data_size)
-			break;
-
-		seen_data = 1;
-		sps_rx_count += data_size;
-
-		if (sps_rx_handler)
-			sps_rx_handler(received_data, data_size, 0);
-
-		if (data_size > max_rx_batch)
-			max_rx_batch = data_size;
-
-		sps_advance_rx(port, data_size);
-	}
-
-	if (cs_deasserted) {
-		if (seen_data) {
-			sps_rx_handler(NULL, 0, 1);
-
-			/*
-			 * Signal the AP that this SPI frame processing is
-			 * completed.
-			 */
-			gpio_set_level(GPIO_INT_AP_L, 0);
-			gpio_set_level(GPIO_INT_AP_L, 1);
-			seen_data = 0;
-		}
-	}
-}
-
-static void sps_cs_deassert_interrupt(uint32_t port)
-{
-	if (sps_cs_asserted()) {
-		/*
-		 * we must have been slow, this is the next CS assertion after
-		 * the 'wake up' pulse, but we have not processed the wake up
-		 * interrupt yet.
-		 *
-		 * There would be no other out of order CS assertions, as all
-		 * the 'real' ones (as opposed to the wake up pulses) are
-		 * confirmed by the H1 pulsing the AP interrupt line
-		 */
-
-		/*
-		 * Make sure we react to the next deassertion when it
-		 * happens.
-		 */
-		GWRITE_FIELD(SPS, ISTATE_CLR, CS_DEASSERT, 1);
-		GWRITE_FIELD(SPS, FIFO_CTRL, TXFIFO_EN, 0);
-		if (sps_cs_asserted())
-			return;
-
-		/*
-		 * The CS went away while we were processing this interrupt,
-		 * this was the 'real' CS, need to process data.
-		 */
-	}
-
-	/* Make sure the receive FIFO is drained. */
-	sps_rx_interrupt(port, 1);
-	GWRITE_FIELD(SPS, ISTATE_CLR, CS_DEASSERT, 1);
-	GWRITE_FIELD(SPS, FIFO_CTRL, TXFIFO_EN, 0);
-
-	/*
-	 * And transmit FIFO is emptied, so the next transaction doesn't start
-	 * by clocking out any bytes left over from this one.
-	 */
-	GREG32(SPS, TXFIFO_WPTR) = GREG32(SPS, TXFIFO_RPTR);
-}
-
-void _sps0_interrupt(void)
-{
-	sps_rx_interrupt(0, 0);
-}
-
-void _sps0_cs_deassert_interrupt(void)
-{
-	sps_cs_deassert_interrupt(0);
-}
-DECLARE_IRQ(GC_IRQNUM_SPS0_CS_DEASSERT_INTR, _sps0_cs_deassert_interrupt, 1);
-DECLARE_IRQ(GC_IRQNUM_SPS0_RXFIFO_LVL_INTR, _sps0_interrupt, 1);
-
-#ifdef CONFIG_SPS_TEST
-
-/* Function to test SPS driver. It expects the host to send SPI frames of size
- * <size> (not exceeding 1100) of the following format:
- *
- * <size/256> <size%256> [<size> bytes of payload]
- *
- * Once the frame is received, it is sent back. The host can receive it and
- * compare with the original.
- */
-
- /*
-  * Receive callback implements a simple state machine, it could be in one of
-  * three states:  not started, receiving frame, frame finished.
-  */
-
-enum sps_test_rx_state {
-	spstrx_not_started,
-	spstrx_receiving,
-	spstrx_finished
-};
-
-static enum sps_test_rx_state rx_state;
-static uint8_t test_frame[1100]; /* Storage for the received frame. */
-/*
- * To verify different alignment cases, the frame is saved in the buffer
- * starting with a certain offset (in range 0..3).
- */
-static size_t frame_base;
-/*
- * This is the index of the next location where received data will be added
- * to. Points to the end of the received frame once it has been pulled in.
- */
-static size_t frame_index;
-
-static void sps_receive_callback(uint8_t *data, size_t data_size, int cs_status)
-{
-	static size_t frame_size; /* Total size of the frame being received. */
-	size_t to_go; /* Number of bytes still to receive. */
-
-	if (rx_state == spstrx_not_started) {
-		if (data_size < 2)
-			return; /* Something went wrong.*/
-
-		frame_size = data[0] * 256 + data[1] + 2;
-		frame_base = (frame_base + 1) % 3;
-		frame_index = frame_base;
-
-		if ((frame_index + frame_size) <= sizeof(test_frame))
-			/* Enter 'receiving frame' state. */
-			rx_state = spstrx_receiving;
-		else
-			/*
-			 * If we won't be able to receive this much, enter the
-			 * 'frame finished' state.
-			 */
-			rx_state = spstrx_finished;
-	}
-
-	if (rx_state == spstrx_finished) {
-		/*
-		 * If CS was deasserted (transitioned to 1) - prepare to start
-		 * receiving the next frame.
-		 */
-		if (cs_status)
-			rx_state = spstrx_not_started;
-		return;
-	}
-
-	if (frame_size > data_size)
-		to_go = data_size;
-	else
-		to_go = frame_size;
-
-	memcpy(test_frame + frame_index, data, to_go);
-	frame_index += to_go;
-	frame_size -= to_go;
-
-	if (!frame_size)
-		rx_state = spstrx_finished; /* Frame finished.*/
-}
-
-static int command_sps(int argc, char **argv)
-{
-	int count = 0;
-	int target = 10; /* Expect 10 frames by default.*/
-	char *e;
-
-	sps_tx_status(GC_SPS_DUMMY_WORD_DEFAULT);
-
-	rx_state = spstrx_not_started;
-	sps_register_rx_handler(SPS_GENERIC_MODE, sps_receive_callback, 0);
-
-	if (argc > 1) {
-		target = strtoi(argv[1], &e, 10);
-		if (*e)
-			return EC_ERROR_PARAM1;
-	}
-
-	while (count++ < target) {
-		size_t transmitted;
-		size_t to_go;
-		size_t index;
-
-		/* Wait for a frame to be received.*/
-		while (rx_state != spstrx_finished) {
-			watchdog_reload();
-			usleep(10);
-		}
-
-		/* Transmit the frame back to the host.*/
-		index = frame_base;
-		to_go = frame_index - frame_base;
-		do {
-			if ((index == frame_base) && (to_go > 8)) {
-				/*
-				 * This is the first transmit attempt for this
-				 * frame. Send a little just to prime the
-				 * transmit FIFO.
-				 */
-				transmitted = sps_transmit
-					(test_frame + index, 8);
-			} else {
-				transmitted = sps_transmit
-					(test_frame + index, to_go);
-			}
-			index += transmitted;
-			to_go -= transmitted;
-		} while (to_go);
-
-		/*
-		 * Wait for receive state machine to transition out of 'frame
-		 * finished' state.
-		 */
-		while (rx_state == spstrx_finished) {
-			watchdog_reload();
-			usleep(10);
-		}
-	}
-
-	ccprintf("Processed %d frames\n", count - 1);
-	ccprintf("rx count %d, tx count %d, tx_empty %d, max rx batch %d\n",
-		 sps_rx_count, sps_tx_count,
-		 tx_empty_count, max_rx_batch);
-
-	sps_rx_count =
-		sps_tx_count =
-		tx_empty_count =
-		max_rx_batch = 0;
-
-	return EC_SUCCESS;
-}
-
-DECLARE_CONSOLE_COMMAND(spstest, command_sps,
-			"<num of frames>",
-			"Loop back frames (10 by default) back to the host");
-#endif /* CONFIG_SPS_TEST */
diff --git a/chip/g/sps.h b/chip/g/sps.h
deleted file mode 100644
index 5e95042a7e..0000000000
--- a/chip/g/sps.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_INCLUDE_SPS_H
-#define __CROS_EC_INCLUDE_SPS_H
-
-#include "spi.h"
-#include "util.h"
-
-/* SPS Control Mode */
-enum sps_mode {
-	SPS_GENERIC_MODE = 0,
-	SPS_SWETLAND_MODE = 1,
-	SPS_ROM_MODE = 2,
-	SPS_UNDEF_MODE = 3,
-};
-
-/* Receive and transmit FIFO size and mask. */
-#define SPS_FIFO_SIZE		BIT(10)
-#define SPS_FIFO_MASK		(SPS_FIFO_SIZE - 1)
-
-/*
- * Tx interrupt callback function prototype. This function returns a portion
- * of the received SPI data and current status of the CS line. When CS is
- * deasserted, this function is called with data_size of zero and a non-zero
- * cs_status. This allows the recipient to delineate the SPS frames.
- */
-typedef void (*rx_handler_f)(uint8_t *data, size_t data_size, int cs_disabled);
-
-/*
- * Push data to the SPS TX FIFO
- * @param data Pointer to 8-bit data
- * @param data_size Number of bytes to transmit
- * @return : actual number of bytes placed into tx fifo
- */
-int sps_transmit(uint8_t *data, size_t data_size);
-
-/*
- * These functions return zero on success or non-zero on failure (attempt to
- * register a callback on top of existing one, or attempt to unregister
- * non-existing callback.
- *
- * rx_fifo_threshold value of zero means 'default'.
- */
-int sps_register_rx_handler(enum sps_mode mode,
-			    rx_handler_f rx_handler,
-			    unsigned rx_fifo_threshold);
-int sps_unregister_rx_handler(void);
-void sps_tx_status(uint8_t byte);
-
-#endif
diff --git a/chip/g/sps_tpm.c b/chip/g/sps_tpm.c
deleted file mode 100644
index 3e504f16b1..0000000000
--- a/chip/g/sps_tpm.c
+++ /dev/null
@@ -1,231 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "console.h"
-#include "hooks.h"
-#include "sps.h"
-#include "system.h"
-#include "tpm_registers.h"
-#include "util.h"
-
-/*
- * This implements the TCG's TPM SPI Hardware Protocol on the SPI bus, using
- * the Cr50 SPS (SPI slave) controller. This turns out to be very similar to
- * the EC host command protocol, which is itself similar to HDLC. All of those
- * protocols provide ways to identify data frames over transports that don't
- * provide them natively. That's the nice thing about standards: there are so
- * many to choose from.
- *
- * ANYWAY, The goal of the TPM protocol is to provide read and write access to
- * device registers over the SPI bus. It is defined as follows (note that the
- * master clocks the bus, but both master and slave transmit data
- * simultaneously).
- *
- * Each transaction starts with the master clocking the bus to transfer 4
- * bytes:
- *
- * The master sends 4 bytes:       [R/W+size-1] [Addr] [Addr] [Addr]
- * The slave also sends 4 bytes:       [xx]      [xx]   [xx]   [x?]
- *
- * Bytes sent by the master define the direction and size (1-64 bytes) of the
- * data transfer, and the address of the register to access.
- *
- * The final bit of the 4th slave response byte determines whether or not the
- * slave needs some extra time. If that bit is 1, the master can IMMEDIATELY
- * clock in (or out) the number of bytes it specified with the header byte 0.
- *
- * If the final bit of the 4th response byte is 0, the master clocks eight more
- * bits and looks again at the new received byte. It repeats this process
- * (clock 8 bits, look at last bit) as long as every eighth bit is 0.
- *
- * When the slave is ready to proceed with the data transfer, it returns a 1
- * for the final bit of the response byte, at which point the master has to
- * resume transferring valid data for write transactions or to start reading
- * bytes sent by the slave for read transactions.
- *
- * So here's what a 4-byte write of value of 0x11223344 to register 0xAABBCC
- * might look like:
- *
- *   xfer:  1  2  3  4  5  6  7  8  9 10 11
- *   MOSI: 03 aa bb cc xx xx xx 11 22 33 44
- *   MISO: xx xx xx x0 x0 x0 x1 xx xx xx xx
- *
- * Bit 0 of MISO xfer #4 is 0, indicating that the slave needs to stall. The
- * slave stalled for three bytes before it was ready to continue accepting the
- * input data from the master. The slave released the stall in xfer #7.
- *
- * Here's a 4-byte read from register 0xAABBCC:
- *
- *   xfer:  1  2  3  4  5  6  7  8  9 10 11
- *   MOSI: 83 aa bb cc xx xx xx xx xx xx xx
- *   MISO: xx xx xx x0 x0 x0 x1 11 22 33 44
- *
- * As before, the slave stalled the read for three bytes and indicated it was
- * done stalling at xfer #7.
- *
- * Note that the ONLY place where a stall can be initiated is the last bit of
- * the fourth MISO byte of the transaction. Once the stall is released,
- * there's no stopping the rest of the data transfer.
- */
-
-#define TPM_STALL_ASSERT   0x00
-#define TPM_STALL_DEASSERT 0x01
-
-/* Locality 0 register address base */
-#define TPM_LOCALITY_0_SPI_BASE 0x00d40000
-
-/* Console output macros */
-#define CPUTS(outstr) cputs(CC_TPM, outstr)
-#define CPRINTS(format, args...) cprints(CC_TPM, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_TPM, format, ## args)
-
-/*
- * Incoming messages are collected here until they're ready to process. The
- * buffer will start with a four-byte header, followed by whatever data
- * is sent by the master (none for a read, 1 to 64 bytes for a write).
- */
-#define RXBUF_MAX 512			/* chosen arbitrarily */
-static uint8_t rxbuf[RXBUF_MAX];
-static unsigned rxbuf_count;		/* num bytes received */
-static uint32_t bytecount;		/* Num of payload bytes when writing. */
-static uint32_t regaddr;		/* Address of register to read/write. */
-
-/*
- * Outgoing messages are shoved in here. We need a TPM_STALL_DEASSERT byte to
- * mark the start of the data stream before the data itself.
- */
-#define TXBUF_MAX 512				/* chosen arbitrarily */
-static uint8_t txbuf[1 + TXBUF_MAX];
-
-static enum sps_state {
-	/* Receiving header */
-	SPS_TPM_STATE_RECEIVING_HEADER,
-
-	/* Receiving data. */
-	SPS_TPM_STATE_RECEIVING_WRITE_DATA,
-
-	/* Finished rx processing, waiting for SPI transaction to finish. */
-	SPS_TPM_STATE_PONDERING,
-
-	/* Something went wrong. */
-	SPS_TPM_STATE_RX_BAD,
-} sps_tpm_state;
-
-/* Set initial conditions to get ready to receive a command. */
-static void init_new_cycle(void)
-{
-	rxbuf_count = 0;
-	sps_tpm_state = SPS_TPM_STATE_RECEIVING_HEADER;
-	sps_tx_status(TPM_STALL_ASSERT);
-	/* We're just waiting for a new command, so we could sleep. */
-	delay_sleep_by(1 * SECOND);
-	enable_sleep(SLEEP_MASK_SPI);
-}
-
-/* Extract R/W bit, register address, and data count from 4-byte header */
-static int header_says_to_read(uint8_t *data, uint32_t *reg, uint32_t *count)
-{
-	uint32_t addr = data[1];		/* reg address is MSB first */
-	addr = (addr << 8) + data[2];
-	addr = (addr << 8) + data[3];
-	*reg = addr;
-	*count = (data[0] & 0x3f) + 1;		/* bits 5-0: 1 to 64 bytes */
-	return !!(data[0] & 0x80);		/* bit 7: 1=read, 0=write */
-}
-
-/* actual RX FIFO handler (runs in interrupt context) */
-static void process_rx_data(uint8_t *data, size_t data_size, int cs_deasserted)
-{
-	/* We're receiving some bytes, so don't sleep */
-	disable_sleep(SLEEP_MASK_SPI);
-
-	if ((rxbuf_count + data_size) > RXBUF_MAX) {
-		CPRINTS("TPM SPI input overflow: %d + %d > %d in state %d",
-			rxbuf_count, data_size, RXBUF_MAX, sps_tpm_state);
-		sps_tx_status(TPM_STALL_DEASSERT);
-		sps_tpm_state = SPS_TPM_STATE_RX_BAD;
-		/* In this state, this function won't be called again until
-		 * after the CS deasserts and we've prepared for a new
-		 * transaction. */
-		return;
-	}
-	memcpy(rxbuf + rxbuf_count, data, data_size);
-	rxbuf_count += data_size;
-
-	/* Okay, we have enough. Now what? */
-	if (sps_tpm_state == SPS_TPM_STATE_RECEIVING_HEADER) {
-		if (rxbuf_count < 4)
-			return;	/* Header is 4 bytes in size. */
-
-		/* Got the header. What's it say to do? */
-		if (header_says_to_read(rxbuf, &regaddr, &bytecount)) {
-			/* Send the stall deassert manually */
-			txbuf[0] = TPM_STALL_DEASSERT;
-
-			/* Copy the register contents into the TXFIFO */
-			/* TODO: This is blindly assuming TXFIFO has enough
-			 * room. What can we do if it doesn't? */
-			tpm_register_get(regaddr - TPM_LOCALITY_0_SPI_BASE,
-					 txbuf + 1, bytecount);
-			sps_transmit(txbuf, bytecount + 1);
-			sps_tpm_state = SPS_TPM_STATE_PONDERING;
-			return;
-		}
-
-		/*
-		 * Write the new idle byte value, to signal the master to
-		 * proceed with data.
-		 */
-		sps_tx_status(TPM_STALL_DEASSERT);
-		sps_tpm_state = SPS_TPM_STATE_RECEIVING_WRITE_DATA;
-		return;
-	}
-
-	if (cs_deasserted &&
-	    (sps_tpm_state == SPS_TPM_STATE_RECEIVING_WRITE_DATA))
-		/* Ok, we have all the write data, pass it to the tpm. */
-		tpm_register_put(regaddr - TPM_LOCALITY_0_SPI_BASE,
-				 rxbuf + rxbuf_count - bytecount, bytecount);
-}
-
-static void tpm_rx_handler(uint8_t *data, size_t data_size, int cs_deasserted)
-{
-	if (chip_factory_mode())
-		return;  /* Ignore TPM traffic in factory mode. */
-
-	if ((sps_tpm_state == SPS_TPM_STATE_RECEIVING_HEADER) ||
-	    (sps_tpm_state == SPS_TPM_STATE_RECEIVING_WRITE_DATA))
-		process_rx_data(data, data_size, cs_deasserted);
-
-	if (cs_deasserted)
-		init_new_cycle();
-}
-
-static void sps_if_stop(void)
-{
-	/* Let's shut down the interface while TPM is being reset. */
-	sps_register_rx_handler(0, NULL, 0);
-}
-
-static void sps_if_start(void)
-{
-	/*
-	 * Threshold of 3 makes sure we get an interrupt as soon as the header
-	 * is received.
-	 */
-	init_new_cycle();
-	sps_register_rx_handler(SPS_GENERIC_MODE, tpm_rx_handler, 3);
-}
-
-
-static void sps_if_register(void)
-{
-	if (!board_tpm_uses_spi())
-		return;
-
-	tpm_register_interface(sps_if_start, sps_if_stop);
-}
-DECLARE_HOOK(HOOK_INIT, sps_if_register, HOOK_PRIO_LAST);
diff --git a/chip/g/system.c b/chip/g/system.c
deleted file mode 100644
index 86c3f52b5d..0000000000
--- a/chip/g/system.c
+++ /dev/null
@@ -1,798 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "board_id.h"
-#include "console.h"
-#include "cpu.h"
-#include "cpu.h"
-#include "flash.h"
-#include "flash_info.h"
-#include "printf.h"
-#include "registers.h"
-#include "system.h"
-#include "system_chip.h"
-#include "task.h"
-#include "version.h"
-
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
-/*
- * Value of the retry counter which, if exceeded, indicates that the currently
- * running RW image is not well and is rebooting before bringing the system
- * manages to come up.
- */
-#define RW_BOOT_MAX_RETRY_COUNT 5
-
-static uint8_t pinhold_on_reset;
-static uint8_t rollback_detected_at_boot;
-
-static void check_reset_cause(void)
-{
-	uint32_t g_rstsrc = GR_PMU_RSTSRC;
-	uint32_t flags = 0;
-
-	rollback_detected_at_boot = (GREG32(PMU, LONG_LIFE_SCRATCH0) >
-		RW_BOOT_MAX_RETRY_COUNT);
-
-	/* Clear the reset source now we have recorded it */
-	GR_PMU_CLRRST = 1;
-
-	if (g_rstsrc & GC_PMU_RSTSRC_POR_MASK) {
-		/* If power-on reset is true, that's the only thing */
-		system_set_reset_flags(EC_RESET_FLAG_POWER_ON);
-		return;
-	}
-
-	/* Low-power exit (ie, wake from deep sleep) */
-	if (g_rstsrc & GC_PMU_RSTSRC_EXIT_MASK) {
-		/* This register is cleared by reading it */
-		uint32_t g_exitpd = GR_PMU_EXITPD_SRC;
-
-		flags |= EC_RESET_FLAG_HIBERNATE;
-
-		if (g_exitpd & GC_PMU_EXITPD_SRC_PIN_PD_EXIT_MASK)
-			flags |= EC_RESET_FLAG_WAKE_PIN;
-		if (g_exitpd & GC_PMU_EXITPD_SRC_UTMI_SUSPEND_N_MASK)
-			flags |= EC_RESET_FLAG_USB_RESUME;
-		if (g_exitpd & (GC_PMU_EXITPD_SRC_TIMELS0_PD_EXIT_TIMER0_MASK |
-				GC_PMU_EXITPD_SRC_TIMELS0_PD_EXIT_TIMER1_MASK))
-			flags |= EC_RESET_FLAG_RTC_ALARM;
-		if (g_exitpd & GC_PMU_EXITPD_SRC_RDD0_PD_EXIT_TIMER_MASK)
-			flags |= EC_RESET_FLAG_RDD;
-		if (g_exitpd & GC_PMU_EXITPD_SRC_RBOX_WAKEUP_MASK)
-			flags |= EC_RESET_FLAG_RBOX;
-	}
-
-	if (g_rstsrc & GC_PMU_RSTSRC_SOFTWARE_MASK)
-		flags |= EC_RESET_FLAG_HARD;
-
-	if (g_rstsrc & GC_PMU_RSTSRC_SYSRESET_MASK)
-		flags |= EC_RESET_FLAG_SOFT;
-
-	if (g_rstsrc & GC_PMU_RSTSRC_FST_BRNOUT_MASK)
-		flags |= EC_RESET_FLAG_BROWNOUT;
-
-	/*
-	 * GC_PMU_RSTSRC_WDOG and GC_PMU_RSTSRC_LOCKUP are considered security
-	 * threats. They won't show up as a direct reset cause.
-	 */
-	if (g_rstsrc & GC_PMU_RSTSRC_SEC_THREAT_MASK)
-		flags |= EC_RESET_FLAG_SECURITY;
-
-	if (g_rstsrc && !flags)
-		flags |= EC_RESET_FLAG_OTHER;
-
-	system_set_reset_flags(flags);
-}
-
-void system_pre_init(void)
-{
-	check_reset_cause();
-
-	/*
-	 * This SoC supports dual "RO" bootloader images. The bootloader locks
-	 * the running RW image (us) before jumping to it, but we want to be
-	 * sure the active bootloader is also locked. Any images updates must
-	 * go into an inactive image location. If it's already locked, this has
-	 * no effect.
-	 */
-	GREG32(GLOBALSEC, FLASH_REGION0_CTRL_CFG_EN) = 0;
-}
-
-void system_pinhold_disengage(void)
-{
-	GREG32(PINMUX, HOLD) = 0;
-}
-
-void system_pinhold_on_reset_enable(void)
-{
-	pinhold_on_reset = 1;
-}
-
-void system_pinhold_on_reset_disable(void)
-{
-	pinhold_on_reset = 0;
-}
-
-void system_reset(int flags)
-{
-	/* Disable interrupts to avoid task swaps during reboot */
-	interrupt_disable();
-
-#if defined(CHIP_FAMILY_CR50)
-	/*
-	 * Decrement the retry counter on manually triggered reboots.  We were
-	 * able to process the console command, therefore we're probably okay.
-	 */
-	if (flags & SYSTEM_RESET_MANUALLY_TRIGGERED)
-		system_decrement_retry_counter();
-
-	/*
-	 * On CR50 we want every reset be hard reset, causing the entire
-	 * chromebook to reboot: we don't want the TPM reset while the AP
-	 * stays up.
-	 */
-	GR_PMU_GLOBAL_RESET = GC_PMU_GLOBAL_RESET_KEY;
-#else
-	if (flags & SYSTEM_RESET_HARD) {
-		/* Reset the full microcontroller */
-		GR_PMU_GLOBAL_RESET = GC_PMU_GLOBAL_RESET_KEY;
-	} else {
-		/* Soft reset is also fairly hard, and requires
-		 * permission registers to be reset to their initial
-		 * state.  To accomplish this, first register a wakeup
-		 * timer and then enter lower power mode. */
-
-		if (pinhold_on_reset)
-			GREG32(PINMUX, HOLD) = 1;
-
-		/* Low speed timers continue to run in low power mode. */
-		GREG32(TIMELS, TIMER1_CONTROL) = 0x1;
-		/* Wait for this long. */
-		GREG32(TIMELS, TIMER1_LOAD) = 1;
-		/* Setup wake-up on Timer1 firing. */
-		GREG32(PMU, EXITPD_MASK) =
-			GC_PMU_EXITPD_MASK_TIMELS0_PD_EXIT_TIMER1_MASK;
-
-		/* All the components to power cycle. */
-		GREG32(PMU, LOW_POWER_DIS) =
-			GC_PMU_LOW_POWER_DIS_VDDL_MASK |
-			GC_PMU_LOW_POWER_DIS_VDDIOF_MASK |
-			GC_PMU_LOW_POWER_DIS_VDDXO_MASK |
-			GC_PMU_LOW_POWER_DIS_JTR_RC_MASK;
-		/* Start low power sequence. */
-		REG_WRITE_MLV(GREG32(PMU, LOW_POWER_DIS),
-			GC_PMU_LOW_POWER_DIS_START_MASK,
-			GC_PMU_LOW_POWER_DIS_START_LSB,
-			1);
-	}
-#endif  /* ^^^^^^^ CHIP_FAMILY_CR50 Not defined */
-
-	/* Wait for reboot; should never return  */
-	while (1)
-		asm("wfi");
-}
-
-const char *system_get_chip_vendor(void)
-{
-	return "g";
-}
-
-const char *system_get_chip_name(void)
-{
-	return "cr50";
-}
-
-/*
- * There are three versions of B2 H1s outhere in the wild so far: chromebook,
- * poppy and detachable. The following registers are different in those
- * three versions in the following way:
- *
- *   register                chromebook          poppy     detachable
- *--------------------------------------------------------------------
- * RBOX_KEY_COMBO0_VAL          0xc0             0x80        0xc0
- * RBOX_POL_KEY1_IN             0x01             0x00        0x00
- * RBOX_KEY_COMBO0_HOLD         0x00             0x00        0x59
- */
-
-static const struct {
-	uint32_t  register_values;
-	const char *revision_str;
-} rev_map[] = {
-	{0xc00100, "B2-C"},	/* Chromebook. */
-	{0x800000, "B2-P"},	/* Poppy (a one off actually). */
-	{0xc00059, "B2-D"},	/* Detachable. */
-};
-
-/* Return a value which allows to identify the fuse setting of this chip. */
-static uint32_t get_fuse_set_id(void)
-{
-	return  (GREAD_FIELD(FUSE, RBOX_KEY_COMBO0_VAL, VAL) << 16) |
-		(GREAD_FIELD(FUSE, RBOX_POL_KEY1_IN, VAL) << 8) |
-		GREAD_FIELD(FUSE, RBOX_KEY_COMBO0_HOLD, VAL);
-}
-
-static const char *get_revision_str(void)
-{
-	int build_date = GR_SWDP_BUILD_DATE;
-	int build_time = GR_SWDP_BUILD_TIME;
-	uint32_t register_vals;
-	int i;
-
-	if ((build_date != GC_SWDP_BUILD_DATE_DEFAULT) ||
-	    (build_time != GC_SWDP_BUILD_TIME_DEFAULT))
-		return " BUILD MISMATCH!";
-
-	switch (GREAD_FIELD(PMU, CHIP_ID, REVISION)) {
-	case 3:
-		return "B1";
-
-	case 4:
-		register_vals = get_fuse_set_id();
-		for (i = 0; i < ARRAY_SIZE(rev_map); i++)
-			if (rev_map[i].register_values == register_vals)
-				return rev_map[i].revision_str;
-
-		return "B2-?";
-	}
-
-	return "B?";
-}
-
-const char *system_get_chip_revision(void)
-{
-	static const char *revision_str;
-
-	if (!revision_str)
-		revision_str = get_revision_str();
-
-	return revision_str;
-}
-
-int system_get_chip_unique_id(uint8_t **id)
-{
-	static uint32_t cached[8];
-
-	if (!cached[3]) { /* generate it if it doesn't exist yet */
-		const struct SignedHeader *ro_hdr = (const void *)
-			get_program_memory_addr(system_get_ro_image_copy());
-		const char *rev = get_revision_str();
-
-		cached[0] = ro_hdr->keyid;
-		cached[1] = GREG32(FUSE, DEV_ID0);
-		cached[2] = GREG32(FUSE, DEV_ID1);
-		strncpy((char *)&cached[3], rev, sizeof(cached[3]));
-	}
-	*id = (uint8_t *)cached;
-	return sizeof(cached);
-}
-
-int system_battery_cutoff_support_required(void)
-{
-	switch (get_fuse_set_id())
-	case 0xc00059:
-		return 1;
-
-	return 0;
-}
-
-int system_get_bbram(enum system_bbram_idx idx, uint8_t *value)
-{
-	return 0;
-}
-
-int system_set_bbram(enum system_bbram_idx idx, uint8_t value)
-{
-	return 0;
-}
-
-enum ec_image system_get_ro_image_copy(void)
-{
-	/*
-	 * The bootrom protects the selected bootloader with REGION0,
-	 * so we should be able to identify the active RO by seeing which one
-	 * is protected.
-	 */
-	switch (GREG32(GLOBALSEC, FLASH_REGION0_BASE_ADDR)) {
-	case CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RO_MEM_OFF:
-		return EC_IMAGE_RO;
-	case CONFIG_PROGRAM_MEMORY_BASE + CHIP_RO_B_MEM_OFF:
-		return EC_IMAGE_RO_B;
-	}
-
-	return EC_IMAGE_UNKNOWN;
-}
-
-/*
- * TODO(crbug.com/698882): Remove support for version_struct_deprecated once
- * we no longer care about supporting legacy RO.
- */
-struct version_struct_deprecated {
-	uint32_t cookie1;
-	char version[32];
-	uint32_t cookie2;
-};
-
-#define CROS_EC_IMAGE_DATA_COOKIE1_DEPRECATED 0xce112233
-#define CROS_EC_IMAGE_DATA_COOKIE2_DEPRECATED 0xce445566
-
-/*
- * The RW images contain version strings. The RO images don't, so we'll make
- * some here.
- */
-#define MAX_RO_VER_LEN 48
-static char vers_str[MAX_RO_VER_LEN];
-
-const char *system_get_version(enum ec_image copy)
-{
-	const struct image_data *data;
-	const struct version_struct_deprecated *data_deprecated;
-	const char *version;
-
-	const struct SignedHeader *h;
-	enum ec_image this_copy;
-	uintptr_t vaddr, delta;
-
-	switch (copy) {
-	case EC_IMAGE_RO:
-	case EC_IMAGE_RO_B:
-		/* The RO header is the first thing in each flash half */
-		vaddr = get_program_memory_addr(copy);
-		if (vaddr == INVALID_ADDR)
-			break;
-		h = (const struct SignedHeader *)vaddr;
-		/* Use some fields from the header for the version string */
-		snprintf(vers_str, MAX_RO_VER_LEN, "%d.%d.%d/%08x",
-			 h->epoch_, h->major_, h->minor_, h->img_chk_);
-		return vers_str;
-
-	case EC_IMAGE_RW:
-	case EC_IMAGE_RW_B:
-		/*
-		 * This function isn't part of any RO image, so we must be in a
-		 * RW image. If the current image is the one we're asked for,
-		 * we can just return our version string.
-		 */
-		this_copy = system_get_image_copy();
-		vaddr = get_program_memory_addr(this_copy);
-		h = (const struct SignedHeader *)vaddr;
-		if (copy == this_copy) {
-			snprintf(vers_str, sizeof(vers_str), "%d.%d.%d/%s",
-				 h->epoch_, h->major_, h->minor_,
-				 current_image_data.version);
-			return vers_str;
-		}
-
-		/*
-		 * We want the version of the other RW image. The linker script
-		 * puts the version string right after the reset vectors, so
-		 * it's at the same relative offset. Measure that offset here.
-		 */
-		delta = (uintptr_t)&current_image_data - vaddr;
-
-		/* Now look at that offset in the requested image */
-		vaddr = get_program_memory_addr(copy);
-		if (vaddr == INVALID_ADDR)
-			break;
-		h = (const struct SignedHeader *)vaddr;
-		/* Corrupted header's magic is set to zero. */
-		if (!h->magic)
-			break;
-
-		vaddr += delta;
-		data = (const struct image_data *)vaddr;
-		data_deprecated = (const struct version_struct_deprecated *)
-				  vaddr;
-
-		/*
-		 * Make sure the version struct cookies match before returning
-		 * the version string.
-		 */
-		if (data->cookie1 == current_image_data.cookie1 &&
-		    data->cookie2 == current_image_data.cookie2)
-			version = data->version;
-		/* Check for old / deprecated structure. */
-		else if (data_deprecated->cookie1 ==
-			 CROS_EC_IMAGE_DATA_COOKIE1_DEPRECATED &&
-			 data_deprecated->cookie2 ==
-			 CROS_EC_IMAGE_DATA_COOKIE2_DEPRECATED)
-			version = data_deprecated->version;
-		else
-			break;
-
-		snprintf(vers_str, sizeof(vers_str), "%d.%d.%d/%s",
-			 h->epoch_, h->major_, h->minor_, version);
-		return vers_str;
-
-	default:
-		break;
-	}
-
-	return "Error";
-}
-
-#if defined(CHIP_FAMILY_CR50)
-void system_clear_retry_counter(void)
-{
-	GWRITE_FIELD(PMU, LONG_LIFE_SCRATCH_WR_EN, REG0, 1);
-	GREG32(PMU, LONG_LIFE_SCRATCH0) = 0;
-	GWRITE_FIELD(PMU, LONG_LIFE_SCRATCH_WR_EN, REG0, 0);
-}
-
-void system_decrement_retry_counter(void)
-{
-	uint32_t val = GREG32(PMU, LONG_LIFE_SCRATCH0);
-
-	if (val != 0) {
-		GWRITE_FIELD(PMU, LONG_LIFE_SCRATCH_WR_EN, REG0, 1);
-		GREG32(PMU, LONG_LIFE_SCRATCH0) = val - 1;
-		GWRITE_FIELD(PMU, LONG_LIFE_SCRATCH_WR_EN, REG0, 0);
-	}
-}
-
-/*
- * Check which of the two cr50 RW images is newer, return true if the first
- * image is no older than the second one.
- *
- * Note that RO and RW images use the same header structure. When deciding
- * which image to run, the boot ROM ignores the timestamp, but the cros loader
- * considers the timestamp if all other fields are equal.
- */
-static int a_is_newer_than_b(const struct SignedHeader *a,
-			     const struct SignedHeader *b)
-{
-	if (a->epoch_ != b->epoch_)
-		return a->epoch_ > b->epoch_;
-	if (a->major_ != b->major_)
-		return a->major_ > b->major_;
-	if (a->minor_ != b->minor_)
-		return a->minor_ > b->minor_;
-
-	/* This comparison is not made by ROM. */
-	if (a->timestamp_ != b->timestamp_)
-		return a->timestamp_ > b->timestamp_;
-
-	return 1; /* All else being equal, consider A to be newer. */
-}
-
-/* Used to track if cr50 has corrupted the inactive header */
-static uint8_t header_corrupted;
-
-/*
- * Corrupt the 'magic' field of the passed in header. This prevents the
- * apparently failing image from being considered as a candidate to load and
- * run on the following reboots.
- */
-static int corrupt_header(volatile struct SignedHeader *header)
-{
-	int rv;
-	const char zero[4] = {}; /* value to write to magic. */
-
-	/* Enable RW access to the other header. */
-	GREG32(GLOBALSEC, FLASH_REGION6_BASE_ADDR) = (uint32_t) header;
-	GREG32(GLOBALSEC, FLASH_REGION6_SIZE) = 1023;
-	GWRITE_FIELD(GLOBALSEC, FLASH_REGION6_CTRL, EN, 1);
-	GWRITE_FIELD(GLOBALSEC, FLASH_REGION6_CTRL, RD_EN, 1);
-	GWRITE_FIELD(GLOBALSEC, FLASH_REGION6_CTRL, WR_EN, 1);
-
-	CPRINTS("%s: RW fallback must have happened, magic at %pP before: %x",
-		__func__, &header->magic, header->magic);
-
-	rv = flash_physical_write((intptr_t)&header->magic -
-			     CONFIG_PROGRAM_MEMORY_BASE,
-			     sizeof(zero), zero);
-
-	/* Disable W access to the other header. */
-	GWRITE_FIELD(GLOBALSEC, FLASH_REGION6_CTRL, WR_EN, 0);
-	CPRINTS("%s: magic after: %x", __func__, header->magic);
-
-	header_corrupted = !rv;
-	return rv;
-}
-/*
- * Check if the current running image is newer. Set the passed in pointer, if
- * supplied, to point to the newer image in case the running image is the
- * older one.
- */
-static int current_image_is_newer(struct SignedHeader **newer_image)
-{
-	struct SignedHeader *me, *other;
-
-	if (system_get_image_copy() == EC_IMAGE_RW) {
-		me = (struct SignedHeader *)
-			get_program_memory_addr(EC_IMAGE_RW);
-		other = (struct SignedHeader *)
-			get_program_memory_addr(EC_IMAGE_RW_B);
-	} else {
-		me = (struct SignedHeader *)
-			get_program_memory_addr(EC_IMAGE_RW_B);
-		other = (struct SignedHeader *)
-			get_program_memory_addr(EC_IMAGE_RW);
-	}
-
-	if (a_is_newer_than_b(me, other))
-		return 1;
-
-	if (newer_image)
-		*newer_image = other;
-	return 0;
-}
-
-int system_rollback_detected(void)
-{
-	return rollback_detected_at_boot;
-}
-
-int system_process_retry_counter(void)
-{
-	struct SignedHeader *newer_image;
-
-	CPRINTS("%s: retry counter %d", __func__,
-		GREG32(PMU, LONG_LIFE_SCRATCH0));
-	system_clear_retry_counter();
-
-	if (!system_rollback_detected())
-		return EC_SUCCESS;
-
-	if (current_image_is_newer(&newer_image)) {
-		CPRINTS("%s: "
-			"this is odd, I am newer, but retry counter indicates "
-			"the system rolledback", __func__);
-		return EC_SUCCESS;
-	}
-
-	if (header_corrupted) {
-		CPRINTS("%s: header already corrupted", __func__);
-		return EC_SUCCESS;
-	}
-
-	/*
-	 * let's corrupt the newer image so that the next restart is happening
-	 * straight into the current version.
-	 */
-	return corrupt_header(newer_image);
-}
-
-void system_ensure_rollback(void)
-{
-	GWRITE_FIELD(PMU, LONG_LIFE_SCRATCH_WR_EN, REG0, 1);
-	GREG32(PMU, LONG_LIFE_SCRATCH0) = RW_BOOT_MAX_RETRY_COUNT + 1;
-	GWRITE_FIELD(PMU, LONG_LIFE_SCRATCH_WR_EN, REG0, 0);
-}
-
-int system_rolling_reboot_suspected(void)
-{
-	if (GREG32(PMU, LONG_LIFE_SCRATCH0) > 50) {
-		/*
-		 * The chip has restarted 50 times without the restart counter
-		 * cleared. There must be something wrong going, the chip is
-		 * likely in rolling reboot.
-		 */
-		CPRINTS("%s: Try powercycling to clear this condition.",
-			__func__);
-		return 1;
-	}
-
-	return 0;
-}
-#endif
-
-/* Prepend header version to the current image's build info. */
-const char *system_get_build_info(void)
-{
-	static char combined_build_info[150];
-
-	if (!*combined_build_info) {
-		const struct SignedHeader *me;
-
-		me = (struct SignedHeader *)
-			get_program_memory_addr(system_get_image_copy());
-		snprintf(combined_build_info, sizeof(combined_build_info),
-			 "%d.%d.%d/%s",
-			 me->epoch_, me->major_, me->minor_, build_info);
-	}
-
-	return combined_build_info;
-}
-
-/**
- * Modify info1 RW rollback mask to match the passed in header(s).
- *
- * If both headers' addressses are passed in, the INFO1 rollback mask field is
- * erased in case both headers have a zero in the appropriate bit. If only one
- * header address is passed (the other one is set to zero), only the valid
- * header is considered when updating INFO1.
- */
-static void update_rollback_mask(uint32_t addr_a, uint32_t addr_b,
-				 uint32_t info_base_offset)
-{
-#ifndef CR50_DEV
-	const struct SignedHeader *header_a;
-	const struct SignedHeader *header_b;
-	int updated_words_count = 0;
-	int i;
-	int write_enabled = 0;
-	uint32_t header_mask = 0;
-
-	header_a = (const struct SignedHeader *)addr_a;
-	header_b = (const struct SignedHeader *)addr_b;
-
-	/*
-	 * The infomap field in the image header has a matching space in the
-	 * flash INFO1 section.
-	 *
-	 * The INFO1 space words which map into zeroed bits in the infomap
-	 * header are ignored by the RO.
-	 *
-	 * Let's make sure that those words in the INFO1 space are erased.
-	 * This in turn makes sure that attempts to load earlier RW images
-	 * (where those bits in the header are not zeroed) will fail, thus
-	 * ensuring rollback protection.
-	 */
-	/* For each bit in the header infomap field of the running image. */
-	for (i = 0; i < INFO_MAX; i++) {
-		uint32_t bit;
-		uint32_t word;
-		int byte_offset;
-
-		/* Read the next infomap word when done with the current one. */
-		if (!(i % 32)) {
-			/*
-			 * Not to shoot ourselves in the foot, let's zero only
-			 * those words in the INFO1 space which are set to
-			 * zero in all headers we are supposed to look at.
-			 */
-			header_mask = 0;
-
-			if (header_a)
-				header_mask |= header_a->infomap[i/32];
-
-			if (header_b)
-				header_mask |= header_b->infomap[i/32];
-		}
-
-		/* Get the next bit value. */
-		bit = !!(header_mask & (1 << (i % 32)));
-		if (bit) {
-			/*
-			 * By convention zeroed bits are expected to be
-			 * adjacent at the LSB of the info mask field. Stop as
-			 * soon as a non-zeroed bit is encountered.
-			 */
-			CPRINTS("%s: bailing out at bit %d", __func__, i);
-			break;
-		}
-
-		byte_offset = info_base_offset + i * sizeof(uint32_t);
-
-		if (flash_physical_info_read_word(byte_offset, &word) !=
-		    EC_SUCCESS) {
-			CPRINTS("failed to read info mask word %d", i);
-			continue;
-		}
-
-		if (!word)
-			continue; /* This word has been zeroed already. */
-
-		if (!write_enabled) {
-			flash_info_write_enable();
-			write_enabled = 1;
-		}
-
-		word = 0;
-		if (flash_info_physical_write(byte_offset,
-					      sizeof(word),
-					      (const char *) &word) !=
-		    EC_SUCCESS) {
-			CPRINTS("failed to write info mask word %d", i);
-			continue;
-		}
-		updated_words_count++;
-
-	}
-	if (!write_enabled)
-		return;
-
-	flash_info_write_disable();
-	CPRINTS("updated %d info map words", updated_words_count);
-#endif  /*  CR50_DEV ^^^^^^^^ NOT defined. */
-}
-
-void system_update_rollback_mask_with_active_img(void)
-{
-	update_rollback_mask(
-		get_program_memory_addr(system_get_ro_image_copy()), 0,
-		INFO_RO_MAP_OFFSET);
-	update_rollback_mask(get_program_memory_addr(system_get_image_copy()),
-			     0, INFO_RW_MAP_OFFSET);
-}
-
-void system_update_rollback_mask_with_both_imgs(void)
-{
-	update_rollback_mask(get_program_memory_addr(EC_IMAGE_RO),
-			     get_program_memory_addr(EC_IMAGE_RO_B),
-			     INFO_RO_MAP_OFFSET);
-	update_rollback_mask(get_program_memory_addr(EC_IMAGE_RW),
-			     get_program_memory_addr(EC_IMAGE_RW_B),
-			     INFO_RW_MAP_OFFSET);
-}
-
-void system_get_rollback_bits(char *value, size_t value_size)
-{
-	int i;
-	size_t str_offset = 0;
-	struct {
-		uint32_t info_map_offset;
-		uint32_t image_types[2];
-	} headers[] = {
-		{ .info_map_offset = INFO_RO_MAP_OFFSET,
-		  .image_types = { EC_IMAGE_RO, EC_IMAGE_RO_B } },
-		{ .info_map_offset = INFO_RW_MAP_OFFSET,
-		  .image_types = { EC_IMAGE_RW, EC_IMAGE_RW_B } }
-	};
-
-	for (i = 0; i < ARRAY_SIZE(headers); i++) {
-		int j;
-
-		/* First see how many bits are cleared in the INFO space. */
-		for (j = 0; j < INFO_MAX; j++) {
-			uint32_t w;
-
-			flash_physical_info_read_word(
-				headers[i].info_map_offset +
-					j * sizeof(uint32_t),
-				&w);
-			if (w)
-				break;
-		}
-		/* Count of INFO space bits. */
-		str_offset += snprintf(value + str_offset,
-				       value_size - str_offset, " %d", j);
-
-		/* Iterate over two sections, A and B. */
-		for (j = 0; j < ARRAY_SIZE(headers[i].image_types); j++) {
-			int k;
-			const struct SignedHeader *sh;
-
-			sh = (const struct SignedHeader *)
-				get_program_memory_addr(
-					headers[i].image_types[j]);
-			for (k = 0; k < INFO_MAX; k++)
-				if (sh->infomap[k/32] & (1 << (k%32)))
-					break;
-			str_offset += snprintf(value + str_offset,
-					       value_size - str_offset, "/%d",
-					       k);
-		}
-	}
-}
-
-#ifdef CONFIG_EXTENDED_VERSION_INFO
-
-void system_print_extended_version_info(void)
-{
-	int i;
-	struct board_id bid;
-	enum ec_image rw_images[] = {
-		EC_IMAGE_RW, EC_IMAGE_RW_B
-	};
-
-	if (read_board_id(&bid) != EC_SUCCESS) {
-		ccprintf("Board ID read failure!\n");
-		return;
-	}
-
-	for (i = 0; i < ARRAY_SIZE(rw_images); i++) {
-		struct SignedHeader *ss = (struct SignedHeader *)
-			get_program_memory_addr(rw_images[i]);
-
-		ccprintf("BID %c:   %08x:%08x:%08x %s\n", 'A' + i,
-			 ss->board_id_type ^ SIGNED_HEADER_PADDING,
-			 ss->board_id_type_mask ^ SIGNED_HEADER_PADDING,
-			 ss->board_id_flags ^ SIGNED_HEADER_PADDING,
-			 check_board_id_vs_header(&bid, ss) ? " No" : "Yes");
-	}
-}
-
-#endif /* CONFIG_EXTENDED_VERSION_INFO */
diff --git a/chip/g/system_chip.h b/chip/g/system_chip.h
deleted file mode 100644
index 3547bf58c7..0000000000
--- a/chip/g/system_chip.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* chip/g-specific system function prototypes */
-
-#ifndef __CROS_EC_SYSTEM_CHIP_H
-#define __CROS_EC_SYSTEM_CHIP_H
-
-/**
- * On systems with protection from a failing RW update: read the retry counter
- * and act on it.
- *
- * @return EC_SUCCESS if no flash write errors were encounterd.
- */
-int system_process_retry_counter(void);
-
-/**
- * On systems with protection from a failing RW update: reset retry
- * counter, this is used after a new image upload is finished, to make
- * sure that the new image has a chance to run.
- */
-void system_clear_retry_counter(void);
-
-/**
- * A function provided by some platforms to decrement a retry counter.
- *
- * This should be used whenever a system reset is manually triggered.
- */
-void system_decrement_retry_counter(void);
-
-/**
- * A function provided by some platforms to hint that something is going
- * wrong.
- *
- * @return a boolean, set to True if rolling reboot condition is suspected.
- */
-int system_rolling_reboot_suspected(void);
-
-/**
- * Returns True if a rollback was detected during system_preinit.
- *
- * system_rollback_detected only returns True from rollback until the AP boots
- * and then enters deep sleep. The system won't know that it rolled back on
- * resume from deep sleep.
- *
- * @return a boolean, set to True if a rollback is detected.
- */
-int system_rollback_detected(void);
-
-/**
- * Returns non-zero value when firmware is expected to be abe to detect user
- * request to cut off battery supply.
- */
-int system_battery_cutoff_support_required(void);
-
-/**
- * Functions to update INFO1 rollback mask based on one or both RW image
- * headers.
- */
-void system_update_rollback_mask_with_active_img(void);
-void system_update_rollback_mask_with_both_imgs(void);
-
-/**
- * Scan INFO1 rollback map and infomap fields of both RW and RW_B image
- * headers, and return a string showing how many zeros are there at the base
- * of in each of these objects.
- *
- * The passed in parameters are the memory area to put the string in and the
- * size of this memory area.
- */
-void system_get_rollback_bits(char *value, size_t value_size);
-
-/**
- * Set the rollback counter to a value which would ensure a rollback on the
- * next boot.
- */
-void system_ensure_rollback(void);
-
-/**
- * Enables holding external pins across soft chip resets. Application firmware
- * is responsible for disengaging pinhold upon reset.
- */
-void system_pinhold_on_reset_enable(void);
-
-/**
- * Disables holding external pins across soft chip resets.
- */
-void system_pinhold_on_reset_disable(void);
-
-/**
- * Disengages pinhold if engaged.
- */
-void system_pinhold_disengage(void);
-
-#endif /* __CROS_EC_SYSTEM_CHIP_H */
diff --git a/chip/g/trng.c b/chip/g/trng.c
deleted file mode 100644
index afd9fa86e3..0000000000
--- a/chip/g/trng.c
+++ /dev/null
@@ -1,170 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "flash_log.h"
-#include "init_chip.h"
-#include "registers.h"
-#include "trng.h"
-
-void init_trng(void)
-{
-#if (!(defined(CONFIG_CUSTOMIZED_RO) && defined(SECTION_IS_RO)))
-	/*
-	 * Most of the trng initialization requires high permissions. If RO has
-	 * dropped the permission level, dont try to read or write these high
-	 * permission registers because it will cause rolling reboots. RO
-	 * should do the TRNG initialization before dropping the level.
-	 */
-	if (!runlevel_is_high())
-		return;
-#endif
-
-	GWRITE(TRNG, POST_PROCESSING_CTRL,
-		GC_TRNG_POST_PROCESSING_CTRL_SHUFFLE_BITS_MASK |
-		GC_TRNG_POST_PROCESSING_CTRL_CHURN_MODE_MASK);
-	GWRITE(TRNG, SLICE_MAX_UPPER_LIMIT, 1);
-	GWRITE(TRNG, SLICE_MIN_LOWER_LIMIT, 0);
-	GWRITE(TRNG, TIMEOUT_COUNTER, 0x7ff);
-	GWRITE(TRNG, TIMEOUT_MAX_TRY_NUM, 4);
-	GWRITE(TRNG, POWER_DOWN_B, 1);
-	GWRITE(TRNG, GO_EVENT, 1);
-}
-
-uint32_t rand(void)
-{
-	while (GREAD(TRNG, EMPTY)) {
-		if (GREAD_FIELD(TRNG, FSM_STATE, FSM_IDLE)) {
-			/* TRNG timed out, restart */
-			GWRITE(TRNG, STOP_WORK, 1);
-#if !defined(SECTION_IS_RO) && defined(CONFIG_FLASH_LOG)
-			flash_log_add_event(FE_LOG_TRNG_STALL, 0, NULL);
-#endif
-			GWRITE(TRNG, GO_EVENT, 1);
-		}
-	}
-	return GREAD(TRNG, READ_DATA);
-}
-
-void rand_bytes(void *buffer, size_t len)
-{
-	int random_togo = 0;
-	int buffer_index = 0;
-	uint32_t random_value;
-	uint8_t *buf = (uint8_t *) buffer;
-
-	/*
-	 * Retrieve random numbers in 4 byte quantities and pack as many bytes
-	 * as needed into 'buffer'. If len is not divisible by 4, the
-	 * remaining random bytes get dropped.
-	 */
-	while (buffer_index < len) {
-		if (!random_togo) {
-			random_value = rand();
-			random_togo = sizeof(random_value);
-		}
-		buf[buffer_index++] = random_value >>
-			((random_togo-- - 1) * 8);
-	}
-}
-
-#if !defined(SECTION_IS_RO) && defined(TEST_TRNG)
-#include "console.h"
-#include "watchdog.h"
-
-static uint32_t histogram[256];
-static int command_rand(int argc, char **argv)
-{
-	int count = 1000; /* Default number of cycles. */
-	struct pair {
-		uint32_t value;
-		uint32_t count;
-	};
-	struct pair min;
-	struct pair max;
-
-	if (argc == 2)
-		count = strtoi(argv[1], NULL, 10);
-
-	memset(histogram, 0, sizeof(histogram));
-	ccprintf("Retrieving %d random words.\n", count);
-	while (count-- > 0) {
-		uint32_t rvalue;
-		int size;
-
-		rvalue = rand();
-		for (size = 0; size < sizeof(rvalue); size++)
-			histogram[((uint8_t *)&rvalue)[size]]++;
-
-		if (!(count % 10000))
-			watchdog_reload();
-	}
-
-	min.count = ~0;
-	max.count = 0;
-	for (count = 0; count < ARRAY_SIZE(histogram); count++) {
-		if (histogram[count] > max.count) {
-			max.count = histogram[count];
-			max.value = count;
-			continue;
-		}
-		if (histogram[count] >= min.count)
-			continue;
-
-		min.count = histogram[count];
-		min.value = count;
-	}
-
-	ccprintf("min %d(%d), max %d(%d)", min.count, min.value,
-		 max.count, max.value);
-
-	for (count = 0; count < ARRAY_SIZE(histogram); count++) {
-		if (!(count % 8)) {
-			ccprintf("\n");
-			cflush();
-		}
-		ccprintf(" %6d", histogram[count]);
-	}
-	ccprintf("\n");
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(rand, command_rand, NULL, NULL);
-#endif /* !defined(SECTION_IS_RO) && defined(TEST_TRNG) */
-
-#ifdef CRYPTO_TEST_SETUP
-#include "extension.h"
-/*
- * This extension command is similar to TPM2_GetRandom, but made
- * available for CRYPTO_TEST = 1 which disables TPM
- * Command structure, shared out of band with the test driver running
- * on the host:
- *
- * field     |    size  |                  note
- * ===================================================================
- * text_len  |    2     | size of the text to process, big endian
- */
-static enum vendor_cmd_rc trng_test(enum vendor_cmd_cc code, void *buf,
-				    size_t input_size, size_t *response_size)
-{
-	uint16_t text_len;
-	uint8_t *cmd;
-	size_t response_room = *response_size;
-
-	if (input_size != sizeof(text_len)) {
-		*response_size = 0;
-		return VENDOR_RC_BOGUS_ARGS;
-	}
-	cmd = buf;
-	text_len = *cmd++;
-	text_len = text_len * 256 + *cmd++;
-	text_len = MIN(text_len, response_room);
-	rand_bytes(buf, text_len);
-	*response_size = text_len;
-	return VENDOR_RC_SUCCESS;
-}
-
-DECLARE_VENDOR_COMMAND(VENDOR_CC_TRNG_TEST, trng_test);
-
-#endif   /* CRYPTO_TEST_SETUP */
diff --git a/chip/g/uart.c b/chip/g/uart.c
deleted file mode 100644
index 2ce2c20ca3..0000000000
--- a/chip/g/uart.c
+++ /dev/null
@@ -1,126 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "clock.h"
-#include "common.h"
-#include "gpio.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "uart.h"
-#include "uartn.h"
-#include "util.h"
-
-enum init_values {
-	INIT_NOT_START,
-	INIT_IN_PROGRESS,
-	INIT_DONE
-};
-
-static enum init_values done_uart_init_yet;
-
-#define USE_UART_INTERRUPTS (!(defined(CONFIG_CUSTOMIZED_RO) && \
-			       defined(SECTION_IS_RO)))
-#ifndef UARTN
-#define UARTN 0
-#endif
-
-static int uart_init_check_pinhold(void)
-{
-	if (!GREAD(PINMUX, HOLD) && done_uart_init_yet == INIT_IN_PROGRESS)
-		done_uart_init_yet = INIT_DONE;
-	return done_uart_init_yet == INIT_DONE;
-}
-
-int uart_init_done(void)
-{
-	return (done_uart_init_yet == INIT_DONE) ||
-		uart_init_check_pinhold();
-}
-
-void uart_tx_start(void)
-{
-	uartn_tx_start(UARTN);
-}
-
-void uart_tx_stop(void)
-{
-	uartn_tx_stop(UARTN);
-}
-
-int uart_tx_in_progress(void)
-{
-	return uartn_tx_in_progress(UARTN);
-}
-
-void uart_tx_flush(void)
-{
-	uartn_tx_flush(UARTN);
-}
-
-int uart_tx_ready(void)
-{
-	/* True if the TX buffer is not completely full */
-	return uartn_tx_ready(UARTN);
-}
-
-int uart_rx_available(void)
-{
-	/* True if the RX buffer is not completely empty. */
-	return uartn_rx_available(UARTN);
-}
-
-void uart_write_char(char c)
-{
-	uartn_write_char(UARTN, c);
-}
-
-int uart_read_char(void)
-{
-	return uartn_read_char(UARTN);
-}
-
-#if USE_UART_INTERRUPTS
-
-/**
- * Interrupt handlers for UART0
- */
-static void uart_console_tx_interrupt(void)
-{
-	/* Clear transmit interrupt status */
-	GR_UART_ISTATECLR(UARTN) = GC_UART_ISTATECLR_TX_MASK;
-
-	/* Fill output FIFO */
-	uart_process_output();
-}
-DECLARE_IRQ(GC_IRQNUM_UART0_TXINT, uart_console_tx_interrupt, 1);
-
-static void uart_console_rx_interrupt(void)
-{
-	/* Clear receive interrupt status */
-	GR_UART_ISTATECLR(UARTN) = GC_UART_ISTATECLR_RX_MASK;
-
-	/* Read input FIFO until empty */
-	uart_process_input();
-}
-DECLARE_IRQ(GC_IRQNUM_UART0_RXINT, uart_console_rx_interrupt, 1);
-#endif  /* USE_UART_INTERRUPTS */
-
-void uart_init(void)
-{
-	clock_enable_module(MODULE_UART, 1);
-
-	/* Initialize the Cr50 UART */
-	uartn_init(UARTN);
-	uartn_enable(UARTN);
-
-#ifdef UART_AP
-	uartn_init(UART_AP);
-#endif
-#ifdef UART_EC
-	uartn_init(UART_EC);
-#endif
-	done_uart_init_yet = INIT_IN_PROGRESS;
-}
diff --git a/chip/g/uart_bitbang.c b/chip/g/uart_bitbang.c
deleted file mode 100644
index 31bce8128a..0000000000
--- a/chip/g/uart_bitbang.c
+++ /dev/null
@@ -1,497 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "gpio.h"
-#include "pmu.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "uart_bitbang.h"
-#include "uartn.h"
-
-#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ##args)
-#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ##args)
-
-#define BITBANG_DEBUG 0 /* Set to 1 to enable debug counters and logs. */
-
-/* Support the "standard" baud rates. */
-#define IS_BAUD_RATE_SUPPORTED(rate) \
-	((rate == 1200) || (rate == 2400) || (rate == 4800) || (rate == 9600) \
-	|| (rate == 19200) || (rate == 38400) || (rate == 57600) || \
-	 (rate == 115200))
-
-#define TIMEUS_CLK_FREQ 24 /* units: MHz */
-#define RX_BUF_SIZE	257
-
-/* Flag indicating whether bit banging is enabled or not. */
-static uint8_t bitbang_enabled;
-/* Flag indicating bit banging is desired.  Allows async enable/disable. */
-static uint8_t bitbang_wanted;
-
-/* Current bitbang context */
-static uint32_t bit_period_ticks;
-static uint8_t set_parity;
-
-#if BITBANG_DEBUG
-/* debug counters and log */
-#define DISCARD_LOG 8
-static int read_char_cnt;
-static int rx_buff_inserted_cnt;
-static int rx_buff_rx_char_cnt;
-static int stop_bit_err_cnt;
-static int parity_err_cnt;
-static int parity_err_discard[DISCARD_LOG];
-static int parity_discard_idx;
-static int stop_bit_discard[DISCARD_LOG];
-static int stop_bit_discard_idx;
-#endif /* BITBANG_DEBUG */
-
-enum parity_type {
-	PARITY_TYPE_NONE = 0,
-	PARITY_TYPE_ODD = 1,
-	PARITY_TYPE_EVEN = 2,
-	PARITY_TYPE_MAX,
-};
-
-char *parity_type_name[PARITY_TYPE_MAX] = {
-	"none",
-	"odd",
-	"even",
-};
-
-static char *feature_name = "Bit bang";
-
-int uart_bitbang_is_enabled(void)
-{
-	return bitbang_enabled;
-}
-
-int uart_bitbang_is_wanted(void)
-{
-	return bitbang_wanted;
-}
-
-static int uart_bitbang_config(int baud_rate, uint8_t parity)
-{
-	/* Can't configure when enabled */
-	if (bitbang_enabled)
-		return EC_ERROR_BUSY;
-
-	/* Check desired properties. */
-	if (!IS_BAUD_RATE_SUPPORTED(baud_rate)) {
-		CPRINTF("Err: invalid baud rate (%d)\n", baud_rate);
-		return EC_ERROR_INVAL;
-	}
-	bitbang_config.baud_rate = baud_rate;
-
-	if (parity >= PARITY_TYPE_MAX) {
-		CPRINTF("Err: invalid parity '%d'. (0:N, 1:O, 2:E)\n", parity);
-		return EC_ERROR_INVAL;
-	}
-	bitbang_config.parity = parity;
-
-	return EC_SUCCESS;
-}
-
-int uart_bitbang_enable(void)
-{
-	if (bitbang_enabled)
-		return EC_SUCCESS;
-
-	/* UART TX must be disconnected first */
-	if (uart_tx_is_connected(bitbang_config.uart))
-		return EC_ERROR_BUSY;
-
-	/* Set this early to avoid interfering with CCD state machine. */
-	bitbang_enabled = 1;
-
-	/*
-	 * Disable aggregate interrupts from GPIOs, otherwise
-	 * _gpio0_interrupt() gets invoked along with the pin specific
-	 * interrupts.
-	 */
-	task_disable_irq(GC_IRQNUM_GPIO0_GPIOCOMBINT);
-	task_disable_irq(GC_IRQNUM_GPIO1_GPIOCOMBINT);
-
-	/* Select the GPIOs instead of the UART block */
-	REG32(bitbang_config.tx_pinmux_reg) = bitbang_config.tx_pinmux_regval;
-	gpio_set_flags(bitbang_config.tx_gpio, GPIO_OUT_HIGH);
-	REG32(bitbang_config.rx_pinmux_reg) = bitbang_config.rx_pinmux_regval;
-	gpio_set_flags(bitbang_config.rx_gpio, GPIO_INPUT);
-
-	/*
-	 * Ungate the microsecond timer so that we can use it.  This is needed
-	 * for accurate framing if using faster baud rates.
-	 */
-	pmu_clock_en(PERIPH_TIMEUS);
-	GR_TIMEUS_EN(0) = 0;
-	GR_TIMEUS_MAXVAL(0) = 0xFFFFFFFF;
-	GR_TIMEUS_CUR_MAJOR(0) = 0; /* Prevent timer counter overflows. */
-	GR_TIMEUS_EN(0) = 1;
-
-	/* Save context information. */
-	bit_period_ticks = ((uint64_t)TIMEUS_CLK_FREQ * SECOND) /
-		bitbang_config.baud_rate;
-	set_parity = bitbang_config.parity;
-
-	uartn_disable_interrupt(bitbang_config.uart);
-	task_enable_irq(bitbang_config.rx_irq);
-	gpio_enable_interrupt(bitbang_config.rx_gpio);
-
-	CPRINTS("%s enabled", feature_name);
-
-	return EC_SUCCESS;
-}
-
-int uart_bitbang_disable(void)
-{
-	if (!uart_bitbang_is_enabled())
-		return EC_SUCCESS;
-
-	gpio_reset(bitbang_config.tx_gpio);
-	gpio_reset(bitbang_config.rx_gpio);
-
-	/* Gate the microsecond timer since we're done with it. */
-	pmu_clock_dis(PERIPH_TIMEUS);
-
-	/* Don't need to watch RX */
-	gpio_disable_interrupt(bitbang_config.rx_gpio);
-	task_disable_irq(bitbang_config.rx_irq);
-	uartn_enable_interrupt(bitbang_config.uart);
-
-	/* Restore aggregate GPIO interrupts. */
-	task_enable_irq(GC_IRQNUM_GPIO0_GPIOCOMBINT);
-	task_enable_irq(GC_IRQNUM_GPIO1_GPIOCOMBINT);
-
-	bitbang_enabled = 0;
-
-	CPRINTS("%s disabled", feature_name);
-	return EC_SUCCESS;
-}
-
-/*
- * Function waiting for completion of the current tick should be re-entrant -
- * it is not likely to happen, but is possible that the RX interrupt gets
- * asserted while the last period of the TX is still counting, because the
- * last TX period is counting with interrupts enabled.
- */
-static void wait_ticks(uint32_t *next_tick)
-{
-	uint32_t nt = *next_tick;
-
-	while (GR_TIMEUS_CUR_MAJOR(0) < nt)
-		;
-
-	*next_tick += bit_period_ticks;
-}
-
-static uint32_t get_next_tick(uint32_t delta)
-{
-	return GR_TIMEUS_CUR_MAJOR(0) + delta;
-}
-
-static void uart_bitbang_write_char(char c)
-{
-	int val;
-	int ones;
-	int i;
-	uint32_t next_tick;
-
-	interrupt_disable();
-
-	next_tick = get_next_tick(bit_period_ticks);
-
-	/* Start bit. */
-	gpio_set_level(bitbang_config.tx_gpio, 0);
-	wait_ticks(&next_tick);
-
-	/* 8 data bits. */
-	ones = 0;
-	for (i = 0; i < 8; i++) {
-		val = !!(c & BIT(i));
-		gpio_set_level(bitbang_config.tx_gpio, val);
-
-		/* Count 1's in order to handle parity bit. */
-		ones += val;
-		wait_ticks(&next_tick);
-	}
-
-	/* Optional parity. */
-	if (set_parity != PARITY_TYPE_NONE) {
-		gpio_set_level(bitbang_config.tx_gpio,
-			       (set_parity == PARITY_TYPE_ODD) ^ (ones & 1));
-		wait_ticks(&next_tick);
-	}
-
-	/* 1 stop bit. */
-	gpio_set_level(bitbang_config.tx_gpio, 1);
-
-	/*
-	 * Re-enable interrupts early: this could be the last byte and the
-	 * response could come very soon, we don't want to waste time enabling
-	 * interrupts AFTER stop bit is completed.
-	 */
-	interrupt_enable();
-	wait_ticks(&next_tick);
-}
-
-void uart_bitbang_drain_tx_queue(struct queue const *q)
-{
-	uint8_t c;
-
-	while (queue_count(q)) {
-		QUEUE_REMOVE_UNITS(q, &c, 1);
-		uart_bitbang_write_char(c);
-	}
-}
-
-static int uart_bitbang_receive_char(uint8_t *rxed_char, uint32_t *next_tick)
-{
-	uint8_t rx_char;
-	int i;
-	int ones;
-	int parity_bit;
-	int stop_bit;
-
-#if BITBANG_DEBUG
-	rx_buff_rx_char_cnt++;
-#endif /* BITBANG_DEBUG */
-
-	rx_char = 0;
-	ones = 0;
-
-	/* Wait 1 bit period for the start bit. */
-	wait_ticks(next_tick);
-
-	for (i = 0; i < 8; i++) {
-		if (gpio_get_level(bitbang_config.rx_gpio)) {
-			ones++;
-			rx_char |= BIT(i);
-		}
-		wait_ticks(next_tick);
-	}
-
-	/* optional parity or stop bit. */
-	parity_bit = gpio_get_level(bitbang_config.rx_gpio);
-
-	if (set_parity) {
-		wait_ticks(next_tick);
-		stop_bit = gpio_get_level(bitbang_config.rx_gpio);
-
-		if ((set_parity == PARITY_TYPE_ODD) !=
-			((ones + parity_bit) & 1)) {
-#if BITBANG_DEBUG
-			parity_err_cnt++;
-			parity_err_discard[parity_discard_idx] = rx_char;
-			parity_discard_idx = (parity_discard_idx + 1) %
-				DISCARD_LOG;
-#endif /* BITBANG_DEBUG */
-			return EC_ERROR_CRC;
-		}
-	} else {
-		/* If there's no parity, that _was_ the stop bit. */
-		stop_bit = parity_bit;
-	}
-
-
-	/* Check that the stop bit is valid. */
-	if (stop_bit != 1) {
-#if BITBANG_DEBUG
-		stop_bit_err_cnt++;
-		stop_bit_discard[stop_bit_discard_idx] = rx_char;
-		stop_bit_discard_idx = (stop_bit_discard_idx + 1) % DISCARD_LOG;
-#endif /* BITBANG_DEBUG */
-		return EC_ERROR_CRC;
-	}
-
-	/* Place the received char in the RX buffer. */
-#if BITBANG_DEBUG
-	rx_buff_inserted_cnt++;
-#endif /* BITBANG_DEBUG */
-
-	*rxed_char = rx_char;
-
-	return EC_SUCCESS;
-}
-
-void __attribute__((used)) uart_bitbang_irq(void)
-{
-	uint8_t rx_buffer[RX_BUF_SIZE];
-	size_t i = 0;
-	uint32_t next_tick;
-
-	/* Empirically chosen IRQ latency compensation. */
-	next_tick = get_next_tick(bit_period_ticks  - 40);
-	do {
-		uint32_t max_time;
-		int rv;
-new_char:
-		rv = uart_bitbang_receive_char(rx_buffer + i, &next_tick);
-		gpio_clear_pending_interrupt(bitbang_config.rx_gpio);
-
-		if (rv != EC_SUCCESS)
-			break;
-
-		if (++i == RX_BUF_SIZE)
-			break;
-		/*
-		 * For the duration of one byte wait for another byte from the
-		 * EC.
-		 */
-		max_time = GR_TIMEUS_CUR_MAJOR(0) + bit_period_ticks * 10;
-		while (GR_TIMEUS_CUR_MAJOR(0) < max_time) {
-			if (!gpio_get_level(bitbang_config.rx_gpio)) {
-				next_tick = get_next_tick(bit_period_ticks);
-				goto new_char;
-			}
-		}
-
-	} while (0);
-
-	QUEUE_ADD_UNITS(bitbang_config.uart_in, rx_buffer, i);
-}
-
-#if BITBANG_DEBUG
-static int write_test_pattern(int pattern_idx)
-{
-	switch (pattern_idx) {
-	case 0:
-		uart_bitbang_write_char(uart, 'a');
-		uart_bitbang_write_char(uart, 'b');
-		uart_bitbang_write_char(uart, 'c');
-		uart_bitbang_write_char(uart, '\n');
-		ccprintf("wrote: 'abc\\n'\n");
-		break;
-
-	case 1:
-		uart_bitbang_write_char(uart, 0xAA);
-		uart_bitbang_write_char(uart, 0xCC);
-		uart_bitbang_write_char(uart, 0x55);
-		ccprintf("wrote: '0xAA 0xCC 0x55'\n");
-		break;
-
-	default:
-		ccprintf("unknown test pattern\n");
-		return EC_ERROR_INVAL;
-	}
-
-	return EC_SUCCESS;
-}
-#endif /* BITBANG_DEBUG */
-
-static int command_bitbang(int argc, char **argv)
-{
-	int baud_rate;
-	uint32_t parity;
-	int rv;
-
-	if (argc > 1) {
-		if (argc == 3) {
-			if (!strcasecmp("disable", argv[2])) {
-				bitbang_wanted = 0;
-				ccd_update_state();
-				return EC_SUCCESS;
-			}
-			return EC_ERROR_PARAM2;
-		}
-
-		if (argc == 4) {
-#if BITBANG_DEBUG
-			if (!strncasecmp("test", argv[2], 4))
-				return write_test_pattern(atoi(argv[3]));
-#endif /* BITBANG_DEBUG */
-
-			baud_rate = atoi(argv[2]);
-			for (parity = PARITY_TYPE_NONE;
-			     parity < PARITY_TYPE_MAX;
-			     ++parity)
-				if (!strcasecmp(parity_type_name[parity],
-						argv[3]))
-					break;
-			if (parity >= PARITY_TYPE_MAX)
-				return EC_ERROR_PARAM3;
-
-			rv = uart_bitbang_config(baud_rate, parity);
-			if (rv)
-				return rv;
-
-			if (servo_is_connected())
-				ccprintf("%sing superseded by servo\n",
-					feature_name);
-
-			bitbang_wanted = 1;
-			ccd_update_state();
-			return EC_SUCCESS;
-		}
-
-		return EC_ERROR_PARAM_COUNT;
-	}
-
-	if (!uart_bitbang_is_enabled()) {
-		ccprintf("%s mode disabled.\n", feature_name);
-	} else {
-		ccprintf("baud rate - parity\n");
-		ccprintf("  %6d    ", bitbang_config.baud_rate);
-		ccprintf("%s\n", parity_type_name[
-			(bitbang_config.parity < PARITY_TYPE_MAX) ?
-			bitbang_config.parity : PARITY_TYPE_NONE]);
-	}
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(bitbang, command_bitbang,
-			"<uart> <baud_rate> <odd,even,none> | <uart> disable "
-#if BITBANG_DEBUG
-			"| <uart> test <0, 1>"
-#endif /* BITBANG_DEBUG */
-			, "set bit bang mode");
-
-#if BITBANG_DEBUG
-static int command_bitbang_dump_stats(int argc, char **argv)
-{
-	int i;
-
-	if (argc == 2) {
-		/* Clear the counters. */
-		if (!strncasecmp(argv[1], "clear", 5)) {
-			parity_err_cnt = 0;
-			stop_bit_err_cnt = 0;
-			rx_buff_rx_char_cnt = 0;
-			read_char_cnt = 0;
-			rx_buff_inserted_cnt = 0;
-			return EC_SUCCESS;
-		}
-		return EC_ERROR_PARAM1;
-	}
-
-	ccprintf("Errors:\n");
-	ccprintf("%d Parity Errors\n", parity_err_cnt);
-	ccprintf("%d Stop Bit Errors\n", stop_bit_err_cnt);
-	ccprintf("Buffer info\n");
-	ccprintf("%d received\n", rx_buff_rx_char_cnt);
-	ccprintf("%d chars inserted\n", rx_buff_inserted_cnt);
-	ccprintf("%d chars read\n", read_char_cnt);
-	ccprintf("Discards\nparity: ");
-	ccprintf("[");
-	for (i = 0; i < DISCARD_LOG; i++)
-		ccprintf(" %02x ", parity_err_discard[i] & 0xFF);
-	ccprintf("]\n");
-	ccprintf("idx: %d\n", parity_discard_idx);
-	ccprintf("stop bit: ");
-	ccprintf("[");
-	for (i = 0; i < DISCARD_LOG; i++)
-		ccprintf(" %02x ", stop_bit_discard[i] & 0xFF);
-	ccprintf("]\n");
-	ccprintf("idx: %d\n", stop_bit_discard_idx);
-	cflush();
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(bbstats, command_bitbang_dump_stats,
-			"",
-			"dumps bitbang stats");
-#endif /* BITBANG_DEBUG */
diff --git a/chip/g/uart_bitbang.h b/chip/g/uart_bitbang.h
deleted file mode 100644
index 16952e35ab..0000000000
--- a/chip/g/uart_bitbang.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_CHIP_G_UART_BITBANG_H
-#define __CROS_EC_CHIP_G_UART_BITBANG_H
-
-/* UART Bit Banging */
-
-#include "common.h"
-#include "gpio.h"
-#include "queue.h"
-
-struct uart_bitbang_properties {
-	enum gpio_signal tx_gpio;
-	enum gpio_signal rx_gpio;
-	uint32_t tx_pinmux_reg;
-	uint32_t tx_pinmux_regval;
-	uint32_t rx_pinmux_reg;
-	uint32_t rx_pinmux_regval;
-	struct queue const *uart_in;
-	uint32_t baud_rate;
-	uint16_t rx_irq;
-	uint8_t uart;
-	uint8_t parity;
-};
-
-/* In order to bitbang a UART, a board must define a bitbang_config. */
-extern struct uart_bitbang_properties bitbang_config;
-
-/**
- * Enable bit banging mode for a UART.
- *
- * The UART must have been configured first.
- */
-int uart_bitbang_enable(void);
-
-/**
- * Disable bit banging mode for a UART.
- */
-int uart_bitbang_disable(void);
-
-/**
- * Returns 1 if bit banging mode is enabled for the UART.
- */
-int uart_bitbang_is_enabled(void);
-
-/**
- * Returns 1 if bit banging mode is wanted for the UART.
- */
-int uart_bitbang_is_wanted(void);
-
-/**
- * Sample the RX line on a UART configured for bit banging mode.
- *
- * This is called when a falling edge is seen on the RX line and will attempt to
- * receive a character.  Incoming data with framing errors or parity errors will
- * be discarded.
- */
-void uart_bitbang_irq(void);
-
-void uart_bitbang_drain_tx_queue(struct queue const *q);
-
-#endif /* __CROS_EC_CHIP_G_UART_BITBANG_H */
diff --git a/chip/g/uartn.c b/chip/g/uartn.c
deleted file mode 100644
index 3f4b75b7e0..0000000000
--- a/chip/g/uartn.c
+++ /dev/null
@@ -1,155 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "clock.h"
-#include "common.h"
-#include "gpio.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "uart.h"
-#include "util.h"
-
-#define USE_UART_INTERRUPTS (!(defined(CONFIG_CUSTOMIZED_RO) && \
-			       defined(SECTION_IS_RO)))
-
-struct uartn_interrupts {
-	int tx_int;
-	int rx_int;
-};
-static struct uartn_interrupts interrupt[] = {
-	{GC_IRQNUM_UART0_TXINT, GC_IRQNUM_UART0_RXINT},
-	{GC_IRQNUM_UART1_TXINT, GC_IRQNUM_UART1_RXINT},
-	{GC_IRQNUM_UART2_TXINT, GC_IRQNUM_UART2_RXINT},
-};
-
-void uartn_tx_start(int uart)
-{
-	if (!uart_init_done())
-		return;
-
-	/* If interrupt is already enabled, nothing to do */
-	if (GR_UART_ICTRL(uart) & GC_UART_ICTRL_TX_MASK)
-		return;
-
-	/* Do not allow deep sleep while transmit in progress */
-	disable_sleep(SLEEP_MASK_UART);
-
-	/*
-	 * Re-enable the transmit interrupt, then forcibly trigger the
-	 * interrupt.  This works around a hardware problem with the
-	 * UART where the FIFO only triggers the interrupt when its
-	 * threshold is _crossed_, not just met.
-	 */
-	/* TODO(crosbug.com/p/33819): Do we need this hack here? Find out. */
-	REG_WRITE_MLV(GR_UART_ICTRL(uart), GC_UART_ICTRL_TX_MASK,
-		      GC_UART_ICTRL_TX_LSB, 1);
-	task_trigger_irq(interrupt[uart].tx_int);
-}
-
-void uartn_tx_stop(int uart)
-{
-	/* Disable the TX interrupt */
-	REG_WRITE_MLV(GR_UART_ICTRL(uart), GC_UART_ICTRL_TX_MASK,
-		      GC_UART_ICTRL_TX_LSB, 0);
-
-	/* Re-allow deep sleep */
-	enable_sleep(SLEEP_MASK_UART);
-}
-
-int uartn_tx_in_progress(int uart)
-{
-	/* Transmit is in progress unless the TX FIFO is empty and idle. */
-	return (GR_UART_STATE(uart) & (GC_UART_STATE_TXIDLE_MASK |
-				       GC_UART_STATE_TXEMPTY_MASK)) !=
-		(GC_UART_STATE_TXIDLE_MASK | GC_UART_STATE_TXEMPTY_MASK);
-}
-
-void uartn_tx_flush(int uart)
-{
-	/* Wait until TX FIFO is idle. */
-	while (uartn_tx_in_progress(uart))
-		;
-}
-
-int uartn_tx_ready(int uart)
-{
-	/* True if the TX buffer is not completely full */
-	return !(GR_UART_STATE(uart) & GC_UART_STATE_TX_MASK);
-}
-
-int uartn_rx_available(int uart)
-{
-	/* True if the RX buffer is not completely empty. */
-	return !(GR_UART_STATE(uart) & GC_UART_STATE_RXEMPTY_MASK);
-}
-
-void uartn_write_char(int uart, char c)
-{
-	/* Wait for space in transmit FIFO. */
-	while (!uartn_tx_ready(uart))
-		;
-
-	GR_UART_WDATA(uart) = c;
-}
-
-int uartn_read_char(int uart)
-{
-	return GR_UART_RDATA(uart);
-}
-
-void uartn_disable_interrupt(int uart)
-{
-	task_disable_irq(interrupt[uart].tx_int);
-	task_disable_irq(interrupt[uart].rx_int);
-}
-
-void uartn_enable_interrupt(int uart)
-{
-	task_enable_irq(interrupt[uart].tx_int);
-	task_enable_irq(interrupt[uart].rx_int);
-}
-
-
-void uartn_enable(int uart)
-{
-	/* Enable TX and RX. Disable HW flow control and loopback. */
-	GR_UART_CTRL(uart) = 0x03;
-}
-
-/* Disable TX, RX, HW flow control, and loopback */
-void uartn_disable(int uart)
-{
-	GR_UART_CTRL(uart) = 0;
-}
-
-int uartn_is_enabled(int uart)
-{
-	return !!(GR_UART_CTRL(uart) & 0x03);
-}
-
-void uartn_init(int uart)
-{
-	long long setting = (16 * BIT(UART_NCO_WIDTH) *
-			     (long long)CONFIG_UART_BAUD_RATE / PCLK_FREQ);
-
-	/* set frequency */
-	GR_UART_NCO(uart) = setting;
-
-	/*
-	 * Interrupt when RX fifo has anything, when TX fifo <= half
-	 * empty and reset (clear) both FIFOs
-	 */
-	GR_UART_FIFO(uart) = 0x63;
-
-	/* enable RX interrupts in block */
-	/* Note: doesn't do anything unless turned on in NVIC */
-	GR_UART_ICTRL(uart) = 0x02;
-
-#if USE_UART_INTERRUPTS
-	/* Enable interrupts for UART */
-	uartn_enable_interrupt(uart);
-#endif
-}
diff --git a/chip/g/uartn.h b/chip/g/uartn.h
deleted file mode 100644
index bfb7772518..0000000000
--- a/chip/g/uartn.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_UARTN_H
-#define __CROS_EC_UARTN_H
-
-#include "common.h"
-
-/**
- * Initialize the UART module.
- */
-void uartn_init(int uart);
-
-/**
- * Flush the transmit FIFO.
- */
-void uartn_tx_flush(int uart);
-
-/**
- * Return non-zero if there is room to transmit a character immediately.
- */
-int uartn_tx_ready(int uart);
-
-/**
- * Return non-zero if a transmit is in progress.
- */
-int uartn_tx_in_progress(int uart);
-
-/*
- * Return non-zero if the UART has a character available to read.
- */
-int uartn_rx_available(int uart);
-
-/**
- * Send a character to the UART data register.
- *
- * If the transmit FIFO is full, blocks until there is space.
- *
- * @param c		Character to send.
- */
-void uartn_write_char(int uart, char c);
-
-/**
- * Read one char from the UART data register.
- *
- * @return		The character read.
- */
-int uartn_read_char(int uart);
-
-/**
- * Disable all UART related IRQs.
- *
- * Used to avoid concurrent accesses on UART management variables.
- */
-void uartn_disable_interrupt(int uart);
-
-/**
- * Re-enable UART IRQs.
- */
-void uartn_enable_interrupt(int uart);
-
-/**
- * Re-enable the UART transmit interrupt.
- *
- * This also forces triggering a UART interrupt, if the transmit interrupt was
- * disabled.
- */
-void uartn_tx_start(int uart);
-
-/**
- * Disable the UART transmit interrupt.
- */
-void uartn_tx_stop(int uart);
-
-/**
- * Return non-zero if TX is connected for the UART.
- *
- * @param uart		UART to check
- * @return 1 if TX pin is connected, 0 if disconnected.
- */
-int uart_tx_is_connected(int uart);
-
-/* Connect TX pin for the UART */
-void uartn_tx_connect(int uart);
-
-/* Disconnect TX pin for the UART */
-void uartn_tx_disconnect(int uart);
-
-/**
- * Return non-zero if TX and RX are enabled for the UART.
- *
- * Note that TX won't be connected unless uart_tx_is_connected() is also
- * non-zero.
- *
- * @param uart		UART to check
- * @return 1 if UART is enabled, 0 if disabled.
- */
-int uartn_is_enabled(int uart);
-
-/**
- * Enable TX and RX for the UART. Disable HW flow control and loopback.
- *
- * @param uart		UART to enable
- *
- * Note that this does NOT connect the TX pin for the UART; that must be done
- * explicitly via uartn_tx_connect().
- */
-void uartn_enable(int uart);
-
-/**
- * Disable TX, RX, HW flow control, and loopback.
- *
- * @param uart		UART to disable
- *
- * Note that this does NOT disconnect the TX pin for the UART; that must be
- * done explicitly via uartn_tx_disconnect().
- */
-void uartn_disable(int uart);
-#endif  /* __CROS_EC_UARTN_H */
diff --git a/chip/g/upgrade.c b/chip/g/upgrade.c
deleted file mode 100644
index e7c6120615..0000000000
--- a/chip/g/upgrade.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "config.h"
-#include "console.h"
-#include "endian.h"
-#include "extension.h"
-#include "flash.h"
-#include "flash_info.h"
-#include "hooks.h"
-#include "signed_header.h"
-#include "system.h"
-#include "upgrade_fw.h"
-#include "util.h"
-
-#define CPRINTF(format, args...) cprintf(CC_EXTENSION, format, ## args)
-
-static void deferred_reboot(void)
-{
-	system_reset(SYSTEM_RESET_MANUALLY_TRIGGERED | SYSTEM_RESET_HARD);
-}
-DECLARE_DEFERRED(deferred_reboot);
-
-#define MAX_REBOOT_TIMEOUT_MS 1000
-
-/*
- * Verify if the header at the passed in flash offset needs to be restored,
- * and restore it if so. If this is an RO header - enable writing into that RO
- * section (the currently active RO writes can not be enabled).
- *
- * Return true if a corruption was detected and restored.
- */
-static int header_restored(uint32_t offset)
-{
-	struct SignedHeader *header;
-	uint32_t new_size;
-
-	header = (struct SignedHeader *)(CONFIG_PROGRAM_MEMORY_BASE + offset);
-
-	new_size = header->image_size;
-	if (!(new_size & TOP_IMAGE_SIZE_BIT))
-		return 0;
-
-	new_size &= ~TOP_IMAGE_SIZE_BIT;
-	/*
-	 * Clear only in case the size is sensible (i.e. not set to all
-	 * ones).
-	 */
-	if (new_size > CONFIG_RW_SIZE)
-		return 0;
-
-	if ((offset == CONFIG_RO_MEM_OFF) || (offset == CHIP_RO_B_MEM_OFF))
-		flash_open_ro_window(offset, sizeof(struct SignedHeader));
-
-	return flash_physical_write(offset + offsetof(struct SignedHeader,
-						      image_size),
-				    sizeof(header->image_size),
-				    (char *)&new_size) == EC_SUCCESS;
-}
-
-/*
- * Try restoring inactive RO and RW headers, Return the number of restored
- * headers.
- *
- * Since the RO could come with new keys, we don't want create a situation
- * where the RO is restored and the RW is not (say due to power failure or an
- * exception, etc.). So, restore the RW first, and then the RO. In this case
- * if restoring failed, the currently running RO is still guaranteed to boot
- * and start the currently running RW, so the update could be attempted again.
- */
-static uint8_t headers_restored(void)
-{
-	uint8_t total_restored;
-
-	/* Examine the RW first. */
-	if (system_get_image_copy() == EC_IMAGE_RW)
-		total_restored = header_restored(CONFIG_RW_B_MEM_OFF);
-	else
-		total_restored = header_restored(CONFIG_RW_MEM_OFF);
-
-	/* Now the RO */
-	if (system_get_ro_image_copy() == EC_IMAGE_RO)
-		total_restored += header_restored(CHIP_RO_B_MEM_OFF);
-	else
-		total_restored += header_restored(CONFIG_RO_MEM_OFF);
-
-	return total_restored;
-}
-
-/*
- * The TURN_UPDATE_ON command comes with a single parameter, which is a 16 bit
- * integer value of the number of milliseconds to wait before reboot in case
- * there has been an update waiting.
- *
- * Maximum wait time is 1000 ms.
- *
- * If the requested timeout exceeds the allowed maximum, or the command is
- * malformed, a protocol error is returned.
- *
- * If there was no errors, the number of restored headers is returned to the
- * host in a single byte.
- *
- * If at least one header was restored AND the host supplied a nonzero timeout
- * value, the H1 will be reset after this many milliseconds.
- *
- * Sending this command with the zero timeout value results in reporting to
- * the host how many headers were restored, the reset is not triggered.
- */
-static enum vendor_cmd_rc turn_update_on(enum vendor_cmd_cc code,
-					 void *buf,
-					 size_t input_size,
-					 size_t *response_size)
-{
-	uint16_t timeout;
-	uint8_t *response;
-
-	/* Just in case. */
-	*response_size = 0;
-
-	if (input_size < sizeof(uint16_t)) {
-		CPRINTF("%s: incorrect request size %d\n",
-			__func__, input_size);
-		return VENDOR_RC_BOGUS_ARGS;
-	}
-
-	/* Retrieve the requested timeout. */
-	memcpy(&timeout, buf, sizeof(timeout));
-	timeout = be16toh(timeout);
-
-	if (timeout > MAX_REBOOT_TIMEOUT_MS) {
-		CPRINTF("%s: incorrect timeout value %d\n",
-			__func__, timeout);
-		return VENDOR_RC_BOGUS_ARGS;
-	}
-
-	*response_size = 1;
-	response = buf;
-
-	*response = headers_restored();
-	if (*response && timeout) {
-		/*
-		 * At least one header was restored, and timeout is not zero,
-		 * set up the reboot.
-		 */
-		CPRINTF("%s: rebooting in %d ms\n", __func__, timeout);
-		hook_call_deferred(&deferred_reboot_data, timeout * MSEC);
-	}
-
-	return VENDOR_RC_SUCCESS;
-}
-DECLARE_VENDOR_COMMAND(VENDOR_CC_TURN_UPDATE_ON, turn_update_on);
-
-/* This command's implementation is shared with USB updater. */
-DECLARE_EXTENSION_COMMAND(EXTENSION_FW_UPGRADE, fw_upgrade_command_handler);
diff --git a/chip/g/upgrade_fw.c b/chip/g/upgrade_fw.c
deleted file mode 100644
index 1afadbc280..0000000000
--- a/chip/g/upgrade_fw.c
+++ /dev/null
@@ -1,535 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "config.h"
-
-#include "board_id.h"
-#include "byteorder.h"
-#include "compile_time_macros.h"
-#include "console.h"
-#include "cryptoc/sha.h"
-#include "dcrypto/dcrypto.h"
-#include "extension.h"
-#include "flash.h"
-#include "flash_info.h"
-#include "hooks.h"
-#include "registers.h"
-#include "signed_header.h"
-#include "system.h"
-#include "system_chip.h"
-#include "uart.h"
-#include "upgrade_fw.h"
-
-#define CPRINTF(format, args...) cprintf(CC_EXTENSION, format, ## args)
-
-/*
- * This structure defines flash offset ranges of the RO and RW images which
- * are not currently active and as such could be overwritten with an update.
- */
-struct {
-	uint32_t ro_base_offset;
-	uint32_t ro_top_offset;
-	uint32_t rw_base_offset;
-	uint32_t rw_top_offset;
-} valid_sections;
-
-/* Pick sections where updates can go to based on current code addresses. */
-static void set_valid_sections(void)
-{
-	switch (system_get_ro_image_copy()) {
-	case EC_IMAGE_RO:
-		valid_sections.ro_base_offset = CHIP_RO_B_MEM_OFF;
-		break;
-	case EC_IMAGE_RO_B:
-		valid_sections.ro_base_offset = CONFIG_RO_MEM_OFF;
-		break;
-	default:
-		CPRINTF("Failed to set RO image offsets\n");
-		return;
-	}
-
-	switch (system_get_image_copy()) {
-	case EC_IMAGE_RW:
-		valid_sections.rw_base_offset = CONFIG_RW_B_MEM_OFF;
-		break;
-	case EC_IMAGE_RW_B:
-		valid_sections.rw_base_offset = CONFIG_RW_MEM_OFF;
-		break;
-	default:
-		CPRINTF("Failed to set RW image offsets\n");
-		return;
-	}
-
-	valid_sections.ro_top_offset = valid_sections.ro_base_offset +
-		CONFIG_RO_SIZE - 0x800; /* 2K for certs! */
-
-	valid_sections.rw_top_offset = valid_sections.rw_base_offset +
-		CONFIG_RW_SIZE;
-}
-
-/*
- * Verify that the passed in block fits into the valid area. If it does, and
- * is destined to the base address of the area - erase the area contents.
- *
- * Return success, or indication of an erase failure or chunk not fitting into
- * valid area.
- */
-static uint8_t check_update_chunk(uint32_t block_offset, size_t body_size)
-{
-	uint32_t base;
-	uint32_t size;
-
-	/* Is this an RW chunk? */
-	if (valid_sections.rw_top_offset &&
-	    (block_offset >= valid_sections.rw_base_offset) &&
-	    ((block_offset + body_size) <= valid_sections.rw_top_offset)) {
-
-		base = valid_sections.rw_base_offset;
-		size = valid_sections.rw_top_offset -
-			 valid_sections.rw_base_offset;
-		/*
-		 * If this is the first chunk for this section, it needs to
-		 * be erased.
-		 */
-		if (block_offset == valid_sections.rw_base_offset) {
-			if (flash_physical_erase(base, size) != EC_SUCCESS) {
-				CPRINTF("%s:%d erase failure of 0x%x..+0x%x\n",
-					__func__, __LINE__, base, size);
-				return UPGRADE_ERASE_FAILURE;
-			}
-		}
-
-		return UPGRADE_SUCCESS;
-	}
-
-	/* Is this an RO chunk? */
-	if (valid_sections.ro_top_offset &&
-	    (block_offset >= valid_sections.ro_base_offset) &&
-	    ((block_offset + body_size) <= valid_sections.ro_top_offset)) {
-		/*
-		 * If this is the first chunk for this section, it needs to
-		 * be erased.
-		 */
-		if (block_offset == valid_sections.ro_base_offset) {
-			uint32_t base;
-			uint32_t size;
-
-			base = valid_sections.ro_base_offset;
-			size = valid_sections.ro_top_offset -
-				valid_sections.ro_base_offset;
-			/* backup RO area write access needs to be enabled. */
-			flash_open_ro_window(base, size);
-			if (flash_physical_erase(base, size) != EC_SUCCESS) {
-				CPRINTF("%s:%d erase failure of 0x%x..+0x%x\n",
-					__func__, __LINE__, base, size);
-				return UPGRADE_ERASE_FAILURE;
-			}
-		}
-		return UPGRADE_SUCCESS;
-	}
-
-	CPRINTF("%s:%d %x, %d ro base %x top %x, rw base %x top %x\n",
-		__func__, __LINE__,
-		block_offset, body_size,
-		valid_sections.ro_base_offset,
-		valid_sections.ro_top_offset,
-		valid_sections.rw_base_offset,
-		valid_sections.rw_top_offset);
-
-	return UPGRADE_BAD_ADDR;
-}
-
-int usb_pdu_valid(struct upgrade_command *cmd_body,  size_t cmd_size)
-{
-	uint8_t sha1_digest[SHA_DIGEST_SIZE];
-	size_t body_size = cmd_size - offsetof(struct update_frame_header,
-					       cmd.block_base);
-
-	/* Check if the block was received properly. */
-	DCRYPTO_SHA1_hash((uint8_t *)&cmd_body->block_base,
-			  body_size + sizeof(cmd_body->block_base),
-			  sha1_digest);
-	if (memcmp(sha1_digest, &cmd_body->block_digest,
-		   sizeof(cmd_body->block_digest))) {
-		CPRINTF("%s:%d sha1 %x not equal received %x\n",
-			__func__, __LINE__,
-			*(uint32_t *)sha1_digest, cmd_body->block_digest);
-		return 0;
-	}
-
-	return 1;
-}
-
-#ifdef CR50_RELAXED
-#ifndef CONFIG_IGNORE_G_UPDATE_CHECKS
-#define CONFIG_IGNORE_G_UPDATE_CHECKS
-#endif
-#endif
-
-#ifndef CONFIG_IGNORE_G_UPDATE_CHECKS
-/* Compare two versions, return True if the new version is older. */
-static int new_is_older(const struct SignedHeader *new,
-			const struct SignedHeader *old)
-{
-	if (new->epoch_ != old->epoch_)
-		return new->epoch_ < old->epoch_;
-
-	if (new->major_ != old->major_)
-		return new->major_ < old->major_;
-
-
-	return new->minor_ < old->minor_;
-}
-
-/*
- * Check if this chunk of data is a rollback attempt, or is unaligned,
- * overlaps RO or RW header, or would cause a board ID mismatch if attempted
- * to run.
- *
- * Return False if there is any of the above problems and set the passed in
- * error_code pointer to the proper error_code.
- */
-static int contents_allowed(uint32_t block_offset,
-			    size_t body_size, void *upgrade_data,
-			    uint8_t *error_code)
-{
-	/* Pointer to RO or RW header in flash, to compare against. */
-	const struct SignedHeader *header;
-	int is_rw_header = 0;
-
-	if (block_offset == valid_sections.ro_base_offset) {
-		header = (const struct SignedHeader *)
-			get_program_memory_addr(system_get_ro_image_copy());
-	} else if (block_offset == valid_sections.rw_base_offset) {
-		header = (const struct SignedHeader *)
-			get_program_memory_addr(system_get_image_copy());
-		is_rw_header = 1;
-	} else {
-
-		/*
-		 * The received block is not destined to a header directly,
-		 * but does it overlap with a header by any chance?
-		 */
-		int i;
-		/* Base offsets of valid headers in flash. */
-		uint32_t bases[] = { valid_sections.ro_base_offset,
-				     valid_sections.rw_base_offset };
-		/* Range of offsets this block is covering. */
-		uint32_t range[] = { block_offset, block_offset + body_size };
-
-		for (i = 0; i < ARRAY_SIZE(bases); i++) {
-			int j;
-
-			for (j = 0; j < ARRAY_SIZE(range); j++) {
-				if ((range[j] >= bases[i]) &&
-				    (range[j] <
-				     (bases[i] +
-				      sizeof(struct SignedHeader)))) {
-					CPRINTF("%s:"
-						" unaligned block overlaps\n",
-						__func__);
-					*error_code =
-						UPGRADE_UNALIGNED_BLOCK_ERROR;
-					return 0;
-				}
-			}
-		}
-
-		return 1;
-	}
-
-	/* This block is a header (ro or rw) of the new image. */
-	if (body_size < sizeof(struct SignedHeader)) {
-		CPRINTF("%s: block too short\n", __func__);
-		*error_code = UPGRADE_TRUNCATED_HEADER_ERROR;
-		return 0;
-	}
-
-	/* upgrade_data is the new header. */
-	if (new_is_older(upgrade_data, header)) {
-		CPRINTF("%s: rejecting an older header.\n", __func__);
-		*error_code = UPGRADE_ROLLBACK_ERROR;
-		return 0;
-	}
-
-	if (is_rw_header && board_id_mismatch(upgrade_data)) {
-		CPRINTF("%s: rejecting Board ID mismatch.\n", __func__);
-		*error_code = UPGRADE_BOARD_ID_ERROR;
-		return 0;
-	}
-
-	return 1;
-}
-
-/*
- * Previously written offsets, index 0 is for the RO section, index 1 - for
- * RW. Keeping track of the previously written offset and allowing only higher
- * offsets for the following writes allows to prevent flash destroying attacks
- * when the perpetrator keeps repetitively writing to the same flash area.
- *
- * Need to preset the value for RO to the negative number so that the first
- * frame of the RO_A update which comes at offset zero does not get rejected.
- */
-static int prev_offsets[2] = {-SIGNED_TRANSFER_SIZE};
-static uint64_t prev_timestamp;
-#define BACKOFF_TIME (60 * SECOND)
-
-/*
- * Match the passed in offset of a chunk to be written into flash into the RO
- * or RW space for using as the index in prev_offsets array.
- *
- * The passed in offset is guaranteed to be falling into either RW or RO space
- * as defined by the valid_sections structure contents.
- *
- * The prev_offsets array uses index 0 for RO and index 1 for RW.
- */
-static int offset_to_index(uint32_t block_offset)
-{
-	/*
-	 * Return index 1 if the offset falls into RW space, index 0
-	 * otherwise.
-	 */
-	return (block_offset >= valid_sections.rw_base_offset) &&
-	       (block_offset < valid_sections.rw_top_offset);
-}
-
-static int chunk_came_too_soon(uint32_t block_offset)
-{
-	/*
-	 * If it has been BACKOFF_TIME since the last time we wrote to a block
-	 * or since the last boot, the write is ok.
-	 */
-	if ((get_time().val - prev_timestamp) > BACKOFF_TIME) {
-		/*
-		 * The Cr50 firmware update utility, gsctool, makes sure that
-		 * in case both RW and RO need to be updated, the RW is
-		 * transferred first.
-		 *
-		 * This means that the RW offset in the prev_offsets array
-		 * does not have to be preset, it will be set by
-		 * new_chunk_written() below after the very first RW chunk is
-		 * processed.
-		 *
-		 * The RO offset in the prev_offset array is a different,
-		 * because the RO will be written after RW but before the
-		 * BACKOFF_TIME timeout expires, i.e. there will be no chance
-		 * for new_chunk_written() run for RO unconditionally.
-		 *
-		 * There also is a problem when just the RO_A is written - it
-		 * comes at offset zero, and would be rejected if prev_offsets
-		 * value for RO were set to zero.
-		 *
-		 * A simple fix for both issues is to preset the prev_offset
-		 * value for RO to the value which would allow any possible RO
-		 * offset to be accepted.
-		 */
-		prev_offsets[0] = -SIGNED_TRANSFER_SIZE;
-		return 0;
-	}
-
-	if (!prev_timestamp) {
-		int hard_reset = system_get_reset_flags() & EC_RESET_FLAG_HARD;
-
-		/*
-		 * If we just recovered from a hard reset, we have to wait until
-		 * backoff time to accept an update. All other resets can accept
-		 * updates immediately.
-		 */
-		if (hard_reset)
-			CPRINTF("%s: rejecting a write soon after hard reset\n",
-				__func__);
-		return hard_reset;
-	}
-
-	if ((int)block_offset >= (prev_offsets[offset_to_index(block_offset)] +
-				  SIGNED_TRANSFER_SIZE))
-		return 0;
-
-	CPRINTF("%s: rejecting a write to the same block\n", __func__);
-	return 1;
-}
-
-static void new_chunk_written(uint32_t block_offset)
-{
-	prev_timestamp = get_time().val;
-	prev_offsets[offset_to_index(block_offset)] = block_offset;
-}
-#else
-static int chunk_came_too_soon(uint32_t block_offset)
-{
-	return 0;
-}
-
-static void new_chunk_written(uint32_t block_offset)
-{
-}
-
-static int contents_allowed(uint32_t block_offset,
-			    size_t body_size, void *upgrade_data,
-			    uint8_t *error_code)
-{
-#ifndef CR50_RELAXED
-#ifdef CONFIG_BOARD_ID_SUPPORT
-	if (block_offset == valid_sections.rw_base_offset) {
-		/* This block is a rw header of the new image. */
-		if (body_size < sizeof(struct SignedHeader)) {
-			CPRINTF("%s: block too short\n", __func__);
-			*error_code = UPGRADE_TRUNCATED_HEADER_ERROR;
-			return 0;
-		}
-		if (board_id_mismatch(upgrade_data)) {
-			CPRINTF("%s: rejecting Board ID mismatch.\n", __func__);
-			*error_code = UPGRADE_BOARD_ID_ERROR;
-			return 0;
-		}
-	}
-#endif
-#endif
-	return 1;
-}
-#endif
-
-void fw_upgrade_command_handler(void *body,
-				size_t cmd_size,
-				size_t *response_size)
-{
-	struct upgrade_command *cmd_body = body;
-	void *upgrade_data;
-	uint8_t *error_code = body;  /* Cache the address for code clarity. */
-	size_t body_size;
-	uint32_t block_offset;
-
-	*response_size = 1; /* One byte response unless this is a start PDU. */
-
-	if (cmd_size < sizeof(struct upgrade_command)) {
-		CPRINTF("%s:%d\n", __func__, __LINE__);
-		*error_code = UPGRADE_GEN_ERROR;
-		return;
-	}
-	body_size = cmd_size - sizeof(struct upgrade_command);
-
-	if (!cmd_body->block_base && !body_size) {
-		struct first_response_pdu *rpdu = body;
-		const struct SignedHeader *header;
-
-		/*
-		 * This is the connection establishment request, the response
-		 * allows the server to decide what sections of the image to
-		 * send to program into the flash.
-		 */
-
-		/* First, prepare the response structure. */
-		memset(rpdu, 0, sizeof(*rpdu));
-		*response_size = sizeof(*rpdu);
-		rpdu->protocol_version = htobe32(UPGRADE_PROTOCOL_VERSION);
-
-		/*
-		 * Determine the valid upgrade sections.
-		 */
-		set_valid_sections();
-
-		/*
-		 * If there have been any problems when determining the valid
-		 * Sections offsets/sizes - return an error code.
-		 */
-		if (!valid_sections.ro_top_offset ||
-		    !valid_sections.rw_top_offset) {
-			CPRINTF("%s:%d\n", __func__, __LINE__);
-			rpdu->return_value = htobe32(UPGRADE_GEN_ERROR);
-			return;
-		}
-
-		rpdu->backup_ro_offset =
-			htobe32(valid_sections.ro_base_offset);
-
-		rpdu->backup_rw_offset =
-			htobe32(valid_sections.rw_base_offset);
-
-		/* RO header information. */
-		header = (const struct SignedHeader *)
-			get_program_memory_addr(system_get_ro_image_copy());
-		rpdu->shv[0].minor = htobe32(header->minor_);
-		rpdu->shv[0].major = htobe32(header->major_);
-		rpdu->shv[0].epoch = htobe32(header->epoch_);
-		/* New with protocol version 5 */
-		rpdu->keyid[0] = htobe32(header->keyid);
-
-		/* RW header information. */
-		header = (const struct SignedHeader *)
-			get_program_memory_addr(system_get_image_copy());
-		rpdu->shv[1].minor = htobe32(header->minor_);
-		rpdu->shv[1].major = htobe32(header->major_);
-		rpdu->shv[1].epoch = htobe32(header->epoch_);
-		/* New with protocol version 5 */
-		rpdu->keyid[1] = htobe32(header->keyid);
-		return;
-	}
-
-	block_offset = be32toh(cmd_body->block_base);
-
-	if (!usb_pdu_valid(cmd_body, cmd_size)) {
-		*error_code = UPGRADE_DATA_ERROR;
-		return;
-	}
-
-	upgrade_data = cmd_body + 1;
-	if (!contents_allowed(block_offset, body_size,
-			      upgrade_data, error_code))
-		return;
-
-	/* Check if the block will fit into the valid area. */
-	*error_code = check_update_chunk(block_offset, body_size);
-	if (*error_code)
-		return;
-
-	if (chunk_came_too_soon(block_offset)) {
-		*error_code = UPGRADE_RATE_LIMIT_ERROR;
-		return;
-	}
-
-	if ((block_offset == valid_sections.ro_base_offset) ||
-	    (block_offset == valid_sections.rw_base_offset)) {
-		/*
-		 * This is the header coming, let's corrupt it so that it does
-		 * not run until it's time to switch.
-		 */
-		struct SignedHeader *header;
-
-		header = (struct SignedHeader *) upgrade_data;
-
-		/*
-		 * Set the top bit of the size field. It will be impossible to
-		 * run this image until this bit is erased.
-		 */
-		header->image_size |= TOP_IMAGE_SIZE_BIT;
-	}
-
-	CPRINTF("at 0x%x\n", block_offset + CONFIG_PROGRAM_MEMORY_BASE);
-	if (flash_physical_write(block_offset, body_size, upgrade_data)
-	    != EC_SUCCESS) {
-		*error_code = UPGRADE_WRITE_FAILURE;
-		CPRINTF("%s:%d upgrade write error\n",	__func__, __LINE__);
-		return;
-	}
-
-	new_chunk_written(block_offset);
-
-	/* Verify that data was written properly. */
-	if (memcmp(upgrade_data, (void *)
-		   (block_offset + CONFIG_PROGRAM_MEMORY_BASE),
-		   body_size)) {
-		*error_code = UPGRADE_VERIFY_ERROR;
-		CPRINTF("%s:%d upgrade verification error\n",
-			__func__, __LINE__);
-		return;
-	}
-
-	*error_code = UPGRADE_SUCCESS;
-}
-
-void fw_upgrade_complete(void)
-{
-	system_clear_retry_counter();
-}
diff --git a/chip/g/upgrade_fw.h b/chip/g/upgrade_fw.h
deleted file mode 100644
index d3414b103e..0000000000
--- a/chip/g/upgrade_fw.h
+++ /dev/null
@@ -1,152 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __EC_CHIP_G_UPGRADE_FW_H
-#define __EC_CHIP_G_UPGRADE_FW_H
-
-#include <stddef.h>
-
-#include "common.h"  /* For __packed. */
-
-/*
- * This file contains structures used to facilitate cr50 firmware updates,
- * which can be used on any g chip.
- *
- * The firmware update protocol consists of two phases: connection
- * establishment and actual image transfer.
- *
- * Image transfer is done in 1K blocks. The host supplying the image
- * encapsulates blocks in frames by prepending a header including the flash
- * offset where the block is destined and its digest.
- *
- * The CR50 device responds to each frame with a confirmation which is 1 byte
- * response. Zero value means success, non zero value is the error code
- * reported by CR50.
- *
- * To establish the connection, the host sends a different frame, which
- * contains no data and is destined to offset 0. Receiving such a frame
- * signals the CR50 that the host intends to transfer a new image.
- *
- * The connection establishment response is described by the
- * first_response_pdu structure below.
- */
-
-#define UPGRADE_PROTOCOL_VERSION 6
-
-/* This is the format of the update frame header. */
-struct upgrade_command {
-	uint32_t  block_digest;  /* first 4 bytes of sha1 of the rest of the
-				  * frame.
-				  */
-	uint32_t  block_base;    /* Offset of this frame into the flash SPI. */
-	/* The actual payload goes here. */
-} __packed;
-
-/*
- * This is the frame format the host uses when sending update PDUs over USB.
- *
- * The PDUs are up to 1K bytes in size, they are fragmented into USB chunks of
- * 64 bytes each and reassembled on the receive side before being passed to
- * the flash update function.
- *
- * The flash update function receives the unframed PDU body (starting at the
- * cmd field below), and puts its reply into the same buffer the PDU was in.
- */
-struct update_frame_header {
-	uint32_t block_size;    /* Total size of the block, including this
-				 * field.
-				 */
-	struct upgrade_command cmd;
-};
-
-/*
- * A convenience structure which allows to group together various revision
- * fields of the header created by the signer.
- *
- * These fields are compared when deciding if versions of two images are the
- * same or when deciding which one of the available images to run.
- */
-struct signed_header_version {
-	uint32_t minor;
-	uint32_t major;
-	uint32_t epoch;
-};
-
-/*
- * Response to the connection establishment request.
- *
- * When responding to the very first packet of the upgrade sequence, the
- * original USB update implementation was responding with a four byte value,
- * just as to any other block of the transfer sequence.
- *
- * It became clear that there is a need to be able to enhance the upgrade
- * protocol, while staying backwards compatible.
- *
- * All newer protocol versions (starting with version 2) respond to the very
- * first packet with an 8 byte or larger response, where the first 4 bytes are
- * a version specific data, and the second 4 bytes - the protocol version
- * number.
- *
- * This way the host receiving of a four byte value in response to the first
- * packet is considered an indication of the target running the 'legacy'
- * protocol, version 1. Receiving of an 8 byte or longer response would
- * communicates the protocol version in the second 4 bytes.
- */
-struct first_response_pdu {
-	uint32_t return_value;
-
-	/* The below fields are present in versions 2 and up. */
-	uint32_t protocol_version;
-
-	/* The below fields are present in versions 3 and up. */
-	uint32_t  backup_ro_offset;
-	uint32_t  backup_rw_offset;
-
-	/* The below fields are present in versions 4 and up. */
-	/* Versions of the currently active RO and RW sections. */
-	struct signed_header_version shv[2];
-
-	/* The below fields are present in versions 5 and up */
-	/* keyids of the currently active RO and RW sections. */
-	uint32_t keyid[2];
-};
-
-#define UPGRADE_DONE          0xB007AB1E
-
-void fw_upgrade_command_handler(void *body,
-				size_t cmd_size,
-				size_t *response_size);
-
-/* Used to tell fw upgrade the update ran successfully and is finished */
-void fw_upgrade_complete(void);
-
-/* Verify integrity of the PDU received over USB. */
-int usb_pdu_valid(struct upgrade_command *cmd_body,
-		  size_t cmd_size);
-
-/* Various upgrade command return values. */
-enum return_value {
-	UPGRADE_SUCCESS = 0,
-	UPGRADE_BAD_ADDR = 1,
-	UPGRADE_ERASE_FAILURE = 2,
-	UPGRADE_DATA_ERROR = 3,
-	UPGRADE_WRITE_FAILURE = 4,
-	UPGRADE_VERIFY_ERROR = 5,
-	UPGRADE_GEN_ERROR = 6,
-	UPGRADE_MALLOC_ERROR = 7,
-	UPGRADE_ROLLBACK_ERROR = 8,
-	UPGRADE_RATE_LIMIT_ERROR = 9,
-	UPGRADE_UNALIGNED_BLOCK_ERROR = 10,
-	UPGRADE_TRUNCATED_HEADER_ERROR = 11,
-	UPGRADE_BOARD_ID_ERROR = 12,
-};
-
-/*
- * This is the size of the update frame payload, unless this is the last chunk
- * of the image.
- */
-#define SIGNED_TRANSFER_SIZE 1024
-
-#endif  /* ! __EC_CHIP_G_UPGRADE_FW_H */
diff --git a/chip/g/usart.c b/chip/g/usart.c
deleted file mode 100644
index 0a08d261b8..0000000000
--- a/chip/g/usart.c
+++ /dev/null
@@ -1,220 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "queue.h"
-#include "queue_policies.h"
-#ifdef CONFIG_STREAM_SIGNATURE
-#include "signing.h"
-#endif
-#ifdef CONFIG_UART_BITBANG
-#include "uart_bitbang.h"
-#endif
-#include "uartn.h"
-#include "usart.h"
-#include "usb-stream.h"
-
-#define USE_UART_INTERRUPTS (!(defined(CONFIG_CUSTOMIZED_RO) && \
-defined(SECTION_IS_RO)))
-#define QUEUE_SIZE 64
-/*
- * Want to be able to accumulate larger amounts of data while USB is
- * momentarily stalled for whatever reason.
- */
-#define QUEUE_SIZE_UART_RX 512
-
-#ifdef CONFIG_STREAM_SIGNATURE
-/*
- * When signing over streaming data, up the relevant queue sizes.
- */
-#define QUEUE_SIZE_SIG_IN  1024
-#define QUEUE_SIZE_USB_IN  8192
-#define QUEUE_SIZE_UART_IN 1024
-#else
-#define QUEUE_SIZE_SIG_IN  QUEUE_SIZE
-#define QUEUE_SIZE_USB_IN  QUEUE_SIZE
-#define QUEUE_SIZE_UART_IN QUEUE_SIZE
-#endif
-
-
-#ifdef CONFIG_STREAM_USART1
-struct usb_stream_config const ap_usb;
-struct usart_config const ap_uart;
-
-#ifdef CONFIG_STREAM_SIGNATURE
-/*
- * This code adds the ability to capture UART data received, and
- * sign it with H1's key. This allows the log output to be verified
- * as actual UART output from this board.
- *
- * This functionality is enabled by redirecting the UART receive queue
- * to feed into the signing module rather than the usb tx. After being
- * added to the running hash, the data is then pushed by the signer
- * into the usb tx queue.
- */
-struct signer_config const sig;
-static struct queue const ap_uart_output =
-	QUEUE_DIRECT(QUEUE_SIZE_SIG_IN, uint8_t, ap_uart.producer,
-		     sig.consumer);
-static struct queue const sig_to_usb =
-	QUEUE_DIRECT(QUEUE_SIZE_USB_IN, uint8_t, sig.producer,
-		     ap_usb.consumer);
-
-SIGNER_CONFIG(sig, stream_uart, sig_to_usb, ap_uart_output);
-
-#else  /* Not CONFIG_STREAM_SIGNATURE */
-static struct queue const ap_uart_output =
-	QUEUE_DIRECT(QUEUE_SIZE_UART_RX, uint8_t,
-		     ap_uart.producer, ap_usb.consumer);
-#endif
-
-static struct queue const ap_usb_to_uart =
-	QUEUE_DIRECT(QUEUE_SIZE_UART_IN, uint8_t, ap_usb.producer,
-		     ap_uart.consumer);
-
-/*
- * AP UART data is sent to the ap_uart_output queue, and received from
- * the ap_usb_to_uart queue. The ap_uart_output queue is received by the
- * USB bridge, or if a signer is enabled, received by the signer, which then
- * passes the data to the USB bridge after processing it.
- */
-USART_CONFIG(ap_uart,
-	     UART_AP,
-	     ap_uart_output,
-	     ap_usb_to_uart);
-
-/*
- * The UART USB bridge receives character data from the UART's queue,
- * unless signing is enabled, in which case it receives data from the
- * signer's queue, after the signer has received it from the UART and
- * processed it.
- */
-USB_STREAM_CONFIG(ap_usb,
-		  USB_IFACE_AP,
-		  USB_STR_AP_NAME,
-		  USB_EP_AP,
-		  USB_MAX_PACKET_SIZE,
-		  USB_MAX_PACKET_SIZE,
-		  ap_usb_to_uart,
-#ifdef CONFIG_STREAM_SIGNATURE
-		  sig_to_usb)
-#else
-		  ap_uart_output)
-#endif
-#endif  /* CONFIG_STREAM_USART1 */
-
-#ifdef CONFIG_STREAM_USART2
-struct usb_stream_config const ec_usb;
-struct usart_config const ec_uart;
-
-static struct queue const ec_uart_to_usb =
-	QUEUE_DIRECT(QUEUE_SIZE_UART_RX, uint8_t,
-		     ec_uart.producer, ec_usb.consumer);
-static struct queue const ec_usb_to_uart =
-	QUEUE_DIRECT(QUEUE_SIZE, uint8_t, ec_usb.producer, ec_uart.consumer);
-
-USART_CONFIG(ec_uart,
-	     UART_EC,
-	     ec_uart_to_usb,
-	     ec_usb_to_uart);
-
-USB_STREAM_CONFIG(ec_usb,
-		  USB_IFACE_EC,
-		  USB_STR_EC_NAME,
-		  USB_EP_EC,
-		  USB_MAX_PACKET_SIZE,
-		  USB_MAX_PACKET_SIZE,
-		  ec_usb_to_uart,
-		  ec_uart_to_usb)
-#endif
-
-void get_data_from_usb(struct usart_config const *config)
-{
-	struct queue const *uart_out = config->consumer.queue;
-	int c;
-
-	/* Copy output from buffer until TX fifo full or output buffer empty */
-	while (queue_count(uart_out) && QUEUE_REMOVE_UNITS(uart_out, &c, 1))
-		uartn_write_char(config->uart, c);
-
-	/* If output buffer is empty, disable transmit interrupt */
-	if (!queue_count(uart_out))
-		uartn_tx_stop(config->uart);
-}
-
-void send_data_to_usb(struct usart_config const *config)
-{
-	struct queue const *uart_in = config->producer.queue;
-	int uart = config->uart;
-	size_t count;
-	size_t q_room;
-	size_t tail;
-	size_t mask;
-
-	q_room = queue_space(uart_in);
-
-	if (!q_room)
-		return;
-
-	mask = uart_in->buffer_units_mask;
-	tail = uart_in->state->tail & mask;
-	count = 0;
-
-	while ((count != q_room) && uartn_rx_available(uart)) {
-		uart_in->buffer[tail] = uartn_read_char(uart);
-		tail = (tail + 1) & mask;
-		count++;
-	}
-	if (count)
-		queue_advance_tail(uart_in, count);
-}
-
-static void uart_read(struct producer const *producer, size_t count)
-{
-}
-
-static void uart_written(struct consumer const *consumer, size_t count)
-{
-	struct usart_config const *config =
-		DOWNCAST(consumer, struct usart_config, consumer);
-
-#ifdef CONFIG_UART_BITBANG
-	if (uart_bitbang_is_enabled() &&
-	    (config->uart == bitbang_config.uart)) {
-		uart_bitbang_drain_tx_queue(consumer->queue);
-		return;
-	}
-#endif
-
-	if (uartn_tx_ready(config->uart) && queue_count(consumer->queue))
-		uartn_tx_start(config->uart);
-}
-
-struct producer_ops const uart_producer_ops = {
-	.read = uart_read,
-};
-
-struct consumer_ops const uart_consumer_ops = {
-	.written = uart_written,
-};
-
-#if USE_UART_INTERRUPTS
-#ifdef CONFIG_STREAM_USART1
-/*
- * Interrupt handlers for UART1
- */
-CONFIGURE_INTERRUPTS(ap_uart,
-		     GC_IRQNUM_UART1_RXINT,
-		     GC_IRQNUM_UART1_TXINT)
-#endif
-
-#ifdef CONFIG_STREAM_USART2
-/*
- * Interrupt handlers for UART2
- */
-CONFIGURE_INTERRUPTS(ec_uart,
-		     GC_IRQNUM_UART2_RXINT,
-		     GC_IRQNUM_UART2_TXINT)
-#endif
-#endif
diff --git a/chip/g/usart.h b/chip/g/usart.h
deleted file mode 100644
index cd3a9cfe40..0000000000
--- a/chip/g/usart.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "consumer.h"
-#include "producer.h"
-#include "registers.h"
-#include "task.h"
-#include "board.h"
-
-#ifndef __CROS_FORWARD_UART_H
-#define __CROS_FORWARD_UART_H
-
-#define CONFIGURE_INTERRUPTS__rx_int(NAME) send_data_to_usb(&NAME)
-
-struct usart_config {
-	int uart;
-
-	struct producer const producer;
-	struct consumer const consumer;
-};
-
-extern struct consumer_ops const uart_consumer_ops;
-extern struct producer_ops const uart_producer_ops;
-#define CONFIGURE_INTERRUPTS(NAME,					\
-			     RXINT,					\
-			     TXINT)					\
-	void CONCAT2(NAME, _rx_int_)(void);				\
-	void CONCAT2(NAME, _tx_int_)(void);				\
-	DECLARE_IRQ(RXINT, CONCAT2(NAME, _rx_int_), 1);			\
-	DECLARE_IRQ(TXINT, CONCAT2(NAME, _tx_int_), 1);			\
-	void CONCAT2(NAME, _tx_int_)(void)				\
-	{								\
-		/* Clear transmit interrupt status */			\
-		GR_UART_ISTATECLR(NAME.uart) =				\
-			GC_UART_ISTATECLR_TX_MASK;			\
-		/* Fill output FIFO */					\
-		get_data_from_usb(&NAME);				\
-	}								\
-	void CONCAT2(NAME, _rx_int_)(void)				\
-	{								\
-		/* Clear receive interrupt status */			\
-		GR_UART_ISTATECLR(NAME.uart) =				\
-			GC_UART_ISTATECLR_RX_MASK;			\
-		/* Read input FIFO until empty */			\
-		CONFIGURE_INTERRUPTS__rx_int(NAME);			\
-	}
-
-
-#define USART_CONFIG(NAME,						\
-		     UART,						\
-		     RX_QUEUE,						\
-		     TX_QUEUE)						\
-	struct usart_config const NAME = {				\
-		.uart      = UART,					\
-		.consumer  = {						\
-			.queue = &TX_QUEUE,				\
-			.ops   = &uart_consumer_ops,			\
-		},							\
-		.producer  = {						\
-			.queue = &RX_QUEUE,				\
-			.ops   = &uart_producer_ops,			\
-		},							\
-	}
-
-
-/* Read data from UART and add it to the producer queue */
-void send_data_to_usb(struct usart_config const *config);
-
-/* Read data from the consumer queue and send it to the UART */
-void get_data_from_usb(struct usart_config const *config);
-
-/* Helper for UART bitbang mode. */
-extern struct usart_config const ec_uart;
-
-#endif  /* __CROS_FORWARD_UART_H */
diff --git a/chip/g/usb-stream.c b/chip/g/usb-stream.c
deleted file mode 100644
index ae3b42e5c2..0000000000
--- a/chip/g/usb-stream.c
+++ /dev/null
@@ -1,354 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "usb-stream.h"
-
-/* Let the USB HW IN-to-host FIFO transmit some bytes */
-static void usb_enable_tx(struct usb_stream_config const *config,
-			  const int len[])
-{
-	const uint32_t flags = DIEPDMA_BS_HOST_RDY | DIEPDMA_IOC | DIEPDMA_LAST;
-	int idx = 0;
-
-	if (len[1]) {
-		config->in_desc[idx].flags = DIEPDMA_TXBYTES(len[idx]) |
-					     DIEPDMA_BS_HOST_RDY;
-		idx++;
-	}
-	config->in_desc[idx].flags = DIEPDMA_TXBYTES(len[idx]) | flags;
-
-	GR_USB_DIEPCTL(config->endpoint) |= DXEPCTL_CNAK | DXEPCTL_EPENA;
-}
-
-/* Let the USB HW OUT-from-host FIFO receive some bytes */
-static void usb_enable_rx(struct usb_stream_config const *config, int len)
-{
-	config->out_desc->flags = DOEPDMA_RXBYTES(len) | DOEPDMA_LAST |
-				  DOEPDMA_BS_HOST_RDY | DOEPDMA_IOC;
-	GR_USB_DOEPCTL(config->endpoint) |= DXEPCTL_CNAK | DXEPCTL_EPENA;
-}
-
-/* True if the HW Rx/OUT FIFO has bytes for us. */
-static inline int rx_fifo_is_ready(struct usb_stream_config const *config)
-{
-	return (config->out_desc->flags & DOEPDMA_BS_MASK) ==
-	       DOEPDMA_BS_DMA_DONE;
-}
-
-/*
- * This function tries to shove new bytes from the USB host into the queue for
- * consumption elsewhere. It is invoked either by a HW interrupt (telling us we
- * have new bytes from the USB host), or by whoever is reading bytes out of the
- * other end of the queue (telling us that there's now more room in the queue
- * if we still have bytes to shove in there).
- */
-void rx_stream_handler(struct usb_stream_config const *config)
-{
-	/*
-	 * The HW FIFO buffer (rx_ram) is always filled from [0] by the
-	 * hardware. The rx_in_fifo variable counts how many bytes of that
-	 * buffer are actually valid, and is calculated from the HW DMA
-	 * descriptor table. The descriptor is updated by the hardware, and it
-	 * and rx_ram remains valid and unchanged until software tells the
-	 * the hardware engine to accept more input.
-	 */
-	int rx_in_fifo, rx_left;
-
-	/*
-	 * The rx_handled variable tracks how many of the bytes in the HW FIFO
-	 * we've copied into the incoming queue. The queue may not accept all
-	 * of them at once, so we have to keep track of where we are so that
-	 * the next time this function is called we can try to shove the rest
-	 * of the HW FIFO bytes into the queue.
-	 */
-	int rx_handled;
-
-	/* If the HW FIFO isn't ready, then we're waiting for more bytes */
-	if (!rx_fifo_is_ready(config))
-		return;
-
-	rx_handled = *(config->rx_handled);
-	/*
-	 * How many of the HW FIFO bytes have we not yet handled? We need to
-	 * know both where we are in the buffer and how many bytes we haven't
-	 * yet enqueued. One can be calculated from the other as long as we
-	 * know rx_in_fifo, but we need at least one static variable.
-	 */
-	rx_in_fifo = config->rx_size
-		- (config->out_desc->flags & DOEPDMA_RXBYTES_MASK);
-	rx_left = rx_in_fifo - rx_handled;
-
-	/* If we have some, try to shove them into the queue */
-	if (rx_left) {
-		size_t added = QUEUE_ADD_UNITS(
-			config->producer.queue, config->rx_ram + rx_handled,
-			rx_left);
-		rx_handled += added;
-		rx_left -= added;
-	}
-
-	/*
-	 * When we've handled all the bytes in the queue ("rx_in_fifo ==
-	 * rx_handled" and "rx_left == 0" indicate the same thing), we can
-	 * reenable the USB HW to go fetch more.
-	 */
-	if (!rx_left) {
-		rx_handled = 0;
-		usb_enable_rx(config, config->rx_size);
-	} else {
-		hook_call_deferred(config->deferred_rx, 0);
-	}
-
-	*(config->rx_handled) = rx_handled;
-}
-
-/* Rx/OUT interrupt handler */
-void usb_stream_rx(struct usb_stream_config const *config)
-{
-	/* Wake up the Rx FIFO handler */
-	hook_call_deferred(config->deferred_rx, 0);
-
-	GR_USB_DOEPINT(config->endpoint) = 0xffffffff;
-}
-
-/* True if the Tx/IN FIFO can take some bytes from us. */
-int tx_fifo_is_ready(struct usb_stream_config const *config)
-{
-	uint32_t status;
-	struct g_usb_desc *in_desc = config->in_desc;
-
-	if (!(in_desc->flags & DIEPDMA_LAST))
-		++in_desc;
-
-	status = in_desc->flags & DIEPDMA_BS_MASK;
-	return status == DIEPDMA_BS_DMA_DONE || status == DIEPDMA_BS_HOST_BSY;
-}
-
-/* Try to send some bytes to the host */
-static void tx_stream_handler(struct usb_stream_config const *config)
-{
-	int len[MAX_IN_DESC];
-	size_t count;
-	size_t head;
-	struct queue const *tx_q = config->consumer.queue;
-
-	/* setup to send bytes to the host */
-	count = MIN(queue_count(tx_q), config->tx_size);
-	if (!count) {
-		/* Report USB TX transfer is not active any more. */
-		*config->tx_in_progress = 0;
-		return;
-	}
-
-	head = tx_q->state->head & tx_q->buffer_units_mask;
-
-	if (config->is_uart_console) {
-		if (!*config->kicker_running &&
-		    (count < config->tx_size)) {
-		/*
-		 * Shipping less than full chunk (64 bytes) over usb is
-		 * wasteful in case there is a lot of data coming from the
-		 * stream source. Let's try collecting more bytes in case more
-		 * is coming.
-		 *
-		 * It takes 5.6 ms to transfer 64 bytes over UART at 115200
-		 * bps with one start and one stop bit. Let's set the deferred
-		 * function delay to 3 ms, it will take longer in reality as
-		 * background tasks will get a chance to run.
-		 */
-			hook_call_deferred(config->tx_kicker, 3 * MSEC);
-			*config->kicker_running = 1;
-			return;
-		}
-
-		if (*config->kicker_running) {
-			*config->kicker_running = 0;
-			hook_call_deferred(config->tx_kicker, -1);
-		}
-	}
-
-	/*
-	 * If queue units are not physically continuous, then setup transfer
-	 * in two USB endpoint descriptors.
-	 *
-	 *      buffer                         buffer + buffer_units
-	 *      |     tail                head |
-	 *      |     |                   |    |
-	 *      V     V                   V    V
-	 * tx_q |xxxxxx___________________xxxxx|
-	 *       <---->                   <--->
-	 *      len[1]                    len[0]
-	 */
-	len[0] = MIN(count, tx_q->buffer_units - head);
-	len[1] = count - len[0];
-
-	/*
-	 * Store the amount to advance head when the transfer is done.
-	 * Note: 'tx byte' field in the endpoint descriptor decreases to zero
-	 *       as data get transferred. Need to store the transfer size,
-	 *       which is 'count', aside into *config-> tx_handlered.
-	 */
-	*(config->tx_handled) = count;
-
-	/*
-	 * Setup the first endpoint descriptor with start memory address No
-	 * need to setup for the second endpoint, because it is always the
-	 * start address of the queue, and already setup in
-	 * usb_stream_reset().
-	 */
-	config->in_desc[0].addr = (void *)tx_q->buffer + head;
-
-	/*
-	 * Enable USB transfer. usb_enable_tx() will setup the transfer size
-	 * in the first endpoint descriptor, and the second descriptor as well
-	 * if it is needed.
-	 */
-	usb_enable_tx(config, len);
-}
-
-/*
- * Deferred function which gets to run if a UART console does not supply
- * enough data to fill a USB chunk (64 bytes).
- */
-void tx_stream_kicker(struct usb_stream_config const *config)
-{
-	/*
-	 * By design this function must run on a task context, i.e. interrupts
-	 * are enabled.
-	 *
-	 * The not so elegant but simplest way to avoid concurrency issues
-	 * with the kicker function execution interrupted by a USB or UART
-	 * event is to invoke tx_stream_handler() with disabled interrupts.
-	 */
-	interrupt_disable();
-
-	if (*config->kicker_running)
-		tx_stream_handler(config);
-
-	interrupt_enable();
-}
-
-/* Tx/IN interrupt handler */
-void usb_stream_tx(struct usb_stream_config const *config)
-{
-	size_t *tx_handled;
-
-	/* Clear the Tx/IN interrupts */
-	GR_USB_DIEPINT(config->endpoint) = 0xffffffff;
-
-	/* Address of the size of the most recent chunk. */
-	tx_handled = config->tx_handled;
-
-	/*
-	 * Transfer completed, advance queue head by the number of bytes
-	 * transmitted in the most recent chunk.
-	 */
-	queue_advance_head(config->consumer.queue, *tx_handled);
-
-	*tx_handled = 0;
-
-	/* See if there is more to transmit. */
-	tx_stream_handler(config);
-}
-
-void usb_stream_reset(struct usb_stream_config const *config)
-{
-	/*
-	 * Mark USB TX transfer is in progress, because it shall be so at
-	 * the end of this function to flush any queued data.
-	 */
-	*config->tx_in_progress = 1;
-
-	config->out_desc->flags = DOEPDMA_RXBYTES(config->rx_size) |
-				  DOEPDMA_LAST | DOEPDMA_BS_HOST_RDY |
-				  DOEPDMA_IOC;
-	config->out_desc->addr = config->rx_ram;
-	GR_USB_DOEPDMA(config->endpoint) = (uint32_t)config->out_desc;
-	config->in_desc[0].flags = DIEPDMA_LAST | DIEPDMA_BS_HOST_BSY |
-				 DIEPDMA_IOC;
-	config->in_desc[1].flags = DIEPDMA_LAST | DIEPDMA_BS_HOST_BSY |
-				 DIEPDMA_IOC;
-	/*
-	 * No need to set config->in_desc[0].addr here, because it will be set
-	 * in tx_stream_handler() with the queue head pointer at that time.
-	 * Meanwhile, config->in_desc[1].addr is set here once, and it won't be
-	 * changed at all.
-	 */
-	config->in_desc[1].addr = (void *)config->consumer.queue->buffer;
-	GR_USB_DIEPDMA(config->endpoint) = (uint32_t)config->in_desc;
-	GR_USB_DOEPCTL(config->endpoint) = DXEPCTL_MPS(64) | DXEPCTL_USBACTEP |
-					   DXEPCTL_EPTYPE_BULK |
-					   DXEPCTL_CNAK | DXEPCTL_EPENA;
-	GR_USB_DIEPCTL(config->endpoint) = DXEPCTL_MPS(64) | DXEPCTL_USBACTEP |
-					   DXEPCTL_EPTYPE_BULK |
-					   DXEPCTL_TXFNUM(config->endpoint);
-	GR_USB_DAINTMSK |= DAINT_INEP(config->endpoint) |
-			   DAINT_OUTEP(config->endpoint);
-
-	*config->is_reset = 1;
-
-	/* Flush any queued data */
-	tx_stream_handler(config);
-	hook_call_deferred(config->deferred_rx, 0);
-}
-
-static void usb_read(struct producer const *producer, size_t count)
-{
-	struct usb_stream_config const *config =
-		DOWNCAST(producer, struct usb_stream_config, producer);
-
-	hook_call_deferred(config->deferred_rx, 0);
-}
-
-/*
- * NOTE: usb_written() should be called by IRQ handlers, so that
- *       it can be non-preemptive.
- */
-static void usb_written(struct consumer const *consumer, size_t count)
-{
-	struct usb_stream_config const *config =
-		DOWNCAST(consumer, struct usb_stream_config, consumer);
-
-	/* USB TX transfer is active. No need to activate it. */
-	if (*config->tx_in_progress) {
-		struct queue const *tx_q;
-
-		if (!*config->kicker_running)
-			return;
-
-		/*
-		 * If kicker is running for too long and we already have a
-		 * certain amount of data accumulated in the buffer, let's
-		 * proceed even before the kicker had a chance to kick in.
-		 */
-		tx_q = config->consumer.queue;
-		if (queue_count(tx_q) < tx_q->buffer_units_mask)
-			return;
-
-		hook_call_deferred(config->tx_kicker, -1);
-		*config->kicker_running = 0;
-	}
-
-	/*
-	 * if USB Endpoint has not been initialized nor in ready status,
-	 * then return.
-	 */
-	if (!tx_fifo_is_ready(config))
-		return;
-
-	*config->tx_in_progress = 1;
-	tx_stream_handler(config);
-}
-
-struct producer_ops const usb_stream_producer_ops = {
-	.read = usb_read,
-};
-
-struct consumer_ops const usb_stream_consumer_ops = {
-	.written = usb_written,
-};
diff --git a/chip/g/usb-stream.h b/chip/g/usb-stream.h
deleted file mode 100644
index 49048a6d9c..0000000000
--- a/chip/g/usb-stream.h
+++ /dev/null
@@ -1,253 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#ifndef __CROS_EC_USB_STREAM_H
-#define __CROS_EC_USB_STREAM_H
-
-/* USB STREAM driver for Chrome EC */
-
-#include "compile_time_macros.h"
-#include "consumer.h"
-#include "hooks.h"
-#include "registers.h"
-#include "producer.h"
-#include "queue.h"
-#include "usb_descriptor.h"
-#include "usb_hw.h"
-
-#define MAX_IN_DESC	2
-
-/*
- * Compile time Per-USB stream configuration stored in flash.  Instances of this
- * structure are provided by the user of the USB stream.  This structure binds
- * together all information required to operate a USB stream.
- */
-struct usb_stream_config {
-	/*
-	 * Endpoint index, and pointers to the USB packet RAM buffers.
-	 */
-	uint16_t endpoint;
-	uint16_t is_uart_console;
-
-	/* USB TX transfer is in progress */
-	uint8_t *tx_in_progress;
-	uint8_t *kicker_running;
-	uint8_t *is_reset;
-
-	/*
-	 * Deferred function to call to handle USB and Queue request.
-	 */
-	const struct deferred_data *deferred_rx;
-	const struct deferred_data *tx_kicker;
-
-	int tx_size;
-	int rx_size;
-
-	uint8_t *rx_ram;
-
-	struct consumer consumer;
-	struct producer producer;
-
-	struct g_usb_desc *out_desc;
-	struct g_usb_desc *in_desc;
-
-	int *rx_handled;
-	/* Number of buffer units in TX queue in transit.
-	 * This is to advance queue tail pointer when the transfer is done.
-	 */
-	size_t *tx_handled;
-};
-
-/*
- * These function tables are defined by the USB Stream driver and are used to
- * initialize the consumer and producer in the usb_stream_config.
- */
-extern struct consumer_ops const usb_stream_consumer_ops;
-extern struct producer_ops const usb_stream_producer_ops;
-
-/* Need to define these so that other than Cr50 boards compile cleanly. */
-#ifndef USB_EP_EC
-#define USB_EP_EC -1
-#endif
-#ifndef USB_EP_AP
-#define USB_EP_AP -1
-#endif
-
-/*
- * Convenience macro for defining USB streams and their associated state and
- * buffers.
- *
- * NAME is used to construct the names of the packet RAM buffers, trampoline
- * functions, usb_stream_state struct, and usb_stream_config struct, the
- * latter is just called NAME.
- *
- * INTERFACE is the index of the USB interface to associate with this
- * stream.
- *
- * INTERFACE_CLASS, INTERFACE_SUBCLASS, INTERFACE_PROTOCOL are the
- * .bInterfaceClass, .bInterfaceSubClass, and .bInterfaceProtocol fields
- * respectively in the USB interface descriptor.
- *
- * INTERFACE_NAME is the index of the USB string descriptor (iInterface).
- *
- * ENDPOINT is the index of the USB bulk endpoint used for receiving and
- * transmitting bytes.
- *
- * RX_SIZE and TX_SIZE are the number of bytes of USB packet RAM to allocate
- * for the RX and TX packets respectively.  The valid values for these
- * parameters are dictated by the USB peripheral.
- *
- * RX_QUEUE and TX_QUEUE are the names of the RX and TX queues that this driver
- * should write to and read from respectively.
- */
-/*
- * The following assertions can not be made because they require access to
- * non-const fields, but should be kept in mind.
- *
- * BUILD_ASSERT(RX_QUEUE.buffer_units >= RX_SIZE);
- * BUILD_ASSERT(TX_QUEUE.buffer_units >= TX_SIZE);
- * BUILD_ASSERT(RX_QUEUE.unit_bytes == 1);
- * BUILD_ASSERT(TX_QUEUE.unit_bytes == 1);
- */
-#define USB_STREAM_CONFIG_FULL(NAME,					\
-			       INTERFACE,				\
-			       INTERFACE_CLASS,				\
-			       INTERFACE_SUBCLASS,			\
-			       INTERFACE_PROTOCOL,			\
-			       INTERFACE_NAME,				\
-			       ENDPOINT,				\
-			       RX_SIZE,					\
-			       TX_SIZE,					\
-			       RX_QUEUE,				\
-			       TX_QUEUE)				\
-									\
-	static struct g_usb_desc CONCAT2(NAME, _out_desc_);		\
-	static struct g_usb_desc CONCAT2(NAME, _in_desc_)[MAX_IN_DESC];	\
-	static uint8_t CONCAT2(NAME, _buf_rx_)[RX_SIZE];		\
-	static uint8_t CONCAT2(NAME, _tx_in_progress_);			\
-	static uint8_t CONCAT2(NAME, _kicker_running_);			\
-	static uint8_t CONCAT2(NAME, _is_reset_);			\
-	static void CONCAT2(NAME, _deferred_rx_)(void);			\
-	static void CONCAT2(NAME, _tx_kicker_)(void);			\
-	DECLARE_DEFERRED(CONCAT2(NAME, _deferred_rx_));			\
-	DECLARE_DEFERRED(CONCAT2(NAME, _tx_kicker_));			\
-	static int CONCAT2(NAME, _rx_handled);				\
-	static size_t CONCAT2(NAME, _tx_handled);			\
-	struct usb_stream_config const NAME = {				\
-		.endpoint     = ENDPOINT,				\
-		.is_uart_console = ((ENDPOINT == USB_EP_EC) ||		\
-				    (ENDPOINT == USB_EP_CONSOLE) ||	\
-				    (ENDPOINT == USB_EP_AP)),		\
-		.tx_in_progress = &CONCAT2(NAME, _tx_in_progress_),	\
-		.kicker_running = &CONCAT2(NAME, _kicker_running_),	\
-		.is_reset     = &CONCAT2(NAME, _is_reset_),		\
-		.in_desc      = &CONCAT2(NAME, _in_desc_)[0],		\
-		.out_desc     = &CONCAT2(NAME, _out_desc_),		\
-		.deferred_rx  = &CONCAT2(NAME, _deferred_rx__data),	\
-		.tx_kicker    = &CONCAT2(NAME, _tx_kicker__data),	\
-		.tx_size      = TX_SIZE,				\
-		.rx_size      = RX_SIZE,				\
-		.rx_ram       = CONCAT2(NAME, _buf_rx_),		\
-		.consumer  = {						\
-			.queue = &TX_QUEUE,				\
-			.ops   = &usb_stream_consumer_ops,		\
-		},							\
-		.producer  = {						\
-			.queue = &RX_QUEUE,				\
-			.ops   = &usb_stream_producer_ops,		\
-		},							\
-		.rx_handled   = &CONCAT2(NAME, _rx_handled),		\
-		.tx_handled   = &CONCAT2(NAME, _tx_handled),		\
-	};								\
-	const struct usb_interface_descriptor				\
-	USB_IFACE_DESC(INTERFACE) = {					\
-		.bLength            = USB_DT_INTERFACE_SIZE,		\
-		.bDescriptorType    = USB_DT_INTERFACE,			\
-		.bInterfaceNumber   = INTERFACE,			\
-		.bAlternateSetting  = 0,				\
-		.bNumEndpoints      = 2,				\
-		.bInterfaceClass    = INTERFACE_CLASS,			\
-		.bInterfaceSubClass = INTERFACE_SUBCLASS,		\
-		.bInterfaceProtocol = INTERFACE_PROTOCOL,		\
-		.iInterface         = INTERFACE_NAME,			\
-	};								\
-	const struct usb_endpoint_descriptor				\
-	USB_EP_DESC(INTERFACE, 0) = {					\
-		.bLength          = USB_DT_ENDPOINT_SIZE,		\
-		.bDescriptorType  = USB_DT_ENDPOINT,			\
-		.bEndpointAddress = 0x80 | ENDPOINT,			\
-		.bmAttributes     = 0x02 /* Bulk IN */,			\
-		.wMaxPacketSize   = TX_SIZE,				\
-		.bInterval        = 10,					\
-	};								\
-	const struct usb_endpoint_descriptor				\
-	USB_EP_DESC(INTERFACE, 1) = {					\
-		.bLength          = USB_DT_ENDPOINT_SIZE,		\
-		.bDescriptorType  = USB_DT_ENDPOINT,			\
-		.bEndpointAddress = ENDPOINT,				\
-		.bmAttributes     = 0x02 /* Bulk OUT */,		\
-		.wMaxPacketSize   = RX_SIZE,				\
-		.bInterval        = 0,					\
-	};								\
-	static void CONCAT2(NAME, _deferred_rx_)(void)			\
-	{ rx_stream_handler(&NAME); }					\
-	static void CONCAT2(NAME, _tx_kicker_)(void)			\
-	{ tx_stream_kicker(&NAME); }					\
-	static void CONCAT2(NAME, _ep_tx)(void)				\
-	{								\
-		usb_stream_tx(&NAME);					\
-	}								\
-	static void CONCAT2(NAME, _ep_rx)(void)				\
-	{								\
-		usb_stream_rx(&NAME);					\
-	}								\
-	static void CONCAT2(NAME, _ep_reset)(void)			\
-	{								\
-		usb_stream_reset(&NAME);				\
-	}								\
-	USB_DECLARE_EP(ENDPOINT,					\
-		       CONCAT2(NAME, _ep_tx),				\
-		       CONCAT2(NAME, _ep_rx),				\
-		       CONCAT2(NAME, _ep_reset));
-
-/* This is a short version for declaring Google serial endpoints */
-#define USB_STREAM_CONFIG(NAME,						\
-			  INTERFACE,					\
-			  INTERFACE_NAME,				\
-			  ENDPOINT,					\
-			  RX_SIZE,					\
-			  TX_SIZE,					\
-			  RX_QUEUE,					\
-			  TX_QUEUE)					\
-	USB_STREAM_CONFIG_FULL(NAME,					\
-			       INTERFACE,				\
-			       USB_CLASS_VENDOR_SPEC,			\
-			       USB_SUBCLASS_GOOGLE_SERIAL,		\
-			       USB_PROTOCOL_GOOGLE_SERIAL,		\
-			       INTERFACE_NAME,				\
-			       ENDPOINT,				\
-			       RX_SIZE,					\
-			       TX_SIZE,					\
-			       RX_QUEUE,				\
-			       TX_QUEUE)
-
-/*
- * Handle USB and Queue request in a deferred callback.
- */
-void rx_stream_handler(struct usb_stream_config const *config);
-void tx_stream_kicker(struct usb_stream_config const *config);
-
-/*
- * These functions are used by the trampoline functions defined above to
- * connect USB endpoint events with the generic USB stream driver.
- */
-void usb_stream_tx(struct usb_stream_config const *config);
-void usb_stream_rx(struct usb_stream_config const *config);
-void usb_stream_reset(struct usb_stream_config const *config);
-
-/*
- * Return non-zero if the USB stream is reset, or 0 otherwise
- */
-int tx_fifo_is_ready(struct usb_stream_config const *config);
-#endif /* __CROS_EC_USB_STREAM_H */
diff --git a/chip/g/usb.c b/chip/g/usb.c
deleted file mode 100644
index cf2e0245da..0000000000
--- a/chip/g/usb.c
+++ /dev/null
@@ -1,1578 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "case_closed_debug.h"
-#include "clock.h"
-#include "common.h"
-#include "config.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "init_chip.h"
-#include "link_defs.h"
-#include "printf.h"
-#include "registers.h"
-#include "system.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_descriptor.h"
-#include "usb_hw.h"
-#include "watchdog.h"
-
-/****************************************************************************/
-/* Debug output */
-
-/* Console output macro */
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
-
-#ifndef CONFIG_USB_SERIALNO
-#define USB_STR_SERIALNO 0
-#endif
-
-/* This is not defined anywhere else. Change it here to debug. */
-#undef DEBUG_ME
-#ifdef DEBUG_ME
-/*
- * For debugging we want to print a bunch of things from within the interrupt
- * handlers, but if we try it'll 1) stop working, and 2) mess up the timing
- * that we're trying to measure. Instead we fill a circular buffer with things
- * to print when we get the chance. The number of args is fixed (a format
- * string and five uint32_t args), and will be printed a few at a time in a
- * HOOK_TICK handler.
- *
- */
-#define MAX_ENTRIES 350				/* Chosen arbitrarily */
-static struct {
-	timestamp_t t;
-	const char *fmt;
-	int a0, a1, a2, a3, a4;
-} stuff_to_print[MAX_ENTRIES];
-static int stuff_in, stuff_out, stuff_overflow;
-
-/* Call this only from within interrupt handler! */
-void print_later(const char *fmt, int a0, int a1, int a2, int a3, int a4)
-{
-	int next;
-
-	stuff_to_print[stuff_in].t = get_time();
-	stuff_to_print[stuff_in].fmt = fmt;
-	stuff_to_print[stuff_in].a0 = a0;
-	stuff_to_print[stuff_in].a1 = a1;
-	stuff_to_print[stuff_in].a2 = a2;
-	stuff_to_print[stuff_in].a3 = a3;
-	stuff_to_print[stuff_in].a4 = a4;
-
-	next = (stuff_in + 1) % MAX_ENTRIES;
-	if (next == stuff_out)
-		stuff_overflow++;
-	else
-		stuff_in = next;
-}
-
-static void do_print_later(void)
-{
-	int lines_per_loop = 32;		/* too much at once fails */
-	int copy_of_stuff_in;
-	int copy_of_overflow;
-
-	interrupt_disable();
-	copy_of_stuff_in = stuff_in;
-	copy_of_overflow = stuff_overflow;
-	stuff_overflow = 0;
-	interrupt_enable();
-
-	if (copy_of_overflow)
-		ccprintf("*** WARNING: %d MESSAGES WERE LOST ***\n",
-			 copy_of_overflow);
-
-	while (lines_per_loop && stuff_out != copy_of_stuff_in) {
-		ccprintf("at %.6lld: ", stuff_to_print[stuff_out].t);
-		ccprintf(stuff_to_print[stuff_out].fmt,
-			 stuff_to_print[stuff_out].a0,
-			 stuff_to_print[stuff_out].a1,
-			 stuff_to_print[stuff_out].a2,
-			 stuff_to_print[stuff_out].a3,
-			 stuff_to_print[stuff_out].a4);
-		ccprintf("\n");
-		stuff_out = (stuff_out + 1) % MAX_ENTRIES;
-		lines_per_loop--;
-	}
-}
-DECLARE_HOOK(HOOK_TICK, do_print_later, HOOK_PRIO_DEFAULT);
-
-/* Debugging stuff to display some registers and bits */
-static const char const *deezbits[32] = {
-	[0]     = "CURMOD",
-	[1]     = "MODEMIS",
-	[2]     = "OTGINT",
-	[3]     = "SOF",
-	[4]     = "RXFLVL",
-	[6]     = "GINNAKEFF",
-	[7]     = "GOUTNAKEFF",
-	[10]    = "ERLYSUSP",
-	[11]    = "USBSUSP",
-	[12]    = "USBRST",
-	[13]    = "ENUMDONE",
-	[14]    = "ISOOUTDROP",
-	[15]    = "EOPF",
-	[17]    = "EPMIS",
-	[18]    = "IEPINT",
-	[19]    = "OEPINT",
-	[20]    = "INCOMPISOIN",
-	[21]    = "INCOMPLP",
-	[22]    = "FETSUSP",
-	[23]    = "RESETDET",
-	[28]    = "CONIDSTSCHNG",
-	[30]    = "SESSREQINT",
-	[31]    = "WKUPINT",
-};
-
-static void showbits(uint32_t b)
-{
-	int i;
-
-	for (i = 0; i < 32; i++)
-		if (b & BIT(i)) {
-			if (deezbits[i])
-				ccprintf(" %s", deezbits[i]);
-			else
-				ccprintf(" %d", i);
-		}
-	ccprintf("\n");
-}
-
-static void showregs(void)
-{
-	ccprintf("GINTSTS:   0x%08x\n", GR_USB_GINTSTS);
-	showbits(GR_USB_GINTSTS);
-	ccprintf("GINTMSK:   0x%08x\n", GR_USB_GINTMSK);
-	showbits(GR_USB_GINTMSK);
-	ccprintf("DAINT:     0x%08x\n", GR_USB_DAINT);
-	ccprintf("DAINTMSK:  0x%08x\n", GR_USB_DAINTMSK);
-	ccprintf("DOEPMSK:   0x%08x\n", GR_USB_DOEPMSK);
-	ccprintf("DIEPMSK:   0x%08x\n", GR_USB_DIEPMSK);
-	ccprintf("DCFG:      0x%08x\n", GR_USB_DCFG);
-	ccprintf("DOEPCTL0:  0x%08x\n", GR_USB_DOEPCTL(0));
-	ccprintf("DIEPCTL0:  0x%08x\n", GR_USB_DIEPCTL(0));
-	ccprintf("DOEPCTL1:  0x%08x\n", GR_USB_DOEPCTL(1));
-	ccprintf("DIEPCTL1:  0x%08x\n", GR_USB_DIEPCTL(1));
-	ccprintf("DOEPCTL2:  0x%08x\n", GR_USB_DOEPCTL(2));
-	ccprintf("DIEPCTL2:  0x%08x\n", GR_USB_DIEPCTL(2));
-}
-
-/* When debugging, print errors as they occur */
-#define report_error(val)						\
-	print_later("Unhandled USB event at usb.c line %d: 0x%x",	\
-		    __LINE__, val, 0, 0, 0)
-
-#else  /* Not debugging */
-#define print_later(...)
-#define showregs(...)
-
-/* TODO: Something unexpected happened. Figure out how to report & fix it. */
-#define report_error(val)						\
-	CPRINTS("Unhandled USB event at %s line %d: 0x%x",		\
-		__FILE__, __LINE__, val)
-
-#endif	/* DEBUG_ME */
-
-/****************************************************************************/
-/* Standard USB stuff */
-
-#ifdef CONFIG_USB_BOS
-/* v2.10 (vs 2.00) BOS Descriptor provided */
-#define USB_DEV_BCDUSB 0x0210
-#else
-#define USB_DEV_BCDUSB 0x0200
-#endif
-
-#ifndef USB_DEV_CLASS
-#define USB_DEV_CLASS USB_CLASS_PER_INTERFACE
-#endif
-
-#ifndef CONFIG_USB_BCD_DEV
-#define CONFIG_USB_BCD_DEV 0x0100		/* 1.00 */
-#endif
-
-/* USB Standard Device Descriptor */
-static const struct usb_device_descriptor dev_desc = {
-	.bLength = USB_DT_DEVICE_SIZE,
-	.bDescriptorType = USB_DT_DEVICE,
-	.bcdUSB = USB_DEV_BCDUSB,
-	.bDeviceClass = USB_DEV_CLASS,
-	.bDeviceSubClass = 0x00,
-	.bDeviceProtocol = 0x00,
-	.bMaxPacketSize0 = USB_MAX_PACKET_SIZE,
-	.idVendor = USB_VID_GOOGLE,
-	.idProduct = CONFIG_USB_PID,
-	.bcdDevice = CONFIG_USB_BCD_DEV,
-	.iManufacturer = USB_STR_VENDOR,
-	.iProduct = USB_STR_PRODUCT,
-	.iSerialNumber = USB_STR_SERIALNO,
-	.bNumConfigurations = 1
-};
-
-/* USB Configuration Descriptor */
-const struct usb_config_descriptor USB_CONF_DESC(conf) = {
-	.bLength = USB_DT_CONFIG_SIZE,
-	.bDescriptorType = USB_DT_CONFIGURATION,
-	.wTotalLength = 0x0BAD,	 /* number of returned bytes, set at runtime */
-	.bNumInterfaces = USB_IFACE_COUNT,
-	.bConfigurationValue = 1,		/* Caution: hard-coded value */
-	.iConfiguration = USB_STR_VERSION,
-	.bmAttributes = 0x80 /* Reserved bit */
-#ifdef CONFIG_USB_SELF_POWERED  /* bus or self powered */
-		      | 0x40
-#endif
-#ifdef CONFIG_USB_REMOTE_WAKEUP
-		      | 0x20
-#endif
-	,
-	.bMaxPower = (CONFIG_USB_MAXPOWER_MA / 2),
-};
-
-const uint8_t usb_string_desc[] = {
-	4,					/* Descriptor size */
-	USB_DT_STRING,
-	0x09, 0x04			    /* LangID = 0x0409: U.S. English */
-};
-
-/****************************************************************************/
-/* Packet-handling stuff, specific to this SoC */
-
-/* Some internal state to keep track of what's going on */
-static enum {
-	WAITING_FOR_SETUP_PACKET,
-	DATA_STAGE_IN,
-	NO_DATA_STAGE,
-} what_am_i_doing;
-
-/* Programmer's Guide, Table 10-7 */
-enum table_case {
-	BAD_0,
-	TABLE_CASE_A,
-	TABLE_CASE_B,
-	TABLE_CASE_C,
-	TABLE_CASE_D,
-	TABLE_CASE_E,
-	BAD_6,
-	BAD_7,
-};
-
-/*
- * Table 10-7 in the Programmer's Guide decodes OUT endpoint interrupts:
- *
- *  Case  StatusPhseRecvd  SetUp  XferCompl   Description
- *
- *   A          0            0       1        Out descriptor is updated. Check
- *                                            its SR bit to see if we got
- *                                            a SETUP packet or an OUT packet.
- *   B          0            1       0        SIE has seen an IN or OUT packet
- *                                            following the SETUP packet.
- *   C          0            1       1        Both A & B at once, I think.
- *                                            Check the SR bit.
- *   D          1            0       0        SIE has seen the host change
- *                                            direction, implying Status phase.
- *   E          1            0       1        Out descriptor is updated, and
- *                                            SIE has seen an IN following it.
- *                                            This is probably the Status phase
- *                                            for a Control Write, but could be
- *                                            an early SETUP for a Control Read
- *                                            instead. Maybe. The documentation
- *                                            is unclear. Check the SR bit
- *                                            anyway.
- */
-static enum table_case decode_table_10_7(uint32_t doepint)
-{
-	enum table_case val = BAD_0;
-
-	/* Bits: SI, SPD, IOC */
-	if (doepint & DOEPINT_XFERCOMPL)
-		val += 1;
-	if (doepint & DOEPINT_SETUP)
-		val += 2;
-	if (doepint & DOEPINT_STSPHSERCVD)
-		val += 4;
-
-	return val;
-}
-
-/* For STATUS/OUT: Use two DMA descriptors, each with one-packet buffers */
-#define NUM_OUT_BUFFERS 2
-static uint8_t ep0_out_buf[NUM_OUT_BUFFERS][USB_MAX_PACKET_SIZE];
-static struct g_usb_desc ep0_out_desc[NUM_OUT_BUFFERS];
-static int cur_out_idx;				/* latest with xfercompl=1 */
-static const struct g_usb_desc *cur_out_desc;
-static int next_out_idx;			/* next packet will go here */
-static struct g_usb_desc *next_out_desc;
-static int processed_update_counter;
-
-/* For IN: Several DMA descriptors, all pointing into one large buffer, so that
- * we can return the configuration descriptor as one big blob. */
-#define NUM_IN_PACKETS_AT_ONCE 4
-#define IN_BUF_SIZE (NUM_IN_PACKETS_AT_ONCE * USB_MAX_PACKET_SIZE)
-static uint8_t ep0_in_buf[IN_BUF_SIZE];
-static struct g_usb_desc ep0_in_desc[NUM_IN_PACKETS_AT_ONCE];
-static struct g_usb_desc *cur_in_desc;
-
-/* Overall device state (USB 2.0 spec, section 9.1.1).
- * We only need a few, though. */
-static enum {
-	DS_DEFAULT,
-	DS_ADDRESS,
-	DS_CONFIGURED,
-} device_state;
-static uint8_t configuration_value;
-
-#ifndef CONFIG_USB_SELECT_PHY_DEFAULT
-#define CONFIG_USB_SELECT_PHY_DEFAULT USB_SEL_PHY1
-#endif
-
-/* Default PHY to use */
-static uint32_t which_phy = CONFIG_USB_SELECT_PHY_DEFAULT;
-
-void usb_select_phy(uint32_t phy)
-{
-	which_phy = phy;
-	GR_USB_GGPIO = GGPIO_WRITE(USB_CUSTOM_CFG_REG,
-				   (USB_PHY_ACTIVE | which_phy));
-	CPRINTS("USB PHY %c", which_phy == USB_SEL_PHY0 ? 'A' : 'B');
-}
-
-uint32_t usb_get_phy(void)
-{
-	return which_phy;
-}
-
-/* Reset all this to a good starting state. */
-static void initialize_dma_buffers(void)
-{
-	int i;
-
-	print_later("initialize_dma_buffers()", 0, 0, 0, 0, 0);
-
-	for (i = 0; i < NUM_OUT_BUFFERS; i++) {
-		ep0_out_desc[i].addr = ep0_out_buf[i];
-		ep0_out_desc[i].flags = DOEPDMA_BS_HOST_BSY;
-	}
-	next_out_idx = 0;
-	next_out_desc = ep0_out_desc + next_out_idx;
-	GR_USB_DOEPDMA(0) = (uint32_t)next_out_desc;
-	/* cur_out_* will be updated when we get the first RX packet */
-
-	for (i = 0; i < NUM_IN_PACKETS_AT_ONCE; i++) {
-		ep0_in_desc[i].addr = ep0_in_buf + i * USB_MAX_PACKET_SIZE;
-		ep0_in_desc[i].flags = DIEPDMA_BS_HOST_BSY;
-	}
-	cur_in_desc = ep0_in_desc;
-	GR_USB_DIEPDMA(0) = (uint32_t)(cur_in_desc);
-};
-
-/* Change the RX descriptors after each SETUP/OUT packet is received so we can
- * prepare to receive another without losing track of this one. */
-static void got_RX_packet(void)
-{
-	cur_out_idx = next_out_idx;
-	cur_out_desc = ep0_out_desc + cur_out_idx;
-	next_out_idx = (next_out_idx + 1) % NUM_OUT_BUFFERS;
-	next_out_desc = ep0_out_desc + next_out_idx;
-	GR_USB_DOEPDMA(0) = (uint32_t)next_out_desc;
-}
-
-/* Load the EP0 IN FIFO buffer with some data (zero-length works too). Returns
- * len, or negative on error. */
-int load_in_fifo(const void *source, uint32_t len)
-{
-	uint8_t *buffer = ep0_in_buf;
-	int zero_packet = (len % USB_MAX_PACKET_SIZE) == 0;
-	int d, l;
-
-	/* Copy the data into our FIFO buffer */
-	if (len >= IN_BUF_SIZE) {
-		report_error(len);
-		return -1;
-	}
-	if (len)
-		memcpy(buffer, source, len);
-
-	/* Set up the descriptors */
-	for (d = l = 0; len >= USB_MAX_PACKET_SIZE; d++) {
-		ep0_in_desc[d].addr = buffer + d * USB_MAX_PACKET_SIZE;
-		ep0_in_desc[d].flags = DIEPDMA_TXBYTES(USB_MAX_PACKET_SIZE);
-		len -= USB_MAX_PACKET_SIZE;
-		l = d;
-	}
-	/* Maybe one short packet left? */
-	if (len || zero_packet) {
-		ep0_in_desc[d].addr = buffer + d * USB_MAX_PACKET_SIZE;
-		ep0_in_desc[d].flags = DIEPDMA_TXBYTES(len) | DIEPDMA_SP;
-		l = d;
-	}
-	/* Mark the last descriptor as last. */
-	ep0_in_desc[l].flags |= (DIEPDMA_LAST | DIEPDMA_IOC);
-
-	/* Point to the first in the chain */
-	cur_in_desc = ep0_in_desc;
-
-	return len;
-}
-
-/* Prepare the EP0 OUT FIFO buffer to accept some data. Returns len, or
- * negative on error. */
-int accept_out_fifo(uint32_t len)
-{
-	/* TODO: This is not yet implemented */
-	report_error(len);
-	return -1;
-}
-
-static void flush_in_fifo(void)
-{
-	/* TODO: Programmer's Guide p167 suggests lots more stuff */
-	GR_USB_GRSTCTL = GRSTCTL_TXFNUM(0) | GRSTCTL_TXFFLSH;
-	while (GR_USB_GRSTCTL & GRSTCTL_TXFFLSH)
-		;				/* timeout? */
-}
-
-/* We're complaining about something by stalling both IN and OUT packets,
- * but a SETUP packet will get through anyway, so prepare for it. */
-static void stall_both_fifos(void)
-{
-	print_later("stall_both_fifos()", 0, 0, 0, 0, 0);
-
-	what_am_i_doing = WAITING_FOR_SETUP_PACKET;
-
-	next_out_desc->flags =
-		DOEPDMA_RXBYTES(USB_MAX_PACKET_SIZE)
-		| DOEPDMA_IOC | DOEPDMA_LAST;
-
-	/* We don't care about IN packets right now, only OUT. */
-	GR_USB_DAINTMSK |= DAINT_OUTEP(0);
-	GR_USB_DAINTMSK &= ~DAINT_INEP(0);
-
-	/* Stall both IN and OUT. The hardware will reset them when the next
-	 * SETUP comes along. */
-	GR_USB_DOEPCTL(0) = DXEPCTL_STALL | DXEPCTL_EPENA;
-	flush_in_fifo();
-	GR_USB_DIEPCTL(0) = DXEPCTL_STALL | DXEPCTL_EPENA;
-}
-
-static void usb_reset_all_ep_pids(void)
-{
-	int i;
-
-	for (i = 1; i < USB_EP_COUNT; i++) {
-		GR_USB_DOEPCTL(i) |= DXEPCTL_SET_D0PID;
-		GR_USB_DIEPCTL(i) |= DXEPCTL_SET_D0PID;
-	}
-}
-
-static void usb_reset_ep_pid(int ep)
-{
-	if (ep & 0x80)	 /* IN enpoint */
-		GR_USB_DIEPCTL(ep & 0x7f) |= DXEPCTL_SET_D0PID;
-	else
-		GR_USB_DOEPCTL(ep) |= DXEPCTL_SET_D0PID;
-}
-
-/* The next packet from the host should be a Setup packet. Get ready for it. */
-static void expect_setup_packet(void)
-{
-	print_later("expect_setup_packet()", 0, 0, 0, 0, 0);
-
-	what_am_i_doing = WAITING_FOR_SETUP_PACKET;
-
-	next_out_desc->flags =
-		DOEPDMA_RXBYTES(USB_MAX_PACKET_SIZE)
-		| DOEPDMA_IOC | DOEPDMA_LAST;
-
-	/* We don't care about IN packets right now, only OUT. */
-	GR_USB_DAINTMSK |= DAINT_OUTEP(0);
-	GR_USB_DAINTMSK &= ~DAINT_INEP(0);
-
-	/* Let it run. We might need CNAK if we just got an OUT for status */
-	GR_USB_DOEPCTL(0) = DXEPCTL_CNAK | DXEPCTL_EPENA;
-}
-
-/* The TX FIFO buffer is loaded. Start the Data phase. */
-static void expect_data_phase_in(enum table_case tc)
-{
-	print_later("expect_data_phase_in(%c)", "0ABCDE67"[tc], 0, 0, 0, 0);
-
-	what_am_i_doing = DATA_STAGE_IN;
-
-	/* We apparently have to do this every time we transmit anything */
-	flush_in_fifo();
-
-	/* I don't think we have to do this every time, but the Programmer's
-	 * Guide says to, so...	*/
-	GR_USB_DIEPDMA(0) = (uint32_t)(cur_in_desc);
-
-	/* Blindly following instructions here, too. */
-	if (tc == TABLE_CASE_C)
-		GR_USB_DIEPCTL(0) = DXEPCTL_CNAK | DXEPCTL_EPENA;
-	else
-		GR_USB_DIEPCTL(0) = DXEPCTL_EPENA;
-
-	/*
-	 * When the IN is done, we expect a zero-length OUT for the status
-	 * phase but it could be an early SETUP instead. We'll have to deal
-	 * with either one when it arrives.
-	 */
-	next_out_desc->flags =
-		DOEPDMA_RXBYTES(USB_MAX_PACKET_SIZE)
-		| DOEPDMA_IOC | DOEPDMA_LAST;
-
-	/* And here's this jimmy rustler again... */
-	if (tc == TABLE_CASE_C)
-		GR_USB_DOEPCTL(0) = DXEPCTL_CNAK | DXEPCTL_EPENA;
-	else
-		GR_USB_DOEPCTL(0) = DXEPCTL_EPENA;
-
-	/* Get an interrupt when either IN or OUT arrives */
-	GR_USB_DAINTMSK |= (DAINT_OUTEP(0) | DAINT_INEP(0));
-
-}
-
-static void expect_data_phase_out(enum table_case tc)
-{
-	print_later("expect_data_phase_out(%c)", "0ABCDE67"[tc], 0, 0, 0, 0);
-	/* TODO: This is not yet supported */
-	report_error(tc);
-	expect_setup_packet();
-}
-
-/* No Data phase, just Status phase (which is IN, since Setup is OUT) */
-static void expect_status_phase_in(enum table_case tc)
-{
-	print_later("expect_status_phase_in(%c)", "0ABCDE67"[tc], 0, 0, 0, 0);
-
-	what_am_i_doing = NO_DATA_STAGE;
-
-	/* Expect a zero-length IN for the Status phase */
-	(void) load_in_fifo(0, 0);
-
-	/* We apparently have to do this every time we transmit anything */
-	flush_in_fifo();
-
-	/* I don't think we have to do this every time, but the Programmer's
-	 * Guide says to, so...	*/
-	GR_USB_DIEPDMA(0) = (uint32_t)(cur_in_desc);
-
-	/* Blindly following instructions here, too. */
-	if (tc == TABLE_CASE_C)
-		GR_USB_DIEPCTL(0) = DXEPCTL_CNAK | DXEPCTL_EPENA;
-	else
-		GR_USB_DIEPCTL(0) = DXEPCTL_EPENA;
-
-	/* The Programmer's Guide instructions for the Normal Two-Stage Control
-	 * Transfer leave this next bit out, so we only need it if we intend to
-	 * process an Exceptional Two-Stage Control Transfer. Because obviously
-	 * we always know in advance what the host is going to do. Idiots. */
-
-	/* Be prepared to get a new Setup packet during the Status phase */
-	next_out_desc->flags =
-		DOEPDMA_RXBYTES(USB_MAX_PACKET_SIZE)
-		| DOEPDMA_IOC | DOEPDMA_LAST;
-
-	/* We've already set GR_USB_DOEPDMA(0), so just enable it. */
-	if (tc == TABLE_CASE_C)
-		GR_USB_DOEPCTL(0) = DXEPCTL_CNAK | DXEPCTL_EPENA;
-	else
-		GR_USB_DOEPCTL(0) = DXEPCTL_EPENA;
-
-	/* Get an interrupt when either IN or OUT arrives */
-	GR_USB_DAINTMSK |= (DAINT_OUTEP(0) | DAINT_INEP(0));
-}
-
-/* Handle a Setup packet that expects us to send back data in reply. Return the
- * length of the data we're returning, or negative to indicate an error. */
-static int handle_setup_with_in_stage(enum table_case tc,
-				      struct usb_setup_packet *req)
-{
-	const void *data = 0;
-	uint32_t len = 0;
-	int ugly_hack = 0;
-	static const uint16_t zero;		/* == 0 */
-
-	print_later("handle_setup_with_in_stage(%c)", "0ABCDE67"[tc],
-		    0, 0, 0, 0);
-
-	switch (req->bRequest) {
-	case USB_REQ_GET_DESCRIPTOR: {
-		uint8_t type = req->wValue >> 8;
-		uint8_t idx = req->wValue & 0xff;
-
-		switch (type) {
-		case USB_DT_DEVICE:
-			data = &dev_desc;
-			len = sizeof(dev_desc);
-			break;
-		case USB_DT_CONFIGURATION:
-			data = __usb_desc;
-			len = USB_DESC_SIZE;
-			ugly_hack = 1;		/* see below */
-			break;
-#ifdef CONFIG_USB_BOS
-		case USB_DT_BOS:
-			data = bos_ctx.descp;
-			len = bos_ctx.size;
-			break;
-#endif
-		case USB_DT_STRING:
-			if (idx >= USB_STR_COUNT)
-				return -1;
-#ifdef CONFIG_USB_SERIALNO
-			if (idx == USB_STR_SERIALNO && ccd_ext_is_enabled())
-				data = usb_serialno_desc;
-			else
-#endif
-				data = usb_strings[idx];
-			len = *(uint8_t *)data;
-			break;
-		case USB_DT_DEVICE_QUALIFIER:
-			/* We're not high speed */
-			return -1;
-		case USB_DT_DEBUG:
-			return -1;
-		default:
-			report_error(type);
-			return -1;
-		}
-		break;
-	}
-	case USB_REQ_GET_STATUS: {
-		/* TODO: Device Status: Remote Wakeup? Self Powered? */
-		data = &zero;
-		len = sizeof(zero);
-		break;
-	}
-	case USB_REQ_GET_CONFIGURATION:
-		data = &configuration_value;
-		len = sizeof(configuration_value);
-		break;
-
-	case USB_REQ_SYNCH_FRAME:
-		/* Unimplemented */
-		return -1;
-
-	default:
-		report_error(req->bRequest);
-		return -1;
-	}
-
-	/* Don't send back more than we were asked for. */
-	len = MIN(req->wLength, len);
-
-	/* Prepare the TX FIFO. If we haven't preallocated enough room in the
-	 * TX FIFO for the largest reply, we'll have to stall. This is a bug in
-	 * our code, but detecting it easily at compile time is related to the
-	 * ugly_hack directly below. */
-	if (load_in_fifo(data, len) < 0)
-		return -1;
-
-	if (ugly_hack) {
-		/*
-		 * TODO: Somebody figure out how to fix this, please.
-		 *
-		 * The USB configuration descriptor request is unique in that
-		 * it not only returns the configuration descriptor, but also
-		 * all the interface descriptors and all their endpoint
-		 * descriptors as one enormous blob. We've set up some macros
-		 * so we can declare and implement separate interfaces in
-		 * separate files just by compiling them, and all the relevant
-		 * descriptors are sorted and bundled up by the linker. But the
-		 * total length of the entire blob needs to appear in the first
-		 * configuration descriptor struct and because we don't know
-		 * that value until after linking, it can't be initialized as a
-		 * constant. So we have to compute it at run-time and shove it
-		 * in here, which also means that we have to copy the whole
-		 * blob into our TX FIFO buffer so that it's mutable. Otherwise
-		 * we could just point at it (or pretty much any other constant
-		 * struct that we wanted to send to the host). Bah.
-		 */
-		struct usb_config_descriptor *cfg =
-			(struct usb_config_descriptor *)ep0_in_buf;
-		/* set the real descriptor size */
-		cfg->wTotalLength = USB_DESC_SIZE;
-	}
-
-	return len;
-}
-
-/* Handle a Setup that comes with additional data for us. */
-static int handle_setup_with_out_stage(enum table_case tc,
-				       struct usb_setup_packet *req)
-{
-	print_later("handle_setup_with_out_stage(%c)", "0ABCDE67"[tc],
-		    0, 0, 0, 0);
-
-	/* TODO: We don't support any of these. We should. */
-	return -1;
-}
-
-/* Some Setup packets don't have a data stage at all. */
-static int handle_setup_with_no_data_stage(enum table_case tc,
-					   struct usb_setup_packet *req)
-{
-	uint8_t set_addr;
-
-	print_later("handle_setup_with_no_data_stage(%c)", "0ABCDE67"[tc],
-		    0, 0, 0, 0);
-
-	switch (req->bRequest) {
-	case USB_REQ_SET_ADDRESS:
-		/*
-		 * Set the address after the IN packet handshake.
-		 *
-		 * From the USB 2.0 spec, section 9.4.6:
-		 *
-		 * As noted elsewhere, requests actually may result in
-		 * up to three stages. In the first stage, the Setup
-		 * packet is sent to the device. In the optional second
-		 * stage, data is transferred between the host and the
-		 * device. In the final stage, status is transferred
-		 * between the host and the device. The direction of
-		 * data and status transfer depends on whether the host
-		 * is sending data to the device or the device is
-		 * sending data to the host. The Status stage transfer
-		 * is always in the opposite direction of the Data
-		 * stage. If there is no Data stage, the Status stage
-		 * is from the device to the host.
-		 *
-		 * Stages after the initial Setup packet assume the
-		 * same device address as the Setup packet. The USB
-		 * device does not change its device address until
-		 * after the Status stage of this request is completed
-		 * successfully. Note that this is a difference between
-		 * this request and all other requests. For all other
-		 * requests, the operation indicated must be completed
-		 * before the Status stage
-		 */
-		set_addr = req->wValue & 0xff;
-		/*
-		 * NOTE: Now that we've said that, we don't do it. The
-		 * hardware for this SoC knows that an IN packet will
-		 * be following the SET ADDRESS, so it waits until it
-		 * sees that happen before the address change takes
-		 * effect. If we wait until after the IN packet to
-		 * change the register, the hardware gets confused and
-		 * doesn't respond to anything.
-		 */
-		GWRITE_FIELD(USB, DCFG, DEVADDR, set_addr);
-		CPRINTS("SETAD 0x%02x (%d)", set_addr, set_addr);
-		print_later("SETAD 0x%02x (%d)", set_addr, set_addr, 0, 0, 0);
-		device_state = DS_ADDRESS;
-		processed_update_counter = 1;
-		break;
-
-	case USB_REQ_SET_CONFIGURATION:
-		print_later("SETCFG 0x%x", req->wValue, 0, 0, 0, 0);
-		switch (req->wValue) {
-		case 0:
-			configuration_value = req->wValue;
-			device_state = DS_ADDRESS;
-			break;
-		case 1:	    /* Caution: Only one config descriptor TODAY */
-			usb_reset_all_ep_pids();
-			configuration_value = req->wValue;
-			device_state = DS_CONFIGURED;
-			break;
-		default:
-			/* Nope. That's a paddlin. */
-			return -1;
-		}
-		break;
-
-	case USB_REQ_CLEAR_FEATURE:
-	case USB_REQ_SET_FEATURE:
-		/* TODO: Handle DEVICE_REMOTE_WAKEUP, ENDPOINT_HALT? */
-		print_later("SET_FEATURE/CLEAR_FEATURE. Whatever...",
-			    0, 0, 0, 0, 0);
-		break;
-
-	default:
-		/* Anything else is unsupported */
-		return -1;
-	}
-
-	/* No data to transfer, go straight to the Status phase. */
-	return 0;
-}
-
-/* Dispatch an incoming Setup packet according to its type */
-static void handle_setup(enum table_case tc)
-{
-	struct usb_setup_packet *req = cur_out_desc->addr;
-	int data_phase_in = req->bmRequestType & USB_DIR_IN;
-	int data_phase_out = !data_phase_in && req->wLength;
-	int bytes = -1;				/* default is to stall */
-	uint8_t rtype = req->bmRequestType & USB_TYPE_MASK;
-	uint8_t recip = req->bmRequestType & USB_RECIP_MASK;
-
-	print_later("R: %02x %02x %04x %04x %04x",
-		    req->bmRequestType, req->bRequest,
-		    req->wValue, req->wIndex, req->wLength);
-
-	if (rtype == USB_TYPE_STANDARD && recip == USB_RECIP_DEVICE) {
-		/* Standard Device requests */
-		if (data_phase_in)
-			bytes = handle_setup_with_in_stage(tc, req);
-		else if (data_phase_out)
-			bytes = handle_setup_with_out_stage(tc, req);
-		else
-			bytes = handle_setup_with_no_data_stage(tc, req);
-	} else if (recip == USB_RECIP_INTERFACE) {
-		/* Interface-specific requests */
-		uint8_t iface = req->wIndex & 0xff;
-
-		print_later("iface %d request (vs %d)",
-			    iface, USB_IFACE_COUNT, 0, 0, 0);
-		if (iface < USB_IFACE_COUNT) {
-			bytes = usb_iface_request[iface](req);
-			print_later("  iface returned %d", bytes, 0, 0, 0, 0);
-		}
-	} else if (rtype == USB_TYPE_STANDARD && recip == USB_RECIP_ENDPOINT) {
-		/* standard endpoint-specific requests */
-		print_later("ep %d request (vs %d)",
-			    req->wIndex, USB_EP_COUNT, 0, 0, 0);
-		if ((req->wIndex & 0x7f) < USB_EP_COUNT) {
-			/*
-			 * This could call out to
-			 * handle_setup_with_no_data_stage(tc, req) etc but only
-			 * clearing the stall is implemented, and that would
-			 * activate a bunch of other untested code paths.
-			 */
-			if (req->bRequest == USB_REQ_CLEAR_FEATURE) {
-				/* Case for CLEAR_FEATURE(endpoint_halt) */
-				usb_reset_ep_pid(req->wIndex);
-				bytes = 0;
-			} else {
-				report_error(-1);
-			}
-		} else {
-			report_error(-1);
-		}
-#ifdef CONFIG_WEBUSB_URL
-	} else if (data_phase_in && rtype == USB_TYPE_VENDOR) {
-		if (req->bRequest == USB_REQ_CLEAR_FEATURE &&
-		    req->wIndex == WEBUSB_REQ_GET_URL) {
-			bytes = *(uint8_t *)webusb_url;
-			bytes = MIN(req->wLength, bytes);
-			if (load_in_fifo(webusb_url, bytes) < 0)
-				bytes = -1;
-		} else {
-			report_error(-1);
-		}
-#endif
-	} else {
-		/* Something we need to add support for? */
-		report_error(-1);
-	}
-
-	print_later("data_phase_in %d data_phase_out %d bytes %d",
-		    !!data_phase_in, !!data_phase_out, bytes, 0, 0);
-
-	/* We say "no" to unsupported and intentionally unhandled requests by
-	 * stalling the Data and/or Status stage. */
-	if (bytes < 0) {
-		/* Stall both IN and OUT. SETUP will come through anyway. */
-		stall_both_fifos();
-	} else {
-		if (data_phase_in)
-			expect_data_phase_in(tc);
-		else if (data_phase_out)
-			expect_data_phase_out(tc);
-		else
-			expect_status_phase_in(tc);
-	}
-}
-
-/* This handles both IN and OUT interrupts for EP0 */
-static void ep0_interrupt(uint32_t intr_on_out, uint32_t intr_on_in)
-{
-	uint32_t doepint, diepint;
-	enum table_case tc;
-	int sr;
-
-	/* Determine the interrupt cause and clear the bits quickly, but only
-	 * if they really apply. I don't think they're trustworthy if we didn't
-	 * actually get an interrupt. */
-	doepint = GR_USB_DOEPINT(0);
-	if (intr_on_out)
-		GR_USB_DOEPINT(0) = doepint;
-	diepint = GR_USB_DIEPINT(0);
-	if (intr_on_in)
-		GR_USB_DIEPINT(0) = diepint;
-
-	print_later("doepint%c 0x%08x diepint%c 0x%08x what %d",
-		    intr_on_out ? '!' : '_', doepint,
-		    intr_on_in ? '!' : '_', diepint,
-		    what_am_i_doing);
-
-	/* Update current and pending RX FIFO buffers */
-	if (intr_on_out && (doepint & DOEPINT_XFERCOMPL))
-		got_RX_packet();
-
-	/* Decode the situation according to Table 10-7 */
-	tc = decode_table_10_7(doepint);
-	sr = cur_out_desc->flags & DOEPDMA_SR;
-
-	print_later("cur_out_idx %d flags 0x%08x case=%c SR=%d",
-		    cur_out_idx, cur_out_desc->flags,
-		    "0ABCDE67"[tc], !!sr, 0);
-
-	switch (what_am_i_doing) {
-	case WAITING_FOR_SETUP_PACKET:
-		if (tc == TABLE_CASE_A || tc == TABLE_CASE_C) {
-			if (sr) {
-				handle_setup(tc);
-			} else {
-				report_error(tc);
-				print_later("next_out_idx %d flags 0x%08x",
-					    next_out_idx, next_out_desc->flags,
-					    0, 0, 0);
-				expect_setup_packet();
-			}
-		}
-		/* This only happens if we're stalling, so keep doing it. */
-		if (tc == TABLE_CASE_B) {
-			print_later("Still waiting for Setup...",
-				    0, 0, 0, 0, 0);
-			stall_both_fifos();
-		}
-		break;
-
-	case DATA_STAGE_IN:
-		if (intr_on_in && (diepint & DIEPINT_XFERCOMPL)) {
-			print_later("IN is complete? Maybe? How do we know?",
-				    0, 0, 0, 0, 0);
-			/* I don't *think* we need to do this, unless we need
-			 * to transfer more data. Customer support agrees and
-			 * it shouldn't matter if the host is well-behaved, but
-			 * it seems like we had issues without it.
-			 * TODO: Test this case until we know for sure. */
-			GR_USB_DIEPCTL(0) = DXEPCTL_EPENA;
-
-			/*
-			 * The Programmer's Guide says (p291) to stall any
-			 * further INs, but that's stupid because it'll destroy
-			 * the packet we just transferred to SPRAM, so don't do
-			 * that (we tried it anyway, and Bad Things happened).
-			 * Also don't stop here, but keep looking at stuff.
-			 */
-		}
-
-		/* But we should ignore the OUT endpoint if we didn't actually
-		 * get an OUT interrupt. */
-		if (!intr_on_out)
-			break;
-
-		if (tc == TABLE_CASE_B) {
-			print_later("IN has been detected...", 0, 0, 0, 0, 0);
-			/* The first IN packet has been seen. Keep going. */
-			GR_USB_DIEPCTL(0) = DXEPCTL_CNAK | DXEPCTL_EPENA;
-			GR_USB_DOEPCTL(0) = DXEPCTL_CNAK | DXEPCTL_EPENA;
-			break;
-		}
-		if (tc == TABLE_CASE_A) {
-			if (!sr) {
-				/* We've handled the Status phase. All done. */
-				print_later("Status phase complete",
-					    0, 0, 0, 0, 0);
-				expect_setup_packet();
-				break;
-			}
-			/* We expected an OUT, but got a Setup. Deal with it. */
-			print_later("Early Setup", 0, 0, 0, 0, 0);
-			handle_setup(tc);
-			break;
-		}
-		/* From the Exceptional Control Read Transfer section ... */
-		if (tc == TABLE_CASE_C) {
-			if (sr) {
-				print_later("Early Setup w/Data packet seen",
-					    0, 0, 0, 0, 0);
-				handle_setup(tc);
-				break;
-			}
-			print_later("Status phase complete. I think...",
-				    0, 0, 0, 0, 0);
-			expect_setup_packet();
-			break;
-		}
-
-		/* Anything else should be ignorable. Right? */
-		break;
-
-	case NO_DATA_STAGE:
-		if (intr_on_in && (diepint & DIEPINT_XFERCOMPL)) {
-			print_later("IN descriptor processed", 0, 0, 0, 0, 0);
-			/* Let the IN proceed */
-			GR_USB_DIEPCTL(0) = DXEPCTL_EPENA;
-		}
-
-		/* Done unless we got an OUT interrupt */
-		if (!intr_on_out)
-			break;
-
-		if (tc == TABLE_CASE_B) {
-			print_later("IN has been detected...", 0, 0, 0, 0, 0);
-			/* Let the IN proceed */
-			GR_USB_DIEPCTL(0) = DXEPCTL_CNAK | DXEPCTL_EPENA;
-			/* Reenable the previously prepared OUT descriptor. */
-			GR_USB_DOEPCTL(0) = DXEPCTL_CNAK | DXEPCTL_EPENA;
-			break;
-		}
-
-		if (tc == TABLE_CASE_A || tc == TABLE_CASE_C) {
-			if (sr) {
-				/* We expected an IN, but got a Setup. */
-				print_later("Early Setup", 0, 0, 0, 0, 0);
-				handle_setup(tc);
-				break;
-			}
-		}
-
-		/* Anything else means get ready for a Setup packet */
-		print_later("Status phase complete. Maybe.",
-			    0, 0, 0, 0, 0);
-		expect_setup_packet();
-		break;
-	}
-}
-
-/****************************************************************************/
-/* USB device initialization and shutdown routines */
-
-/*
- * DATA FIFO Setup. There is an internal SPRAM used to buffer the IN/OUT
- * packets and track related state without hammering the AHB and system RAM
- * during USB transactions. We have to specify where and how much of that SPRAM
- * to use for what.
- *
- * See Programmer's Guide chapter 2, "Calculating FIFO Size".
- * We're using Dedicated TxFIFO Operation, without enabling thresholding.
- *
- * Section 2.1.1.2, page 30: RXFIFO size is the same as for Shared FIFO, which
- * is Section 2.1.1.1, page 28. This is also the same as Method 2 on page 45.
- *
- * We support up to 3 control EPs, no periodic IN EPs, up to 16 TX EPs. Max
- * data packet size is 64 bytes. Total SPRAM available is 1024 slots.
- */
-#define MAX_CONTROL_EPS   3
-#define MAX_NORMAL_EPS    16
-#define FIFO_RAM_DEPTH    1024
-/*
- * Device RX FIFO size is thus:
- *   (4 * 3 + 6) + 2 * ((64 / 4) + 1) + (2 * 16) + 1 == 85
- */
-#define RXFIFO_SIZE  ((4 * MAX_CONTROL_EPS + 6) + \
-		      2 * ((USB_MAX_PACKET_SIZE / 4) + 1) + \
-		      (2 * MAX_NORMAL_EPS) + 1)
-/*
- * Device TX FIFO size is 2 * (64 / 4) == 32 for each IN EP (Page 46).
- */
-#define TXFIFO_SIZE  (2 * (USB_MAX_PACKET_SIZE / 4))
-/*
- * We need 4 slots per endpoint direction for endpoint status stuff (Table 2-1,
- * unconfigurable).
- */
-#define EP_STATUS_SIZE (4 * MAX_NORMAL_EPS * 2)
-/*
- * Make sure all that fits.
- */
-BUILD_ASSERT(RXFIFO_SIZE + TXFIFO_SIZE * MAX_NORMAL_EPS + EP_STATUS_SIZE <
-	     FIFO_RAM_DEPTH);
-
-/* Now put those constants into the correct registers */
-static void setup_data_fifos(void)
-{
-	int i;
-
-	print_later("setup_data_fifos()", 0, 0, 0, 0, 0);
-
-	/* Programmer's Guide, p31 */
-	GR_USB_GRXFSIZ = RXFIFO_SIZE;			      /* RXFIFO */
-	GR_USB_GNPTXFSIZ = (TXFIFO_SIZE << 16) | RXFIFO_SIZE; /* TXFIFO 0 */
-
-	/* TXFIFO 1..15 */
-	for (i = 1; i < MAX_NORMAL_EPS; i++)
-		GR_USB_DIEPTXF(i) = ((TXFIFO_SIZE << 16) |
-				     (RXFIFO_SIZE + i * TXFIFO_SIZE));
-
-	/*
-	 * TODO: The Programmer's Guide is confusing about when or whether to
-	 * flush the FIFOs. Section 2.1.1.2 (p31) just says to flush. Section
-	 * 2.2.2 (p55) says to stop all the FIFOs first, then flush. Section
-	 * 7.5.4 (p162) says that flushing the RXFIFO at reset is not
-	 * recommended at all.
-	 *
-	 * I'm also unclear on whether or not the individual EPs are expected
-	 * to be disabled already (DIEPCTLn/DOEPCTLn.EPENA == 0), and if so,
-	 * whether by firmware or hardware.
-	 */
-
-	/* Flush all FIFOs according to Section 2.1.1.2 */
-	GR_USB_GRSTCTL = GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH
-		| GRSTCTL_RXFFLSH;
-	while (GR_USB_GRSTCTL & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH))
-		;				/* TODO: timeout 100ms */
-}
-
-static void usb_init_endpoints(void)
-{
-	int ep;
-
-	print_later("usb_init_endpoints()", 0, 0, 0, 0, 0);
-
-	/* Prepare to receive packets on EP0 */
-	initialize_dma_buffers();
-	expect_setup_packet();
-
-	/* Reset the other endpoints */
-	for (ep = 1; ep < USB_EP_COUNT; ep++)
-		usb_ep_reset[ep]();
-}
-
-static void usb_reset(void)
-{
-	CPRINTS("%s, status %x", __func__, GR_USB_GINTSTS);
-	print_later("usb_reset()", 0, 0, 0, 0, 0);
-
-	/* Clear our internal state */
-	device_state = DS_DEFAULT;
-	configuration_value = 0;
-
-	/* Clear the device address */
-	GWRITE_FIELD(USB, DCFG, DEVADDR, 0);
-
-	/* Reinitialize all the endpoints */
-	usb_init_endpoints();
-}
-
-void usb_interrupt(void)
-{
-	uint32_t status = GR_USB_GINTSTS;
-	uint32_t oepint = status & GINTSTS(OEPINT);
-	uint32_t iepint = status & GINTSTS(IEPINT);
-
-	int ep;
-
-	print_later("interrupt: GINTSTS 0x%08x", status, 0, 0, 0, 0);
-
-	/* We can suspend if the host stops talking to us. But if anything else
-	 * comes along (even ERLYSUSP), we should NOT suspend. */
-	if (status & GINTSTS(USBSUSP)) {
-		print_later("usb_suspend()", 0, 0, 0, 0, 0);
-		enable_sleep(SLEEP_MASK_USB_DEVICE);
-	} else {
-		disable_sleep(SLEEP_MASK_USB_DEVICE);
-	}
-
-#ifdef DEBUG_ME
-	if (status & GINTSTS(ERLYSUSP))
-		print_later("usb_early_suspend()", 0, 0, 0, 0, 0);
-
-	if (status & GINTSTS(WKUPINT))
-		print_later("usb_wakeup()", 0, 0, 0, 0, 0);
-
-	if (status & GINTSTS(ENUMDONE))
-		print_later("usb_enumdone()", 0, 0, 0, 0, 0);
-#endif
-
-	if (status & (GINTSTS(RESETDET) | GINTSTS(USBRST)))
-		usb_reset();
-
-	/* Initialize the SOF clock calibrator only on the first SOF */
-	if (GR_USB_GINTMSK & GINTMSK(SOF) && status & GINTSTS(SOF)) {
-		init_sof_clock();
-		GR_USB_GINTMSK &= ~GINTMSK(SOF);
-	}
-
-	/* Endpoint interrupts */
-	if (oepint || iepint) {
-		/* Note: It seems that the DAINT bits are only trustworthy for
-		 * identifying interrupts when selected by the corresponding
-		 * OEPINT and IEPINT bits from GINTSTS. */
-		uint32_t daint = GR_USB_DAINT;
-
-		print_later("  oepint%c iepint%c daint 0x%08x",
-			    oepint ? '!' : '_', iepint ? '!' : '_',
-			    daint, 0, 0);
-
-		/* EP0 has a combined IN/OUT handler. Only call it once, but
-		 * let it know which direction(s) had an interrupt. */
-		if (daint & (DAINT_OUTEP(0) | DAINT_INEP(0))) {
-			uint32_t intr_on_out = (oepint &&
-						(daint & DAINT_OUTEP(0)));
-			uint32_t intr_on_in = (iepint &&
-					       (daint & DAINT_INEP(0)));
-			ep0_interrupt(intr_on_out, intr_on_in);
-		}
-
-		/* Invoke the unidirectional IN and OUT functions for the other
-		 * endpoints. Each handler must clear their own bits in
-		 * DIEPINTn/DOEPINTn. */
-		for (ep = 1; ep < USB_EP_COUNT; ep++) {
-			if (oepint && (daint & DAINT_OUTEP(ep)))
-				usb_ep_rx[ep]();
-			if (iepint && (daint & DAINT_INEP(ep)))
-				usb_ep_tx[ep]();
-		}
-	}
-
-	if (status & GINTSTS(GOUTNAKEFF))
-		GR_USB_DCTL |= DCTL_CGOUTNAK;
-
-	if (status & GINTSTS(GINNAKEFF))
-		GR_USB_DCTL |= DCTL_CGNPINNAK;
-
-	GR_USB_GINTSTS = status;
-
-	print_later("end of interrupt", 0, 0, 0, 0, 0);
-}
-DECLARE_IRQ(GC_IRQNUM_USB0_USBINTR, usb_interrupt, 1);
-
-static void usb_softreset(void)
-{
-	int timeout;
-
-	GR_USB_GRSTCTL = GRSTCTL_CSFTRST;
-	timeout = 10000;
-	while ((GR_USB_GRSTCTL & GRSTCTL_CSFTRST) && timeout-- > 0)
-		;
-	if (GR_USB_GRSTCTL & GRSTCTL_CSFTRST) {
-		CPRINTF("USB: reset failed\n");
-		return;
-	}
-
-	timeout = 10000;
-	while (!(GR_USB_GRSTCTL & GRSTCTL_AHBIDLE) && timeout-- > 0)
-		;
-	if (!timeout) {
-		CPRINTF("USB: reset timeout\n");
-		return;
-	}
-	/* TODO: Wait 3 PHY clocks before returning */
-
-#ifdef BOARD_CR50
-	/*
-	 * TODO(b/63867566): This delay is added to get usb to suspend after
-	 * resume from deep sleep. Find out what the root cause is and add a
-	 * fix.
-	 */
-	usleep(100);
-#endif
-}
-
-void usb_connect(void)
-{
-	print_later("usb_connect()", 0, 0, 0, 0, 0);
-	GR_USB_DCTL &= ~DCTL_SFTDISCON;
-}
-
-void usb_disconnect(void)
-{
-	print_later("usb_disconnect()", 0, 0, 0, 0, 0);
-	GR_USB_DCTL |= DCTL_SFTDISCON;
-
-	device_state = DS_DEFAULT;
-	configuration_value = 0;
-}
-
-void usb_save_suspended_state(void)
-{
-	int i;
-	uint32_t pid = 0;
-
-	/* Record the state the DATA PIDs toggling on each endpoint. */
-	for (i = 1; i < USB_EP_COUNT; i++) {
-		if (GR_USB_DOEPCTL(i) & DXEPCTL_DPID)
-			pid |= BIT(i);
-		if (GR_USB_DIEPCTL(i) & DXEPCTL_DPID)
-			pid |= (1 << (i + 16));
-	}
-	/* Save the USB device address */
-	GREG32(PMU, PWRDN_SCRATCH18) = GR_USB_DCFG;
-	GREG32(PMU, PWRDN_SCRATCH19) = pid;
-
-}
-
-void usb_restore_suspended_state(void)
-{
-	int i;
-	uint32_t pid;
-
-	/* restore the USB device address (the DEVADDR field). */
-	GR_USB_DCFG = GREG32(PMU, PWRDN_SCRATCH18);
-	/* Restore the DATA PIDs on endpoints. */
-	pid = GREG32(PMU, PWRDN_SCRATCH19);
-	for (i = 1; i < USB_EP_COUNT; i++) {
-		GR_USB_DOEPCTL(i) = pid & BIT(i) ?
-			DXEPCTL_SET_D1PID : DXEPCTL_SET_D0PID;
-		GR_USB_DIEPCTL(i) = pid & (1 << (i + 16)) ?
-			DXEPCTL_SET_D1PID : DXEPCTL_SET_D0PID;
-	}
-}
-
-void usb_init(void)
-{
-	int i, resume;
-
-	/* USB is in use */
-	disable_sleep(SLEEP_MASK_USB_DEVICE);
-
-	/*
-	 * Resuming from a deep sleep is a lot like a cold boot, but there are
-	 * few things that we need to do slightly differently. However, we ONLY
-	 * do them if we're really resuming due to a USB wakeup. If we're woken
-	 * for some other reason, we just do a normal USB reset. The host
-	 * doesn't mind.
-	 */
-	resume = ((system_get_reset_flags() & EC_RESET_FLAG_USB_RESUME) &&
-		   (GR_USB_GINTSTS & GC_USB_GINTSTS_WKUPINT_MASK));
-
-	/* TODO(crosbug.com/p/46813): Clean this up. Do only what's needed, and
-	 * use meaningful constants instead of magic numbers. */
-	GREG32(GLOBALSEC, DDMA0_REGION0_CTRL) = 0xffffffff;
-	GREG32(GLOBALSEC, DDMA0_REGION1_CTRL) = 0xffffffff;
-	GREG32(GLOBALSEC, DDMA0_REGION2_CTRL) = 0xffffffff;
-	GREG32(GLOBALSEC, DDMA0_REGION3_CTRL) = 0xffffffff;
-	GREG32(GLOBALSEC, DUSB0_REGION0_CTRL) = 0xffffffff;
-	GREG32(GLOBALSEC, DUSB0_REGION1_CTRL) = 0xffffffff;
-	GREG32(GLOBALSEC, DUSB0_REGION2_CTRL) = 0xffffffff;
-	GREG32(GLOBALSEC, DUSB0_REGION3_CTRL) = 0xffffffff;
-
-	/* Enable clocks */
-	clock_enable_module(MODULE_USB, 1);
-
-	/* TODO(crbug.com/496888): set up pinmux */
-	gpio_config_module(MODULE_USB, 1);
-
-	/* Make sure interrupts are disabled */
-	GR_USB_GINTMSK = 0;
-	GR_USB_DAINTMSK = 0;
-	GR_USB_DIEPMSK = 0;
-	GR_USB_DOEPMSK = 0;
-
-	/* Disable the PHY clock whenever usb suspend is detected */
-	GWRITE_FIELD(USB, PCGCCTL, STOPPCLK, 1);
-
-	/* Select the correct PHY */
-	usb_select_phy(which_phy);
-
-	/* Full-Speed Serial PHY */
-	GR_USB_GUSBCFG = GUSBCFG_PHYSEL_FS | GUSBCFG_FSINTF_6PIN
-		| GUSBCFG_TOUTCAL(7)
-		/* FIXME: Magic number! 14 is for 15MHz! Use 9 for 30MHz */
-		| GUSBCFG_USBTRDTIM(14);
-
-	if (!resume)
-		/* Don't reset on resume, because some preserved internal state
-		 * will be lost and there's no way to restore it. */
-		usb_softreset();
-
-	GR_USB_GUSBCFG = GUSBCFG_PHYSEL_FS | GUSBCFG_FSINTF_6PIN
-		| GUSBCFG_TOUTCAL(7)
-		/* FIXME: Magic number! 14 is for 15MHz! Use 9 for 30MHz */
-		| GUSBCFG_USBTRDTIM(14);
-
-	/* Global + DMA configuration */
-	/* TODO: What about the AHB Burst Length Field? It's 0 now. */
-	GR_USB_GAHBCFG = GAHBCFG_DMA_EN | GAHBCFG_GLB_INTR_EN |
-		GAHBCFG_NP_TXF_EMP_LVL;
-
-	/* Be in disconnected state until we are ready */
-	if (!resume)
-		usb_disconnect();
-
-	if (resume)
-		usb_restore_suspended_state();
-	else
-		/* Init: USB2 FS, Scatter/Gather DMA, DEVADDR = 0x00 */
-		GR_USB_DCFG |= DCFG_DEVSPD_FS48 | DCFG_DESCDMA;
-
-	/* If we've restored a nonzero device address, update our state. */
-	if (GR_USB_DCFG & GC_USB_DCFG_DEVADDR_MASK) {
-		/* Caution: We only have one config TODAY, so there's no real
-		 * difference between DS_CONFIGURED and DS_ADDRESS. */
-		device_state = DS_CONFIGURED;
-		configuration_value = 1;
-	} else {
-		device_state = DS_DEFAULT;
-		configuration_value = 0;
-	}
-
-	/* Now that DCFG.DesDMA is accurate, prepare the FIFOs */
-	setup_data_fifos();
-
-	/* If resuming, reinitialize the endpoints now. For a cold boot we'll
-	 * do this as part of handling the host-driven reset. */
-	if (resume)
-		usb_init_endpoints();
-
-	/* Clear any pending interrupts */
-	for (i = 0; i < 16; i++) {
-		GR_USB_DIEPINT(i) = 0xffffffff;
-		GR_USB_DOEPINT(i) = 0xffffffff;
-	}
-	GR_USB_GINTSTS = 0xFFFFFFFF;
-
-	/* Unmask some endpoint interrupt causes */
-	GR_USB_DIEPMSK = DIEPMSK_EPDISBLDMSK | DIEPMSK_XFERCOMPLMSK;
-	GR_USB_DOEPMSK = DOEPMSK_EPDISBLDMSK | DOEPMSK_XFERCOMPLMSK |
-		DOEPMSK_SETUPMSK;
-
-	/* Enable interrupt handlers */
-	task_enable_irq(GC_IRQNUM_USB0_USBINTR);
-
-	/* Allow USB interrupts to come in */
-	GR_USB_GINTMSK =
-		/* NAK bits that must be cleared by the DCTL register */
-		GINTMSK(GOUTNAKEFF) | GINTMSK(GINNAKEFF) |
-		/* Initialization events */
-		GINTMSK(USBRST) | GINTMSK(ENUMDONE) |
-		/* Endpoint activity, cleared by the DOEPINT/DIEPINT regs */
-		GINTMSK(OEPINT) | GINTMSK(IEPINT) |
-		/* Reset detected while suspended. Need to wake up. */
-		GINTMSK(RESETDET) |		/* TODO: Do we need this? */
-		/* Idle, Suspend detected. Should go to sleep. */
-		GINTMSK(ERLYSUSP) | GINTMSK(USBSUSP) |
-		/* Watch for first SOF and usb wakeup */
-		GINTMSK(SOF) | GINTMSK(WKUPINT);
-
-	/* Device registers have been setup */
-	GR_USB_DCTL |= DCTL_PWRONPRGDONE;
-	udelay(10);
-	GR_USB_DCTL &= ~DCTL_PWRONPRGDONE;
-
-	/* Clear global NAKs */
-	GR_USB_DCTL |= DCTL_CGOUTNAK | DCTL_CGNPINNAK;
-
-#ifndef CONFIG_USB_INHIBIT_CONNECT
-	/* Indicate our presence to the USB host */
-	if (!resume)
-		usb_connect();
-#endif
-}
-#ifndef CONFIG_USB_INHIBIT_INIT
-DECLARE_HOOK(HOOK_INIT, usb_init, HOOK_PRIO_DEFAULT - 2);
-#endif
-
-void usb_release(void)
-{
-	/* signal disconnect to host */
-	usb_disconnect();
-
-	/* disable interrupt handlers */
-	task_disable_irq(GC_IRQNUM_USB0_USBINTR);
-
-	/* Deactivate the PHY */
-	GR_USB_GGPIO = GGPIO_WRITE(USB_CUSTOM_CFG_REG, 0);
-
-	/* disable clocks */
-	clock_enable_module(MODULE_USB, 0);
-	/* TODO: pin-mux */
-
-	/* USB is off, so sleep whenever */
-	enable_sleep(SLEEP_MASK_USB_DEVICE);
-}
-
-static int command_usb(int argc, char **argv)
-{
-	int val;
-
-	if (argc > 1) {
-		if (parse_bool(argv[1], &val)) {
-			if (val)
-				usb_init();
-			else
-				usb_release();
-#ifdef CONFIG_USB_SELECT_PHY
-		} else if (!strcasecmp("a", argv[1])) {
-			usb_select_phy(USB_SEL_PHY0);
-		} else if (!strcasecmp("b", argv[1])) {
-			usb_select_phy(USB_SEL_PHY1);
-#endif
-		} else
-			return EC_ERROR_PARAM1;
-	}
-
-	showregs();
-	ccprintf("PHY %c\n", (which_phy == USB_SEL_PHY0 ? 'A' : 'B'));
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(usb, command_usb,
-#ifdef CONFIG_USB_SELECT_PHY
-			"[<BOOLEAN> | a | b]",
-#else
-			"<BOOLEAN>",
-#endif
-			"Get/set the USB connection state and PHY selection");
-
-#ifdef CONFIG_USB_SERIALNO
-/* This will be subbed into USB_STR_SERIALNO. */
-struct usb_string_desc *usb_serialno_desc =
-	USB_WR_STRING_DESC(DEFAULT_SERIALNO);
-
-/* Update serial number */
-static int usb_set_serial(const char *serialno)
-{
-	struct usb_string_desc *sd = usb_serialno_desc;
-	int i;
-
-	if (!serialno)
-		return EC_ERROR_INVAL;
-
-	/* Convert into unicode usb string desc. */
-	for (i = 0; i < CONFIG_SERIALNO_LEN; i++) {
-		sd->_data[i] = serialno[i];
-		if (serialno[i] == 0)
-			break;
-	}
-	/* Count wchars (w/o null terminator) plus size & type bytes. */
-	sd->_len = (i * 2) + 2;
-	sd->_type = USB_DT_STRING;
-
-	return EC_SUCCESS;
-}
-
-static void usb_load_serialno(void)
-{
-	char devid_str[20];
-
-	snprintf(devid_str, 20, "%08X-%08X", GREG32(FUSE, DEV_ID0),
-		GREG32(FUSE, DEV_ID1));
-
-	usb_set_serial(devid_str);
-}
-DECLARE_HOOK(HOOK_INIT, usb_load_serialno, HOOK_PRIO_DEFAULT - 1);
-
-static int command_serialno(int argc, char **argv)
-{
-	struct usb_string_desc *sd = usb_serialno_desc;
-	char buf[CONFIG_SERIALNO_LEN];
-	int rv = EC_SUCCESS;
-	int i;
-
-	if (argc != 1) {
-		ccprintf("Setting serial number\n");
-		rv = usb_set_serial(argv[1]);
-	}
-
-	for (i = 0; i < CONFIG_SERIALNO_LEN; i++)
-		buf[i] = sd->_data[i];
-	ccprintf("Serial number: %s\n", buf);
-	return rv;
-}
-
-DECLARE_CONSOLE_COMMAND(serialno, command_serialno,
-	"[value]",
-	"Read and write USB serial number");
-#endif
diff --git a/chip/g/usb_console.c b/chip/g/usb_console.c
deleted file mode 100644
index ae36bcd89e..0000000000
--- a/chip/g/usb_console.c
+++ /dev/null
@@ -1,397 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-#include "config.h"
-#include "console.h"
-#include "crc.h"
-#include "link_defs.h"
-#include "printf.h"
-#include "queue.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_descriptor.h"
-#include "usb_hw.h"
-
-/* Console output macro */
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
-#define USB_CONSOLE_TIMEOUT_US (30 * MSEC)
-
-static int last_tx_ok = 1;
-
-static int is_reset;
-
-/*
- * Start enabled, so we can queue early debug output before the board gets
- * around to calling usb_console_enable().
- */
-static int is_enabled = 1;
-
-/*
- * But start read-only, so we don't accept console input until we explicitly
- * decide that we're ready for it.
- */
-static int is_readonly = 1;
-
-/* USB-Serial descriptors */
-const struct usb_interface_descriptor USB_IFACE_DESC(USB_IFACE_CONSOLE) =
-{
-	.bLength            = USB_DT_INTERFACE_SIZE,
-	.bDescriptorType    = USB_DT_INTERFACE,
-	.bInterfaceNumber   = USB_IFACE_CONSOLE,
-	.bAlternateSetting  = 0,
-	.bNumEndpoints      = 2,
-	.bInterfaceClass    = USB_CLASS_VENDOR_SPEC,
-	.bInterfaceSubClass = USB_SUBCLASS_GOOGLE_SERIAL,
-	.bInterfaceProtocol = USB_PROTOCOL_GOOGLE_SERIAL,
-	.iInterface         = USB_STR_CONSOLE_NAME,
-};
-const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_CONSOLE, 0) =
-{
-	.bLength            = USB_DT_ENDPOINT_SIZE,
-	.bDescriptorType    = USB_DT_ENDPOINT,
-	.bEndpointAddress   = 0x80 | USB_EP_CONSOLE,
-	.bmAttributes       = 0x02 /* Bulk IN */,
-	.wMaxPacketSize     = USB_MAX_PACKET_SIZE,
-	.bInterval          = 10
-};
-const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_CONSOLE, 1) =
-{
-	.bLength            = USB_DT_ENDPOINT_SIZE,
-	.bDescriptorType    = USB_DT_ENDPOINT,
-	.bEndpointAddress   = USB_EP_CONSOLE,
-	.bmAttributes       = 0x02 /* Bulk OUT */,
-	.wMaxPacketSize     = USB_MAX_PACKET_SIZE,
-	.bInterval          = 0
-};
-
-static uint8_t ep_buf_tx[USB_MAX_PACKET_SIZE];
-static uint8_t ep_buf_rx[USB_MAX_PACKET_SIZE];
-static struct g_usb_desc ep_out_desc;
-static struct g_usb_desc ep_in_desc;
-
-static struct queue const tx_q = QUEUE_NULL(4096, uint8_t);
-static struct queue const rx_q = QUEUE_NULL(USB_MAX_PACKET_SIZE, uint8_t);
-
-
-/* Let the USB HW IN-to-host FIFO transmit some bytes */
-static void usb_enable_tx(int len)
-{
-	ep_in_desc.flags = DIEPDMA_LAST | DIEPDMA_BS_HOST_RDY | DIEPDMA_IOC |
-			   DIEPDMA_TXBYTES(len);
-	GR_USB_DIEPCTL(USB_EP_CONSOLE) |= DXEPCTL_CNAK | DXEPCTL_EPENA;
-}
-
-/* Let the USB HW OUT-from-host FIFO receive some bytes */
-static void usb_enable_rx(int len)
-{
-	ep_out_desc.flags = DOEPDMA_RXBYTES(len) |
-			    DOEPDMA_LAST | DOEPDMA_BS_HOST_RDY | DOEPDMA_IOC;
-	GR_USB_DOEPCTL(USB_EP_CONSOLE) |= DXEPCTL_CNAK | DXEPCTL_EPENA;
-}
-
-/* True if the HW Rx/OUT FIFO has bytes for us. */
-static inline int rx_fifo_is_ready(void)
-{
-	return (ep_out_desc.flags & DOEPDMA_BS_MASK) == DOEPDMA_BS_DMA_DONE;
-}
-
-static void rx_fifo_handler(void);
-DECLARE_DEFERRED(rx_fifo_handler);
-
-/*
- * This function tries to shove new bytes from the USB host into the queue for
- * consumption elsewhere. It is invoked either by a HW interrupt (telling us we
- * have new bytes from the USB host), or by whoever is reading bytes out of the
- * other end of the queue (telling us that there's now more room in the queue
- * if we still have bytes to shove in there).
- */
-static void rx_fifo_handler(void)
-{
-	/*
-	 * The HW FIFO buffer (ep_buf_rx) is always filled from [0] by the
-	 * hardware. The rx_in_fifo variable counts how many bytes of that
-	 * buffer are actually valid, and is calculated from the HW DMA
-	 * descriptor table. The descriptor is updated by the hardware, and it
-	 * and ep_buf_rx remains valid and unchanged until software tells the
-	 * the hardware engine to accept more input.
-	 */
-	int rx_in_fifo, rx_left;
-
-	/*
-	 * The rx_handled variable tracks how many of the bytes in the HW FIFO
-	 * we've copied into the incoming queue. The queue may not accept all
-	 * of them at once, so we have to keep track of where we are so that
-	 * the next time this function is called we can try to shove the rest
-	 * of the HW FIFO bytes into the queue.
-	 */
-	static int rx_handled;
-
-	/* If the HW FIFO isn't ready, then we're waiting for more bytes */
-	if (!rx_fifo_is_ready())
-		return;
-
-	/*
-	 * How many of the HW FIFO bytes have we not yet handled? We need to
-	 * know both where we are in the buffer and how many bytes we haven't
-	 * yet enqueued. One can be calculated from the other as long as we
-	 * know rx_in_fifo, but we need at least one static variable.
-	 */
-	rx_in_fifo = USB_MAX_PACKET_SIZE
-		- (ep_out_desc.flags & DOEPDMA_RXBYTES_MASK);
-	rx_left = rx_in_fifo - rx_handled;
-
-	/* If we have some, try to shove them into the queue */
-	if (rx_left) {
-		size_t added = QUEUE_ADD_UNITS(&rx_q, ep_buf_rx + rx_handled,
-					       rx_left);
-		rx_handled += added;
-		rx_left -= added;
-	}
-
-	if (rx_handled)
-		task_wake(TASK_ID_CONSOLE);
-	/*
-	 * When we've handled all the bytes in the queue ("rx_in_fifo ==
-	 * rx_handled" and "rx_left == 0" indicate the same thing), we can
-	 * reenable the USB HW to go fetch more.
-	 */
-	if (!rx_left) {
-		rx_handled = 0;
-		usb_enable_rx(USB_MAX_PACKET_SIZE);
-	} else {
-		hook_call_deferred(&rx_fifo_handler_data, 0);
-	}
-}
-
-/* Rx/OUT interrupt handler */
-static void con_ep_rx(void)
-{
-	/* Wake up the Rx FIFO handler */
-	hook_call_deferred(&rx_fifo_handler_data, 0);
-
-	/* clear the RX/OUT interrupts */
-	GR_USB_DOEPINT(USB_EP_CONSOLE) = 0xffffffff;
-}
-/* True if the Tx/IN FIFO can take some bytes from us. */
-static inline int tx_fifo_is_ready(void)
-{
-	uint32_t status = ep_in_desc.flags & DIEPDMA_BS_MASK;
-	return status == DIEPDMA_BS_DMA_DONE || status == DIEPDMA_BS_HOST_BSY;
-}
-
-/* Try to send some bytes to the host */
-static void tx_fifo_handler(void)
-{
-	size_t count;
-
-	if (!is_reset)
-		return;
-
-	/* If the HW FIFO isn't ready, then we can't do anything right now. */
-	if (!tx_fifo_is_ready())
-		return;
-
-	count = QUEUE_REMOVE_UNITS(&tx_q, ep_buf_tx, USB_MAX_PACKET_SIZE);
-	if (count)
-		usb_enable_tx(count);
-}
-DECLARE_DEFERRED(tx_fifo_handler);
-
-static void handle_output(void)
-{
-	/* Wake up the Tx FIFO handler */
-	hook_call_deferred(&tx_fifo_handler_data, 0);
-}
-
-/* Tx/IN interrupt handler */
-static void con_ep_tx(void)
-{
-	/* Wake up the Tx FIFO handler */
-	hook_call_deferred(&tx_fifo_handler_data, 0);
-
-	/* clear the Tx/IN interrupts */
-	GR_USB_DIEPINT(USB_EP_CONSOLE) = 0xffffffff;
-}
-
-static void ep_reset(void)
-{
-	ep_out_desc.flags = DOEPDMA_RXBYTES(USB_MAX_PACKET_SIZE) |
-			    DOEPDMA_LAST | DOEPDMA_BS_HOST_RDY | DOEPDMA_IOC;
-	ep_out_desc.addr = ep_buf_rx;
-	GR_USB_DOEPDMA(USB_EP_CONSOLE) = (uint32_t)&ep_out_desc;
-	ep_in_desc.flags = DIEPDMA_LAST | DIEPDMA_BS_HOST_BSY | DIEPDMA_IOC;
-	ep_in_desc.addr = ep_buf_tx;
-	GR_USB_DIEPDMA(USB_EP_CONSOLE) = (uint32_t)&ep_in_desc;
-	GR_USB_DOEPCTL(USB_EP_CONSOLE) = DXEPCTL_MPS(64) | DXEPCTL_USBACTEP |
-					 DXEPCTL_EPTYPE_BULK |
-					 DXEPCTL_CNAK | DXEPCTL_EPENA;
-	GR_USB_DIEPCTL(USB_EP_CONSOLE) = DXEPCTL_MPS(64) | DXEPCTL_USBACTEP |
-					 DXEPCTL_EPTYPE_BULK |
-					 DXEPCTL_TXFNUM(USB_EP_CONSOLE);
-	GR_USB_DAINTMSK |= DAINT_INEP(USB_EP_CONSOLE) |
-			   DAINT_OUTEP(USB_EP_CONSOLE);
-
-	is_reset = 1;
-
-	/* Flush any queued data */
-	hook_call_deferred(&tx_fifo_handler_data, 0);
-	hook_call_deferred(&rx_fifo_handler_data, 0);
-}
-
-
-USB_DECLARE_EP(USB_EP_CONSOLE, con_ep_tx, con_ep_rx, ep_reset);
-
-static int usb_wait_console(void)
-{
-	timestamp_t deadline = get_time();
-	int wait_time_us = 1;
-
-	if (!is_enabled || !tx_fifo_is_ready())
-		return EC_SUCCESS;
-
-	deadline.val += USB_CONSOLE_TIMEOUT_US;
-
-	/*
-	 * If the USB console is not used, Tx buffer would never free up.
-	 * In this case, let's drop characters immediately instead of sitting
-	 * for some time just to time out. On the other hand, if the last
-	 * Tx is good, it's likely the host is there to receive data, and
-	 * we should wait so that we don't clobber the buffer.
-	 */
-	if (last_tx_ok) {
-		while (queue_space(&tx_q) < USB_MAX_PACKET_SIZE || !is_reset) {
-			if (timestamp_expired(deadline, NULL) ||
-			    in_interrupt_context()) {
-				last_tx_ok = 0;
-				return EC_ERROR_TIMEOUT;
-			}
-			if (wait_time_us < MSEC)
-				udelay(wait_time_us);
-			else
-				usleep(wait_time_us);
-			wait_time_us *= 2;
-		}
-
-		return EC_SUCCESS;
-	} else {
-		last_tx_ok = queue_space(&tx_q);
-		return EC_SUCCESS;
-	}
-}
-
-#ifdef CONFIG_USB_CONSOLE_CRC
-static uint32_t usb_tx_crc_ctx;
-
-void usb_console_crc_init(void)
-{
-	crc32_ctx_init(&usb_tx_crc_ctx);
-}
-
-uint32_t usb_console_crc(void)
-{
-	return crc32_ctx_result(&usb_tx_crc_ctx);
-}
-#endif
-
-static int __tx_char(void *context, int c)
-{
-	struct queue *state =
-			(struct queue *) context;
-
-	if (c == '\n' && __tx_char(state, '\r'))
-		return 1;
-
-#ifdef CONFIG_USB_CONSOLE_CRC
-	crc32_ctx_hash8(&usb_tx_crc_ctx, c);
-
-	while (QUEUE_ADD_UNITS(state, &c, 1) != 1)
-		usleep(500);
-#else
-	QUEUE_ADD_UNITS(state, &c, 1);
-#endif
-	return 0;
-}
-
-/*
- * Public USB console implementation below.
- */
-int usb_getc(void)
-{
-	int c;
-
-	if (is_readonly || !is_enabled)
-		return -1;
-
-	if (QUEUE_REMOVE_UNITS(&rx_q, &c, 1))
-		return c;
-	return -1;
-}
-
-int usb_puts(const char *outstr)
-{
-	int ret;
-	struct queue state;
-
-	if (!is_enabled)
-		return EC_SUCCESS;
-
-	ret  = usb_wait_console();
-	if (ret)
-		return ret;
-
-	state = tx_q;
-	while (*outstr)
-		if (__tx_char(&state, *outstr++))
-			break;
-
-	if (queue_count(&state))
-		handle_output();
-
-	return *outstr ? EC_ERROR_OVERFLOW : EC_SUCCESS;
-}
-
-int usb_putc(int c)
-{
-	char string[2];
-
-	string[0] = c;
-	string[1] = '\0';
-	return usb_puts(string);
-}
-
-int usb_vprintf(const char *format, va_list args)
-{
-	int ret;
-	struct queue state;
-
-	if (!is_enabled)
-		return EC_SUCCESS;
-
-	ret = usb_wait_console();
-	if (ret)
-		return ret;
-
-	state = tx_q;
-	ret = vfnprintf(__tx_char, &state, format, args);
-
-	if (queue_count(&state))
-		handle_output();
-
-	return ret;
-}
-
-void usb_console_enable(int enabled, int readonly)
-{
-	is_enabled = enabled;
-	is_readonly = readonly;
-}
-
-int usb_console_tx_blocked(void)
-{
-	return is_enabled && (queue_space(&tx_q) < USB_MAX_PACKET_SIZE);
-}
diff --git a/chip/g/usb_endpoints.c b/chip/g/usb_endpoints.c
deleted file mode 100644
index fe40659778..0000000000
--- a/chip/g/usb_endpoints.c
+++ /dev/null
@@ -1,158 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * USB endpoints/interfaces callbacks declaration
- */
-
-#include "config.h"
-#include "common.h"
-#include "usb_hw.h"
-
-typedef void (*xfer_func)(void);
-typedef void (*rst_func) (void);
-typedef int (*iface_func)(struct usb_setup_packet *req);
-#ifndef PASS
-#define PASS 1
-#endif
-
-#if PASS == 1
-void ep_undefined(void)
-{
-	return;
-}
-
-void ep_rst_undefined(void)
-{
-	return;
-}
-
-/* Undefined interface callbacks fail by returning non-zero*/
-int iface_undefined(struct usb_setup_packet *req)
-{
-	return 1;
-}
-
-#define table(type, name, x) x
-
-#define endpoint_tx(number) \
-	extern void __attribute__((used, weak, alias("ep_undefined"))) \
-		ep_ ## number ## _tx(void);
-#define endpoint_rx(number) \
-	extern void __attribute__((used, weak, alias("ep_undefined"))) \
-		ep_ ## number ## _rx(void);
-#define endpoint_rst(number) \
-	extern void __attribute__((used, weak, alias("ep_rst_undefined"))) \
-		ep_ ## number ## _rst(void);
-#define interface(number) \
-	extern int __attribute__((used, weak, alias("iface_undefined"))) \
-		iface_ ## number ## _request(struct usb_setup_packet *req);
-
-#define null
-
-#endif /* PASS 1 */
-
-#if PASS == 2
-#undef table
-#undef endpoint_tx
-#undef endpoint_rx
-#undef endpoint_rst
-#undef interface
-#undef null
-
-/* align function pointers on a 32-bit boundary */
-#define table(type, name, x) type name[] __attribute__((aligned(4),section(".rodata.usb_ep." #name ",\"a\" @"))) = { x };
-#define null (void *)0
-
-#define ep_(num, suf) CONCAT3(ep_, num, suf)
-#define ep(num, suf) ep_(num, suf)
-
-#define endpoint_tx(number) \
-	[number < USB_EP_COUNT ? number : USB_EP_COUNT - 1] = ep_ ## number ## _tx,
-#define endpoint_rx(number) \
-	[number < USB_EP_COUNT ? number : USB_EP_COUNT - 1] = ep_ ## number ## _rx,
-#define endpoint_rst(number) \
-	[number < USB_EP_COUNT ? number : USB_EP_COUNT - 1] = ep_ ## number ## _rst,
-#define interface(number) \
-	[number < USB_IFACE_COUNT ? number : USB_IFACE_COUNT - 1] = iface_ ## number ## _request,
-#endif /* PASS 2 */
-
-/*
- * The initializers are listed backwards, but that's so that the items beyond
- * the chip's limit are first assigned to the last field, then overwritten by
- * its actual value due to the designated initializers in the macros above.
- * It all sorts out nicely
- */
-table(xfer_func, usb_ep_tx,
-	endpoint_tx(15)
-	endpoint_tx(14)
-	endpoint_tx(13)
-	endpoint_tx(12)
-	endpoint_tx(11)
-	endpoint_tx(10)
-	endpoint_tx(9)
-	endpoint_tx(8)
-	endpoint_tx(7)
-	endpoint_tx(6)
-	endpoint_tx(5)
-	endpoint_tx(4)
-	endpoint_tx(3)
-	endpoint_tx(2)
-	endpoint_tx(1)
-	endpoint_tx(0)
-)
-
-table(xfer_func, usb_ep_rx,
-	endpoint_rx(15)
-	endpoint_rx(14)
-	endpoint_rx(13)
-	endpoint_rx(12)
-	endpoint_rx(11)
-	endpoint_rx(10)
-	endpoint_rx(9)
-	endpoint_rx(8)
-	endpoint_rx(7)
-	endpoint_rx(6)
-	endpoint_rx(5)
-	endpoint_rx(4)
-	endpoint_rx(3)
-	endpoint_rx(2)
-	endpoint_rx(1)
-	endpoint_rx(0)
-)
-
-table(rst_func, usb_ep_reset,
-	endpoint_rst(15)
-	endpoint_rst(14)
-	endpoint_rst(13)
-	endpoint_rst(12)
-	endpoint_rst(11)
-	endpoint_rst(10)
-	endpoint_rst(9)
-	endpoint_rst(8)
-	endpoint_rst(7)
-	endpoint_rst(6)
-	endpoint_rst(5)
-	endpoint_rst(4)
-	endpoint_rst(3)
-	endpoint_rst(2)
-	endpoint_rst(1)
-	endpoint_rst(0)
-)
-
-table(iface_func, usb_iface_request,
-	interface(7)
-	interface(6)
-	interface(5)
-	interface(4)
-	interface(3)
-	interface(2)
-	interface(1)
-	interface(0)
-)
-
-#if PASS == 1
-#undef PASS
-#define PASS 2
-#include "usb_endpoints.c"
-#endif
diff --git a/chip/g/usb_hid_keyboard.c b/chip/g/usb_hid_keyboard.c
deleted file mode 100644
index d6b529839f..0000000000
--- a/chip/g/usb_hid_keyboard.c
+++ /dev/null
@@ -1,159 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "clock.h"
-#include "common.h"
-#include "config.h"
-#include "console.h"
-#include "gpio.h"
-#include "hooks.h"
-#include "link_defs.h"
-#include "registers.h"
-#include "task.h"
-#include "timer.h"
-#include "util.h"
-#include "usb_descriptor.h"
-#include "usb_hid.h"
-
-/* Console output macro */
-#define CPRINTF(format, args...) cprintf(CC_USB, format, ## args)
-
-#define HID_REPORT_SIZE  8
-
-/* HID descriptors */
-const struct usb_interface_descriptor USB_IFACE_DESC(USB_IFACE_HID) = {
-	.bLength = USB_DT_INTERFACE_SIZE,
-	.bDescriptorType = USB_DT_INTERFACE,
-	.bInterfaceNumber = USB_IFACE_HID_KEYBOARD,
-	.bAlternateSetting = 0,
-	.bNumEndpoints = 1,
-	.bInterfaceClass = USB_CLASS_HID,
-	.bInterfaceSubClass = USB_HID_SUBCLASS_BOOT,
-	.bInterfaceProtocol = USB_HID_PROTOCOL_KEYBOARD,
-	.iInterface = USB_STR_HID_KEYBOARD_NAME,
-};
-const struct usb_endpoint_descriptor USB_EP_DESC(USB_IFACE_HID, 81) = {
-	.bLength = USB_DT_ENDPOINT_SIZE,
-	.bDescriptorType = USB_DT_ENDPOINT,
-	.bEndpointAddress = 0x80 | USB_EP_HID_KEYBOARD,
-	.bmAttributes = 0x03 /* Interrupt endpoint */,
-	.wMaxPacketSize = HID_REPORT_SIZE,
-	.bInterval = 32 /* ms polling interval */
-};
-const struct usb_hid_descriptor USB_CUSTOM_DESC(USB_IFACE_HID, hid) = {
-	.bLength = 9,
-	.bDescriptorType = USB_HID_DT_HID,
-	.bcdHID = 0x0100,
-	.bCountryCode = 0x00, /* Hardware target country */
-	.bNumDescriptors = 1,
-	.desc = {
-		{.bDescriptorType = USB_HID_DT_REPORT,
-		.wDescriptorLength = 45}
-	}
-};
-
-/* HID : Report Descriptor */
-static const uint8_t report_desc[] = {
-	0x05, 0x01, /* Usage Page (Generic Desktop) */
-	0x09, 0x06, /* Usage (Keyboard) */
-	0xA1, 0x01, /* Collection (Application) */
-	0x05, 0x07, /* Usage Page (Key Codes) */
-	0x19, 0xE0, /* Usage Minimum (224) */
-	0x29, 0xE7, /* Usage Maximum (231) */
-	0x15, 0x00, /* Logical Minimum (0) */
-	0x25, 0x01, /* Logical Maximum (1) */
-	0x75, 0x01, /* Report Size (1) */
-	0x95, 0x08, /* Report Count (8) */
-	0x81, 0x02, /* Input (Data, Variable, Absolute), ;Modifier byte */
-
-	0x95, 0x01, /* Report Count (1) */
-	0x75, 0x08, /* Report Size (8) */
-	0x81, 0x01, /* Input (Constant), ;Reserved byte */
-
-	0x95, 0x06, /* Report Count (6) */
-	0x75, 0x08, /* Report Size (8) */
-	0x15, 0x00, /* Logical Minimum (0) */
-	0x25, 0x65, /* Logical Maximum(101) */
-	0x05, 0x07, /* Usage Page (Key Codes) */
-	0x19, 0x00, /* Usage Minimum (0) */
-	0x29, 0x65, /* Usage Maximum (101) */
-	0x81, 0x00, /* Input (Data, Array), ;Key arrays (6 bytes) */
-	0xC0,       /* End Collection */
-	0x00        /* Padding */
-};
-
-static uint8_t hid_ep_buf[HID_REPORT_SIZE];
-static struct g_usb_desc hid_ep_desc;
-
-void set_keyboard_report(uint64_t rpt)
-{
-	memcpy(hid_ep_buf, &rpt, sizeof(rpt));
-	hid_ep_desc.flags = DIEPDMA_LAST | DIEPDMA_BS_HOST_RDY | DIEPDMA_IOC |
-			    DIEPDMA_TXBYTES(HID_REPORT_SIZE);
-	/* enable TX */
-	GR_USB_DIEPCTL(USB_EP_HID_KEYBOARD) |= DXEPCTL_CNAK | DXEPCTL_EPENA;
-}
-
-static void hid_tx(void)
-{
-	/* clear IT */
-	GR_USB_DIEPINT(USB_EP_HID_KEYBOARD) = 0xffffffff;
-	return;
-}
-
-static void hid_reset(void)
-{
-	hid_ep_desc.flags = DIEPDMA_LAST | DIEPDMA_BS_HOST_BSY | DIEPDMA_IOC;
-	hid_ep_desc.addr = hid_ep_buf;
-	GR_USB_DIEPDMA(USB_EP_HID_KEYBOARD) = (uint32_t)&hid_ep_desc;
-	GR_USB_DIEPCTL(USB_EP_HID_KEYBOARD) = DXEPCTL_MPS(HID_REPORT_SIZE) |
-				     DXEPCTL_USBACTEP | DXEPCTL_EPTYPE_INT |
-				     DXEPCTL_TXFNUM(USB_EP_HID_KEYBOARD);
-	GR_USB_DAINTMSK |= DAINT_INEP(USB_EP_HID_KEYBOARD);
-}
-
-USB_DECLARE_EP(USB_EP_HID_KEYBOARD, hid_tx, hid_tx, hid_reset);
-
-static int hid_iface_request(struct usb_setup_packet *req)
-{
-	if ((req->bmRequestType & USB_DIR_IN) &&
-	    req->bRequest == USB_REQ_GET_DESCRIPTOR &&
-	    req->wValue == (USB_HID_DT_REPORT << 8)) {
-		/* Setup : HID specific : Get Report descriptor */
-		return load_in_fifo(report_desc,
-				    MIN(req->wLength,
-					sizeof(report_desc)));
-	}
-
-	/* Anything else we'll stall */
-	return -1;
-}
-USB_DECLARE_IFACE(USB_IFACE_HID_KEYBOARD, hid_iface_request);
-
-#ifdef CR50_DEV
-/* Just for debugging */
-static int command_hid(int argc, char **argv)
-{
-	uint8_t keycode = 0x0a; /* 'G' key */
-
-	if (argc >= 2) {
-		char *e;
-
-		keycode = strtoi(argv[1], &e, 16);
-		if (*e)
-			return EC_ERROR_PARAM1;
-	}
-
-	/* press then release the key */
-	set_keyboard_report((uint32_t)keycode << 16);
-	udelay(50 * MSEC);
-	set_keyboard_report(0x000000);
-
-	return EC_SUCCESS;
-}
-DECLARE_CONSOLE_COMMAND(hid, command_hid,
-			"[<HID keycode>]",
-			"test USB HID driver");
-#endif
diff --git a/chip/g/usb_hw.h b/chip/g/usb_hw.h
deleted file mode 100644
index 03cabce5a6..0000000000
--- a/chip/g/usb_hw.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __CROS_EC_USB_HW_H
-#define __CROS_EC_USB_HW_H
-
-/* Helpers for endpoint declaration */
-#define _EP_HANDLER2(num, suffix) CONCAT3(ep_, num, suffix)
-#define _EP_TX_HANDLER(num) _EP_HANDLER2(num, _tx)
-#define _EP_RX_HANDLER(num) _EP_HANDLER2(num, _rx)
-#define _EP_RESET_HANDLER(num) _EP_HANDLER2(num, _rst)
-
-#define USB_DECLARE_EP(num, tx_handler, rx_handler, rst_handler)  \
-	void _EP_TX_HANDLER(num)(void)				  \
-		__attribute__ ((alias(STRINGIFY(tx_handler))));	  \
-	void _EP_RX_HANDLER(num)(void)                            \
-		__attribute__ ((alias(STRINGIFY(rx_handler))));	  \
-	void _EP_RESET_HANDLER(num)(void)                         \
-		__attribute__ ((alias(STRINGIFY(rst_handler))))
-
-/* Endpoint callbacks */
-extern void (*usb_ep_tx[]) (void);
-extern void (*usb_ep_rx[]) (void);
-extern void (*usb_ep_reset[]) (void);
-struct usb_setup_packet;
-/* EP0 Interface handler callbacks */
-extern int (*usb_iface_request[]) (struct usb_setup_packet *req);
-
-/*
- * Declare any interface-specific control request handlers. These Setup packets
- * arrive on the control endpoint (EP0), but are handled by the interface code.
- * The callback must prepare the EP0 IN or OUT FIFOs and return the number of
- * bytes placed in the IN FIFO. A negative return value will STALL the response
- * (and thus indicate error to the host).
- */
-#define _IFACE_HANDLER(num) CONCAT3(iface_, num, _request)
-#define USB_DECLARE_IFACE(num, handler)				\
-	int _IFACE_HANDLER(num)(struct usb_setup_packet *req)	\
-		__attribute__ ((alias(STRINGIFY(handler))))
-
-/*
- * The interface handler can call this to put <len> bytes into the EP0 TX FIFO
- * (zero is acceptable). It returns (int)<len> on success, -1 if <len> is too
- * large.
- */
-int load_in_fifo(const void *source, uint32_t len);
-
-/*
- * The interface handler can call this to enable the EP0 RX FIFO to receive
- * <len> bytes of data for a Control Write request. This is not needed to
- * prepare for the Status phase of a Control Read. It will return (int)<len> on
- * success, -1 if <len> is too large.
- */
-int accept_out_fifo(uint32_t len);
-
-#endif	/* __CROS_EC_USB_HW_H */
diff --git a/chip/g/usb_spi.c b/chip/g/usb_spi.c
deleted file mode 100644
index d7f7ff031f..0000000000
--- a/chip/g/usb_spi.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "ccd_config.h"
-#include "common.h"
-#include "link_defs.h"
-#include "gpio.h"
-#include "registers.h"
-#include "spi.h"
-#include "spi_flash.h"
-#include "usb_descriptor.h"
-#include "usb_spi.h"
-#include "util.h"
-
-#ifdef CONFIG_STREAM_SIGNATURE
-#include "signing.h"
-#endif
-
-#define CPUTS(outstr) cputs(CC_USB, outstr)
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
-
-static int16_t usb_spi_map_error(int error)
-{
-	switch (error) {
-	case EC_SUCCESS:
-		return USB_SPI_SUCCESS;
-	case EC_ERROR_TIMEOUT:
-		return USB_SPI_TIMEOUT;
-	case EC_ERROR_BUSY:
-		return USB_SPI_BUSY;
-	default:
-		return USB_SPI_UNKNOWN_ERROR | (error & 0x7fff);
-	}
-}
-
-static uint16_t usb_spi_read_packet(struct usb_spi_config const *config)
-{
-	return QUEUE_REMOVE_UNITS(config->consumer.queue, config->buffer,
-		queue_count(config->consumer.queue));
-}
-
-static void usb_spi_write_packet(struct usb_spi_config const *config,
-				 uint8_t count)
-{
-#ifdef CONFIG_STREAM_SIGNATURE
-	/*
-	 * This hook allows mn50 to sign SPI data read from newly
-	 * manufactured H1 devieces. The data is added to a running
-	 * hash until a completion message is received.
-	 */
-	sig_append(stream_spi, config->buffer, count);
-#endif
-
-	QUEUE_ADD_UNITS(config->tx_queue, config->buffer, count);
-}
-
-void usb_spi_deferred(struct usb_spi_config const *config)
-{
-	uint16_t count;
-	int write_count;
-	int read_count;
-	int read_length;
-	uint16_t res;
-	int rv = EC_SUCCESS;
-
-	/*
-	 * If our overall enabled state has changed we call the board specific
-	 * enable or disable routines and save our new state.
-	 */
-	int enabled = !!(config->state->enabled_host &
-			 config->state->enabled_device);
-
-	if (enabled ^ config->state->enabled) {
-		if (enabled)
-			rv = usb_spi_board_enable(config);
-		else
-			usb_spi_board_disable(config);
-
-		/* Only update our state if we were successful. */
-		if (rv == EC_SUCCESS)
-			config->state->enabled = enabled;
-	}
-
-	/*
-	 * And if there is a USB packet waiting we process it and generate a
-	 * response.
-	 */
-	count       = usb_spi_read_packet(config);
-	write_count = config->buffer[0];
-	read_count  = config->buffer[1];
-
-	/* Handle SPI_READBACK_ALL case */
-	if (read_count == 255) {
-		/* Handle simultaneously clocked RX and TX */
-		read_count = SPI_READBACK_ALL;
-		read_length = write_count;
-	} else {
-		/* Normal case */
-		read_length = read_count;
-	}
-
-	if (!count || (!read_count && !write_count) ||
-	    (!write_count && read_count == (uint8_t)SPI_READBACK_ALL))
-		return;
-
-	if (!config->state->enabled) {
-		res = USB_SPI_DISABLED;
-	} else if (write_count > USB_SPI_MAX_WRITE_COUNT ||
-		   write_count != (count - HEADER_SIZE)) {
-		res = USB_SPI_WRITE_COUNT_INVALID;
-	} else if (read_length > USB_SPI_MAX_READ_COUNT) {
-		res = USB_SPI_READ_COUNT_INVALID;
-	} else {
-		res = usb_spi_map_error(
-			spi_transaction(SPI_FLASH_DEVICE,
-					config->buffer + HEADER_SIZE,
-					write_count,
-					config->buffer + HEADER_SIZE,
-					read_count));
-	}
-
-	memcpy(config->buffer, &res, HEADER_SIZE);
-	usb_spi_write_packet(config, read_length + HEADER_SIZE);
-}
-
-static void usb_spi_written(struct consumer const *consumer, size_t count)
-{
-	struct usb_spi_config const *config =
-		DOWNCAST(consumer, struct usb_spi_config, consumer);
-
-	hook_call_deferred(config->deferred, 0);
-}
-
-struct consumer_ops const usb_spi_consumer_ops = {
-	.written = usb_spi_written,
-};
-
-void usb_spi_enable(struct usb_spi_config const *config, int enabled)
-{
-	config->state->enabled_device = 0;
-	if (enabled) {
-#ifdef CONFIG_CASE_CLOSED_DEBUG_V1
-		if (ccd_is_cap_enabled(CCD_CAP_AP_FLASH))
-			config->state->enabled_device |= USB_SPI_AP;
-		if (ccd_is_cap_enabled(CCD_CAP_EC_FLASH))
-			config->state->enabled_device |= USB_SPI_EC;
-#else
-		config->state->enabled_device = USB_SPI_ALL;
-#endif
-	}
-
-	hook_call_deferred(config->deferred, 0);
-}
-
diff --git a/chip/g/usb_spi.h b/chip/g/usb_spi.h
deleted file mode 100644
index a98157753f..0000000000
--- a/chip/g/usb_spi.h
+++ /dev/null
@@ -1,248 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#ifndef __CROS_EC_USB_SPI_H
-#define __CROS_EC_USB_SPI_H
-
-/* USB SPI driver for Chrome EC */
-
-#include "compile_time_macros.h"
-#include "hooks.h"
-#include "queue.h"
-#include "queue_policies.h"
-#include "usb_descriptor.h"
-#include "usb-stream.h"
-
-#define HEADER_SIZE 2
-
-/*
- * Command:
- *     +------------------+-----------------+------------------------+
- *     | write count : 1B | read count : 1B | write payload : <= 62B |
- *     +------------------+-----------------+------------------------+
- *
- *     write count:   1 byte, zero based count of bytes to write
- *
- *     read count:    1 byte, zero based count of bytes to read
- *
- *     write payload: up to 62 bytes of data to write, length must match
- *                    write count
- *
- * Response:
- *     +-------------+-----------------------+
- *     | status : 2B | read payload : <= 62B |
- *     +-------------+-----------------------+
- *
- *     status: 2 byte status
- *         0x0000: Success
- *         0x0001: SPI timeout
- *         0x0002: Busy, try again
- *             This can happen if someone else has acquired the shared memory
- *             buffer that the SPI driver uses as /dev/null
- *         0x0003: Write count invalid (> 62 bytes, or mismatch with payload)
- *         0x0004: Read count invalid (> 62 bytes)
- *         0x0005: The SPI bridge is disabled.
- *         0x8000: Unknown error mask
- *             The bottom 15 bits will contain the bottom 15 bits from the EC
- *             error code.
- *
- *     read payload: up to 62 bytes of data read from SPI, length will match
- *                   requested read count
- */
-
-enum usb_spi_error {
-	USB_SPI_SUCCESS             = 0x0000,
-	USB_SPI_TIMEOUT             = 0x0001,
-	USB_SPI_BUSY                = 0x0002,
-	USB_SPI_WRITE_COUNT_INVALID = 0x0003,
-	USB_SPI_READ_COUNT_INVALID  = 0x0004,
-	USB_SPI_DISABLED            = 0x0005,
-	USB_SPI_UNKNOWN_ERROR       = 0x8000,
-};
-
-enum usb_spi_request {
-	USB_SPI_REQ_ENABLE          = 0x0000,
-	USB_SPI_REQ_DISABLE         = 0x0001,
-	USB_SPI_REQ_ENABLE_AP       = 0x0002,
-	USB_SPI_REQ_ENABLE_EC       = 0x0003,
-	USB_SPI_REQ_ENABLE_H1       = 0x0004,
-	USB_SPI_REQ_RESET           = 0x0005,
-	USB_SPI_REQ_BOOT_CFG        = 0x0006,
-	USB_SPI_REQ_SOCKET          = 0x0007,
-	USB_SPI_REQ_SIGNING_START   = 0x0008,
-	USB_SPI_REQ_SIGNING_SIGN    = 0x0009,
-};
-
-/* USB SPI device bitmasks */
-enum usb_spi {
-	USB_SPI_DISABLE = 0,
-	USB_SPI_AP = BIT(0),
-	USB_SPI_EC = BIT(1),
-	USB_SPI_H1 = BIT(2),
-	USB_SPI_ALL = USB_SPI_AP | USB_SPI_EC | USB_SPI_H1
-};
-
-
-#define USB_SPI_MAX_WRITE_COUNT 62
-#define USB_SPI_MAX_READ_COUNT  62
-
-BUILD_ASSERT(USB_MAX_PACKET_SIZE == (1 + 1 + USB_SPI_MAX_WRITE_COUNT));
-BUILD_ASSERT(USB_MAX_PACKET_SIZE == (2 + USB_SPI_MAX_READ_COUNT));
-
-struct usb_spi_state {
-	/*
-	 * The SPI bridge must be enabled both locally and by the host to allow
-	 * access to the SPI device.  The enabled_host flag is set and cleared
-	 * by sending USB_SPI_REQ_ENABLE_EC, USB_SPI_REQ_ENABLE_HOST, and
-	 * USB_SPI_REQ_DISABLE to the device control endpoint.  The
-	 * enabled_device flag is set by calling usb_spi_enable.
-	 */
-	int enabled_host;
-	int enabled_device;
-
-	/*
-	 * The current enabled state.  This is only updated in the deferred
-	 * callback.  Whenever either of the host or device specific enable
-	 * flags is changed the deferred callback is queued, and it will check
-	 * their combined state against this flag.  If the combined state is
-	 * different, then one of usb_spi_board_enable or usb_spi_board_disable
-	 * is called and this flag is updated.  This ensures that the board
-	 * specific state update routines are only called from the deferred
-	 * callback.
-	 */
-	int enabled;
-};
-
-/*
- * Compile time Per-USB gpio configuration stored in flash.  Instances of this
- * structure are provided by the user of the USB gpio.  This structure binds
- * together all information required to operate a USB gpio.
- */
-struct usb_spi_config {
-	/*
-	 * In RAM state of the USB SPI bridge.
-	 */
-	struct usb_spi_state *state;
-
-	/*
-	 * Interface and endpoint indices.
-	 */
-	int interface;
-	int endpoint;
-
-	/*
-	 * Deferred function to call to handle SPI request.
-	 */
-	const struct deferred_data *deferred;
-
-
-
-	/*
-	 * Pointer to tx and rx queues and bounce buffer.
-	 */
-	uint8_t *buffer;
-	struct consumer const consumer;
-	struct queue const *tx_queue;
-};
-
-extern struct consumer_ops const usb_spi_consumer_ops;
-
-/*
- * Convenience macro for defining a USB SPI bridge driver.
- *
- * NAME is used to construct the names of the trampoline functions and the
- * usb_spi_config struct, the latter is just called NAME.
- *
- * INTERFACE is the index of the USB interface to associate with this
- * SPI driver.
- *
- * ENDPOINT is the index of the USB bulk endpoint used for receiving and
- * transmitting bytes.
- *
- * FLAGS is unused right now, but add to definition for consistency
- */
-
-#define USB_SPI_CONFIG(NAME,						\
-		       INTERFACE,					\
-		       ENDPOINT,					\
-		       FLAGS)						\
-									\
-	static uint8_t CONCAT2(NAME, _buffer_)[USB_MAX_PACKET_SIZE];	\
-	static void CONCAT2(NAME, _deferred_)(void);			\
-	DECLARE_DEFERRED(CONCAT2(NAME, _deferred_));			\
-	static struct queue const CONCAT2(NAME, _to_usb_);		\
-	static struct queue const CONCAT3(usb_to_, NAME, _);		\
-	USB_STREAM_CONFIG_FULL(CONCAT2(NAME, _usb_),			\
-			       INTERFACE,				\
-			       USB_CLASS_VENDOR_SPEC,			\
-			       USB_SUBCLASS_GOOGLE_SPI,			\
-			       USB_PROTOCOL_GOOGLE_SPI,			\
-			       USB_STR_SPI_NAME,			\
-			       ENDPOINT,				\
-			       USB_MAX_PACKET_SIZE,			\
-			       USB_MAX_PACKET_SIZE,			\
-			       CONCAT3(usb_to_, NAME, _),		\
-			       CONCAT2(NAME, _to_usb_))			\
-	static struct usb_spi_state CONCAT2(NAME, _state_);		\
-	struct usb_spi_config const NAME = {				\
-		.state     = &CONCAT2(NAME, _state_),			\
-		.interface = INTERFACE,					\
-		.endpoint  = ENDPOINT,					\
-		.deferred  = &CONCAT2(NAME, _deferred__data),		\
-		.buffer    = CONCAT2(NAME, _buffer_),			\
-		.consumer  = {						\
-			.queue = &CONCAT3(usb_to_, NAME, _),		\
-			.ops   = &usb_spi_consumer_ops,			\
-		},							\
-		.tx_queue = &CONCAT2(NAME, _to_usb_),			\
-	};								\
-	static struct queue const CONCAT2(NAME, _to_usb_) =		\
-		QUEUE_DIRECT(USB_MAX_PACKET_SIZE, uint8_t,		\
-		null_producer, CONCAT2(NAME, _usb_).consumer);		\
-	static struct queue const CONCAT3(usb_to_, NAME, _) =		\
-		QUEUE_DIRECT(USB_MAX_PACKET_SIZE, uint8_t,		\
-		CONCAT2(NAME, _usb_).producer, NAME.consumer);		\
-	static int CONCAT2(NAME, _interface_)				\
-		(struct usb_setup_packet *req)				\
-	{								\
-		return usb_spi_interface(&NAME, req);			\
-	}								\
-	USB_DECLARE_IFACE(INTERFACE, CONCAT2(NAME, _interface_));	\
-	static void CONCAT2(NAME, _deferred_)(void)			\
-	{								\
-		usb_spi_deferred(&NAME);				\
-	}
-
-/*
- * Handle SPI request in a deferred callback.
- */
-void usb_spi_deferred(struct usb_spi_config const *config);
-
-/*
- * Set the enable state for the USB-SPI bridge.
- *
- * The bridge must be enabled from both the host and device side
- * before the SPI bus is usable.  This allows the bridge to be
- * available for host tools to use without forcing the device to
- * disconnect or disable whatever else might be using the SPI bus.
- */
-void usb_spi_enable(struct usb_spi_config const *config, int enabled);
-
-/*
- * This is used by the trampoline function defined above  interpret the USB
- * endpoint events with the generic USB GPIO driver.
- */
-int usb_spi_interface(struct usb_spi_config const *config,
-		      struct usb_setup_packet *req);
-
-/*
- * These functions should be implemented by the board to provide any board
- * specific operations required to enable or disable access to the SPI device.
- * usb_spi_board_enable should return EC_SUCCESS on success or an error
- * otherwise.
- */
-int usb_spi_board_enable(struct usb_spi_config const *config);
-void usb_spi_board_disable(struct usb_spi_config const *config);
-
-#endif /* __CROS_EC_USB_SPI_H */
diff --git a/chip/g/usb_upgrade.c b/chip/g/usb_upgrade.c
deleted file mode 100644
index d6fdf80488..0000000000
--- a/chip/g/usb_upgrade.c
+++ /dev/null
@@ -1,426 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "byteorder.h"
-#include "common.h"
-#include "console.h"
-#include "consumer.h"
-#include "extension.h"
-#include "queue_policies.h"
-#include "shared_mem.h"
-#include "system.h"
-#include "upgrade_fw.h"
-#include "usb-stream.h"
-
-#define CPRINTS(format, args...) cprints(CC_USB, format, ## args)
-
-/*
- * This file is an adaptation layer between the USB interface and the firmware
- * update engine. The engine expects to receive long blocks of data, 1K or so
- * in size, prepended by the offset where the data needs to be programmed into
- * the flash and a 4 byte integrity check value.
- *
- * The USB transfer, on the other hand, operates on much shorter chunks of
- * data, typically 64 bytes in this case. This module reassembles firmware
- * programming blocks from the USB chunks, and invokes the programmer passing
- * it the full block.
- *
- * The programmer reports results by putting the return value into the same
- * buffer where the block was passed in. This wrapper retrieves the
- * programmer's return value, and sends it back to the host. The return value
- * is usually one byte in size, the only exception is the connection
- * establishment phase where the return value is 16 bytes in size.
- *
- * In the end of the successful image transfer and programming, the host sends
- * the reset command, and the device reboots itself.
- */
-
-struct consumer const upgrade_consumer;
-struct usb_stream_config const usb_upgrade;
-
-static struct queue const upgrade_to_usb = QUEUE_DIRECT(64, uint8_t,
-						     null_producer,
-						     usb_upgrade.consumer);
-static struct queue const usb_to_upgrade = QUEUE_DIRECT(64, uint8_t,
-						     usb_upgrade.producer,
-						     upgrade_consumer);
-
-USB_STREAM_CONFIG_FULL(usb_upgrade,
-		       USB_IFACE_UPGRADE,
-		       USB_CLASS_VENDOR_SPEC,
-		       USB_SUBCLASS_GOOGLE_CR50,
-		       USB_PROTOCOL_GOOGLE_CR50_NON_HC_FW_UPDATE,
-		       USB_STR_UPGRADE_NAME,
-		       USB_EP_UPGRADE,
-		       USB_MAX_PACKET_SIZE,
-		       USB_MAX_PACKET_SIZE,
-		       usb_to_upgrade,
-		       upgrade_to_usb)
-
-
-/* The receiver can be in one of the states below. */
-enum rx_state {
-	rx_idle,	   /* Nothing happened yet. */
-	rx_inside_block,   /* Assembling a block to pass to the programmer. */
-	rx_outside_block,  /* Waiting for the next block to start or for the
-			      reset command. */
-};
-
-enum rx_state rx_state_ = rx_idle;
-static uint8_t *block_buffer;
-static uint32_t block_size;
-static uint32_t block_index;
-
-/*
- * Verify that the contents of the USB rx queue is a valid transfer start
- * message from host, and if so - save its contents in the passed in
- * update_frame_header structure.
- */
-static int valid_transfer_start(struct consumer const *consumer, size_t count,
-				struct update_frame_header *pupfr)
-{
-	int i;
-
-	/*
-	 * Let's just make sure we drain the queue no matter what the contents
-	 * are. This way they won't be in the way during next callback, even
-	 * if these contents are not what's expected.
-	 */
-	i = count;
-	while (i > 0) {
-		QUEUE_REMOVE_UNITS(consumer->queue, pupfr,
-				   MIN(i, sizeof(*pupfr)));
-		i -= sizeof(*pupfr);
-	}
-
-	if (count != sizeof(struct update_frame_header)) {
-		CPRINTS("FW update: wrong first block, size %d", count);
-		return 0;
-	}
-
-	/* In the first block the payload (pupfr->cmd) must be all zeros. */
-	for (i = 0; i < sizeof(pupfr->cmd); i++)
-		if (((uint8_t *)&pupfr->cmd)[i])
-			return 0;
-	return 1;
-}
-
-static int try_vendor_command(struct consumer const *consumer, size_t count)
-{
-	struct update_frame_header ufh;
-	struct update_frame_header *cmd_buffer;
-	uint16_t *subcommand;
-	size_t request_size;
-	/*
-	 * Should be enough for any vendor command/response. We'll generate an
-	 * error if it is not.
-	 */
-	uint8_t subcommand_body[32];
-
-	if (count < sizeof(ufh))
-		return 0;	/* Too short to be a valid vendor command. */
-
-	/*
-	 * Let's copy off the queue the upgrade frame header, to see if this
-	 * is a channeled vendor command.
-	 */
-	queue_peek_units(consumer->queue, &ufh, 0, sizeof(ufh));
-	if (be32toh(ufh.cmd.block_base) != CONFIG_EXTENSION_COMMAND)
-		return 0;
-
-	if (be32toh(ufh.block_size) != count) {
-		CPRINTS("%s: problem: block size and count mismatch (%d != %d)",
-			__func__, be32toh(ufh.block_size), count);
-		return 0;
-	}
-
-	if (shared_mem_acquire(count, (char **)&cmd_buffer)
-	    != EC_SUCCESS) {
-		CPRINTS("%s: problem: failed to allocate block of %d",
-			__func__, count);
-		return 0;
-	}
-
-	/* Get the entire command, don't remove it from the queue just yet. */
-	queue_peek_units(consumer->queue, cmd_buffer, 0, count);
-
-	/* Looks like this is a vendor command, let's verify it. */
-	if (!usb_pdu_valid(&cmd_buffer->cmd,
-			  count - offsetof(struct update_frame_header, cmd))) {
-		/* Didn't verify */
-		shared_mem_release(cmd_buffer);
-		return 0;
-	}
-
-	/* Looks good; remove from the queue and process it. */
-	queue_advance_head(consumer->queue, count);
-
-	subcommand = (uint16_t *)(cmd_buffer + 1);
-	request_size = count - sizeof(struct update_frame_header) -
-		       sizeof(*subcommand);
-
-	if (request_size > sizeof(subcommand_body)) {
-		const uint8_t err = VENDOR_RC_REQUEST_TOO_BIG;
-
-		CPRINTS("%s: payload too big (%d)", __func__, request_size);
-		QUEUE_ADD_UNITS(&upgrade_to_usb, &err, 1);
-	} else {
-		uint32_t rv;
-		struct vendor_cmd_params p = {
-			.code = be16toh(*subcommand),
-			.buffer = subcommand_body,
-			.in_size = request_size,
-			/*
-			 * The return code normally put into the TPM response
-			 * header is not present in the USB response. Vendor
-			 * command return code is guaranteed to fit in a
-			 * byte. Let's keep space for it in the front of the
-			 * buffer.
-			 */
-			.out_size = sizeof(subcommand_body) - 1,
-			.flags = VENDOR_CMD_FROM_USB
-		};
-		memcpy(subcommand_body, subcommand + 1, request_size);
-		rv = extension_route_command(&p);
-		/*
-		 * Copy actual response, if any, one byte up, to free room for
-		 * the return code.
-		 */
-		if (p.out_size)
-			memmove(subcommand_body + 1, subcommand_body,
-				p.out_size);
-		subcommand_body[0] = rv;  /* We care about LSB only. */
-
-		QUEUE_ADD_UNITS(&upgrade_to_usb, subcommand_body,
-				p.out_size + 1);
-	}
-
-	shared_mem_release(cmd_buffer);
-	return 1;
-}
-
-/*
- * When was last time a USB callback was called, in microseconds, free running
- * timer.
- */
-static uint64_t prev_activity_timestamp;
-
-/*
- * A flag indicating that at least one valid PDU containing flash update block
- * has been received in the current transfer session.
- */
-static uint8_t  data_was_transferred;
-
-/* Called to deal with data from the host */
-static void upgrade_out_handler(struct consumer const *consumer, size_t count)
-{
-	struct update_frame_header upfr;
-	size_t resp_size;
-	uint8_t resp_value;
-	uint64_t delta_time;
-
-	/* How much time since the previous USB callback? */
-	delta_time = get_time().val - prev_activity_timestamp;
-	prev_activity_timestamp += delta_time;
-
-	/* If timeout exceeds 5 seconds - let's start over. */
-	if ((delta_time > 5000000) && (rx_state_ != rx_idle)) {
-		if (block_buffer) {
-			/*
-			 * Previous transfer could have been aborted mid
-			 * block.
-			 */
-			shared_mem_release(block_buffer);
-			block_buffer = NULL;
-		}
-		rx_state_ = rx_idle;
-		CPRINTS("FW update: recovering after timeout");
-	}
-
-	if (rx_state_ == rx_idle) {
-		/*
-		 * The payload must be an update initiating PDU.
-		 *
-		 * The size of the response returned in the same buffer will
-		 * exceed the received frame size; Let's make sure there is
-		 * enough room for the response in the buffer.
-		 */
-		union {
-			struct update_frame_header upfr;
-			struct {
-				uint32_t unused;
-				struct first_response_pdu startup_resp;
-			};
-		} u;
-
-		/* Check is this is a channeled TPM extension command. */
-		if (try_vendor_command(consumer, count))
-			return;
-
-		if (!valid_transfer_start(consumer, count, &u.upfr)) {
-			/*
-			 * Something is wrong, this payload is not a valid
-			 * update start PDU. Let'w indicate this by returning
-			 * a single byte error code.
-			 */
-			resp_value = UPGRADE_GEN_ERROR;
-			CPRINTS("%s:%d", __FILE__, __LINE__);
-			QUEUE_ADD_UNITS(&upgrade_to_usb, &resp_value, 1);
-			return;
-		}
-
-		CPRINTS("FW update: starting...");
-		fw_upgrade_command_handler(&u.upfr.cmd, count -
-					   offsetof(struct update_frame_header,
-						    cmd),
-					   &resp_size);
-
-		if (!u.startup_resp.return_value) {
-			rx_state_ = rx_outside_block;  /* We're in business. */
-			data_was_transferred = 0;   /* No data received yet. */
-		}
-
-		/* Let the host know what upgrader had to say. */
-		QUEUE_ADD_UNITS(&upgrade_to_usb, &u.startup_resp, resp_size);
-		return;
-	}
-
-	if (rx_state_ == rx_outside_block) {
-		/*
-		 * Expecting to receive the beginning of the block or the
-		 * reset command if all data blocks have been processed.
-		 */
-		if (count == 4) {
-			uint32_t command;
-
-			QUEUE_REMOVE_UNITS(consumer->queue, &command,
-					   sizeof(command));
-			command = be32toh(command);
-			if (command == UPGRADE_DONE) {
-				CPRINTS("FW update: done");
-
-				if (data_was_transferred) {
-					fw_upgrade_complete();
-					data_was_transferred = 0;
-				}
-
-				resp_value = 0;
-				QUEUE_ADD_UNITS(&upgrade_to_usb,
-						&resp_value, 1);
-				rx_state_ = rx_idle;
-				return;
-			}
-		}
-
-		/*
-		 * At this point we expect a block start message. It is
-		 * sizeof(upfr) bytes in size, but is not the transfer start
-		 * message, which also is of that size AND has the command
-		 * field of all zeros.
-		 */
-		if (valid_transfer_start(consumer, count, &upfr) ||
-		    (count != sizeof(upfr))) {
-			/*
-			 * Instead of a block start message we received either
-			 * a transfer start message or a chunk. We must have
-			 * gotten out of sync with the host.
-			 */
-			resp_value = UPGRADE_GEN_ERROR;
-			CPRINTS("%s:%d", __FILE__, __LINE__);
-			QUEUE_ADD_UNITS(&upgrade_to_usb, &resp_value, 1);
-			return;
-		}
-
-		/* Let's allocate a large enough buffer. */
-		block_size = be32toh(upfr.block_size) -
-			offsetof(struct update_frame_header, cmd);
-		if (shared_mem_acquire(block_size, (char **)&block_buffer)
-		    != EC_SUCCESS) {
-			CPRINTS("FW update: error: failed to alloc %d bytes.",
-				block_size);
-			resp_value = UPGRADE_MALLOC_ERROR;
-			QUEUE_ADD_UNITS(&upgrade_to_usb, &resp_value, 1);
-			return;
-		}
-
-		/*
-		 * Copy the rest of the message into the block buffer to pass
-		 * to the upgrader.
-		 */
-		block_index = sizeof(upfr) -
-			offsetof(struct update_frame_header, cmd);
-		memcpy(block_buffer, &upfr.cmd, block_index);
-		block_size -= block_index;
-		rx_state_ = rx_inside_block;
-		return;
-	}
-
-	/* Must be inside block. */
-	QUEUE_REMOVE_UNITS(consumer->queue, block_buffer + block_index, count);
-	block_index += count;
-	block_size -= count;
-
-	if (block_size) {
-		if (count == sizeof(upfr)) {
-			/*
-			 * A block header size instead of chunk size message
-			 * has been received. There must have been some packet
-			 * loss and the host is restarting this block.
-			 *
-			 * Let's copy its contents into the header structure.
-			 */
-			memcpy(&upfr, block_buffer + block_index - count,
-			       count);
-
-
-			/* And re-allocate a large enough buffer. */
-			shared_mem_release(block_buffer);
-			block_size = be32toh(upfr.block_size) -
-				offsetof(struct update_frame_header, cmd);
-			if (shared_mem_acquire(block_size,
-					       (char **)&block_buffer)
-			    != EC_SUCCESS) {
-				/* TODO:(vbendeb) report out of memory here. */
-				CPRINTS("FW update: error: failed to alloc "
-					"%d bytes.", block_size);
-				return;
-			}
-
-			/*
-			 * Copy the rest of the message into the block buffer
-			 * to pass to the upgrader.
-			 */
-			block_index = sizeof(upfr) -
-				offsetof(struct update_frame_header, cmd);
-			memcpy(block_buffer, &upfr.cmd, block_index);
-			block_size -= block_index;
-		}
-		return;	/* More to come. */
-	}
-
-	/*
-	 * Ok, the entire block has been received and reassembled, pass it to
-	 * the updater for verification and programming.
-	 */
-	fw_upgrade_command_handler(block_buffer, block_index, &resp_size);
-
-	/*
-	 * There was at least an attempt to program the flash, set the
-	 * flag.
-	 */
-	data_was_transferred = 1;
-	resp_value = block_buffer[0];
-	QUEUE_ADD_UNITS(&upgrade_to_usb, &resp_value, sizeof(resp_value));
-	rx_state_ = rx_outside_block;
-	shared_mem_release(block_buffer);
-	block_buffer = NULL;
-}
-
-struct consumer const upgrade_consumer = {
-	.queue = &usb_to_upgrade,
-	.ops   = &((struct consumer_ops const) {
-		.written = upgrade_out_handler,
-	}),
-};
diff --git a/chip/g/watchdog.c b/chip/g/watchdog.c
deleted file mode 100644
index c5560fc0d7..0000000000
--- a/chip/g/watchdog.c
+++ /dev/null
@@ -1,112 +0,0 @@
-/* Copyright 2014 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Watchdog driver */
-
-#include "common.h"
-#include "ec_commands.h"
-#include "hooks.h"
-#include "registers.h"
-#include "task.h"
-#include "util.h"
-#include "system.h"
-#include "watchdog.h"
-
-/* magic value to unlock the watchdog registers */
-#define WATCHDOG_MAGIC_WORD  0x1ACCE551
-
-/* Watchdog expiration */
-#define WATCHDOG_PERIOD (CONFIG_WATCHDOG_PERIOD_MS * (PCLK_FREQ / 1000))
-
-void __attribute__((used)) trace_and_reset(uint32_t excep_lr, uint32_t excep_sp)
-{
-	watchdog_trace(excep_lr, excep_sp);
-	system_reset(EC_RESET_FLAG_WATCHDOG);
-}
-
-/* Warning interrupt at the middle of the watchdog period */
-void IRQ_HANDLER(GC_IRQNUM_WATCHDOG0_WDOGINT)(void) __attribute__((naked));
-void IRQ_HANDLER(GC_IRQNUM_WATCHDOG0_WDOGINT)(void)
-{
-	/* Naked call so we can extract raw LR and SP */
-	asm volatile("mov r0, lr\n"
-		     "mov r1, sp\n"
-		     /* Must push registers in pairs to keep 64-bit aligned
-		      * stack for ARM EABI.  This also conveniently saves
-		      * R0=LR so we can pass it to task_resched_if_needed. */
-		     "push {r0, lr}\n"
-		     /* We've lowered our runlevel, so just rebooting the ARM
-		      * core doesn't work. */
-		     "bl trace_and_reset\n"
-		     /* Do NOT reset the watchdog interrupt here; it will
-		      * be done in watchdog_reload(), or reset will be
-		      * triggered if we don't call that by the next watchdog
-		      * period.  Instead, de-activate the interrupt in the
-		      * NVIC, so the watchdog trace will only be printed
-		      * once.
-		      */
-		     "mov r0, %[irq]\n"
-		     "bl task_disable_irq\n"
-		     "pop {r0, lr}\n"
-		     "b task_resched_if_needed\n"
-		     : : [irq] "i" (GC_IRQNUM_WATCHDOG0_WDOGINT));
-}
-const struct irq_priority __keep IRQ_PRIORITY(GC_IRQNUM_WATCHDOG0_WDOGINT)
-	__attribute__((section(".rodata.irqprio")))
-		= {GC_IRQNUM_WATCHDOG0_WDOGINT, 0};
-	/* put the watchdog at the highest priority */
-
-void watchdog_reload(void)
-{
-	uint32_t status = GR_WATCHDOG_RIS;
-
-	/* Unlock watchdog registers */
-	GR_WATCHDOG_LOCK = WATCHDOG_MAGIC_WORD;
-
-	/* As we reboot only on the second timeout, if we have already reached
-	 * the first timeout we need to reset the interrupt bit. */
-	if (status) {
-		GR_WATCHDOG_ICR = status;
-		/* That doesn't seem to unpend the watchdog interrupt (even if
-		 * we do dummy writes to force the write to be committed), so
-		 * explicitly unpend the interrupt before re-enabling it. */
-		task_clear_pending_irq(GC_IRQNUM_WATCHDOG0_WDOGINT);
-		task_enable_irq(GC_IRQNUM_WATCHDOG0_WDOGINT);
-	}
-
-	/* Reload the watchdog counter */
-	GR_WATCHDOG_LOAD = WATCHDOG_PERIOD;
-
-	/* Re-lock watchdog registers */
-	GR_WATCHDOG_LOCK = 0xdeaddead;
-}
-DECLARE_HOOK(HOOK_TICK, watchdog_reload, HOOK_PRIO_DEFAULT);
-
-int watchdog_init(void)
-{
-	/* Unlock watchdog registers */
-	GR_WATCHDOG_LOCK = WATCHDOG_MAGIC_WORD;
-
-	/* Reload the watchdog counter */
-	GR_WATCHDOG_LOAD = WATCHDOG_PERIOD;
-
-	/* Reset after 2 time-out : activate both interrupt and reset. */
-	GR_WATCHDOG_CTL = 0x3;
-
-	/* Reset watchdog interrupt bits */
-	GR_WATCHDOG_ICR = GR_WATCHDOG_RIS;
-
-	/* Lock watchdog registers against unintended accesses */
-	GR_WATCHDOG_LOCK = 0xdeaddead;
-
-	/* Enable watchdog interrupt */
-	task_enable_irq(GC_IRQNUM_WATCHDOG0_WDOGINT);
-
-	/* Reboot hard if the watchdog fires or the processor locks up */
-	GWRITE_FIELD(GLOBALSEC, ALERT_CONTROL, WATCHDOG_RESET_SHUTDOWN_EN, 1);
-	GWRITE_FIELD(GLOBALSEC, ALERT_CONTROL, PROC_LOCKUP_SHUTDOWN_EN, 1);
-
-	return EC_SUCCESS;
-}
diff --git a/common/build.mk b/common/build.mk
index 3021bb14c8..a931b10890 100644
--- a/common/build.mk
+++ b/common/build.mk
@@ -114,7 +114,6 @@ common-$(CONFIG_PSTORE)+=pstore_commands.o
 common-$(CONFIG_PWM)+=pwm.o
 common-$(CONFIG_PWM_KBLIGHT)+=pwm_kblight.o
 common-$(CONFIG_KEYBOARD_BACKLIGHT)+=keyboard_backlight.o
-common-$(CONFIG_RMA_AUTH)+=rma_auth.o
 common-$(CONFIG_RSA)+=rsa.o
 common-$(CONFIG_ROLLBACK)+=rollback.o
 common-$(CONFIG_RWSIG)+=rwsig.o vboot/common.o
diff --git a/common/rma_auth.c b/common/rma_auth.c
deleted file mode 100644
index 24c30bbe52..0000000000
--- a/common/rma_auth.c
+++ /dev/null
@@ -1,457 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* RMA authorization challenge-response */
-
-#include "common.h"
-#include "base32.h"
-#include "byteorder.h"
-#include "ccd_config.h"
-#include "chip/g/board_id.h"
-#include "console.h"
-#ifdef CONFIG_CURVE25519
-#include "curve25519.h"
-#endif
-#include "extension.h"
-#include "hooks.h"
-#include "rma_auth.h"
-#include "shared_mem.h"
-#include "system.h"
-#include "timer.h"
-#include "tpm_registers.h"
-#include "tpm_vendor_cmds.h"
-#ifdef CONFIG_RMA_AUTH_USE_P256
-#include "trng.h"
-#endif
-#include "util.h"
-
-#ifndef TEST_BUILD
-#include "cryptoc/util.h"
-#include "rma_key_from_blob.h"
-#else
-/* Cryptoc library is not available to the test layer. */
-#define always_memset memset
-#endif
-
-#ifdef CONFIG_DCRYPTO
-#include "dcrypto.h"
-#else
-#include "sha256.h"
-#endif
-
-#define CPRINTF(format, args...) cprintf(CC_EXTENSION, format, ## args)
-
-/* Minimum time since system boot or last challenge before making a new one */
-#define CHALLENGE_INTERVAL (10 * SECOND)
-
-/* Number of tries to properly enter auth code */
-#define MAX_AUTHCODE_TRIES 3
-
-#ifdef CONFIG_RMA_AUTH_USE_P256
-#define RMA_SERVER_PUB_KEY_SZ 65
-#else
-#define RMA_SERVER_PUB_KEY_SZ 32
-#endif
-
-/* Server public key and key ID */
-static const struct  {
-	union {
-		uint8_t raw_blob[RMA_SERVER_PUB_KEY_SZ + 1];
-		struct {
-			uint8_t server_pub_key[RMA_SERVER_PUB_KEY_SZ];
-			volatile uint8_t server_key_id;
-		};
-	};
-} __packed rma_key_blob = {
-	.raw_blob = RMA_KEY_BLOB
-};
-
-BUILD_ASSERT(sizeof(rma_key_blob) == (RMA_SERVER_PUB_KEY_SZ + 1));
-
-static char challenge[RMA_CHALLENGE_BUF_SIZE];
-static char authcode[RMA_AUTHCODE_BUF_SIZE];
-static int tries_left;
-static uint64_t last_challenge_time;
-
-static void get_hmac_sha256(void *hmac_out, const uint8_t *secret,
-			    size_t secret_size, const void *ch_ptr,
-			    size_t ch_size)
-{
-#ifdef CONFIG_DCRYPTO
-	LITE_HMAC_CTX hmac;
-
-	DCRYPTO_HMAC_SHA256_init(&hmac, secret, secret_size);
-	HASH_update(&hmac.hash, ch_ptr, ch_size);
-	memcpy(hmac_out, DCRYPTO_HMAC_final(&hmac), 32);
-#else
-	hmac_SHA256(hmac_out, secret, secret_size, ch_ptr, ch_size);
-#endif
-}
-
-static void hash_buffer(void *dest, size_t dest_size,
-			const void *buffer, size_t buf_size)
-{
-	/* We know that the destination is no larger than 32 bytes. */
-	uint8_t temp[32];
-
-	get_hmac_sha256(temp, buffer, buf_size, buffer, buf_size);
-
-	/* Or should we do XOR of the temp modulo dest size? */
-	memcpy(dest, temp, dest_size);
-}
-
-#ifdef CONFIG_RMA_AUTH_USE_P256
-/*
- * Generate a p256 key pair, such that Y coordinate component of the public
- * key is an odd value. Use the X component value as the compressed public key
- * to be sent to the server. Multiply server public key by our private key to
- * generate the shared secret.
- *
- * @pub_key - array to return 32 bytes of the X coordinate public key
- *	      component.
- * @secet - array to return the X coordinate of the product of the server
- *            public key multiplied by our private key.
- */
-static void p256_get_pub_key_and_secret(uint8_t pub_key[P256_NBYTES],
-					uint8_t secret[P256_NBYTES])
-{
-	uint8_t buf[SHA256_DIGEST_SIZE];
-	p256_int d;
-	p256_int pk_x;
-	p256_int pk_y;
-
-	/* Get some noise for private key. */
-	rand_bytes(buf, sizeof(buf));
-
-	/*
-	 * By convention with the RMA server the Y coordinate of the Cr50
-	 * public key component is required to be an odd value. Keep trying
-	 * until the genreated bublic key has the compliant Y coordinate.
-	 */
-	while (1) {
-		HASH_CTX sha;
-
-		if (DCRYPTO_p256_key_from_bytes(&pk_x, &pk_y, &d, buf)) {
-
-			/* Is Y coordinate an odd value? */
-			if (p256_is_odd(&pk_y))
-				break; /* Yes it is, got a good key. */
-		}
-
-		/* Did not succeed, rehash the private key and try again. */
-		DCRYPTO_SHA256_init(&sha, 0);
-		HASH_update(&sha, buf, sizeof(buf));
-		memcpy(buf, HASH_final(&sha), sizeof(buf));
-	}
-
-	/* X coordinate is passed to the server as the public key. */
-	p256_to_bin(&pk_x, pub_key);
-
-	/*
-	 * Now let's calculate the secret as a the server pub key multiplied
-	 * by our private key.
-	 */
-	p256_from_bin(rma_key_blob.raw_blob + 1, &pk_x);
-	p256_from_bin(rma_key_blob.raw_blob + 1 + P256_NBYTES, &pk_y);
-
-	/* Use input space for storing multiplication results. */
-	DCRYPTO_p256_point_mul(&pk_x, &pk_y, &d, &pk_x, &pk_y);
-
-	/* X value is the seed for the shared secret. */
-	p256_to_bin(&pk_x, secret);
-
-	/* Wipe out the private key just in case. */
-	always_memset(&d, 0, sizeof(d));
-}
-#endif
-
-void get_rma_device_id(uint8_t rma_device_id[RMA_DEVICE_ID_SIZE])
-{
-	uint8_t *chip_unique_id;
-	int chip_unique_id_size = system_get_chip_unique_id(&chip_unique_id);
-
-	if (chip_unique_id_size < 0)
-		chip_unique_id_size = 0;
-	/* Smaller unique chip IDs will fill rma_device_id only partially. */
-	if (chip_unique_id_size <= RMA_DEVICE_ID_SIZE) {
-		/* The size matches, let's just copy it as is. */
-		memcpy(rma_device_id, chip_unique_id, chip_unique_id_size);
-		if (chip_unique_id_size < RMA_DEVICE_ID_SIZE) {
-			memset(rma_device_id + chip_unique_id_size, 0,
-				RMA_DEVICE_ID_SIZE - chip_unique_id_size);
-		}
-	} else {
-		/*
-		 * The unique chip ID size exceeds space allotted in
-		 * rma_challenge:device_id, let's use first few bytes of
-		 * its hash.
-		 */
-		hash_buffer(rma_device_id, RMA_DEVICE_ID_SIZE,
-			    chip_unique_id, chip_unique_id_size);
-	}
-}
-
-/**
- * Create a new RMA challenge/response
- *
- * @return EC_SUCCESS, EC_ERROR_TIMEOUT if too soon since the last challenge,
- * or other non-zero error code.
- */
-int rma_create_challenge(void)
-{
-	uint8_t temp[32];	/* Private key or HMAC */
-	uint8_t secret[32];
-	struct rma_challenge c;
-	struct board_id bid;
-	uint8_t *cptr = (uint8_t *)&c;
-	uint64_t t;
-
-	/* Clear the current challenge and authcode, if any */
-	memset(challenge, 0, sizeof(challenge));
-	memset(authcode, 0, sizeof(authcode));
-
-	/* Rate limit challenges */
-	t = get_time().val;
-	if (t - last_challenge_time < CHALLENGE_INTERVAL)
-		return EC_ERROR_TIMEOUT;
-	last_challenge_time = t;
-
-	memset(&c, 0, sizeof(c));
-	c.version_key_id = RMA_CHALLENGE_VKID_BYTE(
-	    RMA_CHALLENGE_VERSION, rma_key_blob.server_key_id);
-
-	if (read_board_id(&bid))
-		return EC_ERROR_UNKNOWN;
-
-	memcpy(c.board_id, &bid.type, sizeof(c.board_id));
-	get_rma_device_id(c.device_id);
-
-	/* Calculate a new ephemeral key pair and the shared secret. */
-#ifdef CONFIG_RMA_AUTH_USE_P256
-	p256_get_pub_key_and_secret(c.device_pub_key, secret);
-#endif
-#ifdef CONFIG_CURVE25519
-	X25519_keypair(c.device_pub_key, temp);
-	X25519(secret, temp, rma_key_blob.server_pub_key);
-#endif
-	/* Encode the challenge */
-	if (base32_encode(challenge, sizeof(challenge), cptr, 8 * sizeof(c), 9))
-		return EC_ERROR_UNKNOWN;
-
-
-	/*
-	 * Auth code is a truncated HMAC of the ephemeral public key, BoardID,
-	 * and DeviceID.  Those are all in the right order in the challenge
-	 * struct, after the version/key id byte.
-	 */
-	get_hmac_sha256(temp, secret, sizeof(secret), cptr + 1, sizeof(c) - 1);
-	if (base32_encode(authcode, sizeof(authcode), temp,
-			  RMA_AUTHCODE_CHARS * 5, 0))
-		return EC_ERROR_UNKNOWN;
-
-	tries_left = MAX_AUTHCODE_TRIES;
-	return EC_SUCCESS;
-}
-
-const char *rma_get_challenge(void)
-{
-	return challenge;
-}
-
-int rma_try_authcode(const char *code)
-{
-	int rv = EC_ERROR_INVAL;
-
-	/* Fail if out of tries */
-	if (!tries_left)
-		return EC_ERROR_ACCESS_DENIED;
-
-	/* Fail if auth code has not been calculated yet. */
-	if (!*authcode)
-		return EC_ERROR_ACCESS_DENIED;
-
-	if (safe_memcmp(authcode, code, RMA_AUTHCODE_CHARS)) {
-		/* Mismatch */
-		tries_left--;
-	} else {
-		rv = EC_SUCCESS;
-		tries_left = 0;
-	}
-
-	/* Clear challenge and response if out of tries */
-	if (!tries_left) {
-		memset(challenge, 0, sizeof(challenge));
-		memset(authcode, 0, sizeof(authcode));
-	}
-
-	return rv;
-}
-
-#ifndef TEST_BUILD
-/*
- * Trigger generating of the new challenge/authcode pair. If successful, store
- * the challenge in the vendor command response buffer and send it to the
- * sender. If not successful - return the error value to the sender.
- */
-static enum vendor_cmd_rc get_challenge(uint8_t *buf, size_t *buf_size)
-{
-	int rv;
-	size_t i;
-
-	if (*buf_size < sizeof(challenge)) {
-		*buf_size = 1;
-		buf[0] = VENDOR_RC_RESPONSE_TOO_BIG;
-		return buf[0];
-	}
-
-	rv = rma_create_challenge();
-	if (rv != EC_SUCCESS) {
-		*buf_size = 1;
-		buf[0] = rv;
-		return buf[0];
-	}
-
-	*buf_size = sizeof(challenge) - 1;
-	memcpy(buf, rma_get_challenge(), *buf_size);
-
-
-	CPRINTF("generated challenge:\n\n");
-	for (i = 0; i < *buf_size; i++)
-		CPRINTF("%c", ((uint8_t *)buf)[i]);
-	CPRINTF("\n\n");
-
-#ifdef CR50_DEV
-
-	CPRINTF("expected authcode: ");
-	for (i = 0; i < RMA_AUTHCODE_CHARS; i++)
-		CPRINTF("%c", authcode[i]);
-	CPRINTF("\n");
-#endif
-	return VENDOR_RC_SUCCESS;
-}
-/*
- * Compare response sent by the operator with the pre-compiled auth code.
- * Return error code or success depending on the comparison results.
- */
-static enum vendor_cmd_rc process_response(uint8_t *buf,
-					   size_t input_size,
-					   size_t *response_size)
-{
-	int rv;
-
-	*response_size = 1; /* Just in case there is an error. */
-
-	if (input_size != RMA_AUTHCODE_CHARS) {
-		CPRINTF("%s: authcode size %d\n",
-			__func__, input_size);
-		buf[0] = VENDOR_RC_BOGUS_ARGS;
-		return buf[0];
-	}
-
-	rv = rma_try_authcode(buf);
-
-	if (rv == EC_SUCCESS) {
-		CPRINTF("%s: success!\n", __func__);
-		*response_size = 0;
-		enable_ccd_factory_mode(0);
-		return VENDOR_RC_SUCCESS;
-	}
-
-	CPRINTF("%s: authcode mismatch\n", __func__);
-	buf[0] = VENDOR_RC_INTERNAL_ERROR;
-	return buf[0];
-}
-
-/*
- * Handle the VENDOR_CC_RMA_CHALLENGE_RESPONSE command. When received with
- * empty payload - this is a request to generate a new challenge, when
- * received with a payload, this is a request to check if the payload matches
- * the previously calculated auth code.
- */
-static enum vendor_cmd_rc rma_challenge_response(enum vendor_cmd_cc code,
-						 void *buf,
-						 size_t input_size,
-						 size_t *response_size)
-{
-	if (!input_size)
-		/*
-		 * This is a request for the challenge, get it and send it
-		 * back.
-		 */
-		return get_challenge(buf, response_size);
-
-	return process_response(buf, input_size, response_size);
-}
-DECLARE_VENDOR_COMMAND(VENDOR_CC_RMA_CHALLENGE_RESPONSE,
-		       rma_challenge_response);
-
-
-#define RMA_CMD_BUF_SIZE (sizeof(struct tpm_cmd_header) + \
-			  RMA_CHALLENGE_BUF_SIZE)
-static int rma_auth_cmd(int argc, char **argv)
-{
-	struct tpm_cmd_header *tpmh;
-	int rv;
-
-	if (argc > 2) {
-		ccprintf("Error: the only accepted parameter is"
-			 " the auth code to check\n");
-		return EC_ERROR_PARAM_COUNT;
-	}
-
-	rv = shared_mem_acquire(RMA_CMD_BUF_SIZE, (char **)&tpmh);
-	if (rv != EC_SUCCESS)
-		return rv;
-
-	/* Common fields of the RMA AUTH challenge/response vendor command. */
-	tpmh->tag = htobe16(0x8001); /* TPM_ST_NO_SESSIONS */
-	tpmh->command_code = htobe32(TPM_CC_VENDOR_BIT_MASK);
-	tpmh->subcommand_code = htobe16(VENDOR_CC_RMA_CHALLENGE_RESPONSE);
-
-	if (argc == 2) {
-		/*
-		 * The user entered a value, must be the auth code, build and
-		 * send vendor command to check it.
-		 */
-		const char *authcode = argv[1];
-
-		if (strlen(authcode) != RMA_AUTHCODE_CHARS) {
-			ccprintf("Wrong auth code size.\n");
-			return EC_ERROR_PARAM1;
-		}
-
-		tpmh->size = htobe32(sizeof(struct tpm_cmd_header) +
-				     RMA_AUTHCODE_CHARS);
-
-		memcpy(tpmh + 1, authcode, RMA_AUTHCODE_CHARS);
-
-		tpm_alt_extension(tpmh, RMA_CMD_BUF_SIZE);
-
-		if (tpmh->command_code) {
-			ccprintf("Auth code does not match.\n");
-			return EC_ERROR_PARAM1;
-		}
-		ccprintf("Auth code match, reboot might be coming!\n");
-		return EC_SUCCESS;
-	}
-
-	/* Prepare and send the request to get RMA auth challenge. */
-	tpmh->size = htobe32(sizeof(struct tpm_cmd_header));
-	tpm_alt_extension(tpmh, RMA_CMD_BUF_SIZE);
-
-	/* Return status in the command code field now. */
-	if (tpmh->command_code) {
-		ccprintf("RMA Auth error 0x%x\n", be32toh(tpmh->command_code));
-		rv = EC_ERROR_UNKNOWN;
-	}
-
-	shared_mem_release(tpmh);
-	return EC_SUCCESS;
-}
-
-DECLARE_SAFE_CONSOLE_COMMAND(rma_auth, rma_auth_cmd, NULL,
-			     "rma_auth [auth code] - "
-			"Generate RMA challenge or check auth code match\n");
-#endif
diff --git a/include/config.h b/include/config.h
index 8c9049bb3f..0bf37db722 100644
--- a/include/config.h
+++ b/include/config.h
@@ -736,8 +736,6 @@
 #undef CONFIG_CASE_CLOSED_DEBUG_V1
 /* Allow unsafe debugging functionality in V1 configuration */
 #undef CONFIG_CASE_CLOSED_DEBUG_V1_UNSAFE
-/* Enable ITE EC programming by CCD using the INA i2c interface. */
-#undef CONFIG_CCD_ITE_PROGRAMMING
 /* Loosen Open restrictions for prePVT devices */
 #undef CONFIG_CCD_OPEN_PREPVT
 
@@ -1434,13 +1432,6 @@
 #undef CONFIG_CRC8
 
 /*
- * When enabled, do not build RO image from the same set of files as the RW
- * image. Instead define a separate set of object files in the respective
- * build.mk files by adding the objects to the custom-ro_objs-y variable.
- */
-#undef CONFIG_CUSTOMIZED_RO
-
-/*
  * When enabled, build in support for software & hardware crypto;
  * only supported on CR50.
  *
@@ -1462,12 +1453,6 @@
 #undef CONFIG_DCRYPTO_RSA_SPEEDUP
 
 /*
- * When enabled, accelerate sha512 using the generic crypto engine;
- * only supported on CR50
- */
-#undef CONFIG_DCRYPTO_SHA512
-
-/*
  * When enabled build support for SHA-384/512, requires CONFIG_DCRYPTO.
  */
 #undef CONFIG_UPTO_SHA512
@@ -1478,11 +1463,6 @@
 #undef CONFIG_IGNORE_G_UPDATE_CHECKS
 
 /*
- * When enabled hardware alerts statistics provided via VendorCommand extension.
- */
-#undef CONFIG_ENABLE_H1_ALERTS
-
-/*
  * Enable console shell command 'alerts' that prints chip alerts statistics.
  */
 #undef CONFIG_ENABLE_H1_ALERTS_CONSOLE
@@ -1674,7 +1654,6 @@
 #undef CONFIG_FLASH_LOG_SPACE
 #undef CONFIG_FLASH_ERASED_VALUE32
 #undef CONFIG_FLASH_ERASE_SIZE
-#undef CONFIG_FLASH_ROW_SIZE
 /* Allow deferred (async) flash erase */
 #undef CONFIG_FLASH_DEFERRED_ERASE
 /* Flash must be selected for write/erase operations to succeed. */
@@ -3134,9 +3113,6 @@
 /* Enable rbox wakeup */
 #undef CONFIG_RBOX_WAKEUP
 
-/* Enable RDD peripheral */
-#undef CONFIG_RDD
-
 /* Support IR357x Link voltage regulator debugging / reprogramming */
 #undef CONFIG_REGULATOR_IR357X
 
@@ -3639,8 +3615,6 @@
 /*****************************************************************************/
 /* TPM-like configuration */
 
-/* Speak the TPM SPI Hardware Protocol on the SPI slave interface */
-#undef CONFIG_TPM_SPS
 /* Speak to the TPM 2.0 hardware protocol on the I2C slave interface */
 #undef CONFIG_TPM_I2CS
 
@@ -3671,9 +3645,6 @@
 /* Baud rate for UARTs */
 #define CONFIG_UART_BAUD_RATE 115200
 
-/* Allow bit banging of a UARTs pins and bypassing the UART block. */
-#undef CONFIG_UART_BITBANG
-
 /* UART index (number) for EC console */
 #undef CONFIG_UART_CONSOLE
 
@@ -4179,9 +4150,6 @@
 /* Support USB isochronous handler */
 #undef CONFIG_USB_ISOCHRONOUS
 
-/* Support USB blob handler. */
-#undef CONFIG_USB_BLOB
-
 /* Common USB / BC1.2 charger detection routines */
 #undef CONFIG_USB_CHARGER
 
@@ -4252,8 +4220,6 @@
 
 /* Support control of multiple PHY */
 #undef CONFIG_USB_SELECT_PHY
-/* Select which USB PHY will be used at startup */
-#undef CONFIG_USB_SELECT_PHY_DEFAULT
 
 /* Support simple control of power to the device's USB ports */
 #undef CONFIG_USB_PORT_POWER_DUMB
@@ -4510,9 +4476,6 @@
 #define CONFIG_RW_HEAD_ROOM 0
 
 /* Firmware upgrade options. */
-/* Firmware updates using other than HC channel(s). */
-#undef CONFIG_NON_HC_FW_UPDATE
-#undef CONFIG_USB_FW_UPDATE
 /* A different config for the same update. TODO(vbendeb): dedupe these */
 #undef CONFIG_USB_UPDATE
 
@@ -4544,12 +4507,6 @@
 #undef CONFIG_BOARD_ID_SUPPORT
 
 /*
- * Define this if serial number support is required. For g chip based boards
- * it allows a verifiable serial number to be stored / certified.
- */
-#undef CONFIG_SN_BITS_SUPPORT
-
-/*
  * Define this to enable Cros Board Info support. I2C_EEPROM_PORT and
  * I2C_EEPROM_ADDR must be defined as well.
  */
diff --git a/test/build.mk b/test/build.mk
index 4235274312..2658cca4af 100644
--- a/test/build.mk
+++ b/test/build.mk
@@ -62,7 +62,6 @@ test-list-host += pinweaver
 test-list-host += power_button
 test-list-host += printf
 test-list-host += queue
-test-list-host += rma_auth
 test-list-host += rsa
 test-list-host += rsa3
 test-list-host += rtc
@@ -147,7 +146,6 @@ power_button-y=power_button.o
 powerdemo-y=powerdemo.o
 printf-y=printf.o
 queue-y=queue.o
-rma_auth-y=rma_auth.o
 rsa-y=rsa.o
 rsa3-y=rsa.o
 rtc-y=rtc.o
diff --git a/test/rma_auth.c b/test/rma_auth.c
deleted file mode 100644
index c03ba70acd..0000000000
--- a/test/rma_auth.c
+++ /dev/null
@@ -1,214 +0,0 @@
-/* Copyright 2017 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Test RMA auth challenge/response
- */
-
-#include <endian.h>
-#include <stdio.h>
-#include "common.h"
-#include "chip/g/board_id.h"
-#include "curve25519.h"
-#include "base32.h"
-#include "sha256.h"
-#include "rma_auth.h"
-#include "test_util.h"
-#include "timer.h"
-#include "util.h"
-
-/* Dummy implementations for testing */
-static uint8_t dummy_board_id[4] = {'Z', 'Z', 'C', 'R'};
-static uint8_t dummy_device_id[8] = {'T', 'H', 'X', 1, 1, 3, 8, 0xfe};
-static int server_protocol_version = RMA_CHALLENGE_VERSION;
-static uint8_t server_private_key[32] = RMA_TEST_SERVER_PRIVATE_KEY;
-static int server_key_id = RMA_TEST_SERVER_KEY_ID;
-
-void rand_bytes(void *buffer, size_t len)
-{
-	FILE *f = fopen("/dev/urandom", "rb");
-
-	assert(f);
-	fread(buffer, 1, len, f);
-	fclose(f);
-}
-
-int read_board_id(struct board_id *id)
-{
-	memcpy(&id->type, dummy_board_id, sizeof(id->type));
-	id->type_inv = ~id->type;
-	id->flags = 0xFF00;
-	return EC_SUCCESS;
-}
-
-int system_get_chip_unique_id(uint8_t **id)
-{
-	*id = dummy_device_id;
-	return sizeof(dummy_device_id);
-}
-
-/**
- * Simulate the server side of a RMA challenge-response.
- *
- * @param out_auth_code		Buffer for generated authorization code
- *				(must be >= CR50_AUTH_CODE_CHARS + 1 chars)
- * @param challenge		Challenge from device
- * @return 0 if success, non-zero if error.
- */
-int rma_server_side(char *out_auth_code, const char *challenge)
-{
-	int version, key_id;
-	uint32_t device_id[2];
-	uint8_t secret[32];
-	uint8_t hmac[32];
-	struct rma_challenge c;
-	uint8_t *cptr = (uint8_t *)&c;
-
-	/* Convert the challenge back into binary */
-	if (base32_decode(cptr, 8 * sizeof(c), challenge, 9) != 8 * sizeof(c)) {
-		printf("Error decoding challenge\n");
-		return -1;
-	}
-
-	version = RMA_CHALLENGE_GET_VERSION(c.version_key_id);
-	if (version != server_protocol_version) {
-		printf("Unsupported challenge version %d\n", version);
-		return -1;
-	}
-
-	key_id = RMA_CHALLENGE_GET_KEY_ID(c.version_key_id);
-
-	printf("\nChallenge: %s\n", challenge);
-	printf("  Version:      %d\n", version);
-	printf("  Server KeyID: %d\n", key_id);
-	printf("  BoardID:      %c%c%c%c\n",
-	       isprint(c.board_id[0]) ? c.board_id[0] : '?',
-	       isprint(c.board_id[1]) ? c.board_id[1] : '?',
-	       isprint(c.board_id[2]) ? c.board_id[2] : '?',
-	       isprint(c.board_id[3]) ? c.board_id[3] : '?');
-
-	memcpy(device_id, c.device_id, sizeof(device_id));
-	printf("  DeviceID:     0x%08x 0x%08x\n", device_id[0], device_id[1]);
-
-	if (key_id != server_key_id) {
-		printf("Unsupported KeyID %d\n", key_id);
-		return -1;
-	}
-
-	/*
-	 * Make sure the current user is authorized to reset this board.
-	 *
-	 * Since this is just a test, here we'll just make sure the BoardID
-	 * and DeviceID match what we expected.
-	 */
-	if (memcmp(c.board_id, dummy_board_id, sizeof(c.board_id))) {
-		printf("BoardID mismatch\n");
-		return -1;
-	}
-	if (memcmp(c.device_id, dummy_device_id, sizeof(c.device_id))) {
-		printf("DeviceID mismatch\n");
-		return -1;
-	}
-
-	/* Calculate the shared secret */
-	X25519(secret, server_private_key, c.device_pub_key);
-
-	/*
-	 * Auth code is a truncated HMAC of the ephemeral public key, BoardID,
-	 * and DeviceID.
-	 */
-	hmac_SHA256(hmac, secret, sizeof(secret), cptr + 1, sizeof(c) - 1);
-	if (base32_encode(out_auth_code, RMA_AUTHCODE_BUF_SIZE,
-			  hmac, RMA_AUTHCODE_CHARS * 5, 0)) {
-		printf("Error encoding auth code\n");
-		return -1;
-	}
-	printf("Authcode: %s\n", out_auth_code);
-
-	return 0;
-};
-
-#define FORCE_TIME(t) { ts.val = (t); force_time(ts); }
-
-/*
- * rma_try_authcode expects a buffer that is at least RMA_AUTHCODE_CHARS long,
- * so copy the input string to a buffer before calling the function.
- */
-static int rma_try_authcode_pad(const char *code)
-{
-	char authcode[RMA_AUTHCODE_BUF_SIZE];
-
-	memset(authcode, 0, sizeof(authcode));
-	strncpy(authcode, code, sizeof(authcode));
-
-	return rma_try_authcode(authcode);
-}
-
-static int test_rma_auth(void)
-{
-	const char *challenge;
-	char authcode[RMA_AUTHCODE_BUF_SIZE];
-	timestamp_t ts;
-
-	/* Test rate limiting */
-	FORCE_TIME(9 * SECOND);
-	TEST_ASSERT(rma_create_challenge() == EC_ERROR_TIMEOUT);
-	TEST_ASSERT(rma_try_authcode_pad("Bad") == EC_ERROR_ACCESS_DENIED);
-	TEST_ASSERT(strlen(rma_get_challenge()) == 0);
-
-	FORCE_TIME(10 * SECOND);
-	TEST_ASSERT(rma_create_challenge() == 0);
-	TEST_ASSERT(strlen(rma_get_challenge()) == RMA_CHALLENGE_CHARS);
-
-	/* Test using up tries */
-	TEST_ASSERT(rma_try_authcode_pad("Bad") == EC_ERROR_INVAL);
-	TEST_ASSERT(strlen(rma_get_challenge()) == RMA_CHALLENGE_CHARS);
-	TEST_ASSERT(rma_try_authcode_pad("BadCodeZ") == EC_ERROR_INVAL);
-	TEST_ASSERT(strlen(rma_get_challenge()) == RMA_CHALLENGE_CHARS);
-	TEST_ASSERT(rma_try_authcode_pad("BadLongCode") == EC_ERROR_INVAL);
-	/* Out of tries now */
-	TEST_ASSERT(strlen(rma_get_challenge()) == 0);
-	TEST_ASSERT(rma_try_authcode_pad("Bad") == EC_ERROR_ACCESS_DENIED);
-
-	FORCE_TIME(19 * SECOND);
-	TEST_ASSERT(rma_create_challenge() == EC_ERROR_TIMEOUT);
-	TEST_ASSERT(strlen(rma_get_challenge()) == 0);
-
-	FORCE_TIME(21 * SECOND);
-	TEST_ASSERT(rma_create_challenge() == 0);
-	challenge = rma_get_challenge();
-	TEST_ASSERT(strlen(challenge) == RMA_CHALLENGE_CHARS);
-	TEST_ASSERT(rma_server_side(authcode, challenge) == 0);
-	TEST_ASSERT(rma_try_authcode(authcode) == EC_SUCCESS);
-
-	/*
-	 * Make sure the server-side checks for fields work.  That is, test
-	 * our ability to test those fields...
-	 */
-	server_protocol_version++;
-	TEST_ASSERT(rma_server_side(authcode, challenge) == -1);
-	server_protocol_version--;
-
-	server_key_id++;
-	TEST_ASSERT(rma_server_side(authcode, challenge) == -1);
-	server_key_id--;
-
-	dummy_board_id[0]++;
-	TEST_ASSERT(rma_server_side(authcode, challenge) == -1);
-	dummy_board_id[0]--;
-
-	dummy_device_id[0]++;
-	TEST_ASSERT(rma_server_side(authcode, challenge) == -1);
-	dummy_device_id[0]--;
-
-	return EC_SUCCESS;
-}
-
-void run_test(void)
-{
-	test_reset();
-
-	RUN_TEST(test_rma_auth);
-
-	test_print_result();
-}
diff --git a/test/tpm_test/Makefile b/test/tpm_test/Makefile
deleted file mode 100644
index 8942f0db1d..0000000000
--- a/test/tpm_test/Makefile
+++ /dev/null
@@ -1,85 +0,0 @@
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# V unset for normal output, V=1 for verbose output, V=0 for silent build
-# (warnings/errors only). Use echo thus: $(call echo,"stuff  to  echo")
-ifeq ($(V),0)
-Q := @
-echo = echo -n;
-else
-echo = echo $(1);
-ifeq ($(V),)
-Q := @
-else
-Q :=
-endif
-endif
-
-obj = ../../build/tpm_test
-src = .
-SWIG = /usr/bin/swig
-
-vpath %c $(src) ../../chip/g/dcrypto $(src)/testlib
-
-CFLAGS = -fPIC
-CFLAGS += -I /usr/include/python2.7
-CFLAGS += -I../../../../third_party/cryptoc/include
-CFLAGS += -I../../board/cr50
-CFLAGS += -I../../chip/g
-CFLAGS += -I../../chip/g/dcrypto
-CFLAGS += -I../../fuzz
-CFLAGS += -I../../include
-CFLAGS += -I..
-CFLAGS += -I../..
-CFLAGS += -I.
-CFLAGS += -Itestlib
-CFLAGS += -DLIBFTDI1=1
-CFLAGS += -c
-CFLAGS += -DCR50_NO_BN_ASM
-CFLAGS += -I../../fuzz
-TARGET = ftdi_spi_tpm
-
-.PRECIOUS: $(obj)/ftdi_spi_tpm_wrap.c
-
-all: $(obj)/_$(TARGET).so $(obj)/bn_test
-
-BN_OBJS = $(obj)/bn_test.o $(obj)/common.o $(obj)/bn.o
-
-OBJS = $(obj)/$(TARGET).o $(obj)/$(TARGET)_wrap.o $(obj)/mpsse.o \
-	$(obj)/support.o
-
-DEPS := $(OBJS:.o=.o.d) $(BN_OBJS:.o=.o.d)
-
-$(OBJS) $(BN_OBJS): | $(obj)
-
-$(obj)/%.o: $(obj)/%.c
-	$(call echo,"  CC      $(notdir $@)")
-	$(Q)gcc $(CFLAGS) -o $@ $<
-
-# See "Commonly used compiler options" for more documentation
-$(obj)/%.o: %.c
-	$(call echo,"  CC      $(notdir $@)")
-	$(Q)gcc $(CFLAGS) -Wall -Werror -MMD -MF $@.d -MT $@ -o $@ $<
-
-$(obj)/_$(TARGET).so: $(OBJS) $(obj)/$(TARGET).py
-	$(call echo,"  LD      $(notdir $@)")
-	$(Q)rm -f $@
-	$(Q)gcc -shared $(OBJS) -lftdi1 -o $@
-
-$(obj)/%_wrap.c: $(src)/%.i
-	$(call echo,"  SWIG    $(notdir $@)")
-	$(Q)swig -python -outdir $(obj) -o $@ $<
-
-clean:
-	@rm -rf $(obj)/
-
-$(obj):
-	$(call echo,"  MKDIR   $(obj)")
-	$(Q)mkdir -p $(obj)
-
-$(obj)/bn_test: $(BN_OBJS)
-	$(call echo,"  LD      $(notdir $@)")
-	$(Q)$(CC) -o $@ $^ -lcrypto
-
--include $(DEPS)
diff --git a/test/tpm_test/README.md b/test/tpm_test/README.md
deleted file mode 100644
index 80aaa0a76f..0000000000
--- a/test/tpm_test/README.md
+++ /dev/null
@@ -1,49 +0,0 @@
-# TPM / Crypto unit tests
-tpmtest.py runs set of tests to check correctness of cryptographic functions
-implementation. These tests require a special firmware image built with
-CRYPTO_TEST=1 flag to enable direct exposure of low-level cryptographic
-functions via TPM extensions and vendor commands. TPM functionality itself
-is disabled due to not enough enough flash/memory to fit both.
-As such, these tests are expected to run over H1 Red board.
-
-Firmware image is expected to be built with:
-
-make BOARD=cr50 CRYPTO_TEST=1 -j
-
-Cryptographic tests are invoked when tpmtest.py is executed with no command-line
-parameters:
-
-        ./tpmtest.py
-
-Option *-d* can be used for debugging. It adds output of actual data
-sent/received from H1, which is handy when adding new functionality:
-
-        ./tpmtest.py -d
-
-# TRNG tests
-Another functionality is statistical assessment of entropy from True Random
-Number Generator (TRNG). These tests are prerequisite for FIPS 140-2/3
-certification and governed by NIST SP 800-90B.
-tpmtest.py implements a mode to download raw data from TRNG:
-
-        ./tpmtest.py -t
-
-Script nist_entropy.sh automated this testing by
-1. Downloading latest NIST Entropy Assessment tool from
-   [https://github.com/usnistgov/SP800-90B_EntropyAssessment] and building it.
-2. Gathering 1000000 of 8-bit samples from H1 TRNG and
-   storing it in /tmp/trng_output using tpmtest.py -t
-3. Running NIST tool in non-IID (independent and identically distributed) mode
-   to estimate entropy. This specific mode is choosed as there is no formal
-   proof that TRNG data is independent and identically distributed.
-   It follows manual in
-   [https://nvlpubs.nist.gov/nistpubs/SpecialPublications/NIST.SP.800-90B.pdf]
-
-The successful result is being awarded entropy estimate for TRNG, which is
-expected to be more than 7 (8 is theoretical max).
-If test fails, no entropy assessment is awarded.
-
-This script is expected to run in platform/ec/test/tpm_test directory
-(where ./tpmtest.py is located)
-
-
diff --git a/test/tpm_test/bn_test.c b/test/tpm_test/bn_test.c
deleted file mode 100644
index db06ee93d4..0000000000
--- a/test/tpm_test/bn_test.c
+++ /dev/null
@@ -1,412 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-#include "dcrypto.h"
-
-#include <assert.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <sys/param.h>
-
-#include <openssl/bn.h>
-
-/**
- * Compatibility layer for OpenSSL 1.0.x.
- * BN_bn2lebinpad and BN_lebin2bn were added in OpenSSL 1.1, to provide
- * import/export functionality as BIGNUM struct became opaque.
- */
-#if OPENSSL_VERSION_NUMBER < 0x10100000L
-#define BN_RAND_TOP_ANY -1
-#define BN_RAND_TOP_ONE 0
-#define BN_RAND_TOP_TWO 1
-#define BN_RAND_BOTTOM_ODD 1
-#define BN_RAND_BOTTOM_ANY 0
-
-/* export BIGNUM as little-endian padded to tolen bytes binary */
-static int BN_bn2lebinpad(const BIGNUM *a, unsigned char *to, int tolen)
-{
-	int i;
-	BN_ULONG l;
-
-	bn_check_top(a);
-	i = BN_num_bytes(a);
-	if (tolen < i)
-		return -1;
-	/* Add trailing zeroes if necessary */
-	if (tolen > i)
-		memset(to + i, 0, tolen - i);
-	to += i;
-	while (i--) {
-		l = a->d[i / BN_BYTES];
-		to--;
-		*to = (unsigned char)(l >> (8 * (i % BN_BYTES))) & 0xff;
-	}
-	return tolen;
-}
-
-/* import BIGNUM from little-endian binary of specified length */
-static BIGNUM *BN_lebin2bn(const unsigned char *s, int len, BIGNUM *ret)
-{
-	unsigned int i, m;
-	unsigned int n;
-	BN_ULONG l;
-	BIGNUM *bn = NULL;
-
-	if (ret == NULL)
-		ret = bn = BN_new();
-	if (ret == NULL)
-		return (NULL);
-	bn_check_top(ret);
-	s += len;
-	/* Skip trailing zeroes. */
-	for (; len > 0 && s[-1] == 0; s--, len--)
-		continue;
-	n = len;
-	if (n == 0) {
-		ret->top = 0;
-		return ret;
-	}
-	i = ((n - 1) / BN_BYTES) + 1;
-	m = ((n - 1) % (BN_BYTES));
-	if (bn_wexpand(ret, (int)i) == NULL) {
-		BN_free(bn);
-		return NULL;
-	}
-	ret->top = i;
-	ret->neg = 0;
-	l = 0;
-	while (n--) {
-		s--;
-		l = (l << 8L) | *s;
-		if (m-- == 0) {
-			ret->d[--i] = l;
-			l = 0;
-			m = BN_BYTES - 1;
-		}
-	}
-	/*
-	 * need to call this due to clear byte at top if avoiding
-	 * having the top bit set (-ve number)
-	 */
-	bn_correct_top(ret);
-	return ret;
-}
-#endif
-
-#define MAX_BN_TEST_SIZE 2048
-
-static char to_hexchar(unsigned char c)
-{
-	return (c < 10) ? c + '0' : c - 10 + 'A';
-}
-
-static void hex_print(FILE *fp, unsigned char *d, int size)
-{
-	char buf[MAX_BN_TEST_SIZE / 4 + 1];
-	int i = 0;
-
-	assert((size * 2) + 1 <= sizeof(buf));
-	while (i < size) {
-		buf[i * 2] = to_hexchar((d[size - i - 1] >> 4) & 0xF);
-		buf[i * 2 + 1] = to_hexchar(d[size - i - 1] & 0xF);
-		i++;
-	};
-	buf[size * 2] = 0;
-	fprintf(fp, buf);
-}
-
-static void dcrypto_print(FILE *fp, struct LITE_BIGNUM *d, int size)
-{
-	hex_print(fp, (unsigned char *)d->d, size);
-}
-
-static int bn_dcrypto_cmpeq(const BIGNUM *b, struct LITE_BIGNUM *d)
-{
-	unsigned char buf[MAX_BN_TEST_SIZE / 8];
-	int size = BN_num_bytes(b);
-
-	assert(size <= sizeof(buf));
-	BN_bn2lebinpad(b, buf, size);
-	return memcmp(d->d, buf, size);
-}
-
-/* Convert OpenSSL BIGNUM to Dcrypto, assumes caller provides buffer */
-static void bn_to_dcrypto(const BIGNUM *b, struct LITE_BIGNUM *d, uint32_t *buf,
-			  size_t bufsize)
-{
-	int bn_size = BN_num_bytes(b);
-
-	assert(bn_size <= bufsize);
-	memset(buf, 0, bufsize);
-	/**
-	 * OpenSSL 1.0 was only working for little-endian architectures (x86)
-	 * and had direct access to BIGNUM structure, so DCRYPTO_bn_wrap which
-	 * just sets a pointer to user provided buffer as source for
-	 * LITE_BIGNUM could be applied to data in BIGNUM as is.
-	 * In OpenSSL 1.1 BIGNUM became opaque, so we need to export binary
-	 * to get data in little-endian format which used by DCRYPTO_*.
-	 */
-	BN_bn2lebinpad(b, (unsigned char *)buf, bn_size);
-	DCRYPTO_bn_wrap(d, buf, bufsize);
-}
-
-static int test_bn_modinv_helper(const BIGNUM *E, BN_CTX *ctx, int mod_top,
-				 int mod_bottom)
-{
-	int i, result = 0;
-	BIGNUM *MOD, *r;
-
-	BN_CTX_start(ctx);
-	MOD = BN_CTX_get(ctx);
-	r = BN_CTX_get(ctx);
-
-	for (i = 0; i < 1000; i++) {
-		uint32_t m_buf[MAX_BN_TEST_SIZE / LITE_BN_BITS2];
-		uint32_t d_buf[MAX_BN_TEST_SIZE / LITE_BN_BITS2];
-		uint32_t e_buf[MAX_BN_TEST_SIZE / LITE_BN_BITS2];
-		int has_inverse;
-		int test_inverse;
-
-		struct LITE_BIGNUM m;
-		struct LITE_BIGNUM e;
-		struct LITE_BIGNUM d;
-
-		/* Top bit set, bottom bit clear. */
-		BN_rand(MOD, MAX_BN_TEST_SIZE, mod_top, mod_bottom);
-
-		if (BN_mod_inverse(r, E, MOD, ctx))
-			has_inverse = 1;
-		else
-			has_inverse = 0;
-		bn_to_dcrypto(MOD, &m, m_buf, sizeof(m_buf));
-		bn_to_dcrypto(E, &e, e_buf, sizeof(e_buf));
-
-		bn_init(&d, d_buf, sizeof(d_buf));
-
-		test_inverse = bn_modinv_vartime(&d, &e, &m);
-
-		if (test_inverse != has_inverse) {
-			fprintf(stderr,
-				"ossl inverse: %d, dcrypto inverse: %d\n",
-				has_inverse, test_inverse);
-			fprintf(stderr, "d : ");
-			BN_print_fp(stderr, r);
-			fprintf(stderr, "\n");
-
-			fprintf(stderr, "e : ");
-			BN_print_fp(stderr, E);
-			fprintf(stderr, "\n");
-
-			fprintf(stderr, "M : ");
-			BN_print_fp(stderr, MOD);
-			fprintf(stderr, "\n");
-			result = 1;
-			goto fail;
-		}
-
-		if (has_inverse) {
-			if (bn_dcrypto_cmpeq(r, &d) != 0) {
-				fprintf(stderr,
-					"dcrypto bn_modinv_vartime fail\n");
-				fprintf(stderr, "d : ");
-				BN_print_fp(stderr, r);
-				fprintf(stderr, "\n dd: ");
-				dcrypto_print(stderr, &d, BN_num_bytes(r));
-				fprintf(stderr, "\n");
-
-				fprintf(stderr, "e : ");
-				BN_print_fp(stderr, E);
-				fprintf(stderr, "\n");
-
-				fprintf(stderr, "M : ");
-				BN_print_fp(stderr, MOD);
-				fprintf(stderr, "\n");
-
-				result = 1;
-				goto fail;
-			}
-		}
-	}
-fail:
-	BN_CTX_end(ctx);
-	return result;
-}
-
-static int test_bn_modinv(void)
-{
-	BN_CTX *ctx;
-	BIGNUM *E;
-	int result = 1;
-
-	ctx = BN_CTX_new();
-	BN_CTX_start(ctx);
-
-	E = BN_CTX_get(ctx);
-
-	BN_rand(E, 1024, BN_RAND_TOP_ONE, BN_RAND_BOTTOM_ODD);
-	/* Top bit set, bottom bit clear. */
-	if (test_bn_modinv_helper(E, ctx, BN_RAND_TOP_ONE, BN_RAND_BOTTOM_ANY))
-		goto fail;
-
-	if (test_bn_modinv_helper(E, ctx, BN_RAND_TOP_TWO, BN_RAND_BOTTOM_ANY))
-		goto fail;
-
-	BN_rand(E, 32, BN_RAND_TOP_TWO, BN_RAND_BOTTOM_ODD);
-	if (test_bn_modinv_helper(E, ctx, BN_RAND_TOP_ONE, BN_RAND_BOTTOM_ANY))
-		goto fail;
-
-	BN_rand(E, 17, BN_RAND_TOP_ANY, BN_RAND_BOTTOM_ODD);
-	if (test_bn_modinv_helper(E, ctx, BN_RAND_TOP_ONE, BN_RAND_BOTTOM_ANY))
-		goto fail;
-
-	BN_set_word(E, 3);
-	if (test_bn_modinv_helper(E, ctx, BN_RAND_TOP_ONE, BN_RAND_BOTTOM_ANY))
-		goto fail;
-
-	BN_set_word(E, 65537);
-	if (test_bn_modinv_helper(E, ctx, BN_RAND_TOP_ONE, BN_RAND_BOTTOM_ANY))
-		goto fail;
-
-	result = 0;
-fail:
-	BN_CTX_end(ctx);
-	BN_CTX_free(ctx);
-	return result;
-}
-
-/* Build a BIGNUM with following template:
- * 11111111111111110000001111111111111000000000000123455667
- * size - size in bits
- * front_ones        mid_ones_pos,mid_ones,     rand_low
- * front_ones - number of 1 bits in highest position
- * mid_ones_pos - starting position of middle ones
- * mid_ones - number of 1 bits in the middle
- * rand_low - number of random low bits
- */
-static BIGNUM *bn_gen(BIGNUM *out, int size, int front_ones, int mid_ones_pos,
-		      int mid_ones, int rand_low)
-{
-	unsigned char n[MAX_BN_TEST_SIZE / 8] = {};
-
-	assert(size <= sizeof(n) * 8);
-	assert(front_ones < size);
-	assert(mid_ones_pos < (size - front_ones - 1));
-	assert(mid_ones < (size - mid_ones_pos - 1));
-	assert(rand_low < (size - mid_ones_pos - mid_ones - 1));
-	/* generate little-endian representation */
-	while (front_ones) {
-		n[(size - front_ones) / 8] |= 1 << ((size - front_ones) & 7);
-		front_ones--;
-	}
-	while (mid_ones) {
-		n[(mid_ones_pos - mid_ones) / 8] |=
-			1 << ((mid_ones_pos - mid_ones) & 7);
-		mid_ones--;
-	}
-	while (rand_low) {
-		n[(rand_low - 1) / 8] |= (rand() & 1) << ((rand_low - 1) & 7);
-		rand_low--;
-	}
-
-	return BN_lebin2bn(n, size / 8, out);
-}
-
-static int test_bn_div(void)
-{
-	const int NSIZE = MAX_BN_TEST_SIZE;
-	const int PSIZE = MAX_BN_TEST_SIZE / 2;
-	BIGNUM *N, *P, *Q, *R;
-	BN_CTX *ctx;
-	int result = 0, total = 0, prev = 1;
-	int nf, nmps, nms, pf, pmps, pms;
-	struct LITE_BIGNUM p;
-	struct LITE_BIGNUM q;
-	struct LITE_BIGNUM n;
-	struct LITE_BIGNUM r;
-
-	uint32_t p_buff[MAX_BN_TEST_SIZE / LITE_BN_BITS2];
-	uint32_t q_buff[MAX_BN_TEST_SIZE / LITE_BN_BITS2];
-	uint32_t n_buff[MAX_BN_TEST_SIZE / LITE_BN_BITS2];
-	uint32_t r_buff[MAX_BN_TEST_SIZE / LITE_BN_BITS2];
-
-	ctx = BN_CTX_new();
-	BN_CTX_start(ctx);
-	N = BN_CTX_get(ctx);
-	P = BN_CTX_get(ctx);
-	Q = BN_CTX_get(ctx);
-	R = BN_CTX_get(ctx);
-
-	for (nf = 1; nf <= NSIZE / 8; nf++)
-	for (nmps = NSIZE / 16; nmps < (NSIZE / 16) + 2; nmps++)
-	for (nms = NSIZE / 32; nms < (NSIZE / 32) + 2; nms++) {
-		N = bn_gen(N, NSIZE, nf, nmps, nms, (nmps - nms) / 2);
-		for (pf = 1; pf <= PSIZE / 4; pf++)
-		for (pmps = PSIZE / 16; pmps < (PSIZE / 16) + 2; pmps++)
-		for (pms = PSIZE / 32; pms < (PSIZE / 32) + 2; pms++) {
-			P = bn_gen(P, PSIZE, pf, pmps, pms, (pmps - pms) / 2);
-			total++;
-			bn_to_dcrypto(N, &n, n_buff, sizeof(n_buff));
-			bn_to_dcrypto(P, &p, p_buff, sizeof(p_buff));
-			DCRYPTO_bn_wrap(&q, q_buff, sizeof(q_buff));
-			DCRYPTO_bn_wrap(&r, r_buff, sizeof(r_buff));
-
-			BN_div(Q, R, N, P, ctx);
-			DCRYPTO_bn_div(&q, &r, &n, &p);
-
-			if ((bn_dcrypto_cmpeq(Q, &q) != 0) ||
-			    (bn_dcrypto_cmpeq(R, &r) != 0)) {
-				result++;
-				if (result > prev) {
-					/* print only 1 sample in 100000 */
-					prev = result + 100000;
-					fprintf(stderr, "N : ");
-					BN_print_fp(stderr, N);
-					fprintf(stderr, "\n");
-					fprintf(stderr, "P : ");
-					BN_print_fp(stderr, P);
-					fprintf(stderr, "\n");
-
-					fprintf(stderr, "Q : ");
-					BN_print_fp(stderr, Q);
-					fprintf(stderr, "\nQd: ");
-					dcrypto_print(stderr, &q,
-						      BN_num_bytes(Q));
-					fprintf(stderr, "\n");
-
-					fprintf(stderr, "R : ");
-					BN_print_fp(stderr, R);
-					fprintf(stderr, "\nRd: ");
-					dcrypto_print(stderr, &r,
-						      BN_num_bytes(R));
-					fprintf(stderr, "\n");
-				}
-			}
-		}
-	}
-	if (result)
-		fprintf(stderr, "DCRYPTO_bn_div: total=%d, failures=%d\n",
-			total, result);
-	BN_CTX_end(ctx);
-	BN_CTX_free(ctx);
-
-	return result;
-}
-
-void *always_memset(void *s, int c, size_t n)
-{
-	memset(s, c, n);
-	return s;
-}
-
-void watchdog_reload(void)
-{
-}
-
-int main(void)
-{
-	assert(test_bn_modinv() == 0);
-	assert(test_bn_div() == 0);
-	fprintf(stderr, "PASS\n");
-	return 0;
-}
diff --git a/test/tpm_test/crypto_test.py b/test/tpm_test/crypto_test.py
deleted file mode 100644
index 36253952c5..0000000000
--- a/test/tpm_test/crypto_test.py
+++ /dev/null
@@ -1,243 +0,0 @@
-#!/usr/bin/env python2
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-"""Module for testing cryptography functions using extended commands."""
-
-from __future__ import print_function
-
-import binascii
-import struct
-import xml.etree.ElementTree as ET
-
-import subcmd
-import utils
-
-# Basic crypto operations
-DECRYPT = 0
-ENCRYPT = 1
-
-def get_attribute(tdesc, attr_name, required=True):
-  """Retrieve an attribute value from an XML node.
-
-  Args:
-    tdesc: an Element of the ElementTree, a test descriptor containing
-      necessary information to run a single encryption/description
-      session.
-    attr_name: a string, the name of the attribute to retrieve.
-    required: a Boolean, if True - the attribute must be present in the
-      descriptor, otherwise it is considered optional
-  Returns:
-    The attribute value as a string (ascii or binary)
-  Raises:
-    subcmd.TpmTestError: on various format errors, or in case a required
-      attribute is not found, the error message describes the problem.
-
-  """
-  # Fields stored in hex format by default.
-  default_hex = ('aad', 'cipher_text', 'iv', 'key', 'tag')
-
-  data = tdesc.find(attr_name)
-  if data is None:
-    if required:
-      raise subcmd.TpmTestError('node "%s" does not have attribute "%s"' %
-                        (tdesc.get('name'), attr_name))
-    return ''
-
-  # Attribute is present, does it have to be decoded from hex?
-  cell_format = data.get('format')
-  if not cell_format:
-    if attr_name in default_hex:
-      cell_format = 'hex'
-    else:
-      cell_format = 'ascii'
-  elif cell_format not in ('hex', 'ascii'):
-    raise subcmd.TpmTestError('%s:%s, unrecognizable format "%s"' %
-                      (tdesc.get('name'), attr_name, cell_format))
-
-  text = ' '.join(x.strip() for x in data.text.splitlines() if x)
-  if cell_format == 'ascii':
-    return text
-
-  # Drop spaces from hex representation.
-  text = text.replace(' ', '')
-
-  # Convert hex-text to little-endian binary (in 4-byte word chunks)
-  value = ''
-  for x in range(len(text)/8):
-    try:
-      value += struct.pack('<I', int('0x%s' % text[8*x:8*(x+1)], 16))
-    except ValueError:
-      raise subcmd.TpmTestError('%s:%s %swrong hex value' %
-                        (tdesc.get('name'), attr_name, utils.hex_dump(text)))
-
-  # Unpack remaining hex text, without introducing a zero pad.
-  for x in range(-1, -(len(text) % 8), -1):
-    value += chr(int(text[2*x:len(text) + (2*x)+2], 16))
-
-  return value
-
-
-class CryptoD(object):
-  """A helper object to contain an encryption scheme description.
-
-  Attributes:
-    subcmd: a 16 bit max integer, the extension subcommand to be used with
-      this encryption scheme.
-    sumbodes: an optional dictionary, the keys are strings, names of the
-      encryption scheme submodes, the values are integers to be included in
-      the appropriate subcommand fields to communicat the submode to the
-      device.
-  """
-
-  def __init__(self, subcommand, submodes=None):
-    self.subcmd = subcommand
-    if not submodes:
-      submodes = {}
-    self.submodes = submodes
-
-SUPPORTED_MODES = {
-    'AES': CryptoD(subcmd.AES, {
-        'ECB': 0,
-        'CTR': 1,
-        'CBC': 2,
-        'GCM': 3,
-        'OFB': 4,
-        'CFB': 5
-    }),
-}
-
-def crypto_run(node_name, op_type, key, iv, aad, in_text, out_text, tpm):
-  """Perform a basic operation(encrypt or decrypt).
-
-  This function creates an extended command with the requested parameters,
-  sends it to the device, and then compares the response to the expected
-  value.
-
-  Args:
-    node_name: a string, the name of the XML node this data comes from. The
-      format of the name is "<enc type>:<submode> ....", where <enc type> is
-      the major encryption mode (say AED or DES) and submode - a variant of
-      the major scheme, if exists.
-
-   op_type: an int, encodes the operation to perform (encrypt/decrypt), passed
-     directly to the device as a field in the extended command
-   key: a binary string
-   iv: a binary string, might be empty
-   aad: additional authenticated data
-   in_text: a binary string, the input of the encrypt/decrypt operation
-   out_text: a binary string, might be empty, the expected output of the
-     operation. Note that it could be shorter than actual output (padded to
-     integer number of blocks), in which case only its length of bytes is
-     compared debug_mode: a Boolean, if True - enables tracing on the console
-   tpm: a TPM object to send extended commands to an initialized TPM
-
-  Returns:
-    The actual binary string, result of the operation, if the
-    comparison with the expected value was successful.
-
-  Raises:
-    subcmd.TpmTestError: in case there were problems parsing the node name, or
-      verifying the operation results.
-
-  """
-  mode_name, submode_name = node_name.split(':')
-  submode_name = submode_name[:3].upper()
-
-  mode = SUPPORTED_MODES.get(mode_name.upper())
-  if not mode:
-    raise subcmd.TpmTestError('unrecognizable mode in node "%s"' % node_name)
-
-  submode = mode.submodes.get(submode_name, 0)
-  cmd = '%c' % op_type    # Encrypt or decrypt
-  cmd += '%c' % submode   # A particular type of a generic algorithm.
-  cmd += '%c' % len(key)
-  cmd += key
-  cmd += '%c' % len(iv)
-  if iv:
-    cmd += iv
-  cmd += '%c' % len(aad)
-  if aad:
-    cmd += aad
-  cmd += struct.pack('>H', len(in_text))
-  cmd += in_text
-  if tpm.debug_enabled():
-    print('%d:%d cmd size' % (op_type, mode.subcmd),
-          len(cmd), utils.hex_dump(cmd))
-  wrapped_response = tpm.command(tpm.wrap_ext_command(mode.subcmd, cmd))
-  real_out_text = tpm.unwrap_ext_response(mode.subcmd, wrapped_response)
-  if out_text:
-    if len(real_out_text) > len(out_text):
-      real_out_text = real_out_text[:len(out_text)]  # Ignore padding
-    if real_out_text != out_text:
-      if tpm.debug_enabled():
-        print('Out text mismatch in node %s:\n' % node_name)
-      else:
-        raise subcmd.TpmTestError(
-          'Out text mismatch in node %s, operation %s:\n'
-          'In text:%sExpected out text:%sReal out text:%s' % (
-            node_name, 'ENCRYPT' if op_type == ENCRYPT else 'DECRYPT',
-            utils.hex_dump(in_text),
-            utils.hex_dump(out_text),
-            utils.hex_dump(real_out_text)))
-  return real_out_text
-
-
-def crypto_test(tdesc, tpm):
-  """Perform a single test described in the xml file.
-
-  The xml node contains all pertinent information about the test inputs and
-  outputs.
-
-  Args:
-    tdesc: an Element of the ElementTree, a test descriptor containing
-      necessary information to run a single encryption/description
-      session.
-    tpm: a TPM object to send extended commands to an initialized TPM
-  Raises:
-    subcmd.TpmTestError: on various execution errors, the details are included
-      in the error message.
-
-  """
-  node_name = tdesc.get('name')
-  key = get_attribute(tdesc, 'key')
-  if len(key) not in (16, 24, 32):
-    raise subcmd.TpmTestError('wrong key size "%s:%s"' % (
-        node_name,
-        ''.join('%2.2x' % ord(x) for x in key)))
-  iv = get_attribute(tdesc, 'iv', required=False)
-  if iv and not node_name.startswith('AES:GCM') and len(iv) != 16:
-    raise subcmd.TpmTestError('wrong iv size "%s:%s"' % (
-        node_name,
-        ''.join('%2.2x' % ord(x) for x in iv)))
-  clear_text = get_attribute(tdesc, 'clear_text', required=False)
-  if clear_text:
-    clear_text_len = get_attribute(tdesc, 'clear_text_len', required=False)
-    if clear_text_len:
-      clear_text = clear_text[:int(clear_text_len)]
-  else:
-    clear_text_len = None
-  if tpm.debug_enabled():
-    print('clear text size', len(clear_text))
-  cipher_text = get_attribute(tdesc, 'cipher_text', required=False)
-  if clear_text_len:
-    cipher_text = cipher_text[:int(clear_text_len)]
-  tag = get_attribute(tdesc, 'tag', required=False)
-  aad = get_attribute(tdesc, 'aad', required=False)
-  if aad:
-    aad_len = get_attribute(tdesc, 'aad_len', required=False)
-    if aad_len:
-      aad = aad[:int(aad_len)]
-  real_cipher_text = crypto_run(node_name, ENCRYPT, key, iv,
-                                aad or '', clear_text, cipher_text + tag, tpm)
-  crypto_run(node_name, DECRYPT, key, iv, aad or '',
-             real_cipher_text[:len(real_cipher_text) - len(tag)],
-             clear_text + tag, tpm)
-  print(utils.cursor_back() + 'SUCCESS: %s' % node_name)
-
-def crypto_tests(tpm, xml_file):
-  tree = ET.parse(xml_file)
-  root = tree.getroot()
-  for child in root:
-    crypto_test(child, tpm)
diff --git a/test/tpm_test/crypto_test.xml b/test/tpm_test/crypto_test.xml
deleted file mode 100644
index 152f55c97f..0000000000
--- a/test/tpm_test/crypto_test.xml
+++ /dev/null
@@ -1,899 +0,0 @@
-<?xml version="1.0"?>
-<!--
-Copyright 2015 The Chromium OS Authors. All rights reserved.
-Use of this source code is governed by a BSD-style license that can be
-found in the LICENSE file.
-
-This file describes test vectors for various encryption schemes.
-
-Each description is encapsulated in a 'crypto_test' element. This element must
-have the name property set. The name starts witht the encryption scheme's name
-(say AES or DES), delimited by a colon, and followed by a three character
-encryption submode, if necessary (say ECB for AES).
-
-The rest of the attributes are self explanatory. The default format for the
-clear_text element is ASCII, for the rest - hex. This default could be
-overridded using the 'format' property.
-
-The ascii strings are stripped of leading and trailing whitespace and then
-joined using space as a separator. Whitespace in hes strings is ignored.
-
-Hex values are interpreted as a set of 4 byte entities in network byte order.
-Many of the crypto_test elements were borrowed from NIST test vectors.
--->
-<crypto_tests>
-  <crypto_test name="AES:ECB common">
-    <clear_text>
-      this is the text which will be encrypted if everything is going fine.
-    </clear_text>
-    <key>0123456789abcdef0123456789abcdef0123456789abcdef</key>
-    <cipher_text>
-      <!--
-	  Cipher text matches the case of the clear text padded with zeros to
-	  the nearest block size.
-      -->
-      f90fe23d ce62d9ee 57178af0 d08604c6
-      7244ec3d 871879d8 6d81313f 10bb4c66
-      9fe08dda ccb36763 bde8b464 c9a9b012
-      9ff06d09 fbaee2a4 901cfe0d f0fee26c
-      34b58f68 a9e27607 7bdd8e72 8b2b528b
-    </cipher_text>
-  </crypto_test>
-
-  <crypto_test name="AES:ECB128 1">
-    <clear_text format="hex">
-      33221100 77665544 bbaa9988 ffeeddcc
-    </clear_text>
-    <key>03020100 07060504 0b0a0908 0f0e0d0c</key>
-    <cipher_text>
-      d8e0c469 30047b6a 80b7cdd8 5ac5b470
-    </cipher_text>
-  </crypto_test>
-  <crypto_test name="AES:ECB192 1">
-    <clear_text format="hex">
-      00000000 00000000 00000000 00000000
-    </clear_text>
-    <key>
-      6e0fd215 9f647ebc b1765bd9 badae607
-      948a7c96 297f7984
-    </key>
-    <cipher_text>
-      42184e8e 3d1a594e 76086f5b 94856ff1
-    </cipher_text>
-  </crypto_test>
-  <crypto_test name="AES:ECB256 1">
-    <clear_text format="hex">
-      00000000 00000000 00000000 00000000
-    </clear_text>
-    <key>
-      00000080 00000000 00000000 00000000
-      00000000 00000000 00000000 00000000
-    </key>
-    <cipher_text>
-      cb6d5ae3 a001b219 8afabc1e 59572ba2
-    </cipher_text>
-  </crypto_test>
-  <crypto_test name="AES:ECB256 2">
-    <clear_text format="hex">
-      45249ff6 179b4fdf 7b412bad 10376ce6
-    </clear_text>
-    <key>
-      10eb3d60 be71ca15 f0ae732b 81777d85
-      072c351f d708613b a310982d f4df1409
-    </key>
-    <cipher_text>
-      7a4b3023 fff3f939 8f8d7d06 c7ec249e
-    </cipher_text>
-  </crypto_test>
-  <crypto_test name="AES:CTR128I 1">
-    <clear_text format="hex">
-      e2bec16b 969f402e 117e3de9 2a179373
-    </clear_text>
-    <key>
-      16157e2b a6d2ae28 8815f7ab 3c4fcf09
-    </key>
-    <cipher_text>
-      91614d87 26e320b6 6468ef1b ceb60d99
-    </cipher_text>
-    <iv>f3f2f1f0 f7f6f5f4 fbfaf9f8 fffefdfc</iv>
-  </crypto_test>
-
-  <crypto_test name="AES:CTR128I 2">
-    <clear_text format="hex">
-      8081582f 93b9e22f b62411a3 1cc78eac
-      43e9160a e450aeee c03fd20f 2c857832
-    </clear_text>
-    <key>
-      8c6b27c1 b3f18092 f782418c 0f52779d
-    </key>
-    <cipher_text>
-      0d61fe65 927bb9db 9f9c8cc4 6287a402
-      f530a9cf c892dec2 86cb6ae3 2b54fc89
-    </cipher_text>
-    <iv>
-      00000000 00000000 00000000 FFFFFFFF
-    </iv>
-  </crypto_test>
-
-  <crypto_test name="AES:CTR128I 3">
-    <clear_text format="hex">
-      d66dc833 7ca1d802 572c5244 a24ae3ab
-      ef87947a f917ccf8 568e4d8d 5a4c46d0
-    </clear_text>
-    <key>
-      82bee9e5 57d2cc8c fa8796d4 338eff1d
-    </key>
-    <cipher_text>
-      4ab3cfa4 2866ae63 ea4bbc19 a041774d
-      3c16e4a3 5b5589f2 ff6e2e94 6ead92ba
-    </cipher_text>
-    <iv>
-      00000000 00000000 FFFFFFFF FFFFFFFF
-    </iv>
-  </crypto_test>
-
-  <crypto_test name="AES:CTR128I 4">
-    <clear_text format="hex">
-      50ee7879 ff5eeb9b 8b9bbf8d 75d13193
-      a61b24a3 5b3cd159 1fa0290c 67693d8c
-    </clear_text>
-    <key>
-      ad9af8e4 dfca7c06 d61adf4c a5d845a3
-    </key>
-    <cipher_text>
-      123b06d0 fdfcc772 a8a96688 29f40ff2
-      0fcfa412 01fc81ec 15bde846 1ef15d21
-    </cipher_text>
-    <iv>
-      00000000 FFFFFFFF FFFFFFFF FFFFFFFF
-    </iv>
-  </crypto_test>
-
-  <crypto_test name="AES:CTR128I 5">
-    <clear_text format="hex">
-      3b0c5276 f93ae7c6 7791b673 c2af23a1
-      c907cb9b 44681b6a dce78a4c f688dcb1
-    </clear_text>
-    <key>
-      f8e5cff3 c5032a29 f1ec8fb9 d01cb31a
-    </key>
-    <cipher_text>
-      9a74141f 8f8db10e 81e6f51e 84f571a6
-      72e1d939 4b1ad600 7fd5d973 4497a688
-    </cipher_text>
-    <iv>
-      FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF
-    </iv>
-  </crypto_test>
-
-  <crypto_test name="AES:CTR256I 1">
-    <clear_text format="hex">
-      13c31e60 a5895777 04f5a7b7 28d2f3bb
-    </clear_text>
-    <key>
-      10eb3d60 be71ca15 f0ae732b 81777d85
-      072c351f d708613b a310982d f4df1409
-    </key>
-    <cipher_text>
-      e2bec16b 969f402e 117e3de9 2a179373
-    </cipher_text>
-    <iv>f3f2f1f0 f7f6f5f4 fbfaf9f8 fffefdfc</iv>
-  </crypto_test>
-
-  <crypto_test name="AES:CBC128 1">
-    <clear_text format="hex">
-      a636839ed2b0ad1abf458f93adb6d5eb
-    </clear_text>
-    <key>
-      1f5b102067bf5ed28c24733abceb8b17
-    </key>
-    <cipher_text>
-      d955527cf393f7a6a2cdec0f1692104c
-    </cipher_text>
-    <iv>
-      f67c127e03e4f4de49f690f3b953b6db
-    </iv>
-  </crypto_test>
-
-  <crypto_test name="AES:CBC128 2">
-    <clear_text format="hex">
-      da092d3ab24b2a6b585ea1cc7cd2f9f000d06d5c5169d20d02d883eda07224f5
-    </clear_text>
-    <key>
-      8587d0474afdd5fb265928fea02bce8b
-    </key>
-    <cipher_text>
-      2f039d2e6324fde3778a77f011b975d6e0ac68ad12edee19308536028e7d6e0e
-    </cipher_text>
-    <iv>
-      fd450534ab529f92567ab5c05f221ce2
-    </iv>
-  </crypto_test>
-
-  <crypto_test name="AES:CBC192 1">
-    <clear_text format="hex">
-      9b4d5e71fed8bf8650ac1f4165a24dbf
-    </clear_text>
-    <key>
-      1ccc3bc8256027789502909f6633488906d18472dc5668de
-    </key>
-    <cipher_text>
-      cb0d808aecbf13aadbf9445ef31b211b
-    </cipher_text>
-    <iv>
-      b0aa195cfdb8128cd37006f7be857d2a
-    </iv>
-  </crypto_test>
-
-  <crypto_test name="AES:CBC192 2">
-    <clear_text format="hex">
-      796a503d47ce4f508c781b05cabdf090b10bbd35eb8f266d6aefdf9c2557d1dd
-    </clear_text>
-    <key>
-      f24f6e0e8de446d81be04e8535cba109af54814946a58281
-    </key>
-    <cipher_text>
-      2da16ace5b1928f892816c4564a2156110eb6427068a8b84b91d3f7e2e8ba509
-    </cipher_text>
-    <iv>
-      72cc0e1acd9c45d80ed3aa24748a2d8b
-    </iv>
-  </crypto_test>
-
-  <crypto_test name="AES:CBC256 1">
-    <clear_text format="hex">
-      aac63e7086300c38038512e8897c22d2
-    </clear_text>
-    <key>
-      a0af53a1b0d721ab33888afab77c4629332dd3a6c8e6025da3a5227289dec227
-    </key>
-    <cipher_text>
-      4b8dd68ed2ddac5a738c0ed8e881574d
-    </cipher_text>
-    <iv>
-      187a3ea27c383d45b864036adaa27a26
-    </iv>
-  </crypto_test>
-
-  <crypto_test name="AES:CBC256 2">
-    <clear_text format="hex">
-      02c6dc282c745fe663457d93d3dc6b8259ab14bf7c56ef1ec1ac59c9a650804d
-    </clear_text>
-    <key>
-      5c01c80bc7206471558c157b5f0c053d9d77a0f3ea81059a1384dc9963e7fa67
-    </key>
-    <cipher_text>
-      de4838d472a8bf060378659f073a640d4978a9602e110eb02f70dade4d49e82b
-    </cipher_text>
-    <iv>
-      2dbb1d53de16d52185af3828884a61b3
-    </iv>
-  </crypto_test>
-
-  <crypto_test name="AES:CFB128 1">
-    <clear_text format="hex">
-      c27e8ebe08
-    </clear_text>
-    <key>
-      21df77a9938963824ad4fb63699b9e10
-    </key>
-    <cipher_text>
-      93541291b3
-    </cipher_text>
-    <iv>
-      5b906ff8038ecdf186461cde68ceb87d
-    </iv>
-  </crypto_test>
-
-  <crypto_test name="AES:CFB128 2">
-    <clear_text format="hex">
-      1ba5fec5c8ca5f28a79ee5f531d708c2
-    </clear_text>
-    <key>
-      db5331b06fae350196419746be3c8a99
-    </key>
-    <cipher_text>
-      a44756b5f721ee427f2a46e53ff4d1f5
-    </cipher_text>
-    <iv>
-      f43f8a8fe7db8f22f3627d7d594ead2f
-    </iv>
-  </crypto_test>
-
-  <crypto_test name="AES:CFB128 3">
-    <clear_text format="hex">
-      8395cf5fa9dc4693d0489ed99ed3d79e4117441110
-    </clear_text>
-    <key>
-      c51e8b5aaac64563fdd3edf3756f4bae
-    </key>
-    <cipher_text>
-      229f61813f1d51524a11c17075a7999745055b3011
-    </cipher_text>
-    <iv>
-      d4e2873e252d374f3ab8bee783e33056
-    </iv>
-  </crypto_test>
-
-  <crypto_test name="AES:CFB128 4">
-    <clear_text format="hex">
-      a35814e166659c2fd82894bdccde6f6371025b213bde35920423a7223a09eca3
-    </clear_text>
-    <key>
-      549ab2663df248cd6a971ea07bc4d7b1
-    </key>
-    <cipher_text>
-      40cf3a37ca6db39340f1004a57dda9ed3d0629cc93e4facf143c62e02246d0e4
-    </cipher_text>
-    <iv>
-      8a69c1cf5f9611c00b54478e8a27558b
-    </iv>
-  </crypto_test>
-
-  <crypto_test name="AES:CFB192 1">
-    <clear_text format="hex">
-      86c4803c42
-    </clear_text>
-    <key>
-      746831e7e595aa3fddcbedc1ae26f94bfce4ee40f3e1e980
-    </key>
-    <cipher_text>
-      1856d5a500
-    </cipher_text>
-    <iv>
-      01039108067aaa1d4a5047e15f52a9a3
-    </iv>
-  </crypto_test>
-
-  <crypto_test name="AES:CFB192 2">
-    <clear_text format="hex">
-      369a7f259cec0ee6cff199b5098dc0ac
-    </clear_text>
-    <key>
-      6a924856035968f0a1f99e098573085530af14165eb41c01
-    </key>
-    <cipher_text>
-      49d28326ac3ecabe84b8658ed267beb7
-    </cipher_text>
-    <iv>
-      944506624e812e1abd7eb0ab7fa08b05
-    </iv>
-  </crypto_test>
-
-  <crypto_test name="AES:CFB192 3">
-    <clear_text format="hex">
-      7677dda1638143702f960d314c8b42e9ba012528d9
-    </clear_text>
-    <key>
-      a5f67cbae2b8fdd4ade986274787e74b0c943c4bb3f8ebec
-    </key>
-    <cipher_text>
-      4729f94311972a541de3a0c6a3808e582059db884f
-    </cipher_text>
-    <iv>
-      511d4661e60516891d167322417d565b
-    </iv>
-  </crypto_test>
-
-  <crypto_test name="AES:CFB192 4">
-    <clear_text format="hex">
-      2ddc71dd68cd0b01a350180216d1d4de32b620e83c77a96decc5c45b571338ab
-    </clear_text>
-    <key>
-      f929b89472bdffa025a3a060e068734cd018e6a28071e48b
-    </key>
-    <cipher_text>
-      21e716bd4ebc84627786d1380df8499502dc1c028361442ffbe912fd7052d197
-    </cipher_text>
-    <iv>
-      23975ea307cc5204f29c235b61687ec1
-    </iv>
-  </crypto_test>
-
-  <crypto_test name="AES:CFB256 1">
-    <clear_text format="hex">
-      d1657ed2b3
-    </clear_text>
-    <key>
-      cc0e6b12df0610b91f6d33ee1f712d87ffc798c157cd11e2f52c9a50bf093371
-    </key>
-    <cipher_text>
-      3319824a4f
-    </cipher_text>
-    <iv>
-      b123401360708c4aa6f11f5f04e191e1
-    </iv>
-  </crypto_test>
-
-  <crypto_test name="AES:CFB256 2">
-    <clear_text format="hex">
-      7933ff6df6c98722419edcd3011a0b6b
-    </clear_text>
-    <key>
-      f42a206acd1c7064017cc869eed6a2807ac57e5f25edc220832e1c13daf113e1
-    </key>
-    <cipher_text>
-      ba6b4bd81d0e6926ed83ae684c2dd829
-    </cipher_text>
-    <iv>
-      79d679c00af714f943a1f649217d34b4
-    </iv>
-  </crypto_test>
-
-  <crypto_test name="AES:CFB256 3">
-    <clear_text format="hex">
-      913091426fa791d9f7b822e5a5e360ca7d575943ea
-    </clear_text>
-    <key>
-      3c65a7d551d48c9ee6e37cb3f8d1f31cee6c1369e2068843905249346bbca0fa
-    </key>
-    <cipher_text>
-      fff98201e5fa0b08d818da9a614775c4b1e9d399a8
-    </cipher_text>
-    <iv>
-      70998e67f207486e575b640cfd8ae59f
-    </iv>
-  </crypto_test>
-
-  <crypto_test name="AES:CFB256 4">
-    <clear_text format="hex">
-      59ee972cefa6d30c2c3c0c6c73c189066ced4cc0d59afd0728087223d3724943
-    </clear_text>
-    <key>
-      2826c55b27fdf41c6890a03d4113bb57ae0abb75c5b460e276edc148d3f96dc7
-    </key>
-    <cipher_text>
-      e17c9f488be47bcc54ea366704b9a0941e6e681d8f8445bec6c358038b5169b2
-    </cipher_text>
-    <iv>
-      c3f2173953f34012e82a3f1a6adf9b48
-    </iv>
-  </crypto_test>
-
-  <crypto_test name="AES:OFB128 1">
-    <clear_text format="hex">
-      c69758215b
-    </clear_text>
-    <key>
-      30499479a11899b1b6c5293528809bd3
-    </key>
-    <cipher_text>
-      32fab4a0ac
-    </cipher_text>
-    <iv>
-      36d1827861331652397de67d24b9f6fa
-    </iv>
-  </crypto_test>
-
-  <crypto_test name="AES:OFB128 2">
-    <clear_text format="hex">
-      41efde8ba6e71b9b034234cb7a99b47c
-    </clear_text>
-    <key>
-      5b966ff25d38416a701a27f686a915cf
-    </key>
-    <cipher_text>
-      b752d8e79190e4b8491268f1456a9511
-    </cipher_text>
-    <iv>
-      38acff7be2fdffc9314dfe410b24b3a2
-    </iv>
-  </crypto_test>
-
-  <crypto_test name="AES:OFB128 3">
-    <clear_text format="hex">
-      49c74e50fb982a979eaf39ac2a558be1a9e5488e4b
-    </clear_text>
-    <key>
-      49385d8eb6ea0e63cb32c9383d5c3cb6
-    </key>
-    <cipher_text>
-      6b4f54782fae0cc337b9f806d459df35191fad0b80
-    </cipher_text>
-    <iv>
-      b417edffedd3fc706b5b0fea19ba409b
-    </iv>
-  </crypto_test>
-
-  <crypto_test name="AES:OFB128 4">
-    <clear_text format="hex">
-      557c59c190a96492e7e3ce9a7c06a8e33931b1ed02002cb8727c4cc93ee7fcc0
-    </clear_text>
-    <key>
-      f458f61d05a9fff961c38cc2edbf02dc
-    </key>
-    <cipher_text>
-      778ed8ee5ecb0d41bafea9fbfa8ab5f1f4ab34eb176e9aabab0bc86f33370233
-    </cipher_text>
-    <iv>
-      90dfffe4e188f48eced3b2c39490530f
-    </iv>
-  </crypto_test>
-
-  <crypto_test name="AES:OFB192 1">
-    <clear_text format="hex">
-      bb45f365fd
-    </clear_text>
-    <key>
-      37fa0d1f182f35cb59a11df8737a0c9d0b56801372d2f7ec
-    </key>
-    <cipher_text>
-      3e84a0d15c
-    </cipher_text>
-    <iv>
-      b3343ff1fdef4f95944b088e218e1b72
-    </iv>
-  </crypto_test>
-
-  <crypto_test name="AES:OFB192 2">
-    <clear_text format="hex">
-      44bd7e4e005bc3c01f3f053c7e0589d7
-    </clear_text>
-    <key>
-      529b351bbe630dbf2d8f0c70331d57848cb773a7b70fe6cb
-    </key>
-    <cipher_text>
-      ac3dc2b0692da4604ac51a7136111bba
-    </cipher_text>
-    <iv>
-      9fa0ccfcd6368e9fa3ff25137c1a8112
-    </iv>
-  </crypto_test>
-
-  <crypto_test name="AES:OFB192 3">
-    <clear_text format="hex">
-      0ff5e3ec8a978b623d72cdaf0ef94154b184161d74
-    </clear_text>
-    <key>
-      165a62acbf5ec4a01405b4a2f90fa50575327ceb8f70eb78
-    </key>
-    <cipher_text>
-      2e70ae41889b5d3074221fd830fc1c4774a3c53233
-    </cipher_text>
-    <iv>
-      aa4a6b2c9682c261651836c9205efabe
-    </iv>
-  </crypto_test>
-
-  <crypto_test name="AES:OFB192 4">
-    <clear_text format="hex">
-      4d67b3b279c79349f4ca2cea233a2c982739ee38f40ffd1a2c65c0a15b23b0a0
-    </clear_text>
-    <key>
-      fe9a1fb428ac71ad58a5d701701db9cb385c3f366e0dc4cd
-    </key>
-    <cipher_text>
-      c082c1156c2aaab98094c4a097f1e2d1c986062ce89e86c79420512ad313121d
-    </cipher_text>
-    <iv>
-      db72feeeda791cfcb96b6ee6b724f986
-    </iv>
-  </crypto_test>
-
-  <crypto_test name="AES:OFB256 1">
-    <clear_text format="hex">
-      732b346426
-    </clear_text>
-    <key>
-      2d6f926b2954d80e58e00145a74583dcce46efc6167d7d00b7c01ab73ffa83da
-    </key>
-    <cipher_text>
-      9626f27f3d
-    </cipher_text>
-    <iv>
-      d987a6c6956a951218959da30e2a2169
-    </iv>
-  </crypto_test>
-
-  <crypto_test name="AES:OFB256 2">
-    <clear_text format="hex">
-      71fd48054f6db38d33c7314c62b362c2
-    </clear_text>
-    <key>
-      b8eee3cd1a391b59d2894dd47faa4a8266c814e95a460184b2361efd8b386a7a
-    </key>
-    <cipher_text>
-      d221511b5691c96a03c8b0729f8fc944
-    </cipher_text>
-    <iv>
-      e9404d883cb1fbfe4a1ed33193f9bbcf
-    </iv>
-  </crypto_test>
-
-  <crypto_test name="AES:OFB256 3">
-    <clear_text format="hex">
-      4990a1bf14a3c56b62c32c670dbdb0d1bc2ce052d8
-    </clear_text>
-    <key>
-      8b04f99cf4a659490673fce9e81938895210ff98eb74235c22d5fdcc70f61d96
-    </key>
-    <cipher_text>
-      1246ec884679c1ddad53052a2daeb05f952e54a2d2
-    </cipher_text>
-    <iv>
-      e401e83a2cf2ece54d4b15ed2805d71d
-    </iv>
-  </crypto_test>
-
-  <crypto_test name="AES:OFB256 4">
-    <clear_text format="hex">
-      f9e4439e4eb67cce27f46417d74bcbb4d38040ac87e9ccbcfa2ad9f6ca612686
-    </clear_text>
-    <key>
-      5f6bc2dd955f56882c890b619769114796969b7162e1bbcb1260d25f78aae0bb
-    </key>
-    <cipher_text>
-      af05d2d2be7aeea3208e56741144f41369c98691c6e60f3ad2160bcc238d9099
-    </cipher_text>
-    <iv>
-      b11bf6f21675a8799172a8f52ee927a1
-    </iv>
-  </crypto_test>
-
-  <crypto_test name="AES:GCM128 1">
-    <key>
-      53c372160082fa7a468a6b4c26d0f0f6
-    </key>
-    <iv>
-      05
-    </iv>
-    <tag>
-      21d72a8e745f45f9313db5d88e7ef241
-    </tag>
-  </crypto_test>
-
-  <crypto_test name="AES:GCM128 2">
-    <key>
-      74b5dd7fd041c2533aedfb3e1c374ec4
-    </key>
-    <iv>
-      3f3a28eee37555c78748fd3e
-    </iv>
-    <tag>
-      f91d6db396e5d5b97f8b3ef8b31c9752
-    </tag>
-    <clear_text format="hex">
-      b442ded5256c646129bd875ca2b9d362
-    </clear_text>
-    <cipher_text>
-      a5a4cd2c1eb95c410f2a5c13fdb2c978
-    </cipher_text>
-  </crypto_test>
-
-  <crypto_test name="AES:GCM128 3">
-    <key>
-      5571dcfeb2002d197598dd3cbaebb90d
-    </key>
-    <iv>
-      f5746ba756171a5cb13883a0
-    </iv>
-    <tag>
-      55c43dd28798d4ceeae817c78429ecbe
-    </tag>
-    <aad>
-      c406d22a557e6e173688a02afa16688859e777fa
-    </aad>
-    <clear_text format="hex">
-      5b433168f1da578848b113c5b5130d8290c42ca7989aa7bdd820f5a6d1393c76
-    </clear_text>
-    <cipher_text>
-      0538821592a189da6f1dfc3b564d78878b12d1badedbff4da52fbbef685ec362
-    </cipher_text>
-  </crypto_test>
-
-  <crypto_test name="AES:GCM128 4">
-    <key>
-      7063be77e2c4718979cbd140eb7fd7e8
-    </key>
-    <iv>
-      190fe0e001bad7fef397a736
-    </iv>
-    <tag>
-      8dcc9f2093ed753666719c8e46d99d70
-    </tag>
-    <aad>
-      1dec437a785a0a9c3365b1a0ab3c21a6
-    </aad>
-  </crypto_test>
-
-  <crypto_test name="AES:GCM128 5">
-    <key>
-      79e8e399576e683ec585821d2b5ef764
-    </key>
-    <iv>
-      b80addc2a86ada68230d9cad
-    </iv>
-    <tag>
-      10ba4f3f341faf0eaaadbab0855d99e9
-    </tag>
-    <aad>
-      2de468b6a84c444ed9fd3cb2d5ed9f5a21a58a17b0904814f53c73936c5222cf47ee17599a8041658c7a86c6fc099339
-    </aad>
-  </crypto_test>
-
-  <crypto_test name="AES:GCM128 6">
-    <key>
-      8824a2d45c1dddf8d6a7196c4c9617ca
-    </key>
-    <iv>
-      7f83d5f3041aac22d5d1e025
-    </iv>
-    <tag>
-      f9ac3ef273f8cdd186c526779c6e8248
-    </tag>
-    <aad>
-      24d4c5f1c6963fb88cb28cad470ed2a05a3b025e
-    </aad>
-    <clear_text format="hex">
-      6a01437b97648916e67b45fb2241a5d2
-    </clear_text>
-    <cipher_text>
-      ee67bdc2ac5ce9f56eb0e327a8d03130
-    </cipher_text>
-  </crypto_test>
-
-  <crypto_test name="AES:GCM128 7">
-    <key>
-      635c7cbd562b54b771be0ea088156a33
-    </key>
-    <iv>
-      231f72878e3c9cbabc1a57a5
-    </iv>
-    <tag>
-      2267b59c2e250b0d46ff7bb9f80fb0e4
-    </tag>
-    <aad>
-      7580eca60e37d3a0188959b7483eb9f36251474499b89749a9a67fa84e849f93b7a88a003b4c9f0e28d3191ae743f56bcbfe7b12a517ada1ccfc53ecacecfa266953c7c47daa8e4963ef6a702709004dbae4119b5e3e996c0000d99e
-    </aad>
-    <aad_len>
-      90
-    </aad_len>
-    <clear_text format="hex">
-      bbdd15de6121201ef69aa7e8f3c65aa5
-    </clear_text>
-    <cipher_text>
-      c028eb4162d7e4fe612397de80bc63c8
-    </cipher_text>,
-    </crypto_test>
-
-  <crypto_test name="AES:GCM128 8">
-    <key>
-      23deefdff02b12c689b50a37734b800e
-    </key>
-    <iv>
-      02a8d6920f679099e279de16
-    </iv>
-    <tag>
-      9982a39d07c5cd680dc3d1941545cd41
-    </tag>
-    <aad>
-      786db1a2c1e61d250e35ce9142f25e5c
-    </aad>
-    <clear_text format="hex">
-      8c0a266478e97d2821756ce9000000d0
-    </clear_text>
-    <clear_text_len>
-      13
-    </clear_text_len>
-    <cipher_text>
-      94de78bf177c848ab4d44936000000d0
-    </cipher_text>
-  </crypto_test>
-
-  <crypto_test name="AES:GCM128 9">
-    <key>
-      dbb8d3cbce11fbfce60657341a8873cd
-    </key>
-    <iv>
-      68bb62dc5d9aecd041679d75
-    </iv>
-    <tag>
-      b2215a420c5890ea03349188b54b912b
-    </tag>
-    <aad>
-      61b64409f39462fe08bb2ac959b2c17e4edc32b068285f0c636ebe1c478f17c25af32643c280cad3e785348ec852b2e5
-    </aad>
-    <aad_len>
-      48
-    </aad_len>
-    <clear_text format="hex">
-      f53bf8855bd5df982adebfc800000064
-    </clear_text>
-    <clear_text_len>
-      13
-    </clear_text_len>
-    <cipher_text>
-      3b6b6f20ecdf32b040839fd3000000b1
-    </cipher_text>
-  </crypto_test>
-
-  <crypto_test name="AES:GCM128 10">
-    <key>
-      1007719909c0ab5969bdf2e438b39d86
-    </key>
-    <iv>
-      5ea9a9079c1e82a35132c613
-    </iv>
-    <tag>
-      11d970781a81547ff1706934410c09de
-    </tag>
-    <clear_text format="hex">
-      50c34bf56f4fed1fa85efb6d0bdf060182e636d85cb72562e8f622028359b359
-    </clear_text>
-    <cipher_text>
-      59c156056cf34ef8452b60b10920b1261b6175c7c04db6ff9792cad9016a2ccd
-    </cipher_text>
-    </crypto_test>
-
-  <crypto_test name="AES:GCM128 11">
-    <key>
-      a17cbf8fdd25d52f58621ee9c251fe73
-    </key>
-    <iv>
-      51ea0b20a190977b5eafadcf
-    </iv>
-    <tag>
-      7407867cb93283f8bd6bcea727a77202
-    </tag>
-    <aad>
-      7fc014a4ec0be6e29e40cc9c6f9c899ebb8005e661c807262385f0f71bda9ce61d713a9c09359c1dc9e471176d99b9502e4fd00a10b3d1002a545358ff9fe0960fc82efc2887f88caef094f5a6984fb18b4e23882703f7fb000064b3
-    </aad>
-    <aad_len>
-      90
-    </aad_len>
-    <clear_text format="hex">
-      27e6d33963494b7c42160d840aaefae697dae25b554e1cf602ce57bbc4d40319
-    </clear_text>
-    <cipher_text>
-      f78e67fe95ac696f6d3b55db7aa0d5ad51e1c89da39f6afe1662cda16878b836
-    </cipher_text>
-  </crypto_test>
-
-  <crypto_test name="AES:GCM128 12">
-    <key>
-      bb5315b6b9954885d01c75298403f8c5
-    </key>
-    <iv>
-      99f963885de564ae5774bd0b
-    </iv>
-    <tag>
-      4a5f9b5dc6c16898d86fbd9c4013f051
-    </tag>
-    <aad>
-      f2b514d9e58cb0d1b39ca53e45725810
-    </aad>
-    <clear_text format="hex">
-      32111b9beac4d01712cf4379adc6693c36973c2e75c9518c55d1454186eee1ddffcac840975c7af1136ad237f34bee7e006d0969
-    </clear_text>
-    <clear_text_len>
-      51
-    </clear_text_len>
-    <cipher_text>
-      63b4faac80258a2b3df11251bc82e085bd49dc89a84f169242d2daa2f2b2a1c3df2f6f695f0279f5a96e143f7de4a37d00654bc3
-    </cipher_text>
-  </crypto_test>
-
-  <crypto_test name="AES:GCM128 13">
-    <key>
-      2862503caa50f4680c99280936ebe115
-    </key>
-    <iv>
-      90521d81e7578d76c7b67bd8
-    </iv>
-    <tag>
-      fc5e9bbdcd0880a47d4f3a974438722c
-    </tag>
-    <aad>
-      e0c7e2da2bfdd3a319ca4ec0a07851b184cfb503c2280c890ff215a67f42db8a128c69707887efb2fb93110c7416cdb8
-    </aad>
-    <clear_text format="hex">
-      f8a8d0ed19e93328bfe20f744acfde9edc726cc8ef0c4989aa83697b85fc99af7dc85c6c7c8af96327f31b86a86dea1f00ab156a
-    </clear_text>
-    <clear_text_len>
-      51
-    </clear_text_len>
-    <cipher_text>
-      b02514a54b3b8d6005ecd446f0da1dca8920dd2bec5405ae841c2afbdc823dc6abb9dd71490b1f1b7cd22adee773512b00a60a00
-    </cipher_text>
-  </crypto_test>
-</crypto_tests>
diff --git a/test/tpm_test/drbg_test.py b/test/tpm_test/drbg_test.py
deleted file mode 100644
index 097a222923..0000000000
--- a/test/tpm_test/drbg_test.py
+++ /dev/null
@@ -1,108 +0,0 @@
-#!/usr/bin/env python2
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-"""Module for testing hash functions using extended commands."""
-
-from __future__ import print_function
-
-from binascii import a2b_hex as a2b
-from struct import pack
-
-import subcmd
-import utils
-
-
-# A standard empty response to DRBG extended commands.
-EMPTY_DRBG_RESPONSE = ''.join('%c' % x for x in (0x80, 0x01,
-                                                 0x00, 0x00, 0x00, 0x0c,
-                                                 0x00, 0x00, 0x00, 0x00,
-                                                 0x00, subcmd.DRBG_TEST))
-
-DRBG_INIT = 0
-DRBG_RESEED = 1
-DRBG_GENERATE = 2
-
-test_inputs = (
-  (DRBG_INIT,
-   ('C40894D0C37712140924115BF8A3110C7258532365BB598F81B127A5E4CB8EB0',
-    'FBB1EDAF92D0C2699F5C0A7418D308B09AC679FFBB0D8918C8E62D35091DD2B9',
-    '2B18535D739F7E75AF4FF0C0C713DD4C9B0A6803D2E0DB2BDE3C4F3650ABF750')),
-  (DRBG_RESEED,
-   ('4D58A621857706450338CCA8A1AF5CD2BD9305F3475CF1A8752518DD8E8267B6',
-    '0153A0A1D7487E2EE9915E2CAA8488F97239C67595F418D9503D0B11CC07044E', '')),
-  (DRBG_GENERATE,
-   ('39AE66C2939D1D73EF21AE22988B04CC7E8EA2D790C75E1FC6ACC7FEEEF90F98',
-    '')),
-  (DRBG_GENERATE,
-   ('B8031829E07B09EEEADEBA149D0AC9F08B110197CD8BBDDC32744BCD66FCF3C4',
-    'A1307377F6B472661BC3C6D44C035FB20A13CCB04D6601B2425FC4DDA3B6D7DF')),
-  (DRBG_INIT,
-   ('3A2D261884010CCB4C2C4D7B323CCB7BD4515089BEB749C565A7492710922164',
-    '9E4D22471A4546F516099DD4D737967562D1BB77D774B67B7FE4ED893AE336CF',
-    '5837CAA74345CC2D316555EF820E9F3B0FD454D8C5B7BDE68E4A176D52EE7D1C')),
-  (DRBG_GENERATE,
-   ('4D87985505D779F1AD98455E04199FE8F2FE8E550E6FEB1D26177A2C5B744B9F',
-    '')),
-  (DRBG_GENERATE,
-   ('85D011A3B36AC6B25A792F213A1C22C80BFD1C5B47BCA04CD0D9834BB466447B',
-    'B03863C42C9396B4936D83A551871A424C5A8EDBDC9D1E0E8E89710D58B5CA1E')),
-
-)
-
-_DRBG_INIT_FORMAT = '{op:c}{p0l:s}{p0}{p1l:s}{p1}{p2l:s}{p2}'
-def _drbg_init_cmd(op, entropy, nonce, perso):
-  return _DRBG_INIT_FORMAT.format(op=op,
-                                  p0l=pack('>H', len(entropy)), p0=entropy,
-                                  p1l=pack('>H', len(nonce)), p1=nonce,
-                                  p2l=pack('>H', len(perso)), p2=perso)
-
-_DRBG_GEN_FORMAT = '{op:c}{p0l:s}{p0}{p1l:s}'
-
-def _drbg_gen_cmd(inp, out):
-  outlen = len(out)
-  if outlen == 0:
-    outlen = 32 # if we don't care about output value, still need to have it
-  return _DRBG_GEN_FORMAT.format(op=DRBG_GENERATE,
-                                 p0l=pack('>H', len(inp)), p0=inp,
-                                 p1l=pack('>H', outlen))
-
-
-def drbg_test(tpm):
-  """Runs DRBG test case.
-
-  Args:
-    tpm: a tpm object used to communicate with the device
-
-  Raises:
-    subcmd.TpmTestError: on unexpected target responses
-  """
-
-  for test in test_inputs:
-    drbg_op, drbg_params = test
-    if drbg_op == DRBG_INIT:
-      entropy, nonce, perso = drbg_params
-      cmd = _drbg_init_cmd(drbg_op, a2b(entropy), a2b(nonce), a2b(perso))
-      response = tpm.command(tpm.wrap_ext_command(subcmd.DRBG_TEST, cmd))
-      if response != EMPTY_DRBG_RESPONSE:
-        raise subcmd.TpmTestError("Unexpected response to DRBG_INIT: %s" %
-                        (utils.hex_dump(wrapped_response)))
-    elif drbg_op == DRBG_RESEED:
-      entropy, inp1, inp2 = drbg_params
-      cmd = _drbg_init_cmd(drbg_op, a2b(entropy), a2b(inp1), a2b(inp2))
-      response = tpm.command(tpm.wrap_ext_command(subcmd.DRBG_TEST, cmd))
-      if response != EMPTY_DRBG_RESPONSE:
-        raise subcmd.TpmTestError("Unexpected response to DRBG_RESEED: %s" %
-                        (utils.hex_dump(wrapped_response)))
-    elif drbg_op == DRBG_GENERATE:
-      inp, expected = drbg_params
-      cmd = _drbg_gen_cmd(a2b(inp), a2b(expected))
-      response = tpm.command(tpm.wrap_ext_command(subcmd.DRBG_TEST, cmd))
-      if expected != '':
-        result = response[12:]
-        if a2b(expected) != result:
-           raise subcmd.TpmTestError('error:\nexpected %s\nreceived %s' %
-                                     (utils.hex_dump(a2b(expected)),
-                                      utils.hex_dump(result)))
-  print('%sSUCCESS: %s' % (utils.cursor_back(), 'DRBG test'))
diff --git a/test/tpm_test/ecc_test.py b/test/tpm_test/ecc_test.py
deleted file mode 100644
index 155a497b98..0000000000
--- a/test/tpm_test/ecc_test.py
+++ /dev/null
@@ -1,165 +0,0 @@
-#!/usr/bin/env python2
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-"""Module for testing ecc functions using extended commands."""
-import binascii
-import hashlib
-import os
-import struct
-
-import subcmd
-import utils
-
-_ECC_OPCODES = {
-  'SIGN': 0x00,
-  'VERIFY': 0x01,
-  'KEYGEN': 0x02,
-  'KEYDERIVE': 0x03,
-}
-
-_ECC_CURVES = {
-  'NIST-P256': 0x03,
-}
-
-# TPM2 signature codes.
-_SIGN_MODE = {
-  'NONE': 0x00,
-  'ECDSA': 0x18,
-  # TODO(ngm): add support for SCHNORR.
-  # 'SCHNORR': 0x1c
-}
-
-# TPM2 ALG codes.
-_HASH = {
-  'NONE': 0x00,
-  'SHA1': 0x04,
-  'SHA256': 0x0B
-}
-
-_HASH_FUNC = {
-    'NIST-P256': hashlib.sha256
-}
-
-# Command format.
-#
-#   0x00 OP
-#   0x00 CURVE_ID
-#   0x00 SIGN_MODE
-#   0x00 HASHING
-#   0x00 MSB IN LEN
-#   0x00 LSB IN LEN
-#   .... IN
-#   0x00 MSB DIGEST LEN
-#   0x00 LSB DIGEST LEN
-#   .... DIGEST
-#
-_ECC_CMD_FORMAT = '{o:c}{c:c}{s:c}{h:c}{ml:s}{msg}{dl:s}{dig}'
-
-
-def _sign_cmd(curve_id, hash_func, sign_mode, msg):
-  op = _ECC_OPCODES['SIGN']
-  digest = hash_func(msg).digest()
-  digest_len = len(digest)
-  return _ECC_CMD_FORMAT.format(o=op, c=curve_id, s=sign_mode, h=_HASH['NONE'],
-                               ml=struct.pack('>H', 0), msg='',
-                               dl=struct.pack('>H', digest_len), dig=digest)
-
-
-def _verify_cmd(curve_id, hash_func, sign_mode, msg, sig):
-  op = _ECC_OPCODES['VERIFY']
-  sig_len = len(sig)
-  digest = hash_func(msg).digest()
-  digest_len = len(digest)
-  return _ECC_CMD_FORMAT.format(o=op, c=curve_id, s=sign_mode, h=_HASH['NONE'],
-                               ml=struct.pack('>H', sig_len), msg=sig,
-                               dl=struct.pack('>H', digest_len), dig=digest)
-
-
-def _keygen_cmd(curve_id):
-  op = _ECC_OPCODES['KEYGEN']
-  return _ECC_CMD_FORMAT.format(o=op, c=curve_id, s=_SIGN_MODE['NONE'],
-                               h=_HASH['NONE'], ml=struct.pack('>H', 0), msg='',
-                               dl=struct.pack('>H', 0), dig='')
-
-
-def _keyderive_cmd(curve_id, seed):
-  op = _ECC_OPCODES['KEYDERIVE']
-  seed_len = len(seed)
-  return _ECC_CMD_FORMAT.format(o=op, c=curve_id, s=_SIGN_MODE['NONE'],
-                               h=_HASH['NONE'], ml=struct.pack('>H', seed_len),
-                               msg=seed, dl=struct.pack('>H', 0), dig='')
-
-
-_SIGN_INPUTS = (
-  ('NIST-P256', 'ECDSA'),
-)
-
-
-_KEYGEN_INPUTS = (
-  ('NIST-P256',),
-)
-
-
-_KEYDERIVE_INPUTS = (
-  # Curve-id, random seed size.
-  ('NIST-P256', 32),
-)
-
-
-def _sign_test(tpm):
-  msg = 'Hello CR50'
-
-  for data in _SIGN_INPUTS:
-    curve_id, sign_mode = data
-    test_name = 'ECC-SIGN:%s:%s' % data
-    cmd = _sign_cmd(_ECC_CURVES[curve_id], _HASH_FUNC[curve_id],
-                    _SIGN_MODE[sign_mode], msg)
-    wrapped_response = tpm.command(tpm.wrap_ext_command(subcmd.ECC, cmd))
-    signature = tpm.unwrap_ext_response(subcmd.ECC, wrapped_response)
-
-    cmd = _verify_cmd(_ECC_CURVES[curve_id], _HASH_FUNC[curve_id],
-                      _SIGN_MODE[sign_mode], msg, signature)
-    wrapped_response = tpm.command(tpm.wrap_ext_command(subcmd.ECC, cmd))
-    verified = tpm.unwrap_ext_response(subcmd.ECC, wrapped_response)
-    expected = '\x01'
-    if verified != expected:
-      raise subcmd.TpmTestError('%s error:%s:%s' % (
-        test_name, utils.hex_dump(verified), utils.hex_dump(expected)))
-    print('%sSUCCESS: %s' % (utils.cursor_back(), test_name))
-
-
-def _keygen_test(tpm):
-  for data in _KEYGEN_INPUTS:
-    curve_id, = data
-    test_name = 'ECC-KEYGEN:%s' % data
-    cmd = _keygen_cmd(_ECC_CURVES[curve_id])
-    wrapped_response = tpm.command(tpm.wrap_ext_command(subcmd.ECC, cmd))
-    valid = tpm.unwrap_ext_response(subcmd.ECC, wrapped_response)
-    expected = '\x01'
-    if valid != expected:
-      raise subcmd.TpmTestError('%s error:%s:%s' % (
-        test_name, utils.hex_dump(valid), utils.hex_dump(expected)))
-    print('%sSUCCESS: %s' % (utils.cursor_back(), test_name))
-
-
-def _keyderive_test(tpm):
-  for data in _KEYDERIVE_INPUTS:
-    curve_id, seed_bytes = data
-    seed = os.urandom(seed_bytes)
-    test_name = 'ECC-KEYDERIVE:%s' % data[0]
-    cmd = _keyderive_cmd(_ECC_CURVES[curve_id], seed)
-    wrapped_response = tpm.command(tpm.wrap_ext_command(subcmd.ECC, cmd))
-    valid = tpm.unwrap_ext_response(subcmd.ECC, wrapped_response)
-    expected = '\x01'
-    if valid != expected:
-      raise subcmd.TpmTestError('%s error:%s:%s' % (
-        test_name, utils.hex_dump(valid), utils.hex_dump(expected)))
-    print('%sSUCCESS: %s' % (utils.cursor_back(), test_name))
-
-
-def ecc_test(tpm):
-  _sign_test(tpm)
-  _keygen_test(tpm)
-  _keyderive_test(tpm)
diff --git a/test/tpm_test/ecies_test.py b/test/tpm_test/ecies_test.py
deleted file mode 100644
index 96620c14b5..0000000000
--- a/test/tpm_test/ecies_test.py
+++ /dev/null
@@ -1,233 +0,0 @@
-#!/usr/bin/env python2
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-"""Module for testing ECIES using extended commands."""
-from binascii import b2a_hex as b2a
-from binascii import a2b_hex as a2b
-from struct import pack
-
-import subcmd
-import utils
-
-_ECIES_OPCODES = {
-  'ENCRYPT': 0x00,
-  'DECRYPT': 0x01,
-}
-
-#
-# Command format.
-#
-# WIDTH	        FIELD
-# 1             OP
-# 1             MSB IN LEN
-# 1             LSB IN LEN
-# IN_LEN        IN
-# 1             MSB AUTH_DATA LEN
-# 1             LSB AUTH_DATA LEN
-# 16            IV
-# 1             MSB PUB_X LEN
-# 1             LSB PUB_X LEN
-# PUB_X_LEN     PUB_X
-# 1             MSB PUB_Y LEN
-# 1             LSB PUB_Y LEN
-# PUB_Y_LEN     PUB_Y
-# 1             MSB SALT LEN
-# 1             LSB SALT LEN
-# SALT_LEN      SALT
-# 1             MSB INFO LEN
-# 1             LSB INFO LEN
-# INFO_LEN      INFO
-#
-_ECIES_CMD_FORMAT = '{o:c}{inl:s}{input}{al:s}{iv}{xl:s}{x}{yl:s}{y}{sl:s}{s}{il:s}{i}'
-
-
-_DEFAULT_SALT = 'Salt!'
-_DEFAULT_INFO = 'Info!'
-_STATIC_IV = ''.join([chr(x) for x in range(16)])
-
-_ECIES_INPUTS = (
-  (
-    '',
-    'Test message!!',
-    _STATIC_IV,
-    a2b('6fdaf5e2e11dd61c116222c748d99b45f69031c9d4d3d5787a9a0fdd3b9c471a'),
-    a2b('98e76f53febd6bedc8fa19ce1543cb3f8f5cbc72c74602f1bfdee88c19d3d9d0'),
-    a2b('8750c295cd33be5846868e2869bf2c8cfeefbc4a574874c7388bf40f74e8e0e6'),
-    _DEFAULT_SALT,
-    _DEFAULT_INFO,
-    'SIMPLE'
-  ),
-  (
-    '',
-    'Multi block test message!!!!',
-    _STATIC_IV,
-    a2b('6fdaf5e2e11dd61c116222c748d99b45f69031c9d4d3d5787a9a0fdd3b9c471a'),
-    a2b('98e76f53febd6bedc8fa19ce1543cb3f8f5cbc72c74602f1bfdee88c19d3d9d0'),
-    a2b('8750c295cd33be5846868e2869bf2c8cfeefbc4a574874c7388bf40f74e8e0e6'),
-    _DEFAULT_SALT,
-    _DEFAULT_INFO,
-    'MULTI-BLOCK'
-  ),
-  (
-    'Auth data',
-    'Test message!!!!',
-    _STATIC_IV,
-    a2b('6fdaf5e2e11dd61c116222c748d99b45f69031c9d4d3d5787a9a0fdd3b9c471a'),
-    a2b('98e76f53febd6bedc8fa19ce1543cb3f8f5cbc72c74602f1bfdee88c19d3d9d0'),
-    a2b('8750c295cd33be5846868e2869bf2c8cfeefbc4a574874c7388bf40f74e8e0e6'),
-    _DEFAULT_SALT,
-    _DEFAULT_INFO,
-    'AUTH-DATA'
-  ),
-  (
-    'Auth data' * 10,
-    'Test message!!!!',
-    _STATIC_IV,
-    a2b('6fdaf5e2e11dd61c116222c748d99b45f69031c9d4d3d5787a9a0fdd3b9c471a'),
-    a2b('98e76f53febd6bedc8fa19ce1543cb3f8f5cbc72c74602f1bfdee88c19d3d9d0'),
-    a2b('8750c295cd33be5846868e2869bf2c8cfeefbc4a574874c7388bf40f74e8e0e6'),
-    _DEFAULT_SALT,
-    _DEFAULT_INFO,
-    'LARGE-AUTH-DATA'
-  ),
-  (
-    'Auth data',
-    'Test message!!!!' * 5,
-    _STATIC_IV,
-    a2b('6fdaf5e2e11dd61c116222c748d99b45f69031c9d4d3d5787a9a0fdd3b9c471a'),
-    a2b('98e76f53febd6bedc8fa19ce1543cb3f8f5cbc72c74602f1bfdee88c19d3d9d0'),
-    a2b('8750c295cd33be5846868e2869bf2c8cfeefbc4a574874c7388bf40f74e8e0e6'),
-    _DEFAULT_SALT,
-    _DEFAULT_INFO,
-    'LARGE-PLAINTEXT-DATA'
-  ),
-  (
-    '',
-    'Test message!!',
-    _STATIC_IV,
-    a2b('6fdaf5e2e11dd61c116222c748d99b45f69031c9d4d3d5787a9a0fdd3b9c471a'),
-    a2b('98e76f53febd6bedc8fa19ce1543cb3f8f5cbc72c74602f1bfdee88c19d3d9d0'),
-    a2b('8750c295cd33be5846868e2869bf2c8cfeefbc4a574874c7388bf40f74e8e0e6'),
-    '',
-    '',
-    'NO-SALT-INFO'
-  ),
-  (
-    'Auth data',
-    '',
-    _STATIC_IV,
-    a2b('6fdaf5e2e11dd61c116222c748d99b45f69031c9d4d3d5787a9a0fdd3b9c471a'),
-    a2b('98e76f53febd6bedc8fa19ce1543cb3f8f5cbc72c74602f1bfdee88c19d3d9d0'),
-    a2b('8750c295cd33be5846868e2869bf2c8cfeefbc4a574874c7388bf40f74e8e0e6'),
-    _DEFAULT_SALT,
-    _DEFAULT_INFO,
-    'AUTH-NULL-PLAINTEXT'
-  ),
-  (
-    '',
-    '',
-    _STATIC_IV,
-    a2b('6fdaf5e2e11dd61c116222c748d99b45f69031c9d4d3d5787a9a0fdd3b9c471a'),
-    a2b('98e76f53febd6bedc8fa19ce1543cb3f8f5cbc72c74602f1bfdee88c19d3d9d0'),
-    a2b('8750c295cd33be5846868e2869bf2c8cfeefbc4a574874c7388bf40f74e8e0e6'),
-    _DEFAULT_SALT,
-    _DEFAULT_INFO,
-    'NULL-PLAINTEXT'
-  ),
-)
-
-_ECIES_COMPAT_INPUTS = (
-  (
-    a2b('d61262f22e8c70414777cbc060d1e387'),
-    'The quick brown fox jumps over the lazy dog.',
-    a2b('d61262f22e8c70414777cbc060d1e387'),
-    a2b('040c23b1abb7f7e3d2da6ffd70ce9e6f5bf90467c0e1f2e708483d2e61220f0a'
-        '0257110d695bec78ac1e15333219d7ba3f8f2f155b76acd56d99680031d83853'
-        '99d61262f22e8c70414777cbc060d1e387a4e9ac4624b79e326c19396b44842b'
-        'd995123343efe844821ff97ed08e38db59141ed8185359f76121d5fce7c4491d'
-        '902551bdd9bbd28e0ae27d1d4c9a6c1a9bb7b8aa36d1b1f6cce0425739'),
-    a2b('67e0df0b8e5131766340c895553c13053332fdee1fbd2d9cdde22a331a49aaa1'),
-    _DEFAULT_SALT,
-    _DEFAULT_INFO,
-    'COMPAT-TEST1'
-  ),
-  (
-    a2b('b3a89ed5a7fb6685a67db54c62e663e7'),
-    'Test message!!',
-    a2b('b3a89ed5a7fb6685a67db54c62e663e7'),
-    a2b('04b9d46d1f333baf6896ce7b64d344092671795438b1dc35a21b0d13b004f28a1c'
-        'edd4f1f7ff63106772270050cb62152b07e9c02bbee79db7a3fb4155c464e0d5b3'
-        'a89ed5a7fb6685a67db54c62e663e70fed2b44ce0f705e9a84a09978b82f6c603e'
-        'b6e6923d592f22193fb7ba0e1765ecd4861ec46c138d85b7206dbd41'),
-    a2b('6fdaf5e2e11dd61c116222c748d99b45f69031c9d4d3d5787a9a0fdd3b9c471a'),
-    _DEFAULT_SALT,
-    _DEFAULT_INFO,
-    'COMPAT-TEST2'
-  )
-)
-
-
-def _encrypt_cmd(auth, input, iv, pubx, puby, salt, info):
-  op = _ECIES_OPCODES['ENCRYPT']
-  return _ECIES_CMD_FORMAT.format(o=op, inl=pack('>H', len(auth+input)), input=auth+input,
-                                  al=pack('>H', len(auth)), iv=iv,
-                                  xl=pack('>H', len(pubx)), x=pubx,
-                                  yl=pack('>H', len(puby)), y=puby,
-                                  sl=pack('>H', len(salt)), s=salt,
-                                  il=pack('>H', len(info)), i=info)
-
-
-def _decrypt_cmd(auth, input, iv, d, salt, info):
-  op = _ECIES_OPCODES['DECRYPT']
-  return _ECIES_CMD_FORMAT.format(o=op, inl=pack('>H', len(input)), input=input,
-                                  al=pack('>H', len(auth)), iv=iv,
-                                  xl=pack('>H', len(d)), x=d,
-                                  yl=pack('>H', 0), y='',
-                                  sl=pack('>H', len(salt)), s=salt,
-                                  il=pack('>H', len(info)), i=info)
-
-
-def _ecies_test(tpm):
-  for data in _ECIES_INPUTS:
-    auth, input, iv, d, pubx, puby, salt, info = data[:-1]
-    test_name = 'ECIES-TEST:%s' % data[-1]
-    cmd = _encrypt_cmd(auth, input, iv, pubx, puby, salt, info)
-    wrapped_response = tpm.command(tpm.wrap_ext_command(subcmd.ECIES, cmd))
-    encrypted = tpm.unwrap_ext_response(subcmd.ECIES, wrapped_response)
-    # check length of encrypted.
-    if not encrypted:
-      raise subcmd.TpmTestError('%s error:%s' % (
-          test_name, 'null encrypted'))
-
-    cmd = _decrypt_cmd(auth, encrypted, iv, d, salt, info)
-    wrapped_response = tpm.command(tpm.wrap_ext_command(subcmd.ECIES, cmd))
-    decrypted = tpm.unwrap_ext_response(subcmd.ECIES, wrapped_response)
-
-    expected = auth + input
-    if decrypted != expected:
-      raise subcmd.TpmTestError('%s error:%s:%s' % (
-          test_name, utils.hex_dump(decrypted), utils.hex_dump(expected)))
-    print('%sSUCCESS: %s' % (utils.cursor_back(), test_name))
-
-
-def _compat_test(tpm):
-  for data in _ECIES_COMPAT_INPUTS:
-    auth, plaintext, iv, ciphertext, d, salt, info = data[:-1]
-    test_name = 'ECIES-TEST:%s' % data[-1]
-
-    cmd = _decrypt_cmd(auth, ciphertext, iv, d, salt, info)
-    wrapped_response = tpm.command(tpm.wrap_ext_command(subcmd.ECIES, cmd))
-    decrypted = tpm.unwrap_ext_response(subcmd.ECIES, wrapped_response)
-
-    expected = auth + plaintext
-    if decrypted != expected:
-      raise subcmd.TpmTestError('%s error:%s:%s' % (
-          test_name, utils.hex_dump(decrypted), utils.hex_dump(expected)))
-    print('%sSUCCESS: %s' % (utils.cursor_back(), test_name))
-
-
-def ecies_test(tpm):
-  _ecies_test(tpm)
-  _compat_test(tpm)
diff --git a/test/tpm_test/ftdi_spi_tpm.c b/test/tpm_test/ftdi_spi_tpm.c
deleted file mode 100644
index 4fc281aa24..0000000000
--- a/test/tpm_test/ftdi_spi_tpm.c
+++ /dev/null
@@ -1,495 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include <endian.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <time.h>
-#include <unistd.h>
-
-#include "ftdi_spi_tpm.h"
-
-static struct mpsse_context *mpsse_;
-static unsigned locality_;	/* Set at initialization. */
-static int ftdi_trace_enabled;
-
-/* Assorted TPM2 registers for interface type FIFO. */
-#define TPM_LOCALITY_0_SPI_BASE 0x00d40000
-
-#define TPM_ACCESS_REG    (TPM_LOCALITY_0_SPI_BASE + 0)
-#define TPM_STS_REG       (TPM_LOCALITY_0_SPI_BASE + 0x18)
-#define TPM_DATA_FIFO_REG (TPM_LOCALITY_0_SPI_BASE + 0x24)
-#define TPM_DID_VID_REG   (TPM_LOCALITY_0_SPI_BASE + 0xf00)
-#define TPM_RID_REG       (TPM_LOCALITY_0_SPI_BASE + 0xf04)
-#define TPM_FW_VER        (TPM_LOCALITY_0_SPI_BASE + 0xf90)
-
-static struct swig_string_data empty_string_data = (struct swig_string_data){
-	.size = 0, .data = NULL
-};
-
-/* Locality management bits (in TPM_ACCESS_REG). */
-enum TpmAccessBits {
-	tpmRegValidSts = (1 << 7),
-	activeLocality = (1 << 5),
-	requestUse = (1 << 1),
-	tpmEstablishment = (1 << 0),
-};
-
-enum TpmStsBits {
-	tpmFamilyShift = 26,
-	tpmFamilyMask = ((1 << 2) - 1),	/* 2 bits wide. */
-	tpmFamilyTPM2 = 1,
-	resetEstablishmentBit = (1 << 25),
-	commandCancel = (1 << 24),
-	burstCountShift = 8,
-	burstCountMask = ((1 << 16) - 1),	/* 16 bits wide. */
-	stsValid = (1 << 7),
-	commandReady = (1 << 6),
-	tpmGo = (1 << 5),
-	dataAvail = (1 << 4),
-	Expect = (1 << 3),
-	selfTestDone = (1 << 2),
-	responseRetry = (1 << 1),
-};
-
-enum {
-	false = 0,
-	true = 1
-};
-
-/*
- * SPI frame header for TPM transactions is 4 bytes in size, it is described
- * in section "6.4.6 Spi Bit Protocol" of the TCG issued "TPM Profile (PTP)
- * Specification Revision 00.43.
- */
-struct SpiFrameHeader {
-	unsigned char body[4];
-};
-
-void FtdiStop(void)
-{
-	if (mpsse_)
-		Close(mpsse_);
-
-	mpsse_ = NULL;
-}
-
-/*
- * If the TPM is asleep we may need to poke it once to wake it up. Just assert
- * the CS briefly without sending any data, then wait a bit to be sure it's
- * awake.
- */
-static void FtdiSpiPoke(void)
-{
-	Start(mpsse_);
-	usleep(1000);
-	Stop(mpsse_);
-	usleep(60000);
-}
-
-static void StartTransaction(int read_write, size_t bytes, unsigned addr)
-{
-	struct SpiFrameHeader header;
-	int i;
-	uint8_t flow_c;
-	char *transfer_data;
-
-	/*
-	 * give it 10 ms. TODO(vbendeb): remove this once cr50 SPS TPM driver
-	 * performance is fixed.
-	 */
-	usleep(10000);
-
-	/*
-	 * The first byte of the frame header encodes the transaction type
-	 * (read or write) and size (set to length - 1).
-	 */
-	header.body[0] = (read_write ? 0x80 : 0) | 0x40 | (bytes - 1);
-
-	/* The rest of the frame header is the internal address in the TPM. */
-	for (i = 0; i < 3; i++)
-		header.body[i + 1] = (addr >> (8 * (2 - i))) & 0xff;
-
-	Start(mpsse_);
-
-	transfer_data =
-	    Transfer(mpsse_, (char *)header.body, sizeof(header.body));
-
-	/*
-	 * The TCG TPM over SPI specification itroduces the notion of SPI flow
-	 * control (Section "6.4.5 Flow Control" of the TCG issued "TPM
-	 * Profile (PTP) Specification Revision 00.43).
-	 *
-	 * The slave (TPM device) expects each transaction to start with a 4
-	 * byte header trasmitted by master. If the slave needs to stall the
-	 * transaction, it sets the MOSI bit to 0 during the last clock of the
-	 * 4 byte header. In this case the master is supposed to start polling
-	 * the line, byte at time, until the last bit in the received byte
-	 * (transferred during the last clock of the byte) is set to 1.
-	 */
-	flow_c = transfer_data[3];
-	free(transfer_data);
-	while (!(flow_c & 1)) {
-		transfer_data = Read(mpsse_, 1);
-		flow_c = transfer_data[0];
-		free(transfer_data);
-	}
-}
-
-static void trace_dump(const char *prefix, unsigned reg, size_t bytes,
-		       const uint8_t *buffer)
-{
-	if (!ftdi_trace_enabled)
-		return;
-	printf("%s %2.2x:", prefix, reg);
-	if (bytes == 4) {
-		printf(" %8.8x\n", *(const uint32_t *)buffer);
-	} else {
-		int i;
-
-		for (i = 0; i < bytes; i++)
-			printf(" %2.2x", buffer[i]);
-		printf("\n");
-	}
-}
-
-static int FtdiWriteReg(unsigned reg_number, size_t bytes, void *buffer)
-{
-	if (!mpsse_)
-		return false;
-
-	trace_dump("W", reg_number, bytes, buffer);
-	StartTransaction(false, bytes, reg_number + locality_ * 0x10000);
-	Write(mpsse_, buffer, bytes);
-	Stop(mpsse_);
-	return true;
-}
-
-static int FtdiReadReg(unsigned reg_number, size_t bytes, void *buffer)
-{
-	void *data;
-
-	if (!mpsse_)
-		return false;
-
-	StartTransaction(true, bytes, reg_number + locality_ * 0x10000);
-	data = Read(mpsse_, bytes);
-	if (data)
-		memcpy(buffer, data, bytes);
-	free(data);
-	Stop(mpsse_);
-	trace_dump("R", reg_number, bytes, buffer);
-	return true;
-}
-
-static int ReadTpmSts(uint32_t *status)
-{
-	return FtdiReadReg(TPM_STS_REG, sizeof(*status), status);
-}
-
-static int WriteTpmSts(uint32_t status)
-{
-	return FtdiWriteReg(TPM_STS_REG, sizeof(status), &status);
-}
-
-static uint32_t GetBurstCount(void)
-{
-	uint32_t status;
-
-	ReadTpmSts(&status);
-	return (status >> burstCountShift) & burstCountMask;
-}
-
-static void GetVersion(void)
-{
-	int chunk_count = 0;
-	uint32_t chunk = 0;
-	char vstr[sizeof(chunk) + 1];           /* room for 4 chars + zero */
-
-	/*
-	 * Does not really matter what's written, this just makes sure
-	 * the version is reported from the beginning.
-	 */
-	FtdiWriteReg(TPM_FW_VER, sizeof(chunk), &chunk);
-
-	/* Print it out in 4 byte chunks. */
-	vstr[sizeof(vstr) - 1] = 0;
-	do {
-		FtdiReadReg(TPM_FW_VER, sizeof(chunk), vstr);
-		printf("%s", vstr);
-
-		/*
-		 * While string is not over, and no more than 200
-		 * characters.
-		 * This is likely result in one extra printk()
-		 * invocation with an empty string, not a big deal.
-		 */
-	} while (vstr[0] && (chunk_count++ < (400 / sizeof(chunk))));
-
-	printf("\n");
-}
-
-int FtdiSpiInit(uint32_t freq, int enable_debug)
-{
-	uint32_t did_vid, status;
-	uint8_t cmd;
-	uint16_t vid;
-
-	if (mpsse_)
-		return true;
-
-	ftdi_trace_enabled = enable_debug;
-
-	/* round frequency down to the closest 100KHz */
-	freq = (freq / (100 * 1000)) * 100 * 1000;
-
-	printf("Starting MPSSE at %d kHz\n", freq / 1000);
-	mpsse_ = MPSSE(freq, MSB, NULL);
-	if (!mpsse_)
-		return false;
-
-	/* Just in case, make sure bootsrap is not triggered. */
-	PinLow(mpsse_, GPIOL0);
-
-	FtdiSpiPoke();
-
-	FtdiReadReg(TPM_DID_VID_REG, sizeof(did_vid), &did_vid);
-
-	vid = did_vid & 0xffff;
-	if ((vid != 0x15d1) && (vid != 0x1ae0)) {
-		fprintf(stderr, "unknown did_vid: %#x\n", did_vid);
-		return false;
-	}
-
-	/* Try claiming locality zero. */
-	FtdiReadReg(TPM_ACCESS_REG, sizeof(cmd), &cmd);
-	if ((cmd & (activeLocality & tpmRegValidSts)) ==
-	    (activeLocality & tpmRegValidSts)) {
-		/*
-		 * Locality active - maybe reset line is not connected?
-		 * Release the locality and try again
-		 */
-		cmd = activeLocality;
-		FtdiWriteReg(TPM_ACCESS_REG, sizeof(cmd), &cmd);
-		FtdiReadReg(TPM_ACCESS_REG, sizeof(cmd), &cmd);
-	}
-
-	/* tpmEstablishment can be either set or not. */
-	if ((cmd & ~tpmEstablishment) != tpmRegValidSts) {
-		fprintf(stderr, "invalid reset status: %#x\n", cmd);
-		return false;
-	}
-	cmd = requestUse;
-	FtdiWriteReg(TPM_ACCESS_REG, sizeof(cmd), &cmd);
-	FtdiReadReg(TPM_ACCESS_REG, sizeof(cmd), &cmd);
-	if ((cmd & ~tpmEstablishment) != (tpmRegValidSts | activeLocality)) {
-		fprintf(stderr, "failed to claim locality, status: %#x\n", cmd);
-		return false;
-	}
-
-	ReadTpmSts(&status);
-	if (((status >> tpmFamilyShift) & tpmFamilyMask) != tpmFamilyTPM2) {
-		fprintf(stderr, "unexpected TPM family value, status: %#x\n",
-			status);
-		return false;
-	}
-	FtdiReadReg(TPM_RID_REG, sizeof(cmd), &cmd);
-	printf("Connected to device vid:did:rid of %4.4x:%4.4x:%2.2x\n",
-	       did_vid & 0xffff, did_vid >> 16, cmd);
-
-	GetVersion();
-
-	return true;
-}
-
-/* This is in seconds (prime generation may take several minutes). */
-#define MAX_STATUS_TIMEOUT 900
-static int WaitForStatus(uint32_t statusMask, uint32_t statusExpected)
-{
-	uint32_t status;
-	time_t target_time;
-	static unsigned max_timeout;
-
-	target_time = time(NULL) + MAX_STATUS_TIMEOUT;
-	do {
-		usleep(10000);
-		if (time(NULL) >= target_time) {
-			fprintf(stderr, "failed to get expected status %x\n",
-				statusExpected);
-			return false;
-		}
-		ReadTpmSts(&status);
-	} while ((status & statusMask) != statusExpected);
-
-	/* Calculate time spent waiting */
-	target_time = MAX_STATUS_TIMEOUT - target_time + time(NULL);
-	if (max_timeout < (unsigned)target_time) {
-		max_timeout = target_time;
-		printf("New max timeout: %d s\n", max_timeout);
-	}
-
-	return true;
-}
-
-static void SpinSpinner(void)
-{
-	static const char *spinner = "\\|/-";
-	static int index;
-
-	if (index > strlen(spinner))
-		index = 0;
-
-	fprintf(stdout, "%c[1D%c", 0x1b, spinner[index++]);
-	fflush(stdout);
-}
-
-#define MAX_RESPONSE_SIZE 4096
-#define HEADER_SIZE 6
-
-/* tpm_command points at a buffer 4096 bytes in size */
-struct swig_string_data FtdiSendCommandAndWait(char *tpm_command,
-					       int command_size)
-{
-	uint32_t status;
-	uint32_t expected_status_bits;
-	size_t handled_so_far;
-	uint32_t payload_size;
-	char message[100];
-	int offset = 0;
-	uint8_t *response;
-
-	if (!mpsse_) {
-		fprintf(stderr, "attempt to use an uninitialized FTDI TPM!\n");
-		return empty_string_data;
-	}
-
-	response = malloc(MAX_RESPONSE_SIZE);
-	if (!response) {
-		fprintf(stderr, "attempt to use an uninitialized FTDI TPM!\n");
-		return empty_string_data;
-	}
-
-	handled_so_far = 0;
-
-	WriteTpmSts(commandReady);
-
-	memcpy(&payload_size, tpm_command + 2, sizeof(payload_size));
-	payload_size = be32toh(payload_size);
-	offset +=
-	    snprintf(message, sizeof(message), "Message size %d", payload_size);
-
-	/*
-	 * No need to wait for the sts.Expect bit to be set, at least with the
-	 * 15d1:001b and 1ae0:0028 devices. Let's just write the command into
-	 * FIFO, make sure not to exceed the burst count.
-	 */
-	do {
-		uint32_t transaction_size;
-		uint32_t burst_count = GetBurstCount();
-
-		if (burst_count > 64)
-			burst_count = 64;
-
-		transaction_size = command_size - handled_so_far;
-		if (transaction_size > burst_count)
-			transaction_size = burst_count;
-
-		if (transaction_size) {
-			FtdiWriteReg(TPM_DATA_FIFO_REG, transaction_size,
-				     tpm_command + handled_so_far);
-			handled_so_far += transaction_size;
-		}
-	} while (handled_so_far != command_size);
-
-	/* And tell the device it can start processing it. */
-	WriteTpmSts(tpmGo);
-
-	expected_status_bits = stsValid | dataAvail;
-	if (!WaitForStatus(expected_status_bits, expected_status_bits)) {
-		size_t i;
-
-		printf("Failed processing. %s:", message);
-		for (i = 0; i < command_size; i++) {
-			if (!(i % 16))
-				printf("\n");
-			printf(" %2.2x", (uint8_t)tpm_command[i]);
-		}
-		printf("\n");
-		return empty_string_data;
-	}
-
-	/*
-	 * The tpm_command is ready, let's read it.
-	 *
-	 * First we read the FIFO payload header, to see how much data to
-	 * expect. The header size is fixed to six bytes, the total payload
-	 * size is stored in network order in the last four bytes of the
-	 * header.
-	 */
-	FtdiReadReg(TPM_DATA_FIFO_REG, HEADER_SIZE, response);
-	handled_so_far = HEADER_SIZE;
-
-	/* Figure out the total payload size. */
-	memcpy(&payload_size, response + 2, sizeof(payload_size));
-	payload_size = be32toh(payload_size);
-
-	if (ftdi_trace_enabled)
-		printf("%s response size %d\n\n", message, payload_size);
-	else
-		SpinSpinner();
-
-	if (payload_size > MAX_RESPONSE_SIZE)
-		return empty_string_data;
-	/*
-	 * Let's read all but the last byte in the FIFO to make sure the
-	 * status register is showing correct flow control bits: 'more data'
-	 * until the last byte and then 'no more data' once the last byte is
-	 * read.
-	 */
-	payload_size = payload_size - 1;
-	do {
-		uint32_t transaction_size;
-		uint32_t burst_count = GetBurstCount();
-
-		if (burst_count > 64)
-			burst_count = 64;
-
-		transaction_size = payload_size - handled_so_far;
-		if (transaction_size > burst_count)
-			transaction_size = burst_count;
-
-		if (transaction_size) {
-			FtdiReadReg(TPM_DATA_FIFO_REG, transaction_size,
-				    response + handled_so_far);
-			handled_so_far += transaction_size;
-		}
-	} while (handled_so_far != payload_size);
-
-	/* Verify that there is still data to come. */
-	ReadTpmSts(&status);
-	if ((status & expected_status_bits) != expected_status_bits) {
-		fprintf(stderr, "unexpected status %#x\n", status);
-		return empty_string_data;
-	}
-
-	FtdiReadReg(TPM_DATA_FIFO_REG, 1, response + handled_so_far);
-
-	/* Verify that 'data available' is not asseretd any more. */
-	ReadTpmSts(&status);
-	if ((status & expected_status_bits) != stsValid) {
-		fprintf(stderr, "unexpected status %#x\n", status);
-		return empty_string_data;
-	}
-
-	/* Move the TPM back to idle state. */
-	WriteTpmSts(commandReady);
-
-	handled_so_far++;
-
-	return (struct swig_string_data) {
-		.size = handled_so_far, .data = response};
-}
diff --git a/test/tpm_test/ftdi_spi_tpm.h b/test/tpm_test/ftdi_spi_tpm.h
deleted file mode 100644
index 5393d4cd86..0000000000
--- a/test/tpm_test/ftdi_spi_tpm.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __EC_TEST_TPM_TEST_FTDI_SPI_TPM_H
-#define __EC_TEST_TPM_TEST_FTDI_SPI_TPM_H
-
-#include "mpsse.h"
-
-/*
- * This structure allows to convert string representation between C and
- * Python.
- */
-struct swig_string_data {
-	int size;
-	uint8_t *data;
-};
-
-int FtdiSpiInit(uint32_t freq, int enable_debug);
-void FtdiStop(void);
-struct swig_string_data FtdiSendCommandAndWait(char *tpm_command,
-					       int command_size);
-
-#endif				/* ! __EC_TEST_TPM_TEST_FTDI_SPI_TPM_H */
diff --git a/test/tpm_test/ftdi_spi_tpm.i b/test/tpm_test/ftdi_spi_tpm.i
deleted file mode 100644
index c9cc2fc535..0000000000
--- a/test/tpm_test/ftdi_spi_tpm.i
+++ /dev/null
@@ -1,50 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-%module ftdi_spi_tpm
-typedef unsigned uint32_t;
-typedef unsigned char uint8_t;
-
-%{
-typedef struct swig_string_data
-{
-  int size;
-  char *data;
-} swig_string_data;
-
-extern int FtdiSpiInit(uint32_t freq, int enable_debug);
-extern void FtdiStop(void);
-extern swig_string_data FtdiSendCommandAndWait(char *tpm_command,
-					       int command_size);
-%}
-
-%typemap(in) (char *tpm_command, int command_size)
-{
-        if(!PyString_Check($input))
-        {
-                PyErr_SetString(PyExc_ValueError, "String value required");
-                return NULL;
-        }
-
-        $1 = PyString_AsString($input);
-        $2 = PyString_Size($input);
-}
-
-%typemap(out) swig_string_data
-{
-        $result = PyString_FromStringAndSize($1.data, $1.size);
-        free($1.data);
-}
-
-typedef struct swig_string_data
-{
-  int size;
-  char *data;
-} swig_string_data;
-
-extern int FtdiSpiInit(uint32_t freq, int enable_debug);
-extern void FtdiStop(void);
-extern swig_string_data FtdiSendCommandAndWait(char *tpm_command,
-					       int command_size);
diff --git a/test/tpm_test/genvectors.py b/test/tpm_test/genvectors.py
deleted file mode 100644
index 593a6aab71..0000000000
--- a/test/tpm_test/genvectors.py
+++ /dev/null
@@ -1,77 +0,0 @@
-#!/usr/bin/env python2
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-"""Module for generating AES test vectors."""
-
-from binascii import b2a_hex as b2a
-from Crypto.Cipher import AES
-from itertools import izip_longest
-import os
-
-modes = {
-    AES.MODE_CBC: 'CBC',
-    AES.MODE_CFB: 'CFB',
-    AES.MODE_OFB: 'OFB',
-}
-
-template = \
-'''
-  <crypto_test name="AES:{mode}{key_bits} {test_num}">
-    <clear_text format="hex">
-      {pt}
-    </clear_text>
-    <key>
-      {key}
-    </key>
-    <cipher_text>
-      {ct}
-    </cipher_text>
-    <iv>
-      {iv}
-    </iv>
-  </crypto_test>
-'''
-
-def h2be(v):
-    # Convert input big-endian byte-string to 4-byte segmented
-    # little-endian words.  Pad-bytes (if necessary) are the empty string.
-    word = [iter(v)] * 4
-    return ''.join([
-        ''.join(b[::-1]) for b in izip_longest(*word, fillvalue='')
-    ])
-
-
-for mode in [AES.MODE_CBC, AES.MODE_CFB, AES.MODE_OFB]:
-    for key_bytes in [16, 24, 32]:
-        test_num = 0
-        for pt_len in [5, 16, 21, 32]:
-            # CBC mode requires block sized inputs.
-            if mode == AES.MODE_CBC and pt_len % 16:
-                continue
-            test_num += 1
-
-            actual_pt_len = pt_len
-            if pt_len % 16:
-                pt_len = 16 * ((pt_len / 16) + 1)
-
-            key = os.urandom(key_bytes)
-            iv = os.urandom(16)
-            pt = os.urandom(pt_len)
-
-            obj = AES.new(key, mode=mode, IV=iv, segment_size=128)
-            ct = obj.encrypt(pt)
-            obj = AES.new(key, mode=mode, IV=iv, segment_size=128)
-
-            assert obj.decrypt(ct)[:pt_len] == pt
-
-            print template.format(mode=modes[mode],
-                                  key_bits=str(key_bytes * 8),
-                                  test_num=str(test_num),
-                                  pt=b2a(h2be(pt[:actual_pt_len])),
-                                  key=b2a(h2be(key)),
-                                  ct=b2a(h2be(ct[:actual_pt_len])),
-                                  iv=b2a(h2be(iv))),
-
-
diff --git a/test/tpm_test/hash_test.py b/test/tpm_test/hash_test.py
deleted file mode 100644
index 9f10894d2e..0000000000
--- a/test/tpm_test/hash_test.py
+++ /dev/null
@@ -1,160 +0,0 @@
-#!/usr/bin/env python2
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-"""Module for testing hash functions using extended commands."""
-
-from __future__ import print_function
-
-import hashlib
-import hmac
-import struct
-
-import subcmd
-import utils
-
-# Hash command modes
-CMD_HASH_START = 0
-CMD_HASH_CONT = 1
-CMD_HASH_FINISH = 2
-CMD_HASH = 3
-CMD_HMAC_SW = 4
-CMD_HMAC_HW = 5
-
-
-# Hash algorithm
-ALG_SHA1 = 0
-ALG_SHA256 = 1
-ALG_SHA384 = 2
-ALG_SHA512 = 3
-
-# A standard empty response to HASH extended commands.
-EMPTY_RESPONSE = ''.join('%c' % x for x in (0x80, 0x01, 0x00, 0x00, 0x00, 0x0c,
-                                            0x00, 0x00, 0x00, 0x00, 0x00, 0x01))
-test_inputs = (
-  # Hash cmd    alg      handle  hmac_key           text
-  (CMD_HMAC_SW, ALG_SHA256, 0, 'hmac_key1', 'some text, this time for sw hmac'),
-  (CMD_HMAC_SW, ALG_SHA1,   0, 'hmac_key2', 'some text, this time for sw hmac'),
-  (CMD_HMAC_SW, ALG_SHA384, 0, 'hmac_key3', 'some text, this time for sw hmac'),
-  (CMD_HMAC_SW, ALG_SHA512, 0, 'hmac_key4', 'some text, this time for sw hmac'),
-  (CMD_HMAC_HW, ALG_SHA256, 0, 'hmac_key5', 'some text, this time for hw hmac'),
-  (CMD_HMAC_SW, ALG_SHA256, 0, 'very long hmac_key 456456789012345', '   text'),
-  (CMD_HMAC_HW, ALG_SHA256, 0, 'very long hmac_key 123456789012345', '   text'),
-  (CMD_HMAC_SW, ALG_SHA384, 0, 'very long hmac_key 456456789012345', '   text'),
-  (CMD_HMAC_SW, ALG_SHA512, 0, 'very long hmac_key 456456789012345', '   text'),
-  (CMD_HASH,        ALG_SHA1,   0, '', ''),
-  (CMD_HASH,        ALG_SHA256, 0, '', ''),
-  (CMD_HASH,        ALG_SHA1,   0, '', 'anything really will work here'),
-  (CMD_HASH,        ALG_SHA256, 0, '', 'some more text, this time for sha256'),
-  (CMD_HASH_START,  ALG_SHA256, 1, '', 'some more text, this time for sha256'),
-  (CMD_HASH_CONT,   ALG_SHA256, 1, '', 'some more text, this time for sha256'),
-  (CMD_HASH_START,  ALG_SHA256, 2, '', 'this could be anything here'),
-  (CMD_HASH,        ALG_SHA1,   3, '', 'interleave a SHA1 single shot'),
-  (CMD_HASH,        ALG_SHA256, 3, '', 'interleave a SHA256 single shot'),
-  (CMD_HASH_START,  ALG_SHA1,   3, '', 'let\'s interleave a sha1 calculation'),
-  (CMD_HASH_CONT,   ALG_SHA256, 2, '', 'fill up a second context with data'),
-  (CMD_HASH_CONT,   ALG_SHA256, 1, '', 'let\'s feed some more into context 1'),
-  (CMD_HASH_FINISH, ALG_SHA256, 1, '', 'some more text, this time for sha256'),
-  (CMD_HASH_CONT,   ALG_SHA1,   3, '', 'with two active sha256 calculations'),
-  (CMD_HASH_FINISH, ALG_SHA1,   3, '', 'this should be enough'),
-  (CMD_HASH_FINISH, ALG_SHA256, 2, '', 'it does not really matter what'),
-  (CMD_HASH,        ALG_SHA384, 0, '', 'some more text, this time for sha384'),
-  (CMD_HASH,        ALG_SHA512, 0, '', 'some more text, this time for sha512'),
-  (CMD_HASH_START,  ALG_SHA256, 0, '', 'some more text, this time for sha256'),
-  (CMD_HASH_START,  ALG_SHA384, 1, '', 'some more text, this time for sha384'),
-  (CMD_HASH_CONT,   ALG_SHA384, 1, '', 'some more text, this time for sha384'),
-  (CMD_HASH_CONT,   ALG_SHA256, 0, '', 'some more text, this time for sha256'),
-  (CMD_HASH_START,  ALG_SHA512, 2, '', 'some more text, this time for sha512'),
-  (CMD_HASH_CONT,   ALG_SHA512, 2, '', 'some more text, this time for sha512'),
-  (CMD_HASH_FINISH, ALG_SHA512, 2, '', 'this should be enough'),
-  (CMD_HASH_FINISH, ALG_SHA256, 0, '', 'this should be enough'),
-  (CMD_HASH_FINISH, ALG_SHA384, 1, '', 'this should be enough'),
-)
-
-def hash_test(tpm):
-  """Exercise multiple hash threads simultaneously.
-
-    Command structure, shared out of band with the test running on the target:
-
-    field     |    size  |                  note
-    ===================================================================
-    hash_cmd  |    1     | 0 - start, 1 - cont., 2 - finish, 3 - single
-              |          | 4 - SW HMAC single shot (TPM code)
-              |          | 5 - HW HMAC SHA256 single shot (dcrypto code)
-    hash_alg  |    1     | 0 - sha1, 1 - sha256, 2 - sha384, 3 - sha512
-    handle    |    1     | session handle, ignored in 'single' mode
-    text_len  |    2     | size of the text to process, big endian
-    text      | text_len | text to hash
-            for HMAC single shot only:
-    key_len   |    2     | size of the key for HMAC, big endian
-    key       | key_len  | key for HMAC single shot
-  Args:
-    tpm: a tpm object used to communicate with the device
-
-  Raises:
-    subcmd.TpmTestError: on unexpected target responses
-  """
-
-  contexts = {}
-
-  alg_map = {
-    ALG_SHA1: ('sha1', hashlib.sha1),
-    ALG_SHA256: ('sha256', hashlib.sha256),
-    ALG_SHA384: ('sha384', hashlib.sha384),
-    ALG_SHA512: ('sha512', hashlib.sha512),
-  }
-
-  cmd_map = {
-    CMD_HASH_START: 'hash start',
-    CMD_HASH_CONT: 'hash cont',
-    CMD_HASH_FINISH: 'hash finish',
-    CMD_HASH: 'hash',
-    CMD_HMAC_SW: 'hmac sw',
-    CMD_HMAC_HW: 'hmac hw'
-  }
-
-  for test in test_inputs:
-    hash_cmd, hash_alg, handle, hmac_key, text = test
-    mode_name = cmd_map[hash_cmd]
-    alg_name, hash_func = alg_map[hash_alg]
-
-    test_name = '%s:%s:%d' % (mode_name, alg_name, handle)
-
-    cmd = '%c' % hash_cmd
-    cmd += '%c' % hash_alg
-    cmd += '%c' % handle   # Ignored for single shots
-
-    cmd += struct.pack('>H', len(text))
-    cmd += text
-    # for HMAC add key
-    if hash_cmd in (CMD_HMAC_SW, CMD_HMAC_HW):
-      cmd += struct.pack('>H', len(hmac_key))
-      cmd += hmac_key
-    wrapped_response = tpm.command(tpm.wrap_ext_command(subcmd.HASH, cmd))
-    if hash_cmd in (CMD_HASH_START, CMD_HASH_CONT):
-      if hash_cmd == CMD_HASH_START:
-        contexts[handle] = hash_func()
-      h = contexts[handle]
-      h.update(text)
-      if wrapped_response != EMPTY_RESPONSE:
-        raise subcmd.TpmTestError("Unexpected response to '%s': %s" %
-                        (test_name, utils.hex_dump(wrapped_response)))
-      continue
-    if hash_cmd == CMD_HASH_FINISH:
-      h = contexts[handle]
-    elif hash_cmd == CMD_HASH:
-      h = hash_func()
-    elif hash_cmd in (CMD_HMAC_SW, CMD_HMAC_HW):
-      h = hmac.new(bytes(hmac_key), digestmod=hash_func)
-    else:
-      raise subcmd.TpmTestError('Unknown command %d' % hash_cmd)
-    h.update(text)
-    digest = h.digest()
-    result = wrapped_response[12:]
-    if result != h.digest():
-      raise subcmd.TpmTestError('%s error:%s%s' % (test_name,
-                                         utils.hex_dump(digest),
-                                         utils.hex_dump(result)))
-
-    print('%sSUCCESS: %s' % (utils.cursor_back(), test_name))
diff --git a/test/tpm_test/hkdf_test.py b/test/tpm_test/hkdf_test.py
deleted file mode 100644
index 3330d50105..0000000000
--- a/test/tpm_test/hkdf_test.py
+++ /dev/null
@@ -1,112 +0,0 @@
-#!/usr/bin/env python2
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-"""Module for testing HKDF using extended commands."""
-
-from binascii import a2b_hex as a2b
-from struct import pack
-
-import subcmd
-import utils
-
-
-_HKDF_OPCODES = {
-    'TEST_RFC': 0x00,
-}
-
-
-# Command format.
-#
-#    WIDTH         FIELD
-#    1             OP
-#    1             MSB SALT LEN
-#    1             LSB SALT LEN
-#    SALT_LEN      SALT
-#    1             MSB IKM LEN
-#    1             LSB IKM LEN
-#    IKM_LEN       IKM
-#    1             MSB INFO LEN
-#    1             LSB INFO LEN
-#    INFO_LEN      INFO
-#    1             MSB OKM LEN
-#    1             LSB OKM LEN
-#
-_HKDF_CMD_FORMAT = '{op:c}{sl:s}{salt}{ikml:s}{ikm}{infol:s}{info}{okml:s}'
-
-
-def _rfc_test_cmd(salt, ikm, info, okml):
-  op = _HKDF_OPCODES['TEST_RFC']
-  return _HKDF_CMD_FORMAT.format(op=op,
-                                 sl=pack('>H', len(salt)), salt=salt,
-                                 ikml=pack('>H', len(ikm)), ikm=ikm,
-                                 infol=pack('>H', len(info)), info=info,
-                                 okml=pack('>H', okml))
-
-
-#
-# Test vectors for HKDF-SHA256 from RFC 5869.
-#
-_RFC_TEST_INPUTS = (
-  (
-    '0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b',
-    '000102030405060708090a0b0c',
-    'f0f1f2f3f4f5f6f7f8f9',
-    ('3cb25f25faacd57a90434f64d0362f2a'
-     '2d2d0a90cf1a5a4c5db02d56ecc4c5bf'
-     '34007208d5b887185865'),
-      'BASIC',
-   ),
-  (
-    ('000102030405060708090a0b0c0d0e0f'
-     '101112131415161718191a1b1c1d1e1f'
-     '202122232425262728292a2b2c2d2e2f'
-     '303132333435363738393a3b3c3d3e3f'
-     '404142434445464748494a4b4c4d4e4f'),
-    ('606162636465666768696a6b6c6d6e6f'
-     '707172737475767778797a7b7c7d7e7f'
-     '808182838485868788898a8b8c8d8e8f'
-     '909192939495969798999a9b9c9d9e9f'
-     'a0a1a2a3a4a5a6a7a8a9aaabacadaeaf'),
-    ('b0b1b2b3b4b5b6b7b8b9babbbcbdbebf'
-     'c0c1c2c3c4c5c6c7c8c9cacbcccdcecf'
-     'd0d1d2d3d4d5d6d7d8d9dadbdcdddedf'
-     'e0e1e2e3e4e5e6e7e8e9eaebecedeeef'
-     'f0f1f2f3f4f5f6f7f8f9fafbfcfdfeff'),
-    ('b11e398dc80327a1c8e7f78c596a4934'
-     '4f012eda2d4efad8a050cc4c19afa97c'
-     '59045a99cac7827271cb41c65e590e09'
-     'da3275600c2f09b8367793a9aca3db71'
-     'cc30c58179ec3e87c14c01d5c1f3434f'
-     '1d87'),
-      'LONG INPUTS',
-   ),
-  (
-    '0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b0b',
-    '',
-    '',
-    ('8da4e775a563c18f715f802a063c5a31'
-     'b8a11f5c5ee1879ec3454e5f3c738d2d'
-     '9d201395faa4b61a96c8'),
-      'ZERO SALT/INFO',
-   )
-)
-
-
-def _rfc_tests(tpm):
-  for data in _RFC_TEST_INPUTS:
-    IKM, salt, info, OKM = map(a2b, data[:-1])
-    test_name = 'HKDF:SHA256:%s' % data[-1]
-    cmd = _rfc_test_cmd(salt, IKM, info, len(OKM))
-    wrapped_response = tpm.command(tpm.wrap_ext_command(subcmd.HKDF, cmd))
-    result = tpm.unwrap_ext_response(subcmd.HKDF, wrapped_response)
-
-    if result != OKM:
-      raise subcmd.TpmTestError('%s error:%s%s' % (
-          test_name, utils.hex_dump(result), utils.hex_dump(OKM)))
-    print('%sSUCCESS: %s' % (utils.cursor_back(), test_name))
-
-
-def hkdf_test(tpm):
-  _rfc_tests(tpm)
diff --git a/test/tpm_test/mpsse.c b/test/tpm_test/mpsse.c
deleted file mode 100644
index e57a9cf761..0000000000
--- a/test/tpm_test/mpsse.c
+++ /dev/null
@@ -1,728 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Based on Craig Heffner's version of Dec 27 2011, published on
- * https://github.com/devttys0/libmpsse
- */
-
-#include <stdint.h>
-#include <stdio.h>
-#include <stdlib.h>
-#include <string.h>
-#include <unistd.h>
-
-#if LIBFTDI1 == 1
-#include <libftdi1/ftdi.h>
-#else
-#include <ftdi.h>
-#endif
-
-#include "mpsse.h"
-#include "support.h"
-
-/* FTDI interfaces */
-enum interface {
-	IFACE_ANY = INTERFACE_ANY,
-	IFACE_A = INTERFACE_A,
-	IFACE_B = INTERFACE_B,
-	IFACE_C = INTERFACE_C,
-	IFACE_D = INTERFACE_D
-};
-
-enum mpsse_commands {
-	INVALID_COMMAND = 0xAB,
-	ENABLE_ADAPTIVE_CLOCK = 0x96,
-	DISABLE_ADAPTIVE_CLOCK = 0x97,
-	ENABLE_3_PHASE_CLOCK = 0x8C,
-	DISABLE_3_PHASE_CLOCK = 0x8D,
-	TCK_X5 = 0x8A,
-	TCK_D5 = 0x8B,
-	CLOCK_N_CYCLES = 0x8E,
-	CLOCK_N8_CYCLES = 0x8F,
-	PULSE_CLOCK_IO_HIGH = 0x94,
-	PULSE_CLOCK_IO_LOW = 0x95,
-	CLOCK_N8_CYCLES_IO_HIGH = 0x9C,
-	CLOCK_N8_CYCLES_IO_LOW = 0x9D,
-	TRISTATE_IO = 0x9E,
-};
-
-/* Common clock rates */
-enum clock_rates {
-	ONE_HUNDRED_KHZ = 100000,
-	FOUR_HUNDRED_KHZ = 400000,
-	ONE_MHZ = 1000000,
-	TWO_MHZ = 2000000,
-	FIVE_MHZ = 5000000,
-	SIX_MHZ = 6000000,
-	TEN_MHZ = 10000000,
-	TWELVE_MHZ = 12000000,
-	FIFTEEN_MHZ = 15000000,
-	THIRTY_MHZ = 30000000,
-	SIXTY_MHZ = 60000000
-};
-
-#define NULL_CONTEXT_ERROR_MSG	"NULL MPSSE context pointer!"
-#define SPI_TRANSFER_SIZE	512
-#define SPI_RW_SIZE		(63 * 1024)
-#define SETUP_DELAY		25000
-#define LATENCY_MS		2
-#define USB_TIMEOUT		120000
-#define CHUNK_SIZE		65535
-#define MAX_SETUP_COMMANDS	10
-
-/* SK and CS are high, GPIO1 is reset on the FPGA hookup, all others low */
-#define DEFAULT_PORT            (SK | CS | GPIO1)
-/* SK/DO/CS and GPIOs are outputs, DI is an input */
-#define DEFAULT_TRIS            (SK | DO | CS | GPIO0 | GPIO1 | GPIO2 | GPIO3)
-
-static struct vid_pid {
-	int vid;
-	int pid;
-	char *description;
-	int use_B;
-} supported_devices[] = {
-	{
-	0x0403, 0x6010, "FT2232 Future Technology Devices International, Ltd",
-	1},
-	{
-	0x0403, 0x6011, "FT4232 Future Technology Devices International, Ltd"},
-	{
-	0x0403, 0x6014,
-		    "FT232H Future Technology Devices International, Ltd"},
-	/* These devices are based on FT2232 chips, but have not been tested. */
-	{
-	0x0403, 0x8878, "Bus Blaster v2 (channel A)"}, {
-	0x0403, 0x8879, "Bus Blaster v2 (channel B)"}, {
-	0x0403, 0xBDC8, "Turtelizer JTAG/RS232 Adapter A"}, {
-	0x0403, 0xCFF8, "Amontec JTAGkey"}, {
-	0x0403, 0x8A98, "TIAO Multi Protocol Adapter"}, {
-	0x15BA, 0x0003, "Olimex Ltd. OpenOCD JTAG"}, {
-	0x15BA, 0x0004, "Olimex Ltd. OpenOCD JTAG TINY"}, {
-	0x18d1, 0x0304, "Google UltraDebug", 1}, {
-	0, 0, NULL}
-};
-
-/*
- * Enables or disables flushing of the FTDI chip's RX buffers after each read
- * operation. Flushing is disable by default.
- *
- * @mpsse - MPSSE context pointer.
- * @tf    - Set to 1 to enable flushing, or 0 to disable flushing.
- *
- * Returns void.
- */
-static void FlushAfterRead(struct mpsse_context *mpsse, int tf)
-{
-	mpsse->flush_after_read = tf;
-}
-
-/*
- * Enable / disable internal loopback.
- *
- * @mpsse  - MPSSE context pointer.
- * @enable - Zero to disable loopback, 1 to enable loopback.
- *
- * Returns MPSSE_OK on success.
- * Returns MPSSE_FAIL on failure.
- */
-static int SetLoopback(struct mpsse_context *mpsse, int enable)
-{
-	unsigned char buf[1] = { 0 };
-	int retval = MPSSE_FAIL;
-
-	if (is_valid_context(mpsse)) {
-		if (enable)
-			buf[0] = LOOPBACK_START;
-		else
-			buf[0] = LOOPBACK_END;
-
-		retval = raw_write(mpsse, buf, 1);
-	}
-
-	return retval;
-}
-
-/*
- * Sets the appropriate divisor for the desired clock frequency.
- *
- * @mpsse - MPSSE context pointer.
- * @freq  - Desired clock frequency in hertz.
- *
- * Returns MPSSE_OK on success.
- * Returns MPSSE_FAIL on failure.
- */
-static int SetClock(struct mpsse_context *mpsse, uint32_t freq)
-{
-	int retval = MPSSE_FAIL;
-	uint32_t system_clock = 0;
-	uint16_t divisor = 0;
-	unsigned char buf[CMD_SIZE] = { 0 };
-
-	/*
-	 * Do not call is_valid_context() here, as the FTDI chip may not be
-	 * completely configured when SetClock is called
-	 */
-	if (!mpsse)
-		return retval;
-
-	if (freq > SIX_MHZ) {
-		buf[0] = TCK_X5;
-		system_clock = SIXTY_MHZ;
-	} else {
-		buf[0] = TCK_D5;
-		system_clock = TWELVE_MHZ;
-	}
-
-	if (raw_write(mpsse, buf, 1) == MPSSE_OK) {
-		if (freq <= 0)
-			divisor = 0xFFFF;
-		else
-			divisor = freq2div(system_clock, freq);
-
-		buf[0] = TCK_DIVISOR;
-		buf[1] = (divisor & 0xFF);
-		buf[2] = ((divisor >> 8) & 0xFF);
-
-		if (raw_write(mpsse, buf, 3) == MPSSE_OK) {
-			mpsse->clock = div2freq(system_clock, divisor);
-			retval = MPSSE_OK;
-		}
-	}
-
-	return retval;
-}
-
-/*
- * Sets the appropriate transmit and receive commands based on the requested
- * mode and byte order.
- *
- * @mpsse     - MPSSE context pointer.
- * @endianness - MPSSE_MSB or MPSSE_LSB.
- *
- * Returns MPSSE_OK on success.
- * Returns MPSSE_FAIL on failure.
- */
-static int SetMode(struct mpsse_context *mpsse, int endianness)
-{
-	int retval = MPSSE_OK, i = 0, setup_commands_size = 0;
-	unsigned char buf[CMD_SIZE] = { 0 };
-	unsigned char setup_commands[CMD_SIZE * MAX_SETUP_COMMANDS] = { 0 };
-
-	/*
-	 * Do not call is_valid_context() here, as the FTDI chip may not be
-	 * completely configured when SetMode is called
-	 */
-	if (!mpsse)
-		return MPSSE_FAIL;
-
-	/* Read and write commands need to include endianness */
-	mpsse->tx = MPSSE_DO_WRITE | endianness;
-	mpsse->rx = MPSSE_DO_READ | endianness;
-	mpsse->txrx = MPSSE_DO_WRITE | MPSSE_DO_READ | endianness;
-
-	/*
-	 * Clock, data out, chip select pins are outputs; all others are
-	 * inputs.
-	 */
-	mpsse->tris = DEFAULT_TRIS;
-
-	/* Clock and chip select pins idle high; all others are low */
-	mpsse->pidle = mpsse->pstart = mpsse->pstop = DEFAULT_PORT;
-
-	/* During reads and writes the chip select pin is brought low */
-	mpsse->pstart &= ~CS;
-
-	/* Disable FTDI internal loopback */
-	SetLoopback(mpsse, 0);
-
-	/* Ensure adaptive clock is disabled */
-	setup_commands[setup_commands_size++] = DISABLE_ADAPTIVE_CLOCK;
-
-	switch (mpsse->mode) {
-	case SPI0:
-		/* SPI mode 0 clock idles low */
-		mpsse->pidle &= ~SK;
-		mpsse->pstart &= ~SK;
-		mpsse->pstop &= ~SK;
-
-		/*
-		 * SPI mode 0 propogates data on the falling edge and read
-		 * data on the rising edge of the clock
-		 */
-		mpsse->tx |= MPSSE_WRITE_NEG;
-		mpsse->rx &= ~MPSSE_READ_NEG;
-		mpsse->txrx |= MPSSE_WRITE_NEG;
-		mpsse->txrx &= ~MPSSE_READ_NEG;
-		break;
-	default:
-		fprintf(stderr, "%s:%d attempt to set an unsupported mode %d\n",
-			__func__, __LINE__, mpsse->mode);
-		retval = MPSSE_FAIL;
-	}
-
-	/* Send any setup commands to the chip */
-	if ((retval == MPSSE_OK) && (setup_commands_size > 0))
-		retval = raw_write(mpsse, setup_commands, setup_commands_size);
-
-	if (retval == MPSSE_OK) {
-		/* Set the idle pin states */
-		set_bits_low(mpsse, mpsse->pidle);
-
-		/* All GPIO pins are outputs, set low */
-		mpsse->trish = 0xFF;
-		mpsse->gpioh = 0x00;
-
-		buf[i++] = SET_BITS_HIGH;
-		buf[i++] = mpsse->gpioh;
-		buf[i++] = mpsse->trish;
-
-		retval = raw_write(mpsse, buf, i);
-	}
-
-	return retval;
-}
-
-/*
- * Open device by VID/PID/index
- *
- * @vid         - Device vendor ID.
- * @pid         - Device product ID.
- * @freq        - Clock frequency to use for the specified mode.
- * @endianness   - Specifies how data is clocked in/out (MSB, LSB).
- * @interface   - FTDI interface to use (IFACE_A - IFACE_D).
- * @description - Device product description (set to NULL if not needed).
- * @serial      - Device serial number (set to NULL if not needed).
- * @index       - Device index (set to 0 if not needed).
- *
- * Returns a pointer to an MPSSE context structure.
- * On success, mpsse->open will be set to 1.
- * On failure, mpsse->open will be set to 0.
- */
-static struct mpsse_context *OpenIndex(int vid,
-				       int pid,
-				       int freq,
-				       int endianness,
-				       int interface,
-				       const char *description,
-				       const char *serial, int index)
-{
-	int status = 0;
-	struct mpsse_context *mpsse = NULL;
-	enum modes mode = SPI0;	/* Let's use this mode at all times. */
-
-	mpsse = malloc(sizeof(struct mpsse_context));
-	if (!mpsse)
-		return NULL;
-
-	memset(mpsse, 0, sizeof(struct mpsse_context));
-
-	/* Legacy; flushing is no longer needed, so disable it by default. */
-	FlushAfterRead(mpsse, 0);
-
-	/* ftdilib initialization */
-	if (ftdi_init(&mpsse->ftdi)) {
-		fprintf(stderr, "%s:%d failed to initialize FTDI\n",
-			__func__, __LINE__);
-		free(mpsse);
-		return NULL;
-	}
-
-	mpsse->ftdi_initialized = 1;
-
-	/* Set the FTDI interface  */
-	ftdi_set_interface(&mpsse->ftdi, interface);
-
-	/* Try opening the specified device */
-	if (ftdi_usb_open_desc_index
-	    (&mpsse->ftdi, vid, pid, description, serial, index)) {
-		Close(mpsse);
-		return NULL;
-	}
-
-	mpsse->mode = mode;
-	mpsse->vid = vid;
-	mpsse->pid = pid;
-	mpsse->status = STOPPED;
-	mpsse->endianness = endianness;
-	mpsse->xsize = SPI_RW_SIZE;
-
-	status |= ftdi_usb_reset(&mpsse->ftdi);
-	status |= ftdi_set_latency_timer(&mpsse->ftdi, LATENCY_MS);
-	status |= ftdi_write_data_set_chunksize(&mpsse->ftdi, CHUNK_SIZE);
-	status |= ftdi_read_data_set_chunksize(&mpsse->ftdi, CHUNK_SIZE);
-	status |= ftdi_set_bitmode(&mpsse->ftdi, 0, BITMODE_RESET);
-
-	if (status) {
-		fprintf(stderr,
-			"%s:%d failed setting basic config for %4.4x:%4.4x\n",
-			__func__, __LINE__, vid, pid);
-		Close(mpsse);
-		return NULL;
-	}
-	/* Set the read and write timeout periods */
-	set_timeouts(mpsse, USB_TIMEOUT);
-
-	ftdi_set_bitmode(&mpsse->ftdi, 0, BITMODE_MPSSE);
-
-	if ((SetClock(mpsse, freq) != MPSSE_OK)
-	    || (SetMode(mpsse, endianness) != MPSSE_OK)) {
-		fprintf(stderr,
-			"%s:%d failed setting clock/mode for %4.4x:%4.4x\n",
-			__func__, __LINE__, vid, pid);
-		Close(mpsse);
-		return NULL;
-	}
-
-	mpsse->open = 1;
-
-	/* Give the chip a few mS to initialize */
-	usleep(SETUP_DELAY);
-
-	/*
-	 * Not all FTDI chips support all the commands that SetMode may have
-	 * sent. This clears out any errors from unsupported commands that
-	 * might have been sent during set up.
-	 */
-	ftdi_usb_purge_buffers(&mpsse->ftdi);
-
-	return mpsse;
-}
-
-/*
- * Opens and initializes the first FTDI device found.
- *
- * @freq      - Clock frequency to use for the specified mode.
- * @endianness - Specifies how data is clocked in/out (MSB, LSB).
- * @serial    - Serial number of the USB device (NULL if not needed).
- *
- * Returns a pointer to an MPSSE context structure.
- * On success, mpsse->open will be set to 1.
- * On failure, mpsse->open will be set to 0.
- */
-struct mpsse_context *MPSSE(int freq, int endianness, const char *serial)
-{
-	int i = 0;
-	struct mpsse_context *mpsse = NULL;
-
-	for (i = 0; supported_devices[i].vid != 0; i++) {
-		mpsse = OpenIndex(supported_devices[i].vid,
-				  supported_devices[i].pid, freq, endianness,
-				  supported_devices[i].use_B ?
-					IFACE_B : IFACE_A,
-				  NULL, serial, 0);
-		if (!mpsse)
-			continue;
-
-		if (mpsse->open) {
-			mpsse->description = supported_devices[i].description;
-			break;
-		}
-		/*
-		 * If there is another device still left to try, free
-		 * the context pointer and try again
-		 */
-		if (supported_devices[i + 1].vid != 0) {
-			Close(mpsse);
-			mpsse = NULL;
-		}
-	}
-
-	return mpsse;
-}
-
-/*
- * Closes the device, deinitializes libftdi, and frees the MPSSE context
- * pointer.
- *
- * @mpsse - MPSSE context pointer.
- *
- * Returns void.
- */
-
-void Close(struct mpsse_context *mpsse)
-{
-	if (!mpsse)
-		return;
-
-	if (mpsse->open) {
-		ftdi_usb_close(&mpsse->ftdi);
-		ftdi_set_bitmode(&mpsse->ftdi, 0, BITMODE_RESET);
-	}
-
-	if (mpsse->ftdi_initialized)
-		ftdi_deinit(&mpsse->ftdi);
-
-	free(mpsse);
-}
-
-/*
- * Retrieves the last error string from libftdi.
- *
- * @mpsse - MPSSE context pointer.
- *
- * Returns a pointer to the last error string.
- */
-const char *ErrorString(struct mpsse_context *mpsse)
-{
-	if (mpsse)
-		return ftdi_get_error_string(&mpsse->ftdi);
-
-	return NULL_CONTEXT_ERROR_MSG;
-}
-
-/*
- * Send data start condition.
- *
- * @mpsse - MPSSE context pointer.
- *
- * Returns MPSSE_OK on success.
- * Returns MPSSE_FAIL on failure.
- */
-int Start(struct mpsse_context *mpsse)
-{
-	int status;
-
-	if (!is_valid_context(mpsse)) {
-		mpsse->status = STOPPED;
-		return MPSSE_FAIL;
-	}
-
-	/* Set the start condition */
-	status = set_bits_low(mpsse, mpsse->pstart);
-
-	if (status == MPSSE_OK)
-		mpsse->status = STARTED;
-
-	return status;
-}
-
-/*
- * Send data out via the selected serial protocol.
- *
- * @mpsse - MPSSE context pointer.
- * @data  - Buffer of data to send.
- * @size  - Size of data.
- *
- * Returns MPSSE_OK on success.
- * Returns MPSSE_FAIL on failure.
- */
-int Write(struct mpsse_context *mpsse, char *data, int size)
-{
-	int n = 0;
-
-	if (!is_valid_context(mpsse))
-		return MPSSE_FAIL;
-
-	if (!mpsse->mode)
-		return MPSSE_FAIL;
-
-	while (n < size) {
-		unsigned char *buf;
-		int retval, buf_size, txsize;
-
-		txsize = size - n;
-		if (txsize > mpsse->xsize)
-			txsize = mpsse->xsize;
-
-		buf = build_block_buffer(mpsse, mpsse->tx,
-					 (unsigned char *)(data + n),
-					 txsize, &buf_size);
-		if (!buf)
-			return MPSSE_FAIL;
-
-		retval = raw_write(mpsse, buf, buf_size);
-		n += txsize;
-		free(buf);
-
-		if (retval != MPSSE_OK)
-			return retval;
-
-	}
-
-	return MPSSE_OK;
-}
-
-/* Performs a read. For internal use only; see Read() and ReadBits(). */
-static char *InternalRead(struct mpsse_context *mpsse, int size)
-{
-	unsigned char *buf;
-	int n = 0;
-
-	if (!is_valid_context(mpsse))
-		return NULL;
-
-	if (!mpsse->mode)
-		return NULL;
-	buf = malloc(size);
-
-	if (!buf)
-		return NULL;
-
-	while (n < size) {
-		int rxsize, data_size, retval;
-		unsigned char *data;
-		unsigned char sbuf[SPI_RW_SIZE] = { 0 };
-
-		rxsize = size - n;
-		if (rxsize > mpsse->xsize)
-			rxsize = mpsse->xsize;
-
-		data = build_block_buffer(mpsse, mpsse->rx,
-					  sbuf, rxsize, &data_size);
-		if (!data) {
-			free(buf);
-			return NULL;
-		}
-
-		retval = raw_write(mpsse, data, data_size);
-		free(data);
-
-		if (retval != MPSSE_OK) {
-			free(buf);
-			return NULL;
-		}
-		n += raw_read(mpsse, buf + n, rxsize);
-	}
-
-	return (char *)buf;
-}
-
-/*
- * Reads data over the selected serial protocol.
- *
- * @mpsse - MPSSE context pointer.
- * @size  - Number of bytes to read.
- *
- * Returns a pointer to the read data on success.
- * Returns NULL on failure.
- */
-char *Read(struct mpsse_context *mpsse, int size)
-{
-	char *buf = NULL;
-
-	buf = InternalRead(mpsse, size);
-	return buf;
-}
-
-/*
- * Reads and writes data over the selected serial protocol (SPI only).
- *
- * @mpsse - MPSSE context pointer.
- * @data  - Buffer containing bytes to write.
- * @size  - Number of bytes to transfer.
- *
- * Returns a pointer to the read data on success.
- * Returns NULL on failure.
- */
-char *Transfer(struct mpsse_context *mpsse, char *data, int size)
-{
-	unsigned char *txdata = NULL, *buf = NULL;
-	int n = 0, data_size = 0, rxsize = 0, retval = MPSSE_OK;
-
-	if (!is_valid_context(mpsse))
-		return NULL;
-
-	buf = malloc(size);
-	if (!buf)
-		return NULL;
-
-	while (n < size) {
-		/*
-		 * When sending and receiving, FTDI chips don't seem to like
-		 * large data blocks. Limit the size of each block to
-		 * SPI_TRANSFER_SIZE
-		 */
-		rxsize = size - n;
-		if (rxsize > SPI_TRANSFER_SIZE)
-			rxsize = SPI_TRANSFER_SIZE;
-
-		txdata = build_block_buffer(mpsse, mpsse->txrx,
-					    (unsigned char *)(data + n),
-					    rxsize, &data_size);
-		if (!txdata) {
-			retval = MPSSE_FAIL;
-			break;
-		}
-		retval = raw_write(mpsse, txdata, data_size);
-		free(txdata);
-
-		if (retval != MPSSE_OK)
-			break;
-
-		n += raw_read(mpsse, (buf + n), rxsize);
-	}
-
-	if (retval != MPSSE_OK)
-		return NULL;
-
-	return (char *)buf;
-}
-
-/*
- * Send data stop condition.
- *
- * @mpsse - MPSSE context pointer.
- *
- * Returns MPSSE_OK on success.
- * Returns MPSSE_FAIL on failure.
- */
-int Stop(struct mpsse_context *mpsse)
-{
-	int retval = MPSSE_OK;
-
-	if (is_valid_context(mpsse)) {
-		/* Send the stop condition */
-		retval |= set_bits_low(mpsse, mpsse->pstop);
-
-		if (retval == MPSSE_OK) {
-			/* Restore the pins to their idle states */
-			retval |= set_bits_low(mpsse, mpsse->pidle);
-		}
-
-		mpsse->status = STOPPED;
-	} else {
-		retval = MPSSE_FAIL;
-		mpsse->status = STOPPED;
-	}
-
-	return retval;
-}
-
-/*
- * Sets the specified pin high.
- *
- * @mpsse - MPSSE context pointer.
- * @pin   - Pin number to set high.
- *
- * Returns MPSSE_OK on success.
- * Returns MPSSE_FAIL on failure.
- */
-int PinHigh(struct mpsse_context *mpsse, int pin)
-{
-	int retval = MPSSE_FAIL;
-
-	if (is_valid_context(mpsse))
-		retval = gpio_write(mpsse, pin, HIGH);
-
-	return retval;
-}
-
-/*
- * Sets the specified pin low.
- *
- * @mpsse - MPSSE context pointer.
- * @pin   - Pin number to set low.
- *
- * Returns MPSSE_OK on success.
- * Returns MPSSE_FAIL on failure.
- */
-int PinLow(struct mpsse_context *mpsse, int pin)
-{
-	int retval = MPSSE_FAIL;
-
-	if (is_valid_context(mpsse))
-		retval = gpio_write(mpsse, pin, LOW);
-
-	return retval;
-}
diff --git a/test/tpm_test/mpsse.h b/test/tpm_test/mpsse.h
deleted file mode 100644
index 2925dfe27a..0000000000
--- a/test/tpm_test/mpsse.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Based on Craig Heffner's version of Dec 27 2011, published on
- * https://github.com/devttys0/libmpsse
- */
-
-#ifndef __EC_TEST_TPM_TEST_MPSSE_H
-#define __EC_TEST_TPM_TEST_MPSSE_H
-
-#define MPSSE_OK		0
-#define MPSSE_FAIL		-1
-
-#define MSB			0x00
-#define LSB			0x08
-
-enum gpio_pins {
-	GPIOL0 = 0,
-	GPIOL1 = 1,
-	GPIOL2 = 2,
-	GPIOL3 = 3,
-	GPIOH0 = 4,
-	GPIOH1 = 5,
-	GPIOH2 = 6,
-	GPIOH3 = 7,
-	GPIOH4 = 8,
-	GPIOH5 = 9,
-	GPIOH6 = 10,
-	GPIOH7 = 11
-};
-
-struct mpsse_context;
-
-int Write(struct mpsse_context *mpsse, char *data, int size);
-int Stop(struct mpsse_context *mpsse);
-char *Transfer(struct mpsse_context *mpsse, char *data, int size);
-char *Read(struct mpsse_context *mpsse, int size);
-struct mpsse_context *MPSSE(int freq, int endianness, const char *serial);
-void Close(struct mpsse_context *mpsse);
-int PinHigh(struct mpsse_context *mpsse, int pin);
-int PinLow(struct mpsse_context *mpsse, int pin);
-int Start(struct mpsse_context *mpsse);
-
-#endif  /* ! __EC_TEST_TPM_TEST_MPSSE_H */
diff --git a/test/tpm_test/nist_entropy.sh b/test/tpm_test/nist_entropy.sh
deleted file mode 100755
index f69c5652cd..0000000000
--- a/test/tpm_test/nist_entropy.sh
+++ /dev/null
@@ -1,21 +0,0 @@
-#!/bin/bash
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-# NIST toolset needs sudo emerge dev-libs/libdivsufsort
-rm -rf /tmp/ea
-git clone --depth 1 https://github.com/usnistgov/SP800-90B_EntropyAssessment.git /tmp/ea/
-make -C /tmp/ea/cpp/ non_iid
-make -C /tmp/ea/cpp/ restart
-TRNG_OUT=/tmp/trng_output
-rm -f $TRNG_OUT
-./tpmtest.py -t
-if [ ! -f "$TRNG_OUT" ]; then
-    echo "$TRNG_OUT does not exist"
-    exit 1
-fi
-/tmp/ea/cpp/ea_non_iid -a $TRNG_OUT | tee ea_non_iid.log
-entropy=`grep min ea_non_iid.log | awk '{ print $5 }'`
-echo "Minimal entropy" $entropy
-/tmp/ea/cpp/ea_restart $TRNG_OUT $entropy | tee -a ea_non_iid.log
diff --git a/test/tpm_test/rsa1024.pem b/test/tpm_test/rsa1024.pem
deleted file mode 100644
index 3a349130f0..0000000000
--- a/test/tpm_test/rsa1024.pem
+++ /dev/null
@@ -1,15 +0,0 @@
------BEGIN RSA PRIVATE KEY-----
-MIICXAIBAAKBgQDfTq9zRZSYNDB+Jq1Ag/kXIbBOGw1qRM5OPi5yTJffiYo5ECWu
-IEzyOyCypRDdsmtiTqafkkrZhpfMcCA7ajJjyn9Z+1e2qZnp0C4PHNR9i6C9D9LV
-Ox8RtGqUz08KK0Tn+mskkbSCH/Z1tpHFoPYv1f8Qc5s09nqII6lCPKgkkQIDAQAB
-AoGBAJpthfQHqG1hmi+De8jj+3y9tXkuSCa3kpyVb/VndpgGO+qeehBjEhNqRICG
-mpVWb+C6V4x+1Ph9lbixyfiMxm7le6CvoE5OhNeXuVrdMuUr5YCzsr9W/wHc5qZs
-SoEdj+pL7SQI9GevDfL9Nz8xJfruNbDbZhH/SeHl/xvMww4JAkEA+V55ZUNwQINQ
-Crths4d7JI8qA1u1S5SUZ6qY1hRAkDykDW1YMcVC8S0VDufN5j7K2JQ3qkzW8yEu
-pP4deUTXswJBAOU+zUuXxZY5cJc6EKnDNQrWK/USjbLACxxfoAuGg6eQ6fgWkp/O
-E0wU6J5MJO//WCIG+c/9Gbcj+eOz43qbsKsCQFYw7Uyu7pGd0YCkG7Tt0wZj5WWb
-wSIKjPD36jO0dExmaV2quZ0aTXUG3Ax22pgGhB4vvL3EKVeH1JN6sb1EqjkCQC8X
-yqanxABLRnTaicfGASR7wMX0jMVWrDGk90TG2k7W9yluwaowdEhh1zOFouTmiJ1c
-3365mMnFizUapDVwvEcCQGqkxcod+m/s4Zq2a9DAyfN3FD2AtJ7QasveLXvR16Od
-MRa0hOWA8d3hh+eHU8DsJ+csEuKeDui3tV4kY0UTF0Y=
------END RSA PRIVATE KEY-----
diff --git a/test/tpm_test/rsa2048.pem b/test/tpm_test/rsa2048.pem
deleted file mode 100644
index 8031296fbd..0000000000
--- a/test/tpm_test/rsa2048.pem
+++ /dev/null
@@ -1,27 +0,0 @@
------BEGIN RSA PRIVATE KEY-----
-MIIEowIBAAKCAQEAnNdhLkOOFb7Nc5+39YZL45WQXIUZTB0uLO9uH+11Mg8KwXKf
-DHhQopmCU5C+ZCNJdXsM6y1ol9avsaoq3l6b4wYN8qzZ1x9Qbsld67TwwJgjBDBG
-ENzUa1fHMMMG3a9RbkBB+BDeSRhSsxjKSVCoOs22lHvb8S0FzlcLvjhIu8mxdja4
-qMziB1zIe8/P8Pqjxdc6XrL0v+rC7VEWopKcNqaGDiSlZhXnlyJQBP/JTbC8JwVe
-LPfv3F1YoTtgg7eMt9A2bVUuBSNjdEqXN6d4QO8+Zv26brNySiGCHzOtYgzyGtJq
-tafyUWkfOKVXmsWIZ+MRplNPsekHQd7o35OpmQIDAQABAoIBAE6dAh/fSouJvI8U
-4m8VZlpncBl/uUNWaPuq8ybbrd9ufLSj0Ca+86Pcj9908IleyoYxLDOA6ikZOa0y
-nxQglcBAG6OkkffqwTUWh5YKdpYCa6LA043GMk6vi67cQkfBhW5elPJS+ifnIiSU
-62e+HuSCkd5xCrgjGgLnzIIG0iYVVJdSzfU/bca5cDC+xYimsGUWnEyE4npu6ce9
-z0Un/BnGIx0riKJnH8LW06B5+7/qOKjfT7ybju4Et3wA15UaA4J66EG4sa9/8TCJ
-Vm0HEVV53WgPgghczCRHVGiG8fA/UhCt5BYzFgIhYuMvXesiW2S0KSJ0JCmpTGaE
-McqZlfUCgYEAyIBv9i/7SYt3OeI9PR9N+btUBg1xv1SxHqIgft3PIRbpwLqUAtKk
-Lng8+2Sg5+knZCkZdMV3u+FttIMdQ1qAcuw8MsMgLM73uvbGDPRW/d8hVfPiViWm
-s5aknLj9nOyH+toupPYPFOaBIoTnwB3RP+2wutjk6dQYM64pUXl50Q8CgYEAyEEq
-QvFqgawGq9C3wLvGE939Xjx3/sEudvCUwF0kizAN+CrHJngbgVpClq33DqQbLI84
-BgWNmG43ZbQsgOI41XnS6mLyMqx7iJDDTp5T5X7vE7Hj1UHRqRUEPGF0XhoAXIqL
-F9V4rV7gzzVjCpUecL6X8tN4BoqImyfIsrE9itcCgYA0NHzydPvQ4mdgwu9/Aq+i
-3ou6J7X+Q2b6uuwLHGXaD8U9UVdIhOAK2XPHYSQkPijrg2gFZ4UNfly6K4lrCB15
-zti9vuCZyinmnGpk5RnhcD+VybKdC6CkEg06YVBnk460Wira+NZkcsAc5M4Sz7C0
-HIdvnxm7aGYEzswjUqXNMQKBgEA49e7GMdwoaXNM2sGK9vmEJi/EwM8I8XffrDUN
-Kh0hajl+rqPdvSR86AIfBK7DXpupytPTkBeksUuCvwsOgh+klEnrNbWer3eaxag/
-CrT9QntUf7bzBuRtAxDCSGmteRQ0smsQYUVoujx56KuKK1sJJP4RZ9rhLvJjjfAQ
-+6W9AoGBAL0hOd3kCVY8kxDQry9M30lPZcftJga2IxTErBex60rA9ifmHLm4iFXt
-/e52/1OZVE4Cf7QFEFeSLiBA+U8I0FdV4VMyrfTpjKNVBIDB7JmskdhQbIPXOZzY
-fC2yxCmVsD6PjMDDlT//ck5AQVrktdDpwBj3OX7JSc31KOMBb8FU
------END RSA PRIVATE KEY-----
diff --git a/test/tpm_test/rsa4096.pem b/test/tpm_test/rsa4096.pem
deleted file mode 100644
index c1f82a2d38..0000000000
--- a/test/tpm_test/rsa4096.pem
+++ /dev/null
@@ -1,51 +0,0 @@
------BEGIN RSA PRIVATE KEY-----
-MIIJJwIBAAKCAgEAtNKrnPpCmjdwKuQth2d/FbYxBgbVWumOqdRta5K5Yzd9nPDK
-CkQZ8HGnTOCQnL5pSpxVGLNCQ9lsZf3RzyAMkjQnRkhYCxPN8WdwAn7nTKnY/UgX
-gPYBDmGwvu+HK3EOZYHBUM64ZdLX+nbEtxPZ7drWn54QslD0/fT57NgzVu/0ItPC
-uknVqQuwGKPZJs0ndmpyGzGsPULo2SbTkLs5ZLvqiQt6tIg56unKGYxC+2kiyo69
-bHO3iKChGaj6lFUgb4C612kSH3SC7K/uKK/N2q0bW1TkK+8MTdGr1wPEpJmgvH6d
-PC80O9Xdau2mGZODvuLUb5L/Vaf3Z+vjRtPnbcAplSu/3bSTu0UB/FMhzp+LkIAJ
-uhpuCIcVtHSj3LvbRfI4IIXDnkpFHnUYBUKGrUfmqu2Imp83o7jHmTXiqI6dLrzy
-ZEjDY08c0EXDQaG+5cKkXUXwA4PJgExo8NHa8VGB1f7E6IrWMpU42Dva94xcawH0
-bhK1tjbj0apJRGrz5nsZffg1yy24YlTPLWazf+A3ZRmC1ogkwjF+H27aSyivXivo
-NLLcx9GVDJTnCaDtqpEvkW/wAN8NRu/SWXtlzqLtiuIe0OGTcn8YeRg188rbAV8J
-SCFF/olE7Qd5aDLY1ougxtz5VolbzjUF6cFKHiQLyHMYGWvt+T6SkvILdSUCAwEA
-AQKCAgBWbFY/edE5WgPPTC2CiPHRk7mMktmIURaxjukZQBBBHnV3/BHkpDXtmLSI
-ZtBXSh6S3XNCkfK68QEBIjYUE9JOUoTu74a9DKMinPiJCNRN7OPb8ofhSDKrB//s
-0hi9p5Rk6YZWs+aoLAS0He3ZPrCrISvxMB/0ygK+GkcVbyPiil8aAjIQzVdEK2Tn
-8e/Ivsb8rtWIr84NnZwipY76nrFItxPamlT0UiO0ZjcEzOf6t348Z8qbOhdfQr6c
-wAm7uY/+Gv2yFPLne81TiKaAZb4ypQftN/6yDNfJncvOwWtL7G1Jig5mhH0nmAjy
-oVEA6mNOaaV1CkHlU5lI3xJKeN8j5DWPVu8+12gCjQgasBwo9aEMgNZgu+GYJEt5
-YnNZNz0aYcwajRGrOnrGQBMdlj97ZGgJQableFqWxjxx2TnUuhr6jj62fyMB5FBh
-zVeFesLIvoobRXxYC7vpe1oyfy+hJjTrmDlhQiBLpX4zoAJG3qgqtuQPWrM3dkjT
-yESNSMoLIL2WA2XclWWlH/nQDYGB3HzJtJeg+M6+EDRxTL+pgTgsWxDIkizSiI1c
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-qRb0ERIBmR+R+BTkBXQFUc65mTuV4XCxmvA4Nz8ydk5+4Gh6s5PZwiazeDH87Eup
-awv2b/pZsxr8twKCAQEAx6Qj7vE5MRSFA193+OnLgp4pikCosEzv+xcXmaYeuVmi
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-XPMwIywASDPVhq0jbd5wuvYx33KUKhavwy1J5RwLrliQ4OgoQDWgtrUKeEocaSHe
-vqXDAoIBAEYG4UPTAUih9fY06pQ5DdWHPPLtsz4D/rmIZBLVHjnNovx9hOEB+dmK
-p+RdT2ELiqDPvifspR2QdDJ2N645btInNDpQMyHMrAKd08hHycId71spjRrc3T1l
-OG4ihTEkpzJhuTrJbScbyHdAVPpSTns+Skg9C5KnFi/MC1bYRJ2QRLIGi0PoFrvC
-/a6DDtuNofQl4AFNBMCo8ZwWlQBfeI7QKDQn/pe4J4Z/lC57d9futfyNLsu59fnG
-u1XmXbfUimloRf2Wssct7Tl2f0FGxBpdbaBzrMlyD9dhkSbX54phLRS6eyL6Xeqf
-k64Y1nRX74xnrNIJjNQF5/D9eoB5H5kCggEADkSUsvqv/hpMMNRIyXsIKIko4EW3
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-tJTCuklNgKWiooQIN/Wm0t82a3M3kvcqIbCCG5EGDL/7Uh48DQGpSOGehEn6TYnG
-W42bU/Beq38LQzN4eQPhsiqmOwNJ4dYc4NqpOIkXi6UTCe9hDcpX2p7hG55zkpOA
-2rxpIOeOVSRHHOE8RsfIr8FzO/823P1mOQe5xMSCf1GSj6I+bopT0chL9JsiHLZa
-1VPn744OJjXt14LAt4byOVvgdSoQAgxWEC0LhmHYNXt8/YRMJiZ01bc1dA==
------END RSA PRIVATE KEY-----
diff --git a/test/tpm_test/rsa768.pem b/test/tpm_test/rsa768.pem
deleted file mode 100644
index 5be0fdf5f7..0000000000
--- a/test/tpm_test/rsa768.pem
+++ /dev/null
@@ -1,12 +0,0 @@
------BEGIN RSA PRIVATE KEY-----
-MIIBywIBAAJhALDb7UbZMvB81CAj0jVahhfbJHI2MzvCZIukSW50/vrSggzEEjpI
-Z+EVzJTfRBtOwBi6RhtRLOIPwDJ37V+L5aMA5jwtpxCJU6grM3Q49zYA/d1bvXvB
-fOF1kCt4LTmFaQIDAQABAmEArq25UCWMG1yfQtM+dnXfRUarW6bOuXJJTmbIJDGn
-+WHbEvLBMhF7kCOwuUU/Bl2i1zUP3fwD342Ra4P5We5nHhognov49uKy9SlxTCJU
-z36XvHAk3W1S/hfZ1kF7dkABAjEA1glkyPNcAsfGR05/Q50xRnozhaCkFuoie81k
-m1Dspy9+z+tpKTSOt7Wzun+bAX1pAjEA04iSLdXGKfTwLmHwYK2pRhGpDGkUMQk2
-i3AbEZsmOTQ0/fGaiVFjCsZgC7oYjsgBAjA8oMSPt3+kufoMUMvz1x8SG6NkgrB4
-XTIPZ4rMBAxE/0sokkJjjaOvniSe+25o6aECMQCG3oedM7SSIbpVSFqTuYW4yB/J
-auHV1fLx+ns3wX0gcdnro3SNYtfMEelA8NkhiAECMGVIqAN9qpGW5qAyikDrmzod
-7+wMrWHefpWKsih4+MIvAo7WOOoM+1UasRwVGhMxFQ==
------END RSA PRIVATE KEY-----
diff --git a/test/tpm_test/rsa_test.py b/test/tpm_test/rsa_test.py
deleted file mode 100644
index e411df57b0..0000000000
--- a/test/tpm_test/rsa_test.py
+++ /dev/null
@@ -1,818 +0,0 @@
-#!/usr/bin/env python2
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-"""Module for testing rsa functions using extended commands."""
-
-import binascii
-import Crypto
-import Crypto.Hash.SHA
-import Crypto.Hash.SHA256
-import Crypto.Hash.SHA384
-import Crypto.Hash.SHA512
-from Crypto.PublicKey import RSA
-import Crypto.Signature.PKCS1_PSS
-import Crypto.Signature.PKCS1_v1_5
-import hashlib
-import os
-import rsa
-import struct
-
-import subcmd
-import utils
-
-_MODULE_DIR = os.path.dirname(os.path.abspath(__file__))
-
-_RSA_OPCODES = {
-  'ENCRYPT': 0x00,
-  'DECRYPT': 0x01,
-  'SIGN': 0x02,
-  'VERIFY': 0x03,
-  'KEYGEN': 0x04,
-  'KEYTEST': 0x05,
-  'PRIMEGEN': 0x06,
-  'X509_VERIFY': 0x07
-}
-
-
-# TPM2 ALG codes.
-_RSA_PADDING = {
-  'NONE': 0x00,
-  'PKCS1-SSA': 0x14,
-  'PKCS1-ES': 0x15,
-  'PKCS1-PSS': 0x16,
-  'OAEP': 0x17,
-  'NULL': 0x10,
-}
-
-
-# TPM2 ALG codes.
-_HASH = {
-  'NONE': 0x00,
-  'SHA1': 0x04,
-  'SHA256': 0x0B,
-  'SHA384': 0x0C,
-  'SHA512': 0x0D,
-}
-
-_SIGNER = {
-  'PKCS1-SSA': Crypto.Signature.PKCS1_v1_5,
-  'PKCS1-PSS': Crypto.Signature.PKCS1_PSS,
-}
-
-_HASHER = {
-  'SHA1':   Crypto.Hash.SHA,
-  'SHA256': Crypto.Hash.SHA256,
-  'SHA384': Crypto.Hash.SHA384,
-  'SHA512': Crypto.Hash.SHA512,
-}
-
-_KEYS = {
-  768:  RSA.importKey(open(os.path.join(_MODULE_DIR, 'rsa768.pem')).read()),
-  1024: RSA.importKey(open(os.path.join(_MODULE_DIR, 'rsa1024.pem')).read()),
-  2048: RSA.importKey(open(os.path.join(_MODULE_DIR, 'rsa2048.pem')).read()),
-  4096: RSA.importKey(open(os.path.join(_MODULE_DIR, 'rsa4096.pem')).read()),
-}
-
-# Command format.
-#
-#   0x00 OP
-#   0x00 PADDING
-#   0x00 HASHING
-#   0x00 MSB KEY LEN
-#   0x00 LSB KEY LEN
-#   0x00 MSB IN LEN
-#   0x00 LSB IN LEN
-#   .... IN
-#   0x00 MSB DIGEST LEN
-#   0x00 LSB DIGEST LEN
-#   .... DIGEST
-#
-_RSA_CMD_FORMAT = '{o:c}{p:c}{h:c}{kl:s}{ml:s}{msg}{dl:s}{dig}'
-
-
-def _decrypt_cmd(padding, hashing, key_len, msg):
-  op = _RSA_OPCODES['DECRYPT']
-  msg_len = len(msg)
-  return _RSA_CMD_FORMAT.format(o=op, p=padding, h=hashing,
-                                kl=struct.pack('>H', key_len),
-                                ml=struct.pack('>H', msg_len), msg=msg,
-                                dl='', dig='')
-
-
-def _encrypt_cmd(padding, hashing, key_len, msg):
-  op = _RSA_OPCODES['ENCRYPT']
-  msg_len = len(msg)
-  return _RSA_CMD_FORMAT.format(o=op, p=padding, h=hashing,
-                                kl=struct.pack('>H', key_len),
-                                ml=struct.pack('>H', msg_len), msg=msg,
-                                dl='', dig='')
-
-
-def _sign_cmd(padding, hashing, key_len, digest):
-  op = _RSA_OPCODES['SIGN']
-  digest_len = len(digest)
-  return _RSA_CMD_FORMAT.format(o=op, p=padding, h=hashing,
-                                kl=struct.pack('>H', key_len),
-                                ml=struct.pack('>H', digest_len), msg=digest,
-                                dl='', dig='')
-
-
-def _verify_cmd(padding, hashing, key_len, sig, digest):
-  op = _RSA_OPCODES['VERIFY']
-  sig_len = len(sig)
-  digest_len = len(digest)
-  return _RSA_CMD_FORMAT.format(o=op, p=padding, h=hashing,
-                                kl=struct.pack('>H', key_len),
-                                ml=struct.pack('>H', sig_len), msg=sig,
-                                dl=struct.pack('>H', digest_len), dig=digest)
-
-
-def _keytest_cmd(key_len):
-  op = _RSA_OPCODES['KEYTEST']
-  return _RSA_CMD_FORMAT.format(o=op, p=0, h=_HASH['NONE'],
-                                kl=struct.pack('>H', key_len),
-                                ml=struct.pack('>H', 0), msg='',
-                                dl='', dig='')
-
-
-def _keygen_cmd(key_len, e, label):
-  op = _RSA_OPCODES['KEYGEN']
-  padding = _RSA_PADDING['NONE']
-  hashing = _HASH['NONE']
-  return _RSA_CMD_FORMAT.format(o=op, p=padding, h=hashing,
-                                kl=struct.pack('>H', key_len),
-                                ml=struct.pack('>H', len(label)), msg=label,
-                                dl=struct.pack('>H', 0), dig='')
-
-
-def _primegen_cmd(seed):
-  op = _RSA_OPCODES['PRIMEGEN']
-  padding = _RSA_PADDING['NONE']
-  hashing = _HASH['NONE']
-  return _RSA_CMD_FORMAT.format(o=op, p=padding, h=hashing,
-                                kl=struct.pack('>H', len(seed) * 8 * 2),
-                                ml=struct.pack('>H', len(seed)), msg=seed,
-                                dl=struct.pack('>H', 0), dig='')
-
-def _x509_verify_cmd(key_len):
-  op = _RSA_OPCODES['X509_VERIFY']
-  padding = _RSA_PADDING['NONE']
-  hashing = _HASH['NONE']
-  return _RSA_CMD_FORMAT.format(o=op, p=padding, h=hashing,
-                                kl=struct.pack('>H', key_len),
-                                ml=struct.pack('>H', 0), msg='',
-                                dl=struct.pack('>H', 0), dig='')
-
-
-_PRIMES = [2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47, 53,
-           59, 61, 67, 71, 73, 79, 83, 89, 97, 101, 103, 107, 109, 113, 127, 131,
-           137, 139, 149, 151, 157, 163, 167, 173, 179, 181, 191, 193, 197, 199,
-           211, 223, 227, 229, 233, 239, 241, 251, 257, 263, 269, 271, 277, 281,
-           283, 293, 307, 311, 313, 317, 331, 337, 347, 349, 353, 359, 367, 373,
-           379, 383, 389, 397, 401, 409, 419, 421, 431, 433, 439, 443, 449, 457,
-           461, 463, 467, 479, 487, 491, 499, 503, 509, 521, 523, 541, 547, 557,
-           563, 569, 571, 577, 587, 593, 599, 601, 607, 613, 617, 619, 631, 641,
-           643, 647, 653, 659, 661, 673, 677, 683, 691, 701, 709, 719, 727, 733,
-           739, 743, 751, 757, 761, 769, 773, 787, 797, 809, 811, 821, 823, 827,
-           829, 839, 853, 857, 859, 863, 877, 881, 883, 887, 907, 911, 919, 929,
-           937, 941, 947, 953, 967, 971, 977, 983, 991, 997, 1009, 1013, 1019,
-           1021, 1031, 1033, 1039, 1049, 1051, 1061, 1063, 1069, 1087, 1091,
-           1093, 1097, 1103, 1109, 1117, 1123, 1129, 1151, 1153, 1163, 1171,
-           1181, 1187, 1193, 1201, 1213, 1217, 1223, 1229, 1231, 1237, 1249,
-           1259, 1277, 1279, 1283, 1289, 1291, 1297, 1301, 1303, 1307, 1319,
-           1321, 1327, 1361, 1367, 1373, 1381, 1399, 1409, 1423, 1427, 1429,
-           1433, 1439, 1447, 1451, 1453, 1459, 1471, 1481, 1483, 1487, 1489,
-           1493, 1499, 1511, 1523, 1531, 1543, 1549, 1553, 1559, 1567, 1571,
-           1579, 1583, 1597, 1601, 1607, 1609, 1613, 1619, 1621, 1627, 1637,
-           1657, 1663, 1667, 1669, 1693, 1697, 1699, 1709, 1721, 1723, 1733,
-           1741, 1747, 1753, 1759, 1777, 1783, 1787, 1789, 1801, 1811, 1823,
-           1831, 1847, 1861, 1867, 1871, 1873, 1877, 1879, 1889, 1901, 1907,
-           1913, 1931, 1933, 1949, 1951, 1973, 1979, 1987, 1993, 1997, 1999,
-           2003, 2011, 2017, 2027, 2029, 2039, 2053, 2063, 2069, 2081, 2083,
-           2087, 2089, 2099, 2111, 2113, 2129, 2131, 2137, 2141, 2143, 2153,
-           2161, 2179, 2203, 2207, 2213, 2221, 2237, 2239, 2243, 2251, 2267,
-           2269, 2273, 2281, 2287, 2293, 2297, 2309, 2311, 2333, 2339, 2341,
-           2347, 2351, 2357, 2371, 2377, 2381, 2383, 2389, 2393, 2399, 2411,
-           2417, 2423, 2437, 2441, 2447, 2459, 2467, 2473, 2477, 2503, 2521,
-           2531, 2539, 2543, 2549, 2551, 2557, 2579, 2591, 2593, 2609, 2617,
-           2621, 2633, 2647, 2657, 2659, 2663, 2671, 2677, 2683, 2687, 2689,
-           2693, 2699, 2707, 2711, 2713, 2719, 2729, 2731, 2741, 2749, 2753,
-           2767, 2777, 2789, 2791, 2797, 2801, 2803, 2819, 2833, 2837, 2843,
-           2851, 2857, 2861, 2879, 2887, 2897, 2903, 2909, 2917, 2927, 2939,
-           2953, 2957, 2963, 2969, 2971, 2999, 3001, 3011, 3019, 3023, 3037,
-           3041, 3049, 3061, 3067, 3079, 3083, 3089, 3109, 3119, 3121, 3137,
-           3163, 3167, 3169, 3181, 3187, 3191, 3203, 3209, 3217, 3221, 3229,
-           3251, 3253, 3257, 3259, 3271, 3299, 3301, 3307, 3313, 3319, 3323,
-           3329, 3331, 3343, 3347, 3359, 3361, 3371, 3373, 3389, 3391, 3407,
-           3413, 3433, 3449, 3457, 3461, 3463, 3467, 3469, 3491, 3499, 3511,
-           3517, 3527, 3529, 3533, 3539, 3541, 3547, 3557, 3559, 3571, 3581,
-           3583, 3593, 3607, 3613, 3617, 3623, 3631, 3637, 3643, 3659, 3671,
-           3673, 3677, 3691, 3697, 3701, 3709, 3719, 3727, 3733, 3739, 3761,
-           3767, 3769, 3779, 3793, 3797, 3803, 3821, 3823, 3833, 3847, 3851,
-           3853, 3863, 3877, 3881, 3889, 3907, 3911, 3917, 3919, 3923, 3929,
-           3931, 3943, 3947, 3967, 3989, 4001, 4003, 4007, 4013, 4019, 4021,
-           4027, 4049, 4051, 4057, 4073, 4079, 4091, 4093, 4099, 4111, 4127,
-           4129, 4133, 4139, 4153, 4157, 4159, 4177, 4201, 4211, 4217, 4219,
-           4229, 4231, 4241, 4243, 4253, 4259, 4261, 4271, 4273, 4283, 4289,
-           4297, 4327, 4337, 4339, 4349, 4357, 4363, 4373, 4391, 4397, 4409,
-           4421, 4423, 4441, 4447, 4451, 4457, 4463, 4481, 4483, 4493, 4507,
-           4513, 4517, 4519, 4523, 4547, 4549, 4561, 4567, 4583, 4591, 4597,
-           4603, 4621, 4637, 4639, 4643, 4649, 4651, 4657, 4663, 4673, 4679,
-           4691, 4703, 4721, 4723, 4729, 4733, 4751, 4759, 4783, 4787, 4789,
-           4793, 4799, 4801, 4813, 4817, 4831, 4861, 4871, 4877, 4889, 4903,
-           4909, 4919, 4931, 4933, 4937, 4943, 4951, 4957, 4967, 4969, 4973,
-           4987, 4993, 4999, 5003, 5009, 5011, 5021, 5023, 5039, 5051, 5059,
-           5077, 5081, 5087, 5099, 5101, 5107, 5113, 5119, 5147, 5153, 5167,
-           5171, 5179, 5189, 5197, 5209, 5227, 5231, 5233, 5237, 5261, 5273,
-           5279, 5281, 5297, 5303, 5309, 5323, 5333, 5347, 5351, 5381, 5387,
-           5393, 5399, 5407, 5413, 5417, 5419, 5431, 5437, 5441, 5443, 5449,
-           5471, 5477, 5479, 5483, 5501, 5503, 5507, 5519, 5521, 5527, 5531,
-           5557, 5563, 5569, 5573, 5581, 5591, 5623, 5639, 5641, 5647, 5651,
-           5653, 5657, 5659, 5669, 5683, 5689, 5693, 5701, 5711, 5717, 5737,
-           5741, 5743, 5749, 5779, 5783, 5791, 5801, 5807, 5813, 5821, 5827,
-           5839, 5843, 5849, 5851, 5857, 5861, 5867, 5869, 5879, 5881, 5897,
-           5903, 5923, 5927, 5939, 5953, 5981, 5987, 6007, 6011, 6029, 6037,
-           6043, 6047, 6053, 6067, 6073, 6079, 6089, 6091, 6101, 6113, 6121,
-           6131, 6133, 6143, 6151, 6163, 6173, 6197, 6199, 6203, 6211, 6217,
-           6221, 6229, 6247, 6257, 6263, 6269, 6271, 6277, 6287, 6299, 6301,
-           6311, 6317, 6323, 6329, 6337, 6343, 6353, 6359, 6361, 6367, 6373,
-           6379, 6389, 6397, 6421, 6427, 6449, 6451, 6469, 6473, 6481, 6491,
-           6521, 6529, 6547, 6551, 6553, 6563, 6569, 6571, 6577, 6581, 6599,
-           6607, 6619, 6637, 6653, 6659, 6661, 6673, 6679, 6689, 6691, 6701,
-           6703, 6709, 6719, 6733, 6737, 6761, 6763, 6779, 6781, 6791, 6793,
-           6803, 6823, 6827, 6829, 6833, 6841, 6857, 6863, 6869, 6871, 6883,
-           6899, 6907, 6911, 6917, 6947, 6949, 6959, 6961, 6967, 6971, 6977,
-           6983, 6991, 6997, 7001, 7013, 7019, 7027, 7039, 7043, 7057, 7069,
-           7079, 7103, 7109, 7121, 7127, 7129, 7151, 7159, 7177, 7187, 7193,
-           7207, 7211, 7213, 7219, 7229, 7237, 7243, 7247, 7253, 7283, 7297,
-           7307, 7309, 7321, 7331, 7333, 7349, 7351, 7369, 7393, 7411, 7417,
-           7433, 7451, 7457, 7459, 7477, 7481, 7487, 7489, 7499, 7507, 7517,
-           7523, 7529, 7537, 7541, 7547, 7549, 7559, 7561, 7573, 7577, 7583,
-           7589, 7591, 7603, 7607, 7621, 7639, 7643, 7649, 7669, 7673, 7681,
-           7687, 7691, 7699, 7703, 7717, 7723, 7727, 7741, 7753, 7757, 7759,
-           7789, 7793, 7817, 7823, 7829, 7841, 7853, 7867, 7873, 7877, 7879,
-           7883, 7901, 7907, 7919, 7927, 7933, 7937, 7949, 7951, 7963, 7993,
-           8009, 8011, 8017, 8039, 8053, 8059, 8069, 8081, 8087, 8089, 8093,
-           8101, 8111, 8117, 8123, 8147, 8161, 8167, 8171, 8179, 8191, 8209,
-           8219, 8221, 8231, 8233, 8237, 8243, 8263, 8269, 8273, 8287, 8291,
-           8293, 8297, 8311, 8317, 8329, 8353, 8363, 8369, 8377, 8387, 8389,
-           8419, 8423, 8429, 8431, 8443, 8447, 8461, 8467, 8501, 8513, 8521,
-           8527, 8537, 8539, 8543, 8563, 8573, 8581, 8597, 8599, 8609, 8623,
-           8627, 8629, 8641, 8647, 8663, 8669, 8677, 8681, 8689, 8693, 8699,
-           8707, 8713, 8719, 8731, 8737, 8741, 8747, 8753, 8761, 8779, 8783,
-           8803, 8807, 8819, 8821, 8831, 8837, 8839, 8849, 8861, 8863, 8867,
-           8887, 8893, 8923, 8929, 8933, 8941, 8951, 8963, 8969, 8971, 8999,
-           9001, 9007, 9011, 9013, 9029, 9041, 9043, 9049, 9059, 9067, 9091,
-           9103, 9109, 9127, 9133, 9137, 9151, 9157, 9161, 9173, 9181, 9187,
-           9199, 9203, 9209, 9221, 9227, 9239, 9241, 9257, 9277, 9281, 9283,
-           9293, 9311, 9319, 9323, 9337, 9341, 9343, 9349, 9371, 9377, 9391,
-           9397, 9403, 9413, 9419, 9421, 9431, 9433, 9437, 9439, 9461, 9463,
-           9467, 9473, 9479, 9491, 9497, 9511, 9521, 9533, 9539, 9547, 9551,
-           9587, 9601, 9613, 9619, 9623, 9629, 9631, 9643, 9649, 9661, 9677,
-           9679, 9689, 9697, 9719, 9721, 9733, 9739, 9743, 9749, 9767, 9769,
-           9781, 9787, 9791, 9803, 9811, 9817, 9829, 9833, 9839, 9851, 9857,
-           9859, 9871, 9883, 9887, 9901, 9907, 9923, 9929, 9931, 9941, 9949,
-           9967, 9973, 10007, 10009, 10037, 10039, 10061, 10067, 10069, 10079,
-           10091, 10093, 10099, 10103, 10111, 10133, 10139, 10141, 10151, 10159,
-           10163, 10169, 10177, 10181, 10193, 10211, 10223, 10243, 10247, 10253,
-           10259, 10267, 10271, 10273, 10289, 10301, 10303, 10313, 10321, 10331,
-           10333, 10337, 10343, 10357, 10369, 10391, 10399, 10427, 10429, 10433,
-           10453, 10457, 10459, 10463, 10477, 10487, 10499, 10501, 10513, 10529,
-           10531, 10559, 10567, 10589, 10597, 10601, 10607, 10613, 10627, 10631,
-           10639, 10651, 10657, 10663, 10667, 10687, 10691, 10709, 10711, 10723,
-           10729, 10733, 10739, 10753, 10771, 10781, 10789, 10799, 10831, 10837,
-           10847, 10853, 10859, 10861, 10867, 10883, 10889, 10891, 10903, 10909,
-           10937, 10939, 10949, 10957, 10973, 10979, 10987, 10993, 11003, 11027,
-           11047, 11057, 11059, 11069, 11071, 11083, 11087, 11093, 11113, 11117,
-           11119, 11131, 11149, 11159, 11161, 11171, 11173, 11177, 11197, 11213,
-           11239, 11243, 11251, 11257, 11261, 11273, 11279, 11287, 11299, 11311,
-           11317, 11321, 11329, 11351, 11353, 11369, 11383, 11393, 11399, 11411,
-           11423, 11437, 11443, 11447, 11467, 11471, 11483, 11489, 11491, 11497,
-           11503, 11519, 11527, 11549, 11551, 11579, 11587, 11593, 11597, 11617,
-           11621, 11633, 11657, 11677, 11681, 11689, 11699, 11701, 11717, 11719,
-           11731, 11743, 11777, 11779, 11783, 11789, 11801, 11807, 11813, 11821,
-           11827, 11831, 11833, 11839, 11863, 11867, 11887, 11897, 11903, 11909,
-           11923, 11927, 11933, 11939, 11941, 11953, 11959, 11969, 11971, 11981,
-           11987, 12007, 12011, 12037, 12041, 12043, 12049, 12071, 12073, 12097,
-           12101, 12107, 12109, 12113, 12119, 12143, 12149, 12157, 12161, 12163,
-           12197, 12203, 12211, 12227, 12239, 12241, 12251, 12253, 12263, 12269,
-           12277, 12281, 12289, 12301, 12323, 12329, 12343, 12347, 12373, 12377,
-           12379, 12391, 12401, 12409, 12413, 12421, 12433, 12437, 12451, 12457,
-           12473, 12479, 12487, 12491, 12497, 12503, 12511, 12517, 12527, 12539,
-           12541, 12547, 12553, 12569, 12577, 12583, 12589, 12601, 12611, 12613,
-           12619, 12637, 12641, 12647, 12653, 12659, 12671, 12689, 12697, 12703,
-           12713, 12721, 12739, 12743, 12757, 12763, 12781, 12791, 12799, 12809,
-           12821, 12823, 12829, 12841, 12853, 12889, 12893, 12899, 12907, 12911,
-           12917, 12919, 12923, 12941, 12953, 12959, 12967, 12973, 12979, 12983,
-           13001, 13003, 13007, 13009, 13033, 13037, 13043, 13049, 13063, 13093,
-           13099, 13103, 13109, 13121, 13127, 13147, 13151, 13159, 13163, 13171,
-           13177, 13183, 13187, 13217, 13219, 13229, 13241, 13249, 13259, 13267,
-           13291, 13297, 13309, 13313, 13327, 13331, 13337, 13339, 13367, 13381,
-           13397, 13399, 13411, 13417, 13421, 13441, 13451, 13457, 13463, 13469,
-           13477, 13487, 13499, 13513, 13523, 13537, 13553, 13567, 13577, 13591,
-           13597, 13613, 13619, 13627, 13633, 13649, 13669, 13679, 13681, 13687,
-           13691, 13693, 13697, 13709, 13711, 13721, 13723, 13729, 13751, 13757,
-           13759, 13763, 13781, 13789, 13799, 13807, 13829, 13831, 13841, 13859,
-           13873, 13877, 13879, 13883, 13901, 13903, 13907, 13913, 13921, 13931,
-           13933, 13963, 13967, 13997, 13999, 14009, 14011, 14029, 14033, 14051,
-           14057, 14071, 14081, 14083, 14087, 14107, 14143, 14149, 14153, 14159,
-           14173, 14177, 14197, 14207, 14221, 14243, 14249, 14251, 14281, 14293,
-           14303, 14321, 14323, 14327, 14341, 14347, 14369, 14387, 14389, 14401,
-           14407, 14411, 14419, 14423, 14431, 14437, 14447, 14449, 14461, 14479,
-           14489, 14503, 14519, 14533, 14537, 14543, 14549, 14551, 14557, 14561,
-           14563, 14591, 14593, 14621, 14627, 14629, 14633, 14639, 14653, 14657,
-           14669, 14683, 14699, 14713, 14717, 14723, 14731, 14737, 14741, 14747,
-           14753, 14759, 14767, 14771, 14779, 14783, 14797, 14813, 14821, 14827,
-           14831, 14843, 14851, 14867, 14869, 14879, 14887, 14891, 14897, 14923,
-           14929, 14939, 14947, 14951, 14957, 14969, 14983, 15013, 15017, 15031,
-           15053, 15061, 15073, 15077, 15083, 15091, 15101, 15107, 15121, 15131,
-           15137, 15139, 15149, 15161, 15173, 15187, 15193, 15199, 15217, 15227,
-           15233, 15241, 15259, 15263, 15269, 15271, 15277, 15287, 15289, 15299,
-           15307, 15313, 15319, 15329, 15331, 15349, 15359, 15361, 15373, 15377,
-           15383, 15391, 15401, 15413, 15427, 15439, 15443, 15451, 15461, 15467,
-           15473, 15493, 15497, 15511, 15527, 15541, 15551, 15559, 15569, 15581,
-           15583, 15601, 15607, 15619, 15629, 15641, 15643, 15647, 15649, 15661,
-           15667, 15671, 15679, 15683, 15727, 15731, 15733, 15737, 15739, 15749,
-           15761, 15767, 15773, 15787, 15791, 15797, 15803, 15809, 15817, 15823,
-           15859, 15877, 15881, 15887, 15889, 15901, 15907, 15913, 15919, 15923,
-           15937, 15959, 15971, 15973, 15991, 16001, 16007, 16033, 16057, 16061,
-           16063, 16067, 16069, 16073, 16087, 16091, 16097, 16103, 16111, 16127,
-           16139, 16141, 16183, 16187, 16189, 16193, 16217, 16223, 16229, 16231,
-           16249, 16253, 16267, 16273, 16301, 16319, 16333, 16339, 16349, 16361,
-           16363, 16369, 16381, 16411, 16417, 16421, 16427, 16433, 16447, 16451,
-           16453, 16477, 16481, 16487, 16493, 16519, 16529, 16547, 16553, 16561,
-           16567, 16573, 16603, 16607, 16619, 16631, 16633, 16649, 16651, 16657,
-           16661, 16673, 16691, 16693, 16699, 16703, 16729, 16741, 16747, 16759,
-           16763, 16787, 16811, 16823, 16829, 16831, 16843, 16871, 16879, 16883,
-           16889, 16901, 16903, 16921, 16927, 16931, 16937, 16943, 16963, 16979,
-           16981, 16987, 16993, 17011, 17021, 17027, 17029, 17033, 17041, 17047,
-           17053, 17077, 17093, 17099, 17107, 17117, 17123, 17137, 17159, 17167,
-           17183, 17189, 17191, 17203, 17207, 17209, 17231, 17239, 17257, 17291,
-           17293, 17299, 17317, 17321, 17327, 17333, 17341, 17351, 17359, 17377,
-           17383, 17387, 17389, 17393, 17401, 17417, 17419, 17431, 17443, 17449,
-           17467, 17471, 17477, 17483, 17489, 17491, 17497, 17509, 17519, 17539,
-           17551, 17569, 17573, 17579, 17581, 17597, 17599, 17609, 17623, 17627,
-           17657, 17659, 17669, 17681, 17683, 17707, 17713, 17729, 17737, 17747,
-           17749, 17761, 17783, 17789, 17791, 17807, 17827, 17837, 17839, 17851,
-           17863, 17881, 17891, 17903, 17909, 17911, 17921, 17923, 17929, 17939,
-           17957, 17959, 17971, 17977, 17981, 17987, 17989, 18013, 18041, 18043,
-           18047, 18049, 18059, 18061, 18077, 18089, 18097, 18119, 18121, 18127,
-           18131, 18133, 18143, 18149, 18169, 18181, 18191, 18199, 18211, 18217,
-           18223, 18229, 18233, 18251, 18253, 18257, 18269, 18287, 18289, 18301,
-           18307, 18311, 18313, 18329, 18341, 18353, 18367, 18371, 18379, 18397,
-           18401, 18413, 18427, 18433, 18439, 18443, 18451, 18457, 18461, 18481,
-           18493, 18503, 18517, 18521, 18523, 18539, 18541, 18553, 18583, 18587,
-           18593, 18617, 18637, 18661, 18671, 18679, 18691, 18701, 18713, 18719,
-           18731, 18743, 18749, 18757, 18773, 18787, 18793, 18797, 18803, 18839,
-           18859, 18869, 18899, 18911, 18913, 18917, 18919, 18947, 18959, 18973,
-           18979, 19001, 19009, 19013, 19031, 19037, 19051, 19069, 19073, 19079,
-           19081, 19087, 19121, 19139, 19141, 19157, 19163, 19181, 19183, 19207,
-           19211, 19213, 19219, 19231, 19237, 19249, 19259, 19267, 19273, 19289,
-           19301, 19309, 19319, 19333, 19373, 19379, 19381, 19387, 19391, 19403,
-           19417, 19421, 19423, 19427, 19429, 19433, 19441, 19447, 19457, 19463,
-           19469, 19471, 19477, 19483, 19489, 19501, 19507, 19531, 19541, 19543,
-           19553, 19559, 19571, 19577, 19583, 19597, 19603, 19609, 19661, 19681,
-           19687, 19697, 19699, 19709, 19717, 19727, 19739, 19751, 19753, 19759,
-           19763, 19777, 19793, 19801, 19813, 19819, 19841, 19843, 19853, 19861,
-           19867, 19889, 19891, 19913, 19919, 19927, 19937, 19949, 19961, 19963,
-           19973, 19979, 19991, 19993, 19997, 20011, 20021, 20023, 20029, 20047,
-           20051, 20063, 20071, 20089, 20101, 20107, 20113, 20117, 20123, 20129,
-           20143, 20147, 20149, 20161, 20173, 20177, 20183, 20201, 20219, 20231,
-           20233, 20249, 20261, 20269, 20287, 20297, 20323, 20327, 20333, 20341,
-           20347, 20353, 20357, 20359, 20369, 20389, 20393, 20399, 20407, 20411,
-           20431, 20441, 20443, 20477, 20479, 20483, 20507, 20509, 20521, 20533,
-           20543, 20549, 20551, 20563, 20593, 20599, 20611, 20627, 20639, 20641,
-           20663, 20681, 20693, 20707, 20717, 20719, 20731, 20743, 20747, 20749,
-           20753, 20759, 20771, 20773, 20789, 20807, 20809, 20849, 20857, 20873,
-           20879, 20887, 20897, 20899, 20903, 20921, 20929, 20939, 20947, 20959,
-           20963, 20981, 20983, 21001, 21011, 21013, 21017, 21019, 21023, 21031,
-           21059, 21061, 21067, 21089, 21101, 21107, 21121, 21139, 21143, 21149,
-           21157, 21163, 21169, 21179, 21187, 21191, 21193, 21211, 21221, 21227,
-           21247, 21269, 21277, 21283, 21313, 21317, 21319, 21323, 21341, 21347,
-           21377, 21379, 21383, 21391, 21397, 21401, 21407, 21419, 21433, 21467,
-           21481, 21487, 21491, 21493, 21499, 21503, 21517, 21521, 21523, 21529,
-           21557, 21559, 21563, 21569, 21577, 21587, 21589, 21599, 21601, 21611,
-           21613, 21617, 21647, 21649, 21661, 21673, 21683, 21701, 21713, 21727,
-           21737, 21739, 21751, 21757, 21767, 21773, 21787, 21799, 21803, 21817,
-           21821, 21839, 21841, 21851, 21859, 21863, 21871, 21881, 21893, 21911,
-           21929, 21937, 21943, 21961, 21977, 21991, 21997, 22003, 22013, 22027,
-           22031, 22037, 22039, 22051, 22063, 22067, 22073, 22079, 22091, 22093,
-           22109, 22111, 22123, 22129, 22133, 22147, 22153, 22157, 22159, 22171,
-           22189, 22193, 22229, 22247, 22259, 22271, 22273, 22277, 22279, 22283,
-           22291, 22303, 22307, 22343, 22349, 22367, 22369, 22381, 22391, 22397,
-           22409, 22433, 22441, 22447, 22453, 22469, 22481, 22483, 22501, 22511,
-           22531, 22541, 22543, 22549, 22567, 22571, 22573, 22613, 22619, 22621,
-           22637, 22639, 22643, 22651, 22669, 22679, 22691, 22697, 22699, 22709,
-           22717, 22721, 22727, 22739, 22741, 22751, 22769, 22777, 22783, 22787,
-           22807, 22811, 22817, 22853, 22859, 22861, 22871, 22877, 22901, 22907,
-           22921, 22937, 22943, 22961, 22963, 22973, 22993, 23003, 23011, 23017,
-           23021, 23027, 23029, 23039, 23041, 23053, 23057, 23059, 23063, 23071,
-           23081, 23087, 23099, 23117, 23131, 23143, 23159, 23167, 23173, 23189,
-           23197, 23201, 23203, 23209, 23227, 23251, 23269, 23279, 23291, 23293,
-           23297, 23311, 23321, 23327, 23333, 23339, 23357, 23369, 23371, 23399,
-           23417, 23431, 23447, 23459, 23473, 23497, 23509, 23531, 23537, 23539,
-           23549, 23557, 23561, 23563, 23567, 23581, 23593, 23599, 23603, 23609,
-           23623, 23627, 23629, 23633, 23663, 23669, 23671, 23677, 23687, 23689,
-           23719, 23741, 23743, 23747, 23753, 23761, 23767, 23773, 23789, 23801,
-           23813, 23819, 23827, 23831, 23833, 23857, 23869, 23873, 23879, 23887,
-           23893, 23899, 23909, 23911, 23917, 23929, 23957, 23971, 23977, 23981,
-           23993, 24001, 24007, 24019, 24023, 24029, 24043, 24049, 24061, 24071,
-           24077, 24083, 24091, 24097, 24103, 24107, 24109, 24113, 24121, 24133,
-           24137, 24151, 24169, 24179, 24181, 24197, 24203, 24223, 24229, 24239,
-           24247, 24251, 24281, 24317, 24329, 24337, 24359, 24371, 24373, 24379,
-           24391, 24407, 24413, 24419, 24421, 24439, 24443, 24469, 24473, 24481,
-           24499, 24509, 24517, 24527, 24533, 24547, 24551, 24571, 24593, 24611,
-           24623, 24631, 24659, 24671, 24677, 24683, 24691, 24697, 24709, 24733,
-           24749, 24763, 24767, 24781, 24793, 24799, 24809, 24821, 24841, 24847,
-           24851, 24859, 24877, 24889, 24907, 24917, 24919, 24923, 24943, 24953,
-           24967, 24971, 24977, 24979, 24989, 25013, 25031, 25033, 25037, 25057,
-           25073, 25087, 25097, 25111, 25117, 25121, 25127, 25147, 25153, 25163,
-           25169, 25171, 25183, 25189, 25219, 25229, 25237, 25243, 25247, 25253,
-           25261, 25301, 25303, 25307, 25309, 25321, 25339, 25343, 25349, 25357,
-           25367, 25373, 25391, 25409, 25411, 25423, 25439, 25447, 25453, 25457,
-           25463, 25469, 25471, 25523, 25537, 25541, 25561, 25577, 25579, 25583,
-           25589, 25601, 25603, 25609, 25621, 25633, 25639, 25643, 25657, 25667,
-           25673, 25679, 25693, 25703, 25717, 25733, 25741, 25747, 25759, 25763,
-           25771, 25793, 25799, 25801, 25819, 25841, 25847, 25849, 25867, 25873,
-           25889, 25903, 25913, 25919, 25931, 25933, 25939, 25943, 25951, 25969,
-           25981, 25997, 25999, 26003, 26017, 26021, 26029, 26041, 26053, 26083,
-           26099, 26107, 26111, 26113, 26119, 26141, 26153, 26161, 26171, 26177,
-           26183, 26189, 26203, 26209, 26227, 26237, 26249, 26251, 26261, 26263,
-           26267, 26293, 26297, 26309, 26317, 26321, 26339, 26347, 26357, 26371,
-           26387, 26393, 26399, 26407, 26417, 26423, 26431, 26437, 26449, 26459,
-           26479, 26489, 26497, 26501, 26513, 26539, 26557, 26561, 26573, 26591,
-           26597, 26627, 26633, 26641, 26647, 26669, 26681, 26683, 26687, 26693,
-           26699, 26701, 26711, 26713, 26717, 26723, 26729, 26731, 26737, 26759,
-           26777, 26783, 26801, 26813, 26821, 26833, 26839, 26849, 26861, 26863,
-           26879, 26881, 26891, 26893, 26903, 26921, 26927, 26947, 26951, 26953,
-           26959, 26981, 26987, 26993, 27011, 27017, 27031, 27043, 27059, 27061,
-           27067, 27073, 27077, 27091, 27103, 27107, 27109, 27127, 27143, 27179,
-           27191, 27197, 27211, 27239, 27241, 27253, 27259, 27271, 27277, 27281,
-           27283, 27299, 27329, 27337, 27361, 27367, 27397, 27407, 27409, 27427,
-           27431, 27437, 27449, 27457, 27479, 27481, 27487, 27509, 27527, 27529,
-           27539, 27541, 27551, 27581, 27583, 27611, 27617, 27631, 27647, 27653,
-           27673, 27689, 27691, 27697, 27701, 27733, 27737, 27739, 27743, 27749,
-           27751, 27763, 27767, 27773, 27779, 27791, 27793, 27799, 27803, 27809,
-           27817, 27823, 27827, 27847, 27851, 27883, 27893, 27901, 27917, 27919,
-           27941, 27943, 27947, 27953, 27961, 27967, 27983, 27997, 28001, 28019,
-           28027, 28031, 28051, 28057, 28069, 28081, 28087, 28097, 28099, 28109,
-           28111, 28123, 28151, 28163, 28181, 28183, 28201, 28211, 28219, 28229,
-           28277, 28279, 28283, 28289, 28297, 28307, 28309, 28319, 28349, 28351,
-           28387, 28393, 28403, 28409, 28411, 28429, 28433, 28439, 28447, 28463,
-           28477, 28493, 28499, 28513, 28517, 28537, 28541, 28547, 28549, 28559,
-           28571, 28573, 28579, 28591, 28597, 28603, 28607, 28619, 28621, 28627,
-           28631, 28643, 28649, 28657, 28661, 28663, 28669, 28687, 28697, 28703,
-           28711, 28723, 28729, 28751, 28753, 28759, 28771, 28789, 28793, 28807,
-           28813, 28817, 28837, 28843, 28859, 28867, 28871, 28879, 28901, 28909,
-           28921, 28927, 28933, 28949, 28961, 28979, 29009, 29017, 29021, 29023,
-           29027, 29033, 29059, 29063, 29077, 29101, 29123, 29129, 29131, 29137,
-           29147, 29153, 29167, 29173, 29179, 29191, 29201, 29207, 29209, 29221,
-           29231, 29243, 29251, 29269, 29287, 29297, 29303, 29311, 29327, 29333,
-           29339, 29347, 29363, 29383, 29387, 29389, 29399, 29401, 29411, 29423,
-           29429, 29437, 29443, 29453, 29473, 29483, 29501, 29527, 29531, 29537,
-           29567, 29569, 29573, 29581, 29587, 29599, 29611, 29629, 29633, 29641,
-           29663, 29669, 29671, 29683, 29717, 29723, 29741, 29753, 29759, 29761,
-           29789, 29803, 29819, 29833, 29837, 29851, 29863, 29867, 29873, 29879,
-           29881, 29917, 29921, 29927, 29947, 29959, 29983, 29989, 30011, 30013,
-           30029, 30047, 30059, 30071, 30089, 30091, 30097, 30103, 30109, 30113,
-           30119, 30133, 30137, 30139, 30161, 30169, 30181, 30187, 30197, 30203,
-           30211, 30223, 30241, 30253, 30259, 30269, 30271, 30293, 30307, 30313,
-           30319, 30323, 30341, 30347, 30367, 30389, 30391, 30403, 30427, 30431,
-           30449, 30467, 30469, 30491, 30493, 30497, 30509, 30517, 30529, 30539,
-           30553, 30557, 30559, 30577, 30593, 30631, 30637, 30643, 30649, 30661,
-           30671, 30677, 30689, 30697, 30703, 30707, 30713, 30727, 30757, 30763,
-           30773, 30781, 30803, 30809, 30817, 30829, 30839, 30841, 30851, 30853,
-           30859, 30869, 30871, 30881, 30893, 30911, 30931, 30937, 30941, 30949,
-           30971, 30977, 30983, 31013, 31019, 31033, 31039, 31051, 31063, 31069,
-           31079, 31081, 31091, 31121, 31123, 31139, 31147, 31151, 31153, 31159,
-           31177, 31181, 31183, 31189, 31193, 31219, 31223, 31231, 31237, 31247,
-           31249, 31253, 31259, 31267, 31271, 31277, 31307, 31319, 31321, 31327,
-           31333, 31337, 31357, 31379, 31387, 31391, 31393, 31397, 31469, 31477,
-           31481, 31489, 31511, 31513, 31517, 31531, 31541, 31543, 31547, 31567,
-           31573, 31583, 31601, 31607, 31627, 31643, 31649, 31657, 31663, 31667,
-           31687, 31699, 31721, 31723, 31727, 31729, 31741, 31751, 31769, 31771,
-           31793, 31799, 31817, 31847, 31849, 31859, 31873, 31883, 31891, 31907,
-           31957, 31963, 31973, 31981, 31991, 32003, 32009, 32027, 32029, 32051,
-           32057, 32059, 32063, 32069, 32077, 32083, 32089, 32099, 32117, 32119,
-           32141, 32143, 32159, 32173, 32183, 32189, 32191, 32203, 32213, 32233,
-           32237, 32251, 32257, 32261, 32297, 32299, 32303, 32309, 32321, 32323,
-           32327, 32341, 32353, 32359, 32363, 32369, 32371, 32377, 32381, 32401,
-           32411, 32413, 32423, 32429, 32441, 32443, 32467, 32479, 32491, 32497,
-           32503, 32507, 32531, 32533, 32537, 32561, 32563, 32569, 32573, 32579,
-           32587, 32603, 32609, 32611, 32621, 32633, 32647, 32653, 32687, 32693,
-           32707, 32713, 32717, 32719, 32749, 32771, 32779, 32783, 32789, 32797,
-           32801, 32803, 32831, 32833, 32839, 32843, 32869, 32887, 32909, 32911,
-           32917, 32933, 32939, 32941, 32957, 32969, 32971, 32983, 32987, 32993,
-           32999, 33013, 33023, 33029, 33037, 33049, 33053, 33071, 33073, 33083,
-           33091, 33107, 33113, 33119, 33149, 33151, 33161, 33179, 33181, 33191,
-           33199, 33203, 33211, 33223, 33247, 33287, 33289, 33301, 33311, 33317,
-           33329, 33331, 33343, 33347, 33349, 33353, 33359, 33377, 33391, 33403,
-           33409, 33413, 33427, 33457, 33461, 33469, 33479, 33487, 33493, 33503,
-           33521, 33529, 33533, 33547, 33563, 33569, 33577, 33581, 33587, 33589,
-           33599, 33601, 33613, 33617, 33619, 33623, 33629, 33637, 33641, 33647,
-           33679, 33703, 33713, 33721, 33739, 33749, 33751, 33757, 33767, 33769,
-           33773, 33791, 33797, 33809, 33811, 33827, 33829, 33851, 33857, 33863,
-           33871, 33889, 33893, 33911, 33923, 33931, 33937, 33941, 33961, 33967,
-           33997, 34019, 34031, 34033, 34039, 34057, 34061, 34123, 34127, 34129,
-           34141, 34147, 34157, 34159, 34171, 34183, 34211, 34213, 34217, 34231,
-           34253, 34259, 34261, 34267, 34273, 34283, 34297, 34301, 34303, 34313,
-           34319, 34327, 34337, 34351, 34361, 34367, 34369, 34381, 34403, 34421,
-           34429, 34439, 34457, 34469, 34471, 34483, 34487, 34499, 34501, 34511,
-           34513, 34519, 34537, 34543, 34549, 34583, 34589, 34591, 34603, 34607,
-           34613, 34631, 34649, 34651, 34667, 34673, 34679, 34687, 34693, 34703,
-           34721, 34729, 34739, 34747, 34757, 34759, 34763, 34781, 34807, 34819,
-           34841, 34843, 34847, 34849, 34871, 34877, 34883, 34897, 34913, 34919,
-           34939, 34949, 34961, 34963, 34981, 35023, 35027, 35051, 35053, 35059,
-           35069, 35081, 35083, 35089, 35099, 35107, 35111, 35117, 35129, 35141,
-           35149, 35153, 35159, 35171, 35201, 35221, 35227, 35251, 35257, 35267,
-           35279, 35281, 35291, 35311, 35317, 35323, 35327, 35339, 35353, 35363,
-           35381, 35393, 35401, 35407, 35419, 35423, 35437, 35447, 35449, 35461,
-           35491, 35507, 35509, 35521, 35527, 35531, 35533, 35537, 35543, 35569,
-           35573, 35591, 35593, 35597, 35603, 35617, 35671, 35677, 35729, 35731,
-           35747, 35753, 35759, 35771, 35797, 35801, 35803, 35809, 35831, 35837,
-           35839, 35851, 35863, 35869, 35879, 35897, 35899, 35911, 35923, 35933,
-           35951, 35963, 35969, 35977, 35983, 35993, 35999, 36007, 36011, 36013,
-           36017, 36037, 36061, 36067, 36073, 36083, 36097, 36107, 36109, 36131,
-           36137, 36151, 36161, 36187, 36191, 36209, 36217, 36229, 36241, 36251,
-           36263, 36269, 36277, 36293, 36299, 36307, 36313, 36319, 36341, 36343,
-           36353, 36373, 36383, 36389, 36433, 36451, 36457, 36467, 36469, 36473,
-           36479, 36493, 36497, 36523, 36527, 36529, 36541, 36551, 36559, 36563,
-           36571, 36583, 36587, 36599, 36607, 36629, 36637, 36643, 36653, 36671,
-           36677, 36683, 36691, 36697, 36709, 36713, 36721, 36739, 36749, 36761,
-           36767, 36779, 36781, 36787, 36791, 36793, 36809, 36821, 36833, 36847,
-           36857, 36871, 36877, 36887, 36899, 36901, 36913, 36919, 36923, 36929,
-           36931, 36943, 36947, 36973, 36979, 36997, 37003, 37013, 37019, 37021,
-           37039, 37049, 37057, 37061, 37087, 37097, 37117, 37123, 37139, 37159,
-           37171, 37181, 37189, 37199, 37201, 37217, 37223, 37243, 37253, 37273,
-           37277, 37307, 37309, 37313, 37321, 37337, 37339, 37357, 37361, 37363,
-           37369, 37379, 37397, 37409, 37423, 37441, 37447, 37463, 37483, 37489,
-           37493, 37501, 37507, 37511, 37517, 37529, 37537, 37547, 37549, 37561,
-           37567, 37571, 37573, 37579, 37589, 37591, 37607, 37619, 37633, 37643,
-           37649, 37657, 37663, 37691, 37693, 37699, 37717, 37747, 37781, 37783,
-           37799, 37811, 37813, 37831, 37847, 37853, 37861, 37871, 37879, 37889,
-           37897, 37907, 37951, 37957, 37963, 37967, 37987, 37991, 37993, 37997,
-           38011, 38039, 38047, 38053, 38069, 38083, 38113, 38119, 38149, 38153,
-           38167, 38177, 38183, 38189, 38197, 38201, 38219, 38231, 38237, 38239,
-           38261, 38273, 38281, 38287, 38299, 38303, 38317, 38321, 38327, 38329,
-           38333, 38351, 38371, 38377, 38393, 38431, 38447, 38449, 38453, 38459,
-           38461, 38501, 38543, 38557, 38561, 38567, 38569, 38593, 38603, 38609,
-           38611, 38629, 38639, 38651, 38653, 38669, 38671, 38677, 38693, 38699,
-           38707, 38711, 38713, 38723, 38729, 38737, 38747, 38749, 38767, 38783,
-           38791, 38803, 38821, 38833, 38839, 38851, 38861, 38867, 38873]
-
-
-def _prime_from_seed(seed):
-  ROUNDS = 7
-
-  def _window(s, primes):
-    w = [0] * 4096
-    for i in primes:
-      rem = s % i
-      if rem != 0:
-        rem = i - rem
-      for j in range(rem, len(w), i):
-        w[j] = 1
-    return w
-
-  # Set LSB, and top two bits.
-  candidate = chr(ord(seed[0]) | 192) + seed[1:-1] + chr(ord(seed[-1]) | 1)
-  candidate = int(binascii.b2a_hex(candidate), 16)
-  assert len(bin(candidate)[2:]) == len(seed) * 8
-  w = _window(candidate, _PRIMES[:4096])
-  for i, bit in enumerate(w):
-    if not bit:
-      if rsa.prime.randomized_primality_testing(candidate + i, ROUNDS):
-        return candidate + i
-  return None
-
-
-#
-# TEST VECTORS.
-#
-_ENCRYPT_INPUTS = (
-  ('OAEP', 'SHA1', 768),
-  ('OAEP', 'SHA256', 768),
-  ('OAEP', 'SHA256', 1024),
-  ('PKCS1-ES', 'NONE', 768),
-  ('PKCS1-ES', 'NONE', 2048),
-  ('NULL', 'NONE', 768),
-)
-
-
-_SIGN_INPUTS = (
-  ('PKCS1-SSA', 'SHA1', 768),
-  ('PKCS1-SSA', 'SHA256', 768),
-  ('PKCS1-SSA', 'SHA256', 1024),
-  ('PKCS1-SSA', 'SHA384', 2048),
-  ('PKCS1-SSA', 'SHA512', 2048),
-  ('PKCS1-PSS', 'SHA1', 768),
-  ('PKCS1-PSS', 'SHA256', 768),
-  ('PKCS1-PSS', 'SHA256', 2048),
-)
-
-_VERIFY_INPUTS = (
-  ('PKCS1-SSA', 'SHA1', 768),
-  ('PKCS1-SSA', 'SHA256', 768),
-  ('PKCS1-SSA', 'SHA256', 1024),
-  ('PKCS1-SSA', 'SHA384', 2048),
-  ('PKCS1-SSA', 'SHA512', 4096),
-  ('PKCS1-PSS', 'SHA1', 768),
-  ('PKCS1-PSS', 'SHA256', 768),
-  ('PKCS1-PSS', 'SHA256', 2048),
-  ('PKCS1-PSS', 'SHA256', 4096),
-)
-
-_KEYTEST_INPUTS = (
-  (768,),
-  (1024,),
-  (2048,),
-)
-
-_KEYGEN_INPUTS = (
-  (768, 65537, '', None),
-  (1024, 65537, 'rsa_test', None),
-  (2048, 65537, 'RSA key by vendor', 20811475686431332186511278472307159547870512766846593830860105577496044159545322178313772755518365593670114793803805067608811418757734989708137784444223785391864604211835387393923163468734914392307047296990698533218399115126417934050463597455237478939601236799120239663591264311485133747167378663829046579164891864068853210530642835833947569643788911200934265596274935082689832626616967124524353322373059893974744194447740045242468136414689225322177212281193879756355471091445748150740871146034049776312457888356154834233819876846764944450478069436248506560967902863015152471662817623176815923756421011384149834497587L),
-  (2048, 65537, '', None),
-)
-
-# 2048-bit will be done in hardware (i.e. fast), rest are in software.
-# Sizes below correspond to RSA key size.
-_PRIMEGEN_INPUTS = (
-  768,
-  1024,
-  2048,
-  2048,
-  2048,
-  2048,
-  2048
-)
-
-def _encrypt_tests(tpm):
-  msg = 'Hello CR50!'
-
-  for data in _ENCRYPT_INPUTS:
-    padding, hashing, key_len = data
-    test_name = 'RSA-ENC:%s:%s:%d' % data
-    cmd = _encrypt_cmd(_RSA_PADDING[padding], _HASH[hashing], key_len, msg)
-    wrapped_response = tpm.command(tpm.wrap_ext_command(subcmd.RSA, cmd))
-    ciphertext = tpm.unwrap_ext_response(subcmd.RSA, wrapped_response)
-
-    cmd = _decrypt_cmd(_RSA_PADDING[padding], _HASH[hashing],
-                       key_len, ciphertext)
-    wrapped_response = tpm.command(tpm.wrap_ext_command(subcmd.RSA, cmd))
-    plaintext = tpm.unwrap_ext_response(subcmd.RSA, wrapped_response)
-    if padding == 'NULL':
-      # Check for leading zeros.
-      if reduce(lambda x, y: x | y,
-                map(ord, plaintext[:len(plaintext) - len(msg)])):
-        raise subcmd.TpmTestError('%s error:%s%s' % (
-          test_name, utils.hex_dump(msg), utils.hex_dump(plaintext)))
-      else:
-        plaintext = plaintext[len(plaintext) - len(msg):]
-    if msg != plaintext:
-      raise subcmd.TpmTestError('%s error:%s%s' % (
-          test_name, utils.hex_dump(msg), utils.hex_dump(plaintext)))
-    print('%sSUCCESS: %s' % (utils.cursor_back(), test_name))
-
-
-def _sign_tests(tpm):
-  for data in _SIGN_INPUTS:
-    msg = rsa.randnum.read_random_bits(256)
-    padding, hashing, key_len = data
-    test_name = 'RSA-SIGN:%s:%s:%d' % data
-
-    key = _KEYS[key_len]
-    verifier = _SIGNER[padding].new(key)
-    h = _HASHER[hashing].new()
-    h.update(msg)
-
-    cmd = _sign_cmd(_RSA_PADDING[padding], _HASH[hashing], key_len, h.digest())
-    wrapped_response = tpm.command(tpm.wrap_ext_command(subcmd.RSA, cmd))
-    signature = tpm.unwrap_ext_response(subcmd.RSA, wrapped_response)
-
-    signer = _SIGNER[padding].new(key)
-    expected_signature = signer.sign(h)
-
-    if not verifier.verify(h, signature):
-      raise subcmd.TpmTestError('%s error' % (
-          test_name,))
-    print('%sSUCCESS: %s' % (utils.cursor_back(), test_name))
-
-
-def _verify_tests(tpm):
-  for data in _VERIFY_INPUTS:
-    msg = rsa.randnum.read_random_bits(256)
-    padding, hashing, key_len = data
-    test_name = 'RSA-VERIFY:%s:%s:%d' % data
-
-    key = _KEYS[key_len]
-    signer = _SIGNER[padding].new(key)
-    h = _HASHER[hashing].new()
-    h.update(msg)
-    signature = signer.sign(h)
-
-    cmd = _verify_cmd(_RSA_PADDING[padding], _HASH[hashing],
-                      key_len, signature, h.digest())
-    wrapped_response = tpm.command(tpm.wrap_ext_command(subcmd.RSA, cmd))
-    verified = tpm.unwrap_ext_response(subcmd.RSA, wrapped_response)
-    expected = '\x01'
-    if verified != expected:
-      raise subcmd.TpmTestError('%s error:%s%s' % (
-          test_name, utils.hex_dump(verified), utils.hex_dump(expected)))
-    print('%sSUCCESS: %s' % (utils.cursor_back(), test_name))
-
-
-def _keytest_tests(tpm):
-  for data in _KEYTEST_INPUTS:
-    key_len, = data
-    test_name = 'RSA-KEYTEST:%d' % data
-    cmd = _keytest_cmd(key_len)
-    wrapped_response = tpm.command(tpm.wrap_ext_command(subcmd.RSA, cmd))
-    valid = tpm.unwrap_ext_response(subcmd.RSA, wrapped_response)
-    expected = '\x01'
-    if valid != expected:
-      raise subcmd.TpmTestError('%s error:%s%s' % (
-          test_name, utils.hex_dump(valid), utils.hex_dump(expected)))
-    print('%sSUCCESS: %s' % (utils.cursor_back(), test_name))
-
-
-def _keygen_tests(tpm):
-  for data in _KEYGEN_INPUTS:
-    key_len, e, label, expected_N = data
-    test_name = 'RSA-KEYGEN:%d:%d:%s' % data[:-1]
-    cmd = _keygen_cmd(key_len, e, label)
-
-    wrapped_response = tpm.command(tpm.wrap_ext_command(subcmd.RSA, cmd))
-    result = tpm.unwrap_ext_response(subcmd.RSA, wrapped_response)
-    result_len = len(result)
-    if result_len != int(key_len / 8 * 1.5):
-      raise subcmd.TpmTestError('%s error:%s' % (
-        test_name, utils.hex_dump(result)))
-
-    N = int(binascii.b2a_hex(result[0:result_len * 2 / 3]), 16)
-    if expected_N and N != expected_N:
-      raise subcmd.TpmTestError('%s error:%s' % (
-          test_name, utils.hex_dump(result)))
-    p = int(binascii.b2a_hex(result[result_len * 2 / 3:]), 16)
-    q = N / p
-    if not rsa.prime.is_prime(p):
-      raise subcmd.TpmTestError('%s error:%s' % (
-          test_name, utils.hex_dump(result)))
-    if not rsa.prime.is_prime(q):
-      raise subcmd.TpmTestError('%s error:%s' % (
-          test_name, utils.hex_dump(result)))
-    if p == q:
-      raise subcmd.TpmTestError('%s error:%s' % (
-          test_name, utils.hex_dump(result)))
-    print('%sSUCCESS: %s' % (utils.cursor_back(), test_name))
-
-
-def _primegen_tests(tpm):
-  for data in _PRIMEGEN_INPUTS:
-    key_len = data
-    test_name = 'RSA-PRIMEGEN:%d' % data
-    seed = rsa.randnum.read_random_bits(key_len / 2)
-    assert len(seed) == key_len / 16
-    # dcrypto interface is little-endian.
-    cmd = _primegen_cmd(seed[::-1])
-
-    wrapped_response = tpm.command(tpm.wrap_ext_command(subcmd.RSA, cmd))
-    result = tpm.unwrap_ext_response(subcmd.RSA, wrapped_response)
-    result_len = len(result)
-    if result_len != key_len / 16:
-      raise subcmd.TpmTestError('%s error:%s' % (
-        test_name, utils.hex_dump(result)))
-
-    p = int(binascii.b2a_hex(result[::-1]), 16)
-    if not rsa.prime.is_prime(p):
-      raise subcmd.TpmTestError('%s error:%s' % (
-          test_name, utils.hex_dump(result)))
-    calculated = _prime_from_seed(seed)
-    if p != calculated:
-      raise subcmd.TpmTestError('%s error:%s' % (
-          test_name, utils.hex_dump(result)))
-    print('%sSUCCESS: %s' % (utils.cursor_back(), test_name))
-
-
-def _x509_verify_tests(tpm):
-  test_name = 'RSA-X509-2048-VERIFY'
-  cmd = _x509_verify_cmd(2048)
-  wrapped_response = tpm.command(tpm.wrap_ext_command(subcmd.RSA, cmd))
-  valid = tpm.unwrap_ext_response(subcmd.RSA, wrapped_response)
-  expected = '\x01'
-  if valid != expected:
-    raise subcmd.TpmTestError('%s error:%s%s' % (
-      test_name, utils.hex_dump(valid), utils.hex_dump(expected)))
-  print('%sSUCCESS: %s' % (utils.cursor_back(), test_name))
-
-
-def rsa_test(tpm):
-  _encrypt_tests(tpm)
-  _sign_tests(tpm)
-  _verify_tests(tpm)
-  _keytest_tests(tpm)
-  _keygen_tests(tpm)
-  _primegen_tests(tpm)
-  _x509_verify_tests(tpm)
diff --git a/test/tpm_test/subcmd.py b/test/tpm_test/subcmd.py
deleted file mode 100644
index 7260df0dd5..0000000000
--- a/test/tpm_test/subcmd.py
+++ /dev/null
@@ -1,19 +0,0 @@
-#!/usr/bin/env python2
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-"""Subcommand codes that specify the crypto module."""
-
-# Keep these codes in sync with include/tpm_vendor_cmds.h
-AES = 0
-HASH = 1
-RSA = 2
-ECC = 3
-FW_UPGRADE = 4
-HKDF = 5
-ECIES = 6
-DRBG_TEST = 50
-# The same exception class used by all tpmtest modules.
-class TpmTestError(Exception):
-  pass
diff --git a/test/tpm_test/support.c b/test/tpm_test/support.c
deleted file mode 100644
index fbb4d0b6ab..0000000000
--- a/test/tpm_test/support.c
+++ /dev/null
@@ -1,218 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Based on Craig Heffner's version of Dec 27 2011, published on
- * https://github.com/devttys0/libmpsse
- *
- * Internal functions used by libmpsse.
- */
-
-#include <string.h>
-#include <stdlib.h>
-
-#if LIBFTDI1 == 1
-#include <libftdi1/ftdi.h>
-#else
-#include <ftdi.h>
-#endif
-
-#include "support.h"
-
-/* Write data to the FTDI chip */
-int raw_write(struct mpsse_context *mpsse, unsigned char *buf, int size)
-{
-	int retval = MPSSE_FAIL;
-
-	if (mpsse->mode && (ftdi_write_data(&mpsse->ftdi, buf, size) == size))
-		retval = MPSSE_OK;
-
-	return retval;
-}
-
-/* Read data from the FTDI chip */
-int raw_read(struct mpsse_context *mpsse, unsigned char *buf, int size)
-{
-	int n = 0, r = 0;
-
-	if (!mpsse->mode)
-		return 0;
-
-	while (n < size) {
-		r = ftdi_read_data(&mpsse->ftdi, buf, size);
-		if (r < 0)
-			break;
-		n += r;
-	}
-
-	if (mpsse->flush_after_read) {
-		/*
-		 * Make sure the buffers are cleared after a read or
-		 * subsequent reads may fail. Is this needed anymore?
-		 * It slows down repetitive read operations by ~8%.
-		 */
-		ftdi_usb_purge_rx_buffer(&mpsse->ftdi);
-	}
-
-	return n;
-}
-
-/* Sets the read and write timeout periods for bulk usb data transfers. */
-void set_timeouts(struct mpsse_context *mpsse, int timeout)
-{
-	if (mpsse->mode) {
-		mpsse->ftdi.usb_read_timeout = timeout;
-		mpsse->ftdi.usb_write_timeout = timeout;
-	}
-}
-
-/* Convert a frequency to a clock divisor */
-uint16_t freq2div(uint32_t system_clock, uint32_t freq)
-{
-	return (((system_clock / freq) / 2) - 1);
-}
-
-/* Convert a clock divisor to a frequency */
-uint32_t div2freq(uint32_t system_clock, uint16_t div)
-{
-	return (system_clock / ((1 + div) * 2));
-}
-
-/* Builds a buffer of commands + data blocks */
-unsigned char *build_block_buffer(struct mpsse_context *mpsse,
-				  uint8_t cmd,
-				  unsigned char *data, int size, int *buf_size)
-{
-	unsigned char *buf = NULL;
-	int i = 0, j = 0, k = 0, dsize = 0, num_blocks = 0, total_size =
-	    0, xfer_size = 0;
-	uint16_t rsize = 0;
-
-	*buf_size = 0;
-
-	/* Data block size is 1 in I2C, or when in bitmode */
-	if (mpsse->mode == I2C || (cmd & MPSSE_BITMODE))
-		xfer_size = 1;
-	else
-		xfer_size = mpsse->xsize;
-
-	num_blocks = (size / xfer_size);
-	if (size % xfer_size)
-		num_blocks++;
-
-	/*
-	 * The total size of the data will be the data size + the write
-	 * command
-	 */
-	total_size = size + (CMD_SIZE * num_blocks);
-
-	buf = malloc(total_size);
-	if (!buf)
-		return NULL;
-
-	memset(buf, 0, total_size);
-
-	for (j = 0; j < num_blocks; j++) {
-		dsize = size - k;
-		if (dsize > xfer_size)
-			dsize = xfer_size;
-
-		/* The reported size of this block is block size - 1 */
-		rsize = dsize - 1;
-
-		/* Copy in the command for this block */
-		buf[i++] = cmd;
-		buf[i++] = (rsize & 0xFF);
-		if (!(cmd & MPSSE_BITMODE))
-			buf[i++] = ((rsize >> 8) & 0xFF);
-
-		/* On a write, copy the data to transmit after the command */
-		if (cmd == mpsse->tx || cmd == mpsse->txrx) {
-
-			memcpy(buf + i, data + k, dsize);
-
-			/* i == offset into buf */
-			i += dsize;
-			/* k == offset into data */
-			k += dsize;
-		}
-	}
-
-	*buf_size = i;
-
-	return buf;
-}
-
-/* Set the low bit pins high/low */
-int set_bits_low(struct mpsse_context *mpsse, int port)
-{
-	char buf[CMD_SIZE] = { 0 };
-
-	buf[0] = SET_BITS_LOW;
-	buf[1] = port;
-	buf[2] = mpsse->tris;
-
-	return raw_write(mpsse, (unsigned char *)&buf, sizeof(buf));
-}
-
-/* Set the high bit pins high/low */
-int set_bits_high(struct mpsse_context *mpsse, int port)
-{
-	char buf[CMD_SIZE] = { 0 };
-
-	buf[0] = SET_BITS_HIGH;
-	buf[1] = port;
-	buf[2] = mpsse->trish;
-
-	return raw_write(mpsse, (unsigned char *)&buf, sizeof(buf));
-}
-
-/* Set the GPIO pins high/low */
-int gpio_write(struct mpsse_context *mpsse, int pin, int direction)
-{
-	int retval = MPSSE_FAIL;
-
-	/*
-	 * The first four pins can't be changed unless we are in a stopped
-	 * status
-	 */
-	if (pin < NUM_GPIOL_PINS && mpsse->status == STOPPED) {
-		/* Convert pin number (0-3) to the corresponding pin bit */
-		pin = (GPIO0 << pin);
-
-		if (direction == HIGH) {
-			mpsse->pstart |= pin;
-			mpsse->pidle |= pin;
-			mpsse->pstop |= pin;
-		} else {
-			mpsse->pstart &= ~pin;
-			mpsse->pidle &= ~pin;
-			mpsse->pstop &= ~pin;
-		}
-
-		retval = set_bits_low(mpsse, mpsse->pstop);
-	} else if (pin >= NUM_GPIOL_PINS && pin < NUM_GPIO_PINS) {
-		/* Convert pin number (4 - 11) to the corresponding pin bit */
-		pin -= NUM_GPIOL_PINS;
-
-		if (direction == HIGH)
-			mpsse->gpioh |= (1 << pin);
-		else
-			mpsse->gpioh &= ~(1 << pin);
-
-		retval = set_bits_high(mpsse, mpsse->gpioh);
-	}
-
-	return retval;
-}
-
-/* Checks if a given MPSSE context is valid. */
-int is_valid_context(struct mpsse_context *mpsse)
-{
-	int retval = 0;
-
-	if (mpsse != NULL && mpsse->open)
-		retval = 1;
-
-	return retval;
-}
diff --git a/test/tpm_test/support.h b/test/tpm_test/support.h
deleted file mode 100644
index 77316582cc..0000000000
--- a/test/tpm_test/support.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/* Copyright 2015 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * Based on Craig Heffner's version of Dec 27 2011, published on
- * https://github.com/devttys0/libmpsse
- */
-
-#ifndef __EC_TEST_TPM_TEST_SUPPORT_H
-#define __EC_TEST_TPM_TEST_SUPPORT_H
-
-#include "mpsse.h"
-
-#define CMD_SIZE		3
-#define NUM_GPIOL_PINS		4
-#define NUM_GPIO_PINS		12
-#define LOW			0
-#define HIGH			1
-
-/* Supported MPSSE modes */
-enum modes {
-	SPI0 = 1,
-	SPI1 = 2,
-	SPI2 = 3,
-	SPI3 = 4,
-	I2C = 5,
-	GPIO = 6,
-	BITBANG = 7,
-};
-
-enum low_bits_status {
-	STARTED,
-	STOPPED
-};
-
-enum pins {
-	SK = 1,
-	DO = 2,
-	DI = 4,
-	CS = 8,
-	GPIO0 = 16,
-	GPIO1 = 32,
-	GPIO2 = 64,
-	GPIO3 = 128
-};
-
-struct mpsse_context {
-	char *description;
-	struct ftdi_context ftdi;
-	enum modes mode;
-	enum low_bits_status status;
-	int flush_after_read;
-	int vid;
-	int pid;
-	int clock;
-	int xsize;
-	int open;
-	int ftdi_initialized;
-	int endianness;
-	uint8_t tris;
-	uint8_t pstart;
-	uint8_t pstop;
-	uint8_t pidle;
-	uint8_t gpioh;
-	uint8_t trish;
-	uint8_t bitbang;
-	uint8_t tx;
-	uint8_t rx;
-	uint8_t txrx;
-	uint8_t tack;
-	uint8_t rack;
-};
-
-int raw_write(struct mpsse_context *mpsse, unsigned char *buf, int size);
-int raw_read(struct mpsse_context *mpsse, unsigned char *buf, int size);
-void set_timeouts(struct mpsse_context *mpsse, int timeout);
-uint16_t freq2div(uint32_t system_clock, uint32_t freq);
-uint32_t div2freq(uint32_t system_clock, uint16_t div);
-unsigned char *build_block_buffer(struct mpsse_context *mpsse,
-				  uint8_t cmd,
-				  unsigned char *data, int size, int *buf_size);
-int set_bits_high(struct mpsse_context *mpsse, int port);
-int set_bits_low(struct mpsse_context *mpsse, int port);
-int gpio_write(struct mpsse_context *mpsse, int pin, int direction);
-int is_valid_context(struct mpsse_context *mpsse);
-
-#endif  /* ! __EC_TEST_TPM_TEST_SUPPORT_H */
diff --git a/test/tpm_test/testlib/common.c b/test/tpm_test/testlib/common.c
deleted file mode 100644
index 35b07196aa..0000000000
--- a/test/tpm_test/testlib/common.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#include "common.h"
-
-#include <assert.h>
-#include <stdlib.h>
-#include <string.h>
-
-#include <openssl/rand.h>
-
-void rand_bytes(void *buf, size_t num)
-{
-	assert(RAND_bytes(buf, num) == 1);
-}
diff --git a/test/tpm_test/testlib/common.h b/test/tpm_test/testlib/common.h
deleted file mode 100644
index 9fdd7ebcae..0000000000
--- a/test/tpm_test/testlib/common.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-#ifndef __EC_TEST_TPM_TEST_TESTLIB_COMMON_H
-#define __EC_TEST_TPM_TEST_TESTLIB_COMMON_H
-
-#include "dcrypto.h"
-
-#include <inttypes.h>
-#include <stdlib.h>
-#include <sys/param.h>
-
-void rand_bytes(void *buf, size_t num);
-
-#endif  /* ! __EC_TEST_TPM_TEST_TESTLIB_COMMON_H */
-
diff --git a/test/tpm_test/testlib/trng.h b/test/tpm_test/testlib/trng.h
deleted file mode 100644
index 07c82f3333..0000000000
--- a/test/tpm_test/testlib/trng.h
+++ /dev/null
@@ -1,6 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Dummy empty file, just to make test compilation work. */
diff --git a/test/tpm_test/testlib/util.h b/test/tpm_test/testlib/util.h
deleted file mode 100644
index 07c82f3333..0000000000
--- a/test/tpm_test/testlib/util.h
+++ /dev/null
@@ -1,6 +0,0 @@
-/* Copyright 2016 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- */
-
-/* Dummy empty file, just to make test compilation work. */
diff --git a/test/tpm_test/tpmtest.py b/test/tpm_test/tpmtest.py
deleted file mode 100755
index 11218cbcc6..0000000000
--- a/test/tpm_test/tpmtest.py
+++ /dev/null
@@ -1,179 +0,0 @@
-#!/usr/bin/env python2
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-"""Module for initializing and driving a SPI TPM."""
-
-from __future__ import print_function
-
-import getopt
-import os
-import struct
-import sys
-import traceback
-
-# Suppressing pylint warning about an import not at the top of the file. The
-# path needs to be set *before* the last import.
-# pylint: disable=C6204
-root_dir = os.path.dirname(os.path.abspath(sys.argv[0]))
-sys.path.append(os.path.join(root_dir, '..', '..', 'build', 'tpm_test'))
-
-import crypto_test
-import drbg_test
-import ecc_test
-import ecies_test
-import ftdi_spi_tpm
-import hash_test
-import hkdf_test
-import rsa_test
-import subcmd
-import trng_test
-import upgrade_test
-
-# Extension command for dcypto testing
-EXT_CMD = 0xbaccd00a
-
-
-class TPM(object):
-  """TPM accessor class.
-
-  Object of this class allows to send valid and extended TPM commands (using
-  the command() method. The wrap_command/unwrap_response methods provide a
-  means of encapsulating extended commands in proper TPM data packets, as well
-  as extracting extended command responses.
-
-  Attributes:
-    _handle: a ftdi_spi_tpm object, a USB/FTDI/SPI driver which allows
-      communicate with a TPM connected over USB dongle.
-  """
-
-  HEADER_FMT = '>H2IH'
-  STARTUP_CMD = '80 01 00 00 00 0c 00 00 01 44 00 00'
-  STARTUP_RSP = ('80 01 00 00 00 0a 00 00 00 00',
-                 '80 01 00 00 00 0a 00 00 01 00')
-
-  def __init__(self, freq=800*1000, debug_mode=False):
-    self._debug_enabled = debug_mode
-    self._handle = ftdi_spi_tpm
-    if not self._handle.FtdiSpiInit(freq, debug_mode):
-      raise subcmd.TpmTestError('Failed to connect')
-
-  def validate(self, data_blob, response_mode=False):
-    """Check if a data blob complies with TPM command/response header format."""
-    (tag, size, cmd_code, _) = struct.unpack_from(
-        self.HEADER_FMT, data_blob + '  ')
-    prefix = 'Misformatted blob: '
-    if tag not in (0x8001, 0x8002):
-      raise subcmd.TpmTestError(prefix + 'bad tag value 0x%4.4x' % tag)
-    if size != len(data_blob):
-      raise subcmd.TpmTestError(prefix + 'size mismatch: header %d, actual %d'
-                                % (size, len(data_blob)))
-    if size > 4096:
-      raise subcmd.TpmTestError(prefix + 'invalid size %d' % size)
-    if response_mode:
-      # Startup response code, extension or vendor command response code
-      if cmd_code == 0x100 or cmd_code == 0 or cmd_code == 0x500:
-        return
-      else:
-        raise subcmd.TpmTestError(
-          prefix + 'invalid response code 0x%x' % cmd_code)
-    if cmd_code >= 0x11f and cmd_code <= 0x18f:
-      return  # This is a valid command
-    if cmd_code == EXT_CMD:
-      return  # This is an extension command
-    if cmd_code >= 0x20000000 and cmd_code <= 0x200001ff:
-      return  # this is vendor command
-    raise subcmd.TpmTestError(prefix + 'invalid command code 0x%x' % cmd_code)
-
-  def command(self, cmd_data):
-    # Verify command header
-    self.validate(cmd_data)
-    response = self._handle.FtdiSendCommandAndWait(cmd_data)
-    self.validate(response, response_mode=True)
-    return response
-
-  def wrap_ext_command(self, subcmd_code, cmd_body):
-    return struct.pack(self.HEADER_FMT, 0x8001,
-                       len(cmd_body) + struct.calcsize(self.HEADER_FMT),
-                       EXT_CMD, subcmd_code) + cmd_body
-
-  def unwrap_ext_response(self, expected_subcmd, response):
-    """Verify basic validity and strip off TPM extended command header.
-
-    Get the response generated by the device, as it came off the wire, verify
-    that header fields match expectations, then strip off the extension
-    command header and return the payload to the caller.
-
-    Args:
-      expected_subcmd: an int, up to 16 bits in size, the extension command
-        this response is supposed to be for.
-      response: a binary string, the actual response received over the wire.
-    Returns:
-      the binary string of the response payload, if validation succeeded.
-    Raises:
-      subcmd.TpmTestError: in case there are any validation problems, the
-        error message describes the problem.
-    """
-    header_size = struct.calcsize(self.HEADER_FMT)
-    tag, size, cmd, sub = struct.unpack(self.HEADER_FMT,
-                                           response[:header_size])
-    if tag != 0x8001:
-      raise subcmd.TpmTestError('Wrong response tag: %4.4x' % tag)
-    if cmd:
-      raise subcmd.TpmTestError('Unexpected response command field: %8.8x' %
-                                cmd)
-    if sub != expected_subcmd:
-      raise subcmd.TpmTestError('Unexpected response subcommand field: %2.2x' %
-                     sub)
-    if size != len(response):
-      raise subcmd.TpmTestError('Size mismatch: header %d, actual %d' % (
-          size, len(response)))
-    return response[header_size:]
-
-  def debug_enabled(self):
-    return self._debug_enabled
-
-def usage():
-  print ('Syntax: tpmtest.py [-d | -t | -h ]\n'
-         '     -d   -  prints additional debug information during tests\n'
-         '     -t   -  dump raw output from TRNG to /tmp/trng_output\n'
-         '     -h   -  this help\n')
-  return
-
-if __name__ == '__main__':
-  try:
-    opts, args = getopt.getopt(sys.argv[1:], 'dth','help')
-  except getopt.GetoptError as err:
-    print(str(err))
-    usage()
-    sys.exit(2)
-  debug_needed = False
-  trng_only = False
-  for o, a in opts:
-    if o == '-d':
-      debug_needed = True
-    elif o == '-t':
-      trng_only = True
-    elif o == '-h' or o == '--help':
-      usage()
-      sys.exit(0)
-  try:
-    t = TPM(debug_mode=debug_needed)
-    if trng_only:
-      trng_test.trng_test(t)
-      sys.exit(1)
-    crypto_test.crypto_tests(t, os.path.join(root_dir, 'crypto_test.xml'))
-    drbg_test.drbg_test(t)
-    ecc_test.ecc_test(t)
-    ecies_test.ecies_test(t)
-    hash_test.hash_test(t)
-    hkdf_test.hkdf_test(t)
-    rsa_test.rsa_test(t)
-    upgrade_test.upgrade(t)
-  except subcmd.TpmTestError as e:
-    exc_file, exc_line = traceback.extract_tb(sys.exc_traceback)[-1][:2]
-    print('\nError in %s:%s: ' % (os.path.basename(exc_file), exc_line), e)
-    if debug_needed:
-      traceback.print_exc()
-    sys.exit(1)
diff --git a/test/tpm_test/trng_test.py b/test/tpm_test/trng_test.py
deleted file mode 100644
index aac2803076..0000000000
--- a/test/tpm_test/trng_test.py
+++ /dev/null
@@ -1,50 +0,0 @@
-#!/usr/bin/env python2
-# Copyright 2019 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-"""Tests for trng."""
-from __future__ import print_function
-import struct
-
-import subcmd
-import utils
-
-TRNG_TEST_FMT = '>H'
-TRNG_TEST_RSP_FMT = '>H2IH'
-TRNG_TEST_CC = 0x33
-TRNG_SAMPLE_SIZE = 1000 # minimal recommended by NIST is 1000 bytes per sample
-TRNG_SAMPLE_COUNT = 1000 # NIST require at least 1000000 of 8-bit samples
-
-def get_random_command(size):
-  return struct.pack(TRNG_TEST_FMT, size)
-
-def get_random_command_rsp(size):
-  return struct.pack(TRNG_TEST_RSP_FMT, 0x8001,
-                     struct.calcsize(TRNG_TEST_RSP_FMT) + size, 0, TRNG_TEST_CC)
-
-
-def trng_test(tpm):
-  """Download entropy samples from TRNG
-
-    Command structure, shared out of band with the test running on the target:
-
-    field     |    size  |                  note
-    ===================================================================
-    text_len  |    2     | size of the text to process, big endian
-
-  Args:
-    tpm: a tpm object used to communicate with the device
-
-  Raises:
-    subcmd.TpmTestError: on unexpected target responses
-  """
-  with open('/tmp/trng_output', 'wb') as f:
-    for x in range(0, TRNG_SAMPLE_COUNT):
-      wrapped_response = tpm.command(tpm.wrap_ext_command(TRNG_TEST_CC,
-                                     get_random_command(TRNG_SAMPLE_SIZE)))
-      if wrapped_response[:12] != get_random_command_rsp(TRNG_SAMPLE_SIZE):
-        raise subcmd.TpmTestError("Unexpected response to '%s': %s" %
-                                 ("trng", utils.hex_dump(wrapped_response)))
-      f.write(wrapped_response[12:])
-      print('%s %d%%\r' %( utils.cursor_back(), (x/10)), end=""),
-  print('%sSUCCESS: %s' % (utils.cursor_back(), 'trng'))
diff --git a/test/tpm_test/upgrade_test.py b/test/tpm_test/upgrade_test.py
deleted file mode 100644
index 35f8405ba7..0000000000
--- a/test/tpm_test/upgrade_test.py
+++ /dev/null
@@ -1,68 +0,0 @@
-#!/usr/bin/env python2
-# Copyright 2016 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-from __future__ import print_function
-
-import hashlib
-import os
-import struct
-
-import subcmd
-import utils
-
-
-def upgrade(tpm):
-  """Exercise the upgrade command.
-
-  The target expect the upgrade extension command to have the following
-  structure:
-
-  cmd         1  value of FW_UPGRADE
-  digest      4  first 4 bytes of sha1 of the remainder of the message
-  block_base  4  address of the block to write
-  data      var
-
-  Args:
-    tpm: a properly initialized tpmtest.TPM object
-    Raises:
-      subcmd.TpmTestError: In case of various test problems
-  """
-  cmd  = struct.pack('>I', 0)  # address
-  cmd += struct.pack('>I', 0)  # data (a noop)
-  wrapped_response = tpm.command(tpm.wrap_ext_command(subcmd.FW_UPGRADE, cmd))
-  base_str = tpm.unwrap_ext_response(subcmd.FW_UPGRADE, wrapped_response)
-  if len(base_str) < 4:
-    raise subcmd.TpmTestError('Initialization error %d' %
-                              ord(base_str[0]))
-  base = struct.unpack_from('>4I', base_str)[3]
-  if base == 0x44000:
-    fname = 'build/cr50/RW/ec.RW_B.flat'
-  elif base == 0x4000:
-    fname = 'build/cr50/RW/ec.RW.flat'
-  else:
-    raise subcmd.TpmTestError('Unknown base address 0x%x' % base)
-  fname = os.path.join(os.path.dirname(__file__), '../..', fname)
-  data = open(fname, 'r').read()[:2000]
-  transferred = 0
-  block_size = 1024
-
-  while transferred < len(data):
-    tx_size = min(block_size, len(data) - transferred)
-    chunk = data[transferred:transferred+tx_size]
-    cmd  = struct.pack('>I', base)  # address
-    h = hashlib.sha1()
-    h.update(cmd)
-    h.update(chunk)
-    cmd = h.digest()[0:4] + cmd + chunk
-    resp = tpm.unwrap_ext_response(subcmd.FW_UPGRADE,
-                                   tpm.command(tpm.wrap_ext_command(
-                                     subcmd.FW_UPGRADE, cmd)))
-    code = ord(resp[0])
-    if code:
-      raise subcmd.TpmTestError('%x - resp %d' % (base, code))
-    base += tx_size
-    transferred += tx_size
-
-  print('%sSUCCESS: Firmware upgrade' % (utils.cursor_back()))
diff --git a/test/tpm_test/utils.py b/test/tpm_test/utils.py
deleted file mode 100644
index 38cda2a1e2..0000000000
--- a/test/tpm_test/utils.py
+++ /dev/null
@@ -1,38 +0,0 @@
-#!/usr/bin/env python2
-# Copyright 2015 The Chromium OS Authors. All rights reserved.
-# Use of this source code is governed by a BSD-style license that can be
-# found in the LICENSE file.
-
-"""Support functions for extended command based testing."""
-
-import sys
-
-if hasattr(sys.stdout, 'isatty') and sys.stdout.isatty():
-  cursor_back_cmd = '\x1b[1D'  # Move one space to the left.
-else:
-  cursor_back_cmd = ''
-
-
-def cursor_back():
-  """Return a string which would move cursor one space left, if available.
-
-  This is used to remove the remaining 'spinner' character after the test
-  completes and its result is printed on the same line where the 'spinner' was
-  spinning.
-
-  """
-  return cursor_back_cmd
-
-
-def hex_dump(binstr):
-  """Convert binary string into its multiline hex representation."""
-
-  dump_lines = ['',]
-  i = 0
-  while i < len(binstr):
-    strsize = min(16, len(binstr) - i)
-    hexstr = ' '.join('%2.2x' % ord(x) for x in binstr[i:i+strsize])
-    dump_lines.append(hexstr)
-    i += strsize
-  dump_lines.append('')
-  return '\n'.join(dump_lines)