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| author | Paul Ma <magf@bitland.corp-partner.google.com> | 2020-04-01 09:52:52 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-04-01 13:54:07 +0000 |
| commit | ced16b95b2ada60c38b07b905b94ed9d236e78fb (patch) | |
| tree | fc16dcc8d4e0e5669af69f1ff7c0a2c6a529dc1a | |
| parent | 903534647fa0143b6948be1c9d1fe160f01427ed (diff) | |
| download | chrome-ec-ced16b95b2ada60c38b07b905b94ed9d236e78fb.tar.gz | |
dalboz: use physical pin to generate SCI to SOC
Use physical pin (GPIO) to generate SCI to SOC.
BUG=b:152820928, b:150239200
BRANCH=none
TEST=build and boot dalboz, console command 'tabletmode on' and
'tabletmode off' work well.
Change-Id: I2f8396891c2be58f2518a2c8d33ed5f55cd08d3b
Signed-off-by: Paul Ma <magf@bitland.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2130147
Reviewed-by: Edward Hill <ecgh@chromium.org>
| -rw-r--r-- | board/dalboz/board.h | 1 | ||||
| -rw-r--r-- | board/dalboz/gpio.inc | 3 |
2 files changed, 4 insertions, 0 deletions
diff --git a/board/dalboz/board.h b/board/dalboz/board.h index 8b2dd8f024..38d409fc5b 100644 --- a/board/dalboz/board.h +++ b/board/dalboz/board.h @@ -40,6 +40,7 @@ /* GPIO mapping from board specific name to EC common name. */ #define CONFIG_BATTERY_PRESENT_GPIO GPIO_EC_BATT_PRES_ODL +#define CONFIG_SCI_GPIO GPIO_EC_FCH_SCI_ODL #define GPIO_AC_PRESENT GPIO_ACOK_OD #define GPIO_CPU_PROCHOT GPIO_PROCHOT_ODL #define GPIO_EC_INT_L GPIO_EC_AP_INT_ODL diff --git a/board/dalboz/gpio.inc b/board/dalboz/gpio.inc index dacf9164eb..d10d151f74 100644 --- a/board/dalboz/gpio.inc +++ b/board/dalboz/gpio.inc @@ -41,12 +41,15 @@ GPIO(EC_FCH_PWR_BTN_L, PIN(6, 7), GPIO_OUT_HIGH) /* Power Button to SOC */ GPIO(EC_FCH_RSMRST_L, PIN(A, 1), GPIO_OUT_LOW) /* RSMRST# to SOC */ GPIO(EC_FCH_PWROK, PIN(7, 0), GPIO_OUT_LOW) /* Power OK to SOC */ GPIO(EC_FCH_WAKE_L, PIN(0, 3), GPIO_OUT_HIGH) /* Wake SOC */ +GPIO(EC_FCH_SCI_ODL, PIN(7, 6), GPIO_ODR_HIGH) /* SCI to SOC */ GPIO(EC_SYS_RST_L, PIN(C, 7), GPIO_ODR_HIGH) /* Cold Reset to SOC */ GPIO(USB_C0_TCPC_RST_L, PIN(E, 1), GPIO_OUT_HIGH) /* C0 TCPC Reset */ GPIO(USB_C1_TCPC_RST_L, PIN(F, 0), GPIO_OUT_HIGH) /* C1 TCPC Reset */ GPIO(USB3_C0_DP2_HPD, PIN(F, 5), GPIO_OUT_LOW) /* C0 DP Hotplug Detect */ GPIO(DP1_HPD, PIN(F, 4), GPIO_OUT_LOW) /* C1 DP Hotplug Detect */ +UNIMPLEMENTED(PCH_SMI_L) + GPIO(LED_FULL_L, PIN(6, 0), GPIO_OUT_HIGH) GPIO(LED_CHRG_L, PIN(C, 0), GPIO_OUT_HIGH) |