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| author | Ruibin Chang <ruibin.chang@ite.com.tw> | 2020-03-25 13:28:03 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-03-30 05:10:20 +0000 |
| commit | fa1381fa9a2a9067451302ef03372bae9c289dd2 (patch) | |
| tree | 1d1bc23f01bf5b30ab1838f97026505337254d11 | |
| parent | 3fd849f1ba5c22836d3c23bce213dc87f87bcb36 (diff) | |
| download | chrome-ec-fa1381fa9a2a9067451302ef03372bae9c289dd2.tar.gz | |
tcpm/it83xx_pd: cc1 and cc2 resistance setting separate
In it81202/it81302 setting cc1 and cc2 resistance is
individual for each cc.
BUG=none
BRANCH=none
TEST=on it8xxx2_pdevb board,
check cc toggle and connection with adater and dongle
by Oscilloscope.
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Change-Id: I3d0697b39b2302830c67061fc3279d33d40b9957
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2120112
Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
| -rw-r--r-- | chip/it83xx/config_chip_it8xxx2.h | 2 | ||||
| -rw-r--r-- | driver/tcpm/it83xx_pd.h | 4 |
2 files changed, 6 insertions, 0 deletions
diff --git a/chip/it83xx/config_chip_it8xxx2.h b/chip/it83xx/config_chip_it8xxx2.h index fe9914d4aa..b1a620895a 100644 --- a/chip/it83xx/config_chip_it8xxx2.h +++ b/chip/it83xx/config_chip_it8xxx2.h @@ -109,6 +109,8 @@ #define IT83XX_INTC_PLUG_IN_SUPPORT /* Wake up CPU from low power mode even if interrupts are disabled */ #define IT83XX_RISCV_WAKEUP_CPU_WITHOUT_INT_ENABLED +/* Individual setting CC1 and CC2 resistance. */ +#define IT83XX_USBPD_CC1_CC2_RESISTANCE_SEPARATE /* Chip actually has TCPC physical port count. */ #define IT83XX_USBPD_PHY_PORT_COUNT 2 #else diff --git a/driver/tcpm/it83xx_pd.h b/driver/tcpm/it83xx_pd.h index fe55813435..0056f85cb1 100644 --- a/driver/tcpm/it83xx_pd.h +++ b/driver/tcpm/it83xx_pd.h @@ -123,7 +123,11 @@ #define USBPD_REG_MASK_CC2_DISCONNECT_5_1K_TO_GND BIT(6) #define USBPD_REG_MASK_CC1_DISCONNECT BIT(3) #define USBPD_REG_MASK_CC1_DISCONNECT_5_1K_TO_GND BIT(2) +#ifdef IT83XX_USBPD_CC1_CC2_RESISTANCE_SEPARATE +#define USBPD_REG_MASK_CC1_CC2_RP_RD_SELECT (BIT(1) | BIT(5)) +#else #define USBPD_REG_MASK_CC1_CC2_RP_RD_SELECT BIT(1) +#endif #define IT83XX_USBPD_CCPSR(p) REG8(IT83XX_USBPD_BASE(p)+0x06) #define USBPD_REG_MASK_DISCONNECT_5_1K_CC2_DB BIT(6) #define USBPD_REG_MASK_DISCONNECT_POWER_CC2 BIT(5) |