diff options
| author | Vadim Bendebury <vbendeb@chromium.org> | 2015-10-30 11:27:12 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2015-10-30 14:33:28 -0700 |
| commit | e4d78afafbf5170d1ceb60f1b0043a70c3449970 (patch) | |
| tree | bf10719d015b7c4357c974014f569296e4d1eb1d | |
| parent | 832b2cc58b492eb706aade155a34e8e4cbeb4da2 (diff) | |
| download | chrome-ec-e4d78afafbf5170d1ceb60f1b0043a70c3449970.tar.gz | |
cr50: upgrade to the latest FPGA image 20151029_41713@78167
This patch updates the EC codebase to match the latest USB build which
now provides ability to programatically tell between different FPGA
flavors. It also changes the polarity of the 'cold bootsrap' pin, so
using the latest spiflash utility is mandatory.
Note that there has been no signer changes.
BRANCH=none
BUG=none
TEST=as follows:
- programmed the FPGA, it now reports the following when reset:
FPGA |20151029_041713@78167
- booted the new image using the latest spiflash version. Note
that the bootrom now reports the FPGA image it comes from
- disconnected the FPGA upgrade port, rebooted the device, entered
on the device console:
> spstp off
> spste
run on the workstation:
$ examples/spiraw.py -l 10 -f 800000
FT232H Future Technology Devices International, Ltd initialized at 857142 hertz
and observe on the DUT console:
Processed 10 frames
rx count 11574, tx count 5497, tx_empty 10, max rx batch 11
>
Change-Id: I66596061731d9abcf41c5f5984ac479bbc1648e8
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/309963
Commit-Ready: Vadim Bendebury <vbendeb@google.com>
Tested-by: Vadim Bendebury <vbendeb@google.com>
Reviewed-by: Ewout van Bekkum <ewout@google.com>
Reviewed-by: Nagendra Modadugu <ngm@google.com>
| -rw-r--r-- | chip/g/cr50_fpga_regdefs.h | 1277 |
1 files changed, 700 insertions, 577 deletions
diff --git a/chip/g/cr50_fpga_regdefs.h b/chip/g/cr50_fpga_regdefs.h index 9c55820109..0821d341b5 100644 --- a/chip/g/cr50_fpga_regdefs.h +++ b/chip/g/cr50_fpga_regdefs.h @@ -615,7 +615,7 @@ #define GC_CAMO_VERSION_OFFSET 0x8 #define GC_CAMO_VERSION_DEFAULT 0x3011319 #define GC_CRYPTO_VERSION_OFFSET 0x0 -#define GC_CRYPTO_VERSION_DEFAULT 0x2a012cce +#define GC_CRYPTO_VERSION_DEFAULT 0x2b012fb1 #define GC_CRYPTO_CONTROL_OFFSET 0x4 #define GC_CRYPTO_CONTROL_DEFAULT 0x0 #define GC_CRYPTO_PARITY_CFG_OFFSET 0x8 @@ -659,7 +659,7 @@ #define GC_CRYPTO_DMEM_DUMMY_OFFSET 0x4000 #define GC_CRYPTO_IMEM_DUMMY_OFFSET 0x8000 #define GC_DMA_VERSION_OFFSET 0x0 -#define GC_DMA_VERSION_DEFAULT 0x13012cce +#define GC_DMA_VERSION_DEFAULT 0x14012f32 #define GC_DMA_INT_ENABLE_OFFSET 0x4 #define GC_DMA_INT_ENABLE_DEFAULT 0x0 #define GC_DMA_INT_STATE_OFFSET 0x8 @@ -684,7 +684,9 @@ #define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN0_DEFAULT 0x0 #define GC_DMA_MAX_NUM_TIMEOUT_CHAN0_OFFSET 0x120 #define GC_DMA_MAX_NUM_TIMEOUT_CHAN0_DEFAULT 0xf9f -#define GC_DMA_FSM_STATE_CHAN0_OFFSET 0x124 +#define GC_DMA_PAUSE_COUNTER_CHAN0_OFFSET 0x124 +#define GC_DMA_PAUSE_COUNTER_CHAN0_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN0_OFFSET 0x128 #define GC_DMA_FSM_STATE_CHAN0_DEFAULT 0x1 #define GC_DMA_START_CHAN1_OFFSET 0x200 #define GC_DMA_START_CHAN1_DEFAULT 0x0 @@ -704,7 +706,9 @@ #define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN1_DEFAULT 0x0 #define GC_DMA_MAX_NUM_TIMEOUT_CHAN1_OFFSET 0x220 #define GC_DMA_MAX_NUM_TIMEOUT_CHAN1_DEFAULT 0xf9f -#define GC_DMA_FSM_STATE_CHAN1_OFFSET 0x224 +#define GC_DMA_PAUSE_COUNTER_CHAN1_OFFSET 0x224 +#define GC_DMA_PAUSE_COUNTER_CHAN1_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN1_OFFSET 0x228 #define GC_DMA_FSM_STATE_CHAN1_DEFAULT 0x1 #define GC_DMA_START_CHAN2_OFFSET 0x300 #define GC_DMA_START_CHAN2_DEFAULT 0x0 @@ -724,7 +728,9 @@ #define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN2_DEFAULT 0x0 #define GC_DMA_MAX_NUM_TIMEOUT_CHAN2_OFFSET 0x320 #define GC_DMA_MAX_NUM_TIMEOUT_CHAN2_DEFAULT 0xf9f -#define GC_DMA_FSM_STATE_CHAN2_OFFSET 0x324 +#define GC_DMA_PAUSE_COUNTER_CHAN2_OFFSET 0x324 +#define GC_DMA_PAUSE_COUNTER_CHAN2_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN2_OFFSET 0x328 #define GC_DMA_FSM_STATE_CHAN2_DEFAULT 0x1 #define GC_DMA_START_CHAN3_OFFSET 0x400 #define GC_DMA_START_CHAN3_DEFAULT 0x0 @@ -744,7 +750,9 @@ #define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN3_DEFAULT 0x0 #define GC_DMA_MAX_NUM_TIMEOUT_CHAN3_OFFSET 0x420 #define GC_DMA_MAX_NUM_TIMEOUT_CHAN3_DEFAULT 0xf9f -#define GC_DMA_FSM_STATE_CHAN3_OFFSET 0x424 +#define GC_DMA_PAUSE_COUNTER_CHAN3_OFFSET 0x424 +#define GC_DMA_PAUSE_COUNTER_CHAN3_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN3_OFFSET 0x428 #define GC_DMA_FSM_STATE_CHAN3_DEFAULT 0x1 #define GC_DMA_START_CHAN4_OFFSET 0x500 #define GC_DMA_START_CHAN4_DEFAULT 0x0 @@ -764,7 +772,9 @@ #define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN4_DEFAULT 0x0 #define GC_DMA_MAX_NUM_TIMEOUT_CHAN4_OFFSET 0x520 #define GC_DMA_MAX_NUM_TIMEOUT_CHAN4_DEFAULT 0xf9f -#define GC_DMA_FSM_STATE_CHAN4_OFFSET 0x524 +#define GC_DMA_PAUSE_COUNTER_CHAN4_OFFSET 0x524 +#define GC_DMA_PAUSE_COUNTER_CHAN4_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN4_OFFSET 0x528 #define GC_DMA_FSM_STATE_CHAN4_DEFAULT 0x1 #define GC_DMA_START_CHAN5_OFFSET 0x600 #define GC_DMA_START_CHAN5_DEFAULT 0x0 @@ -784,7 +794,9 @@ #define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN5_DEFAULT 0x0 #define GC_DMA_MAX_NUM_TIMEOUT_CHAN5_OFFSET 0x620 #define GC_DMA_MAX_NUM_TIMEOUT_CHAN5_DEFAULT 0xf9f -#define GC_DMA_FSM_STATE_CHAN5_OFFSET 0x624 +#define GC_DMA_PAUSE_COUNTER_CHAN5_OFFSET 0x624 +#define GC_DMA_PAUSE_COUNTER_CHAN5_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN5_OFFSET 0x628 #define GC_DMA_FSM_STATE_CHAN5_DEFAULT 0x1 #define GC_DMA_START_CHAN6_OFFSET 0x700 #define GC_DMA_START_CHAN6_DEFAULT 0x0 @@ -804,7 +816,9 @@ #define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN6_DEFAULT 0x0 #define GC_DMA_MAX_NUM_TIMEOUT_CHAN6_OFFSET 0x720 #define GC_DMA_MAX_NUM_TIMEOUT_CHAN6_DEFAULT 0xf9f -#define GC_DMA_FSM_STATE_CHAN6_OFFSET 0x724 +#define GC_DMA_PAUSE_COUNTER_CHAN6_OFFSET 0x724 +#define GC_DMA_PAUSE_COUNTER_CHAN6_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN6_OFFSET 0x728 #define GC_DMA_FSM_STATE_CHAN6_DEFAULT 0x1 #define GC_DMA_START_CHAN7_OFFSET 0x800 #define GC_DMA_START_CHAN7_DEFAULT 0x0 @@ -824,7 +838,9 @@ #define GC_DMA_CURRENT_NUM_TRANSACTION_COUNT_CHAN7_DEFAULT 0x0 #define GC_DMA_MAX_NUM_TIMEOUT_CHAN7_OFFSET 0x820 #define GC_DMA_MAX_NUM_TIMEOUT_CHAN7_DEFAULT 0xf9f -#define GC_DMA_FSM_STATE_CHAN7_OFFSET 0x824 +#define GC_DMA_PAUSE_COUNTER_CHAN7_OFFSET 0x824 +#define GC_DMA_PAUSE_COUNTER_CHAN7_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN7_OFFSET 0x828 #define GC_DMA_FSM_STATE_CHAN7_DEFAULT 0x1 #define GC_FLASH_FSH_PE_CONTROL0_OFFSET 0x0 #define GC_FLASH_FSH_PE_CONTROL0_DEFAULT 0x0 @@ -3581,6 +3597,10 @@ #define GC_KEYMGR_HKEY_ERR_FLAGS_DEFAULT 0x0 #define GC_KEYMGR_HKEY_ERR_CTRL_OFFSET 0x3328 #define GC_KEYMGR_HKEY_ERR_CTRL_DEFAULT 0x0 +#define GC_KEYMGR_HKEY_FLASH_RCV_STATUS_OFFSET 0x332c +#define GC_KEYMGR_HKEY_FLASH_RCV_STATUS_DEFAULT 0x0 +#define GC_KEYMGR_HKEY_TESTMODE_UNLOCKED_STATUS_OFFSET 0x3330 +#define GC_KEYMGR_HKEY_TESTMODE_UNLOCKED_STATUS_DEFAULT 0x0 #define GC_PINMUX_DIOM0_SEL_OFFSET 0x0 #define GC_PINMUX_DIOM0_SEL_DEFAULT 0x0 #define GC_PINMUX_DIOM0_CTL_OFFSET 0x4 @@ -3945,13 +3965,13 @@ #define GC_PMU_PERICLKCLR0_OFFSET 0x68 #define GC_PMU_PERICLKCLR0_DEFAULT 0xff3fe0fb #define GC_PMU_PERICLKSET1_OFFSET 0x6c -#define GC_PMU_PERICLKSET1_DEFAULT 0xf310 +#define GC_PMU_PERICLKSET1_DEFAULT 0xff10 #define GC_PMU_PERICLKCLR1_OFFSET 0x70 -#define GC_PMU_PERICLKCLR1_DEFAULT 0xf310 +#define GC_PMU_PERICLKCLR1_DEFAULT 0xff10 #define GC_PMU_CLK_RO_MASK0_OFFSET 0x74 -#define GC_PMU_CLK_RO_MASK0_DEFAULT 0xfc0e0 +#define GC_PMU_CLK_RO_MASK0_DEFAULT 0x800fc0e1 #define GC_PMU_CLK_RO_MASK1_OFFSET 0x78 -#define GC_PMU_CLK_RO_MASK1_DEFAULT 0xc000 +#define GC_PMU_CLK_RO_MASK1_DEFAULT 0xcc00 #define GC_PMU_PERIGATEONSLEEPSET0_OFFSET 0x7c #define GC_PMU_PERIGATEONSLEEPSET0_DEFAULT 0x0 #define GC_PMU_PERIGATEONSLEEPCLR0_OFFSET 0x80 @@ -3962,93 +3982,97 @@ #define GC_PMU_PERIGATEONSLEEPCLR1_DEFAULT 0x0 #define GC_PMU_CLK0_OFFSET 0x8c #define GC_PMU_CLK0_DEFAULT 0x1f -#define GC_PMU_RST0_OFFSET 0x90 +#define GC_PMU_RST0_WR_EN_OFFSET 0x90 +#define GC_PMU_RST0_WR_EN_DEFAULT 0x1 +#define GC_PMU_RST0_OFFSET 0x94 #define GC_PMU_RST0_DEFAULT 0x0 -#define GC_PMU_RST1_OFFSET 0x94 +#define GC_PMU_RST1_WR_EN_OFFSET 0x98 +#define GC_PMU_RST1_WR_EN_DEFAULT 0x1 +#define GC_PMU_RST1_OFFSET 0x9c #define GC_PMU_RST1_DEFAULT 0x0 -#define GC_PMU_PWRDN_SCRATCH0_OFFSET 0x98 -#define GC_PMU_PWRDN_SCRATCH0_DEFAULT 0x3dde243 -#define GC_PMU_PWRDN_SCRATCH1_OFFSET 0x9c -#define GC_PMU_PWRDN_SCRATCH1_DEFAULT 0x95c5dc7 -#define GC_PMU_PWRDN_SCRATCH2_OFFSET 0xa0 -#define GC_PMU_PWRDN_SCRATCH2_DEFAULT 0x22450809 -#define GC_PMU_PWRDN_SCRATCH3_OFFSET 0xa4 -#define GC_PMU_PWRDN_SCRATCH3_DEFAULT 0x93601bfd -#define GC_PMU_PWRDN_SCRATCH4_OFFSET 0xa8 -#define GC_PMU_PWRDN_SCRATCH4_DEFAULT 0x781c64f6 -#define GC_PMU_PWRDN_SCRATCH5_OFFSET 0xac -#define GC_PMU_PWRDN_SCRATCH5_DEFAULT 0x1fa07e69 -#define GC_PMU_PWRDN_SCRATCH6_OFFSET 0xb0 -#define GC_PMU_PWRDN_SCRATCH6_DEFAULT 0x21d0e430 -#define GC_PMU_PWRDN_SCRATCH7_OFFSET 0xb4 -#define GC_PMU_PWRDN_SCRATCH7_DEFAULT 0x1046bf8d -#define GC_PMU_PWRDN_SCRATCH8_OFFSET 0xb8 -#define GC_PMU_PWRDN_SCRATCH8_DEFAULT 0x1bf72e60 -#define GC_PMU_PWRDN_SCRATCH9_OFFSET 0xbc -#define GC_PMU_PWRDN_SCRATCH9_DEFAULT 0x55a2c962 -#define GC_PMU_PWRDN_SCRATCH10_OFFSET 0xc0 -#define GC_PMU_PWRDN_SCRATCH10_DEFAULT 0x5324b8a7 -#define GC_PMU_PWRDN_SCRATCH11_OFFSET 0xc4 -#define GC_PMU_PWRDN_SCRATCH11_DEFAULT 0x3eb0aea7 -#define GC_PMU_PWRDN_SCRATCH12_OFFSET 0xc8 -#define GC_PMU_PWRDN_SCRATCH12_DEFAULT 0x5974e457 -#define GC_PMU_PWRDN_SCRATCH13_OFFSET 0xcc -#define GC_PMU_PWRDN_SCRATCH13_DEFAULT 0x4d2b580b -#define GC_PMU_PWRDN_SCRATCH14_OFFSET 0xd0 -#define GC_PMU_PWRDN_SCRATCH14_DEFAULT 0x580ffa8d -#define GC_PMU_PWRDN_SCRATCH15_OFFSET 0xd4 -#define GC_PMU_PWRDN_SCRATCH15_DEFAULT 0xc602002 -#define GC_PMU_PWRDN_SCRATCH16_OFFSET 0xd8 +#define GC_PMU_PWRDN_SCRATCH0_OFFSET 0xa0 +#define GC_PMU_PWRDN_SCRATCH0_DEFAULT 0x6dcadfc4 +#define GC_PMU_PWRDN_SCRATCH1_OFFSET 0xa4 +#define GC_PMU_PWRDN_SCRATCH1_DEFAULT 0x3c5efbfb +#define GC_PMU_PWRDN_SCRATCH2_OFFSET 0xa8 +#define GC_PMU_PWRDN_SCRATCH2_DEFAULT 0x2090fb0d +#define GC_PMU_PWRDN_SCRATCH3_OFFSET 0xac +#define GC_PMU_PWRDN_SCRATCH3_DEFAULT 0x561d44c7 +#define GC_PMU_PWRDN_SCRATCH4_OFFSET 0xb0 +#define GC_PMU_PWRDN_SCRATCH4_DEFAULT 0x52e631b +#define GC_PMU_PWRDN_SCRATCH5_OFFSET 0xb4 +#define GC_PMU_PWRDN_SCRATCH5_DEFAULT 0x4fe0eda3 +#define GC_PMU_PWRDN_SCRATCH6_OFFSET 0xb8 +#define GC_PMU_PWRDN_SCRATCH6_DEFAULT 0x232352d7 +#define GC_PMU_PWRDN_SCRATCH7_OFFSET 0xbc +#define GC_PMU_PWRDN_SCRATCH7_DEFAULT 0x943d90d4 +#define GC_PMU_PWRDN_SCRATCH8_OFFSET 0xc0 +#define GC_PMU_PWRDN_SCRATCH8_DEFAULT 0x511d8933 +#define GC_PMU_PWRDN_SCRATCH9_OFFSET 0xc4 +#define GC_PMU_PWRDN_SCRATCH9_DEFAULT 0x1fa46c1b +#define GC_PMU_PWRDN_SCRATCH10_OFFSET 0xc8 +#define GC_PMU_PWRDN_SCRATCH10_DEFAULT 0x38bf05bc +#define GC_PMU_PWRDN_SCRATCH11_OFFSET 0xcc +#define GC_PMU_PWRDN_SCRATCH11_DEFAULT 0x53dd4e04 +#define GC_PMU_PWRDN_SCRATCH12_OFFSET 0xd0 +#define GC_PMU_PWRDN_SCRATCH12_DEFAULT 0x6505d80 +#define GC_PMU_PWRDN_SCRATCH13_OFFSET 0xd4 +#define GC_PMU_PWRDN_SCRATCH13_DEFAULT 0x4f6e92d0 +#define GC_PMU_PWRDN_SCRATCH14_OFFSET 0xd8 +#define GC_PMU_PWRDN_SCRATCH14_DEFAULT 0x24f5edda +#define GC_PMU_PWRDN_SCRATCH15_OFFSET 0xdc +#define GC_PMU_PWRDN_SCRATCH15_DEFAULT 0x411941a7 +#define GC_PMU_PWRDN_SCRATCH16_OFFSET 0xe0 #define GC_PMU_PWRDN_SCRATCH16_DEFAULT 0x0 -#define GC_PMU_PWRDN_SCRATCH17_OFFSET 0xdc +#define GC_PMU_PWRDN_SCRATCH17_OFFSET 0xe4 #define GC_PMU_PWRDN_SCRATCH17_DEFAULT 0x0 -#define GC_PMU_PWRDN_SCRATCH18_OFFSET 0xe0 +#define GC_PMU_PWRDN_SCRATCH18_OFFSET 0xe8 #define GC_PMU_PWRDN_SCRATCH18_DEFAULT 0x0 -#define GC_PMU_PWRDN_SCRATCH19_OFFSET 0xe4 +#define GC_PMU_PWRDN_SCRATCH19_OFFSET 0xec #define GC_PMU_PWRDN_SCRATCH19_DEFAULT 0x0 -#define GC_PMU_PWRDN_SCRATCH20_OFFSET 0xe8 +#define GC_PMU_PWRDN_SCRATCH20_OFFSET 0xf0 #define GC_PMU_PWRDN_SCRATCH20_DEFAULT 0x0 -#define GC_PMU_PWRDN_SCRATCH21_OFFSET 0xec +#define GC_PMU_PWRDN_SCRATCH21_OFFSET 0xf4 #define GC_PMU_PWRDN_SCRATCH21_DEFAULT 0x0 -#define GC_PMU_PWRDN_SCRATCH22_OFFSET 0xf0 +#define GC_PMU_PWRDN_SCRATCH22_OFFSET 0xf8 #define GC_PMU_PWRDN_SCRATCH22_DEFAULT 0x0 -#define GC_PMU_PWRDN_SCRATCH23_OFFSET 0xf4 +#define GC_PMU_PWRDN_SCRATCH23_OFFSET 0xfc #define GC_PMU_PWRDN_SCRATCH23_DEFAULT 0x0 -#define GC_PMU_PWRDN_SCRATCH24_OFFSET 0xf8 +#define GC_PMU_PWRDN_SCRATCH24_OFFSET 0x100 #define GC_PMU_PWRDN_SCRATCH24_DEFAULT 0x0 -#define GC_PMU_PWRDN_SCRATCH25_OFFSET 0xfc +#define GC_PMU_PWRDN_SCRATCH25_OFFSET 0x104 #define GC_PMU_PWRDN_SCRATCH25_DEFAULT 0x0 -#define GC_PMU_PWRDN_SCRATCH26_OFFSET 0x100 +#define GC_PMU_PWRDN_SCRATCH26_OFFSET 0x108 #define GC_PMU_PWRDN_SCRATCH26_DEFAULT 0x0 -#define GC_PMU_PWRDN_SCRATCH27_OFFSET 0x104 +#define GC_PMU_PWRDN_SCRATCH27_OFFSET 0x10c #define GC_PMU_PWRDN_SCRATCH27_DEFAULT 0x0 -#define GC_PMU_PWRDN_SCRATCH28_OFFSET 0x108 +#define GC_PMU_PWRDN_SCRATCH28_OFFSET 0x110 #define GC_PMU_PWRDN_SCRATCH28_DEFAULT 0x0 -#define GC_PMU_PWRDN_SCRATCH29_OFFSET 0x10c +#define GC_PMU_PWRDN_SCRATCH29_OFFSET 0x114 #define GC_PMU_PWRDN_SCRATCH29_DEFAULT 0x0 -#define GC_PMU_PWRDN_SCRATCH30_OFFSET 0x110 +#define GC_PMU_PWRDN_SCRATCH30_OFFSET 0x118 #define GC_PMU_PWRDN_SCRATCH30_DEFAULT 0x0 -#define GC_PMU_PWRDN_SCRATCH31_OFFSET 0x114 +#define GC_PMU_PWRDN_SCRATCH31_OFFSET 0x11c #define GC_PMU_PWRDN_SCRATCH31_DEFAULT 0x0 -#define GC_PMU_PWRDN_SCRATCH_LOCK_OFFSET 0x118 +#define GC_PMU_PWRDN_SCRATCH_LOCK_OFFSET 0x120 #define GC_PMU_PWRDN_SCRATCH_LOCK_DEFAULT 0x0 -#define GC_PMU_PWRDN_SCRATCH_LOCK1_OFFSET 0x11c +#define GC_PMU_PWRDN_SCRATCH_LOCK1_OFFSET 0x124 #define GC_PMU_PWRDN_SCRATCH_LOCK1_DEFAULT 0x0 -#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_OFFSET 0x120 +#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_OFFSET 0x128 #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_DEFAULT 0x0 -#define GC_PMU_LONG_LIFE_SCRATCH0_OFFSET 0x124 +#define GC_PMU_LONG_LIFE_SCRATCH0_OFFSET 0x12c #define GC_PMU_LONG_LIFE_SCRATCH0_DEFAULT 0x0 -#define GC_PMU_LONG_LIFE_SCRATCH1_OFFSET 0x128 +#define GC_PMU_LONG_LIFE_SCRATCH1_OFFSET 0x130 #define GC_PMU_LONG_LIFE_SCRATCH1_DEFAULT 0x0 -#define GC_PMU_LONG_LIFE_SCRATCH2_OFFSET 0x12c +#define GC_PMU_LONG_LIFE_SCRATCH2_OFFSET 0x134 #define GC_PMU_LONG_LIFE_SCRATCH2_DEFAULT 0x0 -#define GC_PMU_LONG_LIFE_SCRATCH3_OFFSET 0x130 +#define GC_PMU_LONG_LIFE_SCRATCH3_OFFSET 0x138 #define GC_PMU_LONG_LIFE_SCRATCH3_DEFAULT 0x0 -#define GC_PMU_INT_ENABLE_OFFSET 0x134 +#define GC_PMU_INT_ENABLE_OFFSET 0x13c #define GC_PMU_INT_ENABLE_DEFAULT 0x0 -#define GC_PMU_INT_STATE_OFFSET 0x138 +#define GC_PMU_INT_STATE_OFFSET 0x140 #define GC_PMU_INT_STATE_DEFAULT 0x0 -#define GC_PMU_INT_TEST_OFFSET 0x13c +#define GC_PMU_INT_TEST_OFFSET 0x144 #define GC_PMU_INT_TEST_DEFAULT 0x0 #define GC_PMU_ANTEST_TOP_CTRL_OFFSET 0x1008 #define GC_PMU_ANTEST_TOP_CTRL_DEFAULT 0x3 @@ -4429,21 +4453,23 @@ #define GC_SPS_PASSTHRU_FILTER_RULE14_DEFAULT 0x0 #define GC_SPS_PASSTHRU_FILTER_RULE15_OFFSET 0x55c #define GC_SPS_PASSTHRU_FILTER_RULE15_DEFAULT 0x0 -#define GC_SPS_DEBUG_CS_CNT_OFFSET 0x560 +#define GC_SPS_VIRTUAL_ADDR_FILTER_OFFSET 0x560 +#define GC_SPS_VIRTUAL_ADDR_FILTER_DEFAULT 0xffffffff +#define GC_SPS_DEBUG_CS_CNT_OFFSET 0x564 #define GC_SPS_DEBUG_CS_CNT_DEFAULT 0x0 -#define GC_SPS_TESTBUS_SEL_OFFSET 0x564 +#define GC_SPS_TESTBUS_SEL_OFFSET 0x568 #define GC_SPS_TESTBUS_SEL_DEFAULT 0x0 -#define GC_SPS_DPU_TESTBUS_OFFSET 0x568 +#define GC_SPS_DPU_TESTBUS_OFFSET 0x56c #define GC_SPS_DPU_TESTBUS_DEFAULT 0x0 -#define GC_SPS_RD_CMD_TESTBUS_OFFSET 0x56c +#define GC_SPS_RD_CMD_TESTBUS_OFFSET 0x570 #define GC_SPS_RD_CMD_TESTBUS_DEFAULT 0x0 -#define GC_SPS_CMD_PASSTHRU_TESTBUS_OFFSET 0x570 +#define GC_SPS_CMD_PASSTHRU_TESTBUS_OFFSET 0x574 #define GC_SPS_CMD_PASSTHRU_TESTBUS_DEFAULT 0x0 -#define GC_SPS_EEPROM_INT_ENABLE_OFFSET 0x574 +#define GC_SPS_EEPROM_INT_ENABLE_OFFSET 0x578 #define GC_SPS_EEPROM_INT_ENABLE_DEFAULT 0x0 -#define GC_SPS_EEPROM_INT_STATE_OFFSET 0x578 +#define GC_SPS_EEPROM_INT_STATE_OFFSET 0x57c #define GC_SPS_EEPROM_INT_STATE_DEFAULT 0x0 -#define GC_SPS_EEPROM_INT_TEST_OFFSET 0x57c +#define GC_SPS_EEPROM_INT_TEST_OFFSET 0x580 #define GC_SPS_EEPROM_INT_TEST_DEFAULT 0x0 #define GC_SPS_DATA_OFFSET 0x1000 #define GC_SPS_TX_DATA_OFFSET 0x1000 @@ -4473,15 +4499,21 @@ #define GC_SWDP_HEADER_MD5SUM_OFFSET 0x28 #define GC_SWDP_HEADER_MD5SUM_DEFAULT 0x0 #define GC_SWDP_P4_LAST_SYNC_OFFSET 0x2c -#define GC_SWDP_P4_LAST_SYNC_DEFAULT 0x12d72 +#define GC_SWDP_P4_LAST_SYNC_DEFAULT 0x13157 #define GC_SWDP_BUILD_DATE_OFFSET 0x30 -#define GC_SWDP_BUILD_DATE_DEFAULT 0x1337aed +#define GC_SWDP_BUILD_DATE_DEFAULT 0x1337af5 #define GC_SWDP_BUILD_TIME_OFFSET 0x34 -#define GC_SWDP_BUILD_TIME_DEFAULT 0xd489 +#define GC_SWDP_BUILD_TIME_DEFAULT 0xa2f1 #define GC_SWDP_TEST_PORT_DISABLE_OFFSET 0x38 #define GC_SWDP_TEST_PORT_DISABLE_DEFAULT 0x0 +#define GC_SWDP_FPGA_CONFIG_OFFSET 0x3c +#define GC_SWDP_FPGA_CONFIG_DEFAULT 0x2 +#define GC_SWDP_FPGA_JITTER_FIXED_FREQ_OFFSET 0x40 +#define GC_SWDP_FPGA_JITTER_FIXED_FREQ_DEFAULT 0xe4e1c0 +#define GC_SWDP_FPGA_TIMER_FIXED_FREQ_OFFSET 0x44 +#define GC_SWDP_FPGA_TIMER_FIXED_FREQ_DEFAULT 0x16e3600 #define GC_TEMP_VERSION_OFFSET 0x0 -#define GC_TEMP_VERSION_DEFAULT 0x8011f6d +#define GC_TEMP_VERSION_DEFAULT 0x9012df1 #define GC_TEMP_ADC_INT_ENABLE_OFFSET 0x4 #define GC_TEMP_ADC_INT_ENABLE_DEFAULT 0x0 #define GC_TEMP_ADC_INT_STATE_OFFSET 0x8 @@ -4705,7 +4737,7 @@ #define GC_TIMEUS_CUR_MINOR_CNTR3_OFFSET 0x418 #define GC_TIMEUS_CUR_MINOR_CNTR3_DEFAULT 0x0 #define GC_TRNG_VERSION_OFFSET 0x0 -#define GC_TRNG_VERSION_DEFAULT 0x29012a70 +#define GC_TRNG_VERSION_DEFAULT 0x2c012f4d #define GC_TRNG_INT_ENABLE_OFFSET 0x4 #define GC_TRNG_INT_ENABLE_DEFAULT 0x0 #define GC_TRNG_INT_STATE_OFFSET 0x8 @@ -4745,7 +4777,7 @@ #define GC_TRNG_POWER_DOWN_B_OFFSET 0x4c #define GC_TRNG_POWER_DOWN_B_DEFAULT 0x0 #define GC_TRNG_PROC_LOCK_POWER_DOWN_B_OFFSET 0x50 -#define GC_TRNG_PROC_LOCK_POWER_DOWN_B_DEFAULT 0x0 +#define GC_TRNG_PROC_LOCK_POWER_DOWN_B_DEFAULT 0x1 #define GC_TRNG_ANTEST_OFFSET 0x54 #define GC_TRNG_ANTEST_DEFAULT 0x0 #define GC_TRNG_ANALOG_SEN_LSR_INPUT_OFFSET 0x58 @@ -4851,7 +4883,7 @@ #define GC_USB_GDFIFOCFG_OFFSET 0x5c #define GC_USB_GDFIFOCFG_DEFAULT 0x0 #define GC_USB_DIEPTXF1_OFFSET 0x104 -#define GC_USB_DIEPTXF1_DEFAULT 0x0 +#define GC_USB_DIEPTXF1_DEFAULT 0x1000 #define GC_USB_DIEPTXF2_OFFSET 0x108 #define GC_USB_DIEPTXF2_DEFAULT 0x0 #define GC_USB_DIEPTXF3_OFFSET 0x10c @@ -4887,7 +4919,7 @@ #define GC_USB_DSTS_OFFSET 0x808 #define GC_USB_DSTS_DEFAULT 0x0 #define GC_USB_DIEPMSK_OFFSET 0x810 -#define GC_USB_DIEPMSK_DEFAULT 0x0 +#define GC_USB_DIEPMSK_DEFAULT 0x80 #define GC_USB_DOEPMSK_OFFSET 0x814 #define GC_USB_DOEPMSK_DEFAULT 0x0 #define GC_USB_DAINT_OFFSET 0x818 @@ -5310,277 +5342,279 @@ #define GC_WATCHDOG_WDOGPCELLID3_OFFSET 0xffc #define GC_WATCHDOG_WDOGPCELLID3_DEFAULT 0xb1 #define GC_XO_VERSION_OFFSET 0x0 -#define GC_XO_VERSION_DEFAULT 0x19012cf2 +#define GC_XO_VERSION_DEFAULT 0x1b012f5a #define GC_XO_CFG_WR_EN_OFFSET 0x4 #define GC_XO_CFG_WR_EN_DEFAULT 0x1 -#define GC_XO_CLK_JTR_CTRL_OFFSET 0x8 +#define GC_XO_JTR_CTRL_EN_OFFSET 0x8 +#define GC_XO_JTR_CTRL_EN_DEFAULT 0x1 +#define GC_XO_CLK_JTR_CTRL_OFFSET 0xc #define GC_XO_CLK_JTR_CTRL_DEFAULT 0x3 -#define GC_XO_CLK_JTR_RC_COARSE_ATE_TRIM_OFFSET 0xc +#define GC_XO_CLK_JTR_RC_COARSE_ATE_TRIM_OFFSET 0x10 #define GC_XO_CLK_JTR_RC_COARSE_ATE_TRIM_DEFAULT 0x0 -#define GC_XO_CLK_JTR_RC_FINE_ATE_TRIM_OFFSET 0x10 +#define GC_XO_CLK_JTR_RC_FINE_ATE_TRIM_OFFSET 0x14 #define GC_XO_CLK_JTR_RC_FINE_ATE_TRIM_DEFAULT 0x0 -#define GC_XO_CLK_JTR_CURRENT_OFFSET 0x14 +#define GC_XO_CLK_JTR_CURRENT_OFFSET 0x18 #define GC_XO_CLK_JTR_CURRENT_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SYNC_CONTENTS_OFFSET 0x18 +#define GC_XO_CLK_JTR_SYNC_CONTENTS_OFFSET 0x1c #define GC_XO_CLK_JTR_SYNC_CONTENTS_DEFAULT 0x0 -#define GC_XO_CLK_JTR_TRIM_CTRL_OFFSET 0x1c +#define GC_XO_CLK_JTR_TRIM_CTRL_OFFSET 0x20 #define GC_XO_CLK_JTR_TRIM_CTRL_DEFAULT 0x1e -#define GC_XO_CLK_JTR_JITTERY_TRIM_EN_OFFSET 0x20 +#define GC_XO_CLK_JTR_JITTERY_TRIM_EN_OFFSET 0x24 #define GC_XO_CLK_JTR_JITTERY_TRIM_EN_DEFAULT 0x0 -#define GC_XO_CLK_JTR_JITTERY_TRIM_DIS_SIGNATURE_OFFSET 0x24 +#define GC_XO_CLK_JTR_JITTERY_TRIM_DIS_SIGNATURE_OFFSET 0x28 #define GC_XO_CLK_JTR_JITTERY_TRIM_DIS_SIGNATURE_DEFAULT 0x0 -#define GC_XO_CLK_JTR_JITTERY_TRIM_RELOAD_PERIOD_OFFSET 0x28 +#define GC_XO_CLK_JTR_JITTERY_TRIM_RELOAD_PERIOD_OFFSET 0x2c #define GC_XO_CLK_JTR_JITTERY_TRIM_RELOAD_PERIOD_DEFAULT 0xff -#define GC_XO_CLK_JTR_JITTERY_TRIM_RANDOM_SEED_EN_OFFSET 0x2c +#define GC_XO_CLK_JTR_JITTERY_TRIM_RANDOM_SEED_EN_OFFSET 0x30 #define GC_XO_CLK_JTR_JITTERY_TRIM_RANDOM_SEED_EN_DEFAULT 0x0 -#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK0_OFFSET 0x30 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK0_OFFSET 0x34 #define GC_XO_CLK_JTR_JITTERY_TRIM_BANK0_DEFAULT 0x0 -#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK1_OFFSET 0x34 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK1_OFFSET 0x38 #define GC_XO_CLK_JTR_JITTERY_TRIM_BANK1_DEFAULT 0x0 -#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK2_OFFSET 0x38 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK2_OFFSET 0x3c #define GC_XO_CLK_JTR_JITTERY_TRIM_BANK2_DEFAULT 0x0 -#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK3_OFFSET 0x3c +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK3_OFFSET 0x40 #define GC_XO_CLK_JTR_JITTERY_TRIM_BANK3_DEFAULT 0x0 -#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK4_OFFSET 0x40 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK4_OFFSET 0x44 #define GC_XO_CLK_JTR_JITTERY_TRIM_BANK4_DEFAULT 0x0 -#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK5_OFFSET 0x44 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK5_OFFSET 0x48 #define GC_XO_CLK_JTR_JITTERY_TRIM_BANK5_DEFAULT 0x0 -#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK6_OFFSET 0x48 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK6_OFFSET 0x4c #define GC_XO_CLK_JTR_JITTERY_TRIM_BANK6_DEFAULT 0x0 -#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK7_OFFSET 0x4c +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK7_OFFSET 0x50 #define GC_XO_CLK_JTR_JITTERY_TRIM_BANK7_DEFAULT 0x0 -#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK8_OFFSET 0x50 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK8_OFFSET 0x54 #define GC_XO_CLK_JTR_JITTERY_TRIM_BANK8_DEFAULT 0x0 -#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK9_OFFSET 0x54 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK9_OFFSET 0x58 #define GC_XO_CLK_JTR_JITTERY_TRIM_BANK9_DEFAULT 0x0 -#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK10_OFFSET 0x58 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK10_OFFSET 0x5c #define GC_XO_CLK_JTR_JITTERY_TRIM_BANK10_DEFAULT 0x0 -#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK11_OFFSET 0x5c +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK11_OFFSET 0x60 #define GC_XO_CLK_JTR_JITTERY_TRIM_BANK11_DEFAULT 0x0 -#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK12_OFFSET 0x60 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK12_OFFSET 0x64 #define GC_XO_CLK_JTR_JITTERY_TRIM_BANK12_DEFAULT 0x0 -#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK13_OFFSET 0x64 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK13_OFFSET 0x68 #define GC_XO_CLK_JTR_JITTERY_TRIM_BANK13_DEFAULT 0x0 -#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK14_OFFSET 0x68 +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK14_OFFSET 0x6c #define GC_XO_CLK_JTR_JITTERY_TRIM_BANK14_DEFAULT 0x0 -#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK15_OFFSET 0x6c +#define GC_XO_CLK_JTR_JITTERY_TRIM_BANK15_OFFSET 0x70 #define GC_XO_CLK_JTR_JITTERY_TRIM_BANK15_DEFAULT 0x0 -#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_OFFSET 0x70 +#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_OFFSET 0x74 #define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_DEFAULT 0x0 -#define GC_XO_CLK_JTR_CALIB_NOP_SEEN_OFFSET 0x74 +#define GC_XO_CLK_JTR_CALIB_NOP_SEEN_OFFSET 0x78 #define GC_XO_CLK_JTR_CALIB_NOP_SEEN_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_TRIM_CLK_CNT_OFFSET 0x78 +#define GC_XO_CLK_JTR_SLOW_TRIM_CLK_CNT_OFFSET 0x7c #define GC_XO_CLK_JTR_SLOW_TRIM_CLK_CNT_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_TRIM_CLK_CNT_OFFSET 0x7c +#define GC_XO_CLK_JTR_FAST_TRIM_CLK_CNT_OFFSET 0x80 #define GC_XO_CLK_JTR_FAST_TRIM_CLK_CNT_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB0_OFFSET 0x80 +#define GC_XO_CLK_JTR_FAST_CALIB0_OFFSET 0x84 #define GC_XO_CLK_JTR_FAST_CALIB0_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB1_OFFSET 0x84 +#define GC_XO_CLK_JTR_FAST_CALIB1_OFFSET 0x88 #define GC_XO_CLK_JTR_FAST_CALIB1_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB2_OFFSET 0x88 +#define GC_XO_CLK_JTR_FAST_CALIB2_OFFSET 0x8c #define GC_XO_CLK_JTR_FAST_CALIB2_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB3_OFFSET 0x8c +#define GC_XO_CLK_JTR_FAST_CALIB3_OFFSET 0x90 #define GC_XO_CLK_JTR_FAST_CALIB3_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB4_OFFSET 0x90 +#define GC_XO_CLK_JTR_FAST_CALIB4_OFFSET 0x94 #define GC_XO_CLK_JTR_FAST_CALIB4_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB5_OFFSET 0x94 +#define GC_XO_CLK_JTR_FAST_CALIB5_OFFSET 0x98 #define GC_XO_CLK_JTR_FAST_CALIB5_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB6_OFFSET 0x98 +#define GC_XO_CLK_JTR_FAST_CALIB6_OFFSET 0x9c #define GC_XO_CLK_JTR_FAST_CALIB6_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB7_OFFSET 0x9c +#define GC_XO_CLK_JTR_FAST_CALIB7_OFFSET 0xa0 #define GC_XO_CLK_JTR_FAST_CALIB7_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OFFSET 0xa0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OFFSET 0xa4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OFFSET 0xa4 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OFFSET 0xa8 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OFFSET 0xa8 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OFFSET 0xac #define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OFFSET 0xac +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OFFSET 0xb0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OFFSET 0xb0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OFFSET 0xb4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OFFSET 0xb4 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OFFSET 0xb8 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OFFSET 0xb8 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OFFSET 0xbc #define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OFFSET 0xbc +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OFFSET 0xc0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OFFSET 0xc0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OFFSET 0xc4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB0_OFFSET 0xc4 +#define GC_XO_CLK_JTR_SLOW_CALIB0_OFFSET 0xc8 #define GC_XO_CLK_JTR_SLOW_CALIB0_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB1_OFFSET 0xc8 +#define GC_XO_CLK_JTR_SLOW_CALIB1_OFFSET 0xcc #define GC_XO_CLK_JTR_SLOW_CALIB1_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB2_OFFSET 0xcc +#define GC_XO_CLK_JTR_SLOW_CALIB2_OFFSET 0xd0 #define GC_XO_CLK_JTR_SLOW_CALIB2_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB3_OFFSET 0xd0 +#define GC_XO_CLK_JTR_SLOW_CALIB3_OFFSET 0xd4 #define GC_XO_CLK_JTR_SLOW_CALIB3_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB4_OFFSET 0xd4 +#define GC_XO_CLK_JTR_SLOW_CALIB4_OFFSET 0xd8 #define GC_XO_CLK_JTR_SLOW_CALIB4_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB5_OFFSET 0xd8 +#define GC_XO_CLK_JTR_SLOW_CALIB5_OFFSET 0xdc #define GC_XO_CLK_JTR_SLOW_CALIB5_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB6_OFFSET 0xdc +#define GC_XO_CLK_JTR_SLOW_CALIB6_OFFSET 0xe0 #define GC_XO_CLK_JTR_SLOW_CALIB6_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB7_OFFSET 0xe0 +#define GC_XO_CLK_JTR_SLOW_CALIB7_OFFSET 0xe4 #define GC_XO_CLK_JTR_SLOW_CALIB7_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OFFSET 0xe4 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OFFSET 0xe8 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OFFSET 0xe8 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OFFSET 0xec #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OFFSET 0xec +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OFFSET 0xf0 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OFFSET 0xf0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OFFSET 0xf4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OFFSET 0xf4 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OFFSET 0xf8 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OFFSET 0xf8 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OFFSET 0xfc #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OFFSET 0xfc +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OFFSET 0x100 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OFFSET 0x100 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OFFSET 0x104 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OFFSET 0x104 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OFFSET 0x108 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_DEFAULT 0x0 -#define GC_XO_CLK_JTR_ENABLE_SW_TRIM_OFFSET 0x108 +#define GC_XO_CLK_JTR_ENABLE_SW_TRIM_OFFSET 0x10c #define GC_XO_CLK_JTR_ENABLE_SW_TRIM_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SW_TRIM_COUNTER_OFFSET 0x10c +#define GC_XO_CLK_JTR_SW_TRIM_COUNTER_OFFSET 0x110 #define GC_XO_CLK_JTR_SW_TRIM_COUNTER_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_CTRL_OFFSET 0x110 +#define GC_XO_CLK_TIMER_CTRL_OFFSET 0x114 #define GC_XO_CLK_TIMER_CTRL_DEFAULT 0x3 -#define GC_XO_CLK_TIMER_RC_COARSE_ATE_TRIM_OFFSET 0x114 +#define GC_XO_CLK_TIMER_RC_COARSE_ATE_TRIM_OFFSET 0x118 #define GC_XO_CLK_TIMER_RC_COARSE_ATE_TRIM_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_RC_FINE_ATE_TRIM_OFFSET 0x118 +#define GC_XO_CLK_TIMER_RC_FINE_ATE_TRIM_OFFSET 0x11c #define GC_XO_CLK_TIMER_RC_FINE_ATE_TRIM_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_CURRENT_OFFSET 0x11c +#define GC_XO_CLK_TIMER_CURRENT_OFFSET 0x120 #define GC_XO_CLK_TIMER_CURRENT_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SYNC_CONTENTS_OFFSET 0x120 +#define GC_XO_CLK_TIMER_SYNC_CONTENTS_OFFSET 0x124 #define GC_XO_CLK_TIMER_SYNC_CONTENTS_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_TRIM_CTRL_OFFSET 0x124 +#define GC_XO_CLK_TIMER_TRIM_CTRL_OFFSET 0x128 #define GC_XO_CLK_TIMER_TRIM_CTRL_DEFAULT 0x1e -#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_OFFSET 0x128 +#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_OFFSET 0x12c #define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_CALIB_NOP_SEEN_OFFSET 0x12c +#define GC_XO_CLK_TIMER_CALIB_NOP_SEEN_OFFSET 0x130 #define GC_XO_CLK_TIMER_CALIB_NOP_SEEN_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_TRIM_CLK_CNT_OFFSET 0x130 +#define GC_XO_CLK_TIMER_SLOW_TRIM_CLK_CNT_OFFSET 0x134 #define GC_XO_CLK_TIMER_SLOW_TRIM_CLK_CNT_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_TRIM_CLK_CNT_OFFSET 0x134 +#define GC_XO_CLK_TIMER_FAST_TRIM_CLK_CNT_OFFSET 0x138 #define GC_XO_CLK_TIMER_FAST_TRIM_CLK_CNT_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB0_OFFSET 0x138 +#define GC_XO_CLK_TIMER_FAST_CALIB0_OFFSET 0x13c #define GC_XO_CLK_TIMER_FAST_CALIB0_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB1_OFFSET 0x13c +#define GC_XO_CLK_TIMER_FAST_CALIB1_OFFSET 0x140 #define GC_XO_CLK_TIMER_FAST_CALIB1_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB2_OFFSET 0x140 +#define GC_XO_CLK_TIMER_FAST_CALIB2_OFFSET 0x144 #define GC_XO_CLK_TIMER_FAST_CALIB2_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB3_OFFSET 0x144 +#define GC_XO_CLK_TIMER_FAST_CALIB3_OFFSET 0x148 #define GC_XO_CLK_TIMER_FAST_CALIB3_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB4_OFFSET 0x148 +#define GC_XO_CLK_TIMER_FAST_CALIB4_OFFSET 0x14c #define GC_XO_CLK_TIMER_FAST_CALIB4_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB5_OFFSET 0x14c +#define GC_XO_CLK_TIMER_FAST_CALIB5_OFFSET 0x150 #define GC_XO_CLK_TIMER_FAST_CALIB5_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB6_OFFSET 0x150 +#define GC_XO_CLK_TIMER_FAST_CALIB6_OFFSET 0x154 #define GC_XO_CLK_TIMER_FAST_CALIB6_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB7_OFFSET 0x154 +#define GC_XO_CLK_TIMER_FAST_CALIB7_OFFSET 0x158 #define GC_XO_CLK_TIMER_FAST_CALIB7_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OFFSET 0x158 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OFFSET 0x15c #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OFFSET 0x15c +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OFFSET 0x160 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OFFSET 0x160 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OFFSET 0x164 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OFFSET 0x164 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OFFSET 0x168 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OFFSET 0x168 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OFFSET 0x16c #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OFFSET 0x16c +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OFFSET 0x170 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OFFSET 0x170 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OFFSET 0x174 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OFFSET 0x174 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OFFSET 0x178 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OFFSET 0x178 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OFFSET 0x17c #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB0_OFFSET 0x17c +#define GC_XO_CLK_TIMER_SLOW_CALIB0_OFFSET 0x180 #define GC_XO_CLK_TIMER_SLOW_CALIB0_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB1_OFFSET 0x180 +#define GC_XO_CLK_TIMER_SLOW_CALIB1_OFFSET 0x184 #define GC_XO_CLK_TIMER_SLOW_CALIB1_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB2_OFFSET 0x184 +#define GC_XO_CLK_TIMER_SLOW_CALIB2_OFFSET 0x188 #define GC_XO_CLK_TIMER_SLOW_CALIB2_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB3_OFFSET 0x188 +#define GC_XO_CLK_TIMER_SLOW_CALIB3_OFFSET 0x18c #define GC_XO_CLK_TIMER_SLOW_CALIB3_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB4_OFFSET 0x18c +#define GC_XO_CLK_TIMER_SLOW_CALIB4_OFFSET 0x190 #define GC_XO_CLK_TIMER_SLOW_CALIB4_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB5_OFFSET 0x190 +#define GC_XO_CLK_TIMER_SLOW_CALIB5_OFFSET 0x194 #define GC_XO_CLK_TIMER_SLOW_CALIB5_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB6_OFFSET 0x194 +#define GC_XO_CLK_TIMER_SLOW_CALIB6_OFFSET 0x198 #define GC_XO_CLK_TIMER_SLOW_CALIB6_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB7_OFFSET 0x198 +#define GC_XO_CLK_TIMER_SLOW_CALIB7_OFFSET 0x19c #define GC_XO_CLK_TIMER_SLOW_CALIB7_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OFFSET 0x19c +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OFFSET 0x1a0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OFFSET 0x1a0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OFFSET 0x1a4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OFFSET 0x1a4 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OFFSET 0x1a8 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OFFSET 0x1a8 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OFFSET 0x1ac #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OFFSET 0x1ac +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OFFSET 0x1b0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OFFSET 0x1b0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OFFSET 0x1b4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OFFSET 0x1b4 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OFFSET 0x1b8 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OFFSET 0x1b8 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OFFSET 0x1bc #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OFFSET 0x1bc +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OFFSET 0x1c0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_ENABLE_SW_TRIM_OFFSET 0x1c0 +#define GC_XO_CLK_TIMER_ENABLE_SW_TRIM_OFFSET 0x1c4 #define GC_XO_CLK_TIMER_ENABLE_SW_TRIM_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_OFFSET 0x1c4 +#define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_OFFSET 0x1c8 #define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_DEFAULT 0x0 -#define GC_XO_OSC_XTL_FREQ2X_OFFSET 0x1c8 +#define GC_XO_OSC_XTL_FREQ2X_OFFSET 0x1cc #define GC_XO_OSC_XTL_FREQ2X_DEFAULT 0x7 -#define GC_XO_OSC_XTL_FREQ2X_STAT_OFFSET 0x1cc +#define GC_XO_OSC_XTL_FREQ2X_STAT_OFFSET 0x1d0 #define GC_XO_OSC_XTL_FREQ2X_STAT_DEFAULT 0x6 -#define GC_XO_OSC_XTL_TRIMD_OFFSET 0x1d0 -#define GC_XO_OSC_XTL_TRIMD_DEFAULT 0x40 -#define GC_XO_OSC_XTL_TRIMG_OFFSET 0x1d4 -#define GC_XO_OSC_XTL_TRIMG_DEFAULT 0x40 -#define GC_XO_OSC_XTL_CTRL_OFFSET 0x1d8 +#define GC_XO_OSC_XTL_TRIMD_OFFSET 0x1d4 +#define GC_XO_OSC_XTL_TRIMD_DEFAULT 0x7f +#define GC_XO_OSC_XTL_TRIMG_OFFSET 0x1d8 +#define GC_XO_OSC_XTL_TRIMG_DEFAULT 0x7f +#define GC_XO_OSC_XTL_CTRL_OFFSET 0x1dc #define GC_XO_OSC_XTL_CTRL_DEFAULT 0x0 -#define GC_XO_OSC_XTL_RC_FLTR_OFFSET 0x1dc +#define GC_XO_OSC_XTL_RC_FLTR_OFFSET 0x1e0 #define GC_XO_OSC_XTL_RC_FLTR_DEFAULT 0x15 -#define GC_XO_OSC_XTL_OVRD_OFFSET 0x1e0 +#define GC_XO_OSC_XTL_OVRD_OFFSET 0x1e4 #define GC_XO_OSC_XTL_OVRD_DEFAULT 0x17 -#define GC_XO_OSC_XTL_OVRD_HOLDB_OFFSET 0x1e4 +#define GC_XO_OSC_XTL_OVRD_HOLDB_OFFSET 0x1e8 #define GC_XO_OSC_XTL_OVRD_HOLDB_DEFAULT 0x1 -#define GC_XO_OSC_XTL_TRIM_OFFSET 0x1e8 +#define GC_XO_OSC_XTL_TRIM_OFFSET 0x1ec #define GC_XO_OSC_XTL_TRIM_DEFAULT 0x0 -#define GC_XO_OSC_XTL_TRIM_STAT_OFFSET 0x1ec +#define GC_XO_OSC_XTL_TRIM_STAT_OFFSET 0x1f0 #define GC_XO_OSC_XTL_TRIM_STAT_DEFAULT 0x0 -#define GC_XO_OSC_XTL_FSM_EN_OFFSET 0x1f0 +#define GC_XO_OSC_XTL_FSM_EN_OFFSET 0x1f4 #define GC_XO_OSC_XTL_FSM_EN_DEFAULT 0x0 #define GC_XO_OSC_XTL_FSM_EN_KEY 0x60221413 -#define GC_XO_OSC_XTL_FSM_RESETB_OFFSET 0x1f4 +#define GC_XO_OSC_XTL_FSM_RESETB_OFFSET 0x1f8 #define GC_XO_OSC_XTL_FSM_RESETB_DEFAULT 0x0 -#define GC_XO_OSC_XTL_FSM_OFFSET 0x1f8 +#define GC_XO_OSC_XTL_FSM_OFFSET 0x1fc #define GC_XO_OSC_XTL_FSM_DEFAULT 0x0 -#define GC_XO_OSC_XTL_FSM_CFG_OFFSET 0x1fc +#define GC_XO_OSC_XTL_FSM_CFG_OFFSET 0x200 #define GC_XO_OSC_XTL_FSM_CFG_DEFAULT 0xd7488 -#define GC_XO_OSC_TEST_OFFSET 0x200 +#define GC_XO_OSC_TEST_OFFSET 0x204 #define GC_XO_OSC_TEST_DEFAULT 0x0 -#define GC_XO_TESTBUS_SEL_OFFSET 0x204 +#define GC_XO_TESTBUS_SEL_OFFSET 0x208 #define GC_XO_TESTBUS_SEL_DEFAULT 0x0 -#define GC_XO_CLK_JTR_TESTBUS_RD_OFFSET 0x208 +#define GC_XO_CLK_JTR_TESTBUS_RD_OFFSET 0x20c #define GC_XO_CLK_JTR_TESTBUS_RD_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_TESTBUS_RD_OFFSET 0x20c +#define GC_XO_CLK_TIMER_TESTBUS_RD_OFFSET 0x210 #define GC_XO_CLK_TIMER_TESTBUS_RD_DEFAULT 0x0 -#define GC_XO_ANTEST_CTRL_OFFSET 0x210 +#define GC_XO_ANTEST_CTRL_OFFSET 0x214 #define GC_XO_ANTEST_CTRL_DEFAULT 0x0 -#define GC_XO_DXO_INT_ENABLE_OFFSET 0x214 +#define GC_XO_DXO_INT_ENABLE_OFFSET 0x218 #define GC_XO_DXO_INT_ENABLE_DEFAULT 0x0 -#define GC_XO_DXO_INT_STATE_OFFSET 0x218 +#define GC_XO_DXO_INT_STATE_OFFSET 0x21c #define GC_XO_DXO_INT_STATE_DEFAULT 0x0 -#define GC_XO_DXO_INT_TEST_OFFSET 0x21c +#define GC_XO_DXO_INT_TEST_OFFSET 0x220 #define GC_XO_DXO_INT_TEST_DEFAULT 0x0 #define GC_M3_ITM_STIM0_OFFSET 0x0 #define GC_M3_ITM_STIM0_DEFAULT 0x0 @@ -6225,12 +6259,12 @@ #define GC_CRYPTO_VERSION_CHANGE_LSB 0x0 #define GC_CRYPTO_VERSION_CHANGE_MASK 0xffffff #define GC_CRYPTO_VERSION_CHANGE_SIZE 0x18 -#define GC_CRYPTO_VERSION_CHANGE_DEFAULT 0x12cce +#define GC_CRYPTO_VERSION_CHANGE_DEFAULT 0x12fb1 #define GC_CRYPTO_VERSION_CHANGE_OFFSET 0x0 #define GC_CRYPTO_VERSION_REVISION_LSB 0x18 #define GC_CRYPTO_VERSION_REVISION_MASK 0xff000000 #define GC_CRYPTO_VERSION_REVISION_SIZE 0x8 -#define GC_CRYPTO_VERSION_REVISION_DEFAULT 0x2a +#define GC_CRYPTO_VERSION_REVISION_DEFAULT 0x2b #define GC_CRYPTO_VERSION_REVISION_OFFSET 0x0 #define GC_CRYPTO_CONTROL_RESET_LSB 0x0 #define GC_CRYPTO_CONTROL_RESET_MASK 0x1 @@ -6585,12 +6619,12 @@ #define GC_DMA_VERSION_CHANGE_LSB 0x0 #define GC_DMA_VERSION_CHANGE_MASK 0xffffff #define GC_DMA_VERSION_CHANGE_SIZE 0x18 -#define GC_DMA_VERSION_CHANGE_DEFAULT 0x12cce +#define GC_DMA_VERSION_CHANGE_DEFAULT 0x12f32 #define GC_DMA_VERSION_CHANGE_OFFSET 0x0 #define GC_DMA_VERSION_REVISION_LSB 0x18 #define GC_DMA_VERSION_REVISION_MASK 0xff000000 #define GC_DMA_VERSION_REVISION_SIZE 0x8 -#define GC_DMA_VERSION_REVISION_DEFAULT 0x13 +#define GC_DMA_VERSION_REVISION_DEFAULT 0x14 #define GC_DMA_VERSION_REVISION_OFFSET 0x0 #define GC_DMA_INT_ENABLE_INTR_COMPLETE_CHAN_LSB 0x0 #define GC_DMA_INT_ENABLE_INTR_COMPLETE_CHAN_MASK 0xff @@ -6701,42 +6735,47 @@ #define GC_DMA_FSM_STATE_CHAN0_IDLE_MASK 0x1 #define GC_DMA_FSM_STATE_CHAN0_IDLE_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN0_IDLE_DEFAULT 0x1 -#define GC_DMA_FSM_STATE_CHAN0_IDLE_OFFSET 0x124 +#define GC_DMA_FSM_STATE_CHAN0_IDLE_OFFSET 0x128 #define GC_DMA_FSM_STATE_CHAN0_BID_READ_LSB 0x1 #define GC_DMA_FSM_STATE_CHAN0_BID_READ_MASK 0x2 #define GC_DMA_FSM_STATE_CHAN0_BID_READ_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN0_BID_READ_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN0_BID_READ_OFFSET 0x124 +#define GC_DMA_FSM_STATE_CHAN0_BID_READ_OFFSET 0x128 #define GC_DMA_FSM_STATE_CHAN0_BID_WRITE_LSB 0x2 #define GC_DMA_FSM_STATE_CHAN0_BID_WRITE_MASK 0x4 #define GC_DMA_FSM_STATE_CHAN0_BID_WRITE_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN0_BID_WRITE_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN0_BID_WRITE_OFFSET 0x124 +#define GC_DMA_FSM_STATE_CHAN0_BID_WRITE_OFFSET 0x128 #define GC_DMA_FSM_STATE_CHAN0_CHECK_EMPTY_LSB 0x3 #define GC_DMA_FSM_STATE_CHAN0_CHECK_EMPTY_MASK 0x8 #define GC_DMA_FSM_STATE_CHAN0_CHECK_EMPTY_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN0_CHECK_EMPTY_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN0_CHECK_EMPTY_OFFSET 0x124 +#define GC_DMA_FSM_STATE_CHAN0_CHECK_EMPTY_OFFSET 0x128 #define GC_DMA_FSM_STATE_CHAN0_CHECK_FULL_LSB 0x4 #define GC_DMA_FSM_STATE_CHAN0_CHECK_FULL_MASK 0x10 #define GC_DMA_FSM_STATE_CHAN0_CHECK_FULL_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN0_CHECK_FULL_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN0_CHECK_FULL_OFFSET 0x124 +#define GC_DMA_FSM_STATE_CHAN0_CHECK_FULL_OFFSET 0x128 #define GC_DMA_FSM_STATE_CHAN0_READ_LSB 0x5 #define GC_DMA_FSM_STATE_CHAN0_READ_MASK 0x20 #define GC_DMA_FSM_STATE_CHAN0_READ_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN0_READ_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN0_READ_OFFSET 0x124 +#define GC_DMA_FSM_STATE_CHAN0_READ_OFFSET 0x128 #define GC_DMA_FSM_STATE_CHAN0_WRITE_LSB 0x6 #define GC_DMA_FSM_STATE_CHAN0_WRITE_MASK 0x40 #define GC_DMA_FSM_STATE_CHAN0_WRITE_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN0_WRITE_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN0_WRITE_OFFSET 0x124 +#define GC_DMA_FSM_STATE_CHAN0_WRITE_OFFSET 0x128 #define GC_DMA_FSM_STATE_CHAN0_ERROR_LSB 0x7 #define GC_DMA_FSM_STATE_CHAN0_ERROR_MASK 0x80 #define GC_DMA_FSM_STATE_CHAN0_ERROR_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN0_ERROR_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN0_ERROR_OFFSET 0x124 +#define GC_DMA_FSM_STATE_CHAN0_ERROR_OFFSET 0x128 +#define GC_DMA_FSM_STATE_CHAN0_PAUSE_LSB 0x8 +#define GC_DMA_FSM_STATE_CHAN0_PAUSE_MASK 0x100 +#define GC_DMA_FSM_STATE_CHAN0_PAUSE_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN0_PAUSE_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN0_PAUSE_OFFSET 0x128 #define GC_DMA_CTRL_CHAN1_CLR_ERROR_LSB 0x0 #define GC_DMA_CTRL_CHAN1_CLR_ERROR_MASK 0x1 #define GC_DMA_CTRL_CHAN1_CLR_ERROR_SIZE 0x1 @@ -6786,42 +6825,47 @@ #define GC_DMA_FSM_STATE_CHAN1_IDLE_MASK 0x1 #define GC_DMA_FSM_STATE_CHAN1_IDLE_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN1_IDLE_DEFAULT 0x1 -#define GC_DMA_FSM_STATE_CHAN1_IDLE_OFFSET 0x224 +#define GC_DMA_FSM_STATE_CHAN1_IDLE_OFFSET 0x228 #define GC_DMA_FSM_STATE_CHAN1_BID_READ_LSB 0x1 #define GC_DMA_FSM_STATE_CHAN1_BID_READ_MASK 0x2 #define GC_DMA_FSM_STATE_CHAN1_BID_READ_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN1_BID_READ_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN1_BID_READ_OFFSET 0x224 +#define GC_DMA_FSM_STATE_CHAN1_BID_READ_OFFSET 0x228 #define GC_DMA_FSM_STATE_CHAN1_BID_WRITE_LSB 0x2 #define GC_DMA_FSM_STATE_CHAN1_BID_WRITE_MASK 0x4 #define GC_DMA_FSM_STATE_CHAN1_BID_WRITE_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN1_BID_WRITE_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN1_BID_WRITE_OFFSET 0x224 +#define GC_DMA_FSM_STATE_CHAN1_BID_WRITE_OFFSET 0x228 #define GC_DMA_FSM_STATE_CHAN1_CHECK_EMPTY_LSB 0x3 #define GC_DMA_FSM_STATE_CHAN1_CHECK_EMPTY_MASK 0x8 #define GC_DMA_FSM_STATE_CHAN1_CHECK_EMPTY_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN1_CHECK_EMPTY_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN1_CHECK_EMPTY_OFFSET 0x224 +#define GC_DMA_FSM_STATE_CHAN1_CHECK_EMPTY_OFFSET 0x228 #define GC_DMA_FSM_STATE_CHAN1_CHECK_FULL_LSB 0x4 #define GC_DMA_FSM_STATE_CHAN1_CHECK_FULL_MASK 0x10 #define GC_DMA_FSM_STATE_CHAN1_CHECK_FULL_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN1_CHECK_FULL_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN1_CHECK_FULL_OFFSET 0x224 +#define GC_DMA_FSM_STATE_CHAN1_CHECK_FULL_OFFSET 0x228 #define GC_DMA_FSM_STATE_CHAN1_READ_LSB 0x5 #define GC_DMA_FSM_STATE_CHAN1_READ_MASK 0x20 #define GC_DMA_FSM_STATE_CHAN1_READ_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN1_READ_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN1_READ_OFFSET 0x224 +#define GC_DMA_FSM_STATE_CHAN1_READ_OFFSET 0x228 #define GC_DMA_FSM_STATE_CHAN1_WRITE_LSB 0x6 #define GC_DMA_FSM_STATE_CHAN1_WRITE_MASK 0x40 #define GC_DMA_FSM_STATE_CHAN1_WRITE_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN1_WRITE_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN1_WRITE_OFFSET 0x224 +#define GC_DMA_FSM_STATE_CHAN1_WRITE_OFFSET 0x228 #define GC_DMA_FSM_STATE_CHAN1_ERROR_LSB 0x7 #define GC_DMA_FSM_STATE_CHAN1_ERROR_MASK 0x80 #define GC_DMA_FSM_STATE_CHAN1_ERROR_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN1_ERROR_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN1_ERROR_OFFSET 0x224 +#define GC_DMA_FSM_STATE_CHAN1_ERROR_OFFSET 0x228 +#define GC_DMA_FSM_STATE_CHAN1_PAUSE_LSB 0x8 +#define GC_DMA_FSM_STATE_CHAN1_PAUSE_MASK 0x100 +#define GC_DMA_FSM_STATE_CHAN1_PAUSE_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN1_PAUSE_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN1_PAUSE_OFFSET 0x228 #define GC_DMA_CTRL_CHAN2_CLR_ERROR_LSB 0x0 #define GC_DMA_CTRL_CHAN2_CLR_ERROR_MASK 0x1 #define GC_DMA_CTRL_CHAN2_CLR_ERROR_SIZE 0x1 @@ -6871,42 +6915,47 @@ #define GC_DMA_FSM_STATE_CHAN2_IDLE_MASK 0x1 #define GC_DMA_FSM_STATE_CHAN2_IDLE_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN2_IDLE_DEFAULT 0x1 -#define GC_DMA_FSM_STATE_CHAN2_IDLE_OFFSET 0x324 +#define GC_DMA_FSM_STATE_CHAN2_IDLE_OFFSET 0x328 #define GC_DMA_FSM_STATE_CHAN2_BID_READ_LSB 0x1 #define GC_DMA_FSM_STATE_CHAN2_BID_READ_MASK 0x2 #define GC_DMA_FSM_STATE_CHAN2_BID_READ_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN2_BID_READ_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN2_BID_READ_OFFSET 0x324 +#define GC_DMA_FSM_STATE_CHAN2_BID_READ_OFFSET 0x328 #define GC_DMA_FSM_STATE_CHAN2_BID_WRITE_LSB 0x2 #define GC_DMA_FSM_STATE_CHAN2_BID_WRITE_MASK 0x4 #define GC_DMA_FSM_STATE_CHAN2_BID_WRITE_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN2_BID_WRITE_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN2_BID_WRITE_OFFSET 0x324 +#define GC_DMA_FSM_STATE_CHAN2_BID_WRITE_OFFSET 0x328 #define GC_DMA_FSM_STATE_CHAN2_CHECK_EMPTY_LSB 0x3 #define GC_DMA_FSM_STATE_CHAN2_CHECK_EMPTY_MASK 0x8 #define GC_DMA_FSM_STATE_CHAN2_CHECK_EMPTY_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN2_CHECK_EMPTY_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN2_CHECK_EMPTY_OFFSET 0x324 +#define GC_DMA_FSM_STATE_CHAN2_CHECK_EMPTY_OFFSET 0x328 #define GC_DMA_FSM_STATE_CHAN2_CHECK_FULL_LSB 0x4 #define GC_DMA_FSM_STATE_CHAN2_CHECK_FULL_MASK 0x10 #define GC_DMA_FSM_STATE_CHAN2_CHECK_FULL_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN2_CHECK_FULL_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN2_CHECK_FULL_OFFSET 0x324 +#define GC_DMA_FSM_STATE_CHAN2_CHECK_FULL_OFFSET 0x328 #define GC_DMA_FSM_STATE_CHAN2_READ_LSB 0x5 #define GC_DMA_FSM_STATE_CHAN2_READ_MASK 0x20 #define GC_DMA_FSM_STATE_CHAN2_READ_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN2_READ_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN2_READ_OFFSET 0x324 +#define GC_DMA_FSM_STATE_CHAN2_READ_OFFSET 0x328 #define GC_DMA_FSM_STATE_CHAN2_WRITE_LSB 0x6 #define GC_DMA_FSM_STATE_CHAN2_WRITE_MASK 0x40 #define GC_DMA_FSM_STATE_CHAN2_WRITE_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN2_WRITE_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN2_WRITE_OFFSET 0x324 +#define GC_DMA_FSM_STATE_CHAN2_WRITE_OFFSET 0x328 #define GC_DMA_FSM_STATE_CHAN2_ERROR_LSB 0x7 #define GC_DMA_FSM_STATE_CHAN2_ERROR_MASK 0x80 #define GC_DMA_FSM_STATE_CHAN2_ERROR_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN2_ERROR_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN2_ERROR_OFFSET 0x324 +#define GC_DMA_FSM_STATE_CHAN2_ERROR_OFFSET 0x328 +#define GC_DMA_FSM_STATE_CHAN2_PAUSE_LSB 0x8 +#define GC_DMA_FSM_STATE_CHAN2_PAUSE_MASK 0x100 +#define GC_DMA_FSM_STATE_CHAN2_PAUSE_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN2_PAUSE_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN2_PAUSE_OFFSET 0x328 #define GC_DMA_CTRL_CHAN3_CLR_ERROR_LSB 0x0 #define GC_DMA_CTRL_CHAN3_CLR_ERROR_MASK 0x1 #define GC_DMA_CTRL_CHAN3_CLR_ERROR_SIZE 0x1 @@ -6956,42 +7005,47 @@ #define GC_DMA_FSM_STATE_CHAN3_IDLE_MASK 0x1 #define GC_DMA_FSM_STATE_CHAN3_IDLE_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN3_IDLE_DEFAULT 0x1 -#define GC_DMA_FSM_STATE_CHAN3_IDLE_OFFSET 0x424 +#define GC_DMA_FSM_STATE_CHAN3_IDLE_OFFSET 0x428 #define GC_DMA_FSM_STATE_CHAN3_BID_READ_LSB 0x1 #define GC_DMA_FSM_STATE_CHAN3_BID_READ_MASK 0x2 #define GC_DMA_FSM_STATE_CHAN3_BID_READ_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN3_BID_READ_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN3_BID_READ_OFFSET 0x424 +#define GC_DMA_FSM_STATE_CHAN3_BID_READ_OFFSET 0x428 #define GC_DMA_FSM_STATE_CHAN3_BID_WRITE_LSB 0x2 #define GC_DMA_FSM_STATE_CHAN3_BID_WRITE_MASK 0x4 #define GC_DMA_FSM_STATE_CHAN3_BID_WRITE_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN3_BID_WRITE_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN3_BID_WRITE_OFFSET 0x424 +#define GC_DMA_FSM_STATE_CHAN3_BID_WRITE_OFFSET 0x428 #define GC_DMA_FSM_STATE_CHAN3_CHECK_EMPTY_LSB 0x3 #define GC_DMA_FSM_STATE_CHAN3_CHECK_EMPTY_MASK 0x8 #define GC_DMA_FSM_STATE_CHAN3_CHECK_EMPTY_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN3_CHECK_EMPTY_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN3_CHECK_EMPTY_OFFSET 0x424 +#define GC_DMA_FSM_STATE_CHAN3_CHECK_EMPTY_OFFSET 0x428 #define GC_DMA_FSM_STATE_CHAN3_CHECK_FULL_LSB 0x4 #define GC_DMA_FSM_STATE_CHAN3_CHECK_FULL_MASK 0x10 #define GC_DMA_FSM_STATE_CHAN3_CHECK_FULL_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN3_CHECK_FULL_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN3_CHECK_FULL_OFFSET 0x424 +#define GC_DMA_FSM_STATE_CHAN3_CHECK_FULL_OFFSET 0x428 #define GC_DMA_FSM_STATE_CHAN3_READ_LSB 0x5 #define GC_DMA_FSM_STATE_CHAN3_READ_MASK 0x20 #define GC_DMA_FSM_STATE_CHAN3_READ_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN3_READ_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN3_READ_OFFSET 0x424 +#define GC_DMA_FSM_STATE_CHAN3_READ_OFFSET 0x428 #define GC_DMA_FSM_STATE_CHAN3_WRITE_LSB 0x6 #define GC_DMA_FSM_STATE_CHAN3_WRITE_MASK 0x40 #define GC_DMA_FSM_STATE_CHAN3_WRITE_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN3_WRITE_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN3_WRITE_OFFSET 0x424 +#define GC_DMA_FSM_STATE_CHAN3_WRITE_OFFSET 0x428 #define GC_DMA_FSM_STATE_CHAN3_ERROR_LSB 0x7 #define GC_DMA_FSM_STATE_CHAN3_ERROR_MASK 0x80 #define GC_DMA_FSM_STATE_CHAN3_ERROR_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN3_ERROR_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN3_ERROR_OFFSET 0x424 +#define GC_DMA_FSM_STATE_CHAN3_ERROR_OFFSET 0x428 +#define GC_DMA_FSM_STATE_CHAN3_PAUSE_LSB 0x8 +#define GC_DMA_FSM_STATE_CHAN3_PAUSE_MASK 0x100 +#define GC_DMA_FSM_STATE_CHAN3_PAUSE_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN3_PAUSE_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN3_PAUSE_OFFSET 0x428 #define GC_DMA_CTRL_CHAN4_CLR_ERROR_LSB 0x0 #define GC_DMA_CTRL_CHAN4_CLR_ERROR_MASK 0x1 #define GC_DMA_CTRL_CHAN4_CLR_ERROR_SIZE 0x1 @@ -7041,42 +7095,47 @@ #define GC_DMA_FSM_STATE_CHAN4_IDLE_MASK 0x1 #define GC_DMA_FSM_STATE_CHAN4_IDLE_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN4_IDLE_DEFAULT 0x1 -#define GC_DMA_FSM_STATE_CHAN4_IDLE_OFFSET 0x524 +#define GC_DMA_FSM_STATE_CHAN4_IDLE_OFFSET 0x528 #define GC_DMA_FSM_STATE_CHAN4_BID_READ_LSB 0x1 #define GC_DMA_FSM_STATE_CHAN4_BID_READ_MASK 0x2 #define GC_DMA_FSM_STATE_CHAN4_BID_READ_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN4_BID_READ_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN4_BID_READ_OFFSET 0x524 +#define GC_DMA_FSM_STATE_CHAN4_BID_READ_OFFSET 0x528 #define GC_DMA_FSM_STATE_CHAN4_BID_WRITE_LSB 0x2 #define GC_DMA_FSM_STATE_CHAN4_BID_WRITE_MASK 0x4 #define GC_DMA_FSM_STATE_CHAN4_BID_WRITE_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN4_BID_WRITE_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN4_BID_WRITE_OFFSET 0x524 +#define GC_DMA_FSM_STATE_CHAN4_BID_WRITE_OFFSET 0x528 #define GC_DMA_FSM_STATE_CHAN4_CHECK_EMPTY_LSB 0x3 #define GC_DMA_FSM_STATE_CHAN4_CHECK_EMPTY_MASK 0x8 #define GC_DMA_FSM_STATE_CHAN4_CHECK_EMPTY_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN4_CHECK_EMPTY_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN4_CHECK_EMPTY_OFFSET 0x524 +#define GC_DMA_FSM_STATE_CHAN4_CHECK_EMPTY_OFFSET 0x528 #define GC_DMA_FSM_STATE_CHAN4_CHECK_FULL_LSB 0x4 #define GC_DMA_FSM_STATE_CHAN4_CHECK_FULL_MASK 0x10 #define GC_DMA_FSM_STATE_CHAN4_CHECK_FULL_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN4_CHECK_FULL_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN4_CHECK_FULL_OFFSET 0x524 +#define GC_DMA_FSM_STATE_CHAN4_CHECK_FULL_OFFSET 0x528 #define GC_DMA_FSM_STATE_CHAN4_READ_LSB 0x5 #define GC_DMA_FSM_STATE_CHAN4_READ_MASK 0x20 #define GC_DMA_FSM_STATE_CHAN4_READ_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN4_READ_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN4_READ_OFFSET 0x524 +#define GC_DMA_FSM_STATE_CHAN4_READ_OFFSET 0x528 #define GC_DMA_FSM_STATE_CHAN4_WRITE_LSB 0x6 #define GC_DMA_FSM_STATE_CHAN4_WRITE_MASK 0x40 #define GC_DMA_FSM_STATE_CHAN4_WRITE_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN4_WRITE_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN4_WRITE_OFFSET 0x524 +#define GC_DMA_FSM_STATE_CHAN4_WRITE_OFFSET 0x528 #define GC_DMA_FSM_STATE_CHAN4_ERROR_LSB 0x7 #define GC_DMA_FSM_STATE_CHAN4_ERROR_MASK 0x80 #define GC_DMA_FSM_STATE_CHAN4_ERROR_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN4_ERROR_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN4_ERROR_OFFSET 0x524 +#define GC_DMA_FSM_STATE_CHAN4_ERROR_OFFSET 0x528 +#define GC_DMA_FSM_STATE_CHAN4_PAUSE_LSB 0x8 +#define GC_DMA_FSM_STATE_CHAN4_PAUSE_MASK 0x100 +#define GC_DMA_FSM_STATE_CHAN4_PAUSE_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN4_PAUSE_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN4_PAUSE_OFFSET 0x528 #define GC_DMA_CTRL_CHAN5_CLR_ERROR_LSB 0x0 #define GC_DMA_CTRL_CHAN5_CLR_ERROR_MASK 0x1 #define GC_DMA_CTRL_CHAN5_CLR_ERROR_SIZE 0x1 @@ -7126,42 +7185,47 @@ #define GC_DMA_FSM_STATE_CHAN5_IDLE_MASK 0x1 #define GC_DMA_FSM_STATE_CHAN5_IDLE_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN5_IDLE_DEFAULT 0x1 -#define GC_DMA_FSM_STATE_CHAN5_IDLE_OFFSET 0x624 +#define GC_DMA_FSM_STATE_CHAN5_IDLE_OFFSET 0x628 #define GC_DMA_FSM_STATE_CHAN5_BID_READ_LSB 0x1 #define GC_DMA_FSM_STATE_CHAN5_BID_READ_MASK 0x2 #define GC_DMA_FSM_STATE_CHAN5_BID_READ_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN5_BID_READ_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN5_BID_READ_OFFSET 0x624 +#define GC_DMA_FSM_STATE_CHAN5_BID_READ_OFFSET 0x628 #define GC_DMA_FSM_STATE_CHAN5_BID_WRITE_LSB 0x2 #define GC_DMA_FSM_STATE_CHAN5_BID_WRITE_MASK 0x4 #define GC_DMA_FSM_STATE_CHAN5_BID_WRITE_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN5_BID_WRITE_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN5_BID_WRITE_OFFSET 0x624 +#define GC_DMA_FSM_STATE_CHAN5_BID_WRITE_OFFSET 0x628 #define GC_DMA_FSM_STATE_CHAN5_CHECK_EMPTY_LSB 0x3 #define GC_DMA_FSM_STATE_CHAN5_CHECK_EMPTY_MASK 0x8 #define GC_DMA_FSM_STATE_CHAN5_CHECK_EMPTY_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN5_CHECK_EMPTY_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN5_CHECK_EMPTY_OFFSET 0x624 +#define GC_DMA_FSM_STATE_CHAN5_CHECK_EMPTY_OFFSET 0x628 #define GC_DMA_FSM_STATE_CHAN5_CHECK_FULL_LSB 0x4 #define GC_DMA_FSM_STATE_CHAN5_CHECK_FULL_MASK 0x10 #define GC_DMA_FSM_STATE_CHAN5_CHECK_FULL_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN5_CHECK_FULL_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN5_CHECK_FULL_OFFSET 0x624 +#define GC_DMA_FSM_STATE_CHAN5_CHECK_FULL_OFFSET 0x628 #define GC_DMA_FSM_STATE_CHAN5_READ_LSB 0x5 #define GC_DMA_FSM_STATE_CHAN5_READ_MASK 0x20 #define GC_DMA_FSM_STATE_CHAN5_READ_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN5_READ_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN5_READ_OFFSET 0x624 +#define GC_DMA_FSM_STATE_CHAN5_READ_OFFSET 0x628 #define GC_DMA_FSM_STATE_CHAN5_WRITE_LSB 0x6 #define GC_DMA_FSM_STATE_CHAN5_WRITE_MASK 0x40 #define GC_DMA_FSM_STATE_CHAN5_WRITE_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN5_WRITE_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN5_WRITE_OFFSET 0x624 +#define GC_DMA_FSM_STATE_CHAN5_WRITE_OFFSET 0x628 #define GC_DMA_FSM_STATE_CHAN5_ERROR_LSB 0x7 #define GC_DMA_FSM_STATE_CHAN5_ERROR_MASK 0x80 #define GC_DMA_FSM_STATE_CHAN5_ERROR_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN5_ERROR_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN5_ERROR_OFFSET 0x624 +#define GC_DMA_FSM_STATE_CHAN5_ERROR_OFFSET 0x628 +#define GC_DMA_FSM_STATE_CHAN5_PAUSE_LSB 0x8 +#define GC_DMA_FSM_STATE_CHAN5_PAUSE_MASK 0x100 +#define GC_DMA_FSM_STATE_CHAN5_PAUSE_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN5_PAUSE_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN5_PAUSE_OFFSET 0x628 #define GC_DMA_CTRL_CHAN6_CLR_ERROR_LSB 0x0 #define GC_DMA_CTRL_CHAN6_CLR_ERROR_MASK 0x1 #define GC_DMA_CTRL_CHAN6_CLR_ERROR_SIZE 0x1 @@ -7211,42 +7275,47 @@ #define GC_DMA_FSM_STATE_CHAN6_IDLE_MASK 0x1 #define GC_DMA_FSM_STATE_CHAN6_IDLE_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN6_IDLE_DEFAULT 0x1 -#define GC_DMA_FSM_STATE_CHAN6_IDLE_OFFSET 0x724 +#define GC_DMA_FSM_STATE_CHAN6_IDLE_OFFSET 0x728 #define GC_DMA_FSM_STATE_CHAN6_BID_READ_LSB 0x1 #define GC_DMA_FSM_STATE_CHAN6_BID_READ_MASK 0x2 #define GC_DMA_FSM_STATE_CHAN6_BID_READ_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN6_BID_READ_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN6_BID_READ_OFFSET 0x724 +#define GC_DMA_FSM_STATE_CHAN6_BID_READ_OFFSET 0x728 #define GC_DMA_FSM_STATE_CHAN6_BID_WRITE_LSB 0x2 #define GC_DMA_FSM_STATE_CHAN6_BID_WRITE_MASK 0x4 #define GC_DMA_FSM_STATE_CHAN6_BID_WRITE_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN6_BID_WRITE_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN6_BID_WRITE_OFFSET 0x724 +#define GC_DMA_FSM_STATE_CHAN6_BID_WRITE_OFFSET 0x728 #define GC_DMA_FSM_STATE_CHAN6_CHECK_EMPTY_LSB 0x3 #define GC_DMA_FSM_STATE_CHAN6_CHECK_EMPTY_MASK 0x8 #define GC_DMA_FSM_STATE_CHAN6_CHECK_EMPTY_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN6_CHECK_EMPTY_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN6_CHECK_EMPTY_OFFSET 0x724 +#define GC_DMA_FSM_STATE_CHAN6_CHECK_EMPTY_OFFSET 0x728 #define GC_DMA_FSM_STATE_CHAN6_CHECK_FULL_LSB 0x4 #define GC_DMA_FSM_STATE_CHAN6_CHECK_FULL_MASK 0x10 #define GC_DMA_FSM_STATE_CHAN6_CHECK_FULL_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN6_CHECK_FULL_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN6_CHECK_FULL_OFFSET 0x724 +#define GC_DMA_FSM_STATE_CHAN6_CHECK_FULL_OFFSET 0x728 #define GC_DMA_FSM_STATE_CHAN6_READ_LSB 0x5 #define GC_DMA_FSM_STATE_CHAN6_READ_MASK 0x20 #define GC_DMA_FSM_STATE_CHAN6_READ_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN6_READ_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN6_READ_OFFSET 0x724 +#define GC_DMA_FSM_STATE_CHAN6_READ_OFFSET 0x728 #define GC_DMA_FSM_STATE_CHAN6_WRITE_LSB 0x6 #define GC_DMA_FSM_STATE_CHAN6_WRITE_MASK 0x40 #define GC_DMA_FSM_STATE_CHAN6_WRITE_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN6_WRITE_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN6_WRITE_OFFSET 0x724 +#define GC_DMA_FSM_STATE_CHAN6_WRITE_OFFSET 0x728 #define GC_DMA_FSM_STATE_CHAN6_ERROR_LSB 0x7 #define GC_DMA_FSM_STATE_CHAN6_ERROR_MASK 0x80 #define GC_DMA_FSM_STATE_CHAN6_ERROR_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN6_ERROR_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN6_ERROR_OFFSET 0x724 +#define GC_DMA_FSM_STATE_CHAN6_ERROR_OFFSET 0x728 +#define GC_DMA_FSM_STATE_CHAN6_PAUSE_LSB 0x8 +#define GC_DMA_FSM_STATE_CHAN6_PAUSE_MASK 0x100 +#define GC_DMA_FSM_STATE_CHAN6_PAUSE_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN6_PAUSE_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN6_PAUSE_OFFSET 0x728 #define GC_DMA_CTRL_CHAN7_CLR_ERROR_LSB 0x0 #define GC_DMA_CTRL_CHAN7_CLR_ERROR_MASK 0x1 #define GC_DMA_CTRL_CHAN7_CLR_ERROR_SIZE 0x1 @@ -7296,42 +7365,47 @@ #define GC_DMA_FSM_STATE_CHAN7_IDLE_MASK 0x1 #define GC_DMA_FSM_STATE_CHAN7_IDLE_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN7_IDLE_DEFAULT 0x1 -#define GC_DMA_FSM_STATE_CHAN7_IDLE_OFFSET 0x824 +#define GC_DMA_FSM_STATE_CHAN7_IDLE_OFFSET 0x828 #define GC_DMA_FSM_STATE_CHAN7_BID_READ_LSB 0x1 #define GC_DMA_FSM_STATE_CHAN7_BID_READ_MASK 0x2 #define GC_DMA_FSM_STATE_CHAN7_BID_READ_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN7_BID_READ_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN7_BID_READ_OFFSET 0x824 +#define GC_DMA_FSM_STATE_CHAN7_BID_READ_OFFSET 0x828 #define GC_DMA_FSM_STATE_CHAN7_BID_WRITE_LSB 0x2 #define GC_DMA_FSM_STATE_CHAN7_BID_WRITE_MASK 0x4 #define GC_DMA_FSM_STATE_CHAN7_BID_WRITE_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN7_BID_WRITE_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN7_BID_WRITE_OFFSET 0x824 +#define GC_DMA_FSM_STATE_CHAN7_BID_WRITE_OFFSET 0x828 #define GC_DMA_FSM_STATE_CHAN7_CHECK_EMPTY_LSB 0x3 #define GC_DMA_FSM_STATE_CHAN7_CHECK_EMPTY_MASK 0x8 #define GC_DMA_FSM_STATE_CHAN7_CHECK_EMPTY_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN7_CHECK_EMPTY_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN7_CHECK_EMPTY_OFFSET 0x824 +#define GC_DMA_FSM_STATE_CHAN7_CHECK_EMPTY_OFFSET 0x828 #define GC_DMA_FSM_STATE_CHAN7_CHECK_FULL_LSB 0x4 #define GC_DMA_FSM_STATE_CHAN7_CHECK_FULL_MASK 0x10 #define GC_DMA_FSM_STATE_CHAN7_CHECK_FULL_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN7_CHECK_FULL_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN7_CHECK_FULL_OFFSET 0x824 +#define GC_DMA_FSM_STATE_CHAN7_CHECK_FULL_OFFSET 0x828 #define GC_DMA_FSM_STATE_CHAN7_READ_LSB 0x5 #define GC_DMA_FSM_STATE_CHAN7_READ_MASK 0x20 #define GC_DMA_FSM_STATE_CHAN7_READ_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN7_READ_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN7_READ_OFFSET 0x824 +#define GC_DMA_FSM_STATE_CHAN7_READ_OFFSET 0x828 #define GC_DMA_FSM_STATE_CHAN7_WRITE_LSB 0x6 #define GC_DMA_FSM_STATE_CHAN7_WRITE_MASK 0x40 #define GC_DMA_FSM_STATE_CHAN7_WRITE_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN7_WRITE_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN7_WRITE_OFFSET 0x824 +#define GC_DMA_FSM_STATE_CHAN7_WRITE_OFFSET 0x828 #define GC_DMA_FSM_STATE_CHAN7_ERROR_LSB 0x7 #define GC_DMA_FSM_STATE_CHAN7_ERROR_MASK 0x80 #define GC_DMA_FSM_STATE_CHAN7_ERROR_SIZE 0x1 #define GC_DMA_FSM_STATE_CHAN7_ERROR_DEFAULT 0x0 -#define GC_DMA_FSM_STATE_CHAN7_ERROR_OFFSET 0x824 +#define GC_DMA_FSM_STATE_CHAN7_ERROR_OFFSET 0x828 +#define GC_DMA_FSM_STATE_CHAN7_PAUSE_LSB 0x8 +#define GC_DMA_FSM_STATE_CHAN7_PAUSE_MASK 0x100 +#define GC_DMA_FSM_STATE_CHAN7_PAUSE_SIZE 0x1 +#define GC_DMA_FSM_STATE_CHAN7_PAUSE_DEFAULT 0x0 +#define GC_DMA_FSM_STATE_CHAN7_PAUSE_OFFSET 0x828 #define GC_FLASH_FSH_TRANS_OFFSET_LSB 0x0 #define GC_FLASH_FSH_TRANS_OFFSET_MASK 0xffff #define GC_FLASH_FSH_TRANS_OFFSET_SIZE 0x10 @@ -12907,6 +12981,26 @@ #define GC_KEYMGR_HKEY_ERR_CTRL_TM_LONG1_CHK_EN_SIZE 0x1 #define GC_KEYMGR_HKEY_ERR_CTRL_TM_LONG1_CHK_EN_DEFAULT 0x0 #define GC_KEYMGR_HKEY_ERR_CTRL_TM_LONG1_CHK_EN_OFFSET 0x3328 +#define GC_KEYMGR_HKEY_FLASH_RCV_STATUS_FBS_START_LSB 0x0 +#define GC_KEYMGR_HKEY_FLASH_RCV_STATUS_FBS_START_MASK 0x1 +#define GC_KEYMGR_HKEY_FLASH_RCV_STATUS_FBS_START_SIZE 0x1 +#define GC_KEYMGR_HKEY_FLASH_RCV_STATUS_FBS_START_DEFAULT 0x0 +#define GC_KEYMGR_HKEY_FLASH_RCV_STATUS_FBS_START_OFFSET 0x332c +#define GC_KEYMGR_HKEY_FLASH_RCV_STATUS_FBS_SUCCESS_LSB 0x1 +#define GC_KEYMGR_HKEY_FLASH_RCV_STATUS_FBS_SUCCESS_MASK 0x2 +#define GC_KEYMGR_HKEY_FLASH_RCV_STATUS_FBS_SUCCESS_SIZE 0x1 +#define GC_KEYMGR_HKEY_FLASH_RCV_STATUS_FBS_SUCCESS_DEFAULT 0x0 +#define GC_KEYMGR_HKEY_FLASH_RCV_STATUS_FBS_SUCCESS_OFFSET 0x332c +#define GC_KEYMGR_HKEY_FLASH_RCV_STATUS_RSR_START_LSB 0x2 +#define GC_KEYMGR_HKEY_FLASH_RCV_STATUS_RSR_START_MASK 0x4 +#define GC_KEYMGR_HKEY_FLASH_RCV_STATUS_RSR_START_SIZE 0x1 +#define GC_KEYMGR_HKEY_FLASH_RCV_STATUS_RSR_START_DEFAULT 0x0 +#define GC_KEYMGR_HKEY_FLASH_RCV_STATUS_RSR_START_OFFSET 0x332c +#define GC_KEYMGR_HKEY_FLASH_RCV_STATUS_RSR_SUCCESS_LSB 0x3 +#define GC_KEYMGR_HKEY_FLASH_RCV_STATUS_RSR_SUCCESS_MASK 0x8 +#define GC_KEYMGR_HKEY_FLASH_RCV_STATUS_RSR_SUCCESS_SIZE 0x1 +#define GC_KEYMGR_HKEY_FLASH_RCV_STATUS_RSR_SUCCESS_DEFAULT 0x0 +#define GC_KEYMGR_HKEY_FLASH_RCV_STATUS_RSR_SUCCESS_OFFSET 0x332c #define GC_PINMUX_DIOM0_CTL_DS_LSB 0x0 #define GC_PINMUX_DIOM0_CTL_DS_MASK 0x3 #define GC_PINMUX_DIOM0_CTL_DS_SIZE 0x2 @@ -14918,12 +15012,12 @@ #define GC_PMU_PERICLKSET1_DVOLT0_CLK_LSB 0xa #define GC_PMU_PERICLKSET1_DVOLT0_CLK_MASK 0x400 #define GC_PMU_PERICLKSET1_DVOLT0_CLK_SIZE 0x1 -#define GC_PMU_PERICLKSET1_DVOLT0_CLK_DEFAULT 0x0 +#define GC_PMU_PERICLKSET1_DVOLT0_CLK_DEFAULT 0x1 #define GC_PMU_PERICLKSET1_DVOLT0_CLK_OFFSET 0x6c #define GC_PMU_PERICLKSET1_DWATCHDOG0_CLK_LSB 0xb #define GC_PMU_PERICLKSET1_DWATCHDOG0_CLK_MASK 0x800 #define GC_PMU_PERICLKSET1_DWATCHDOG0_CLK_SIZE 0x1 -#define GC_PMU_PERICLKSET1_DWATCHDOG0_CLK_DEFAULT 0x0 +#define GC_PMU_PERICLKSET1_DWATCHDOG0_CLK_DEFAULT 0x1 #define GC_PMU_PERICLKSET1_DWATCHDOG0_CLK_OFFSET 0x6c #define GC_PMU_PERICLKSET1_DXO0_CLK_LSB 0xc #define GC_PMU_PERICLKSET1_DXO0_CLK_MASK 0x1000 @@ -14998,12 +15092,12 @@ #define GC_PMU_PERICLKCLR1_DVOLT0_CLK_LSB 0xa #define GC_PMU_PERICLKCLR1_DVOLT0_CLK_MASK 0x400 #define GC_PMU_PERICLKCLR1_DVOLT0_CLK_SIZE 0x1 -#define GC_PMU_PERICLKCLR1_DVOLT0_CLK_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR1_DVOLT0_CLK_DEFAULT 0x1 #define GC_PMU_PERICLKCLR1_DVOLT0_CLK_OFFSET 0x70 #define GC_PMU_PERICLKCLR1_DWATCHDOG0_CLK_LSB 0xb #define GC_PMU_PERICLKCLR1_DWATCHDOG0_CLK_MASK 0x800 #define GC_PMU_PERICLKCLR1_DWATCHDOG0_CLK_SIZE 0x1 -#define GC_PMU_PERICLKCLR1_DWATCHDOG0_CLK_DEFAULT 0x0 +#define GC_PMU_PERICLKCLR1_DWATCHDOG0_CLK_DEFAULT 0x1 #define GC_PMU_PERICLKCLR1_DWATCHDOG0_CLK_OFFSET 0x70 #define GC_PMU_PERICLKCLR1_DXO0_CLK_LSB 0xc #define GC_PMU_PERICLKCLR1_DXO0_CLK_MASK 0x1000 @@ -15028,7 +15122,7 @@ #define GC_PMU_CLK_RO_MASK0_DCAMO0_CLK_LSB 0x0 #define GC_PMU_CLK_RO_MASK0_DCAMO0_CLK_MASK 0x1 #define GC_PMU_CLK_RO_MASK0_DCAMO0_CLK_SIZE 0x1 -#define GC_PMU_CLK_RO_MASK0_DCAMO0_CLK_DEFAULT 0x0 +#define GC_PMU_CLK_RO_MASK0_DCAMO0_CLK_DEFAULT 0x1 #define GC_PMU_CLK_RO_MASK0_DCAMO0_CLK_OFFSET 0x74 #define GC_PMU_CLK_RO_MASK0_DCRYPTO0_CLK_LSB 0x1 #define GC_PMU_CLK_RO_MASK0_DCRYPTO0_CLK_MASK 0x2 @@ -15183,7 +15277,7 @@ #define GC_PMU_CLK_RO_MASK0_DTEMP0_CLK_LSB 0x1f #define GC_PMU_CLK_RO_MASK0_DTEMP0_CLK_MASK 0x80000000 #define GC_PMU_CLK_RO_MASK0_DTEMP0_CLK_SIZE 0x1 -#define GC_PMU_CLK_RO_MASK0_DTEMP0_CLK_DEFAULT 0x0 +#define GC_PMU_CLK_RO_MASK0_DTEMP0_CLK_DEFAULT 0x1 #define GC_PMU_CLK_RO_MASK0_DTEMP0_CLK_OFFSET 0x74 #define GC_PMU_CLK_RO_MASK1_DTIMEHS0_CLK_TIMER_LSB 0x0 #define GC_PMU_CLK_RO_MASK1_DTIMEHS0_CLK_TIMER_MASK 0x1 @@ -15238,12 +15332,12 @@ #define GC_PMU_CLK_RO_MASK1_DVOLT0_CLK_LSB 0xa #define GC_PMU_CLK_RO_MASK1_DVOLT0_CLK_MASK 0x400 #define GC_PMU_CLK_RO_MASK1_DVOLT0_CLK_SIZE 0x1 -#define GC_PMU_CLK_RO_MASK1_DVOLT0_CLK_DEFAULT 0x0 +#define GC_PMU_CLK_RO_MASK1_DVOLT0_CLK_DEFAULT 0x1 #define GC_PMU_CLK_RO_MASK1_DVOLT0_CLK_OFFSET 0x78 #define GC_PMU_CLK_RO_MASK1_DWATCHDOG0_CLK_LSB 0xb #define GC_PMU_CLK_RO_MASK1_DWATCHDOG0_CLK_MASK 0x800 #define GC_PMU_CLK_RO_MASK1_DWATCHDOG0_CLK_SIZE 0x1 -#define GC_PMU_CLK_RO_MASK1_DWATCHDOG0_CLK_DEFAULT 0x0 +#define GC_PMU_CLK_RO_MASK1_DWATCHDOG0_CLK_DEFAULT 0x1 #define GC_PMU_CLK_RO_MASK1_DWATCHDOG0_CLK_OFFSET 0x78 #define GC_PMU_CLK_RO_MASK1_DXO0_CLK_LSB 0xc #define GC_PMU_CLK_RO_MASK1_DXO0_CLK_MASK 0x1000 @@ -15784,302 +15878,302 @@ #define GC_PMU_RST0_DCAMO0_AON_MASK 0x1 #define GC_PMU_RST0_DCAMO0_AON_SIZE 0x1 #define GC_PMU_RST0_DCAMO0_AON_DEFAULT 0x0 -#define GC_PMU_RST0_DCAMO0_AON_OFFSET 0x90 +#define GC_PMU_RST0_DCAMO0_AON_OFFSET 0x94 #define GC_PMU_RST0_DCRYPTO0_LSB 0x1 #define GC_PMU_RST0_DCRYPTO0_MASK 0x2 #define GC_PMU_RST0_DCRYPTO0_SIZE 0x1 #define GC_PMU_RST0_DCRYPTO0_DEFAULT 0x0 -#define GC_PMU_RST0_DCRYPTO0_OFFSET 0x90 +#define GC_PMU_RST0_DCRYPTO0_OFFSET 0x94 #define GC_PMU_RST0_DDMA0_LSB 0x2 #define GC_PMU_RST0_DDMA0_MASK 0x4 #define GC_PMU_RST0_DDMA0_SIZE 0x1 #define GC_PMU_RST0_DDMA0_DEFAULT 0x0 -#define GC_PMU_RST0_DDMA0_OFFSET 0x90 +#define GC_PMU_RST0_DDMA0_OFFSET 0x94 #define GC_PMU_RST0_DFLASH0_LSB 0x3 #define GC_PMU_RST0_DFLASH0_MASK 0x8 #define GC_PMU_RST0_DFLASH0_SIZE 0x1 #define GC_PMU_RST0_DFLASH0_DEFAULT 0x0 -#define GC_PMU_RST0_DFLASH0_OFFSET 0x90 +#define GC_PMU_RST0_DFLASH0_OFFSET 0x94 #define GC_PMU_RST0_DFUSE0_LSB 0x4 #define GC_PMU_RST0_DFUSE0_MASK 0x10 #define GC_PMU_RST0_DFUSE0_SIZE 0x1 #define GC_PMU_RST0_DFUSE0_DEFAULT 0x0 -#define GC_PMU_RST0_DFUSE0_OFFSET 0x90 +#define GC_PMU_RST0_DFUSE0_OFFSET 0x94 #define GC_PMU_RST0_DGLOBALSEC_LSB 0x5 #define GC_PMU_RST0_DGLOBALSEC_MASK 0x20 #define GC_PMU_RST0_DGLOBALSEC_SIZE 0x1 #define GC_PMU_RST0_DGLOBALSEC_DEFAULT 0x0 -#define GC_PMU_RST0_DGLOBALSEC_OFFSET 0x90 +#define GC_PMU_RST0_DGLOBALSEC_OFFSET 0x94 #define GC_PMU_RST0_DGLOBALSEC_CLK_TIMER_LSB 0x6 #define GC_PMU_RST0_DGLOBALSEC_CLK_TIMER_MASK 0x40 #define GC_PMU_RST0_DGLOBALSEC_CLK_TIMER_SIZE 0x1 #define GC_PMU_RST0_DGLOBALSEC_CLK_TIMER_DEFAULT 0x0 -#define GC_PMU_RST0_DGLOBALSEC_CLK_TIMER_OFFSET 0x90 +#define GC_PMU_RST0_DGLOBALSEC_CLK_TIMER_OFFSET 0x94 #define GC_PMU_RST0_DGLOBALSEC_CLK_HS_LSB 0x7 #define GC_PMU_RST0_DGLOBALSEC_CLK_HS_MASK 0x80 #define GC_PMU_RST0_DGLOBALSEC_CLK_HS_SIZE 0x1 #define GC_PMU_RST0_DGLOBALSEC_CLK_HS_DEFAULT 0x0 -#define GC_PMU_RST0_DGLOBALSEC_CLK_HS_OFFSET 0x90 +#define GC_PMU_RST0_DGLOBALSEC_CLK_HS_OFFSET 0x94 #define GC_PMU_RST0_DGPIO0_LSB 0x8 #define GC_PMU_RST0_DGPIO0_MASK 0x100 #define GC_PMU_RST0_DGPIO0_SIZE 0x1 #define GC_PMU_RST0_DGPIO0_DEFAULT 0x0 -#define GC_PMU_RST0_DGPIO0_OFFSET 0x90 +#define GC_PMU_RST0_DGPIO0_OFFSET 0x94 #define GC_PMU_RST0_DGPIO1_LSB 0x9 #define GC_PMU_RST0_DGPIO1_MASK 0x200 #define GC_PMU_RST0_DGPIO1_SIZE 0x1 #define GC_PMU_RST0_DGPIO1_DEFAULT 0x0 -#define GC_PMU_RST0_DGPIO1_OFFSET 0x90 +#define GC_PMU_RST0_DGPIO1_OFFSET 0x94 #define GC_PMU_RST0_DI2C0_CLK_TIMER_LSB 0xa #define GC_PMU_RST0_DI2C0_CLK_TIMER_MASK 0x400 #define GC_PMU_RST0_DI2C0_CLK_TIMER_SIZE 0x1 #define GC_PMU_RST0_DI2C0_CLK_TIMER_DEFAULT 0x0 -#define GC_PMU_RST0_DI2C0_CLK_TIMER_OFFSET 0x90 +#define GC_PMU_RST0_DI2C0_CLK_TIMER_OFFSET 0x94 #define GC_PMU_RST0_DI2C1_CLK_TIMER_LSB 0xb #define GC_PMU_RST0_DI2C1_CLK_TIMER_MASK 0x800 #define GC_PMU_RST0_DI2C1_CLK_TIMER_SIZE 0x1 #define GC_PMU_RST0_DI2C1_CLK_TIMER_DEFAULT 0x0 -#define GC_PMU_RST0_DI2C1_CLK_TIMER_OFFSET 0x90 +#define GC_PMU_RST0_DI2C1_CLK_TIMER_OFFSET 0x94 #define GC_PMU_RST0_DI2CS0_LSB 0xc #define GC_PMU_RST0_DI2CS0_MASK 0x1000 #define GC_PMU_RST0_DI2CS0_SIZE 0x1 #define GC_PMU_RST0_DI2CS0_DEFAULT 0x0 -#define GC_PMU_RST0_DI2CS0_OFFSET 0x90 +#define GC_PMU_RST0_DI2CS0_OFFSET 0x94 #define GC_PMU_RST0_DKEYMGR0_LSB 0xd #define GC_PMU_RST0_DKEYMGR0_MASK 0x2000 #define GC_PMU_RST0_DKEYMGR0_SIZE 0x1 #define GC_PMU_RST0_DKEYMGR0_DEFAULT 0x0 -#define GC_PMU_RST0_DKEYMGR0_OFFSET 0x90 +#define GC_PMU_RST0_DKEYMGR0_OFFSET 0x94 #define GC_PMU_RST0_DPERI_APB0_LSB 0xe #define GC_PMU_RST0_DPERI_APB0_MASK 0x4000 #define GC_PMU_RST0_DPERI_APB0_SIZE 0x1 #define GC_PMU_RST0_DPERI_APB0_DEFAULT 0x0 -#define GC_PMU_RST0_DPERI_APB0_OFFSET 0x90 +#define GC_PMU_RST0_DPERI_APB0_OFFSET 0x94 #define GC_PMU_RST0_DPERI_APB1_LSB 0xf #define GC_PMU_RST0_DPERI_APB1_MASK 0x8000 #define GC_PMU_RST0_DPERI_APB1_SIZE 0x1 #define GC_PMU_RST0_DPERI_APB1_DEFAULT 0x0 -#define GC_PMU_RST0_DPERI_APB1_OFFSET 0x90 +#define GC_PMU_RST0_DPERI_APB1_OFFSET 0x94 #define GC_PMU_RST0_DPERI_APB2_LSB 0x10 #define GC_PMU_RST0_DPERI_APB2_MASK 0x10000 #define GC_PMU_RST0_DPERI_APB2_SIZE 0x1 #define GC_PMU_RST0_DPERI_APB2_DEFAULT 0x0 -#define GC_PMU_RST0_DPERI_APB2_OFFSET 0x90 +#define GC_PMU_RST0_DPERI_APB2_OFFSET 0x94 #define GC_PMU_RST0_DPERI_APB2_CLK_TIMER_LSB 0x11 #define GC_PMU_RST0_DPERI_APB2_CLK_TIMER_MASK 0x20000 #define GC_PMU_RST0_DPERI_APB2_CLK_TIMER_SIZE 0x1 #define GC_PMU_RST0_DPERI_APB2_CLK_TIMER_DEFAULT 0x0 -#define GC_PMU_RST0_DPERI_APB2_CLK_TIMER_OFFSET 0x90 +#define GC_PMU_RST0_DPERI_APB2_CLK_TIMER_OFFSET 0x94 #define GC_PMU_RST0_DPERI_APB3_LSB 0x12 #define GC_PMU_RST0_DPERI_APB3_MASK 0x40000 #define GC_PMU_RST0_DPERI_APB3_SIZE 0x1 #define GC_PMU_RST0_DPERI_APB3_DEFAULT 0x0 -#define GC_PMU_RST0_DPERI_APB3_OFFSET 0x90 +#define GC_PMU_RST0_DPERI_APB3_OFFSET 0x94 #define GC_PMU_RST0_DPERI_APB3_CLK_HS_LSB 0x13 #define GC_PMU_RST0_DPERI_APB3_CLK_HS_MASK 0x80000 #define GC_PMU_RST0_DPERI_APB3_CLK_HS_SIZE 0x1 #define GC_PMU_RST0_DPERI_APB3_CLK_HS_DEFAULT 0x0 -#define GC_PMU_RST0_DPERI_APB3_CLK_HS_OFFSET 0x90 +#define GC_PMU_RST0_DPERI_APB3_CLK_HS_OFFSET 0x94 #define GC_PMU_RST0_DPINMUX_AON_LSB 0x14 #define GC_PMU_RST0_DPINMUX_AON_MASK 0x100000 #define GC_PMU_RST0_DPINMUX_AON_SIZE 0x1 #define GC_PMU_RST0_DPINMUX_AON_DEFAULT 0x0 -#define GC_PMU_RST0_DPINMUX_AON_OFFSET 0x90 +#define GC_PMU_RST0_DPINMUX_AON_OFFSET 0x94 #define GC_PMU_RST0_DPMU_AON_LSB 0x15 #define GC_PMU_RST0_DPMU_AON_MASK 0x200000 #define GC_PMU_RST0_DPMU_AON_SIZE 0x1 #define GC_PMU_RST0_DPMU_AON_DEFAULT 0x0 -#define GC_PMU_RST0_DPMU_AON_OFFSET 0x90 +#define GC_PMU_RST0_DPMU_AON_OFFSET 0x94 #define GC_PMU_RST0_DRBOX0_AON_LSB 0x16 #define GC_PMU_RST0_DRBOX0_AON_MASK 0x400000 #define GC_PMU_RST0_DRBOX0_AON_SIZE 0x1 #define GC_PMU_RST0_DRBOX0_AON_DEFAULT 0x0 -#define GC_PMU_RST0_DRBOX0_AON_OFFSET 0x90 +#define GC_PMU_RST0_DRBOX0_AON_OFFSET 0x94 #define GC_PMU_RST0_DRDD0_AON_LSB 0x17 #define GC_PMU_RST0_DRDD0_AON_MASK 0x800000 #define GC_PMU_RST0_DRDD0_AON_SIZE 0x1 #define GC_PMU_RST0_DRDD0_AON_DEFAULT 0x0 -#define GC_PMU_RST0_DRDD0_AON_OFFSET 0x90 +#define GC_PMU_RST0_DRDD0_AON_OFFSET 0x94 #define GC_PMU_RST0_DRTC0_AON_LSB 0x18 #define GC_PMU_RST0_DRTC0_AON_MASK 0x1000000 #define GC_PMU_RST0_DRTC0_AON_SIZE 0x1 #define GC_PMU_RST0_DRTC0_AON_DEFAULT 0x0 -#define GC_PMU_RST0_DRTC0_AON_OFFSET 0x90 +#define GC_PMU_RST0_DRTC0_AON_OFFSET 0x94 #define GC_PMU_RST0_DRTC0_CLK_TIMER_AON_LSB 0x19 #define GC_PMU_RST0_DRTC0_CLK_TIMER_AON_MASK 0x2000000 #define GC_PMU_RST0_DRTC0_CLK_TIMER_AON_SIZE 0x1 #define GC_PMU_RST0_DRTC0_CLK_TIMER_AON_DEFAULT 0x0 -#define GC_PMU_RST0_DRTC0_CLK_TIMER_AON_OFFSET 0x90 +#define GC_PMU_RST0_DRTC0_CLK_TIMER_AON_OFFSET 0x94 #define GC_PMU_RST0_DSPI0_CLK_HS_LSB 0x1a #define GC_PMU_RST0_DSPI0_CLK_HS_MASK 0x4000000 #define GC_PMU_RST0_DSPI0_CLK_HS_SIZE 0x1 #define GC_PMU_RST0_DSPI0_CLK_HS_DEFAULT 0x0 -#define GC_PMU_RST0_DSPI0_CLK_HS_OFFSET 0x90 +#define GC_PMU_RST0_DSPI0_CLK_HS_OFFSET 0x94 #define GC_PMU_RST0_DSPI1_CLK_HS_LSB 0x1b #define GC_PMU_RST0_DSPI1_CLK_HS_MASK 0x8000000 #define GC_PMU_RST0_DSPI1_CLK_HS_SIZE 0x1 #define GC_PMU_RST0_DSPI1_CLK_HS_DEFAULT 0x0 -#define GC_PMU_RST0_DSPI1_CLK_HS_OFFSET 0x90 +#define GC_PMU_RST0_DSPI1_CLK_HS_OFFSET 0x94 #define GC_PMU_RST0_DSPS0_LSB 0x1c #define GC_PMU_RST0_DSPS0_MASK 0x10000000 #define GC_PMU_RST0_DSPS0_SIZE 0x1 #define GC_PMU_RST0_DSPS0_DEFAULT 0x0 -#define GC_PMU_RST0_DSPS0_OFFSET 0x90 +#define GC_PMU_RST0_DSPS0_OFFSET 0x94 #define GC_PMU_RST0_DSPS0_CLK_TIMER_HS_LSB 0x1d #define GC_PMU_RST0_DSPS0_CLK_TIMER_HS_MASK 0x20000000 #define GC_PMU_RST0_DSPS0_CLK_TIMER_HS_SIZE 0x1 #define GC_PMU_RST0_DSPS0_CLK_TIMER_HS_DEFAULT 0x0 -#define GC_PMU_RST0_DSPS0_CLK_TIMER_HS_OFFSET 0x90 +#define GC_PMU_RST0_DSPS0_CLK_TIMER_HS_OFFSET 0x94 #define GC_PMU_RST0_DSWDP0_LSB 0x1e #define GC_PMU_RST0_DSWDP0_MASK 0x40000000 #define GC_PMU_RST0_DSWDP0_SIZE 0x1 #define GC_PMU_RST0_DSWDP0_DEFAULT 0x0 -#define GC_PMU_RST0_DSWDP0_OFFSET 0x90 +#define GC_PMU_RST0_DSWDP0_OFFSET 0x94 #define GC_PMU_RST0_DTEMP0_LSB 0x1f #define GC_PMU_RST0_DTEMP0_MASK 0x80000000 #define GC_PMU_RST0_DTEMP0_SIZE 0x1 #define GC_PMU_RST0_DTEMP0_DEFAULT 0x0 -#define GC_PMU_RST0_DTEMP0_OFFSET 0x90 +#define GC_PMU_RST0_DTEMP0_OFFSET 0x94 #define GC_PMU_RST1_DTIMEHS0_CLK_TIMER_LSB 0x0 #define GC_PMU_RST1_DTIMEHS0_CLK_TIMER_MASK 0x1 #define GC_PMU_RST1_DTIMEHS0_CLK_TIMER_SIZE 0x1 #define GC_PMU_RST1_DTIMEHS0_CLK_TIMER_DEFAULT 0x0 -#define GC_PMU_RST1_DTIMEHS0_CLK_TIMER_OFFSET 0x94 +#define GC_PMU_RST1_DTIMEHS0_CLK_TIMER_OFFSET 0x9c #define GC_PMU_RST1_DTIMEHS1_CLK_TIMER_LSB 0x1 #define GC_PMU_RST1_DTIMEHS1_CLK_TIMER_MASK 0x2 #define GC_PMU_RST1_DTIMEHS1_CLK_TIMER_SIZE 0x1 #define GC_PMU_RST1_DTIMEHS1_CLK_TIMER_DEFAULT 0x0 -#define GC_PMU_RST1_DTIMEHS1_CLK_TIMER_OFFSET 0x94 +#define GC_PMU_RST1_DTIMEHS1_CLK_TIMER_OFFSET 0x9c #define GC_PMU_RST1_DTIMELS0_AON_LSB 0x2 #define GC_PMU_RST1_DTIMELS0_AON_MASK 0x4 #define GC_PMU_RST1_DTIMELS0_AON_SIZE 0x1 #define GC_PMU_RST1_DTIMELS0_AON_DEFAULT 0x0 -#define GC_PMU_RST1_DTIMELS0_AON_OFFSET 0x94 +#define GC_PMU_RST1_DTIMELS0_AON_OFFSET 0x9c #define GC_PMU_RST1_DTIMEUS0_CLK_TIMER_LSB 0x3 #define GC_PMU_RST1_DTIMEUS0_CLK_TIMER_MASK 0x8 #define GC_PMU_RST1_DTIMEUS0_CLK_TIMER_SIZE 0x1 #define GC_PMU_RST1_DTIMEUS0_CLK_TIMER_DEFAULT 0x0 -#define GC_PMU_RST1_DTIMEUS0_CLK_TIMER_OFFSET 0x94 +#define GC_PMU_RST1_DTIMEUS0_CLK_TIMER_OFFSET 0x9c #define GC_PMU_RST1_DTRNG0_LSB 0x4 #define GC_PMU_RST1_DTRNG0_MASK 0x10 #define GC_PMU_RST1_DTRNG0_SIZE 0x1 #define GC_PMU_RST1_DTRNG0_DEFAULT 0x0 -#define GC_PMU_RST1_DTRNG0_OFFSET 0x94 +#define GC_PMU_RST1_DTRNG0_OFFSET 0x9c #define GC_PMU_RST1_DUART0_CLK_TIMER_LSB 0x5 #define GC_PMU_RST1_DUART0_CLK_TIMER_MASK 0x20 #define GC_PMU_RST1_DUART0_CLK_TIMER_SIZE 0x1 #define GC_PMU_RST1_DUART0_CLK_TIMER_DEFAULT 0x0 -#define GC_PMU_RST1_DUART0_CLK_TIMER_OFFSET 0x94 +#define GC_PMU_RST1_DUART0_CLK_TIMER_OFFSET 0x9c #define GC_PMU_RST1_DUART1_CLK_TIMER_LSB 0x6 #define GC_PMU_RST1_DUART1_CLK_TIMER_MASK 0x40 #define GC_PMU_RST1_DUART1_CLK_TIMER_SIZE 0x1 #define GC_PMU_RST1_DUART1_CLK_TIMER_DEFAULT 0x0 -#define GC_PMU_RST1_DUART1_CLK_TIMER_OFFSET 0x94 +#define GC_PMU_RST1_DUART1_CLK_TIMER_OFFSET 0x9c #define GC_PMU_RST1_DUART2_CLK_TIMER_LSB 0x7 #define GC_PMU_RST1_DUART2_CLK_TIMER_MASK 0x80 #define GC_PMU_RST1_DUART2_CLK_TIMER_SIZE 0x1 #define GC_PMU_RST1_DUART2_CLK_TIMER_DEFAULT 0x0 -#define GC_PMU_RST1_DUART2_CLK_TIMER_OFFSET 0x94 +#define GC_PMU_RST1_DUART2_CLK_TIMER_OFFSET 0x9c #define GC_PMU_RST1_DUSB0_LSB 0x8 #define GC_PMU_RST1_DUSB0_MASK 0x100 #define GC_PMU_RST1_DUSB0_SIZE 0x1 #define GC_PMU_RST1_DUSB0_DEFAULT 0x0 -#define GC_PMU_RST1_DUSB0_OFFSET 0x94 +#define GC_PMU_RST1_DUSB0_OFFSET 0x9c #define GC_PMU_RST1_DUSB0_AON_LSB 0x9 #define GC_PMU_RST1_DUSB0_AON_MASK 0x200 #define GC_PMU_RST1_DUSB0_AON_SIZE 0x1 #define GC_PMU_RST1_DUSB0_AON_DEFAULT 0x0 -#define GC_PMU_RST1_DUSB0_AON_OFFSET 0x94 +#define GC_PMU_RST1_DUSB0_AON_OFFSET 0x9c #define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_LSB 0xa #define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_MASK 0x400 #define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_SIZE 0x1 #define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_DEFAULT 0x0 -#define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_OFFSET 0x94 +#define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_OFFSET 0x9c #define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_AON_LSB 0xb #define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_AON_MASK 0x800 #define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_AON_SIZE 0x1 #define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_AON_DEFAULT 0x0 -#define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_AON_OFFSET 0x94 +#define GC_PMU_RST1_DUSB0_CLK_TIMER_HS_AON_OFFSET 0x9c #define GC_PMU_RST1_DVOLT0_LSB 0xc #define GC_PMU_RST1_DVOLT0_MASK 0x1000 #define GC_PMU_RST1_DVOLT0_SIZE 0x1 #define GC_PMU_RST1_DVOLT0_DEFAULT 0x0 -#define GC_PMU_RST1_DVOLT0_OFFSET 0x94 +#define GC_PMU_RST1_DVOLT0_OFFSET 0x9c #define GC_PMU_RST1_DWATCHDOG0_LSB 0xd #define GC_PMU_RST1_DWATCHDOG0_MASK 0x2000 #define GC_PMU_RST1_DWATCHDOG0_SIZE 0x1 #define GC_PMU_RST1_DWATCHDOG0_DEFAULT 0x0 -#define GC_PMU_RST1_DWATCHDOG0_OFFSET 0x94 +#define GC_PMU_RST1_DWATCHDOG0_OFFSET 0x9c #define GC_PMU_RST1_DXO0_AON_LSB 0xe #define GC_PMU_RST1_DXO0_AON_MASK 0x4000 #define GC_PMU_RST1_DXO0_AON_SIZE 0x1 #define GC_PMU_RST1_DXO0_AON_DEFAULT 0x0 -#define GC_PMU_RST1_DXO0_AON_OFFSET 0x94 +#define GC_PMU_RST1_DXO0_AON_OFFSET 0x9c #define GC_PMU_RST1_DXO0_CLK_TIMER_AON_LSB 0xf #define GC_PMU_RST1_DXO0_CLK_TIMER_AON_MASK 0x8000 #define GC_PMU_RST1_DXO0_CLK_TIMER_AON_SIZE 0x1 #define GC_PMU_RST1_DXO0_CLK_TIMER_AON_DEFAULT 0x0 -#define GC_PMU_RST1_DXO0_CLK_TIMER_AON_OFFSET 0x94 +#define GC_PMU_RST1_DXO0_CLK_TIMER_AON_OFFSET 0x9c #define GC_PMU_RST1_PERI_MASTER_MATRIX_LSB 0x10 #define GC_PMU_RST1_PERI_MASTER_MATRIX_MASK 0x10000 #define GC_PMU_RST1_PERI_MASTER_MATRIX_SIZE 0x1 #define GC_PMU_RST1_PERI_MASTER_MATRIX_DEFAULT 0x0 -#define GC_PMU_RST1_PERI_MASTER_MATRIX_OFFSET 0x94 +#define GC_PMU_RST1_PERI_MASTER_MATRIX_OFFSET 0x9c #define GC_PMU_RST1_PERI_MATRIX_LSB 0x11 #define GC_PMU_RST1_PERI_MATRIX_MASK 0x20000 #define GC_PMU_RST1_PERI_MATRIX_SIZE 0x1 #define GC_PMU_RST1_PERI_MATRIX_DEFAULT 0x0 -#define GC_PMU_RST1_PERI_MATRIX_OFFSET 0x94 +#define GC_PMU_RST1_PERI_MATRIX_OFFSET 0x9c #define GC_PMU_RST1_SEC_FABRIC_LSB 0x12 #define GC_PMU_RST1_SEC_FABRIC_MASK 0x40000 #define GC_PMU_RST1_SEC_FABRIC_SIZE 0x1 #define GC_PMU_RST1_SEC_FABRIC_DEFAULT 0x0 -#define GC_PMU_RST1_SEC_FABRIC_OFFSET 0x94 +#define GC_PMU_RST1_SEC_FABRIC_OFFSET 0x9c #define GC_PMU_RST1_SEC_FABRIC_CLK_TIMER_LSB 0x13 #define GC_PMU_RST1_SEC_FABRIC_CLK_TIMER_MASK 0x80000 #define GC_PMU_RST1_SEC_FABRIC_CLK_TIMER_SIZE 0x1 #define GC_PMU_RST1_SEC_FABRIC_CLK_TIMER_DEFAULT 0x0 -#define GC_PMU_RST1_SEC_FABRIC_CLK_TIMER_OFFSET 0x94 +#define GC_PMU_RST1_SEC_FABRIC_CLK_TIMER_OFFSET 0x9c #define GC_PMU_RST1_SEC_FABRIC_CLK_HS_LSB 0x14 #define GC_PMU_RST1_SEC_FABRIC_CLK_HS_MASK 0x100000 #define GC_PMU_RST1_SEC_FABRIC_CLK_HS_SIZE 0x1 #define GC_PMU_RST1_SEC_FABRIC_CLK_HS_DEFAULT 0x0 -#define GC_PMU_RST1_SEC_FABRIC_CLK_HS_OFFSET 0x94 +#define GC_PMU_RST1_SEC_FABRIC_CLK_HS_OFFSET 0x9c #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG0_LSB 0x0 #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG0_MASK 0x1 #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG0_SIZE 0x1 #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG0_DEFAULT 0x0 -#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG0_OFFSET 0x120 +#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG0_OFFSET 0x128 #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG1_LSB 0x1 #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG1_MASK 0x2 #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG1_SIZE 0x1 #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG1_DEFAULT 0x0 -#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG1_OFFSET 0x120 +#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG1_OFFSET 0x128 #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG2_LSB 0x2 #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG2_MASK 0x4 #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG2_SIZE 0x1 #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG2_DEFAULT 0x0 -#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG2_OFFSET 0x120 +#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG2_OFFSET 0x128 #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG3_LSB 0x3 #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG3_MASK 0x8 #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG3_SIZE 0x1 #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG3_DEFAULT 0x0 -#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG3_OFFSET 0x120 +#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG3_OFFSET 0x128 #define GC_PMU_INT_ENABLE_INTR_WAKEUP_LSB 0x0 #define GC_PMU_INT_ENABLE_INTR_WAKEUP_MASK 0x1 #define GC_PMU_INT_ENABLE_INTR_WAKEUP_SIZE 0x1 #define GC_PMU_INT_ENABLE_INTR_WAKEUP_DEFAULT 0x0 -#define GC_PMU_INT_ENABLE_INTR_WAKEUP_OFFSET 0x134 +#define GC_PMU_INT_ENABLE_INTR_WAKEUP_OFFSET 0x13c #define GC_PMU_INT_STATE_INTR_WAKEUP_LSB 0x0 #define GC_PMU_INT_STATE_INTR_WAKEUP_MASK 0x1 #define GC_PMU_INT_STATE_INTR_WAKEUP_SIZE 0x1 #define GC_PMU_INT_STATE_INTR_WAKEUP_DEFAULT 0x0 -#define GC_PMU_INT_STATE_INTR_WAKEUP_OFFSET 0x138 +#define GC_PMU_INT_STATE_INTR_WAKEUP_OFFSET 0x140 #define GC_PMU_INT_TEST_INTR_WAKEUP_LSB 0x0 #define GC_PMU_INT_TEST_INTR_WAKEUP_MASK 0x1 #define GC_PMU_INT_TEST_INTR_WAKEUP_SIZE 0x1 #define GC_PMU_INT_TEST_INTR_WAKEUP_DEFAULT 0x0 -#define GC_PMU_INT_TEST_INTR_WAKEUP_OFFSET 0x13c +#define GC_PMU_INT_TEST_INTR_WAKEUP_OFFSET 0x144 #define GC_PMU_ANTEST_TOP_CTRL_ATEST_PAD_ENB_LSB 0x0 #define GC_PMU_ANTEST_TOP_CTRL_ATEST_PAD_ENB_MASK 0x1 #define GC_PMU_ANTEST_TOP_CTRL_ATEST_PAD_ENB_SIZE 0x1 @@ -17810,6 +17904,11 @@ #define GC_SPS_EEPROM_CTRL_FAST_DUAL_RD_EN_SIZE 0x1 #define GC_SPS_EEPROM_CTRL_FAST_DUAL_RD_EN_DEFAULT 0x1 #define GC_SPS_EEPROM_CTRL_FAST_DUAL_RD_EN_OFFSET 0x400 +#define GC_SPS_EEPROM_CTRL_VIRTUAL_ADDR_FILTER_EN_LSB 0xb +#define GC_SPS_EEPROM_CTRL_VIRTUAL_ADDR_FILTER_EN_MASK 0x800 +#define GC_SPS_EEPROM_CTRL_VIRTUAL_ADDR_FILTER_EN_SIZE 0x1 +#define GC_SPS_EEPROM_CTRL_VIRTUAL_ADDR_FILTER_EN_DEFAULT 0x0 +#define GC_SPS_EEPROM_CTRL_VIRTUAL_ADDR_FILTER_EN_OFFSET 0x400 #define GC_SPS_BUSY_OPCODE0_EN_LSB 0x0 #define GC_SPS_BUSY_OPCODE0_EN_MASK 0x1 #define GC_SPS_BUSY_OPCODE0_EN_SIZE 0x1 @@ -17934,107 +18033,107 @@ #define GC_SPS_EEPROM_INT_ENABLE_INTR_CMD_ADDR_FIFO_NOT_EMPTY_MASK 0x1 #define GC_SPS_EEPROM_INT_ENABLE_INTR_CMD_ADDR_FIFO_NOT_EMPTY_SIZE 0x1 #define GC_SPS_EEPROM_INT_ENABLE_INTR_CMD_ADDR_FIFO_NOT_EMPTY_DEFAULT 0x0 -#define GC_SPS_EEPROM_INT_ENABLE_INTR_CMD_ADDR_FIFO_NOT_EMPTY_OFFSET 0x574 +#define GC_SPS_EEPROM_INT_ENABLE_INTR_CMD_ADDR_FIFO_NOT_EMPTY_OFFSET 0x578 #define GC_SPS_EEPROM_INT_ENABLE_INTR_CMD_ADDR_FIFO_OVFL_LSB 0x1 #define GC_SPS_EEPROM_INT_ENABLE_INTR_CMD_ADDR_FIFO_OVFL_MASK 0x2 #define GC_SPS_EEPROM_INT_ENABLE_INTR_CMD_ADDR_FIFO_OVFL_SIZE 0x1 #define GC_SPS_EEPROM_INT_ENABLE_INTR_CMD_ADDR_FIFO_OVFL_DEFAULT 0x0 -#define GC_SPS_EEPROM_INT_ENABLE_INTR_CMD_ADDR_FIFO_OVFL_OFFSET 0x574 +#define GC_SPS_EEPROM_INT_ENABLE_INTR_CMD_ADDR_FIFO_OVFL_OFFSET 0x578 #define GC_SPS_EEPROM_INT_ENABLE_INTR_CMD_MEM_OVFL_LSB 0x2 #define GC_SPS_EEPROM_INT_ENABLE_INTR_CMD_MEM_OVFL_MASK 0x4 #define GC_SPS_EEPROM_INT_ENABLE_INTR_CMD_MEM_OVFL_SIZE 0x1 #define GC_SPS_EEPROM_INT_ENABLE_INTR_CMD_MEM_OVFL_DEFAULT 0x0 -#define GC_SPS_EEPROM_INT_ENABLE_INTR_CMD_MEM_OVFL_OFFSET 0x574 +#define GC_SPS_EEPROM_INT_ENABLE_INTR_CMD_MEM_OVFL_OFFSET 0x578 #define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE0_LVL_LSB 0x3 #define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE0_LVL_MASK 0x8 #define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE0_LVL_SIZE 0x1 #define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE0_LVL_DEFAULT 0x0 -#define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE0_LVL_OFFSET 0x574 +#define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE0_LVL_OFFSET 0x578 #define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE1_LVL_LSB 0x4 #define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE1_LVL_MASK 0x10 #define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE1_LVL_SIZE 0x1 #define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE1_LVL_DEFAULT 0x0 -#define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE1_LVL_OFFSET 0x574 +#define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE1_LVL_OFFSET 0x578 #define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE2_LVL_LSB 0x5 #define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE2_LVL_MASK 0x20 #define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE2_LVL_SIZE 0x1 #define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE2_LVL_DEFAULT 0x0 -#define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE2_LVL_OFFSET 0x574 +#define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE2_LVL_OFFSET 0x578 #define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE3_LVL_LSB 0x6 #define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE3_LVL_MASK 0x40 #define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE3_LVL_SIZE 0x1 #define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE3_LVL_DEFAULT 0x0 -#define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE3_LVL_OFFSET 0x574 +#define GC_SPS_EEPROM_INT_ENABLE_INTR_RAM_PAGE3_LVL_OFFSET 0x578 #define GC_SPS_EEPROM_INT_STATE_INTR_CMD_ADDR_FIFO_NOT_EMPTY_LSB 0x0 #define GC_SPS_EEPROM_INT_STATE_INTR_CMD_ADDR_FIFO_NOT_EMPTY_MASK 0x1 #define GC_SPS_EEPROM_INT_STATE_INTR_CMD_ADDR_FIFO_NOT_EMPTY_SIZE 0x1 #define GC_SPS_EEPROM_INT_STATE_INTR_CMD_ADDR_FIFO_NOT_EMPTY_DEFAULT 0x0 -#define GC_SPS_EEPROM_INT_STATE_INTR_CMD_ADDR_FIFO_NOT_EMPTY_OFFSET 0x578 +#define GC_SPS_EEPROM_INT_STATE_INTR_CMD_ADDR_FIFO_NOT_EMPTY_OFFSET 0x57c #define GC_SPS_EEPROM_INT_STATE_INTR_CMD_ADDR_FIFO_OVFL_LSB 0x1 #define GC_SPS_EEPROM_INT_STATE_INTR_CMD_ADDR_FIFO_OVFL_MASK 0x2 #define GC_SPS_EEPROM_INT_STATE_INTR_CMD_ADDR_FIFO_OVFL_SIZE 0x1 #define GC_SPS_EEPROM_INT_STATE_INTR_CMD_ADDR_FIFO_OVFL_DEFAULT 0x0 -#define GC_SPS_EEPROM_INT_STATE_INTR_CMD_ADDR_FIFO_OVFL_OFFSET 0x578 +#define GC_SPS_EEPROM_INT_STATE_INTR_CMD_ADDR_FIFO_OVFL_OFFSET 0x57c #define GC_SPS_EEPROM_INT_STATE_INTR_CMD_MEM_OVFL_LSB 0x2 #define GC_SPS_EEPROM_INT_STATE_INTR_CMD_MEM_OVFL_MASK 0x4 #define GC_SPS_EEPROM_INT_STATE_INTR_CMD_MEM_OVFL_SIZE 0x1 #define GC_SPS_EEPROM_INT_STATE_INTR_CMD_MEM_OVFL_DEFAULT 0x0 -#define GC_SPS_EEPROM_INT_STATE_INTR_CMD_MEM_OVFL_OFFSET 0x578 +#define GC_SPS_EEPROM_INT_STATE_INTR_CMD_MEM_OVFL_OFFSET 0x57c #define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE0_LVL_LSB 0x3 #define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE0_LVL_MASK 0x8 #define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE0_LVL_SIZE 0x1 #define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE0_LVL_DEFAULT 0x0 -#define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE0_LVL_OFFSET 0x578 +#define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE0_LVL_OFFSET 0x57c #define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE1_LVL_LSB 0x4 #define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE1_LVL_MASK 0x10 #define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE1_LVL_SIZE 0x1 #define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE1_LVL_DEFAULT 0x0 -#define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE1_LVL_OFFSET 0x578 +#define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE1_LVL_OFFSET 0x57c #define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE2_LVL_LSB 0x5 #define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE2_LVL_MASK 0x20 #define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE2_LVL_SIZE 0x1 #define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE2_LVL_DEFAULT 0x0 -#define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE2_LVL_OFFSET 0x578 +#define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE2_LVL_OFFSET 0x57c #define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE3_LVL_LSB 0x6 #define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE3_LVL_MASK 0x40 #define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE3_LVL_SIZE 0x1 #define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE3_LVL_DEFAULT 0x0 -#define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE3_LVL_OFFSET 0x578 +#define GC_SPS_EEPROM_INT_STATE_INTR_RAM_PAGE3_LVL_OFFSET 0x57c #define GC_SPS_EEPROM_INT_TEST_INTR_CMD_ADDR_FIFO_NOT_EMPTY_LSB 0x0 #define GC_SPS_EEPROM_INT_TEST_INTR_CMD_ADDR_FIFO_NOT_EMPTY_MASK 0x1 #define GC_SPS_EEPROM_INT_TEST_INTR_CMD_ADDR_FIFO_NOT_EMPTY_SIZE 0x1 #define GC_SPS_EEPROM_INT_TEST_INTR_CMD_ADDR_FIFO_NOT_EMPTY_DEFAULT 0x0 -#define GC_SPS_EEPROM_INT_TEST_INTR_CMD_ADDR_FIFO_NOT_EMPTY_OFFSET 0x57c +#define GC_SPS_EEPROM_INT_TEST_INTR_CMD_ADDR_FIFO_NOT_EMPTY_OFFSET 0x580 #define GC_SPS_EEPROM_INT_TEST_INTR_CMD_ADDR_FIFO_OVFL_LSB 0x1 #define GC_SPS_EEPROM_INT_TEST_INTR_CMD_ADDR_FIFO_OVFL_MASK 0x2 #define GC_SPS_EEPROM_INT_TEST_INTR_CMD_ADDR_FIFO_OVFL_SIZE 0x1 #define GC_SPS_EEPROM_INT_TEST_INTR_CMD_ADDR_FIFO_OVFL_DEFAULT 0x0 -#define GC_SPS_EEPROM_INT_TEST_INTR_CMD_ADDR_FIFO_OVFL_OFFSET 0x57c +#define GC_SPS_EEPROM_INT_TEST_INTR_CMD_ADDR_FIFO_OVFL_OFFSET 0x580 #define GC_SPS_EEPROM_INT_TEST_INTR_CMD_MEM_OVFL_LSB 0x2 #define GC_SPS_EEPROM_INT_TEST_INTR_CMD_MEM_OVFL_MASK 0x4 #define GC_SPS_EEPROM_INT_TEST_INTR_CMD_MEM_OVFL_SIZE 0x1 #define GC_SPS_EEPROM_INT_TEST_INTR_CMD_MEM_OVFL_DEFAULT 0x0 -#define GC_SPS_EEPROM_INT_TEST_INTR_CMD_MEM_OVFL_OFFSET 0x57c +#define GC_SPS_EEPROM_INT_TEST_INTR_CMD_MEM_OVFL_OFFSET 0x580 #define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE0_LVL_LSB 0x3 #define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE0_LVL_MASK 0x8 #define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE0_LVL_SIZE 0x1 #define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE0_LVL_DEFAULT 0x0 -#define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE0_LVL_OFFSET 0x57c +#define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE0_LVL_OFFSET 0x580 #define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE1_LVL_LSB 0x4 #define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE1_LVL_MASK 0x10 #define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE1_LVL_SIZE 0x1 #define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE1_LVL_DEFAULT 0x0 -#define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE1_LVL_OFFSET 0x57c +#define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE1_LVL_OFFSET 0x580 #define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE2_LVL_LSB 0x5 #define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE2_LVL_MASK 0x20 #define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE2_LVL_SIZE 0x1 #define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE2_LVL_DEFAULT 0x0 -#define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE2_LVL_OFFSET 0x57c +#define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE2_LVL_OFFSET 0x580 #define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE3_LVL_LSB 0x6 #define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE3_LVL_MASK 0x40 #define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE3_LVL_SIZE 0x1 #define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE3_LVL_DEFAULT 0x0 -#define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE3_LVL_OFFSET 0x57c +#define GC_SPS_EEPROM_INT_TEST_INTR_RAM_PAGE3_LVL_OFFSET 0x580 #define GC_SWDP_TEST_PORT_DISABLE_SWD_LSB 0x0 #define GC_SWDP_TEST_PORT_DISABLE_SWD_MASK 0x1 #define GC_SWDP_TEST_PORT_DISABLE_SWD_SIZE 0x1 @@ -18048,12 +18147,12 @@ #define GC_TEMP_VERSION_CHANGE_LSB 0x0 #define GC_TEMP_VERSION_CHANGE_MASK 0xffffff #define GC_TEMP_VERSION_CHANGE_SIZE 0x18 -#define GC_TEMP_VERSION_CHANGE_DEFAULT 0x11f6d +#define GC_TEMP_VERSION_CHANGE_DEFAULT 0x12df1 #define GC_TEMP_VERSION_CHANGE_OFFSET 0x0 #define GC_TEMP_VERSION_REVISION_LSB 0x18 #define GC_TEMP_VERSION_REVISION_MASK 0xff000000 #define GC_TEMP_VERSION_REVISION_SIZE 0x8 -#define GC_TEMP_VERSION_REVISION_DEFAULT 0x8 +#define GC_TEMP_VERSION_REVISION_DEFAULT 0x9 #define GC_TEMP_VERSION_REVISION_OFFSET 0x0 #define GC_TEMP_ADC_INT_ENABLE_ADC_ICLKDV_LSB 0x0 #define GC_TEMP_ADC_INT_ENABLE_ADC_ICLKDV_MASK 0x1 @@ -18568,12 +18667,12 @@ #define GC_TRNG_VERSION_CHANGE_LSB 0x0 #define GC_TRNG_VERSION_CHANGE_MASK 0xffffff #define GC_TRNG_VERSION_CHANGE_SIZE 0x18 -#define GC_TRNG_VERSION_CHANGE_DEFAULT 0x12a70 +#define GC_TRNG_VERSION_CHANGE_DEFAULT 0x12f4d #define GC_TRNG_VERSION_CHANGE_OFFSET 0x0 #define GC_TRNG_VERSION_REVISION_LSB 0x18 #define GC_TRNG_VERSION_REVISION_MASK 0xff000000 #define GC_TRNG_VERSION_REVISION_SIZE 0x8 -#define GC_TRNG_VERSION_REVISION_DEFAULT 0x29 +#define GC_TRNG_VERSION_REVISION_DEFAULT 0x2c #define GC_TRNG_VERSION_REVISION_OFFSET 0x0 #define GC_TRNG_INT_ENABLE_INTR_BUFFER_FULL_LSB 0x0 #define GC_TRNG_INT_ENABLE_INTR_BUFFER_FULL_MASK 0x1 @@ -19400,6 +19499,11 @@ #define GC_USB_GINTMSK_RXFLVLMSK_SIZE 0x1 #define GC_USB_GINTMSK_RXFLVLMSK_DEFAULT 0x0 #define GC_USB_GINTMSK_RXFLVLMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_UNKNOWN5_LSB 0x5 +#define GC_USB_GINTMSK_UNKNOWN5_MASK 0x20 +#define GC_USB_GINTMSK_UNKNOWN5_SIZE 0x1 +#define GC_USB_GINTMSK_UNKNOWN5_DEFAULT 0x0 +#define GC_USB_GINTMSK_UNKNOWN5_OFFSET 0x18 #define GC_USB_GINTMSK_GINNAKEFFMSK_LSB 0x6 #define GC_USB_GINTMSK_GINNAKEFFMSK_MASK 0x40 #define GC_USB_GINTMSK_GINNAKEFFMSK_SIZE 0x1 @@ -19440,6 +19544,11 @@ #define GC_USB_GINTMSK_EOPFMSK_SIZE 0x1 #define GC_USB_GINTMSK_EOPFMSK_DEFAULT 0x0 #define GC_USB_GINTMSK_EOPFMSK_OFFSET 0x18 +#define GC_USB_GINTMSK_UNKNOWN16_LSB 0x10 +#define GC_USB_GINTMSK_UNKNOWN16_MASK 0x10000 +#define GC_USB_GINTMSK_UNKNOWN16_SIZE 0x1 +#define GC_USB_GINTMSK_UNKNOWN16_DEFAULT 0x0 +#define GC_USB_GINTMSK_UNKNOWN16_OFFSET 0x18 #define GC_USB_GINTMSK_EPMISMSK_LSB 0x11 #define GC_USB_GINTMSK_EPMISMSK_MASK 0x20000 #define GC_USB_GINTMSK_EPMISMSK_SIZE 0x1 @@ -19805,6 +19914,11 @@ #define GC_USB_DIEPTXF1_INEPNTXFSTADDR_SIZE 0xb #define GC_USB_DIEPTXF1_INEPNTXFSTADDR_DEFAULT 0x0 #define GC_USB_DIEPTXF1_INEPNTXFSTADDR_OFFSET 0x104 +#define GC_USB_DIEPTXF1_RESERVED11_LSB 0xc +#define GC_USB_DIEPTXF1_RESERVED11_MASK 0x1000 +#define GC_USB_DIEPTXF1_RESERVED11_SIZE 0x1 +#define GC_USB_DIEPTXF1_RESERVED11_DEFAULT 0x1 +#define GC_USB_DIEPTXF1_RESERVED11_OFFSET 0x104 #define GC_USB_DIEPTXF1_INEPNTXFDEP_LSB 0x10 #define GC_USB_DIEPTXF1_INEPNTXFDEP_MASK 0x3f0000 #define GC_USB_DIEPTXF1_INEPNTXFDEP_SIZE 0x6 @@ -20135,6 +20249,11 @@ #define GC_USB_DIEPMSK_INEPNAKEFFMSK_SIZE 0x1 #define GC_USB_DIEPMSK_INEPNAKEFFMSK_DEFAULT 0x0 #define GC_USB_DIEPMSK_INEPNAKEFFMSK_OFFSET 0x810 +#define GC_USB_DIEPMSK_RESERVED7_LSB 0x7 +#define GC_USB_DIEPMSK_RESERVED7_MASK 0x80 +#define GC_USB_DIEPMSK_RESERVED7_SIZE 0x1 +#define GC_USB_DIEPMSK_RESERVED7_DEFAULT 0x1 +#define GC_USB_DIEPMSK_RESERVED7_OFFSET 0x810 #define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_LSB 0x8 #define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_MASK 0x100 #define GC_USB_DIEPMSK_TXFIFOUNDRNMSK_SIZE 0x1 @@ -25808,948 +25927,948 @@ #define GC_XO_VERSION_CHANGE_LSB 0x0 #define GC_XO_VERSION_CHANGE_MASK 0xffffff #define GC_XO_VERSION_CHANGE_SIZE 0x18 -#define GC_XO_VERSION_CHANGE_DEFAULT 0x12cf2 +#define GC_XO_VERSION_CHANGE_DEFAULT 0x12f5a #define GC_XO_VERSION_CHANGE_OFFSET 0x0 #define GC_XO_VERSION_REVISION_LSB 0x18 #define GC_XO_VERSION_REVISION_MASK 0xff000000 #define GC_XO_VERSION_REVISION_SIZE 0x8 -#define GC_XO_VERSION_REVISION_DEFAULT 0x19 +#define GC_XO_VERSION_REVISION_DEFAULT 0x1b #define GC_XO_VERSION_REVISION_OFFSET 0x0 #define GC_XO_CLK_JTR_CTRL_HS_SEL_LSB 0x0 #define GC_XO_CLK_JTR_CTRL_HS_SEL_MASK 0x1 #define GC_XO_CLK_JTR_CTRL_HS_SEL_SIZE 0x1 #define GC_XO_CLK_JTR_CTRL_HS_SEL_DEFAULT 0x1 -#define GC_XO_CLK_JTR_CTRL_HS_SEL_OFFSET 0x8 +#define GC_XO_CLK_JTR_CTRL_HS_SEL_OFFSET 0xc #define GC_XO_CLK_JTR_CTRL_SEL_LSB 0x1 #define GC_XO_CLK_JTR_CTRL_SEL_MASK 0x2 #define GC_XO_CLK_JTR_CTRL_SEL_SIZE 0x1 #define GC_XO_CLK_JTR_CTRL_SEL_DEFAULT 0x1 -#define GC_XO_CLK_JTR_CTRL_SEL_OFFSET 0x8 +#define GC_XO_CLK_JTR_CTRL_SEL_OFFSET 0xc #define GC_XO_CLK_JTR_CURRENT_COARSE_TRIM_LSB 0x0 #define GC_XO_CLK_JTR_CURRENT_COARSE_TRIM_MASK 0xff #define GC_XO_CLK_JTR_CURRENT_COARSE_TRIM_SIZE 0x8 #define GC_XO_CLK_JTR_CURRENT_COARSE_TRIM_DEFAULT 0x0 -#define GC_XO_CLK_JTR_CURRENT_COARSE_TRIM_OFFSET 0x14 +#define GC_XO_CLK_JTR_CURRENT_COARSE_TRIM_OFFSET 0x18 #define GC_XO_CLK_JTR_CURRENT_FINE_TRIM_LSB 0x8 #define GC_XO_CLK_JTR_CURRENT_FINE_TRIM_MASK 0xff00 #define GC_XO_CLK_JTR_CURRENT_FINE_TRIM_SIZE 0x8 #define GC_XO_CLK_JTR_CURRENT_FINE_TRIM_DEFAULT 0x0 -#define GC_XO_CLK_JTR_CURRENT_FINE_TRIM_OFFSET 0x14 +#define GC_XO_CLK_JTR_CURRENT_FINE_TRIM_OFFSET 0x18 #define GC_XO_CLK_JTR_TRIM_CTRL_RC_TRIM_EN_LSB 0x0 #define GC_XO_CLK_JTR_TRIM_CTRL_RC_TRIM_EN_MASK 0x1 #define GC_XO_CLK_JTR_TRIM_CTRL_RC_TRIM_EN_SIZE 0x1 #define GC_XO_CLK_JTR_TRIM_CTRL_RC_TRIM_EN_DEFAULT 0x0 -#define GC_XO_CLK_JTR_TRIM_CTRL_RC_TRIM_EN_OFFSET 0x1c +#define GC_XO_CLK_JTR_TRIM_CTRL_RC_TRIM_EN_OFFSET 0x20 #define GC_XO_CLK_JTR_TRIM_CTRL_RC_INITIAL_TRIM_PERIOD_LSB 0x1 #define GC_XO_CLK_JTR_TRIM_CTRL_RC_INITIAL_TRIM_PERIOD_MASK 0x1fe #define GC_XO_CLK_JTR_TRIM_CTRL_RC_INITIAL_TRIM_PERIOD_SIZE 0x8 #define GC_XO_CLK_JTR_TRIM_CTRL_RC_INITIAL_TRIM_PERIOD_DEFAULT 0xf -#define GC_XO_CLK_JTR_TRIM_CTRL_RC_INITIAL_TRIM_PERIOD_OFFSET 0x1c +#define GC_XO_CLK_JTR_TRIM_CTRL_RC_INITIAL_TRIM_PERIOD_OFFSET 0x20 #define GC_XO_CLK_JTR_TRIM_CTRL_RC_FINE_TRIM_SRC_LSB 0x9 #define GC_XO_CLK_JTR_TRIM_CTRL_RC_FINE_TRIM_SRC_MASK 0x200 #define GC_XO_CLK_JTR_TRIM_CTRL_RC_FINE_TRIM_SRC_SIZE 0x1 #define GC_XO_CLK_JTR_TRIM_CTRL_RC_FINE_TRIM_SRC_DEFAULT 0x0 -#define GC_XO_CLK_JTR_TRIM_CTRL_RC_FINE_TRIM_SRC_OFFSET 0x1c +#define GC_XO_CLK_JTR_TRIM_CTRL_RC_FINE_TRIM_SRC_OFFSET 0x20 #define GC_XO_CLK_JTR_TRIM_CTRL_RC_COARSE_TRIM_SRC_LSB 0xa #define GC_XO_CLK_JTR_TRIM_CTRL_RC_COARSE_TRIM_SRC_MASK 0xc00 #define GC_XO_CLK_JTR_TRIM_CTRL_RC_COARSE_TRIM_SRC_SIZE 0x2 #define GC_XO_CLK_JTR_TRIM_CTRL_RC_COARSE_TRIM_SRC_DEFAULT 0x0 -#define GC_XO_CLK_JTR_TRIM_CTRL_RC_COARSE_TRIM_SRC_OFFSET 0x1c +#define GC_XO_CLK_JTR_TRIM_CTRL_RC_COARSE_TRIM_SRC_OFFSET 0x20 #define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_ENABLE_FAST_LSB 0x0 #define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_ENABLE_FAST_MASK 0x1 #define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_ENABLE_FAST_SIZE 0x1 #define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_ENABLE_FAST_DEFAULT 0x0 -#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_ENABLE_FAST_OFFSET 0x70 +#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_ENABLE_FAST_OFFSET 0x74 #define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_ENABLE_SLOW_LSB 0x1 #define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_ENABLE_SLOW_MASK 0x2 #define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_ENABLE_SLOW_SIZE 0x1 #define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_ENABLE_SLOW_DEFAULT 0x0 -#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_ENABLE_SLOW_OFFSET 0x70 +#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_ENABLE_SLOW_OFFSET 0x74 #define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_SLOW_MODE_SEL_LSB 0x2 #define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_SLOW_MODE_SEL_MASK 0x4 #define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_SLOW_MODE_SEL_SIZE 0x1 #define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_SLOW_MODE_SEL_DEFAULT 0x0 -#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_SLOW_MODE_SEL_OFFSET 0x70 +#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_SLOW_MODE_SEL_OFFSET 0x74 #define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_MAX_TRIM_SEL_LSB 0x3 #define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_MAX_TRIM_SEL_MASK 0x8 #define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_MAX_TRIM_SEL_SIZE 0x1 #define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_MAX_TRIM_SEL_DEFAULT 0x0 -#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_MAX_TRIM_SEL_OFFSET 0x70 +#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_MAX_TRIM_SEL_OFFSET 0x74 #define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_STOP_ON_NOP_LSB 0x4 #define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_STOP_ON_NOP_MASK 0x10 #define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_STOP_ON_NOP_SIZE 0x1 #define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_STOP_ON_NOP_DEFAULT 0x0 -#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_STOP_ON_NOP_OFFSET 0x70 +#define GC_XO_CLK_JTR_CALIB_TRIM_CTRL_STOP_ON_NOP_OFFSET 0x74 #define GC_XO_CLK_JTR_FAST_CALIB0_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_JTR_FAST_CALIB0_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_JTR_FAST_CALIB0_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_JTR_FAST_CALIB0_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB0_UPPER_COUNT_OFFSET 0x80 +#define GC_XO_CLK_JTR_FAST_CALIB0_UPPER_COUNT_OFFSET 0x84 #define GC_XO_CLK_JTR_FAST_CALIB1_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_JTR_FAST_CALIB1_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_JTR_FAST_CALIB1_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_JTR_FAST_CALIB1_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB1_UPPER_COUNT_OFFSET 0x84 +#define GC_XO_CLK_JTR_FAST_CALIB1_UPPER_COUNT_OFFSET 0x88 #define GC_XO_CLK_JTR_FAST_CALIB2_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_JTR_FAST_CALIB2_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_JTR_FAST_CALIB2_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_JTR_FAST_CALIB2_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB2_UPPER_COUNT_OFFSET 0x88 +#define GC_XO_CLK_JTR_FAST_CALIB2_UPPER_COUNT_OFFSET 0x8c #define GC_XO_CLK_JTR_FAST_CALIB3_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_JTR_FAST_CALIB3_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_JTR_FAST_CALIB3_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_JTR_FAST_CALIB3_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB3_UPPER_COUNT_OFFSET 0x8c +#define GC_XO_CLK_JTR_FAST_CALIB3_UPPER_COUNT_OFFSET 0x90 #define GC_XO_CLK_JTR_FAST_CALIB4_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_JTR_FAST_CALIB4_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_JTR_FAST_CALIB4_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_JTR_FAST_CALIB4_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB4_UPPER_COUNT_OFFSET 0x90 +#define GC_XO_CLK_JTR_FAST_CALIB4_UPPER_COUNT_OFFSET 0x94 #define GC_XO_CLK_JTR_FAST_CALIB5_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_JTR_FAST_CALIB5_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_JTR_FAST_CALIB5_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_JTR_FAST_CALIB5_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB5_UPPER_COUNT_OFFSET 0x94 +#define GC_XO_CLK_JTR_FAST_CALIB5_UPPER_COUNT_OFFSET 0x98 #define GC_XO_CLK_JTR_FAST_CALIB6_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_JTR_FAST_CALIB6_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_JTR_FAST_CALIB6_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_JTR_FAST_CALIB6_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB6_UPPER_COUNT_OFFSET 0x98 +#define GC_XO_CLK_JTR_FAST_CALIB6_UPPER_COUNT_OFFSET 0x9c #define GC_XO_CLK_JTR_FAST_CALIB7_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_JTR_FAST_CALIB7_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_JTR_FAST_CALIB7_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_JTR_FAST_CALIB7_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB7_UPPER_COUNT_OFFSET 0x9c +#define GC_XO_CLK_JTR_FAST_CALIB7_UPPER_COUNT_OFFSET 0xa0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OP_LSB 0x0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OP_MASK 0xf #define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OP_SIZE 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OP_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OP_OFFSET 0xa0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OP_OFFSET 0xa4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OPERAND_LSB 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OPERAND_MASK 0xf0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OPERAND_SIZE 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OPERAND_OFFSET 0xa0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL0_OPERAND_OFFSET 0xa4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OP_LSB 0x0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OP_MASK 0xf #define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OP_SIZE 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OP_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OP_OFFSET 0xa4 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OP_OFFSET 0xa8 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OPERAND_LSB 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OPERAND_MASK 0xf0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OPERAND_SIZE 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OPERAND_OFFSET 0xa4 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL1_OPERAND_OFFSET 0xa8 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OP_LSB 0x0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OP_MASK 0xf #define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OP_SIZE 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OP_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OP_OFFSET 0xa8 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OP_OFFSET 0xac #define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OPERAND_LSB 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OPERAND_MASK 0xf0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OPERAND_SIZE 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OPERAND_OFFSET 0xa8 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL2_OPERAND_OFFSET 0xac #define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OP_LSB 0x0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OP_MASK 0xf #define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OP_SIZE 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OP_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OP_OFFSET 0xac +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OP_OFFSET 0xb0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OPERAND_LSB 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OPERAND_MASK 0xf0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OPERAND_SIZE 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OPERAND_OFFSET 0xac +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL3_OPERAND_OFFSET 0xb0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OP_LSB 0x0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OP_MASK 0xf #define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OP_SIZE 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OP_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OP_OFFSET 0xb0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OP_OFFSET 0xb4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OPERAND_LSB 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OPERAND_MASK 0xf0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OPERAND_SIZE 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OPERAND_OFFSET 0xb0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL4_OPERAND_OFFSET 0xb4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OP_LSB 0x0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OP_MASK 0xf #define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OP_SIZE 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OP_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OP_OFFSET 0xb4 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OP_OFFSET 0xb8 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OPERAND_LSB 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OPERAND_MASK 0xf0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OPERAND_SIZE 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OPERAND_OFFSET 0xb4 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL5_OPERAND_OFFSET 0xb8 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OP_LSB 0x0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OP_MASK 0xf #define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OP_SIZE 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OP_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OP_OFFSET 0xb8 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OP_OFFSET 0xbc #define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OPERAND_LSB 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OPERAND_MASK 0xf0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OPERAND_SIZE 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OPERAND_OFFSET 0xb8 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL6_OPERAND_OFFSET 0xbc #define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OP_LSB 0x0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OP_MASK 0xf #define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OP_SIZE 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OP_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OP_OFFSET 0xbc +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OP_OFFSET 0xc0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OPERAND_LSB 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OPERAND_MASK 0xf0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OPERAND_SIZE 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OPERAND_OFFSET 0xbc +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL7_OPERAND_OFFSET 0xc0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OP_LSB 0x0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OP_MASK 0xf #define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OP_SIZE 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OP_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OP_OFFSET 0xc0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OP_OFFSET 0xc4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OPERAND_LSB 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OPERAND_MASK 0xf0 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OPERAND_SIZE 0x4 #define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OPERAND_OFFSET 0xc0 +#define GC_XO_CLK_JTR_FAST_CALIB_CTRL8_OPERAND_OFFSET 0xc4 #define GC_XO_CLK_JTR_SLOW_CALIB0_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_JTR_SLOW_CALIB0_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_JTR_SLOW_CALIB0_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_JTR_SLOW_CALIB0_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB0_UPPER_COUNT_OFFSET 0xc4 +#define GC_XO_CLK_JTR_SLOW_CALIB0_UPPER_COUNT_OFFSET 0xc8 #define GC_XO_CLK_JTR_SLOW_CALIB1_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_JTR_SLOW_CALIB1_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_JTR_SLOW_CALIB1_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_JTR_SLOW_CALIB1_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB1_UPPER_COUNT_OFFSET 0xc8 +#define GC_XO_CLK_JTR_SLOW_CALIB1_UPPER_COUNT_OFFSET 0xcc #define GC_XO_CLK_JTR_SLOW_CALIB2_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_JTR_SLOW_CALIB2_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_JTR_SLOW_CALIB2_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_JTR_SLOW_CALIB2_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB2_UPPER_COUNT_OFFSET 0xcc +#define GC_XO_CLK_JTR_SLOW_CALIB2_UPPER_COUNT_OFFSET 0xd0 #define GC_XO_CLK_JTR_SLOW_CALIB3_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_JTR_SLOW_CALIB3_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_JTR_SLOW_CALIB3_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_JTR_SLOW_CALIB3_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB3_UPPER_COUNT_OFFSET 0xd0 +#define GC_XO_CLK_JTR_SLOW_CALIB3_UPPER_COUNT_OFFSET 0xd4 #define GC_XO_CLK_JTR_SLOW_CALIB4_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_JTR_SLOW_CALIB4_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_JTR_SLOW_CALIB4_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_JTR_SLOW_CALIB4_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB4_UPPER_COUNT_OFFSET 0xd4 +#define GC_XO_CLK_JTR_SLOW_CALIB4_UPPER_COUNT_OFFSET 0xd8 #define GC_XO_CLK_JTR_SLOW_CALIB5_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_JTR_SLOW_CALIB5_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_JTR_SLOW_CALIB5_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_JTR_SLOW_CALIB5_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB5_UPPER_COUNT_OFFSET 0xd8 +#define GC_XO_CLK_JTR_SLOW_CALIB5_UPPER_COUNT_OFFSET 0xdc #define GC_XO_CLK_JTR_SLOW_CALIB6_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_JTR_SLOW_CALIB6_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_JTR_SLOW_CALIB6_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_JTR_SLOW_CALIB6_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB6_UPPER_COUNT_OFFSET 0xdc +#define GC_XO_CLK_JTR_SLOW_CALIB6_UPPER_COUNT_OFFSET 0xe0 #define GC_XO_CLK_JTR_SLOW_CALIB7_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_JTR_SLOW_CALIB7_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_JTR_SLOW_CALIB7_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_JTR_SLOW_CALIB7_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB7_UPPER_COUNT_OFFSET 0xe0 +#define GC_XO_CLK_JTR_SLOW_CALIB7_UPPER_COUNT_OFFSET 0xe4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OP_LSB 0x0 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OP_MASK 0xf #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OP_SIZE 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OP_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OP_OFFSET 0xe4 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OP_OFFSET 0xe8 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OPERAND_LSB 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OPERAND_MASK 0xf0 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OPERAND_SIZE 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OPERAND_OFFSET 0xe4 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL0_OPERAND_OFFSET 0xe8 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OP_LSB 0x0 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OP_MASK 0xf #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OP_SIZE 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OP_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OP_OFFSET 0xe8 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OP_OFFSET 0xec #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OPERAND_LSB 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OPERAND_MASK 0xf0 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OPERAND_SIZE 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OPERAND_OFFSET 0xe8 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL1_OPERAND_OFFSET 0xec #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OP_LSB 0x0 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OP_MASK 0xf #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OP_SIZE 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OP_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OP_OFFSET 0xec +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OP_OFFSET 0xf0 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OPERAND_LSB 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OPERAND_MASK 0xf0 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OPERAND_SIZE 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OPERAND_OFFSET 0xec +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL2_OPERAND_OFFSET 0xf0 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OP_LSB 0x0 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OP_MASK 0xf #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OP_SIZE 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OP_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OP_OFFSET 0xf0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OP_OFFSET 0xf4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OPERAND_LSB 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OPERAND_MASK 0xf0 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OPERAND_SIZE 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OPERAND_OFFSET 0xf0 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL3_OPERAND_OFFSET 0xf4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OP_LSB 0x0 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OP_MASK 0xf #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OP_SIZE 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OP_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OP_OFFSET 0xf4 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OP_OFFSET 0xf8 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OPERAND_LSB 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OPERAND_MASK 0xf0 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OPERAND_SIZE 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OPERAND_OFFSET 0xf4 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL4_OPERAND_OFFSET 0xf8 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OP_LSB 0x0 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OP_MASK 0xf #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OP_SIZE 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OP_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OP_OFFSET 0xf8 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OP_OFFSET 0xfc #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OPERAND_LSB 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OPERAND_MASK 0xf0 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OPERAND_SIZE 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OPERAND_OFFSET 0xf8 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL5_OPERAND_OFFSET 0xfc #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OP_LSB 0x0 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OP_MASK 0xf #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OP_SIZE 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OP_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OP_OFFSET 0xfc +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OP_OFFSET 0x100 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OPERAND_LSB 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OPERAND_MASK 0xf0 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OPERAND_SIZE 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OPERAND_OFFSET 0xfc +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL6_OPERAND_OFFSET 0x100 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OP_LSB 0x0 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OP_MASK 0xf #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OP_SIZE 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OP_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OP_OFFSET 0x100 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OP_OFFSET 0x104 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OPERAND_LSB 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OPERAND_MASK 0xf0 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OPERAND_SIZE 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OPERAND_OFFSET 0x100 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL7_OPERAND_OFFSET 0x104 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OP_LSB 0x0 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OP_MASK 0xf #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OP_SIZE 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OP_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OP_OFFSET 0x104 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OP_OFFSET 0x108 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OPERAND_LSB 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OPERAND_MASK 0xf0 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OPERAND_SIZE 0x4 #define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OPERAND_OFFSET 0x104 +#define GC_XO_CLK_JTR_SLOW_CALIB_CTRL8_OPERAND_OFFSET 0x108 #define GC_XO_CLK_JTR_SW_TRIM_COUNTER_VALUE_LSB 0x0 #define GC_XO_CLK_JTR_SW_TRIM_COUNTER_VALUE_MASK 0xffffff #define GC_XO_CLK_JTR_SW_TRIM_COUNTER_VALUE_SIZE 0x18 #define GC_XO_CLK_JTR_SW_TRIM_COUNTER_VALUE_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SW_TRIM_COUNTER_VALUE_OFFSET 0x10c +#define GC_XO_CLK_JTR_SW_TRIM_COUNTER_VALUE_OFFSET 0x110 #define GC_XO_CLK_JTR_SW_TRIM_COUNTER_DONE_LSB 0x18 #define GC_XO_CLK_JTR_SW_TRIM_COUNTER_DONE_MASK 0x1000000 #define GC_XO_CLK_JTR_SW_TRIM_COUNTER_DONE_SIZE 0x1 #define GC_XO_CLK_JTR_SW_TRIM_COUNTER_DONE_DEFAULT 0x0 -#define GC_XO_CLK_JTR_SW_TRIM_COUNTER_DONE_OFFSET 0x10c +#define GC_XO_CLK_JTR_SW_TRIM_COUNTER_DONE_OFFSET 0x110 #define GC_XO_CLK_TIMER_CTRL_HS_SEL_LSB 0x0 #define GC_XO_CLK_TIMER_CTRL_HS_SEL_MASK 0x1 #define GC_XO_CLK_TIMER_CTRL_HS_SEL_SIZE 0x1 #define GC_XO_CLK_TIMER_CTRL_HS_SEL_DEFAULT 0x1 -#define GC_XO_CLK_TIMER_CTRL_HS_SEL_OFFSET 0x110 +#define GC_XO_CLK_TIMER_CTRL_HS_SEL_OFFSET 0x114 #define GC_XO_CLK_TIMER_CTRL_SEL_LSB 0x1 #define GC_XO_CLK_TIMER_CTRL_SEL_MASK 0x2 #define GC_XO_CLK_TIMER_CTRL_SEL_SIZE 0x1 #define GC_XO_CLK_TIMER_CTRL_SEL_DEFAULT 0x1 -#define GC_XO_CLK_TIMER_CTRL_SEL_OFFSET 0x110 +#define GC_XO_CLK_TIMER_CTRL_SEL_OFFSET 0x114 #define GC_XO_CLK_TIMER_CURRENT_COARSE_TRIM_LSB 0x0 #define GC_XO_CLK_TIMER_CURRENT_COARSE_TRIM_MASK 0xff #define GC_XO_CLK_TIMER_CURRENT_COARSE_TRIM_SIZE 0x8 #define GC_XO_CLK_TIMER_CURRENT_COARSE_TRIM_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_CURRENT_COARSE_TRIM_OFFSET 0x11c +#define GC_XO_CLK_TIMER_CURRENT_COARSE_TRIM_OFFSET 0x120 #define GC_XO_CLK_TIMER_CURRENT_FINE_TRIM_LSB 0x8 #define GC_XO_CLK_TIMER_CURRENT_FINE_TRIM_MASK 0xff00 #define GC_XO_CLK_TIMER_CURRENT_FINE_TRIM_SIZE 0x8 #define GC_XO_CLK_TIMER_CURRENT_FINE_TRIM_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_CURRENT_FINE_TRIM_OFFSET 0x11c +#define GC_XO_CLK_TIMER_CURRENT_FINE_TRIM_OFFSET 0x120 #define GC_XO_CLK_TIMER_TRIM_CTRL_RC_TRIM_EN_LSB 0x0 #define GC_XO_CLK_TIMER_TRIM_CTRL_RC_TRIM_EN_MASK 0x1 #define GC_XO_CLK_TIMER_TRIM_CTRL_RC_TRIM_EN_SIZE 0x1 #define GC_XO_CLK_TIMER_TRIM_CTRL_RC_TRIM_EN_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_TRIM_EN_OFFSET 0x124 +#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_TRIM_EN_OFFSET 0x128 #define GC_XO_CLK_TIMER_TRIM_CTRL_RC_INITIAL_TRIM_PERIOD_LSB 0x1 #define GC_XO_CLK_TIMER_TRIM_CTRL_RC_INITIAL_TRIM_PERIOD_MASK 0x1fe #define GC_XO_CLK_TIMER_TRIM_CTRL_RC_INITIAL_TRIM_PERIOD_SIZE 0x8 #define GC_XO_CLK_TIMER_TRIM_CTRL_RC_INITIAL_TRIM_PERIOD_DEFAULT 0xf -#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_INITIAL_TRIM_PERIOD_OFFSET 0x124 +#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_INITIAL_TRIM_PERIOD_OFFSET 0x128 #define GC_XO_CLK_TIMER_TRIM_CTRL_RC_FINE_TRIM_SRC_LSB 0x9 #define GC_XO_CLK_TIMER_TRIM_CTRL_RC_FINE_TRIM_SRC_MASK 0x200 #define GC_XO_CLK_TIMER_TRIM_CTRL_RC_FINE_TRIM_SRC_SIZE 0x1 #define GC_XO_CLK_TIMER_TRIM_CTRL_RC_FINE_TRIM_SRC_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_FINE_TRIM_SRC_OFFSET 0x124 +#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_FINE_TRIM_SRC_OFFSET 0x128 #define GC_XO_CLK_TIMER_TRIM_CTRL_RC_COARSE_TRIM_SRC_LSB 0xa #define GC_XO_CLK_TIMER_TRIM_CTRL_RC_COARSE_TRIM_SRC_MASK 0xc00 #define GC_XO_CLK_TIMER_TRIM_CTRL_RC_COARSE_TRIM_SRC_SIZE 0x2 #define GC_XO_CLK_TIMER_TRIM_CTRL_RC_COARSE_TRIM_SRC_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_COARSE_TRIM_SRC_OFFSET 0x124 +#define GC_XO_CLK_TIMER_TRIM_CTRL_RC_COARSE_TRIM_SRC_OFFSET 0x128 #define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_ENABLE_FAST_LSB 0x0 #define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_ENABLE_FAST_MASK 0x1 #define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_ENABLE_FAST_SIZE 0x1 #define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_ENABLE_FAST_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_ENABLE_FAST_OFFSET 0x128 +#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_ENABLE_FAST_OFFSET 0x12c #define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_ENABLE_SLOW_LSB 0x1 #define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_ENABLE_SLOW_MASK 0x2 #define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_ENABLE_SLOW_SIZE 0x1 #define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_ENABLE_SLOW_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_ENABLE_SLOW_OFFSET 0x128 +#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_ENABLE_SLOW_OFFSET 0x12c #define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_SLOW_MODE_SEL_LSB 0x2 #define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_SLOW_MODE_SEL_MASK 0x4 #define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_SLOW_MODE_SEL_SIZE 0x1 #define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_SLOW_MODE_SEL_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_SLOW_MODE_SEL_OFFSET 0x128 +#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_SLOW_MODE_SEL_OFFSET 0x12c #define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_MAX_TRIM_SEL_LSB 0x3 #define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_MAX_TRIM_SEL_MASK 0x8 #define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_MAX_TRIM_SEL_SIZE 0x1 #define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_MAX_TRIM_SEL_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_MAX_TRIM_SEL_OFFSET 0x128 +#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_MAX_TRIM_SEL_OFFSET 0x12c #define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_STOP_ON_NOP_LSB 0x4 #define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_STOP_ON_NOP_MASK 0x10 #define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_STOP_ON_NOP_SIZE 0x1 #define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_STOP_ON_NOP_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_STOP_ON_NOP_OFFSET 0x128 +#define GC_XO_CLK_TIMER_CALIB_TRIM_CTRL_STOP_ON_NOP_OFFSET 0x12c #define GC_XO_CLK_TIMER_FAST_CALIB0_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_TIMER_FAST_CALIB0_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_TIMER_FAST_CALIB0_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_TIMER_FAST_CALIB0_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB0_UPPER_COUNT_OFFSET 0x138 +#define GC_XO_CLK_TIMER_FAST_CALIB0_UPPER_COUNT_OFFSET 0x13c #define GC_XO_CLK_TIMER_FAST_CALIB1_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_TIMER_FAST_CALIB1_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_TIMER_FAST_CALIB1_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_TIMER_FAST_CALIB1_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB1_UPPER_COUNT_OFFSET 0x13c +#define GC_XO_CLK_TIMER_FAST_CALIB1_UPPER_COUNT_OFFSET 0x140 #define GC_XO_CLK_TIMER_FAST_CALIB2_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_TIMER_FAST_CALIB2_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_TIMER_FAST_CALIB2_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_TIMER_FAST_CALIB2_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB2_UPPER_COUNT_OFFSET 0x140 +#define GC_XO_CLK_TIMER_FAST_CALIB2_UPPER_COUNT_OFFSET 0x144 #define GC_XO_CLK_TIMER_FAST_CALIB3_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_TIMER_FAST_CALIB3_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_TIMER_FAST_CALIB3_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_TIMER_FAST_CALIB3_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB3_UPPER_COUNT_OFFSET 0x144 +#define GC_XO_CLK_TIMER_FAST_CALIB3_UPPER_COUNT_OFFSET 0x148 #define GC_XO_CLK_TIMER_FAST_CALIB4_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_TIMER_FAST_CALIB4_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_TIMER_FAST_CALIB4_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_TIMER_FAST_CALIB4_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB4_UPPER_COUNT_OFFSET 0x148 +#define GC_XO_CLK_TIMER_FAST_CALIB4_UPPER_COUNT_OFFSET 0x14c #define GC_XO_CLK_TIMER_FAST_CALIB5_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_TIMER_FAST_CALIB5_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_TIMER_FAST_CALIB5_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_TIMER_FAST_CALIB5_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB5_UPPER_COUNT_OFFSET 0x14c +#define GC_XO_CLK_TIMER_FAST_CALIB5_UPPER_COUNT_OFFSET 0x150 #define GC_XO_CLK_TIMER_FAST_CALIB6_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_TIMER_FAST_CALIB6_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_TIMER_FAST_CALIB6_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_TIMER_FAST_CALIB6_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB6_UPPER_COUNT_OFFSET 0x150 +#define GC_XO_CLK_TIMER_FAST_CALIB6_UPPER_COUNT_OFFSET 0x154 #define GC_XO_CLK_TIMER_FAST_CALIB7_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_TIMER_FAST_CALIB7_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_TIMER_FAST_CALIB7_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_TIMER_FAST_CALIB7_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB7_UPPER_COUNT_OFFSET 0x154 +#define GC_XO_CLK_TIMER_FAST_CALIB7_UPPER_COUNT_OFFSET 0x158 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OP_LSB 0x0 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OP_MASK 0xf #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OP_SIZE 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OP_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OP_OFFSET 0x158 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OP_OFFSET 0x15c #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OPERAND_LSB 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OPERAND_MASK 0xf0 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OPERAND_SIZE 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OPERAND_OFFSET 0x158 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL0_OPERAND_OFFSET 0x15c #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OP_LSB 0x0 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OP_MASK 0xf #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OP_SIZE 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OP_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OP_OFFSET 0x15c +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OP_OFFSET 0x160 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OPERAND_LSB 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OPERAND_MASK 0xf0 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OPERAND_SIZE 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OPERAND_OFFSET 0x15c +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL1_OPERAND_OFFSET 0x160 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OP_LSB 0x0 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OP_MASK 0xf #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OP_SIZE 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OP_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OP_OFFSET 0x160 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OP_OFFSET 0x164 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OPERAND_LSB 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OPERAND_MASK 0xf0 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OPERAND_SIZE 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OPERAND_OFFSET 0x160 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL2_OPERAND_OFFSET 0x164 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OP_LSB 0x0 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OP_MASK 0xf #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OP_SIZE 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OP_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OP_OFFSET 0x164 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OP_OFFSET 0x168 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OPERAND_LSB 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OPERAND_MASK 0xf0 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OPERAND_SIZE 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OPERAND_OFFSET 0x164 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL3_OPERAND_OFFSET 0x168 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OP_LSB 0x0 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OP_MASK 0xf #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OP_SIZE 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OP_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OP_OFFSET 0x168 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OP_OFFSET 0x16c #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OPERAND_LSB 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OPERAND_MASK 0xf0 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OPERAND_SIZE 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OPERAND_OFFSET 0x168 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL4_OPERAND_OFFSET 0x16c #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OP_LSB 0x0 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OP_MASK 0xf #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OP_SIZE 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OP_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OP_OFFSET 0x16c +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OP_OFFSET 0x170 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OPERAND_LSB 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OPERAND_MASK 0xf0 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OPERAND_SIZE 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OPERAND_OFFSET 0x16c +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL5_OPERAND_OFFSET 0x170 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OP_LSB 0x0 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OP_MASK 0xf #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OP_SIZE 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OP_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OP_OFFSET 0x170 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OP_OFFSET 0x174 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OPERAND_LSB 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OPERAND_MASK 0xf0 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OPERAND_SIZE 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OPERAND_OFFSET 0x170 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL6_OPERAND_OFFSET 0x174 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OP_LSB 0x0 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OP_MASK 0xf #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OP_SIZE 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OP_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OP_OFFSET 0x174 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OP_OFFSET 0x178 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OPERAND_LSB 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OPERAND_MASK 0xf0 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OPERAND_SIZE 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OPERAND_OFFSET 0x174 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL7_OPERAND_OFFSET 0x178 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OP_LSB 0x0 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OP_MASK 0xf #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OP_SIZE 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OP_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OP_OFFSET 0x178 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OP_OFFSET 0x17c #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OPERAND_LSB 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OPERAND_MASK 0xf0 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OPERAND_SIZE 0x4 #define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OPERAND_OFFSET 0x178 +#define GC_XO_CLK_TIMER_FAST_CALIB_CTRL8_OPERAND_OFFSET 0x17c #define GC_XO_CLK_TIMER_SLOW_CALIB0_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_TIMER_SLOW_CALIB0_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_TIMER_SLOW_CALIB0_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_TIMER_SLOW_CALIB0_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB0_UPPER_COUNT_OFFSET 0x17c +#define GC_XO_CLK_TIMER_SLOW_CALIB0_UPPER_COUNT_OFFSET 0x180 #define GC_XO_CLK_TIMER_SLOW_CALIB1_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_TIMER_SLOW_CALIB1_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_TIMER_SLOW_CALIB1_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_TIMER_SLOW_CALIB1_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB1_UPPER_COUNT_OFFSET 0x180 +#define GC_XO_CLK_TIMER_SLOW_CALIB1_UPPER_COUNT_OFFSET 0x184 #define GC_XO_CLK_TIMER_SLOW_CALIB2_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_TIMER_SLOW_CALIB2_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_TIMER_SLOW_CALIB2_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_TIMER_SLOW_CALIB2_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB2_UPPER_COUNT_OFFSET 0x184 +#define GC_XO_CLK_TIMER_SLOW_CALIB2_UPPER_COUNT_OFFSET 0x188 #define GC_XO_CLK_TIMER_SLOW_CALIB3_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_TIMER_SLOW_CALIB3_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_TIMER_SLOW_CALIB3_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_TIMER_SLOW_CALIB3_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB3_UPPER_COUNT_OFFSET 0x188 +#define GC_XO_CLK_TIMER_SLOW_CALIB3_UPPER_COUNT_OFFSET 0x18c #define GC_XO_CLK_TIMER_SLOW_CALIB4_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_TIMER_SLOW_CALIB4_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_TIMER_SLOW_CALIB4_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_TIMER_SLOW_CALIB4_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB4_UPPER_COUNT_OFFSET 0x18c +#define GC_XO_CLK_TIMER_SLOW_CALIB4_UPPER_COUNT_OFFSET 0x190 #define GC_XO_CLK_TIMER_SLOW_CALIB5_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_TIMER_SLOW_CALIB5_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_TIMER_SLOW_CALIB5_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_TIMER_SLOW_CALIB5_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB5_UPPER_COUNT_OFFSET 0x190 +#define GC_XO_CLK_TIMER_SLOW_CALIB5_UPPER_COUNT_OFFSET 0x194 #define GC_XO_CLK_TIMER_SLOW_CALIB6_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_TIMER_SLOW_CALIB6_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_TIMER_SLOW_CALIB6_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_TIMER_SLOW_CALIB6_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB6_UPPER_COUNT_OFFSET 0x194 +#define GC_XO_CLK_TIMER_SLOW_CALIB6_UPPER_COUNT_OFFSET 0x198 #define GC_XO_CLK_TIMER_SLOW_CALIB7_UPPER_COUNT_LSB 0x0 #define GC_XO_CLK_TIMER_SLOW_CALIB7_UPPER_COUNT_MASK 0xffff #define GC_XO_CLK_TIMER_SLOW_CALIB7_UPPER_COUNT_SIZE 0x10 #define GC_XO_CLK_TIMER_SLOW_CALIB7_UPPER_COUNT_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB7_UPPER_COUNT_OFFSET 0x198 +#define GC_XO_CLK_TIMER_SLOW_CALIB7_UPPER_COUNT_OFFSET 0x19c #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OP_LSB 0x0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OP_MASK 0xf #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OP_SIZE 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OP_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OP_OFFSET 0x19c +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OP_OFFSET 0x1a0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OPERAND_LSB 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OPERAND_MASK 0xf0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OPERAND_SIZE 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OPERAND_OFFSET 0x19c +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL0_OPERAND_OFFSET 0x1a0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OP_LSB 0x0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OP_MASK 0xf #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OP_SIZE 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OP_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OP_OFFSET 0x1a0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OP_OFFSET 0x1a4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OPERAND_LSB 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OPERAND_MASK 0xf0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OPERAND_SIZE 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OPERAND_OFFSET 0x1a0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL1_OPERAND_OFFSET 0x1a4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OP_LSB 0x0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OP_MASK 0xf #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OP_SIZE 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OP_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OP_OFFSET 0x1a4 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OP_OFFSET 0x1a8 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OPERAND_LSB 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OPERAND_MASK 0xf0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OPERAND_SIZE 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OPERAND_OFFSET 0x1a4 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL2_OPERAND_OFFSET 0x1a8 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OP_LSB 0x0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OP_MASK 0xf #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OP_SIZE 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OP_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OP_OFFSET 0x1a8 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OP_OFFSET 0x1ac #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OPERAND_LSB 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OPERAND_MASK 0xf0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OPERAND_SIZE 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OPERAND_OFFSET 0x1a8 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL3_OPERAND_OFFSET 0x1ac #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OP_LSB 0x0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OP_MASK 0xf #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OP_SIZE 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OP_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OP_OFFSET 0x1ac +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OP_OFFSET 0x1b0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OPERAND_LSB 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OPERAND_MASK 0xf0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OPERAND_SIZE 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OPERAND_OFFSET 0x1ac +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL4_OPERAND_OFFSET 0x1b0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OP_LSB 0x0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OP_MASK 0xf #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OP_SIZE 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OP_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OP_OFFSET 0x1b0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OP_OFFSET 0x1b4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OPERAND_LSB 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OPERAND_MASK 0xf0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OPERAND_SIZE 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OPERAND_OFFSET 0x1b0 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL5_OPERAND_OFFSET 0x1b4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OP_LSB 0x0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OP_MASK 0xf #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OP_SIZE 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OP_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OP_OFFSET 0x1b4 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OP_OFFSET 0x1b8 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OPERAND_LSB 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OPERAND_MASK 0xf0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OPERAND_SIZE 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OPERAND_OFFSET 0x1b4 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL6_OPERAND_OFFSET 0x1b8 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OP_LSB 0x0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OP_MASK 0xf #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OP_SIZE 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OP_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OP_OFFSET 0x1b8 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OP_OFFSET 0x1bc #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OPERAND_LSB 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OPERAND_MASK 0xf0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OPERAND_SIZE 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OPERAND_OFFSET 0x1b8 +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL7_OPERAND_OFFSET 0x1bc #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OP_LSB 0x0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OP_MASK 0xf #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OP_SIZE 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OP_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OP_OFFSET 0x1bc +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OP_OFFSET 0x1c0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OPERAND_LSB 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OPERAND_MASK 0xf0 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OPERAND_SIZE 0x4 #define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OPERAND_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OPERAND_OFFSET 0x1bc +#define GC_XO_CLK_TIMER_SLOW_CALIB_CTRL8_OPERAND_OFFSET 0x1c0 #define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_VALUE_LSB 0x0 #define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_VALUE_MASK 0xffffff #define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_VALUE_SIZE 0x18 #define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_VALUE_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_VALUE_OFFSET 0x1c4 +#define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_VALUE_OFFSET 0x1c8 #define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_DONE_LSB 0x18 #define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_DONE_MASK 0x1000000 #define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_DONE_SIZE 0x1 #define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_DONE_DEFAULT 0x0 -#define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_DONE_OFFSET 0x1c4 +#define GC_XO_CLK_TIMER_SW_TRIM_COUNTER_DONE_OFFSET 0x1c8 #define GC_XO_OSC_XTL_FREQ2X_CAL_CNTL_LSB 0x0 #define GC_XO_OSC_XTL_FREQ2X_CAL_CNTL_MASK 0xf #define GC_XO_OSC_XTL_FREQ2X_CAL_CNTL_SIZE 0x4 #define GC_XO_OSC_XTL_FREQ2X_CAL_CNTL_DEFAULT 0x7 -#define GC_XO_OSC_XTL_FREQ2X_CAL_CNTL_OFFSET 0x1c8 +#define GC_XO_OSC_XTL_FREQ2X_CAL_CNTL_OFFSET 0x1cc #define GC_XO_OSC_XTL_FREQ2X_CAL_EN_LSB 0x4 #define GC_XO_OSC_XTL_FREQ2X_CAL_EN_MASK 0x10 #define GC_XO_OSC_XTL_FREQ2X_CAL_EN_SIZE 0x1 #define GC_XO_OSC_XTL_FREQ2X_CAL_EN_DEFAULT 0x0 -#define GC_XO_OSC_XTL_FREQ2X_CAL_EN_OFFSET 0x1c8 +#define GC_XO_OSC_XTL_FREQ2X_CAL_EN_OFFSET 0x1cc #define GC_XO_OSC_XTL_FREQ2X_SELB_LSB 0x5 #define GC_XO_OSC_XTL_FREQ2X_SELB_MASK 0x20 #define GC_XO_OSC_XTL_FREQ2X_SELB_SIZE 0x1 #define GC_XO_OSC_XTL_FREQ2X_SELB_DEFAULT 0x0 -#define GC_XO_OSC_XTL_FREQ2X_SELB_OFFSET 0x1c8 +#define GC_XO_OSC_XTL_FREQ2X_SELB_OFFSET 0x1cc #define GC_XO_OSC_XTL_FREQ2X_STAT_CAL_CNTL_LSB 0x0 #define GC_XO_OSC_XTL_FREQ2X_STAT_CAL_CNTL_MASK 0xf #define GC_XO_OSC_XTL_FREQ2X_STAT_CAL_CNTL_SIZE 0x4 #define GC_XO_OSC_XTL_FREQ2X_STAT_CAL_CNTL_DEFAULT 0x6 -#define GC_XO_OSC_XTL_FREQ2X_STAT_CAL_CNTL_OFFSET 0x1cc +#define GC_XO_OSC_XTL_FREQ2X_STAT_CAL_CNTL_OFFSET 0x1d0 #define GC_XO_OSC_XTL_FREQ2X_STAT_CAL_EN_LSB 0x4 #define GC_XO_OSC_XTL_FREQ2X_STAT_CAL_EN_MASK 0x10 #define GC_XO_OSC_XTL_FREQ2X_STAT_CAL_EN_SIZE 0x1 #define GC_XO_OSC_XTL_FREQ2X_STAT_CAL_EN_DEFAULT 0x0 -#define GC_XO_OSC_XTL_FREQ2X_STAT_CAL_EN_OFFSET 0x1cc +#define GC_XO_OSC_XTL_FREQ2X_STAT_CAL_EN_OFFSET 0x1d0 #define GC_XO_OSC_XTL_FREQ2X_STAT_SELB_LSB 0x5 #define GC_XO_OSC_XTL_FREQ2X_STAT_SELB_MASK 0x20 #define GC_XO_OSC_XTL_FREQ2X_STAT_SELB_SIZE 0x1 #define GC_XO_OSC_XTL_FREQ2X_STAT_SELB_DEFAULT 0x0 -#define GC_XO_OSC_XTL_FREQ2X_STAT_SELB_OFFSET 0x1cc +#define GC_XO_OSC_XTL_FREQ2X_STAT_SELB_OFFSET 0x1d0 #define GC_XO_OSC_XTL_RC_FLTR_TRIM_LSB 0x0 #define GC_XO_OSC_XTL_RC_FLTR_TRIM_MASK 0xf #define GC_XO_OSC_XTL_RC_FLTR_TRIM_SIZE 0x4 #define GC_XO_OSC_XTL_RC_FLTR_TRIM_DEFAULT 0x5 -#define GC_XO_OSC_XTL_RC_FLTR_TRIM_OFFSET 0x1dc +#define GC_XO_OSC_XTL_RC_FLTR_TRIM_OFFSET 0x1e0 #define GC_XO_OSC_XTL_RC_FLTR_BYPASS_LSB 0x4 #define GC_XO_OSC_XTL_RC_FLTR_BYPASS_MASK 0x10 #define GC_XO_OSC_XTL_RC_FLTR_BYPASS_SIZE 0x1 #define GC_XO_OSC_XTL_RC_FLTR_BYPASS_DEFAULT 0x1 -#define GC_XO_OSC_XTL_RC_FLTR_BYPASS_OFFSET 0x1dc +#define GC_XO_OSC_XTL_RC_FLTR_BYPASS_OFFSET 0x1e0 #define GC_XO_OSC_XTL_OVRD_TRIM_LSB 0x0 #define GC_XO_OSC_XTL_OVRD_TRIM_MASK 0xf #define GC_XO_OSC_XTL_OVRD_TRIM_SIZE 0x4 #define GC_XO_OSC_XTL_OVRD_TRIM_DEFAULT 0x7 -#define GC_XO_OSC_XTL_OVRD_TRIM_OFFSET 0x1e0 +#define GC_XO_OSC_XTL_OVRD_TRIM_OFFSET 0x1e4 #define GC_XO_OSC_XTL_OVRD_ENB_LSB 0x4 #define GC_XO_OSC_XTL_OVRD_ENB_MASK 0x10 #define GC_XO_OSC_XTL_OVRD_ENB_SIZE 0x1 #define GC_XO_OSC_XTL_OVRD_ENB_DEFAULT 0x1 -#define GC_XO_OSC_XTL_OVRD_ENB_OFFSET 0x1e0 +#define GC_XO_OSC_XTL_OVRD_ENB_OFFSET 0x1e4 #define GC_XO_OSC_XTL_TRIM_CODE_LSB 0x0 #define GC_XO_OSC_XTL_TRIM_CODE_MASK 0xf #define GC_XO_OSC_XTL_TRIM_CODE_SIZE 0x4 #define GC_XO_OSC_XTL_TRIM_CODE_DEFAULT 0x0 -#define GC_XO_OSC_XTL_TRIM_CODE_OFFSET 0x1e8 +#define GC_XO_OSC_XTL_TRIM_CODE_OFFSET 0x1ec #define GC_XO_OSC_XTL_TRIM_EN_LSB 0x4 #define GC_XO_OSC_XTL_TRIM_EN_MASK 0x10 #define GC_XO_OSC_XTL_TRIM_EN_SIZE 0x1 #define GC_XO_OSC_XTL_TRIM_EN_DEFAULT 0x0 -#define GC_XO_OSC_XTL_TRIM_EN_OFFSET 0x1e8 +#define GC_XO_OSC_XTL_TRIM_EN_OFFSET 0x1ec #define GC_XO_OSC_XTL_TRIM_STAT_CODE_LSB 0x0 #define GC_XO_OSC_XTL_TRIM_STAT_CODE_MASK 0xf #define GC_XO_OSC_XTL_TRIM_STAT_CODE_SIZE 0x4 #define GC_XO_OSC_XTL_TRIM_STAT_CODE_DEFAULT 0x0 -#define GC_XO_OSC_XTL_TRIM_STAT_CODE_OFFSET 0x1ec +#define GC_XO_OSC_XTL_TRIM_STAT_CODE_OFFSET 0x1f0 #define GC_XO_OSC_XTL_TRIM_STAT_EN_LSB 0x4 #define GC_XO_OSC_XTL_TRIM_STAT_EN_MASK 0x10 #define GC_XO_OSC_XTL_TRIM_STAT_EN_SIZE 0x1 #define GC_XO_OSC_XTL_TRIM_STAT_EN_DEFAULT 0x0 -#define GC_XO_OSC_XTL_TRIM_STAT_EN_OFFSET 0x1ec +#define GC_XO_OSC_XTL_TRIM_STAT_EN_OFFSET 0x1f0 #define GC_XO_OSC_XTL_FSM_DONE_LSB 0x0 #define GC_XO_OSC_XTL_FSM_DONE_MASK 0x1 #define GC_XO_OSC_XTL_FSM_DONE_SIZE 0x1 #define GC_XO_OSC_XTL_FSM_DONE_DEFAULT 0x0 -#define GC_XO_OSC_XTL_FSM_DONE_OFFSET 0x1f8 +#define GC_XO_OSC_XTL_FSM_DONE_OFFSET 0x1fc #define GC_XO_OSC_XTL_FSM_TRIM_LSB 0x1 #define GC_XO_OSC_XTL_FSM_TRIM_MASK 0x1e #define GC_XO_OSC_XTL_FSM_TRIM_SIZE 0x4 #define GC_XO_OSC_XTL_FSM_TRIM_DEFAULT 0x0 -#define GC_XO_OSC_XTL_FSM_TRIM_OFFSET 0x1f8 +#define GC_XO_OSC_XTL_FSM_TRIM_OFFSET 0x1fc #define GC_XO_OSC_XTL_FSM_STATUS_LSB 0x5 #define GC_XO_OSC_XTL_FSM_STATUS_MASK 0x20 #define GC_XO_OSC_XTL_FSM_STATUS_SIZE 0x1 #define GC_XO_OSC_XTL_FSM_STATUS_DEFAULT 0x0 -#define GC_XO_OSC_XTL_FSM_STATUS_OFFSET 0x1f8 +#define GC_XO_OSC_XTL_FSM_STATUS_OFFSET 0x1fc #define GC_XO_OSC_XTL_FSM_STATE_LSB 0x6 #define GC_XO_OSC_XTL_FSM_STATE_MASK 0x3c0 #define GC_XO_OSC_XTL_FSM_STATE_SIZE 0x4 #define GC_XO_OSC_XTL_FSM_STATE_DEFAULT 0x0 -#define GC_XO_OSC_XTL_FSM_STATE_OFFSET 0x1f8 +#define GC_XO_OSC_XTL_FSM_STATE_OFFSET 0x1fc #define GC_XO_OSC_XTL_FSM_LVL_DET_SYNC_LSB 0xa #define GC_XO_OSC_XTL_FSM_LVL_DET_SYNC_MASK 0x400 #define GC_XO_OSC_XTL_FSM_LVL_DET_SYNC_SIZE 0x1 #define GC_XO_OSC_XTL_FSM_LVL_DET_SYNC_DEFAULT 0x0 -#define GC_XO_OSC_XTL_FSM_LVL_DET_SYNC_OFFSET 0x1f8 +#define GC_XO_OSC_XTL_FSM_LVL_DET_SYNC_OFFSET 0x1fc #define GC_XO_OSC_XTL_FSM_CFG_TRIM_MAX_LSB 0x0 #define GC_XO_OSC_XTL_FSM_CFG_TRIM_MAX_MASK 0xf #define GC_XO_OSC_XTL_FSM_CFG_TRIM_MAX_SIZE 0x4 #define GC_XO_OSC_XTL_FSM_CFG_TRIM_MAX_DEFAULT 0x8 -#define GC_XO_OSC_XTL_FSM_CFG_TRIM_MAX_OFFSET 0x1fc +#define GC_XO_OSC_XTL_FSM_CFG_TRIM_MAX_OFFSET 0x200 #define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SNIFF_LSB 0x4 #define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SNIFF_MASK 0x30 #define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SNIFF_SIZE 0x2 #define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SNIFF_DEFAULT 0x0 -#define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SNIFF_OFFSET 0x1fc +#define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SNIFF_OFFSET 0x200 #define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SENSE_LSB 0x6 #define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SENSE_MASK 0xc0 #define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SENSE_SIZE 0x2 #define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SENSE_DEFAULT 0x2 -#define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SENSE_OFFSET 0x1fc +#define GC_XO_OSC_XTL_FSM_CFG_LVL_DET_SENSE_OFFSET 0x200 #define GC_XO_OSC_XTL_FSM_CFG_PWRUP_REG_MAX_LSB 0x8 #define GC_XO_OSC_XTL_FSM_CFG_PWRUP_REG_MAX_MASK 0x700 #define GC_XO_OSC_XTL_FSM_CFG_PWRUP_REG_MAX_SIZE 0x3 #define GC_XO_OSC_XTL_FSM_CFG_PWRUP_REG_MAX_DEFAULT 0x4 -#define GC_XO_OSC_XTL_FSM_CFG_PWRUP_REG_MAX_OFFSET 0x1fc +#define GC_XO_OSC_XTL_FSM_CFG_PWRUP_REG_MAX_OFFSET 0x200 #define GC_XO_OSC_XTL_FSM_CFG_SNIFF_REG_MAX_LSB 0xb #define GC_XO_OSC_XTL_FSM_CFG_SNIFF_REG_MAX_MASK 0xf800 #define GC_XO_OSC_XTL_FSM_CFG_SNIFF_REG_MAX_SIZE 0x5 #define GC_XO_OSC_XTL_FSM_CFG_SNIFF_REG_MAX_DEFAULT 0xe -#define GC_XO_OSC_XTL_FSM_CFG_SNIFF_REG_MAX_OFFSET 0x1fc +#define GC_XO_OSC_XTL_FSM_CFG_SNIFF_REG_MAX_OFFSET 0x200 #define GC_XO_OSC_XTL_FSM_CFG_SENSE_REG_MAX_LSB 0x10 #define GC_XO_OSC_XTL_FSM_CFG_SENSE_REG_MAX_MASK 0x1f0000 #define GC_XO_OSC_XTL_FSM_CFG_SENSE_REG_MAX_SIZE 0x5 #define GC_XO_OSC_XTL_FSM_CFG_SENSE_REG_MAX_DEFAULT 0xd -#define GC_XO_OSC_XTL_FSM_CFG_SENSE_REG_MAX_OFFSET 0x1fc +#define GC_XO_OSC_XTL_FSM_CFG_SENSE_REG_MAX_OFFSET 0x200 #define GC_XO_OSC_TEST_CLK2X_EN_LSB 0x0 #define GC_XO_OSC_TEST_CLK2X_EN_MASK 0x1 #define GC_XO_OSC_TEST_CLK2X_EN_SIZE 0x1 #define GC_XO_OSC_TEST_CLK2X_EN_DEFAULT 0x0 -#define GC_XO_OSC_TEST_CLK2X_EN_OFFSET 0x200 +#define GC_XO_OSC_TEST_CLK2X_EN_OFFSET 0x204 #define GC_XO_OSC_TEST_CLK_JTR_EN_LSB 0x1 #define GC_XO_OSC_TEST_CLK_JTR_EN_MASK 0x2 #define GC_XO_OSC_TEST_CLK_JTR_EN_SIZE 0x1 #define GC_XO_OSC_TEST_CLK_JTR_EN_DEFAULT 0x0 -#define GC_XO_OSC_TEST_CLK_JTR_EN_OFFSET 0x200 +#define GC_XO_OSC_TEST_CLK_JTR_EN_OFFSET 0x204 #define GC_XO_OSC_TEST_CLK_TIMER_EN_LSB 0x2 #define GC_XO_OSC_TEST_CLK_TIMER_EN_MASK 0x4 #define GC_XO_OSC_TEST_CLK_TIMER_EN_SIZE 0x1 #define GC_XO_OSC_TEST_CLK_TIMER_EN_DEFAULT 0x0 -#define GC_XO_OSC_TEST_CLK_TIMER_EN_OFFSET 0x200 +#define GC_XO_OSC_TEST_CLK_TIMER_EN_OFFSET 0x204 #define GC_XO_ANTEST_CTRL_LDO_EN_LSB 0x0 #define GC_XO_ANTEST_CTRL_LDO_EN_MASK 0x1 #define GC_XO_ANTEST_CTRL_LDO_EN_SIZE 0x1 #define GC_XO_ANTEST_CTRL_LDO_EN_DEFAULT 0x0 -#define GC_XO_ANTEST_CTRL_LDO_EN_OFFSET 0x210 +#define GC_XO_ANTEST_CTRL_LDO_EN_OFFSET 0x214 #define GC_XO_DXO_INT_ENABLE_FAST_CALIB_OVERFLOW_LSB 0x0 #define GC_XO_DXO_INT_ENABLE_FAST_CALIB_OVERFLOW_MASK 0x1 #define GC_XO_DXO_INT_ENABLE_FAST_CALIB_OVERFLOW_SIZE 0x1 #define GC_XO_DXO_INT_ENABLE_FAST_CALIB_OVERFLOW_DEFAULT 0x0 -#define GC_XO_DXO_INT_ENABLE_FAST_CALIB_OVERFLOW_OFFSET 0x214 +#define GC_XO_DXO_INT_ENABLE_FAST_CALIB_OVERFLOW_OFFSET 0x218 #define GC_XO_DXO_INT_ENABLE_FAST_CALIB_UNDERRUN_LSB 0x1 #define GC_XO_DXO_INT_ENABLE_FAST_CALIB_UNDERRUN_MASK 0x2 #define GC_XO_DXO_INT_ENABLE_FAST_CALIB_UNDERRUN_SIZE 0x1 #define GC_XO_DXO_INT_ENABLE_FAST_CALIB_UNDERRUN_DEFAULT 0x0 -#define GC_XO_DXO_INT_ENABLE_FAST_CALIB_UNDERRUN_OFFSET 0x214 +#define GC_XO_DXO_INT_ENABLE_FAST_CALIB_UNDERRUN_OFFSET 0x218 #define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_OVERFLOW_LSB 0x2 #define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_OVERFLOW_MASK 0x4 #define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_OVERFLOW_SIZE 0x1 #define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_OVERFLOW_DEFAULT 0x0 -#define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_OVERFLOW_OFFSET 0x214 +#define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_OVERFLOW_OFFSET 0x218 #define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_UNDERRUN_LSB 0x3 #define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_UNDERRUN_MASK 0x8 #define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_UNDERRUN_SIZE 0x1 #define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_UNDERRUN_DEFAULT 0x0 -#define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_UNDERRUN_OFFSET 0x214 +#define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_UNDERRUN_OFFSET 0x218 #define GC_XO_DXO_INT_ENABLE_CLK_JTR_NOP_SEEN_LSB 0x4 #define GC_XO_DXO_INT_ENABLE_CLK_JTR_NOP_SEEN_MASK 0x10 #define GC_XO_DXO_INT_ENABLE_CLK_JTR_NOP_SEEN_SIZE 0x1 #define GC_XO_DXO_INT_ENABLE_CLK_JTR_NOP_SEEN_DEFAULT 0x0 -#define GC_XO_DXO_INT_ENABLE_CLK_JTR_NOP_SEEN_OFFSET 0x214 +#define GC_XO_DXO_INT_ENABLE_CLK_JTR_NOP_SEEN_OFFSET 0x218 #define GC_XO_DXO_INT_ENABLE_CLK_TIMER_NOP_SEEN_LSB 0x5 #define GC_XO_DXO_INT_ENABLE_CLK_TIMER_NOP_SEEN_MASK 0x20 #define GC_XO_DXO_INT_ENABLE_CLK_TIMER_NOP_SEEN_SIZE 0x1 #define GC_XO_DXO_INT_ENABLE_CLK_TIMER_NOP_SEEN_DEFAULT 0x0 -#define GC_XO_DXO_INT_ENABLE_CLK_TIMER_NOP_SEEN_OFFSET 0x214 +#define GC_XO_DXO_INT_ENABLE_CLK_TIMER_NOP_SEEN_OFFSET 0x218 #define GC_XO_DXO_INT_ENABLE_CLK_JTR_SW_TRIM_DONE_LSB 0x6 #define GC_XO_DXO_INT_ENABLE_CLK_JTR_SW_TRIM_DONE_MASK 0x40 #define GC_XO_DXO_INT_ENABLE_CLK_JTR_SW_TRIM_DONE_SIZE 0x1 #define GC_XO_DXO_INT_ENABLE_CLK_JTR_SW_TRIM_DONE_DEFAULT 0x0 -#define GC_XO_DXO_INT_ENABLE_CLK_JTR_SW_TRIM_DONE_OFFSET 0x214 +#define GC_XO_DXO_INT_ENABLE_CLK_JTR_SW_TRIM_DONE_OFFSET 0x218 #define GC_XO_DXO_INT_ENABLE_CLK_TIMER_SW_TRIM_DONE_LSB 0x7 #define GC_XO_DXO_INT_ENABLE_CLK_TIMER_SW_TRIM_DONE_MASK 0x80 #define GC_XO_DXO_INT_ENABLE_CLK_TIMER_SW_TRIM_DONE_SIZE 0x1 #define GC_XO_DXO_INT_ENABLE_CLK_TIMER_SW_TRIM_DONE_DEFAULT 0x0 -#define GC_XO_DXO_INT_ENABLE_CLK_TIMER_SW_TRIM_DONE_OFFSET 0x214 +#define GC_XO_DXO_INT_ENABLE_CLK_TIMER_SW_TRIM_DONE_OFFSET 0x218 #define GC_XO_DXO_INT_STATE_FAST_CALIB_OVERFLOW_LSB 0x0 #define GC_XO_DXO_INT_STATE_FAST_CALIB_OVERFLOW_MASK 0x1 #define GC_XO_DXO_INT_STATE_FAST_CALIB_OVERFLOW_SIZE 0x1 #define GC_XO_DXO_INT_STATE_FAST_CALIB_OVERFLOW_DEFAULT 0x0 -#define GC_XO_DXO_INT_STATE_FAST_CALIB_OVERFLOW_OFFSET 0x218 +#define GC_XO_DXO_INT_STATE_FAST_CALIB_OVERFLOW_OFFSET 0x21c #define GC_XO_DXO_INT_STATE_FAST_CALIB_UNDERRUN_LSB 0x1 #define GC_XO_DXO_INT_STATE_FAST_CALIB_UNDERRUN_MASK 0x2 #define GC_XO_DXO_INT_STATE_FAST_CALIB_UNDERRUN_SIZE 0x1 #define GC_XO_DXO_INT_STATE_FAST_CALIB_UNDERRUN_DEFAULT 0x0 -#define GC_XO_DXO_INT_STATE_FAST_CALIB_UNDERRUN_OFFSET 0x218 +#define GC_XO_DXO_INT_STATE_FAST_CALIB_UNDERRUN_OFFSET 0x21c #define GC_XO_DXO_INT_STATE_SLOW_CALIB_OVERFLOW_LSB 0x2 #define GC_XO_DXO_INT_STATE_SLOW_CALIB_OVERFLOW_MASK 0x4 #define GC_XO_DXO_INT_STATE_SLOW_CALIB_OVERFLOW_SIZE 0x1 #define GC_XO_DXO_INT_STATE_SLOW_CALIB_OVERFLOW_DEFAULT 0x0 -#define GC_XO_DXO_INT_STATE_SLOW_CALIB_OVERFLOW_OFFSET 0x218 +#define GC_XO_DXO_INT_STATE_SLOW_CALIB_OVERFLOW_OFFSET 0x21c #define GC_XO_DXO_INT_STATE_SLOW_CALIB_UNDERRUN_LSB 0x3 #define GC_XO_DXO_INT_STATE_SLOW_CALIB_UNDERRUN_MASK 0x8 #define GC_XO_DXO_INT_STATE_SLOW_CALIB_UNDERRUN_SIZE 0x1 #define GC_XO_DXO_INT_STATE_SLOW_CALIB_UNDERRUN_DEFAULT 0x0 -#define GC_XO_DXO_INT_STATE_SLOW_CALIB_UNDERRUN_OFFSET 0x218 +#define GC_XO_DXO_INT_STATE_SLOW_CALIB_UNDERRUN_OFFSET 0x21c #define GC_XO_DXO_INT_STATE_CLK_JTR_NOP_SEEN_LSB 0x4 #define GC_XO_DXO_INT_STATE_CLK_JTR_NOP_SEEN_MASK 0x10 #define GC_XO_DXO_INT_STATE_CLK_JTR_NOP_SEEN_SIZE 0x1 #define GC_XO_DXO_INT_STATE_CLK_JTR_NOP_SEEN_DEFAULT 0x0 -#define GC_XO_DXO_INT_STATE_CLK_JTR_NOP_SEEN_OFFSET 0x218 +#define GC_XO_DXO_INT_STATE_CLK_JTR_NOP_SEEN_OFFSET 0x21c #define GC_XO_DXO_INT_STATE_CLK_TIMER_NOP_SEEN_LSB 0x5 #define GC_XO_DXO_INT_STATE_CLK_TIMER_NOP_SEEN_MASK 0x20 #define GC_XO_DXO_INT_STATE_CLK_TIMER_NOP_SEEN_SIZE 0x1 #define GC_XO_DXO_INT_STATE_CLK_TIMER_NOP_SEEN_DEFAULT 0x0 -#define GC_XO_DXO_INT_STATE_CLK_TIMER_NOP_SEEN_OFFSET 0x218 +#define GC_XO_DXO_INT_STATE_CLK_TIMER_NOP_SEEN_OFFSET 0x21c #define GC_XO_DXO_INT_STATE_CLK_JTR_SW_TRIM_DONE_LSB 0x6 #define GC_XO_DXO_INT_STATE_CLK_JTR_SW_TRIM_DONE_MASK 0x40 #define GC_XO_DXO_INT_STATE_CLK_JTR_SW_TRIM_DONE_SIZE 0x1 #define GC_XO_DXO_INT_STATE_CLK_JTR_SW_TRIM_DONE_DEFAULT 0x0 -#define GC_XO_DXO_INT_STATE_CLK_JTR_SW_TRIM_DONE_OFFSET 0x218 +#define GC_XO_DXO_INT_STATE_CLK_JTR_SW_TRIM_DONE_OFFSET 0x21c #define GC_XO_DXO_INT_STATE_CLK_TIMER_SW_TRIM_DONE_LSB 0x7 #define GC_XO_DXO_INT_STATE_CLK_TIMER_SW_TRIM_DONE_MASK 0x80 #define GC_XO_DXO_INT_STATE_CLK_TIMER_SW_TRIM_DONE_SIZE 0x1 #define GC_XO_DXO_INT_STATE_CLK_TIMER_SW_TRIM_DONE_DEFAULT 0x0 -#define GC_XO_DXO_INT_STATE_CLK_TIMER_SW_TRIM_DONE_OFFSET 0x218 +#define GC_XO_DXO_INT_STATE_CLK_TIMER_SW_TRIM_DONE_OFFSET 0x21c #define GC_XO_DXO_INT_TEST_FAST_CALIB_OVERFLOW_LSB 0x0 #define GC_XO_DXO_INT_TEST_FAST_CALIB_OVERFLOW_MASK 0x1 #define GC_XO_DXO_INT_TEST_FAST_CALIB_OVERFLOW_SIZE 0x1 #define GC_XO_DXO_INT_TEST_FAST_CALIB_OVERFLOW_DEFAULT 0x0 -#define GC_XO_DXO_INT_TEST_FAST_CALIB_OVERFLOW_OFFSET 0x21c +#define GC_XO_DXO_INT_TEST_FAST_CALIB_OVERFLOW_OFFSET 0x220 #define GC_XO_DXO_INT_TEST_FAST_CALIB_UNDERRUN_LSB 0x1 #define GC_XO_DXO_INT_TEST_FAST_CALIB_UNDERRUN_MASK 0x2 #define GC_XO_DXO_INT_TEST_FAST_CALIB_UNDERRUN_SIZE 0x1 #define GC_XO_DXO_INT_TEST_FAST_CALIB_UNDERRUN_DEFAULT 0x0 -#define GC_XO_DXO_INT_TEST_FAST_CALIB_UNDERRUN_OFFSET 0x21c +#define GC_XO_DXO_INT_TEST_FAST_CALIB_UNDERRUN_OFFSET 0x220 #define GC_XO_DXO_INT_TEST_SLOW_CALIB_OVERFLOW_LSB 0x2 #define GC_XO_DXO_INT_TEST_SLOW_CALIB_OVERFLOW_MASK 0x4 #define GC_XO_DXO_INT_TEST_SLOW_CALIB_OVERFLOW_SIZE 0x1 #define GC_XO_DXO_INT_TEST_SLOW_CALIB_OVERFLOW_DEFAULT 0x0 -#define GC_XO_DXO_INT_TEST_SLOW_CALIB_OVERFLOW_OFFSET 0x21c +#define GC_XO_DXO_INT_TEST_SLOW_CALIB_OVERFLOW_OFFSET 0x220 #define GC_XO_DXO_INT_TEST_SLOW_CALIB_UNDERRUN_LSB 0x3 #define GC_XO_DXO_INT_TEST_SLOW_CALIB_UNDERRUN_MASK 0x8 #define GC_XO_DXO_INT_TEST_SLOW_CALIB_UNDERRUN_SIZE 0x1 #define GC_XO_DXO_INT_TEST_SLOW_CALIB_UNDERRUN_DEFAULT 0x0 -#define GC_XO_DXO_INT_TEST_SLOW_CALIB_UNDERRUN_OFFSET 0x21c +#define GC_XO_DXO_INT_TEST_SLOW_CALIB_UNDERRUN_OFFSET 0x220 #define GC_XO_DXO_INT_TEST_CLK_JTR_NOP_SEEN_LSB 0x4 #define GC_XO_DXO_INT_TEST_CLK_JTR_NOP_SEEN_MASK 0x10 #define GC_XO_DXO_INT_TEST_CLK_JTR_NOP_SEEN_SIZE 0x1 #define GC_XO_DXO_INT_TEST_CLK_JTR_NOP_SEEN_DEFAULT 0x0 -#define GC_XO_DXO_INT_TEST_CLK_JTR_NOP_SEEN_OFFSET 0x21c +#define GC_XO_DXO_INT_TEST_CLK_JTR_NOP_SEEN_OFFSET 0x220 #define GC_XO_DXO_INT_TEST_CLK_TIMER_NOP_SEEN_LSB 0x5 #define GC_XO_DXO_INT_TEST_CLK_TIMER_NOP_SEEN_MASK 0x20 #define GC_XO_DXO_INT_TEST_CLK_TIMER_NOP_SEEN_SIZE 0x1 #define GC_XO_DXO_INT_TEST_CLK_TIMER_NOP_SEEN_DEFAULT 0x0 -#define GC_XO_DXO_INT_TEST_CLK_TIMER_NOP_SEEN_OFFSET 0x21c +#define GC_XO_DXO_INT_TEST_CLK_TIMER_NOP_SEEN_OFFSET 0x220 #define GC_XO_DXO_INT_TEST_CLK_JTR_SW_TRIM_DONE_LSB 0x6 #define GC_XO_DXO_INT_TEST_CLK_JTR_SW_TRIM_DONE_MASK 0x40 #define GC_XO_DXO_INT_TEST_CLK_JTR_SW_TRIM_DONE_SIZE 0x1 #define GC_XO_DXO_INT_TEST_CLK_JTR_SW_TRIM_DONE_DEFAULT 0x0 -#define GC_XO_DXO_INT_TEST_CLK_JTR_SW_TRIM_DONE_OFFSET 0x21c +#define GC_XO_DXO_INT_TEST_CLK_JTR_SW_TRIM_DONE_OFFSET 0x220 #define GC_XO_DXO_INT_TEST_CLK_TIMER_SW_TRIM_DONE_LSB 0x7 #define GC_XO_DXO_INT_TEST_CLK_TIMER_SW_TRIM_DONE_MASK 0x80 #define GC_XO_DXO_INT_TEST_CLK_TIMER_SW_TRIM_DONE_SIZE 0x1 #define GC_XO_DXO_INT_TEST_CLK_TIMER_SW_TRIM_DONE_DEFAULT 0x0 -#define GC_XO_DXO_INT_TEST_CLK_TIMER_SW_TRIM_DONE_OFFSET 0x21c +#define GC_XO_DXO_INT_TEST_CLK_TIMER_SW_TRIM_DONE_OFFSET 0x220 #define GC_M3_ITM_TCR_ITMENA_LSB 0x0 #define GC_M3_ITM_TCR_ITMENA_MASK 0x1 #define GC_M3_ITM_TCR_ITMENA_SIZE 0x1 @@ -27431,10 +27550,14 @@ -1 #endif /* GC__ENABLE_FLASH_DFT_DEFINITIONS__ */ +#define GC_CONST_SWDP_FPGA_CONFIG_USB_CRYPTO 0x3 #define GC_CONST_FPGA_JITTER_FIXED_FREQ 0xf +#define GC_CONST_SWDP_FPGA_CONFIG_USB_8X8CRYPTO 0x2 +#define GC_CONST_SWDP_FPGA_CONFIG 0x2 #define GC_CONST_FSH_PE_CONTROL_BULKERASE 0x1d1e2bad #define GC_CONST_FSH_PE_EN 0xb11924e1 #define GC_CONST_FSH_PE_CONTROL_PROGRAM 0x27182818 +#define GC_CONST_SWDP_FPGA_CONFIG_NOUSB_CRYPTO 0x1 #define GC_CONST_FSH_PE_CONTROL_ERASE 0x31415927 #define GC_CONST_FSH_PE_CONTROL_READ 0x16021765 #define GC_CONST_FPGA_TIMER_FIXED_FREQ 0x18 |