npcx7: introduce new chip variant npcx7m7fc

Add the following changes:
1. add CHIP_VARIANT_NPCX7M7WC in the npcx7 chip configuration files to
   define what (RAM, flash, features...) are supported in npcx7m7fc.
2. add the chip id and chip revision id of npcx7m7fc

BRANCH=none
BUG=b:163910671
TEST=pass "make buildall"
TEST=with related CLs, change CHIP_VARIANT to npcx7m7fc in
board/npcx7_evb/build.mk; flash image and run on the internal testing board of
npcx7m7fc; make sure the EC can boot up; check the chip ID and chip
revision ID are correct by console command "version".

Signed-off-by: CHLin <CHLin56@nuvoton.com>
Change-Id: Ibef17148eeba71bbbb63145064a5fa398c0118dc
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2355156
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: CH Lin <chlin56@nuvoton.com>

4 files changed, 23 insertions, 10 deletions

diff --git a/chip/npcx/config_chip-npcx7.h b/chip/npcx/config_chip-npcx7.h
index d3c6d4e367..5aa42ae065 100644
--- a/chip/npcx/config_chip-npcx7.h
+++ b/chip/npcx/config_chip-npcx7.h
@@ -20,15 +20,16 @@
 
 /* The optional hardware features depend on chip variant */
 #if defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) || \
-	defined(CHIP_VARIANT_NPCX7M6FC) || defined(CHIP_VARIANT_NPCX7M7WB) || \
-	defined(CHIP_VARIANT_NPCX7M7WC)
+	defined(CHIP_VARIANT_NPCX7M6FC) || defined(CHIP_VARIANT_NPCX7M7FC) || \
+	defined(CHIP_VARIANT_NPCX7M7WB) || defined(CHIP_VARIANT_NPCX7M7WC)
 #define NPCX_INT_FLASH_SUPPORT /* Internal flash support */
 #define NPCX_PSL_MODE_SUPPORT /* Power switch logic mode for ultra-low power */
 #define NPCX_EXT32K_OSC_SUPPORT /* External 32KHz crytal osc. input support */
 #endif
 
 #if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M6FC) || \
-	defined(CHIP_VARIANT_NPCX7M7WB) || defined(CHIP_VARIANT_NPCX7M7WC)
+	defined(CHIP_VARIANT_NPCX7M7FC) || defined(CHIP_VARIANT_NPCX7M7WB) || \
+	defined(CHIP_VARIANT_NPCX7M7WC)
 #define NPCX_UART_FIFO_SUPPORT
 /* Number of UART modules. */
 #define NPCX_SECOND_UART
@@ -83,9 +84,16 @@
 #	define CONFIG_RAM_BASE    0x200B0000 /* memory address of data ram */
 	/* 126 KB data RAM + 2 KB BT RAM size */
 #	define CONFIG_DATA_RAM_SIZE    0x00020000
-#elif defined(CHIP_VARIANT_NPCX7M7WC)
+#elif defined(CHIP_VARIANT_NPCX7M7FC) || defined(CHIP_VARIANT_NPCX7M7WC)
 	/*
-	 * 256KB program RAM, but only 512K of Flash (vs 1M for the
+	 * In npcx797wc and npcx797fc, the code RAM size is limited by the
+	 * internal flash size (i.e. 512 KB/2=256 KB.) The driver has to
+	 * re-organize the memory to:
+	 * 1. the overall memory (RAM) layout is re-organized against the
+	 * datasheet:
+	 *     In datasheet: 320 KB code RAM + 64 KB data RAM
+	 *     After re-organization: 256 KB code RAM + 128 KB data RAM.
+	 * 2. 256KB program RAM, but only 512K of Flash (vs 1M for the
 	 * -WB). After the boot header is added, a 256K image would be
 	 * too large to fit in either RO or RW sections of Flash (each
 	 * of which is half of it). Because other code assumes that
diff --git a/chip/npcx/config_flash_layout.h b/chip/npcx/config_flash_layout.h
index 7aebe172c7..91b3ba9e9f 100644
--- a/chip/npcx/config_flash_layout.h
+++ b/chip/npcx/config_flash_layout.h
@@ -32,7 +32,7 @@
 #define CONFIG_EC_WRITABLE_STORAGE_SIZE  0x40000
 #elif defined(CHIP_VARIANT_NPCX7M6F) || defined(CHIP_VARIANT_NPCX7M6FB) || \
 	defined(CHIP_VARIANT_NPCX7M6FC) || defined(CHIP_VARIANT_NPCX7M6G) || \
-	defined(CHIP_VARIANT_NPCX7M7WC)
+	defined(CHIP_VARIANT_NPCX7M7FC) || defined(CHIP_VARIANT_NPCX7M7WC)
 #define CONFIG_EC_PROTECTED_STORAGE_OFF  0
 #define CONFIG_EC_PROTECTED_STORAGE_SIZE 0x40000
 #define CONFIG_EC_WRITABLE_STORAGE_OFF   0x40000
diff --git a/chip/npcx/registers.h b/chip/npcx/registers.h
index 3c1cd4f006..8ed003ab5c 100644
--- a/chip/npcx/registers.h
+++ b/chip/npcx/registers.h
@@ -985,7 +985,8 @@ enum {
 #define NPCX_PWDWN_CTL7_SMB6_PD          1
 #define NPCX_PWDWN_CTL7_SMB7_PD          2
 #if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M6FC) || \
-	defined(CHIP_VARIANT_NPCX7M7WB) || defined(CHIP_VARIANT_NPCX7M7WC)
+	defined(CHIP_VARIANT_NPCX7M7FC) || defined(CHIP_VARIANT_NPCX7M7WB) || \
+	defined(CHIP_VARIANT_NPCX7M7WC)
 #define NPCX_PWDWN_CTL7_ITIM64_PD        5
 #define NPCX_PWDWN_CTL7_UART2_PD         6
 #endif
@@ -1271,7 +1272,8 @@ enum PM_CHANNEL_T {
 /* BBRAM register fields */
 #define NPCX_BKUP_STS_IBBR               7
 #if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M6FC) || \
-	defined(CHIP_VARIANT_NPCX7M7WB) || defined(CHIP_VARIANT_NPCX7M7WC)
+	defined(CHIP_VARIANT_NPCX7M7FC) || defined(CHIP_VARIANT_NPCX7M7WB) || \
+	defined(CHIP_VARIANT_NPCX7M7WC)
 #define NPCX_BKUP_STS_VSBY_STS           1
 #define NPCX_BKUP_STS_VCC1_STS           0
 #define NPCX_BKUP_STS_ALL_MASK \
diff --git a/chip/npcx/system.c b/chip/npcx/system.c
index 2a1407d4f8..3a1c84601f 100644
--- a/chip/npcx/system.c
+++ b/chip/npcx/system.c
@@ -99,7 +99,7 @@ void system_check_bbram_on_reset(void)
 		/*
 		 * npcx5/npcx7m6g/npcx7m6f:
 		 *   Clear IBBR bit
-		 * npcx7m6fb/npcx7m6fc/npcx7m7wb/npcx7m7wc:
+		 * npcx7m6fb/npcx7m6fc/npcx7m7fc/npcx7m7wb/npcx7m7wc:
 		 *   Clear IBBR/VSBY_STS/VCC1_STS bit
 		 */
 		NPCX_BKUP_STS = NPCX_BKUP_STS_ALL_MASK;
@@ -736,7 +736,8 @@ void system_pre_init(void)
 
 #if defined(CHIP_FAMILY_NPCX7)
 #if defined(CHIP_VARIANT_NPCX7M6FB) || defined(CHIP_VARIANT_NPCX7M6FC) || \
-	defined(CHIP_VARIANT_NPCX7M7WB) || defined(CHIP_VARIANT_NPCX7M7WC)
+	defined(CHIP_VARIANT_NPCX7M7FC) || defined(CHIP_VARIANT_NPCX7M7WB) || \
+	defined(CHIP_VARIANT_NPCX7M7WC)
 	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_7) = 0xE7;
 #else
 	NPCX_PWDWN_CTL(NPCX_PMC_PWDWN_7) = 0x07;
@@ -847,6 +848,8 @@ const char *system_get_chip_name(void)
 #elif defined(CHIP_FAMILY_NPCX7)
 	case 0x1F:
 		return "NPCX787G";
+	case 0x20:
+		return "NPCX797F";
 	case 0x21:
 	case 0x29:
 		return "NPCX796F";