jslrvp: add Jasperlake RVP support

Following features are enabled and verified.
   1. Power sequencing
   2. Host communication
   3. Battery
   4. Charger
   5. USB TYPE-C MUX, DP/HDMI, USB2/3
   6. TPM-SOC communication
   7. LED
   8. Keyboard

BRANCH=none
BUG=b:146693933
TEST=Build, flash and boot the Jasperlake RVP platform to OS
make BOARD=jslrvp_ite; sudo util/flash_ec --board=jslrvp_ite

Change-Id: I80227833fcfca5636ac8f30abc099db5717bfa05
Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com>
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1980091
Reviewed-by: Justin TerAvest <teravest@chromium.org>

8 files changed, 439 insertions, 0 deletions

diff --git a/baseboard/intelrvp/build.mk b/baseboard/intelrvp/build.mk
index 8b22ee835c..4247a38948 100644
--- a/baseboard/intelrvp/build.mk
+++ b/baseboard/intelrvp/build.mk
@@ -20,6 +20,7 @@ baseboard-$(CONFIG_BC12_DETECT_MAX14637)+=bc12.o
 
 #USB MUX specific files
 baseboard-$(CONFIG_USB_MUX_VIRTUAL)+=usb_mux.o
+baseboard-$(CONFIG_USB_MUX_ANX7440)+=usb_mux.o
 
 #USB Retimer specific files
 baseboard-$(CONFIG_USBC_RETIMER_INTEL_BB)+=retimer.o
diff --git a/baseboard/intelrvp/usb_mux.c b/baseboard/intelrvp/usb_mux.c
index 2526fa5450..65448f5992 100644
--- a/baseboard/intelrvp/usb_mux.c
+++ b/baseboard/intelrvp/usb_mux.c
@@ -6,6 +6,8 @@
 /* Intel BASEBOARD-RVP USB MUX specific configuration */
 
 #include "common.h"
+#include "anx7440.h"
+#include "timer.h"
 #include "usb_mux.h"
 
 /* USB muxes Configuration */
@@ -24,3 +26,19 @@ struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
 };
 BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == CONFIG_USB_PD_PORT_MAX_COUNT);
 #endif /* CONFIG_USB_MUX_VIRTUAL */
+
+#ifdef CONFIG_USB_MUX_ANX7440
+struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	[TYPE_C_PORT_0] = {
+		.port_addr = I2C_ADDR_USB_MUX0_FLAGS,
+		.driver = &anx7440_usb_mux_driver,
+	},
+#ifdef HAS_TASK_PD_C1
+	[TYPE_C_PORT_1] = {
+		.port_addr = I2C_ADDR_USB_MUX1_FLAGS,
+		.driver = &anx7440_usb_mux_driver,
+	},
+#endif /* HAS_TASK_PD_C1 */
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == CONFIG_USB_PD_PORT_MAX_COUNT);
+#endif /* CONFIG_USB_MUX_ANX7440 */
diff --git a/board/jslrvp_ite/board.c b/board/jslrvp_ite/board.c
new file mode 100644
index 0000000000..4e7ece9799
--- /dev/null
+++ b/board/jslrvp_ite/board.c
@@ -0,0 +1,115 @@
+/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Intel Jasperlake RVP with ITE EC board specific configuration */
+
+#include "button.h"
+#include "extpower.h"
+#include "i2c.h"
+#include "intc.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "switch.h"
+#include "system.h"
+#include "tablet_mode.h"
+#include "uart.h"
+
+#include "gpio_list.h"
+
+#define CPRINTS(format, args...) cprints(CC_COMMAND, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_COMMAND, format, ## args)
+
+/* TCPC gpios */
+const struct tcpc_gpio_config_t tcpc_gpios[CONFIG_USB_PD_PORT_MAX_COUNT] = {
+	[TYPE_C_PORT_0] = {
+		.vbus = {
+			.pin = GPIO_USB_C0_VBUS_INT,
+			.pin_pol = 1,
+		},
+		.src = {
+			.pin = GPIO_USB_C0_SRC_EN,
+			.pin_pol = 1,
+		},
+		.snk = {
+			.pin = GPIO_USB_C0_SNK_EN_L,
+			.pin_pol = 0,
+		},
+	},
+	[TYPE_C_PORT_1] = {
+		.vbus = {
+			.pin = GPIO_USB_C1_VBUS_INT,
+			.pin_pol = 1,
+		},
+		.src = {
+			.pin = GPIO_USB_C1_SRC_EN,
+			.pin_pol = 1,
+		},
+		.snk = {
+			.pin = GPIO_USB_C1_SNK_EN_L,
+			.pin_pol = 0,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_gpios) == CONFIG_USB_PD_PORT_MAX_COUNT);
+
+/* I2C ports */
+const struct i2c_port_t i2c_ports[] = {
+	/* Flash EC */
+	[I2C_CHAN_FLASH] = {
+		.name = "chan-A",
+		.port = IT83XX_I2C_CH_A,
+		.kbps = 100,
+		.scl = GPIO_I2C_A_SCL,
+		.sda = GPIO_I2C_A_SDA,
+	},
+	/*
+	 * Port-80 Display, Charger, Battery, IO-expanders, EEPROM,
+	 * IMVP9, AUX-rail, power-monitor.
+	 */
+	[I2C_CHAN_BATT_CHG] = {
+		.name = "batt_chg",
+		.port = IT83XX_I2C_CH_B,
+		.kbps = 100,
+		.scl = GPIO_I2C_B_SCL,
+		.sda = GPIO_I2C_B_SDA,
+	},
+	/* Retimers, PDs */
+	[I2C_CHAN_RETIMER] = {
+		.name = "retimer",
+		.port = IT83XX_I2C_CH_E,
+		.kbps = 100,
+		.scl = GPIO_I2C_E_SCL,
+		.sda = GPIO_I2C_E_SDA,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(i2c_ports) == I2C_CHAN_COUNT);
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+/*
+ * Returns board information (board id[7:0] and Fab id[15:8]) on success
+ * -1 on error.
+ */
+int board_get_version(void)
+{
+	int fab_id;
+	int board_id;
+	int bom_id;
+
+	if (ioexpander_read_intelrvp_version(&fab_id, &board_id))
+		return -1;
+	/*
+	 * Port0: bit 1:0 - FAB ID(1:0) + 1
+	 * Port1: bit 7:5 - BOM ID(2:0)
+	 *        bit 4:0 - BOARD ID(4:0)
+	 */
+	fab_id = (fab_id & 0x03) + 1;
+	bom_id = ((board_id & 0xE0) >> 5);
+	board_id &= 0x1F;
+
+	CPRINTS("BID:0x%x, FID:0x%x, BOM:0x%x", board_id, fab_id, bom_id);
+
+	return board_id | (fab_id << 8);
+}
diff --git a/board/jslrvp_ite/board.h b/board/jslrvp_ite/board.h
new file mode 100644
index 0000000000..2ac8afa8d9
--- /dev/null
+++ b/board/jslrvp_ite/board.h
@@ -0,0 +1,78 @@
+/* Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Intel Jasperlake RVP with ITE EC board specific configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#define CONFIG_CHIPSET_JASPERLAKE
+#define GPIO_PG_EC_RSMRST_ODL		GPIO_RSMRST_L_PGOOD
+#define GPIO_PCH_DSW_PWROK		GPIO_EC_PCH_DSW_PWROK
+#define GPIO_PG_EC_ALL_SYS_PWRGD	GPIO_ALL_SYS_PWRGD
+
+/* Fan features */
+#define CONFIG_FANS 1
+#define BOARD_FAN_MIN_RPM 3000
+#define BOARD_FAN_MAX_RPM 10000
+
+/* Temperature sensor */
+#define CONFIG_TEMP_SENSOR
+
+#include "baseboard.h"
+
+/* Charger */
+#define CONFIG_CHARGER_ISL9238
+
+/* DC Jack charge ports */
+#undef  CONFIG_DEDICATED_CHARGE_PORT_COUNT
+#define CONFIG_DEDICATED_CHARGE_PORT_COUNT 1
+
+/* USB ports */
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+#define DEDICATED_CHARGE_PORT 2
+
+/* USB MUX */
+#define CONFIG_USB_MUX_ANX7440
+
+/* USB HPD */
+#define CONFIG_USB_PD_DP_HPD_GPIO
+
+/* Thermal configs */
+
+/* I2C ports */
+#define CONFIG_IT83XX_SMCLK2_ON_GPC7
+
+#define I2C_PORT_CHARGER	IT83XX_I2C_CH_B
+#define I2C_PORT_BATTERY	IT83XX_I2C_CH_B
+#define I2C_PORT_PCA9555_BOARD_ID_GPIO	IT83XX_I2C_CH_B
+#define I2C_PORT_PORT80		IT83XX_I2C_CH_B
+#define I2C_PORT_USB_MUX    IT83XX_I2C_CH_E
+
+#define I2C_ADDR_PCA9555_BOARD_ID_GPIO	0x22
+#define PORT80_I2C_ADDR			MAX695X_I2C_ADDR1_FLAGS
+
+#ifndef __ASSEMBLER__
+
+enum jslrvp_charge_ports {
+	TYPE_C_PORT_0,
+	TYPE_C_PORT_1,
+};
+
+enum jslrvp_i2c_channel {
+	I2C_CHAN_FLASH,
+	I2C_CHAN_BATT_CHG,
+	I2C_CHAN_RETIMER,
+	I2C_CHAN_COUNT,
+};
+
+/* Define max power */
+#define PD_MAX_POWER_MW        45000
+
+int board_get_version(void);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/jslrvp_ite/build.mk b/board/jslrvp_ite/build.mk
new file mode 100644
index 0000000000..31f33208ba
--- /dev/null
+++ b/board/jslrvp_ite/build.mk
@@ -0,0 +1,15 @@
+# -*- makefile -*-
+# Copyright 2019 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Intel Jasperlake RVP with ITE EC board specific configuration
+#
+
+#it8320
+CHIP:=it83xx
+CHIP_FAMILY:=it8320
+CHIP_VARIANT:=it8320dx
+BASEBOARD:=intelrvp
+
+board-y=board.o
diff --git a/board/jslrvp_ite/ec.tasklist b/board/jslrvp_ite/ec.tasklist
new file mode 100644
index 0000000000..04a12640fd
--- /dev/null
+++ b/board/jslrvp_ite/ec.tasklist
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Intel Jasperlake RVP with ITE EC board specific configuration.
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
+	TASK_NOTEST(PDCMD, pd_command_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/jslrvp_ite/gpio.inc b/board/jslrvp_ite/gpio.inc
new file mode 100644
index 0000000000..b652aa1379
--- /dev/null
+++ b/board/jslrvp_ite/gpio.inc
@@ -0,0 +1,189 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Intel Jasperlake RVP with ITE EC board specific configuration */
+
+/*
+ * Declare symbolic names for all the GPIOs that we care about.
+ * Note: Those with interrupt handlers must be declared first.
+ */
+
+/* Power sequencing interrupts */
+GPIO_INT(PG_EC_DSW_PWROK,	PIN(C, 0), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(SLP_SUS_L,	PIN(K, 2), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(ALL_SYS_PWRGD,	PIN(F, 0), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(RSMRST_L_PGOOD,PIN(F, 1), GPIO_INT_BOTH, power_signal_interrupt)
+GPIO_INT(PCH_SLP_S0_L,	PIN(G, 6), GPIO_INT_BOTH, power_signal_interrupt)
+#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S3
+GPIO_INT(PCH_SLP_S3_L,		PIN(F, 2), GPIO_INT_BOTH, power_signal_interrupt)
+#endif
+#ifndef CONFIG_HOSTCMD_ESPI_VW_SLP_S4
+GPIO_INT(PCH_SLP_S4_L,		PIN(F, 3), GPIO_INT_BOTH, power_signal_interrupt)
+#endif
+
+/* Button interrupts */
+GPIO_INT(VOLUME_UP_L,	PIN(D, 5), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(VOLUME_DOWN_L,	PIN(D, 6), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
+GPIO_INT(LID_OPEN,	PIN(E, 2), GPIO_INT_BOTH | GPIO_PULL_UP, lid_interrupt)
+GPIO_INT(POWER_BUTTON_L,PIN(L, 3), GPIO_INT_BOTH, power_button_interrupt)
+
+GPIO_INT(AC_PRESENT,	PIN(A, 7), GPIO_INT_BOTH, extpower_interrupt)
+
+GPIO_INT(UART1_RX,	PIN(B, 0), GPIO_INT_FALLING, uart_deepsleep_interrupt)	/* UART1 RX input */
+
+GPIO_INT(WP_L,      PIN(I, 4), GPIO_INT_BOTH, switch_interrupt)     /* EC_WP_ODL */
+
+#ifdef CONFIG_HOSTCMD_ESPI
+/* enable 1.8v input of EC's espi_reset pin, and then this pin takes effect. */
+GPIO_INT(ESPI_RESET_L,	PIN(D, 2), GPIO_INT_FALLING | GPIO_SEL_1P8V, espi_reset_pin_asserted_interrupt) /* eSPI_reset# */
+#endif
+
+GPIO_INT(TABLET_MODE_L,	PIN(K, 1), GPIO_INT_BOTH, gmr_tablet_switch_isr)
+
+/* DC Jack presence coming from +VADP_OUT */
+GPIO_INT(DC_JACK_PRESENT,   PIN(J, 2), GPIO_INT_BOTH, board_dc_jack_interrupt)
+
+/* Type-C interrupts */
+GPIO_INT(USB_C0_VBUS_INT,	PIN(L, 5), GPIO_INT_BOTH, vbus0_evt)
+GPIO_INT(USB_C1_VBUS_INT,	PIN(D, 4), GPIO_INT_BOTH, vbus1_evt)
+
+/* Power sequencing GPIOs */
+GPIO(CPU_PROCHOT,	PIN(B, 2), GPIO_INPUT)
+GPIO(SYS_RESET_L,	PIN(B, 6), GPIO_ODR_HIGH)
+GPIO(PCH_RSMRST_L,	PIN(C, 6), GPIO_OUT_LOW)
+GPIO(PCH_PWRBTN_L,	PIN(D, 0), GPIO_ODR_HIGH)
+GPIO(EC_SPI_OE_N,	PIN(I, 2), GPIO_OUT_LOW)
+/*
+ * PCH_SYS_PWROK is an input, driven by the Silego chip. The common x86
+ * power sequencing expects that PCH_SYS_PWROK is an output and will drive
+ * this signal if GPIO_PCH_SYS_PWROK is configured. Map this pin as no-connect
+ * so that state can be monitored using the console.
+ */
+GPIO(NC_PCH_SYS_PWROK,	PIN(K, 4), GPIO_INPUT)
+GPIO(EN_PP5000, 	PIN(L, 4), GPIO_OUT_LOW)
+GPIO(EN_PP3300_A,	PIN(C, 3), GPIO_OUT_LOW)
+GPIO(EC_PCH_DSW_PWROK,	PIN(L, 6), GPIO_OUT_LOW)
+
+/*
+ * SYS_PWROK driven directly to AP by Silego, EC not needed for generation.
+ * PCH_SYS_PWROK is routed to EC, but mark unimplemented to prevent common
+ * Ice Lake code from driving signal.
+ */
+UNIMPLEMENTED(PCH_SYS_PWROK)
+
+/* Host communication GPIOs */
+GPIO(PCH_WAKE_L,	PIN(J, 0), GPIO_ODR_HIGH)
+#ifndef CONFIG_HOSTCMD_ESPI
+GPIO(PCH_PLTRST_L,	PIN(E, 3), GPIO_INPUT | GPIO_PULL_UP)
+#endif
+
+/* Battery present */
+GPIO(EC_BATT_PRES_L,	PIN(K, 0), GPIO_INPUT)
+
+/* Type-C GPIOs */
+GPIO(USB_C0_SRC_EN,	PIN(L, 1), GPIO_OUT_LOW)
+GPIO(USB_C0_SNK_EN_L,	PIN(H, 6), GPIO_ODR_LOW)
+GPIO(USB_C0_SRC_HI_ILIM, PIN(M, 6), GPIO_OUT_LOW)
+GPIO(USB_C0_DP_HPD,	PIN(E, 6), GPIO_OUT_LOW)
+GPIO(USB_C0_FRS_EN,	PIN(L, 7), GPIO_INPUT)
+
+GPIO(USB_C1_SRC_EN,	PIN(G, 1), GPIO_OUT_LOW)
+GPIO(USB_C1_SNK_EN_L,	PIN(I, 5), GPIO_ODR_LOW)
+GPIO(USB_C1_SRC_HI_ILIM, PIN(A, 0), GPIO_OUT_LOW)
+GPIO(USB_C1_DP_HPD,	PIN(D, 3), GPIO_OUT_LOW)
+GPIO(USB_C1_FRS_EN,	PIN(K, 5), GPIO_INPUT)
+
+/*
+ * Type-C USB MUX GPIOs
+ * TODO(b/146683781): drive initial level to low and
+ * handle the low power mode
+ */
+GPIO(USB_C0_LS_EN,		PIN(J, 1), GPIO_OUT_HIGH)
+GPIO(USB_C1_LS_EN,		PIN(C, 4), GPIO_OUT_HIGH)
+
+/* Type-C BC1.2 GPIOs */
+GPIO(USB_C0_BC12_CHG_DET_L,	PIN(A, 1), GPIO_INPUT)
+GPIO(USB_C0_BC12_VBUS_ON_ODL,	PIN(H, 4), GPIO_ODR_HIGH)
+
+GPIO(USB_C1_BC12_CHG_DET_L,	PIN(B, 7), GPIO_INPUT)
+GPIO(USB_C1_BC12_VBUS_ON_ODL,	PIN(J, 6), GPIO_ODR_HIGH)
+
+/* USB-A GPIOs */
+GPIO(USB_A_5V_EN,	PIN(K, 3), GPIO_INPUT)
+
+/* LED */
+GPIO(BAT_LED_GREEN_L,	PIN(A, 6), GPIO_OUT_HIGH)	/* LED_2_L */
+GPIO(AC_LED_GREEN_L,	PIN(A, 3), GPIO_OUT_HIGH)	/* LED_1_L */
+
+/* FAN control pins */
+GPIO(FAN_POWER_EN,	PIN(K, 6), GPIO_OUT_LOW)
+
+/* H1 pins */
+GPIO(CCD_MODE_ODL,	PIN(B, 5), GPIO_INPUT)
+GPIO(ENTERING_RW,	PIN(C, 5), GPIO_OUT_LOW)
+
+/* Used if Type-A ports have BC1.2 */
+GPIO(NC_USB_A_CHG_EN,		PIN(D, 1), GPIO_INPUT)
+
+/* Used if dead battery LDO present */
+GPIO(NC_USBC_LDO_ENABLE,	PIN(G, 2), GPIO_INPUT)
+
+/* Used with Discreate TBT and or with PD on RVP */
+GPIO(NC_TBT_C0_RESET_N,		PIN(KSO_H, 7), GPIO_INPUT)
+GPIO(NC_TBT_C1_RESET_N,		PIN(K, 7), GPIO_INPUT)
+GPIO(NC_USB_C0_RETIMER_ALRT,	PIN(I, 7), GPIO_INPUT)
+GPIO(NC_USB_C1_RETIMER_ALRT,	PIN(G, 0), GPIO_INPUT)
+
+/* Used if PMIC is used */
+GPIO(NC_PMIC_EN,		PIN(H, 3), GPIO_INPUT)
+
+/* Used if Base EC is present */
+GPIO(NC_EC_BASE_DET,		PIN(I, 3), GPIO_INPUT)
+
+#ifndef CONFIG_HOSTCMD_ESPI
+GPIO_INT(ESPI_RESET_L,	PIN(D, 2), GPIO_INPUT)
+#endif
+
+/* Unused pins */
+GPIO(NC_SUSWARN,		PIN(E, 1), GPIO_INPUT)
+GPIO(NC_SD_CARD_DETECT,		PIN(E, 5), GPIO_INPUT)
+GPIO(NC_BATT_DISABLE,		PIN(H, 0), GPIO_INPUT)
+GPIO(NC_SLP_S0_CS_N,		PIN(I, 0), GPIO_INPUT)
+
+/*
+ * I2C pins should be configure as inputs until I2C module is
+ * initialized. This will avoid driving the lines unintentionally.
+ */
+GPIO(I2C_A_SCL,	PIN(B, 3), GPIO_INPUT)
+GPIO(I2C_A_SDA,	PIN(B, 4), GPIO_INPUT)
+GPIO(I2C_B_SCL,	PIN(C, 1), GPIO_INPUT)
+GPIO(I2C_B_SDA,	PIN(C, 2), GPIO_INPUT)
+GPIO(I2C_C_SCL,	PIN(C, 7), GPIO_INPUT)
+GPIO(I2C_C_SDA,	PIN(F, 7), GPIO_INPUT)
+GPIO(I2C_E_SCL,	PIN(E, 0), GPIO_INPUT)
+GPIO(I2C_E_SDA,	PIN(E, 7), GPIO_INPUT)
+GPIO(I2C_F_SCL,	PIN(A, 4), GPIO_INPUT)
+GPIO(I2C_F_SDA,	PIN(A, 5), GPIO_INPUT)
+
+/* Alternate pins for I2C */
+ALTERNATE(PIN_MASK(A, BIT(4) | BIT(5)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)	/* I2C F SCL/SDA A4/A5 */
+ALTERNATE(PIN_MASK(B, BIT(3) | BIT(4)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)	/* I2C A SCL/SDA B3/B4 */
+ALTERNATE(PIN_MASK(C, BIT(1) | BIT(2)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)	/* I2C B SCL/SDA C1/C2 */
+ALTERNATE(PIN_MASK(E, BIT(0) | BIT(7)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)	/* I2C E SCL/SDA E0/E7 */
+ALTERNATE(PIN_MASK(C, BIT(7)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)	/* I2C C SCL C7 */
+ALTERNATE(PIN_MASK(F, BIT(7)), GPIO_ALT_FUNC_DEFAULT, MODULE_I2C, GPIO_FLAG_NONE)	/* I2C C SDA F7 */
+
+/* Alternate pins for UART */
+ALTERNATE(PIN_MASK(B, BIT(0) | BIT(1)), GPIO_ALT_FUNC_DEFAULT, MODULE_UART, GPIO_PULL_UP) /* UART1 B0/B1 */
+
+/* Alternate pins for ADC */
+ALTERNATE(PIN_MASK(I, BIT(1) | BIT(6)), GPIO_ALT_FUNC_DEFAULT, MODULE_ADC, GPIO_FLAG_NONE)	/* ADC 1,6 -> I1,I6 */
+ALTERNATE(PIN_MASK(L, BIT(0) | BIT(2)), GPIO_ALT_FUNC_DEFAULT, MODULE_ADC, GPIO_FLAG_NONE)	/* ADC 13,15 -> L0,L2 */
+
+/* Alternate pins for FAN */
+ALTERNATE(PIN_MASK(A, BIT(2)), GPIO_ALT_FUNC_DEFAULT, MODULE_PWM, GPIO_FLAG_NONE)	/* PWM2 A2 */
+ALTERNATE(PIN_MASK(D, BIT(7)), GPIO_ALT_FUNC_DEFAULT, MODULE_PWM, GPIO_FLAG_NONE)	/* TACH1A D7 */
diff --git a/util/flash_ec b/util/flash_ec
index 3aca26bba8..2b985e275d 100755
--- a/util/flash_ec
+++ b/util/flash_ec
@@ -54,6 +54,7 @@ BOARDS_IT83XX=(
 	reef_it8320
 	tglrvpu_ite
 	tglrvpy_ite
+	jslrvp_ite
 )
 
 BOARDS_STM32=(