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| author | Dino Li <Dino.Li@ite.com.tw> | 2020-08-14 11:08:55 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-08-14 13:39:26 +0000 |
| commit | a8ce3ace8d774c8902c5a600c15d5f971ef99742 (patch) | |
| tree | 6412fd0aa10705d88fd88745d9c003542855a0db | |
| parent | 12c0146bebec938fa3a790b55c2161bf6f4547ba (diff) | |
| download | chrome-ec-a8ce3ace8d774c8902c5a600c15d5f971ef99742.tar.gz | |
it83xx/adc: Enable automatic hardware calibration
We missed it when ADC accuracy initialization, let's fix it.
BUG=b:164011390
BRANCH=none
TEST=ADC accuracy is in +/- 4LSB.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Change-Id: Id40adbdc6823fbf3db506681ce4bff6a2f32b843
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2355166
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
Tested-by: Parker Lin <parkerlin@google.com>
| -rw-r--r-- | chip/it83xx/adc.c | 2 | ||||
| -rw-r--r-- | chip/it83xx/registers.h | 1 |
2 files changed, 3 insertions, 0 deletions
diff --git a/chip/it83xx/adc.c b/chip/it83xx/adc.c index ba5f70e27e..ec662b0490 100644 --- a/chip/it83xx/adc.c +++ b/chip/it83xx/adc.c @@ -308,6 +308,8 @@ static void adc_accuracy_initialization(void) { /* bit3 : start adc accuracy initialization */ IT83XX_ADC_ADCSTS |= 0x08; + /* Enable automatic HW calibration. */ + IT83XX_ADC_KDCTL |= IT83XX_ADC_AHCE; /* short delay for adc accuracy initialization */ IT83XX_GCTRL_WNCKR = 0; /* bit3 : stop adc accuracy initialization */ diff --git a/chip/it83xx/registers.h b/chip/it83xx/registers.h index be346c6153..f925691dab 100644 --- a/chip/it83xx/registers.h +++ b/chip/it83xx/registers.h @@ -1044,6 +1044,7 @@ enum clock_gate_offsets { #define IT83XX_ADC_ADCGCR REG8(IT83XX_ADC_BASE+0x03) #define IT83XX_ADC_VCH0CTL REG8(IT83XX_ADC_BASE+0x04) #define IT83XX_ADC_KDCTL REG8(IT83XX_ADC_BASE+0x05) +#define IT83XX_ADC_AHCE BIT(7) #define IT83XX_ADC_VCH1CTL REG8(IT83XX_ADC_BASE+0x06) #define IT83XX_ADC_VCH1DATL REG8(IT83XX_ADC_BASE+0x07) #define IT83XX_ADC_VCH1DATM REG8(IT83XX_ADC_BASE+0x08) |