diff options
| author | Scott Collyer <scollyer@google.com> | 2020-05-21 22:14:25 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-09-29 23:52:28 +0000 |
| commit | 77d86a6161e9388c48a607c654844ec2798a017d (patch) | |
| tree | 0a93971268d22101a7dc986da3bd7823e4feb2ba | |
| parent | 86f58bd95f42f1afad046ce65e5c68b7d813c8f5 (diff) | |
| download | chrome-ec-77d86a6161e9388c48a607c654844ec2798a017d.tar.gz | |
honeybuns: Increase flash size to work with RO only
We don't have enough flash space on to do a full RO + RW image. This
CL simply adjusts the flash size define from 128k to 256k and only the
RO image is only being used for development and HW verification.
Note also that at this stage there is no support for RO -> RW jump
other than using EC console command, so RO is the only image being
executed.
BUG=b:167462264
BRANCH=None
TEST=make -j BOARD=quiche is successful.
Signed-off-by: Scott Collyer <scollyer@google.com>
Change-Id: Iec062f9f3be966c0653cbdafe72f5a160351cf07
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2213839
Commit-Queue: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
| -rw-r--r-- | chip/stm32/config-stm32g41xb.h | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/chip/stm32/config-stm32g41xb.h b/chip/stm32/config-stm32g41xb.h index 1daca3c4a7..ab8642b9e6 100644 --- a/chip/stm32/config-stm32g41xb.h +++ b/chip/stm32/config-stm32g41xb.h @@ -16,7 +16,12 @@ * The minimum write size for STM32G4 is 8 bytes. Cros-EC does not support * PSTATE in single bank memories with a write size > 4 bytes. */ -#define CONFIG_FLASH_SIZE (128 * 1024) +/* + * TODO(b/167462264): This is a temporary change to allow for platform bringup + * without being constrained by flash space issue. Currently only using RO image + * flashed with STM32 debugger. + */ +#define CONFIG_FLASH_SIZE (256 * 1024) #define CONFIG_FLASH_WRITE_SIZE 0x0004 #define CONFIG_FLASH_BANK_SIZE (2 * 1024) #define CONFIG_FLASH_ERASE_SIZE CONFIG_FLASH_BANK_SIZE |