diff options
author | Ting Shen <phoenixshen@google.com> | 2020-08-20 18:07:51 +0800 |
---|---|---|
committer | Commit Bot <commit-bot@chromium.org> | 2020-08-25 07:15:43 +0000 |
commit | 9dafd43be882202d413a444a4e193bf5ffcae670 (patch) | |
tree | 83e3bd35d7b1fab67f6f809b6bcfea5886b75abd | |
parent | 6f4bb4c9f8f252d749ade2ab809a362e2072c5d6 (diff) | |
download | chrome-ec-9dafd43be882202d413a444a4e193bf5ffcae670.tar.gz |
asurada: implement ULP mode
Implemented ultra low power mode by pulling EN_SLP_Z, with a known
issue that reboot reason is not configured correctly before entering
hibernate.
BUG=b:162790592
TEST=manually
BRANCH=master
Signed-off-by: Ting Shen <phoenixshen@google.com>
Change-Id: Idbee7914fc261d74bdc70c2858befdfbd83c40e7
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2342986
Tested-by: Ting Shen <phoenixshen@chromium.org>
Commit-Queue: Ting Shen <phoenixshen@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
-rw-r--r-- | board/asurada/board.c | 17 | ||||
-rw-r--r-- | board/asurada/gpio.inc | 2 |
2 files changed, 18 insertions, 1 deletions
diff --git a/board/asurada/board.c b/board/asurada/board.c index 6fa4471291..f14cbeabbd 100644 --- a/board/asurada/board.c +++ b/board/asurada/board.c @@ -89,6 +89,23 @@ enum gpio_signal hibernate_wake_pins[] = { }; int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); +__override void board_hibernate_late(void) +{ + /* + * GPIO_EN_SLP_Z not implemented in rev0/1, + * fallback to usual hibernate process. + */ + if (board_get_version() <= 1) + return; + + isl9238c_hibernate(CHARGER_SOLO); + + gpio_set_level(GPIO_EN_SLP_Z, 1); + + /* should not reach here */ + __builtin_unreachable(); +} + /* power signal list. Must match order of enum power_signal. */ const struct power_signal_info power_signal_list[] = { {GPIO_PMIC_EC_PWRGD, POWER_SIGNAL_ACTIVE_HIGH, "PMIC_PWR_GOOD"}, diff --git a/board/asurada/gpio.inc b/board/asurada/gpio.inc index 37899122a6..c21324ba86 100644 --- a/board/asurada/gpio.inc +++ b/board/asurada/gpio.inc @@ -69,7 +69,7 @@ GPIO(EN_PP5000_A, PIN(C, 6), GPIO_OUT_HIGH) GPIO(PG_MT6315_PROC_ODL, PIN(E, 1), GPIO_INPUT) GPIO(PG_MT6360_ODL, PIN(F, 1), GPIO_INPUT) GPIO(PG_PP5000_A_ODL, PIN(A, 6), GPIO_INPUT) -GPIO(PMIC_FORCE_RESET, PIN(E, 3), GPIO_OUT_LOW | GPIO_SEL_1P8V) +GPIO(EN_SLP_Z, PIN(E, 3), GPIO_OUT_LOW) GPIO(SYS_RST_ODL, PIN(B, 6), GPIO_ODR_LOW) GPIO(EC_BL_EN_OD, PIN(B, 5), GPIO_ODR_LOW) |