diff options
| author | Keith Short <keithshort@chromium.org> | 2020-11-04 12:55:25 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-11-06 03:11:21 +0000 |
| commit | 2964489475b13ddd5ffae7023bd07ce3af65cc9e (patch) | |
| tree | 7640b98964d6ab4284ad0990f426de42b7f609bd | |
| parent | 2de0771d670e072e6a60973543f70318c1345d56 (diff) | |
| download | chrome-ec-2964489475b13ddd5ffae7023bd07ce3af65cc9e.tar.gz | |
trondo: remove board ID 0 checks
Board ID 0 checks were only used on the volteer reference board.
BUG=b:149858568
BRANCH=firmware-volteer-13521.B-master
TEST=make buildall
Signed-off-by: Keith Short <keithshort@chromium.org>
Change-Id: I91c949c74e455ee620b22c771a2c62341eba46a1
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2519965
Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
Commit-Queue: Abe Levkoy <alevkoy@chromium.org>
| -rw-r--r-- | board/trondo/gpio.inc | 18 |
1 files changed, 2 insertions, 16 deletions
diff --git a/board/trondo/gpio.inc b/board/trondo/gpio.inc index ffad6194ef..eee76df08b 100644 --- a/board/trondo/gpio.inc +++ b/board/trondo/gpio.inc @@ -43,13 +43,6 @@ GPIO_INT(USB_C1_MIX_INT_ODL, PIN(0, 3), GPIO_INT_BOTH, bc12_interrupt) /* Volume button interrupts */ GPIO_INT(EC_VOLDN_BTN_ODL, PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt) -/* - * EC_VOLUP_BTN_ODL moved from GPIO75 to GPIO97 on boards with board ID >=1. - * GPIO97/EN_PP1050_BYPASS is DNS on board ID 0, and GPIO75 will be used once - * EFS support is added. - * TODO (b/149858568): remove board ID=0 support. - */ -GPIO_INT(EC_VOLUP_BTN_ODL_BOARDID_0, PIN(7, 5), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt) GPIO_INT(EC_VOLUP_BTN_ODL, PIN(9, 7), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt) /* Power Sequencing Signals */ @@ -85,15 +78,7 @@ GPIO(SYS_RST_ODL, PIN(C, 5), GPIO_ODR_HIGH) GPIO(EC_PCH_INT_ODL, PIN(B, 0), GPIO_ODR_HIGH) /* USB and USBC Signals */ - -/* - * USB_C1 moved from GPIO32 to GPIO83 on boards with board ID >=1. - * GPIO83/EN_PP1800_A is DNS on board ID 0 and GPIO32 is N/C on board ID >=1 - * so it's safe to define GPIOs compatible with both designs. - * TODO (b/149858568): remove board ID=0 support. - */ -GPIO(USB_C1_RT_RST_ODL_BOARDID_0, PIN(3, 2), GPIO_ODR_LOW) /* USB_C1 Reset on boards without board ID */ -GPIO(USB_C1_RT_RST_ODL, PIN(8, 3), GPIO_ODR_LOW) /* USB_C1 Reset on boards board ID >=1 */ +GPIO(USB_C1_RT_RST_ODL, PIN(8, 3), GPIO_ODR_LOW) GPIO(USB_C0_OC_ODL, PIN(B, 1), GPIO_ODR_HIGH) GPIO(USB_C1_OC_ODL, PIN(5, 0), GPIO_ODR_HIGH) @@ -101,6 +86,7 @@ GPIO(USB_C1_OC_ODL, PIN(5, 0), GPIO_ODR_HIGH) UNIMPLEMENTED(USB_C1_LS_EN) /* Misc Signals */ +GPIO(EC_H1_PACKET_MODE, PIN(7, 5), GPIO_OUT_LOW) /* H1 Packet Mode */ /* * eDP backlight - both PCH and EC have enable pins that must be high |