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| author | Tzung-Bi Shih <tzungbi@chromium.org> | 2021-01-12 18:30:17 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-01-14 10:04:21 +0000 |
| commit | 0873122c27b50455b0618d7cf58a4e7cde4f2aef (patch) | |
| tree | b92d3d90709210a610d87fe54db8c9227b24e0ea | |
| parent | 45651535396a735de6e000e090eaf05d9d32c335 (diff) | |
| download | chrome-ec-0873122c27b50455b0618d7cf58a4e7cde4f2aef.tar.gz | |
chip/mt8192_scp: add memory barrier
Writing to SCP SYS (e.g. SCP_GIPC_IN_CLR) is asynchronous and is slower
than writing to CSR (e.g. CSR_VIC_MIEMS).
There is a race condition if writing to MIEMS before acknowledging to
interrupt sources. GVIC will re-latche interrupts wrongly.
Adds memory barrier between them. The issue is exposed when enabling
LTO because task_clear_pending_irq() will be inlined.
BRANCH=none
BUG=b:176959740
BUG=b:177289443
TEST=make BOARD=asurada_scp
Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org>
Change-Id: I5cbf94d3db08c051f360e927b52514041dba769d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2624369
Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
| -rw-r--r-- | chip/mt8192_scp/ipi.c | 1 | ||||
| -rw-r--r-- | chip/mt8192_scp/uart.c | 1 |
2 files changed, 2 insertions, 0 deletions
diff --git a/chip/mt8192_scp/ipi.c b/chip/mt8192_scp/ipi.c index fba511a642..39fcc09809 100644 --- a/chip/mt8192_scp/ipi.c +++ b/chip/mt8192_scp/ipi.c @@ -171,6 +171,7 @@ static void irq_group7_handler(void) if (SCP_GIPC_IN_SET & GIPC_IN(0)) { ipi_handler(); SCP_GIPC_IN_CLR = GIPC_IN(0); + asm volatile ("fence.i" ::: "memory"); task_clear_pending_irq(ec_int); } } diff --git a/chip/mt8192_scp/uart.c b/chip/mt8192_scp/uart.c index 8b9f7452ae..30708acaeb 100644 --- a/chip/mt8192_scp/uart.c +++ b/chip/mt8192_scp/uart.c @@ -148,6 +148,7 @@ static void uart_irq_handler(void) case UART_RX_IRQ(UARTN): uart_process(); SCP_CORE0_INTC_UART_RX_IRQ(UARTN) = BIT(0); + asm volatile ("fence.i" ::: "memory"); task_clear_pending_irq(ec_int); break; } |