diff options
author | Marius Schilder <mschilder@google.com> | 2017-10-18 22:58:34 -0700 |
---|---|---|
committer | chrome-bot <chrome-bot@chromium.org> | 2017-10-19 12:56:49 -0700 |
commit | de007979d37e2ad1ba7354df55fb267d858d5028 (patch) | |
tree | 21946a4cf0e4e0f77496a982ec446fbd75719523 | |
parent | 165f7d6f3bad4d49f977e1c5efad326f11007bf0 (diff) | |
download | chrome-ec-de007979d37e2ad1ba7354df55fb267d858d5028.tar.gz |
MN50: delete
Project moved to private-cr53/
BUG=none
BRANCH=none
TEST=compiles
Change-Id: I30f99678f8b572030f565bcf3a31ca0f00babebc
Reviewed-on: https://chromium-review.googlesource.com/727660
Commit-Ready: Marius Schilder <mschilder@chromium.org>
Tested-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Marius Schilder <mschilder@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
-rw-r--r-- | board/mn50/board.c | 456 | ||||
-rw-r--r-- | board/mn50/board.h | 192 | ||||
-rw-r--r-- | board/mn50/build.mk | 55 | ||||
-rw-r--r-- | board/mn50/ec.tasklist | 21 | ||||
-rw-r--r-- | board/mn50/gpio.inc | 124 | ||||
-rw-r--r-- | board/mn50/signing.c | 201 | ||||
-rw-r--r-- | board/mn50/signing.h | 73 | ||||
-rw-r--r-- | board/mn50/usb_spi.c | 94 |
8 files changed, 0 insertions, 1216 deletions
diff --git a/board/mn50/board.c b/board/mn50/board.c deleted file mode 100644 index 302a7d5296..0000000000 --- a/board/mn50/board.c +++ /dev/null @@ -1,456 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include <endian.h> - -#include "case_closed_debug.h" -#include "clock.h" -#include "common.h" -#include "console.h" -#include "dcrypto/dcrypto.h" -#include "ec_version.h" -#include "extension.h" -#include "flash.h" -#include "flash_config.h" -#include "gpio.h" -#include "hooks.h" -#include "i2c.h" -#include "ina2xx.h" -#include "init_chip.h" -#include "nvmem.h" -#include "nvmem_vars.h" -#include "registers.h" -#include "signed_header.h" -#include "signing.h" -#include "spi.h" -#include "system.h" -#include "task.h" -#include "trng.h" -#include "uartn.h" -#include "usb_api.h" -#include "usb_console.h" -#include "usb_descriptor.h" -#include "usb_hid.h" -#include "usb_spi.h" -#include "usb_i2c.h" -#include "util.h" - -/* Define interrupt and gpio structs */ -#include "gpio_list.h" - -#include "cryptoc/sha.h" - -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) - -/* NvMem user buffer lengths table */ -uint32_t nvmem_user_sizes[NVMEM_NUM_USERS] = { - NVMEM_CR50_SIZE -}; - -/* I2C Port definition. No GPIO access. */ -const struct i2c_port_t i2c_ports[] = { - {"master", I2C_PORT_MASTER, 100, 0, 0}, -}; -const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports); - -/* Recall whether we have enable socket power. */ -static int socket_set_enabled; - -/*****************************************************************************/ - -#include "gpio.wrap" - -static void init_interrupts(void) -{ - int i; - uint32_t exiten = GREG32(PINMUX, EXITEN0); - - /* Clear wake pin interrupts */ - GREG32(PINMUX, EXITEN0) = 0; - GREG32(PINMUX, EXITEN0) = exiten; - - /* Enable all GPIO interrupts */ - for (i = 0; i < gpio_ih_count; i++) - if (gpio_list[i].flags & GPIO_INT_ANY) - gpio_enable_interrupt(i); -} - -void decrement_retry_counter(void) -{ - uint32_t counter = GREG32(PMU, LONG_LIFE_SCRATCH0); - - if (counter) { - GWRITE_FIELD(PMU, LONG_LIFE_SCRATCH_WR_EN, REG0, 1); - GREG32(PMU, LONG_LIFE_SCRATCH0) = counter - 1; - GWRITE_FIELD(PMU, LONG_LIFE_SCRATCH_WR_EN, REG0, 0); - } -} - -void ccd_phy_init(void) -{ - usb_select_phy(USB_SEL_PHY1); - - usb_init(); -} - -void usb_i2c_board_disable(void) -{ -} - -int usb_i2c_board_enable(void) -{ - return EC_SUCCESS; -} - -int usb_i2c_board_is_enabled(void) -{ - return 1; -} - -USB_SPI_CONFIG(ccd_usb_spi, USB_IFACE_SPI, USB_EP_SPI); - -/* Initialize board. */ -static void board_init(void) -{ - /* - * Deep sleep resets should be considered valid and should not impact - * the rolling reboot count. - */ - if (system_get_reset_flags() & RESET_FLAG_HIBERNATE) - decrement_retry_counter(); - init_interrupts(); - init_trng(); - init_jittery_clock(1); - init_runlevel(PERMISSION_MEDIUM); - /* Initialize NvMem partitions */ - nvmem_init(); - /* Initialize the persistent storage. */ - initvars(); - - /* Disable all power to socket, for hot swapping. */ - disable_socket(); - - /* Indication that firmware is running, for debug purposes. */ - GREG32(PMU, PWRDN_SCRATCH16) = 0xCAFECAFE; - - /* Enable USB / CCD */ - usb_release(); - usb_console_enable(1, 0); - ccd_phy_init(); - - /* Calibrate INA0 (VBUS) with 1mA/LSB scale */ - i2cm_init(); - ina2xx_init(0, 0x8000, INA2XX_CALIB_1MA(150 /*mOhm*/)); - ina2xx_init(1, 0x8000, INA2XX_CALIB_1MA(150 /*mOhm*/)); - ina2xx_init(4, 0x8000, INA2XX_CALIB_1MA(150 /*mOhm*/)); -} -DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT); - -int ccd_ext_is_enabled(void) -{ - return 1; -} - -const void * const usb_strings[] = { - [USB_STR_DESC] = usb_string_desc, - [USB_STR_VENDOR] = USB_STRING_DESC("Google Inc."), - [USB_STR_PRODUCT] = USB_STRING_DESC("Mn50"), - [USB_STR_VERSION] = USB_STRING_DESC(CROS_EC_VERSION32), - [USB_STR_CONSOLE_NAME] = USB_STRING_DESC("Shell"), - [USB_STR_BLOB_NAME] = USB_STRING_DESC("Blob"), - [USB_STR_AP_NAME] = USB_STRING_DESC("DUT UART"), - [USB_STR_UPGRADE_NAME] = USB_STRING_DESC("Firmware upgrade"), - [USB_STR_SPI_NAME] = USB_STRING_DESC("SPI"), - [USB_STR_SERIALNO] = USB_STRING_DESC(DEFAULT_SERIALNO), - [USB_STR_I2C_NAME] = USB_STRING_DESC("I2C"), -}; -BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT); - -/* SPI devices */ -/* port 0, 40MHz / (16 + 1) = 2.3MHz SPI, no soft CS */ -const struct spi_device_t spi_devices[] = { - [CONFIG_SPI_FLASH_PORT] = {0, 16, GPIO_COUNT} -}; -const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices); - -int flash_regions_to_enable(struct g_flash_region *regions, - int max_regions) -{ - /* - * This needs to account for two regions: the "other" RW partition and - * the NVRAM in TOP_B. - * - * When running from RW_A the two regions are adjacent, but it is - * simpler to keep function logic the same and always configure two - * separate regions. - */ - - if (max_regions < 3) - return 0; - - /* Enable access to the other RW image... */ - if (system_get_image_copy() == SYSTEM_IMAGE_RW) - /* Running RW_A, enable RW_B */ - regions[0].reg_base = CONFIG_MAPPED_STORAGE_BASE + - CONFIG_RW_B_MEM_OFF; - else - /* Running RW_B, enable RW_A */ - regions[0].reg_base = CONFIG_MAPPED_STORAGE_BASE + - CONFIG_RW_MEM_OFF; - /* Size is the same */ - regions[0].reg_size = CONFIG_RW_SIZE; - regions[0].reg_perms = FLASH_REGION_EN_ALL; - - /* Enable access to the NVRAM partition A region */ - regions[1].reg_base = CONFIG_MAPPED_STORAGE_BASE + - CONFIG_FLASH_NVMEM_OFFSET_A; - regions[1].reg_size = NVMEM_PARTITION_SIZE; - regions[1].reg_perms = FLASH_REGION_EN_ALL; - - /* Enable access to the NVRAM partition B region */ - regions[2].reg_base = CONFIG_MAPPED_STORAGE_BASE + - CONFIG_FLASH_NVMEM_OFFSET_B; - regions[2].reg_size = NVMEM_PARTITION_SIZE; - regions[2].reg_perms = FLASH_REGION_EN_ALL; - - return 3; -} - -/* Check if socket has been anabled and power is OK. */ -int is_socket_enabled(void) -{ - /* TODO: check voltage rails within approved bands. */ - return (gpio_get_level(GPIO_DUT_PWRGOOD) && socket_set_enabled); -} - -/* Determine whether the socket has no voltage. TODO: check GPIOS? */ -int is_socket_off(void) -{ - /* Check 3.3v = 0. */ - if (ina2xx_get_voltage(1) > 10) - return 0; - /* Check 2.6v = 0. */ - if (ina2xx_get_voltage(4) > 10) - return 0; - return 1; -} - -void enable_socket(void) -{ - /* Power up. */ - gpio_set_level(GPIO_DUT_PWR_EN, 1); - - /* Indicate socket powered with red LED. */ - gpio_set_level(GPIO_LED_L, 0); - - /* GPIOs as ioutputs. */ - gpio_set_flags(GPIO_DUT_RST_L, GPIO_OUT_LOW); - gpio_set_flags(GPIO_DUT_BOOT_CFG, GPIO_OUT_LOW); - gpio_set_flags(GPIO_SPI_CS_ALT_L, GPIO_OUT_HIGH); - - /* Connect DIO A4, A8 to the SPI peripheral */ - GWRITE(PINMUX, DIOA4_SEL, 0); /* SPI_MOSI */ - GWRITE(PINMUX, DIOA8_SEL, 0); /* SPI_CLK */ - GWRITE(PINMUX, DIOA5_SEL, GC_PINMUX_GPIO0_GPIO10_SEL); - - /* UART */ - GWRITE(PINMUX, DIOA7_SEL, GC_PINMUX_UART1_TX_SEL); - GWRITE(PINMUX, DIOA3_SEL, GC_PINMUX_UART1_RX_SEL); - GWRITE_FIELD(PINMUX, DIOA3_CTL, PU, 1); - uartn_enable(UART_AP); - - /* Chip select. */ - GWRITE_FIELD(PINMUX, DIOA5_CTL, PU, 1); - - socket_set_enabled = 1; -} - -void disable_socket(void) -{ - /* Disable CS pin. */ - GWRITE_FIELD(PINMUX, DIOA5_CTL, PU, 0); - - /* TODO: Implement way to get the gpio */ - ASSERT(GREAD(PINMUX, GPIO0_GPIO7_SEL) == GC_PINMUX_DIOA4_SEL); - ASSERT(GREAD(PINMUX, GPIO0_GPIO8_SEL) == GC_PINMUX_DIOA8_SEL); - ASSERT(GREAD(PINMUX, GPIO0_GPIO10_SEL) == GC_PINMUX_DIOA5_SEL); - - /* Set SPI MOSI, CLK, and CS_L as inputs */ - GWRITE(PINMUX, DIOA4_SEL, GC_PINMUX_GPIO0_GPIO7_SEL); - GWRITE(PINMUX, DIOA8_SEL, GC_PINMUX_GPIO0_GPIO8_SEL); - GWRITE(PINMUX, DIOA5_SEL, GC_PINMUX_GPIO0_GPIO10_SEL); - - /* UART */ - uartn_disable(UART_AP); - GWRITE(PINMUX, DIOA7_SEL, 0); - GWRITE(PINMUX, DIOA3_SEL, 0); - GWRITE_FIELD(PINMUX, DIOA3_CTL, PU, 0); - - /* GPIOs as inputs. */ - gpio_set_flags(GPIO_DUT_BOOT_CFG, GPIO_INPUT); - gpio_set_flags(GPIO_DUT_RST_L, GPIO_INPUT); - gpio_set_flags(GPIO_SPI_CS_ALT_L, GPIO_INPUT); - - /* Turn off socket power. */ - gpio_set_level(GPIO_DUT_PWR_EN, 0); - - /* Indicate socket unpowered with no red LED. */ - gpio_set_level(GPIO_LED_L, 1); - socket_set_enabled = 0; -} - -static int command_socket(int argc, char **argv) -{ - if (argc > 1) { - if (!strcasecmp("enable", argv[1])) - enable_socket(); - else if (!strcasecmp("disable", argv[1])) - disable_socket(); - else - return EC_ERROR_PARAM1; - - /* Let power settle. */ - msleep(5); - } - - ccprintf("Socket enabled: %s, powered: %s\n", - is_socket_enabled() ? "yes" : "no", - is_socket_off() ? "off" : "on"); - return EC_SUCCESS; -} -DECLARE_SAFE_CONSOLE_COMMAND(socket, command_socket, - "[enable|disable]", - "Activate and deactivate socket"); - -#ifdef CONFIG_STREAM_SIGNATURE -/* - * This command allows signing the contents of a data stream that passes - * through mn50/scribe. This allows critical segments of SPI readouts, - * including the haven personalization data to be verified on the server - * side as coming from a registered scribe board. (go/haven-registration) - * - * The actual interface enables capturing data (start command) on a stream - * (either SPI or UART), until stopped (sign command), at which point a - * signature is printed to the console. An "append" command is available - * to manually insert characters for testing, and should be disabled - * before release. - */ -static int command_signer(int argc, char **argv) -{ - static int initted; /* = 0; */ - char *data; - - if (!initted) { - init_signing(); - initted = 1; - } - - if (argc > 2) { - enum stream_id id; - - if (!strcasecmp("spi", argv[1])) - id = stream_spi; - else if (!strcasecmp("uart", argv[1])) - id = stream_uart; - else - return EC_ERROR_PARAM1; - - if (!strcasecmp("sign", argv[2])) { - if (argc == 3) - return sig_sign(id); - else - return EC_ERROR_PARAM3; - } else if (!strcasecmp("start", argv[2])) { - if (argc == 3) - return sig_start(id); - else - return EC_ERROR_PARAM3; - } else if (!strcasecmp("append", argv[2])) { - if (argc == 4) { - data = argv[3]; - return sig_append(id, data, strlen(data)); - } else - return EC_ERROR_PARAM3; - } else - return EC_ERROR_PARAM2; - } else - return EC_ERROR_PARAM1; - - return EC_SUCCESS; -} -DECLARE_SAFE_CONSOLE_COMMAND(signer, command_signer, - "[spi|uart] [start|append|sign] data", - "Sign data"); -#endif - -void post_reboot_request(void) -{ - /* This will never return. */ - system_reset(SYSTEM_RESET_MANUALLY_TRIGGERED | SYSTEM_RESET_HARD); -} - -/* Determine key type based on the key ID. */ -static const char *key_type(uint32_t key_id) -{ - - /* - * It is a mere convention, but all prod keys are required to have key - * IDs such, that bit D2 is set, and all dev keys are required to have - * key IDs such, that bit D2 is not set. - * - * This convention is enforced at the key generation time. - */ - if (key_id & (1 << 2)) - return "prod"; - else - return "dev"; -} - -static int command_sysinfo(int argc, char **argv) -{ - enum system_image_copy_t active; - uintptr_t vaddr; - const struct SignedHeader *h; - - ccprintf("Reset flags: 0x%08x (", system_get_reset_flags()); - system_print_reset_flags(); - ccprintf(")\n"); - - ccprintf("Chip: %s %s %s\n", system_get_chip_vendor(), - system_get_chip_name(), system_get_chip_revision()); - - active = system_get_ro_image_copy(); - vaddr = get_program_memory_addr(active); - h = (const struct SignedHeader *)vaddr; - ccprintf("RO keyid: 0x%08x(%s)\n", h->keyid, key_type(h->keyid)); - - active = system_get_image_copy(); - vaddr = get_program_memory_addr(active); - h = (const struct SignedHeader *)vaddr; - ccprintf("RW keyid: 0x%08x(%s)\n", h->keyid, key_type(h->keyid)); - - ccprintf("DEV_ID: 0x%08x 0x%08x\n", - GREG32(FUSE, DEV_ID0), GREG32(FUSE, DEV_ID1)); - - return EC_SUCCESS; -} -DECLARE_SAFE_CONSOLE_COMMAND(sysinfo, command_sysinfo, - NULL, - "Print system info"); - -/* - * SysInfo command: - * There are no input args. - * Output is this struct, all fields in network order. - */ -struct sysinfo_s { - uint32_t ro_keyid; - uint32_t rw_keyid; - uint32_t dev_id0; - uint32_t dev_id1; -} __packed; - - - diff --git a/board/mn50/board.h b/board/mn50/board.h deleted file mode 100644 index fd63a10ff9..0000000000 --- a/board/mn50/board.h +++ /dev/null @@ -1,192 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#ifndef __CROS_EC_BOARD_H -#define __CROS_EC_BOARD_H - -/* - * Make sure we don't trigger the watchdog accidentally if the timing - * is just a little off. - */ -#undef CONFIG_WATCHDOG_PERIOD_MS -#define CONFIG_WATCHDOG_PERIOD_MS 5000 - -#ifndef CR50_DEV -#define CR50_DEV 1 -#endif - -/* Features that we don't want */ -#undef CONFIG_CMD_LID_ANGLE -#undef CONFIG_CMD_POWERINDEBUG -#undef CONFIG_DMA_DEFAULT_HANDLERS -#undef CONFIG_FMAP -#undef CONFIG_HIBERNATE -#undef CONFIG_LID_SWITCH -#undef CONFIG_CMD_SYSINFO -#undef CONFIG_CMD_SYSJUMP -#undef CONFIG_CMD_SYSLOCK - -#ifndef CR50_DEV -/* Disable stuff that should only be in debug builds */ -#undef CONFIG_CMD_MD -#undef CONFIG_CMD_RW -#undef CONFIG_CMD_SLEEPMASK -#undef CONFIG_CMD_WAITMS -#undef CONFIG_FLASH -#endif - -/* Flash configuration */ -#undef CONFIG_FLASH_PSTATE -/* TODO(crosbug.com/p/44745): Bringup only! Do the right thing for real! */ -#define CONFIG_WP_ALWAYS -/* TODO(crosbug.com/p/44745): For debugging only */ -#define CONFIG_CMD_FLASH - -/* We're using TOP_A for partition 0, TOP_B for partition 1 */ -#define CONFIG_FLASH_NVMEM -/* Offset to start of NvMem area from base of flash */ -#define CONFIG_FLASH_NVMEM_OFFSET_A (CFG_TOP_A_OFF) -#define CONFIG_FLASH_NVMEM_OFFSET_B (CFG_TOP_B_OFF) -/* Address of start of Nvmem area */ -#define CONFIG_FLASH_NVMEM_BASE_A (CONFIG_PROGRAM_MEMORY_BASE + \ - CONFIG_FLASH_NVMEM_OFFSET_A) -#define CONFIG_FLASH_NVMEM_BASE_B (CONFIG_PROGRAM_MEMORY_BASE + \ - CONFIG_FLASH_NVMEM_OFFSET_B) -/* Size partition in NvMem */ -#define NVMEM_PARTITION_SIZE CFG_TOP_SIZE -/* Size in bytes of NvMem area */ -#define CONFIG_FLASH_NVMEM_SIZE (CFG_TOP_SIZE * NVMEM_NUM_PARTITIONS) -/* Enable <key, value> variable support. */ -#define CONFIG_FLASH_NVMEM_VARS -#define NVMEM_CR50_SIZE 272 -#define CONFIG_FLASH_NVMEM_VARS_USER_SIZE NVMEM_CR50_SIZE - -/* Allow multiple concurrent memory allocations. */ -#define CONFIG_MALLOC - -/* USB configuration */ -#define CONFIG_USB -#define CONFIG_USB_CONSOLE -#define CONFIG_USB_I2C -#define CONFIG_USB_INHIBIT_INIT -#define CONFIG_USB_SELECT_PHY -#define CONFIG_USB_SPI -#define CONFIG_USB_SERIALNO -#define DEFAULT_SERIALNO "0" -#define CONFIG_CMD_GPIO_EXTENDED - -#define CONFIG_STREAM_USART -#define CONFIG_STREAM_USB -#define CONFIG_STREAM_USART1 -#define CONFIG_STREAM_SIGNATURE - -#define CONFIG_USB_PID 0x502a -#define CONFIG_USB_SELF_POWERED - -#undef CONFIG_USB_MAXPOWER_MA -#define CONFIG_USB_MAXPOWER_MA 0 - -/* Enable SPI Master (SPI) module */ -#define CONFIG_SPI_MASTER -#define CONFIG_SPI_MASTER_NO_CS_GPIOS -#define CONFIG_SPI_MASTER_CONFIGURE_GPIOS -#define CONFIG_SPI_FLASH_PORT 0 - -/* We don't need to send events to the AP */ -#undef CONFIG_HOSTCMD_EVENTS - -#define CONFIG_CONSOLE_COMMAND_FLAGS - -/* Include crypto stuff, both software and hardware. */ -#define CONFIG_DCRYPTO -#define CONFIG_UPTO_SHA512 - -#ifndef __ASSEMBLER__ - -#include "gpio_signal.h" - -/* USB string indexes */ -enum usb_strings { - USB_STR_DESC = 0, - USB_STR_VENDOR, - USB_STR_PRODUCT, - USB_STR_VERSION, - USB_STR_CONSOLE_NAME, - USB_STR_BLOB_NAME, - USB_STR_HID_KEYBOARD_NAME, - USB_STR_AP_NAME, - USB_STR_UPGRADE_NAME, - USB_STR_SPI_NAME, - USB_STR_SERIALNO, - USB_STR_I2C_NAME, - - USB_STR_COUNT -}; - -void post_reboot_request(void); -void ccd_force_enable(void); -void disable_socket(void); -void enable_socket(void); -int is_socket_enabled(void); -int is_socket_off(void); - -#endif /* !__ASSEMBLER__ */ - -/* USB interface indexes (use define rather than enum to expand them) */ -#define USB_IFACE_CONSOLE 0 -#define USB_IFACE_AP 1 -#define USB_IFACE_UPGRADE 2 -#define USB_IFACE_SPI 3 -#define USB_IFACE_I2C 4 -#define USB_IFACE_COUNT 5 - -/* USB endpoint indexes (use define rather than enum to expand them) */ -#define USB_EP_CONTROL 0 -#define USB_EP_CONSOLE 1 -#define USB_EP_AP 2 -#define USB_EP_UPGRADE 3 -#define USB_EP_SPI 4 -#define USB_EP_I2C 5 -#define USB_EP_COUNT 6 - -/* UART indexes (use define rather than enum to expand them) */ -#define UART_CR50 0 -#define UART_AP 1 - -#define UARTN UART_CR50 - -/* TODO(crosbug.com/p/56540): Remove this when UART0_RX works everywhere */ -#define GC_UART0_RX_DISABLE - -#define CC_DEFAULT (CC_ALL & ~CC_MASK(CC_TPM)) - -/* Nv Memory users */ -#ifndef __ASSEMBLER__ -enum nvmem_users { - NVMEM_CR50 = 0, - NVMEM_NUM_USERS -}; -#endif - -#define CONFIG_FLASH_NVMEM_VARS_USER_NUM NVMEM_CR50 - -/* - * Let's be on the lookout for stack overflow, while debugging. - * - * TODO(vbendeb): remove this before finalizing the code. - */ -#define CONFIG_DEBUG_STACK_OVERFLOW -#define CONFIG_RW_B - -/* Firmware upgrade options. */ -#define CONFIG_NON_HC_FW_UPDATE -#define CONFIG_USB_FW_UPDATE - -#define CONFIG_I2C -#define CONFIG_I2C_MASTER -#define I2C_PORT_MASTER 0 -#define CONFIG_INA231 - -#endif /* __CROS_EC_BOARD_H */ diff --git a/board/mn50/build.mk b/board/mn50/build.mk deleted file mode 100644 index ca5cc90a74..0000000000 --- a/board/mn50/build.mk +++ /dev/null @@ -1,55 +0,0 @@ -# -*- makefile -*- -# Copyright 2017 The Chromium OS Authors. All rights reserved. -# Use of this source code is governed by a BSD-style license that can be -# found in the LICENSE file. -# -# Board-specific build requirements - -# Define the SoC used by this board -CHIP:=g -CHIP_FAMILY:=cr50 - -# This file is included twice by the Makefile, once to determine the CHIP info -# and then again after defining all the CONFIG_ and HAS_TASK variables. We use -# a guard so that recipe definitions and variable extensions only happen the -# second time. -ifeq ($(BOARD_MK_INCLUDED_ONCE),) -BOARD_MK_INCLUDED_ONCE=1 -SIG_EXTRA = --cros -else - -# Need to generate a .hex file -all: hex - -# The simulator components have their own subdirectory -CFLAGS += -I$(realpath chip/$(CHIP)/dcrypto) -dirs-y += chip/$(CHIP)/dcrypto - -# Objects that we need to build -board-y = board.o -board-${CONFIG_STREAM_SIGNATURE} += signing.o -board-${CONFIG_USB_SPI} += usb_spi.o - -INCLUDE_ROOT := $(abspath ./include) -CFLAGS += -I$(INCLUDE_ROOT) -CPPFLAGS += -I$(abspath ./builtin) -CPPFLAGS += -I$(abspath ./chip/$(CHIP)) -# For core includes -CPPFLAGS += -I$(abspath .) -CPPFLAGS += -I$(abspath $(BDIR)) -CPPFLAGS += -I$(abspath ./test) -ifeq ($(CONFIG_UPTO_SHA512),y) -CPPFLAGS += -DSHA512_SUPPORT -endif - -# Make sure the context of the software sha512 implementation fits. If it ever -# increases, a compile time assert will fire in tpm2/hash.c. -ifeq ($(CONFIG_UPTO_SHA512),y) -CFLAGS += -DUSER_MIN_HASH_STATE_SIZE=208 -else -CFLAGS += -DUSER_MIN_HASH_STATE_SIZE=112 -endif -# Configure cryptoc headers to handle unaligned accesses. -CFLAGS += -DSUPPORT_UNALIGNED=1 - -endif # BOARD_MK_INCLUDED_ONCE is nonempty diff --git a/board/mn50/ec.tasklist b/board/mn50/ec.tasklist deleted file mode 100644 index d831b1a1ad..0000000000 --- a/board/mn50/ec.tasklist +++ /dev/null @@ -1,21 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/** - * List of enabled tasks in the priority order - * - * The first one has the lowest priority. - * - * For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and - * TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries, - * where : - * 'n' in the name of the task - * 'r' in the main routine of the task - * 'd' in an opaque parameter passed to the routine at startup - * 's' is the stack size in bytes; must be a multiple of 8 - */ -#define CONFIG_TASK_LIST \ - TASK_ALWAYS(HOOKS, hook_task, NULL, CONFIG_STACK_SIZE) \ - TASK_ALWAYS(CONSOLE, console_task, NULL, 8192) diff --git a/board/mn50/gpio.inc b/board/mn50/gpio.inc deleted file mode 100644 index 069d57bcfb..0000000000 --- a/board/mn50/gpio.inc +++ /dev/null @@ -1,124 +0,0 @@ -/* -*- mode:c -*- - * Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* - * This file describes GPIO mapping for the cr50 code running on the H1 chip. - * - * For the purposes of this file H1 core has the following logical and - * physical items and properties: - * - * - 32 internal GPIOs, which are split into two ports of 16 bits each. - * Ports' architecture and programmig is described in "ARM Cortex-M System - * Design Kit TRM" DDIO47B. - * - * - a set of peripherals - slave and master SPI and I2C controllers, UARTs, - * interrupt controller, etc. - * - * - 28 pins on the package named DIOA0..14, DIOB0..7 and DIOM0..4 - * - * - a PINMUX - a unit which allows to interconnect objects from the three - * groups listed above. Note that some peripherals are attached to some - * pins directly, so in case those peripherals are used the pins should - * not be connected by PINMUX to any other outputs. - * - * The below macros are somewhat misleading (apparently for historical - * reasons), as PIN(p, b) component in fact refers not to the external pin, - * but to the GPIO (bit b on port p), where bit is in 0..15 range, and port is - * in 0..1 range. - * - * To describe routing of an external signal two macro instantiations are - * required: - * - * The GPIO_INT() or GPIO() macro assigns the signal a name and assigns it to - * the internal GPIO port, (again, defining the port using the PIN(port, bit) - * component of the macro invocation). GPIO_INT definitions assign their - * respective signals to interrupts and ISRs. - * - * The PINMUX macro assigns the previously defined GPIO to another object, - * most commonly to an external pin, but possibly to some internal component. - */ - -/* Declare symbolic names for all the GPIOs that we care about. - * Note: Those with interrupt handlers must be declared first. */ - - -/* Use these to reset/flash the DUT haven */ -GPIO(DUT_PWR_EN, PIN(0, 2), GPIO_OUT_LOW) /* DIOB5 */ -GPIO(DUT_PWRGOOD, PIN(0, 3), GPIO_INPUT) /* DIOB7 */ -/* These GPIOS are switched between input/output by socket enable. */ -GPIO(DUT_BOOT_CFG, PIN(0, 0), GPIO_OUT_LOW) /* DIOB2 */ -GPIO(DUT_RST_L, PIN(0, 1), GPIO_OUT_LOW) /* DIOB3 */ - -GPIO(LED_B_L, PIN(0, 4), GPIO_ODR_HIGH) /* DIOA9 */ -GPIO(LED_R_L, PIN(0, 5), GPIO_ODR_HIGH) /* DIOA13 */ -GPIO(LED_G_L, PIN(0, 6), GPIO_ODR_HIGH) /* DIOA14 */ -GPIO(LED_L, PIN(0, 11), GPIO_ODR_HIGH) /* DIOB6 */ - -/* GPIOs used to tristate the SPI bus */ -GPIO(SPI_MOSI, PIN(0, 7), GPIO_INPUT) /* DIOA4 */ -GPIO(SPI_CLK, PIN(0, 8), GPIO_INPUT) /* DIOA8 */ -GPIO(SPI_CS_L, PIN(0, 9), GPIO_INPUT) /* DIOA14 */ -GPIO(SPI_CS_ALT_L, PIN(0, 10), GPIO_INPUT) /* DIOA5 */ - -/* Unimplemented signals which we need to emulate for now */ -/* TODO(wfrichar): Half the boards don't use this signal. Take it out. */ -UNIMPLEMENTED(ENTERING_RW) - -/* - * If we are included by generic GPIO code that doesn't know about the PINMUX - * macro we need to provide an empty definition so that the invocations don't - * interfere with other GPIO processing. - */ -#ifndef PINMUX -#define PINMUX(...) -#endif - -/* GPIOs - mark outputs as inputs too, to read back from the driven pad */ -PINMUX(GPIO(DUT_BOOT_CFG), B2, DIO_INPUT) -PINMUX(GPIO(DUT_RST_L), B3, DIO_INPUT) -PINMUX(GPIO(DUT_PWR_EN), B5, DIO_INPUT) -PINMUX(GPIO(DUT_PWRGOOD), B7, DIO_INPUT) - -PINMUX(GPIO(LED_B_L), A9, DIO_INPUT) -PINMUX(GPIO(LED_R_L), A13, DIO_INPUT) -PINMUX(GPIO(LED_G_L), A14, DIO_INPUT) -PINMUX(GPIO(LED_L), B6, DIO_INPUT) - -/* UARTs */ -PINMUX(FUNC(UART0_TX), A0, DIO_OUTPUT) /* Cr50 console */ -PINMUX(FUNC(UART0_RX), A1, DIO_INPUT | DIO_WAKE_LOW) - -/* - * UART1_TX will be enabled when the socket power is enabled, - * to prevent backpowering. - * - * PINMUX(FUNC(UART1_TX), A7, DIO_OUTPUT) - */ - -/* DUT console */ -PINMUX(FUNC(UART1_RX), A3, DIO_INPUT) - -/* I2C setup */ -PINMUX(FUNC(I2C0_SCL), B0, DIO_INPUT | DIO_OUTPUT) -PINMUX(FUNC(I2C0_SDA), B1, DIO_INPUT | DIO_OUTPUT) - -/* - * Both SPI master and slave buses are wired directly to specific pads - * - * If CONFIG_SPI_MASTER is defined, these pads are used: - * DIOA4 = SPI_MOSI (output) - * DIOA8 = SPI_CLK (output) - * DIOA11 = SPI_MISO (input) - * DIOA14 = SPI_CS_L (output) - mn50 doesn't use HS CS implementation. - * The pads are only connected to the peripheral outputs when SPI is enabled to - * avoid interfering with other things on the board. - * Note: Double-check to be sure these are configured in spi_master.c - */ -PINMUX(GPIO(SPI_MOSI), A4, DIO_OUTPUT) -PINMUX(GPIO(SPI_CLK), A8, DIO_OUTPUT) -PINMUX(GPIO(SPI_CS_ALT_L), A5, DIO_OUTPUT) - -#undef PINMUX diff --git a/board/mn50/signing.c b/board/mn50/signing.c deleted file mode 100644 index ca61f59a9d..0000000000 --- a/board/mn50/signing.c +++ /dev/null @@ -1,201 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - - -#include "common.h" -#include "console.h" -#include "dcrypto/dcrypto.h" -#include "signing.h" -#include "task.h" - -#include "cryptoc/sha.h" - -#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) -#define fail() cprints(CC_SYSTEM, "FAIL: %s:%d", __FILE__, __LINE__) - -static p256_int x, y, d; - -static HASH_CTX sig_sha[stream_count]; - -enum signer_states { - state_notready = 0, - state_ready, - state_started, -}; - -/* Current state of each signer stream. */ -static int signer_state[stream_count]; - -/* Bytes ingested into the hash so far. */ -static int signer_bytes[stream_count]; - -/* Human readable name of each stream. */ -static const char *signer_name[stream_count] = { - "spi", "uart" -}; - -void init_signing(void) -{ - /* Add this enum to dcrypto.h */ - enum dcrypto_appid appid = PERSO_AUTH; - struct APPKEY_CTX ctx; - uint32_t key_bytes[8]; - const uint32_t PERSO_SALT[8] = {0xd00d1e, 0xba0, 0xc0ffee}; - - /* - * Initialize signing key - */ - if (!DCRYPTO_appkey_init(appid, &ctx)) - fail(); - if (!DCRYPTO_appkey_derive(appid, PERSO_SALT, key_bytes)) - fail(); - if (!DCRYPTO_p256_key_from_bytes(&x, &y, &d, - (const uint8_t *)key_bytes)) - fail(); - - /* (x,y) = pubkey, d = privkey */ - signer_state[stream_uart] = state_ready; - signer_state[stream_spi] = state_ready; -} - -/* - * Start collecting data into a hash to be signed. - * stream_id can be either stream_uart or stream_spi. - */ -int sig_start(enum stream_id id) -{ - if ((id < 0) || (id >= stream_count)) - return EC_ERROR_PARAM1; - - if (signer_state[id] != state_ready) { - CPRINTS("Signer %d not ready", id); - return EC_ERROR_INVAL; - } - - /* Zero the hash. */ - DCRYPTO_SHA256_init(&sig_sha[id], 0); - signer_bytes[id] = 0; - signer_state[id] = state_started; - - return EC_SUCCESS; -} - -/* - * Append data into this stream's hash for future signing. - * This function is called inline with data receive, from the UART rx code - * or the SPI rx code. - * - * This can be called any time, but only hashes data when the stream - * capture is started. - */ -int sig_append(enum stream_id id, const uint8_t *data, size_t data_len) -{ - HASH_CTX *sha = &sig_sha[id]; - const uint8_t *blob = data; - size_t len = data_len; - - if ((id < 0) || (id >= stream_count)) - return EC_ERROR_PARAM1; - - if (signer_state[id] != state_started) - return EC_ERROR_INVAL; - - HASH_update(sha, blob, len); - signer_bytes[id] += len; - - return EC_SUCCESS; -} - -/* Close this stream's capture and print out the signature. */ -int sig_sign(enum stream_id id) -{ - HASH_CTX *sha = &sig_sha[id]; - p256_int r, s; /* signature tuple */ - p256_int digest; - struct drbg_ctx drbg; - - if ((id < 0) || (id >= stream_count)) - return EC_ERROR_PARAM1; - - if (signer_state[id] != state_started) { - CPRINTS("Signer %d not starter", id); - return EC_ERROR_INVAL; - } - - p256_from_bin(HASH_final(sha), &digest); - drbg_rand_init(&drbg); - - if (!dcrypto_p256_ecdsa_sign(&drbg, &d, &digest, &r, &s)) { - fail(); - return EC_ERROR_INVAL; - } - - /* Check that the signature was correctly computed */ - if (!dcrypto_p256_ecdsa_verify(&x, &y, &digest, &r, &s)) { - fail(); - return EC_ERROR_INVAL; - } - - /* Serialize r, s into output. */ - - CPRINTS("Signed %d bytes from %s.", signer_bytes[id], signer_name[id]); - CPRINTS("digest:"); - CPRINTS("%08x %08x %08x %08x", - digest.a[0], digest.a[1], digest.a[2], digest.a[3]); - CPRINTS("%08x %08x %08x %08x", - digest.a[4], digest.a[5], digest.a[6], digest.a[7]); - CPRINTS("r:"); - CPRINTS("%08x %08x %08x %08x", r.a[0], r.a[1], r.a[2], r.a[3]); - CPRINTS("%08x %08x %08x %08x", r.a[4], r.a[5], r.a[6], r.a[7]); - CPRINTS("s:"); - CPRINTS("%08x %08x %08x %08x", s.a[0], s.a[1], s.a[2], s.a[3]); - CPRINTS("%08x %08x %08x %08x", s.a[4], s.a[5], s.a[6], s.a[7]); - - signer_state[id] = state_ready; - return EC_SUCCESS; -} - - -/* - * Intercept UART data between the uart driver and usb bridge. - * - * This code is called by the ec's queue implementation, and ingests - * the UART RX queue, appends the data to the signer, then passes it - * on the the USB bridge's TX queue. - */ -void signer_written(struct consumer const *consumer, size_t count) -{ - struct signer_config const *config = - DOWNCAST(consumer, struct signer_config, consumer); - struct producer const *producer = &(config->producer); - enum stream_id id = config->id; - - /* This queue receives characters from the UART. */ - struct queue const *sig_in = consumer->queue; - - /* - * This enqueues characters into the USB bridge, - * once they have been hashed. - */ - struct queue const *sig_out = producer->queue; - char c; - - /* Copy UART rx from queue. */ - while (queue_count(sig_in) && QUEUE_REMOVE_UNITS(sig_in, &c, 1)) { - /* Append this data to the hash. */ - sig_append(id, &c, 1); - /* Pass the data to the USB bridge. */ - QUEUE_ADD_UNITS(sig_out, &c, 1); - } -} - -struct producer_ops const signer_producer_ops = { - .read = NULL, -}; - -struct consumer_ops const signer_consumer_ops = { - .written = signer_written, - .flush = NULL, -}; diff --git a/board/mn50/signing.h b/board/mn50/signing.h deleted file mode 100644 index 397a78441b..0000000000 --- a/board/mn50/signing.h +++ /dev/null @@ -1,73 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -/* - * Add inline signing to verify records pasased through - * AUTH haven on Scribe SLT board. - */ - -#ifndef __CROS_EC_SIGNER_H -#define __CROS_EC_SIGNER_H - -#include "queue.h" -#include "queue_policies.h" - -/* - * Data signing is supported on the following inputs: - * stream_spi: data received on H1's SPI master. - * stream_uart: data received on UART1. - * - * It's possible to hash multiple streams at once. - * Currently the hash will print out as console output - * in hex format when the stream is stopped. - */ -enum stream_id { - stream_spi = 0, - stream_uart = 1, - stream_count = 2, -}; - -/* Init the signing state and derive keys. Must be called before sig_start. */ -void init_signing(void); - -/* Zero the existing hash and start processing data in the specified stream. */ -int sig_start(enum stream_id id); - -/* Append data into the specified stream, if started, otherwise do nothing. */ -int sig_append(enum stream_id id, const uint8_t *data, size_t data_len); - -/* Stop a stream and sign the hash. The signature will print to the console. */ -int sig_sign(enum stream_id id); - - -struct signer_config { - enum stream_id id; - - struct producer const producer; - struct consumer const consumer; -}; - -extern struct consumer_ops const signer_consumer_ops; -extern struct producer_ops const signer_producer_ops; - -void signer_written(struct consumer const *consumer, size_t count); - -/* - * Macro to set up inline signer. - * Usage: SIGNER_CONFIG(name, stream_id, tx queue, rx queue) - */ -#define SIGNER_CONFIG(NAME, ID, RX_QUEUE, TX_QUEUE) \ - struct signer_config const NAME = { \ - .id = ID, \ - .consumer = { \ - .queue = &TX_QUEUE, \ - .ops = &signer_consumer_ops, \ - }, \ - .producer = { \ - .queue = &RX_QUEUE, \ - .ops = &signer_producer_ops, \ - }, \ - } -#endif diff --git a/board/mn50/usb_spi.c b/board/mn50/usb_spi.c deleted file mode 100644 index b44a450f91..0000000000 --- a/board/mn50/usb_spi.c +++ /dev/null @@ -1,94 +0,0 @@ -/* Copyright 2017 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. - */ - -#include "console.h" -#include "gpio.h" -#include "hooks.h" -#include "registers.h" -#include "signing.h" -#include "spi.h" -#include "system.h" -#include "timer.h" -#include "usb_spi.h" - -#define CPRINTS(format, args...) cprints(CC_USB, format, ## args) - -int usb_spi_board_enable(struct usb_spi_config const *config) -{ - spi_enable(CONFIG_SPI_FLASH_PORT, 1); - - /* Enable SPI framing for H1 bootloader */ - gpio_set_level(GPIO_SPI_CS_ALT_L, 0); - - return EC_SUCCESS; -} - -void usb_spi_board_disable(struct usb_spi_config const *config) -{ - /* End SPI framing for H1 bootloader */ - gpio_set_level(GPIO_SPI_CS_ALT_L, 1); - - spi_enable(CONFIG_SPI_FLASH_PORT, 0); -} - -int usb_spi_interface(struct usb_spi_config const *config, - struct usb_setup_packet *req) -{ - if (req->bmRequestType != (USB_DIR_OUT | - USB_TYPE_VENDOR | - USB_RECIP_INTERFACE)) - return 1; - - if ((req->wValue != 0 && req->wValue != 1) || - req->wIndex != config->interface || - req->wLength != 0) - return 1; - - if (!config->state->enabled_device) - return 1; - - switch (req->bRequest) { - case USB_SPI_REQ_ENABLE_H1: - config->state->enabled_host = USB_SPI_H1; - break; - - /* Set reset and DFU pins. Both active high. */ - case USB_SPI_REQ_RESET: - gpio_set_level(GPIO_DUT_RST_L, !req->wValue); - break; - case USB_SPI_REQ_BOOT_CFG: - gpio_set_level(GPIO_DUT_BOOT_CFG, req->wValue); - break; - /* Set socket power. */ - case USB_SPI_REQ_SOCKET: - if (req->wValue) - enable_socket(); - else - disable_socket(); - break; - case USB_SPI_REQ_SIGNING_START: - sig_start(stream_spi); - break; - case USB_SPI_REQ_SIGNING_SIGN: - sig_sign(stream_spi); - break; - case USB_SPI_REQ_ENABLE_AP: - case USB_SPI_REQ_ENABLE: - CPRINTS("ERROR: Must specify target"); - case USB_SPI_REQ_DISABLE: - config->state->enabled_host = USB_SPI_DISABLE; - break; - - default: - return 1; - } - - /* - * Our state has changed, call the deferred function to handle the - * state change. - */ - hook_call_deferred(config->deferred, 0); - return 0; -} |