Add JTAG module

This just ensures the JTAG pins are reset to JTAG function on warm reboot.

Signed-off-by: Randall Spangler <rspangler@chromium.org>

BUG=chrome-os-partner:7448
TEST=none

Change-Id: I0cccdbe7a68c228db7f354898ed30598e9fabff0

7 files changed, 65 insertions, 36 deletions

diff --git a/board/bds/board.c b/board/bds/board.c
index d9c79b675a..1d544e1fbe 100644
--- a/board/bds/board.c
+++ b/board/bds/board.c
@@ -30,38 +30,4 @@ void configure_board(void)
 	LM4_GPIO_DR8R(LM4_GPIO_A)  = 0x3c;
 	LM4_GPIO_DATA(LM4_GPIO_A, 0x40) = 0x40;
 	LM4_GPIO_DATA(LM4_GPIO_A, 0x80) = 0;
-
-	/* GPIOB muxing
-	 * pin 0 : GPIO = function 0 (USB ID)
-	 * pin 1 : USB digital (VBus sense)
-	 */
-	LM4_GPIO_DEN(LM4_GPIO_B)   |= 0x01;
-	LM4_GPIO_AFSEL(LM4_GPIO_B) |= 0x01;
-
-	/* GPIOC muxing
-	 * pins 0/1/2/3 : JTAG (default config)
-	 * pin 4 : GPIO = function 0 (OLED +15v power enable)
-	 * pin 6 : USB digital (USB power enable)
-	 * pin 7 : USB digital (USB current overflow)
-	 */
-	LM4_GPIO_PCTL(LM4_GPIO_C)  = 0x88001111;
-	LM4_GPIO_AFSEL(LM4_GPIO_C) = 0xcf;
-	LM4_GPIO_DEN(LM4_GPIO_C)   = 0xdf;
-	LM4_GPIO_DIR(LM4_GPIO_C)   = 0x10;
-	LM4_GPIO_DATA(LM4_GPIO_C, 0x10) = 0;
-
-	/* GPIOD muxing
-	 * pins 0/1/2/3/4 : GPIO = function 0 (buttons up,down,left,right,select)
-	 * pin 5 : GPIO = function 0 (OLED d/Cn)
-	 * pin 6 : GPIO = function 0 (OLED reset)
-	 */
-	LM4_GPIO_DEN(LM4_GPIO_D)   = 0x7f;
-	LM4_GPIO_DIR(LM4_GPIO_D)   = 0x60;
-	LM4_GPIO_PUR(LM4_GPIO_D)   = 0x1f;
-
-	/* GPIOE muxing
-	 * pin 3 : Analog function : AIN0 ADC (potentiometer)
-	 * pin 6/7: USB analog
-	 */
-	LM4_GPIO_AMSEL(LM4_GPIO_E) = 0x8;
 }
diff --git a/chip/lm4/build.mk b/chip/lm4/build.mk
index 28f7c4da2f..ec91bcc6db 100644
--- a/chip/lm4/build.mk
+++ b/chip/lm4/build.mk
@@ -8,6 +8,6 @@
 # CPU specific compilation flags
 CFLAGS_CPU=-mcpu=cortex-m4 -mthumb -Os -mno-sched-prolog
 
-chip-objs=init.o panic.o switch.o task.o timer.o pwm.o i2c.o adc.o
+chip-objs=init.o panic.o switch.o task.o timer.o pwm.o i2c.o adc.o jtag.o
 chip-objs+=clock.o gpio.o system.o lpc.o uart.o x86_power.o power_button.o
 chip-objs+=flash.o watchdog.o eeprom.o keyboard_scan.o temp_sensor.o
diff --git a/chip/lm4/gpio.c b/chip/lm4/gpio.c
index 974f849d8e..bc0e32fc31 100644
--- a/chip/lm4/gpio.c
+++ b/chip/lm4/gpio.c
@@ -18,7 +18,8 @@
 struct gpio_info {
 	const char *name;
 	int port;   /* Port (LM4_GPIO_*) */
-	int mask;   /* Bitmask on that port (0x01 - 0x80) */
+	int mask;   /* Bitmask on that port (0x01 - 0x80; 0x00 =
+		       signal not implemented) */
 	void (*irq_handler)(enum gpio_signal signal);
 };
 
@@ -201,6 +202,11 @@ static int command_gpio_set(int argc, char **argv)
 		return EC_ERROR_UNKNOWN;
 	}
 
+	if (!signal_info[i].mask) {
+		uart_puts("Signal is not implemented; ignoring request.\n");
+		return EC_SUCCESS;
+	}
+
 	v = strtoi(argv[2], &e, 0);
 	if (*e) {
 		uart_puts("Invalid signal value.\n");
diff --git a/chip/lm4/jtag.c b/chip/lm4/jtag.c
new file mode 100644
index 0000000000..89870d5a0d
--- /dev/null
+++ b/chip/lm4/jtag.c
@@ -0,0 +1,37 @@
+/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "jtag.h"
+#include "registers.h"
+
+
+int jtag_pre_init(void)
+{
+	/* Ensure PC0:3 are set to JTAG function.  They should be set this way
+	 * on a cold boot, but on a warm reboot a previous misbehaving image
+	 * could have set them differently. */
+	if (((LM4_GPIO_PCTL(LM4_GPIO_C) & 0x0000ffff) == 0x00001111) &&
+	    ((LM4_GPIO_AFSEL(LM4_GPIO_C) & 0x0f) == 0x0f) &&
+	    ((LM4_GPIO_DEN(LM4_GPIO_C) & 0x0f) == 0x0f) &&
+	    ((LM4_GPIO_PUR(LM4_GPIO_C) & 0x0f) == 0x0f))
+		return EC_SUCCESS;  /* Already properly configured */
+
+	/* Unlock commit register for JTAG pins */
+	LM4_GPIO_LOCK(LM4_GPIO_C) = LM4_GPIO_LOCK_UNLOCK;
+	LM4_GPIO_CR(LM4_GPIO_C) |= 0x0f;
+
+	/* Reset JTAG pins */
+	LM4_GPIO_PCTL(LM4_GPIO_C) =
+		(LM4_GPIO_PCTL(LM4_GPIO_C) & 0xffff0000) | 0x00001111;
+	LM4_GPIO_AFSEL(LM4_GPIO_C) |= 0x0f;
+	LM4_GPIO_DEN(LM4_GPIO_C) |= 0x0f;
+	LM4_GPIO_PUR(LM4_GPIO_C) |= 0x0f;
+
+	/* Re-lock commit register */
+	LM4_GPIO_CR(LM4_GPIO_C) &= ~0x0f;
+	LM4_GPIO_LOCK(LM4_GPIO_C) = 0;
+
+	return EC_SUCCESS;
+}
diff --git a/chip/lm4/registers.h b/chip/lm4/registers.h
index 6762cb0410..ff4394fc28 100644
--- a/chip/lm4/registers.h
+++ b/chip/lm4/registers.h
@@ -355,6 +355,8 @@ static inline int lm4_fan_addr(int ch, int offset)
 #define LM4_GPIO_AMSEL(port)          LM4GPIOREG(port, 0x528)
 #define LM4_GPIO_PCTL(port)           LM4GPIOREG(port, 0x52c)
 
+/* Value to write to LM4_GPIO_LOCK to unlock writes */
+#define LM4_GPIO_LOCK_UNLOCK          0x4c4f434b
 
 /* I2C */
 #define LM4_I2C0_BASE                 0x40020000
diff --git a/common/main.c b/common/main.c
index c2c71fd67a..69062e75f3 100644
--- a/common/main.c
+++ b/common/main.c
@@ -17,6 +17,7 @@
 #include "flash_commands.h"
 #include "gpio.h"
 #include "i2c.h"
+#include "jtag.h"
 #include "keyboard.h"
 #include "lpc.h"
 #include "memory_commands.h"
@@ -51,6 +52,7 @@ int main(void)
 {
 	/* Configure the pin multiplexers */
 	configure_board();
+	jtag_pre_init();
 	/* Set the CPU clocks / PLLs */
 	clock_init();
 
diff --git a/include/jtag.h b/include/jtag.h
new file mode 100644
index 0000000000..6dd83a92bf
--- /dev/null
+++ b/include/jtag.h
@@ -0,0 +1,16 @@
+/* Copyright (c) 2012 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* JTAG interface for Chrome EC */
+
+#ifndef __CROS_EC_JTAG_H
+#define __CROS_EC_JTAG_H
+
+#include "common.h"
+
+/* Pre-initializes the module. */
+int jtag_pre_init(void);
+
+#endif  /* __CROS_EC_JTAG_H */