zephyr: initial delbin bringup

Initial project files for delbin supporting only basic UART
functionality.

More features to come!

BUG=b:180410072
BRANCH=none
TEST=flash to delbin, test basic uart functionality

Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I115ef9b976adb50d29170656c39994ab039865c9
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2698267
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>

11 files changed, 271 insertions, 0 deletions

diff --git a/zephyr/projects/delbin/CMakeLists.txt b/zephyr/projects/delbin/CMakeLists.txt
new file mode 100644
index 0000000000..b7330162de
--- /dev/null
+++ b/zephyr/projects/delbin/CMakeLists.txt
@@ -0,0 +1,10 @@
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.13.1)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(delbin)
+
+zephyr_include_directories(include)
diff --git a/zephyr/projects/delbin/boards/arm/delbin/Kconfig.board b/zephyr/projects/delbin/boards/arm/delbin/Kconfig.board
new file mode 100644
index 0000000000..612127c0d0
--- /dev/null
+++ b/zephyr/projects/delbin/boards/arm/delbin/Kconfig.board
@@ -0,0 +1,7 @@
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+config BOARD_DELBIN
+	bool "Google Delbin EC"
+	depends on SOC_NPCX7M6FB # Actually NPCX7M6FC; C has 512K Flash
diff --git a/zephyr/projects/delbin/boards/arm/delbin/Kconfig.defconfig b/zephyr/projects/delbin/boards/arm/delbin/Kconfig.defconfig
new file mode 100644
index 0000000000..3b5e04a219
--- /dev/null
+++ b/zephyr/projects/delbin/boards/arm/delbin/Kconfig.defconfig
@@ -0,0 +1,10 @@
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if BOARD_DELBIN
+
+config BOARD
+	default "delbin"
+
+endif # BOARD_DELBIN
diff --git a/zephyr/projects/delbin/boards/arm/delbin/board.cmake b/zephyr/projects/delbin/boards/arm/delbin/board.cmake
new file mode 100644
index 0000000000..5c02f2707f
--- /dev/null
+++ b/zephyr/projects/delbin/boards/arm/delbin/board.cmake
@@ -0,0 +1,5 @@
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+set(ECST_CHIP_ARG npcx7m7)
diff --git a/zephyr/projects/delbin/boards/arm/delbin/delbin.dts b/zephyr/projects/delbin/boards/arm/delbin/delbin.dts
new file mode 100644
index 0000000000..0260090864
--- /dev/null
+++ b/zephyr/projects/delbin/boards/arm/delbin/delbin.dts
@@ -0,0 +1,98 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/dts-v1/;
+
+#include <cros/nuvoton/npcx.dtsi>
+#include <dt-bindings/gpio_defines.h>
+#include <nuvoton/npcx7m6fb.dtsi>
+
+/ {
+	model = "Google Delbin EC";
+
+	aliases {
+		i2c-0 = &i2c0_0;
+		i2c-1 = &i2c1_0;
+		i2c-2 = &i2c2_0;
+		i2c-3 = &i2c3_0;
+		i2c-5 = &i2c5_0;
+		i2c-7 = &i2c7_0;
+	};
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,console = &uart1;
+		zephyr,shell-uart = &uart1;
+		zephyr,flash = &flash0;
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+	};
+
+	named-gpios {
+		compatible = "named-gpios";
+	};
+
+	def_lvol_io_list {
+		compatible = "nuvoton,npcx-lvolctrl-def";
+
+		/* I2C_SDA0 & SCL0 */
+		lvol_io_pads = <&lvol_iob4 &lvol_iob5>;
+	};
+
+	soc {
+		fiu0: cros-flash@40020000 {
+			compatible = "nuvoton,npcx-cros-flash";
+			reg = <0x40020000 0x2000>;
+			clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL1 2>;
+			size = <0x80000>;
+			label = "FLASH_INTERFACE_UNIT0";
+			pinctrl-0 = <>;
+		};
+	};
+
+	/* Update flash size to 512KB from 196KB since we are using C variant */
+	/delete-node/ flash@10090000;
+	flash0: flash@10070000 {
+		reg = <0x10070000 0x40000>;
+	};
+};
+
+&uart1 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&altc_uart1_sl2>; /* Use UART1_SL2 ie. PIN64.65 */
+};
+
+&i2c0_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&i2c1_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+};
+
+&i2c2_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+};
+
+&i2c3_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+};
+
+&i2c5_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+};
+
+&i2c7_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
diff --git a/zephyr/projects/delbin/boards/arm/delbin/delbin.yaml b/zephyr/projects/delbin/boards/arm/delbin/delbin.yaml
new file mode 100644
index 0000000000..17d4bc734e
--- /dev/null
+++ b/zephyr/projects/delbin/boards/arm/delbin/delbin.yaml
@@ -0,0 +1,17 @@
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+identifier: delbin
+name: "Google Delbin Embedded Controller"
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+ram: 64
+flash: 512
+testing:
+  ignore_tags:
+    - net
+    - bluetooth
diff --git a/zephyr/projects/delbin/boards/arm/delbin/delbin_defconfig b/zephyr/projects/delbin/boards/arm/delbin/delbin_defconfig
new file mode 100644
index 0000000000..2d1cf94d25
--- /dev/null
+++ b/zephyr/projects/delbin/boards/arm/delbin/delbin_defconfig
@@ -0,0 +1,52 @@
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Zephyr Kernel Configuration
+CONFIG_SOC_SERIES_NPCX7=y
+
+# Platform Configuration
+CONFIG_SOC_NPCX7M6FB=y # Actually NPCX7M6FC; C just has 512K Flash
+CONFIG_BOARD_DELBIN=y
+
+# Serial Drivers
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Pinmux Driver
+CONFIG_PINMUX=y
+
+# GPIO Controller
+CONFIG_GPIO=y
+
+# Clock configuration
+CONFIG_CLOCK_CONTROL=y
+
+# PLL configuration
+CONFIG_CLOCK_NPCX_OSC_CYCLES_PER_SEC=90000000
+CONFIG_CLOCK_NPCX_APB1_PRESCALER=6
+CONFIG_CLOCK_NPCX_APB2_PRESCALER=6
+CONFIG_CLOCK_NPCX_APB3_PRESCALER=6
+
+CONFIG_CORTEX_M_SYSTICK=y
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=15000000
+
+# Code RAM base for NPCX797FC
+CONFIG_CROS_EC_PROGRAM_MEMORY_BASE=0x10070000
+CONFIG_CROS_EC_RAM_BASE=0x200c0000
+CONFIG_CROS_EC_DATA_RAM_SIZE=0x00010000
+CONFIG_CROS_EC_RAM_SIZE=0x0000f800
+
+CONFIG_FLASH_SIZE=512
+CONFIG_CROS_EC_RO_MEM_OFF=0x0
+# (44*1024)
+CONFIG_CROS_EC_RO_SIZE=0x40000
+# (CONFIG_CROS_EC_RO_MEM_OFF + CONFIG_CROS_EC_RO_SIZE)
+CONFIG_CROS_EC_RW_MEM_OFF=0x0
+# (CONFIG_CROS_EC_FLASH_SIZE - CONFIG_CROS_EC_RW_MEM_OFF -
+#  CONFIG_CROS_EC_RO_MEM_OFF)
+CONFIG_CROS_EC_RW_SIZE=0x40000
diff --git a/zephyr/projects/delbin/include/gpio_map.h b/zephyr/projects/delbin/include/gpio_map.h
new file mode 100644
index 0000000000..93247729dc
--- /dev/null
+++ b/zephyr/projects/delbin/include/gpio_map.h
@@ -0,0 +1,36 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __ZEPHYR_GPIO_MAP_H
+#define __ZEPHYR_GPIO_MAP_H
+
+#include <devicetree.h>
+#include <gpio_signal.h>
+
+/*
+ * TODO(b/180410072): system.c seems to require these to be defined,
+ * but we don't have GPIO brought up yet...
+ */
+#define GPIO_ENTERING_RW -1
+#define GPIO_WP_L -1
+
+/*
+ * Set EC_CROS_GPIO_INTERRUPTS to a space-separated list of GPIO_INT items.
+ *
+ * Each GPIO_INT requires three parameters:
+ *   gpio_signal - The enum gpio_signal for the interrupt gpio
+ *   interrupt_flags - The interrupt-related flags (e.g. GPIO_INT_EDGE_BOTH)
+ *   handler - The platform/ec interrupt handler.
+ *
+ * Ensure that this files includes all necessary headers to declare all
+ * referenced handler functions.
+ *
+ * For example, one could use the follow definition:
+ * #define EC_CROS_GPIO_INTERRUPTS \
+ *   GPIO_INT(NAMED_GPIO(h1_ec_pwr_btn_odl), GPIO_INT_EDGE_BOTH, button_print)
+ */
+#define EC_CROS_GPIO_INTERRUPTS
+
+#endif /* __ZEPHYR_GPIO_MAP_H */
diff --git a/zephyr/projects/delbin/include/i2c_map.h b/zephyr/projects/delbin/include/i2c_map.h
new file mode 100644
index 0000000000..aa4c5f970f
--- /dev/null
+++ b/zephyr/projects/delbin/include/i2c_map.h
@@ -0,0 +1,9 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __ZEPHYR_I2C_MAP_H
+#define __ZEPHYR_I2C_MAP_H
+
+#endif /* __ZEPHYR_I2C_MAP_H */
diff --git a/zephyr/projects/delbin/prj.conf b/zephyr/projects/delbin/prj.conf
new file mode 100644
index 0000000000..1fcf2cbb5c
--- /dev/null
+++ b/zephyr/projects/delbin/prj.conf
@@ -0,0 +1,18 @@
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_CROS_EC=y
+CONFIG_PLATFORM_EC=y
+CONFIG_SHIMMED_TASKS=y
+CONFIG_PLATFORM_EC_BRINGUP=y
+
+# TODO(b/180410072): bringup these features
+CONFIG_PLATFORM_EC_BACKLIGHT_LID=n
+CONFIG_PLATFORM_EC_BOARD_VERSION=n
+CONFIG_PLATFORM_EC_HOSTCMD=n
+CONFIG_PLATFORM_EC_KEYBOARD=n
+CONFIG_CROS_KB_RAW_NPCX=n
+CONFIG_PLATFORM_EC_SWITCH=n
+CONFIG_PLATFORM_EC_VBOOT_HASH=n
+CONFIG_PLATFORM_EC_VSTORE=n
diff --git a/zephyr/projects/delbin/zmake.yaml b/zephyr/projects/delbin/zmake.yaml
new file mode 100644
index 0000000000..2ceb55f073
--- /dev/null
+++ b/zephyr/projects/delbin/zmake.yaml
@@ -0,0 +1,9 @@
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+board: delbin
+supported-zephyr-versions:
+  - v2.4
+toolchain: coreboot-sdk
+output-type: raw