diff options
author | Tzung-Bi Shih <tzungbi@chromium.org> | 2021-03-08 12:32:16 +0800 |
---|---|---|
committer | Commit Bot <commit-bot@chromium.org> | 2021-03-08 07:48:37 +0000 |
commit | 04c8f38e22c58f82346eec8d72631ba0c0d48d78 (patch) | |
tree | b50b1cfd762776b58fa04335c77d21700804bc38 | |
parent | f7637b3f78d82061922f2e5d28ca9d812e2fd51e (diff) | |
download | chrome-ec-04c8f38e22c58f82346eec8d72631ba0c0d48d78.tar.gz |
chip/mt8192_scp: change clock source to ULPOSC for UART
26M clock cannot be used when AP enters S3. Changes the clock source to
ULPOSC instead.
Note: it is still 26M.
BRANCH=none
BUG=b:181629273
TEST=powerd_dbus_suspend
Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org>
Change-Id: I4d691c8b930fa87fc4b04a361274156766f387cc
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2738588
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
-rw-r--r-- | chip/mt8192_scp/uart.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/chip/mt8192_scp/uart.c b/chip/mt8192_scp/uart.c index 30708acaeb..2479bb8711 100644 --- a/chip/mt8192_scp/uart.c +++ b/chip/mt8192_scp/uart.c @@ -25,19 +25,18 @@ static uint8_t init_done, tx_started; void uart_init(void) { const uint32_t baud_rate = CONFIG_UART_BAUD_RATE; - /* TODO: use ULPOSC1 for S3 */ const uint32_t uart_clock = 26000000; const uint32_t div = DIV_ROUND_NEAREST(uart_clock, baud_rate * 16); #if UARTN == 0 - SCP_UART_CK_SEL |= UART0_CK_SEL_VAL(UART_CK_SEL_26M); + SCP_UART_CK_SEL |= UART0_CK_SEL_VAL(UART_CK_SEL_ULPOSC); SCP_SET_CLK_CG |= CG_UART0_MCLK | CG_UART0_BCLK | CG_UART0_RST; /* set AP GPIO164 and GPIO165 to alt func 3 */ AP_GPIO_MODE20_CLR = 0x00770000; AP_GPIO_MODE20_SET = 0x00330000; #elif UARTN == 1 - SCP_UART_CK_SEL |= UART1_CK_SEL_VAL(UART_CK_SEL_26M); + SCP_UART_CK_SEL |= UART1_CK_SEL_VAL(UART_CK_SEL_ULPOSC); SCP_SET_CLK_CG |= CG_UART1_MCLK | CG_UART1_BCLK | CG_UART1_RST; #endif |