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| author | Rob Barnes <robbarnes@google.com> | 2021-05-07 17:24:10 -0600 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-05-10 19:56:17 +0000 |
| commit | f534a64194bdf9320d6f243f8ebbb770ab51db79 (patch) | |
| tree | e7fa9bffdd3eaa35d79950d4a821986e18425b9f | |
| parent | fd27ad0b0502f53e8b367847ecc104b7d492a393 (diff) | |
| download | chrome-ec-f534a64194bdf9320d6f243f8ebbb770ab51db79.tar.gz | |
mancomb: Enable 4 byte port80 codes
AMD SOCs send 4 byte port80 codes. This CL will allow these codes to be
properly displayed.
BUG=b:181598456
TEST=4 byte codes on guybrush
BRANCH=None
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I931ecca06097765d61a83cab739b3dffab80d282
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2881032
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Commit-Queue: Diana Z <dzigterman@chromium.org>
| -rw-r--r-- | baseboard/mancomb/baseboard.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/baseboard/mancomb/baseboard.h b/baseboard/mancomb/baseboard.h index 0c4782788e..841f71a95f 100644 --- a/baseboard/mancomb/baseboard.h +++ b/baseboard/mancomb/baseboard.h @@ -9,6 +9,7 @@ #define __CROS_EC_BASEBOARD_H /* NPCX9 config */ +#define CONFIG_PORT80_4_BYTE #define NPCX9_PWM1_SEL 1 /* GPIO C2 is used as PWM1. */ #define NPCX_UART_MODULE2 1 /* GPIO64/65 are used as UART pins. */ |