PE Test: Add unit test for PR swap interruption during power transition

When a non-interruptible AMS is interrupted during power transition,
send a hard reset.  Attempting a soft reset here will result in a bad
connection state since Vbus is currently discharging and the soft reset
process can't complete without Vbus presence.  Add a unit test to
enforce this.

BRANCH=None
BUG=b:184764468
TEST=make -j buildall

Signed-off-by: Diana Z <dzigterman@chromium.org>
Change-Id: Ifa20a7cea2c2c3a52e4ba4e88712c262c7c18967
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2897128
Reviewed-by: Denis Brockus <dbrockus@chromium.org>

1 files changed, 62 insertions, 0 deletions

diff --git a/test/usb_pe_drp.c b/test/usb_pe_drp.c
index 55be741ad6..da204f3610 100644
--- a/test/usb_pe_drp.c
+++ b/test/usb_pe_drp.c
@@ -262,12 +262,74 @@ test_static int test_send_caps_error_when_connected(void)
 	return EC_SUCCESS;
 }
 
+/*
+ * Verify that when PR swap is interrupted during power transitiong, hard
+ * reset is sent
+ */
+test_static int test_interrupting_pr_swap(void)
+{
+	/* Enable PE as source, expect SOURCE_CAP. */
+	mock_tc_port[PORT0].power_role = PD_ROLE_SOURCE;
+	mock_tc_port[PORT0].pd_enable = 1;
+	mock_tc_port[PORT0].vconn_src = true;
+	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPC_TX_SOP,
+					 0, PD_DATA_SOURCE_CAP, 10 * MSEC),
+		EC_SUCCESS, "%d");
+	mock_prl_message_sent(PORT0);
+	task_wait_event(10 * MSEC);
+
+	/* REQUEST 5V, expect ACCEPT, PS_RDY. */
+	rx_message(PD_MSG_SOP, 0, PD_DATA_REQUEST,
+		   PD_ROLE_SINK, PD_ROLE_UFP, RDO_FIXED(1, 500, 500, 0));
+	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPC_TX_SOP,
+					 PD_CTRL_ACCEPT, 0, 10 * MSEC),
+		EC_SUCCESS, "%d");
+	mock_prl_message_sent(PORT0);
+	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPC_TX_SOP,
+					 PD_CTRL_PS_RDY, 0, 35 * MSEC),
+		EC_SUCCESS, "%d");
+	mock_prl_message_sent(PORT0);
+
+	TEST_EQ(finish_src_discovery(0), EC_SUCCESS, "%d");
+
+	task_wait_event(5 * SECOND);
+
+	/*
+	 * Now connected.  Initiate a PR swap and then interrupt it after the
+	 * Accept, when power is transitioning to off.
+	 */
+	rx_message(PD_MSG_SOP, PD_CTRL_PR_SWAP, 0,
+		   PD_ROLE_SINK, PD_ROLE_UFP, 0);
+
+	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPC_TX_SOP,
+					 PD_CTRL_ACCEPT, 0, 10 * MSEC),
+		EC_SUCCESS, "%d");
+	mock_prl_message_sent(PORT0);
+
+	task_wait_event(5 * SECOND);
+
+	/* Interrupt the non-interruptible AMS */
+	rx_message(PD_MSG_SOP, PD_CTRL_PR_SWAP, 0,
+		   PD_ROLE_SINK, PD_ROLE_UFP, 0);
+
+	/*
+	 * Expect a hard reset since power was transitioning during this
+	 * interruption
+	 */
+	TEST_EQ(mock_prl_wait_for_tx_msg(PORT0, TCPC_TX_HARD_RESET,
+					 0, 0, 10 * MSEC),
+		EC_SUCCESS, "%d");
+
+	return EC_SUCCESS;
+}
+
 void run_test(int argc, char **argv)
 {
 	test_reset();
 
 	RUN_TEST(test_send_caps_error_before_connected);
 	RUN_TEST(test_send_caps_error_when_connected);
+	RUN_TEST(test_interrupting_pr_swap);
 
 	/* Do basic state machine validity checks last. */
 	RUN_TEST(test_pe_no_parent_cycles);