adlrvpp_mchp1521: Add code for ADL-P-DDR4 RVP using Microchip EC

ADL-P-DDR4 RVP has on board Microchip EC-MEC1521. This code enables
RVP powering ON using this on board EC, instead of Mica EC.
As this onboard EC doesn't have internal flash memory, EC binary of
512KB size generated is flashed to external SPI Flash1(32MB size)
available on RVP over SPI using servo.This image from flash1 is
then bootloaded by MEC1521, when powered ON.

BUG=b:186669325
BRANCH=none
TEST=ADL-P-DDR4 board with Microchip 1521 EC booted to S0.

Signed-off-by: Poornima Tom <poornima.tom@intel.com>
Change-Id: I39f937f60e2f79b0d2de195621084e3276e36bf2
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2755363
Tested-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: caveh jalali <caveh@chromium.org>

7 files changed, 605 insertions, 1 deletions

diff --git a/baseboard/intelrvp/build.mk b/baseboard/intelrvp/build.mk
index 90335afd3b..5b225d375e 100644
--- a/baseboard/intelrvp/build.mk
+++ b/baseboard/intelrvp/build.mk
@@ -28,7 +28,7 @@ baseboard-$(CONFIG_BC12_DETECT_MAX14637)+=bc12.o
 
 #Common board specific files
 ifneq ($(filter y,$(BOARD_ADLRVPP_ITE) $(BOARD_ADLRVPM_ITE) \
-		$(BOARD_ADLRVPP_NPCX)),)
+		$(BOARD_ADLRVPP_MCHP1521) $(BOARD_ADLRVPP_NPCX)),)
 baseboard-y+=adlrvp.o
 ifneq ($(BOARD_ADLRVPM_ITE),)
 baseboard-$(CONFIG_BATTERY_SMART)+=adlrvp_battery2s.o
diff --git a/board/adlrvpp_mchp1521/board.c b/board/adlrvpp_mchp1521/board.c
new file mode 100644
index 0000000000..3e676a1c6c
--- /dev/null
+++ b/board/adlrvpp_mchp1521/board.c
@@ -0,0 +1,88 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Intel ADLRVP-P-DDR4-MEC1521 board-specific configuration */
+
+#include "button.h"
+#include "fan.h"
+#include "fusb302.h"
+#include "gpio.h"
+#include "i2c.h"
+#include "keyboard_scan.h"
+#include "lid_switch.h"
+#include "pca9675.h"
+#include "power.h"
+#include "power_button.h"
+#include "pwm.h"
+#include "pwm_chip.h"
+#include "spi_chip.h"
+#include "switch.h"
+#include "tablet_mode.h"
+#include "timer.h"
+#include "uart.h"
+#include "usb_pd_tbt.h"
+#include "usb_pd_tcpm.h"
+#include "util.h"
+
+#include "gpio_list.h" /* Must come after other header files. */
+
+/******************************************************************************/
+/* I2C ports */
+const struct i2c_port_t i2c_ports[] = {
+	/*
+	 * Port-80 Display, Charger, Battery, IO-expander, EEPROM,
+	 * ISH sensor, AUX-rail, power-monitor.
+	 */
+	[I2C_CHAN_BATT_CHG] = {
+		.name = "batt_chg",
+		.port = I2C_PORT_CHARGER,
+		.kbps = 100,
+		.scl = GPIO_SMB_BS_CLK,
+		.sda = GPIO_SMB_BS_DATA,
+	},
+	[I2C_CHAN_TCPC_0] = {
+		.name = "typec_0",
+		.port = I2C_PORT_TYPEC_0,
+		.kbps = 400,
+		.scl = GPIO_TYPEC_EC_SMBUS1_CLK_EC,
+		.sda = GPIO_TYPEC_EC_SMBUS1_DATA_EC,
+	},
+	[I2C_CHAN_TCPC_1] = {
+		.name = "typec_1",
+		.port = I2C_PORT_TYPEC_1,
+		.kbps = 400,
+		.scl = GPIO_TYPEC_EC_SMBUS3_CLK,
+		.sda = GPIO_TYPEC_EC_SMBUS3_DATA,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(i2c_ports) == I2C_CHAN_COUNT);
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+/* USB-C TCPC Configuration */
+const struct tcpc_config_t tcpc_config[] = {
+	[TYPE_C_PORT_0] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TYPEC_0,
+			.addr_flags = I2C_ADDR_FUSB302_TCPC_AIC,
+		},
+		.drv = &fusb302_tcpm_drv,
+	},
+	[TYPE_C_PORT_1] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TYPEC_1,
+			.addr_flags = I2C_ADDR_FUSB302_TCPC_AIC,
+		},
+		.drv = &fusb302_tcpm_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == CONFIG_USB_PD_PORT_MAX_COUNT);
+
+/* SPI devices */
+const struct spi_device_t spi_devices[] = {
+	{ QMSPI0_PORT, 4, GPIO_QMSPI_CS0},
+};
+const unsigned int spi_devices_used = ARRAY_SIZE(spi_devices);
diff --git a/board/adlrvpp_mchp1521/board.h b/board/adlrvpp_mchp1521/board.h
new file mode 100644
index 0000000000..b78f433dfd
--- /dev/null
+++ b/board/adlrvpp_mchp1521/board.h
@@ -0,0 +1,157 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Intel ADLRVP-P-DDR4-MEC1521 board-specific configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/* Microchip EC variant */
+#define VARIANT_INTELRVP_EC_MCHP
+
+/* UART for EC console */
+#undef CONFIG_UART_CONSOLE
+#define CONFIG_UART_CONSOLE 2
+
+#include "adlrvp.h"
+
+/*
+ * Macros for GPIO signals used in common code that don't match the
+ * schematic names. Signal names in gpio.inc match the schematic and are
+ * then redefined here to so it's more clear which signal is being used for
+ * which purpose.
+ */
+/* Power sequencing */
+#define GPIO_EC_SPI_OE_N		GPIO_EC_PCH_SPI_OE_N
+#define GPIO_PG_EC_ALL_SYS_PWRGD	GPIO_ALL_SYS_PWRGD
+#define GPIO_RSMRST_L_PGOOD		GPIO_RSMRST_PWRGD_EC_N
+#define GPIO_PG_EC_RSMRST_ODL		GPIO_RSMRST_PWRGD_EC_N
+#define GPIO_PCH_SLP_S0_L		GPIO_PM_SLP_S0_R_N
+#define GPIO_PG_EC_DSW_PWROK		GPIO_EC_TRACE_DATA_2
+#define GPIO_VCCST_PWRGD		GPIO_EC_TRACE_DATA_3
+#define GPIO_SLP_SUS_L			GPIO_PM_SLP_SUS_N
+#define GPIO_SYS_RESET_L		GPIO_DG2_PRESENT
+#define GPIO_PCH_RSMRST_L		GPIO_PM_RSMRST_R
+#define GPIO_PCH_PWRBTN_L		GPIO_PM_PWRBTN_N_R
+#define GPIO_EN_PP3300_A		GPIO_EC_DS3_R
+#define GPIO_SYS_PWROK_EC		GPIO_SYS_PWROK_EC_R
+#define GPIO_PCH_DSW_PWROK		GPIO_EC_TRACE_DATA_1
+
+/* Buttons */
+#define GPIO_LID_OPEN			GPIO_SMC_LID
+#define GPIO_VOLUME_UP_L		GPIO_VOL_UP_EC
+#define GPIO_VOLUME_DOWN_L		GPIO_VOL_DOWN_EC
+#define GPIO_POWER_BUTTON_L		GPIO_PWRBTN_EC_IN_N
+
+/* Sensors */
+#define GMR_TABLET_MODE_GPIO_L		GPIO_EC_SLATEMODE_HALLOUT_SNSR_R
+#define GPIO_CPU_PROCHOT		GPIO_PROCHOT_EC_R
+
+/* AC & Battery */
+#define GPIO_DC_JACK_PRESENT		GPIO_STD_ADP_PRSNT_EC
+#define GPIO_AC_PRESENT			GPIO_BC_ACOK_EC_IN
+#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_BATT_ID_R
+
+/* eSPI/Host communication */
+#define GPIO_ESPI_RESET_L		GPIO_ESPI_RST_EC_R_N
+#define GPIO_PCH_WAKE_L			GPIO_SMC_WAKE_SCI_N
+#define GPIO_EC_INT_L			GPIO_EC_TRACE_DATA_0
+
+/* H1 */
+#define GPIO_WP_L			GPIO_EC_WAKE_CLK_R
+#define GPIO_PACKET_MODE_EN		GPIO_EC_TRACE_CLK
+#define GPIO_ENTERING_RW		GPIO_DNX_FORCE_RELOAD_EC_R
+
+/* FAN */
+#define GPIO_FAN_POWER_EN		GPIO_FAN_PWR_DISABLE
+
+/* LEDs */
+#define GPIO_BAT_LED_RED_L		GPIO_PM_BAT_STATUS_LED2
+#define GPIO_PWR_LED_WHITE_L		GPIO_PM_PWRBTN_LED
+
+/* Uart */
+#define GPIO_UART2_RX			GPIO_EC_UART_RX
+
+/* Case Closed Debug Mode interrupt */
+#define GPIO_CCD_MODE_ODL		GPIO_KBC_NUMLOCK
+
+/* USB-C interrupts */
+#define GPIO_USBC_TCPC_ALRT_P0		GPIO_TYPEC_EC_SMBUS_ALERT_0_R
+#define GPIO_USBC_TCPC_ALRT_P1		GPIO_TYPEC_EC_SMBUS_ALERT_1_R
+#define GPIO_USBC_TCPC_PPC_ALRT_P0	GPIO_KBC_SCANOUT_15
+#define GPIO_USBC_TCPC_PPC_ALRT_P1	GPIO_KBC_CAPSLOCK
+
+
+/* I2C ports & Configs */
+/* Charger */
+#define I2C_PORT_CHARGER		MCHP_I2C_PORT0
+/* Port 80 */
+#define I2C_PORT_PORT80			MCHP_I2C_PORT0
+/* Board ID */
+#define I2C_PORT_PCA9555_BOARD_ID_GPIO	MCHP_I2C_PORT0
+/* Battery */
+#define I2C_PORT_BATTERY		MCHP_I2C_PORT0
+/* USB-C I2C */
+#define I2C_PORT_TYPEC_0		MCHP_I2C_PORT1
+#define I2C_PORT_TYPEC_1		MCHP_I2C_PORT5
+
+/*
+ * MEC1521H loads firmware using QMSPI controller
+ * CONFIG_SPI_FLASH_PORT is the index into
+ * spi_devices[] in board.c
+ */
+#define CONFIG_SPI_FLASH_PORT 0
+#define CONFIG_SPI_FLASH
+
+/*
+ * ADLRVP uses 32MB SPI flash- W25R256JVEIQ.But, EC binary to be generated
+ * is of size 512KB. This bin is then later appended with 0xFF to become 32MB
+ * binary for flashing purpose.
+ */
+#define CONFIG_FLASH_SIZE_BYTES	(512 * 1024)
+#define CONFIG_SPI_FLASH_W25X40	/* TODO: change to W25R256 */
+
+/* ADC channels */
+/*
+ * Undefining below and redefining based on ADL RVP schematics,
+ * as they are already defined with different channels in mchp_ec.h.
+ */
+#undef ADC_TEMP_SNS_AMBIENT_CHANNEL
+#undef ADC_TEMP_SNS_VR_CHANNEL
+#undef ADC_TEMP_SNS_DDR_CHANNEL
+#undef ADC_TEMP_SNS_SKIN_CHANNEL
+
+#define ADC_TEMP_SNS_AMBIENT_CHANNEL	CHIP_ADC_CH4
+#define ADC_TEMP_SNS_VR_CHANNEL		CHIP_ADC_CH5
+#define ADC_TEMP_SNS_DDR_CHANNEL	CHIP_ADC_CH6
+#define ADC_TEMP_SNS_SKIN_CHANNEL	CHIP_ADC_CH7
+
+/* To do: Remove once fan register details are added in mchp/fan.c */
+#undef CONFIG_FANS
+
+/*
+ * MEC152x I2C controllers are multi-port.
+ * Each controller can use any of the 11 ports.
+ */
+#define I2C_CONTROLLER_COUNT	3
+#define I2C_PORT_COUNT		3
+
+/* Use internal silicon 32KHz oscillator */
+#undef CONFIG_CLOCK_SRC_EXTERNAL
+
+#ifndef __ASSEMBLER__
+
+enum adlrvp_i2c_channel {
+	I2C_CHAN_BATT_CHG,
+	I2C_CHAN_TCPC_0,
+	I2C_CHAN_TCPC_1,
+	I2C_CHAN_COUNT,
+};
+
+/* Map I2C port to controller */
+int board_i2c_p2c(int port);
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/adlrvpp_mchp1521/build.mk b/board/adlrvpp_mchp1521/build.mk
new file mode 100644
index 0000000000..b53a3bb479
--- /dev/null
+++ b/board/adlrvpp_mchp1521/build.mk
@@ -0,0 +1,18 @@
+# -*- makefile -*-
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Intel ADLRVP-P-DDR4-MEC1521 board-specific configuration
+#
+
+# the IC is Microchip MEC1521 with SRAM of 256KB
+# external SPI is 32MB
+# external clock is crystal
+CHIP:=mchp
+CHIP_FAMILY:=mec152x
+CHIP_VARIANT:=mec1521
+CHIP_SPI_SIZE_KB:=512
+BASEBOARD:=intelrvp
+
+board-y=board.o
diff --git a/board/adlrvpp_mchp1521/ec.tasklist b/board/adlrvpp_mchp1521/ec.tasklist
new file mode 100644
index 0000000000..bf4660ce03
--- /dev/null
+++ b/board/adlrvpp_mchp1521/ec.tasklist
@@ -0,0 +1,24 @@
+/*
+ * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Intel ADLRVP-P-DDR4-MEC1521 board-specific configuration.
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, VENTI_TASK_STACK_SIZE)
diff --git a/board/adlrvpp_mchp1521/gpio.inc b/board/adlrvpp_mchp1521/gpio.inc
new file mode 100644
index 0000000000..fd20e16568
--- /dev/null
+++ b/board/adlrvpp_mchp1521/gpio.inc
@@ -0,0 +1,314 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Intel ADLRVP-P-DDR4-MEC1521 board-specific configuration. */
+
+/*
+ * MEC152X data sheets GPIO numbers are OCTAL.
+ */
+
+/*
+ * MEC1521H-SZ MECC board SPI flash is connected to MEC1521H-SZ shared SPI port.
+ * GPIO055/SHD_CS0# pin is used to determine the boot source (eSPI Flash channel
+ * or shared SPI). On RVP, SHD_CS0_N is connected to Flash0 and SHD_CS1_N is
+ * connected to Flash1. Based on RVP design, Flash1 is meant for EC & Flash0
+ * for Coreboot.But, for MEC, it is mandatory to route CS0 to external Flash
+ * for EC to boot load the image. Hence, necessary rework must be taken care to
+ * route CS0 to external Flash1.
+ */
+/* Include common gpios needed for LFW loader and main process FW */
+#include "chip/mchp/lfw/gpio.inc"
+
+#include "baseboard/intelrvp/adlrvp_ioex_gpio.inc"
+
+/* As all signal names used here are supposed to match the schematic,
+ * few pin names may not indicate the real purpose.Refer comments to clarify the pin usage.
+ * Such pins are further renamed in board.h.
+ */
+
+/* Power sequencing interrupts */
+GPIO_INT(ALL_SYS_PWRGD,		PIN(057),	GPIO_INT_BOTH,	power_signal_interrupt)
+GPIO_INT(RSMRST_PWRGD_EC_N,	PIN(012),	GPIO_INT_BOTH,	power_signal_interrupt)
+GPIO_INT(PM_SLP_S0_R_N,		PIN(0243),	GPIO_INT_BOTH,	power_signal_interrupt)
+/* Below meaningless pin names are to match the schematic.*/
+/* PG_EC_DSW_PWROK signal */
+GPIO_INT(EC_TRACE_DATA_2,	PIN(0202),	GPIO_INT_BOTH,	power_signal_interrupt)
+/* VCCST_PWRGD signal */
+GPIO_INT(EC_TRACE_DATA_3,	PIN(0203),	GPIO_INT_BOTH,	power_signal_interrupt)
+GPIO_INT(PM_SLP_SUS_N,		PIN(000),	GPIO_INT_BOTH,	power_signal_interrupt)
+
+/* Button interrupts */
+GPIO_INT(VOL_UP_EC,		PIN(0242),	GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
+GPIO_INT(VOL_DOWN_EC,		PIN(0246),	GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)
+GPIO_INT(SMC_LID,		PIN(033),	GPIO_INT_BOTH | GPIO_PULL_UP,	lid_interrupt)
+/* Buffered power button input from
+ * PMIC-SLG7NT4192VTR / PWRBTN_EC_SILEGO_OUTPUT */
+GPIO_INT(PWRBTN_EC_IN_N,	PIN(0163),	GPIO_INT_BOTH,	power_button_interrupt)
+
+/* DC Jack presence coming from +VADP_OUT */
+/* DC_JACK_PRESENT */
+GPIO_INT(STD_ADP_PRSNT_EC,	PIN(052),	GPIO_INT_BOTH,	board_dc_jack_interrupt)
+/* AC Present */
+GPIO_INT(BC_ACOK_EC_IN,		PIN(0172),	GPIO_INT_BOTH,	extpower_interrupt)
+
+/* H1 */
+/* WP_L interrupt pin */
+GPIO_INT(EC_WAKE_CLK_R,		PIN(0241),	GPIO_INT_BOTH,	switch_interrupt)
+
+/* Case Closed Debug Mode */
+/* CCD_MODE_ODL pin */
+GPIO_INT(KBC_NUMLOCK,		PIN(0255),	GPIO_INT_BOTH,	board_connect_c0_sbu)
+
+/* USB-C interrupts */
+/* Below meaningless pin names are to match the schematic */
+/* TCPC & PPC Alerts */
+/* USBC_TCPC_ALRT_P0 */
+GPIO_INT(TYPEC_EC_SMBUS_ALERT_0_R,	PIN(0132),	GPIO_INT_BOTH,	tcpc_alert_event)
+/* USBC_TCPC_ALRT_P1 */
+GPIO_INT(TYPEC_EC_SMBUS_ALERT_1_R,	PIN(0245),	GPIO_INT_BOTH,	tcpc_alert_event)
+/* USBC_TCPC_PPC_ALRT_P0 */
+GPIO_INT(KBC_SCANOUT_15,	PIN(0151),	GPIO_INT_BOTH,	ppc_interrupt)
+/* USBC_TCPC_PPC_ALRT_P1 */
+GPIO_INT(KBC_CAPSLOCK,		PIN(0127),	GPIO_INT_BOTH,	ppc_interrupt)
+
+/* Sensor Interrupts */
+/* GMR_TABLET_MODE_GPIO_L */
+GPIO_INT(EC_SLATEMODE_HALLOUT_SNSR_R,	PIN(064),	GPIO_INT_BOTH |
+					GPIO_SEL_1P8V,	gmr_tablet_switch_isr)
+
+/* UART Interrupt */
+GPIO_INT(EC_UART_RX,	PIN(0145),	GPIO_INT_BOTH_DSLEEP | GPIO_PULL_UP,
+						uart_deepsleep_interrupt)
+
+/* Power sequencing GPIOs */
+GPIO(PM_RSMRST_R,	PIN(054),	GPIO_OUT_LOW)
+GPIO(PM_PWRBTN_N_R,	PIN(0101),	GPIO_ODR_HIGH)
+GPIO(EC_PCH_SPI_OE_N,	PIN(024),	GPIO_OUT_LOW)
+GPIO(SYS_PWROK_EC_R,	PIN(043),	GPIO_OUT_LOW)
+/* Below names are meaningless to match schematic */
+/* PCH_DSW_PWROK */
+GPIO(EC_TRACE_DATA_1,	PIN(0201),	GPIO_OUT_LOW)
+/* SYS_RESET_L */
+GPIO(DG2_PRESENT,	PIN(0165),	GPIO_ODR_HIGH)
+/* EN_PP3300_A */
+GPIO(EC_DS3_R,		PIN(0226),	GPIO_OUT_LOW)
+/* PCH_PWROK_EC is an input, as it is driven by the Silego chip on RVP */
+GPIO(EC_PM_PCH_PWROK,	PIN(0106),	GPIO_INPUT)
+UNIMPLEMENTED(EN_PP5000)
+
+/* Host communication GPIOs */
+/* PCH_WAKE_L pin*/
+GPIO(SMC_WAKE_SCI_N,	PIN(0114),	GPIO_ODR_HIGH)
+/* EC_INT_L pin */
+GPIO(EC_TRACE_DATA_0,	PIN(0200),	GPIO_ODR_HIGH)
+#ifndef CONFIG_HOSTCMD_ESPI
+GPIO(ESPI_RST_EC_R_N,	PIN(061),	GPIO_INPUT)
+#endif
+
+/* H1 Pins */
+/* PACKET_MODE_EN */
+GPIO(EC_TRACE_CLK,	PIN(0105),	GPIO_OUT_LOW)
+/* ENTERING_RW */
+GPIO(DNX_FORCE_RELOAD_EC_R,	PIN(0115),	GPIO_OUT_LOW)
+
+/* FAN control pins */
+GPIO(FAN_PWR_DISABLE,	PIN(060),	GPIO_OUT_LOW)
+
+/* EDP */
+GPIO(EC_EDP1_BKLT_EN,	PIN(0157),	GPIO_OUT_HIGH)
+
+/* LEDs */
+GPIO(PM_BAT_STATUS_LED2,	PIN(035),	GPIO_OUT_LOW)
+GPIO(PM_PWRBTN_LED,		PIN(0254),	GPIO_OUT_LOW)
+
+/* Battery present */
+GPIO(BATT_ID_R,		PIN(0162),	GPIO_INPUT)
+
+/* VTR2 STRAP PIN - GPIO0104_UART0_TX
+ * Voltage level strap used to determine,
+ * if shared flash interface must be configured
+ * for 3.3V or 1.8V.
+ * 1 = 3.3V operation
+ * 0 = 1.8V operation
+ */
+GPIO(EC_VTR2_STRAP,	PIN(0104),	GPIO_INPUT)
+
+/* Tap Controller select strap - GPIO0170_UART1_TX
+ * If any of the JTAG TAP controllers are used, GPIO170 must only
+ * be configured as an output to a VTRx powered external function.
+ * GPIO170 may only be configured as an input when
+ * the JTAG TAP controllers are not needed or when an external driver
+ * does not violate the Slave Select Timing.
+ */
+GPIO(EC_JTAG_STRAP,	PIN(0170),	GPIO_ODR_HIGH)
+
+/* I2C pins */
+/* I2C pins should be configure as inputs until I2C module is
+ * initialized. This will avoid driving the lines unintentionally.
+ */
+GPIO(SMB_BS_CLK,		PIN(004),	GPIO_INPUT)
+GPIO(SMB_BS_DATA,		PIN(003),	GPIO_INPUT)
+GPIO(TYPEC_EC_SMBUS1_CLK_EC,	PIN(0131),	GPIO_INPUT)
+GPIO(TYPEC_EC_SMBUS1_DATA_EC,	PIN(0130),	GPIO_INPUT)
+GPIO(TYPEC_EC_SMBUS3_DATA,	PIN(0142),	GPIO_INPUT)
+GPIO(TYPEC_EC_SMBUS3_CLK,	PIN(0141),	GPIO_INPUT)
+
+/* Unused Pins */
+/* These have different meaning on RVP for alternate OS
+ * support.Hence, keep them as input.
+ */
+GPIO(PROCHOT_EC_R,		PIN(0253),	GPIO_INPUT)
+GPIO(BC_PROCHOT_EC_N,		PIN(034),	GPIO_INPUT)
+GPIO(EC_PEG_PLI_N_DG2,		PIN(036),	GPIO_INPUT)
+GPIO(PEG_PIM_DG2,		PIN(0240),	GPIO_INPUT)
+GPIO(KBD_BKLT_CTRL,		PIN(014),	GPIO_INPUT)
+GPIO(STD_ADPT_CNTRL_GPIO_R,	PIN(0171),	GPIO_INPUT)
+GPIO(SAF_G3_DETECT,		PIN(013),	GPIO_INPUT)
+GPIO(EC_GPIO015_PWM7,		PIN(015),	GPIO_INPUT)
+GPIO(EC_GPPC_B14,		PIN(0244),	GPIO_INPUT)
+GPIO(SX_EXIT_HOLDOFF_N,		PIN(0175),	GPIO_INPUT)
+GPIO(MIC_PRIVACY_EC,		PIN(0100),	GPIO_INPUT)
+GPIO(MIC_PRIVACY_SWITCH,	PIN(011),	GPIO_INPUT)
+GPIO(PECI_MUX_CTRL_ER_INT,	PIN(025),	GPIO_INPUT)
+GPIO(PEG_RTD3_COLD_MOD_SW_R,	PIN(0156),	GPIO_INPUT)
+GPIO(H_CATERR_EC_N,		PIN(0153),	GPIO_INPUT)
+GPIO(PM_BATLOW_N,		PIN(0140),	GPIO_INPUT)
+GPIO(HOME_BTN_EC_RVP_AEP_ID,	PIN(023),	GPIO_INPUT)
+GPIO(CPU_C10_GATE_N_R,		PIN(022),	GPIO_INPUT)
+GPIO(VREF_VTT,			PIN(044),	GPIO_INPUT)
+GPIO(HB_NVDC_SEL,		PIN(0161), 	GPIO_INPUT)
+GPIO(EC_VCI_OUT_WAKE_R,		PIN(0250),	GPIO_INPUT)
+GPIO(PM_SLP_S0_CS_N,		PIN(0221),	GPIO_INPUT)
+GPIO(GPPC_E7_EC_SMI_N_R,	PIN(0102),	GPIO_INPUT)
+GPIO(TC_RETIMER_FORCE_PWR_BTP_EC_R,	PIN(0222),	GPIO_INPUT)
+
+/* Alternate functions */
+
+/* Alternate functions GPIO definitions */
+
+/*
+ * MCHP has 6 banks/ports each containing 32 GPIO's.
+ * Each bank/port is connected to a GIRQ.
+ * Port numbering Example:
+ * GPIO_015 = 13 decimal. Port/bank = 13/32 = 0, bit = 13 % 32 = 13
+ * GPIO_0123 = 83 decimal. Port/bank = 83/32 = 2, bit = 83 % 32 = 19
+ * OR port = 0123 >> 5, bit = 0123 & 037(0x1F) = 023 = 19 decimal.
+ */
+
+/*
+ * Configure I2C as alternate function
+ * I2C00_SDA = GPIO_0003(Bank=0, bit=3) Func1
+ * I2C00_SCL = GPIO_0004(Bank=0, bit=4) Func1
+ * I2C01_SDA = GPIO_0130(Bank=2, bit=24) Func1
+ * I2C01_SCL = GPIO_0131(Bank=2, bit=25) Func1
+ * I2C04_SDA = GPIO_0143(Bank=3, bit=3) Func1
+ * I2C04_SCL = GPIO_0144(Bank=3, bit=4) Func1
+ * I2C05_SDA = GPIO_0141(Bank=3, bit=1) Func1
+ * I2C05_SDL = GPIO_0142(Bank=3, bit=2) Func1
+ */
+ALTERNATE(PIN_MASK(0, 0x00000018),	GPIO_ALT_FUNC_1,	MODULE_I2C,
+								GPIO_ODR_HIGH)
+ALTERNATE(PIN_MASK(2, 0x03000000),	GPIO_ALT_FUNC_1,	MODULE_I2C,
+								GPIO_ODR_HIGH)
+ALTERNATE(PIN_MASK(3, 0x0000001E),	GPIO_ALT_FUNC_1,	MODULE_I2C,
+								GPIO_ODR_HIGH)
+
+/* Alternate pins for ADC */
+/*
+ * ADC04 - ADC07
+ * GPIO_0204 Func 1 = ADC04 - AMBIET_THERM_IN0
+ * GPIO_0205 Func 1 = ADC05 - VR_THERM_IN
+ * GPIO_0206 Func 1 = ADC06 - DDR_THERM_IN
+ * GPIO_0207 Func 1 = ADC07 - SKIN_THERM_IN1
+ * Bank 4 bits[4:5:6:7]
+ */
+ALTERNATE(PIN_MASK(4, 0x00000F0),	GPIO_ALT_FUNC_1,	MODULE_ADC,
+								GPIO_ANALOG)
+/*
+ * VREF2_ADC_R
+ * GPIO_067 Func 1 = VREF2_ADC
+ * Bank 1 bit [23]
+ */
+ALTERNATE(PIN_MASK(1, 0x0800000),	GPIO_ALT_FUNC_1,	MODULE_ADC,
+								GPIO_ANALOG)
+
+/* Alternate pins for FAN */
+/*
+ * GPIO_050 Func 1 = TACH0 - CPU_TACHO_FAN
+ * GPIO_053 Func 1 = PWM0 - CPU_PWM_FAN
+ * Bank 1 bits[8:11]
+ */
+ALTERNATE(PIN_MASK(1, 0x0000900),	GPIO_ALT_FUNC_1,	MODULE_PWM,
+								GPIO_FLAG_NONE)
+
+/* KB pins */
+/*
+ * MEC1521H-SZ (144 pin package)
+ * KSO00 = GPIO_0040 Func2 bank 1 bit 0
+ * KSO01 = GPIO_0045 Func1 bank 1 bit 5
+ * KSO02 = GPIO_0046 Func1 bank 1 bit 6
+ * KSO03 = GPIO_0047 Func1 bank 1 bit 7
+ * KSO04 = GPIO_0107 Func2 bank 2 bit 7
+ * KSO05 = GPIO_0112 Func1 bank 2 bit 10
+ * KSO06 = GPIO_0113 Func1 bank 2 bit 11
+ * KSO07 = GPIO_0120 Func1 bank 2 bit 16
+ * KSO08 = GPIO_0121 Func2 bank 2 bit 17
+ * KSO09 = GPIO_0122 Func2 bank 2 bit 18
+ * KSO10 = GPIO_0123 Func2 bank 2 bit 19
+ * KSO11 = GPIO_0124 Func2 bank 2 bit 20
+ * KSO12 = GPIO_0125 Func2 bank 2 bit 21
+ * For 8x16 test keyboard add KSO13 - KSO15
+ * KSO13 = GPIO_0126 Func2 bank 2 bit 22
+ * KSO14 = GPIO_0152 Func1 bank 3 bit 10
+ * KSO15 = GPIO_0151 Func2 bank 3 bit 9
+ *
+ * KSI0 = GPIO_0017 Func1 bank 0 bit 15
+ * KSI1 = GPIO_0020 Func1 bank 0 bit 16
+ * KSI2 = GPIO_0021 Func1 bank 0 bit 17
+ * KSI3 = GPIO_0026 Func1 bank 0 bit 22
+ * KSI4 = GPIO_0027 Func1 bank 0 bit 23
+ * KSI5 = GPIO_0030 Func1 bank 0 bit 24
+ * KSI6 = GPIO_0031 Func1 bank 0 bit 25
+ * KSI7 = GPIO_0032 Func1 bank 0 bit 26
+ */
+/* KSO 0 Bank 1, Func2, bit 0 */
+ALTERNATE(PIN_MASK(1, 0x01),		2,	MODULE_KEYBOARD_SCAN,
+							GPIO_ODR_HIGH)
+
+#ifdef CONFIG_KEYBOARD_COL2_INVERTED
+/* KSO 1-3 Bank 1, Func1, bits 5-7 */
+ALTERNATE(PIN_MASK(1, 0xA0),		1,	MODULE_KEYBOARD_SCAN,
+							GPIO_ODR_HIGH)
+GPIO(KBD_KSO2,		PIN(046),	GPIO_OUT_LOW)
+#else
+/* KSO 1-3 Bank 1, Func1, bits 5-7 */
+ALTERNATE(PIN_MASK(1, 0xE0),		1,	MODULE_KEYBOARD_SCAN,
+							GPIO_ODR_HIGH)
+#endif
+
+/* KSO 4, 8-12 Bank 2, Func2, bits 7, 17-21 */
+ALTERNATE(PIN_MASK(2, 0x003E0080),	2,	MODULE_KEYBOARD_SCAN,
+							GPIO_ODR_HIGH)
+/* KSO 5-7, Bank 2, Func1, bits 10-11, 16 */
+ALTERNATE(PIN_MASK(2, 0x00010C00),	1,	MODULE_KEYBOARD_SCAN,
+							GPIO_ODR_HIGH)
+
+/* KSI 0-7, Bank 0, Func1, bit 15-17, 22-26 */
+ALTERNATE(PIN_MASK(0, 0x07C38000),	1,	MODULE_KEYBOARD_SCAN,
+						(GPIO_INPUT | GPIO_PULL_UP))
+
+/*
+ * ESPI_RST_EC_R_N# - GPIO_0061 Func 1, Bank 1 bit[17]
+ * ESPI_ALERT0_EC_R_N# - GPIO_0063 Func 1, Bank 1 bit[19]
+ * ESPI_CLK_EC_R    - GPIO_0065 Func 1, Bank 1 bit[21]
+ * ESPI_CS0_EC_R_N# - GPIO_0066 Func 1, Bank 1 bit[22]
+ * ESPI_IO0_EC_R    - GPIO_0070 Func 1, Bank 1 bit[24]
+ * ESPI_IO1_EC_R    - GPIO_0071 Func 1, Bank 1 bit[25]
+ * ESPI_IO2_EC_R    - GPIO_0072 Func 1, Bank 1 bit[26]
+ * ESPI_IO3_EC_R    - GPIO_0073 Func 1, Bank 1 bit[27]
+ */
+ALTERNATE(PIN_MASK(1, 0x0F6A0000),	1,	MODULE_LPC,	GPIO_FLAG_NONE)
diff --git a/board/adlrvpp_mchp1521/vif_override.xml b/board/adlrvpp_mchp1521/vif_override.xml
new file mode 100644
index 0000000000..32736caf64
--- /dev/null
+++ b/board/adlrvpp_mchp1521/vif_override.xml
@@ -0,0 +1,3 @@
+<!-- Add VIF field overrides here. See genvif.c and the Vendor Info File
+     Definition from the USB-IF.
+-->