zephyr: dts: Move cros_kb_raw node to npcx.dtsi

cros-kb-raw@400a3000 is a npcx chip node. Move it to npcx.dtsi &
overwrite the pin control setting in the corresponding dts file.

For the status property in cros_kb_raw, npcx kbsan only has one
hardware instance. NPCX cros_kb_raw driver doesn't use status property
to enable the device. Remove status setting in cros_kb_raw node.

Compared with 'gpio.inc' for boards based on trogdor, the keyboard
doesn't use KSO13, 14. Remove KSO13, 14 in 'trogdor.dts'.

BUG=none
BRANCH=none
TEST=zmake testall
TEST=Check all keys work on volteer & lazor by "ksstate on".

Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com>
Change-Id: Ie352b91ee13b18fa9079001ab7c3685f059ba299
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2931750
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>

3 files changed, 89 insertions, 75 deletions

diff --git a/zephyr/include/cros/nuvoton/npcx.dtsi b/zephyr/include/cros/nuvoton/npcx.dtsi
index a0b56e5018..743cbf76fc 100644
--- a/zephyr/include/cros/nuvoton/npcx.dtsi
+++ b/zephyr/include/cros/nuvoton/npcx.dtsi
@@ -73,6 +73,46 @@
 			label = "BBRAM";
 		};
 
+		cros_kb_raw: cros-kb-raw@400a3000 {
+			compatible = "nuvoton,npcx-cros-kb-raw";
+			reg = <0x400a3000 0x2000>;
+			label = "CROS_KB_RAW_0";
+			interrupts = <49 4>;
+			clocks = <&pcc NPCX_CLOCK_BUS_APB1 NPCX_PWDWN_CTL1 0>;
+			/*
+			 * No KSO2 (It's inverted and implemented by GPIO for
+			 * CONFIG_KEYBOARD_COL2_INVERTED.)
+			 */
+			pinctrl-0 = <&alt7_no_ksi0_sl
+				     &alt7_no_ksi1_sl
+				     &alt7_no_ksi2_sl
+				     &alt7_no_ksi3_sl
+				     &alt7_no_ksi4_sl
+				     &alt7_no_ksi5_sl
+				     &alt7_no_ksi6_sl
+				     &alt7_no_ksi7_sl
+				     &alt8_no_kso00_sl
+				     &alt8_no_kso01_sl
+				     &alt8_no_kso03_sl
+				     &alt8_no_kso04_sl
+				     &alt8_no_kso05_sl
+				     &alt8_no_kso06_sl
+				     &alt8_no_kso07_sl
+				     &alt9_no_kso08_sl
+				     &alt9_no_kso09_sl
+				     &alt9_no_kso10_sl
+				     &alt9_no_kso11_sl
+				     &alt9_no_kso12_sl
+				     &alt9_no_kso13_sl
+				     &alt9_no_kso14_sl
+				     &alt9_no_kso15_sl
+				     &alta_no_kso16_sl
+				     &alta_no_kso17_sl
+				     >;
+			wui_maps = <&wui_io31 &wui_io30 &wui_io27 &wui_io26
+				    &wui_io25 &wui_io24 &wui_io23 &wui_io22>;
+		};
+
 		mtc: mtc@400b7000 {
 			compatible = "nuvoton,npcx-cros-mtc";
 			reg = <0x400b7000 0x2000>;
diff --git a/zephyr/projects/trogdor/boards/arm/trogdor/trogdor.dts b/zephyr/projects/trogdor/boards/arm/trogdor/trogdor.dts
index 2c66da1ae5..7e3100a0fe 100644
--- a/zephyr/projects/trogdor/boards/arm/trogdor/trogdor.dts
+++ b/zephyr/projects/trogdor/boards/arm/trogdor/trogdor.dts
@@ -140,43 +140,6 @@
 		/* I2C_SDA0 & SCL0 */
 		lvol-io-pads = <&lvol_iob4 &lvol_iob5>;
 	};
-
-	soc {
-		cros_kb_raw: cros-kb-raw@400a3000 {
-			compatible = "nuvoton,npcx-cros-kb-raw";
-			reg = <0x400a3000 0x2000>;
-			label = "CROS_KB_RAW_0";
-			interrupts = <49 4>;
-			clocks = <&pcc NPCX_CLOCK_BUS_APB1 NPCX_PWDWN_CTL1 0>;
-			/* No KSO2 (it's inverted and implemented by GPIO) */
-			pinctrl-0 = <&alt7_no_ksi0_sl /* KSI0 PIN31 */
-				     &alt7_no_ksi1_sl /* KSI1 PIN30 */
-				     &alt7_no_ksi2_sl /* KSI2 PIN27 */
-				     &alt7_no_ksi3_sl /* KSI3 PIN26 */
-				     &alt7_no_ksi4_sl /* KSI4 PIN25 */
-				     &alt7_no_ksi5_sl /* KSI5 PIN24 */
-				     &alt7_no_ksi6_sl /* KSI6 PIN23 */
-				     &alt7_no_ksi7_sl /* KSI7 PIN22 */
-				     &alt8_no_kso00_sl /* KSO00 PIN21 */
-				     &alt8_no_kso01_sl /* KSO01 PIN20 */
-				     &alt8_no_kso03_sl /* KSO03 PIN16 */
-				     &alt8_no_kso04_sl /* KSO04 PIN15 */
-				     &alt8_no_kso05_sl /* KSO05 PIN14 */
-				     &alt8_no_kso06_sl /* KSO06 PIN13 */
-				     &alt8_no_kso07_sl /* KSO07 PIN12 */
-				     &alt9_no_kso08_sl /* KSO08 PIN11 */
-				     &alt9_no_kso09_sl /* KSO09 PIN10 */
-				     &alt9_no_kso10_sl /* KSO10 PIN07 */
-				     &alt9_no_kso11_sl /* KSO11 PIN06 */
-				     &alt9_no_kso12_sl /* KSO12 PIN05 */
-				     &alt9_no_kso13_sl /* KSO13 PIN04 */
-				     &alt9_no_kso14_sl /* KSO14 PIN82 */
-				     >;
-			wui_maps = <&wui_io31 &wui_io30 &wui_io27 &wui_io26
-				    &wui_io25 &wui_io24 &wui_io23 &wui_io22>;
-			status = "disabled";
-		};
-	};
 };
 
 &uart1 {
@@ -234,3 +197,28 @@
 &adc0 {
 	status = "okay";
 };
+
+&cros_kb_raw {
+	/* No KSO2 (it's inverted and implemented by GPIO) */
+	pinctrl-0 = <&alt7_no_ksi0_sl
+		     &alt7_no_ksi1_sl
+		     &alt7_no_ksi2_sl
+		     &alt7_no_ksi3_sl
+		     &alt7_no_ksi4_sl
+		     &alt7_no_ksi5_sl
+		     &alt7_no_ksi6_sl
+		     &alt7_no_ksi7_sl
+		     &alt8_no_kso00_sl
+		     &alt8_no_kso01_sl
+		     &alt8_no_kso03_sl
+		     &alt8_no_kso04_sl
+		     &alt8_no_kso05_sl
+		     &alt8_no_kso06_sl
+		     &alt8_no_kso07_sl
+		     &alt9_no_kso08_sl
+		     &alt9_no_kso09_sl
+		     &alt9_no_kso10_sl
+		     &alt9_no_kso11_sl
+		     &alt9_no_kso12_sl
+		     >;
+};
diff --git a/zephyr/projects/volteer/boards/arm/volteer/volteer.dts b/zephyr/projects/volteer/boards/arm/volteer/volteer.dts
index 8cd5978d5e..845d2abaaa 100644
--- a/zephyr/projects/volteer/boards/arm/volteer/volteer.dts
+++ b/zephyr/projects/volteer/boards/arm/volteer/volteer.dts
@@ -173,43 +173,6 @@
 		psl-in-pads = <&psl_in1 &psl_in2 &psl_in3 &psl_in4>;
 	};
 
-	soc {
-		cros_kb_raw: cros-kb-raw@400a3000 {
-			compatible = "nuvoton,npcx-cros-kb-raw";
-			reg = <0x400a3000 0x2000>;
-			label = "CROS_KB_RAW_0";
-			interrupts = <49 4>;
-			clocks = <&pcc NPCX_CLOCK_BUS_APB1 NPCX_PWDWN_CTL1 0>;
-			/* No KSO2 (it's inverted and implemented by GPIO.) */
-			pinctrl-0 = <&alt7_no_ksi0_sl /* KSI0 PIN31 */
-				     &alt7_no_ksi1_sl /* KSI1 PIN30 */
-				     &alt7_no_ksi2_sl /* KSI2 PIN27 */
-				     &alt7_no_ksi3_sl /* KSI3 PIN26 */
-				     &alt7_no_ksi4_sl /* KSI4 PIN25 */
-				     &alt7_no_ksi5_sl /* KSI5 PIN24 */
-				     &alt7_no_ksi6_sl /* KSI6 PIN23 */
-				     &alt7_no_ksi7_sl /* KSI7 PIN22 */
-				     &alt8_no_kso00_sl /* KSO00 PIN21 */
-				     &alt8_no_kso01_sl /* KSO01 PIN20 */
-				     &alt8_no_kso03_sl /* KSO03 PIN16 */
-				     &alt8_no_kso04_sl /* KSO04 PIN15 */
-				     &alt8_no_kso05_sl /* KSO05 PIN14 */
-				     &alt8_no_kso06_sl /* KSO06 PIN13 */
-				     &alt8_no_kso07_sl /* KSO07 PIN12 */
-				     &alt9_no_kso08_sl /* KSO08 PIN11 */
-				     &alt9_no_kso09_sl /* KSO09 PIN10 */
-				     &alt9_no_kso10_sl /* KSO10 PIN07 */
-				     &alt9_no_kso11_sl /* KSO11 PIN06 */
-				     &alt9_no_kso12_sl /* KSO12 PIN05 */
-				     &alt9_no_kso13_sl /* KSO13 PIN04 */
-				     &alt9_no_kso14_sl /* KSO14 PIN82 */
-				     >;
-			wui_maps = <&wui_io31 &wui_io30 &wui_io27 &wui_io26
-				    &wui_io25 &wui_io24 &wui_io23 &wui_io22>;
-			status = "disabled";
-		};
-	};
-
 	/*
 	 * The CBI Second Source Factory Cache (SSFC) layout definition.
 	 * Specific fields values are defined per board.
@@ -276,7 +239,30 @@
 };
 
 &cros_kb_raw {
-	status = "okay";
+	/* No KSO2 (it's inverted and implemented by GPIO) */
+	pinctrl-0 = <&alt7_no_ksi0_sl
+		     &alt7_no_ksi1_sl
+		     &alt7_no_ksi2_sl
+		     &alt7_no_ksi3_sl
+		     &alt7_no_ksi4_sl
+		     &alt7_no_ksi5_sl
+		     &alt7_no_ksi6_sl
+		     &alt7_no_ksi7_sl
+		     &alt8_no_kso00_sl
+		     &alt8_no_kso01_sl
+		     &alt8_no_kso03_sl
+		     &alt8_no_kso04_sl
+		     &alt8_no_kso05_sl
+		     &alt8_no_kso06_sl
+		     &alt8_no_kso07_sl
+		     &alt9_no_kso08_sl
+		     &alt9_no_kso09_sl
+		     &alt9_no_kso10_sl
+		     &alt9_no_kso11_sl
+		     &alt9_no_kso12_sl
+		     &alt9_no_kso13_sl
+		     &alt9_no_kso14_sl
+		     >;
 };
 
 &adc0 {