diff options
| author | Devin Lu <Devin.Lu@quantatw.com> | 2021-06-18 10:48:49 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-06-25 02:02:48 +0000 |
| commit | 4a03fa567cf62f82e61324c8836f2a36ed1679bd (patch) | |
| tree | 15df334ac469e2bb580cd39e77ce74f3fe87abd2 | |
| parent | 2ffc903ae4c772f2b12897634e24fa8e0c1791ef (diff) | |
| download | chrome-ec-4a03fa567cf62f82e61324c8836f2a36ed1679bd.tar.gz | |
ps8815: Add displayport related settings
This patch adds one more register for displayport related settings
with ps8815.
BUG=b:189587527
BRANCH=firmware-volteer-13672.B-main
TEST=make buildall
Signed-off-by: Devin Lu <Devin.Lu@quantatw.com>
Change-Id: If79dce87a581923bb1f382786042018bc37c737a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2972021
Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
| -rw-r--r-- | driver/tcpm/ps8xxx.h | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/driver/tcpm/ps8xxx.h b/driver/tcpm/ps8xxx.h index 514579ecca..933ec53ba9 100644 --- a/driver/tcpm/ps8xxx.h +++ b/driver/tcpm/ps8xxx.h @@ -59,6 +59,27 @@ #define PS8815_P1_REG_HW_REVISION 0xF0 /* + * Below register is defined from Parade PS8815 Register Table, + * See b:189587527 for more detail. + */ + +/* Displayport related settings */ +#define PS8815_REG_DP_EQ_SETTING 0xF8 +#define PS8815_AUTO_EQ_DISABLE BIT(7) +#define PS8815_DPEQ_LOSS_UP_21DB 0x09 +#define PS8815_DPEQ_LOSS_UP_20DB 0x08 +#define PS8815_DPEQ_LOSS_UP_19DB 0x07 +#define PS8815_DPEQ_LOSS_UP_18DB 0x06 +#define PS8815_DPEQ_LOSS_UP_17DB 0x05 +#define PS8815_DPEQ_LOSS_UP_16DB 0x04 +#define PS8815_DPEQ_LOSS_UP_13DB 0x03 +#define PS8815_DPEQ_LOSS_UP_12DB 0x02 +#define PS8815_DPEQ_LOSS_UP_10DB 0x01 +#define PS8815_DPEQ_LOSS_UP_9DB 0x00 +#define PS8815_REG_DP_EQ_COMP_SHIFT 3 +#define PS8815_AUX_INTERCEPTION_DISABLE BIT(1) + +/* * PS8805 GPIO control register. Note the device I2C address of 0x1A is * independent of the ADDR pin on the chip, and not the same address being used * for TCPCI functions. |