chip/mt_scp: add mt8195 irq support

Update IRQ definition for mt8195 and move IRQ definitions to
chip-specific folder.

BRANCH=none
BUG=b:189300514
TEST=make BOARD=asurada_scp &&
     make BOARD=cherry_scp

Change-Id: I3bb4d97e374328fbe86d537b14cce11322365c10
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2940337
Tested-by: Tzung-Bi Shih <tzungbi@chromium.org>
Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org>
Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org>

4 files changed, 451 insertions, 113 deletions

diff --git a/chip/mt_scp/mt8192/intc.h b/chip/mt_scp/mt8192/intc.h
new file mode 100644
index 0000000000..b2035a9025
--- /dev/null
+++ b/chip/mt_scp/mt8192/intc.h
@@ -0,0 +1,123 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_INTC_H
+#define __CROS_EC_INTC_H
+
+/* INTC */
+#define SCP_INTC_GRP_LEN		3
+#define SCP_INTC_IRQ_COUNT		96
+
+/* IRQ numbers */
+#define SCP_IRQ_GIPC_IN0		0
+#define SCP_IRQ_GIPC_IN1		1
+#define SCP_IRQ_GIPC_IN2		2
+#define SCP_IRQ_GIPC_IN3		3
+/* 4 */
+#define SCP_IRQ_SPM			4
+#define SCP_IRQ_AP_CIRQ			5
+#define SCP_IRQ_EINT			6
+#define SCP_IRQ_PMIC			7
+/* 8 */
+#define SCP_IRQ_UART0_TX		8
+#define SCP_IRQ_UART1_TX		9
+#define SCP_IRQ_I2C0			10
+#define SCP_IRQ_I2C1_0			11
+/* 12 */
+#define SCP_IRQ_BUS_DBG_TRACKER		12
+#define SCP_IRQ_CLK_CTRL		13
+#define SCP_IRQ_VOW			14
+#define SCP_IRQ_TIMER0			15
+/* 16 */
+#define SCP_IRQ_TIMER1			16
+#define SCP_IRQ_TIMER2			17
+#define SCP_IRQ_TIMER3			18
+#define SCP_IRQ_TIMER4			19
+/* 20 */
+#define SCP_IRQ_TIMER5			20
+#define SCP_IRQ_OS_TIMER		21
+#define SCP_IRQ_UART0_RX		22
+#define SCP_IRQ_UART1_RX		23
+/* 24 */
+#define SCP_IRQ_GDMA			24
+#define SCP_IRQ_AUDIO			25
+#define SCP_IRQ_MD_DSP			26
+#define SCP_IRQ_ADSP			27
+/* 28 */
+#define SCP_IRQ_CPU_TICK		28
+#define SCP_IRQ_SPI0			29
+#define SCP_IRQ_SPI1			30
+#define SCP_IRQ_SPI2			31
+/* 32 */
+#define SCP_IRQ_NEW_INFRA_SYS_CIRQ	32
+#define SCP_IRQ_DBG			33
+#define SCP_IRQ_CCIF0			34
+#define SCP_IRQ_CCIF1			35
+/* 36 */
+#define SCP_IRQ_CCIF2			36
+#define SCP_IRQ_WDT			37
+#define SCP_IRQ_USB0			38
+#define SCP_IRQ_USB1			39
+/* 40 */
+#define SCP_IRQ_DPMAIF			40
+#define SCP_IRQ_INFRA			41
+#define SCP_IRQ_CLK_CTRL_CORE		42
+#define SCP_IRQ_CLK_CTRL2_CORE		43
+/* 44 */
+#define SCP_IRQ_CLK_CTRL2		44
+#define SCP_IRQ_GIPC_IN4		45 /* HALT */
+#define SCP_IRQ_PERIBUS_TIMEOUT		46
+#define SCP_IRQ_INFRABUS_TIMEOUT	47
+/* 48 */
+#define SCP_IRQ_MET0			48
+#define SCP_IRQ_MET1			49
+#define SCP_IRQ_MET2			50
+#define SCP_IRQ_MET3			51
+/* 52 */
+#define SCP_IRQ_AP_WDT			52
+#define SCP_IRQ_L2TCM_SEC_VIO		53
+#define SCP_IRQ_CPU_TICK1		54
+#define SCP_IRQ_MAD_DATAIN		55
+/* 56 */
+#define SCP_IRQ_I3C0_IBI_WAKE		56
+#define SCP_IRQ_I3C1_IBI_WAKE		57
+#define SCP_IRQ_I3C2_IBI_WAKE		58
+#define SCP_IRQ_APU_ENGINE		59
+/* 60 */
+#define SCP_IRQ_MBOX0			60
+#define SCP_IRQ_MBOX1			61
+#define SCP_IRQ_MBOX2			62
+#define SCP_IRQ_MBOX3			63
+/* 64 */
+#define SCP_IRQ_MBOX4			64
+#define SCP_IRQ_SYS_CLK_REQ		65
+#define SCP_IRQ_BUS_REQ			66
+#define SCP_IRQ_APSRC_REQ		67
+/* 68 */
+#define SCP_IRQ_APU_MBOX		68
+#define SCP_IRQ_DEVAPC_SECURE_VIO	69
+/* 72 */
+/* 76 */
+#define SCP_IRQ_I2C1_2			78
+#define SCP_IRQ_I2C2			79
+/* 80 */
+#define SCP_IRQ_AUD2AUDIODSP		80
+#define SCP_IRQ_AUD2AUDIODSP_2		81
+#define SCP_IRQ_CONN2ADSP_A2DPOL	82
+#define SCP_IRQ_CONN2ADSP_BTCVSD	83
+/* 84 */
+#define SCP_IRQ_CONN2ADSP_BLEISO	84
+#define SCP_IRQ_PCIE2ADSP		85
+#define SCP_IRQ_APU2ADSP_ENGINE		86
+#define SCP_IRQ_APU2ADSP_MBOX		87
+/* 88 */
+#define SCP_IRQ_CCIF3			88
+#define SCP_IRQ_I2C_DMA0		89
+#define SCP_IRQ_I2C_DMA1		90
+#define SCP_IRQ_I2C_DMA2		91
+/* 92 */
+#define SCP_IRQ_I2C_DMA3		92
+
+#endif /* __CROS_EC_INTC_H */
diff --git a/chip/mt_scp/mt8195/intc.h b/chip/mt_scp/mt8195/intc.h
new file mode 100644
index 0000000000..f098229e8c
--- /dev/null
+++ b/chip/mt_scp/mt8195/intc.h
@@ -0,0 +1,163 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_INTC_H
+#define __CROS_EC_INTC_H
+
+/* INTC */
+#define SCP_INTC_IRQ_POL3		0xfffffff3
+#define SCP_INTC_GRP_LEN		4
+#define SCP_INTC_IRQ_COUNT		127
+
+/* IRQ numbers */
+#define SCP_IRQ_GIPC_IN0		0
+#define SCP_IRQ_GIPC_IN1		1
+#define SCP_IRQ_GIPC_IN2		2
+#define SCP_IRQ_GIPC_IN3		3
+/* 4 */
+#define SCP_IRQ_SPM			4
+#define SCP_IRQ_AP_CIRQ			5
+#define SCP_IRQ_EINT			6
+#define SCP_IRQ_PMIC			7
+/* 8 */
+#define SCP_IRQ_UART0_TX		8
+#define SCP_IRQ_UART1_TX		9
+#define SCP_IRQ_I2C0			10
+#define SCP_IRQ_I2C1_0			11
+/* 12 */
+#define SCP_IRQ_BUS_DBG_TRACKER		12
+#define SCP_IRQ_CLK_CTRL		13
+#define SCP_IRQ_VOW			14
+#define SCP_IRQ_TIMER0			15
+/* 16 */
+#define SCP_IRQ_TIMER1			16
+#define SCP_IRQ_TIMER2			17
+#define SCP_IRQ_TIMER3			18
+#define SCP_IRQ_TIMER4			19
+/* 20 */
+#define SCP_IRQ_TIMER5			20
+#define SCP_IRQ_OS_TIMER		21
+#define SCP_IRQ_UART0_RX		22
+#define SCP_IRQ_UART1_RX		23
+/* 24 */
+#define SCP_IRQ_GDMA			24
+#define SCP_IRQ_AUDIO			25
+#define SCP_IRQ_MD_DSP			26
+#define SCP_IRQ_ADSP			27
+/* 28 */
+#define SCP_IRQ_CPU_TICK		28
+#define SCP_IRQ_SPI0			29
+#define SCP_IRQ_SPI1			30
+#define SCP_IRQ_SPI2			31
+/* 32 */
+#define SCP_IRQ_NEW_INFRA_SYS_CIRQ	32
+#define SCP_IRQ_DBG			33
+#define SCP_IRQ_GCE			34
+#define SCP_IRQ_MDP_GCE			35
+/* 36 */
+#define SCP_IRQ_VDEC			36
+#define SCP_IRQ_WDT			37
+#define SCP_IRQ_VDEC_LAT		38
+#define SCP_IRQ_VDEC1			39
+/* 40 */
+#define SCP_IRQ_VDEC1_LAT		40
+#define SCP_IRQ_INFRA			41
+#define SCP_IRQ_CLK_CTRL_CORE		42
+#define SCP_IRQ_CLK_CTRL2_CORE		43
+/* 44 */
+#define SCP_IRQ_CLK_CTRL2		44
+#define SCP_IRQ_GIPC_IN4		45 /* HALT */
+#define SCP_IRQ_PERIBUS_TIMEOUT		46
+#define SCP_IRQ_INFRABUS_TIMEOUT	47
+/* 48 */
+#define SCP_IRQ_MET0			48
+#define SCP_IRQ_MET1			49
+#define SCP_IRQ_MET2			50
+#define SCP_IRQ_MET3			51
+/* 52 */
+#define SCP_IRQ_AP_WDT			52
+#define SCP_IRQ_L2TCM_SEC_VIO		53
+#define SCP_IRQ_VDEC_INT_LINE_CNT	54
+#define SCP_IRQ_VOW_DATAIN		55
+/* 56 */
+#define SCP_IRQ_I3C0_IBI_WAKE		56
+#define SCP_IRQ_I3C1_IBI_WAKE		57
+#define SCP_IRQ_VENC			58
+#define SCP_IRQ_APU_ENGINE		59
+/* 60 */
+#define SCP_IRQ_MBOX0			60
+#define SCP_IRQ_MBOX1			61
+#define SCP_IRQ_MBOX2			62
+#define SCP_IRQ_MBOX3			63
+/* 64 */
+#define SCP_IRQ_MBOX4			64
+#define SCP_IRQ_SYS_CLK_REQ		65
+#define SCP_IRQ_BUS_REQ			66
+#define SCP_IRQ_APSRC_REQ		67
+/* 68 */
+#define SCP_IRQ_APU_MBOX		68
+#define SCP_IRQ_DEVAPC_SECURE_VIO	69
+#define SCP_IRQ_CAMSYS_29		70
+#define SCP_IRQ_CAMSYS_28		71
+/* 72 */
+#define SCP_IRQ_CAMSYS_5		72
+#define SCP_IRQ_CAMSYS_4		73
+#define SCP_IRQ_CAMSYS_3		74
+#define SCP_IRQ_CAMSYS_2		75
+/* 76 */
+#define SCP_IRQ_HDMIRX_PM_DVI_SQH	76
+#define SCP_IRQ_HDMIRX_RESERVED		77
+#define SCP_IRQ_NNA0_0			78
+#define SCP_IRQ_NNA0_1			79
+/* 80 */
+#define SCP_IRQ_NNA0_2			80
+#define SCP_IRQ_NNA1_0			81
+#define SCP_IRQ_NNA1_1			82
+#define SCP_IRQ_NNA1_2			83
+/* 84 */
+#define SCP_IRQ_JPEGENC			84
+#define SCP_IRQ_JPEGDEC			85
+#define SCP_IRQ_JPEGDEC_C2		86
+#define SCP_IRQ_VENC_C1			87
+/* 88 */
+#define SCP_IRQ_JPEGENC_C1		88
+#define SCP_IRQ_JPEGDEC_C1		89
+#define SCP_IRQ_HDMITX			90
+#define SCP_IRQ_HDMI2			91
+/* 92 */
+#define SCP_IRQ_EARC			92
+#define SCP_IRQ_CEC			93
+#define SCP_IRQ_HDMI_DEV_DET		94
+#define SCP_IRQ_HDMIRX_OUT_ARM_PHY	95
+/* 96 */
+#define SCP_IRQ_I2C2			96
+#define SCP_IRQ_I2C3			97
+#define SCP_IRQ_I3C2_IBI_WAKE		98
+#define SCP_IRQ_I3C3_IBI_WAKE		99
+/* 100 */
+#define SCP_IRQ_SYS_I2C_0		100
+#define SCP_IRQ_SYS_I2C_1		101
+#define SCP_IRQ_SYS_I2C_2		102
+#define SCP_IRQ_SYS_I2C_3		103
+/* 104 */
+#define SCP_IRQ_SYS_I2C_4		104
+#define SCP_IRQ_SYS_I2C_5		105
+#define SCP_IRQ_SYS_I2C_6		106
+#define SCP_IRQ_SYS_I2C_7		107
+/* 108 */
+#define SCP_IRQ_DISP2ADSP_0		108
+#define SCP_IRQ_DISP2ADSP_1		109
+#define SCP_IRQ_DISP2ADSP_2		110
+#define SCP_IRQ_DISP2ADSP_3		111
+/* 112 */
+#define SCP_IRQ_DISP2ADSP_4		112
+#define SCP_IRQ_VDO1_DISP_MON2ADSP_0	113
+#define SCP_IRQ_VDO1_DISP_MON2ADSP_1	114
+#define SCP_IRQ_VDO1_DISP_MON2ADSP_2	115
+/* 116 */
+#define SCP_IRQ_GCE1_SECURE		116
+#define SCP_IRQ_GCE_SECURE		117
+
+#endif /* __CROS_EC_INTC_H */
diff --git a/chip/mt_scp/rv32i_common/intc.c b/chip/mt_scp/rv32i_common/intc.c
index bd7416c31e..9555dbf2f2 100644
--- a/chip/mt_scp/rv32i_common/intc.c
+++ b/chip/mt_scp/rv32i_common/intc.c
@@ -7,13 +7,14 @@
 
 #include "console.h"
 #include "csr.h"
+#include "intc.h"
 #include "registers.h"
 
 /*
  * INTC_GRP_0 is reserved.  See swirq of syscall_handler() in
  * core/riscv-rv32i/task.c for more details.
  *
- * Lower group has higher priority.
+ * Lower group has higher priority.  Group 0 has highest priority.
  */
 enum INTC_GROUP {
 	INTC_GRP_0 = 0x0,
@@ -33,6 +34,7 @@ enum INTC_GROUP {
 	INTC_GRP_14,
 };
 
+#ifdef BOARD_ASURADA_SCP
 static struct {
 	uint8_t group;
 } irqs[SCP_INTC_IRQ_COUNT] = {
@@ -147,6 +149,163 @@ static struct {
 	[SCP_IRQ_I2C_DMA3]		= { INTC_GRP_0 },
 };
 BUILD_ASSERT(ARRAY_SIZE(irqs) == SCP_INTC_IRQ_COUNT);
+#endif
+
+#ifdef BOARD_CHERRY_SCP
+static struct {
+	uint8_t group;
+} irqs[SCP_INTC_IRQ_COUNT] = {
+	/* 0 */
+	[SCP_IRQ_GIPC_IN0]		= { INTC_GRP_7 },
+	[SCP_IRQ_GIPC_IN1]		= { INTC_GRP_0 },
+	[SCP_IRQ_GIPC_IN2]		= { INTC_GRP_0 },
+	[SCP_IRQ_GIPC_IN3]		= { INTC_GRP_0 },
+	/* 4 */
+	[SCP_IRQ_SPM]			= { INTC_GRP_0 },
+	[SCP_IRQ_AP_CIRQ]		= { INTC_GRP_0 },
+	[SCP_IRQ_EINT]			= { INTC_GRP_0 },
+	[SCP_IRQ_PMIC]			= { INTC_GRP_0 },
+	/* 8 */
+	[SCP_IRQ_UART0_TX]		= { INTC_GRP_12 },
+	[SCP_IRQ_UART1_TX]		= { INTC_GRP_12 },
+	[SCP_IRQ_I2C0]			= { INTC_GRP_0 },
+	[SCP_IRQ_I2C1_0]		= { INTC_GRP_0 },
+	/* 12 */
+	[SCP_IRQ_BUS_DBG_TRACKER]	= { INTC_GRP_0 },
+	[SCP_IRQ_CLK_CTRL]		= { INTC_GRP_0 },
+	[SCP_IRQ_VOW]			= { INTC_GRP_0 },
+	[SCP_IRQ_TIMER0]		= { INTC_GRP_6 },
+	/* 16 */
+	[SCP_IRQ_TIMER1]		= { INTC_GRP_6 },
+	[SCP_IRQ_TIMER2]		= { INTC_GRP_6 },
+	[SCP_IRQ_TIMER3]		= { INTC_GRP_6 },
+	[SCP_IRQ_TIMER4]		= { INTC_GRP_6 },
+	/* 20 */
+	[SCP_IRQ_TIMER5]		= { INTC_GRP_6 },
+	[SCP_IRQ_OS_TIMER]		= { INTC_GRP_0 },
+	[SCP_IRQ_UART0_RX]		= { INTC_GRP_12 },
+	[SCP_IRQ_UART1_RX]		= { INTC_GRP_12 },
+	/* 24 */
+	[SCP_IRQ_GDMA]			= { INTC_GRP_0 },
+	[SCP_IRQ_AUDIO]			= { INTC_GRP_0 },
+	[SCP_IRQ_MD_DSP]		= { INTC_GRP_0 },
+	[SCP_IRQ_ADSP]			= { INTC_GRP_0 },
+	/* 28 */
+	[SCP_IRQ_CPU_TICK]		= { INTC_GRP_0 },
+	[SCP_IRQ_SPI0]			= { INTC_GRP_0 },
+	[SCP_IRQ_SPI1]			= { INTC_GRP_0 },
+	[SCP_IRQ_SPI2]			= { INTC_GRP_0 },
+	/* 32 */
+	[SCP_IRQ_NEW_INFRA_SYS_CIRQ]	= { INTC_GRP_0 },
+	[SCP_IRQ_DBG]			= { INTC_GRP_0 },
+	[SCP_IRQ_GCE]			= { INTC_GRP_0 },
+	[SCP_IRQ_MDP_GCE]		= { INTC_GRP_0 },
+	/* 36 */
+	[SCP_IRQ_VDEC]			= { INTC_GRP_0 },
+	[SCP_IRQ_WDT]			= { INTC_GRP_0 },
+	[SCP_IRQ_VDEC_LAT]		= { INTC_GRP_0 },
+	[SCP_IRQ_VDEC1]			= { INTC_GRP_0 },
+	/* 40 */
+	[SCP_IRQ_VDEC1_LAT]		= { INTC_GRP_0 },
+	[SCP_IRQ_INFRA]			= { INTC_GRP_0 },
+	[SCP_IRQ_CLK_CTRL_CORE]		= { INTC_GRP_0 },
+	[SCP_IRQ_CLK_CTRL2_CORE]	= { INTC_GRP_0 },
+	/* 44 */
+	[SCP_IRQ_CLK_CTRL2]		= { INTC_GRP_0 },
+	[SCP_IRQ_GIPC_IN4]		= { INTC_GRP_0 },
+	[SCP_IRQ_PERIBUS_TIMEOUT]	= { INTC_GRP_0 },
+	[SCP_IRQ_INFRABUS_TIMEOUT]	= { INTC_GRP_0 },
+	/* 48 */
+	[SCP_IRQ_MET0]			= { INTC_GRP_0 },
+	[SCP_IRQ_MET1]			= { INTC_GRP_0 },
+	[SCP_IRQ_MET2]			= { INTC_GRP_0 },
+	[SCP_IRQ_MET3]			= { INTC_GRP_0 },
+	/* 52 */
+	[SCP_IRQ_AP_WDT]		= { INTC_GRP_0 },
+	[SCP_IRQ_L2TCM_SEC_VIO]		= { INTC_GRP_0 },
+	[SCP_IRQ_VDEC_INT_LINE_CNT]	= { INTC_GRP_0 },
+	[SCP_IRQ_VOW_DATAIN]		= { INTC_GRP_0 },
+	/* 56 */
+	[SCP_IRQ_I3C0_IBI_WAKE]		= { INTC_GRP_0 },
+	[SCP_IRQ_I3C1_IBI_WAKE]		= { INTC_GRP_0 },
+	[SCP_IRQ_VENC]			= { INTC_GRP_0 },
+	[SCP_IRQ_APU_ENGINE]		= { INTC_GRP_0 },
+	/* 60 */
+	[SCP_IRQ_MBOX0]			= { INTC_GRP_0 },
+	[SCP_IRQ_MBOX1]			= { INTC_GRP_0 },
+	[SCP_IRQ_MBOX2]			= { INTC_GRP_0 },
+	[SCP_IRQ_MBOX3]			= { INTC_GRP_0 },
+	/* 64 */
+	[SCP_IRQ_MBOX4]			= { INTC_GRP_0 },
+	[SCP_IRQ_SYS_CLK_REQ]		= { INTC_GRP_0 },
+	[SCP_IRQ_BUS_REQ]		= { INTC_GRP_0 },
+	[SCP_IRQ_APSRC_REQ]		= { INTC_GRP_0 },
+	/* 68 */
+	[SCP_IRQ_APU_MBOX]		= { INTC_GRP_0 },
+	[SCP_IRQ_DEVAPC_SECURE_VIO]	= { INTC_GRP_0 },
+	[SCP_IRQ_CAMSYS_29]		= { INTC_GRP_0 },
+	[SCP_IRQ_CAMSYS_28]		= { INTC_GRP_0 },
+	/* 72 */
+	[SCP_IRQ_CAMSYS_5]		= { INTC_GRP_0 },
+	[SCP_IRQ_CAMSYS_4]		= { INTC_GRP_0 },
+	[SCP_IRQ_CAMSYS_3]		= { INTC_GRP_0 },
+	[SCP_IRQ_CAMSYS_2]		= { INTC_GRP_0 },
+	/* 76 */
+	[SCP_IRQ_HDMIRX_PM_DVI_SQH]	= { INTC_GRP_0 },
+	[SCP_IRQ_HDMIRX_RESERVED]	= { INTC_GRP_0 },
+	[SCP_IRQ_NNA0_0]		= { INTC_GRP_0 },
+	[SCP_IRQ_NNA0_1]		= { INTC_GRP_0 },
+	/* 80 */
+	[SCP_IRQ_NNA0_2]		= { INTC_GRP_0 },
+	[SCP_IRQ_NNA1_0]		= { INTC_GRP_0 },
+	[SCP_IRQ_NNA1_1]		= { INTC_GRP_0 },
+	[SCP_IRQ_NNA1_2]		= { INTC_GRP_0 },
+	/* 84 */
+	[SCP_IRQ_JPEGENC]		= { INTC_GRP_0 },
+	[SCP_IRQ_JPEGDEC]		= { INTC_GRP_0 },
+	[SCP_IRQ_JPEGDEC_C2]		= { INTC_GRP_0 },
+	[SCP_IRQ_VENC_C1]		= { INTC_GRP_0 },
+	/* 88 */
+	[SCP_IRQ_JPEGENC_C1]		= { INTC_GRP_0 },
+	[SCP_IRQ_JPEGDEC_C1]		= { INTC_GRP_0 },
+	[SCP_IRQ_HDMITX]		= { INTC_GRP_0 },
+	[SCP_IRQ_HDMI2]			= { INTC_GRP_0 },
+	/* 92 */
+	[SCP_IRQ_EARC]			= { INTC_GRP_0 },
+	[SCP_IRQ_HDMI2]			= { INTC_GRP_0 },
+	[SCP_IRQ_HDMI2]			= { INTC_GRP_0 },
+	[SCP_IRQ_HDMI2]			= { INTC_GRP_0 },
+	/* 96 */
+	[SCP_IRQ_I2C2]			= { INTC_GRP_0 },
+	[SCP_IRQ_I2C3]			= { INTC_GRP_0 },
+	[SCP_IRQ_I3C2_IBI_WAKE]		= { INTC_GRP_0 },
+	[SCP_IRQ_I3C3_IBI_WAKE]		= { INTC_GRP_0 },
+	/* 100 */
+	[SCP_IRQ_SYS_I2C_0]		= { INTC_GRP_0 },
+	[SCP_IRQ_SYS_I2C_1]		= { INTC_GRP_0 },
+	[SCP_IRQ_SYS_I2C_2]		= { INTC_GRP_0 },
+	[SCP_IRQ_SYS_I2C_3]		= { INTC_GRP_0 },
+	/* 104 */
+	[SCP_IRQ_SYS_I2C_4]		= { INTC_GRP_0 },
+	[SCP_IRQ_SYS_I2C_5]		= { INTC_GRP_0 },
+	[SCP_IRQ_SYS_I2C_6]		= { INTC_GRP_0 },
+	[SCP_IRQ_SYS_I2C_7]		= { INTC_GRP_0 },
+	/* 108 */
+	[SCP_IRQ_DISP2ADSP_0]		= { INTC_GRP_0 },
+	[SCP_IRQ_DISP2ADSP_1]		= { INTC_GRP_0 },
+	[SCP_IRQ_DISP2ADSP_2]		= { INTC_GRP_0 },
+	[SCP_IRQ_DISP2ADSP_3]		= { INTC_GRP_0 },
+	/* 112 */
+	[SCP_IRQ_DISP2ADSP_4]		= { INTC_GRP_0 },
+	[SCP_IRQ_VDO1_DISP_MON2ADSP_0]	= { INTC_GRP_0 },
+	[SCP_IRQ_VDO1_DISP_MON2ADSP_1]	= { INTC_GRP_0 },
+	[SCP_IRQ_VDO1_DISP_MON2ADSP_2]	= { INTC_GRP_0 },
+	/* 116 */
+	[SCP_IRQ_GCE1_SECURE]		= { INTC_GRP_0 },
+	[SCP_IRQ_GCE_SECURE]		= { INTC_GRP_0 },
+};
+BUILD_ASSERT(ARRAY_SIZE(irqs) == SCP_INTC_IRQ_COUNT);
+#endif
 
 /*
  * Find current interrupt source.
@@ -246,6 +405,9 @@ void chip_init_irqs(void)
 	SCP_CORE0_INTC_IRQ_POL(0) = SCP_INTC_IRQ_POL0;
 	SCP_CORE0_INTC_IRQ_POL(1) = SCP_INTC_IRQ_POL1;
 	SCP_CORE0_INTC_IRQ_POL(2) = SCP_INTC_IRQ_POL2;
+#if SCP_INTC_GRP_LEN > 3
+	SCP_CORE0_INTC_IRQ_POL(3) = SCP_INTC_IRQ_POL3;
+#endif
 
 	/* GVIC init */
 	/* enable all groups as interrupt sources */
diff --git a/chip/mt_scp/rv32i_common/registers.h b/chip/mt_scp/rv32i_common/registers.h
index b19afe5e0d..82450be169 100644
--- a/chip/mt_scp/rv32i_common/registers.h
+++ b/chip/mt_scp/rv32i_common/registers.h
@@ -10,6 +10,7 @@
 
 #include "common.h"
 #include "compile_time_macros.h"
+#include "intc.h"
 
 #define UNIMPLEMENTED_GPIO_BANK 0
 
@@ -147,9 +148,8 @@
 #define SCP_INTC_WORD(irq)		((irq) >> 5) /* word length = 2^5 */
 #define SCP_INTC_BIT(irq)		((irq) & 0x1F) /* bit shift =LSB[0:4] */
 #define SCP_INTC_GRP_COUNT		15
-#define SCP_INTC_GRP_LEN		3
 #define SCP_INTC_GRP_GAP		4
-#define SCP_INTC_IRQ_COUNT		96
+
 #define SCP_CORE0_INTC_IRQ_BASE		(SCP_REG_BASE + 0x32000)
 #define SCP_CORE0_INTC_IRQ_STA(w) \
 		REG32_ADDR(SCP_CORE0_INTC_IRQ_BASE + 0x0010)[(w)]
@@ -211,114 +211,4 @@
 
 #include "clock_regs.h"
 
-/* IRQ numbers */
-#define SCP_IRQ_GIPC_IN0		0
-#define SCP_IRQ_GIPC_IN1		1
-#define SCP_IRQ_GIPC_IN2		2
-#define SCP_IRQ_GIPC_IN3		3
-/* 4 */
-#define SCP_IRQ_SPM			4
-#define SCP_IRQ_AP_CIRQ			5
-#define SCP_IRQ_EINT			6
-#define SCP_IRQ_PMIC			7
-/* 8 */
-#define SCP_IRQ_UART0_TX		8
-#define SCP_IRQ_UART1_TX		9
-#define SCP_IRQ_I2C0			10
-#define SCP_IRQ_I2C1_0			11
-/* 12 */
-#define SCP_IRQ_BUS_DBG_TRACKER		12
-#define SCP_IRQ_CLK_CTRL		13
-#define SCP_IRQ_VOW			14
-#define SCP_IRQ_TIMER0			15
-/* 16 */
-#define SCP_IRQ_TIMER1			16
-#define SCP_IRQ_TIMER2			17
-#define SCP_IRQ_TIMER3			18
-#define SCP_IRQ_TIMER4			19
-/* 20 */
-#define SCP_IRQ_TIMER5			20
-#define SCP_IRQ_OS_TIMER		21
-#define SCP_IRQ_UART0_RX		22
-#define SCP_IRQ_UART1_RX		23
-/* 24 */
-#define SCP_IRQ_GDMA			24
-#define SCP_IRQ_AUDIO			25
-#define SCP_IRQ_MD_DSP			26
-#define SCP_IRQ_ADSP			27
-/* 28 */
-#define SCP_IRQ_CPU_TICK		28
-#define SCP_IRQ_SPI0			29
-#define SCP_IRQ_SPI1			30
-#define SCP_IRQ_SPI2			31
-/* 32 */
-#define SCP_IRQ_NEW_INFRA_SYS_CIRQ	32
-#define SCP_IRQ_DBG			33
-#define SCP_IRQ_CCIF0			34
-#define SCP_IRQ_CCIF1			35
-/* 36 */
-#define SCP_IRQ_CCIF2			36
-#define SCP_IRQ_WDT			37
-#define SCP_IRQ_USB0			38
-#define SCP_IRQ_USB1			39
-/* 40 */
-#define SCP_IRQ_DPMAIF			40
-#define SCP_IRQ_INFRA			41
-#define SCP_IRQ_CLK_CTRL_CORE		42
-#define SCP_IRQ_CLK_CTRL2_CORE		43
-/* 44 */
-#define SCP_IRQ_CLK_CTRL2		44
-#define SCP_IRQ_GIPC_IN4		45 /* HALT */
-#define SCP_IRQ_PERIBUS_TIMEOUT		46
-#define SCP_IRQ_INFRABUS_TIMEOUT	47
-/* 48 */
-#define SCP_IRQ_MET0			48
-#define SCP_IRQ_MET1			49
-#define SCP_IRQ_MET2			50
-#define SCP_IRQ_MET3			51
-/* 52 */
-#define SCP_IRQ_AP_WDT			52
-#define SCP_IRQ_L2TCM_SEC_VIO		53
-#define SCP_IRQ_CPU_TICK1		54
-#define SCP_IRQ_MAD_DATAIN		55
-/* 56 */
-#define SCP_IRQ_I3C0_IBI_WAKE		56
-#define SCP_IRQ_I3C1_IBI_WAKE		57
-#define SCP_IRQ_I3C2_IBI_WAKE		58
-#define SCP_IRQ_APU_ENGINE		59
-/* 60 */
-#define SCP_IRQ_MBOX0			60
-#define SCP_IRQ_MBOX1			61
-#define SCP_IRQ_MBOX2			62
-#define SCP_IRQ_MBOX3			63
-/* 64 */
-#define SCP_IRQ_MBOX4			64
-#define SCP_IRQ_SYS_CLK_REQ		65
-#define SCP_IRQ_BUS_REQ			66
-#define SCP_IRQ_APSRC_REQ		67
-/* 68 */
-#define SCP_IRQ_APU_MBOX		68
-#define SCP_IRQ_DEVAPC_SECURE_VIO	69
-/* 72 */
-/* 76 */
-#define SCP_IRQ_I2C1_2			78
-#define SCP_IRQ_I2C2			79
-/* 80 */
-#define SCP_IRQ_AUD2AUDIODSP		80
-#define SCP_IRQ_AUD2AUDIODSP_2		81
-#define SCP_IRQ_CONN2ADSP_A2DPOL	82
-#define SCP_IRQ_CONN2ADSP_BTCVSD	83
-/* 84 */
-#define SCP_IRQ_CONN2ADSP_BLEISO	84
-#define SCP_IRQ_PCIE2ADSP		85
-#define SCP_IRQ_APU2ADSP_ENGINE		86
-#define SCP_IRQ_APU2ADSP_MBOX		87
-/* 88 */
-#define SCP_IRQ_CCIF3			88
-#define SCP_IRQ_I2C_DMA0		89
-#define SCP_IRQ_I2C_DMA1		90
-#define SCP_IRQ_I2C_DMA2		91
-/* 92 */
-#define SCP_IRQ_I2C_DMA3		92
-
 #endif /* __CROS_EC_REGISTERS_H */