zephyr: herobrine_npcx9: Initial image which uses NPCX9

This CL copies the Zephyr board/trogdor to board/herobrine_npcx9.
Modify the chip config to npcx9m3f and some related configs (simply
rename) and dts (update the UART property). The board/herobrine_npcx9
and other NPCX9 boards, like board/brya will be merged to a single
board. But the merge needs more work to remove the not-common configs
and dts to the project directories. Leave it as a future work.

This CL also copies the project trogdor/herobrine_npcx7 to
herobrine/herobrine_npcx9. Remove the dead files power.c and
hibernate.c, in the EC-OS directory. Remove the Zephyr 2.5 support
and board.cmake (needed only for 2.5).

BRANCH=None
BUG=b:192253134
TEST=Built the herobrine_npcx9 image successfully.

Change-Id: I9641768ee978920f6a8677f13ae14e0a26ad35f4
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2993220
Reviewed-by: Yuval Peress <peress@chromium.org>

14 files changed, 1140 insertions, 0 deletions

diff --git a/zephyr/boards/arm/herobrine_npcx9/Kconfig.board b/zephyr/boards/arm/herobrine_npcx9/Kconfig.board
new file mode 100644
index 0000000000..d9e7faf3af
--- /dev/null
+++ b/zephyr/boards/arm/herobrine_npcx9/Kconfig.board
@@ -0,0 +1,15 @@
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# "BOARD" below refers to a Zephyr board, which does not have a 1:1
+# mapping with the Chrome OS concept of a board.  By Zephyr's
+# conventions, we'll still call it "BOARD_*" to make this more
+# applicable to be upstreamed, even though this code is shared by all
+# projects using Herobrine-NPCX9 baseboard.
+config BOARD_HEROBRINE_NPCX9
+	bool "Google Herobrine-NPCX9 Baseboard"
+	depends on SOC_NPCX9M3F
+	# NPCX doesn't actually have enough ram for coverage, but this will
+	# allow generating initial 0 line coverage.
+	select HAS_COVERAGE_SUPPORT
diff --git a/zephyr/boards/arm/herobrine_npcx9/Kconfig.defconfig b/zephyr/boards/arm/herobrine_npcx9/Kconfig.defconfig
new file mode 100644
index 0000000000..65f3225d91
--- /dev/null
+++ b/zephyr/boards/arm/herobrine_npcx9/Kconfig.defconfig
@@ -0,0 +1,10 @@
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+if BOARD_HEROBRINE_NPCX9
+
+config BOARD
+	default "herobrine_npcx9"
+
+endif # BOARD_HEROBRINE_NPCX9
diff --git a/zephyr/boards/arm/herobrine_npcx9/herobrine_npcx9.dts b/zephyr/boards/arm/herobrine_npcx9/herobrine_npcx9.dts
new file mode 100644
index 0000000000..deb902c97f
--- /dev/null
+++ b/zephyr/boards/arm/herobrine_npcx9/herobrine_npcx9.dts
@@ -0,0 +1,247 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/dts-v1/;
+
+#include <cros/nuvoton/npcx9.dtsi>
+#include <dt-bindings/adc/adc.h>
+#include <dt-bindings/gpio_defines.h>
+#include <dt-bindings/wake_mask_event_defines.h>
+#include <nuvoton/npcx9m3f.dtsi>
+
+/ {
+	model = "Google Herobrine-NPCX9 Baseboard";
+
+	aliases {
+		i2c-0 = &i2c0_0;
+		i2c-1 = &i2c1_0;
+		i2c-2 = &i2c2_0;
+		i2c-3 = &i2c3_0;
+		i2c-5 = &i2c5_0;
+		i2c-7 = &i2c7_0;
+	};
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,console = &uart1;
+		zephyr,shell-uart = &uart1;
+		zephyr,flash = &flash0;
+		cros,rtc = &mtc;
+	};
+
+	ec-console {
+		compatible = "ec-console";
+
+		disabled = "hostcmd";
+	};
+
+	ec-mkbp-host-event-wakeup-mask {
+		compatible = "ec-wake-mask-event";
+		wakeup-mask = <(HOST_EVENT_LID_OPEN | \
+				HOST_EVENT_POWER_BUTTON | \
+				HOST_EVENT_AC_CONNECTED | \
+				HOST_EVENT_AC_DISCONNECTED | \
+				HOST_EVENT_HANG_DETECT | \
+				HOST_EVENT_RTC | \
+				HOST_EVENT_MODE_CHANGE | \
+				HOST_EVENT_DEVICE)>;
+	};
+
+	ec-mkbp-event-wakeup-mask {
+		compatible = "ec-wake-mask-event";
+		wakeup-mask = <(MKBP_EVENT_KEY_MATRIX | \
+				MKBP_EVENT_HOST_EVENT | \
+				MKBP_EVENT_SENSOR_FIFO)>;
+	};
+
+	named-i2c-ports {
+		compatible = "named-i2c-ports";
+
+		power {
+			i2c-port = <&i2c0_0>;
+			enum-name = "I2C_PORT_POWER";
+			label = "POWER";
+		};
+		battery {
+			i2c-port = <&i2c0_0>;
+			remote-port = <0>;
+			enum-name = "I2C_PORT_BATTERY";
+			label = "BATTERY";
+		};
+		virtual {
+			i2c-port = <&i2c0_0>;
+			enum-name = "I2C_PORT_VIRTUAL";
+			label = "VIRTUAL";
+		};
+		charger {
+			i2c-port = <&i2c0_0>;
+			enum-name = "I2C_PORT_CHARGER";
+			label = "CHARGER";
+		};
+		tcpc0 {
+			i2c-port = <&i2c1_0>;
+			enum-name = "I2C_PORT_TCPC0";
+			label = "TCPC0";
+		};
+		tcpc1 {
+			i2c-port = <&i2c2_0>;
+			enum-name = "I2C_PORT_TCPC1";
+			label = "TCPC1";
+		};
+		eeprom {
+			i2c-port = <&i2c5_0>;
+			enum-name = "I2C_PORT_EEPROM";
+			label = "EEPROM";
+		};
+		i2c_sensor: sensor {
+			i2c-port = <&i2c7_0>;
+			enum-name = "I2C_PORT_SENSOR";
+			label = "SENSOR";
+		};
+		accel {
+			i2c-port = <&i2c7_0>;
+			enum-name = "I2C_PORT_ACCEL";
+			label = "ACCEL";
+		};
+	};
+
+	named-pwms {
+		compatible = "named-pwms";
+
+		kblight {
+			pwms = <&pwm3 0 0>;
+			label = "KBLIGHT";
+			frequency = <10000>;
+		};
+		displight {
+			pwms = <&pwm5 0 0>;
+			label = "DISPLIGHT";
+			frequency = <4800>;
+		};
+	};
+
+	named-adc-channels {
+		compatible = "named-adc-channels";
+
+		vbus {
+			label = "ADC_VBUS";
+			enum-name = "ADC_VBUS";
+			channel = <1>;
+			/* Measure VBUS through a 1/10 voltage divider */
+			mul = <10>;
+		};
+		amon_bmon {
+			label = "ADC_AMON_BMON";
+			enum-name = "ADC_AMON_BMON";
+			channel = <2>;
+			/*
+			 * Adapter current output or battery charging/
+			 * discharging current (uV) 18x amplification on
+			 * charger side.
+			 */
+			mul = <1000>;
+			div = <18>;
+		};
+		psys {
+			label = "ADC_PSYS";
+			enum-name = "ADC_PSYS";
+			channel = <3>;
+			/*
+			 * ISL9238 PSYS output is 1.44 uA/W over 5.6K resistor,
+			 * to read 0.8V @ 99 W, i.e. 124000 uW/mV.
+			 */
+			mul = <124000>;
+		};
+	};
+
+	def-lvol-io-list {
+		compatible = "nuvoton,npcx-lvolctrl-def";
+
+		/* I2C_SDA0 & SCL0 */
+		lvol-io-pads = <&lvol_iob4 &lvol_iob5>;
+	};
+};
+
+&uart1 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&altj_cr_sin1_sl2 &altj_cr_sout1_sl2>;
+};
+
+&i2c0_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_STANDARD>;
+
+	isl9238: isl9238@9 {
+		compatible = "intersil,isl9238";
+		reg = <0x09>;
+		label = "ISL9238_CHARGER";
+	};
+};
+
+&i2c1_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+};
+
+&i2c2_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST_PLUS>;
+};
+
+&i2c3_0 {
+	/* Not used as no WLC connected */
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&i2c5_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+&i2c7_0 {
+	status = "okay";
+	clock-frequency = <I2C_BITRATE_FAST>;
+};
+
+/* Keyboard backlight */
+&pwm3 {
+	status = "okay";
+};
+
+/* Display backlight */
+&pwm5 {
+	status = "okay";
+};
+
+&adc0 {
+	status = "okay";
+};
+
+&cros_kb_raw {
+	status = "okay";
+	/* No KSO2 (it's inverted and implemented by GPIO) */
+	pinctrl-0 = <&alt7_no_ksi0_sl
+		     &alt7_no_ksi1_sl
+		     &alt7_no_ksi2_sl
+		     &alt7_no_ksi3_sl
+		     &alt7_no_ksi4_sl
+		     &alt7_no_ksi5_sl
+		     &alt7_no_ksi6_sl
+		     &alt7_no_ksi7_sl
+		     &alt8_no_kso00_sl
+		     &alt8_no_kso01_sl
+		     &alt8_no_kso03_sl
+		     &alt8_no_kso04_sl
+		     &alt8_no_kso05_sl
+		     &alt8_no_kso06_sl
+		     &alt8_no_kso07_sl
+		     &alt9_no_kso08_sl
+		     &alt9_no_kso09_sl
+		     &alt9_no_kso10_sl
+		     &alt9_no_kso11_sl
+		     &alt9_no_kso12_sl
+		     >;
+};
diff --git a/zephyr/boards/arm/herobrine_npcx9/herobrine_npcx9_defconfig b/zephyr/boards/arm/herobrine_npcx9/herobrine_npcx9_defconfig
new file mode 100644
index 0000000000..43efac9786
--- /dev/null
+++ b/zephyr/boards/arm/herobrine_npcx9/herobrine_npcx9_defconfig
@@ -0,0 +1,36 @@
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+# Zephyr Kernel Configuration
+CONFIG_SOC_SERIES_NPCX9=y
+CONFIG_SOC_NPCX9M3F=y
+
+# Platform Configuration
+CONFIG_BOARD_HEROBRINE_NPCX9=y
+
+# Serial Drivers
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+
+# Enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# Pinmux Driver
+CONFIG_PINMUX=y
+
+# GPIO Controller
+CONFIG_GPIO=y
+
+# Clock configuration
+CONFIG_CLOCK_CONTROL=y
+
+# WATCHDOG configuration
+CONFIG_WATCHDOG=y
+
+# Power Management
+CONFIG_SOC_POWER_MANAGEMENT=y
+CONFIG_PM_POLICY_APP=y
+CONFIG_UART_CONSOLE_INPUT_EXPIRED=y
+CONFIG_SOC_POWER_MANAGEMENT_TRACE=y
diff --git a/zephyr/projects/herobrine/herobrine_npcx9/CMakeLists.txt b/zephyr/projects/herobrine/herobrine_npcx9/CMakeLists.txt
new file mode 100644
index 0000000000..fa503185af
--- /dev/null
+++ b/zephyr/projects/herobrine/herobrine_npcx9/CMakeLists.txt
@@ -0,0 +1,33 @@
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+cmake_minimum_required(VERSION 3.13.1)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(herobrine_npcx9)
+
+zephyr_library_include_directories(include)
+
+set(PLATFORM_EC_BASEBOARD "${PLATFORM_EC}/baseboard/herobrine" CACHE PATH
+    "Path to the platform/ec baseboard directory")
+set(PLATFORM_EC_BOARD "${PLATFORM_EC}/board/herobrine_npcx9" CACHE PATH
+  "Path to the platform/ec board directory")
+
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_USBC
+  "${PLATFORM_EC_BASEBOARD}/usbc_config.c"
+  "${PLATFORM_EC_BASEBOARD}/usb_pd_policy.c")
+
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_LED_COMMON
+  "${PLATFORM_EC_BOARD}/led.c")
+
+zephyr_library_sources(
+  "${PLATFORM_EC_BOARD}/battery.c"
+  "${PLATFORM_EC_BOARD}/switchcap.c"
+  "${PLATFORM_EC_BOARD}/usbc_config.c")
+
+# Board specific implementation
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_MOTIONSENSE
+  "src/sensors.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_I2C
+  "src/i2c.c")
diff --git a/zephyr/projects/herobrine/herobrine_npcx9/battery.dts b/zephyr/projects/herobrine/herobrine_npcx9/battery.dts
new file mode 100644
index 0000000000..1dd7527241
--- /dev/null
+++ b/zephyr/projects/herobrine/herobrine_npcx9/battery.dts
@@ -0,0 +1,14 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	named-batteries {
+		compatible = "named-batteries";
+
+		ap16l5j {
+			enum-name = "ap16l5j";
+		};
+	};
+};
diff --git a/zephyr/projects/herobrine/herobrine_npcx9/gpio.dts b/zephyr/projects/herobrine/herobrine_npcx9/gpio.dts
new file mode 100644
index 0000000000..b4b716d0d7
--- /dev/null
+++ b/zephyr/projects/herobrine/herobrine_npcx9/gpio.dts
@@ -0,0 +1,341 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/ {
+	named-gpios {
+		compatible = "named-gpios";
+
+		usb_c0_pd_int_odl {
+			gpios = <&gpioe 0 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C0_PD_INT_ODL";
+			label = "USB_C0_PD_INT_ODL";
+		};
+		usb_c1_pd_int_odl {
+			gpios = <&gpiof 5 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C1_PD_INT_ODL";
+			label = "USB_C1_PD_INT_ODL";
+		};
+		usb_c0_swctl_int_odl {
+			gpios = <&gpio0 3 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C0_SWCTL_INT_ODL";
+			label = "USB_C0_SWCTL_INT_ODL";
+		};
+		usb_c1_swctl_int_odl {
+			gpios = <&gpio4 0 GPIO_INPUT>;
+			enum-name = "GPIO_USB_C1_SWCTL_INT_ODL";
+			label = "USB_C1_SWCTL_INT_ODL";
+		};
+		usb_c0_bc12_int_l {
+			gpios = <&gpio6 1 (GPIO_INPUT | GPIO_PULL_UP)>;
+			enum-name = "GPIO_USB_C0_BC12_INT_L";
+			label = "USB_C0_BC12_INT_L";
+		};
+		usb_c1_bc12_int_l {
+			gpios = <&gpio8 2 (GPIO_INPUT | GPIO_PULL_UP)>;
+			enum-name = "GPIO_USB_C1_BC12_INT_L";
+			label = "USB_C1_BC12_INT_L";
+		};
+		usb_a0_oc_odl {
+			gpios = <&gpiod 1 (GPIO_INPUT | GPIO_PULL_UP)>;
+			enum-name = "GPIO_USB_A0_OC_ODL";
+			label = "USB_A0_OC_ODL";
+		};
+		gpio_chg_acok_od: chg_acok_od {
+			gpios = <&gpio0 0 GPIO_INPUT>;
+			enum-name = "GPIO_AC_PRESENT";
+			label = "CHG_ACOK_OD";
+		};
+		gpio_ec_pwr_btn_odl: ec_pwr_btn_odl {
+			gpios = <&gpio0 1 GPIO_INPUT>;
+			enum-name = "GPIO_POWER_BUTTON_L";
+			label = "EC_PWR_BTN_ODL";
+		};
+		ec_voldn_btn_odl {
+			gpios = <&gpio7 0 (GPIO_INPUT | GPIO_PULL_UP)>;
+			enum-name = "GPIO_VOLUME_DOWN_L";
+			label = "EC_VOLDN_BTN_ODL";
+		};
+		ec_volup_btn_odl {
+			gpios = <&gpiof 2 (GPIO_INPUT | GPIO_PULL_UP)>;
+			enum-name = "GPIO_VOLUME_UP_L";
+			label = "EC_VOLUP_BTN_ODL";
+		};
+		ec_wp_odl {
+			gpios = <&gpioa 1 GPIO_INPUT>;
+			enum-name = "GPIO_WP_L";
+			label = "EC_WP_ODL";
+		};
+		gpio_lid_open_ec: lid_open_ec {
+			gpios = <&gpiod 2 GPIO_INPUT>;
+			enum-name = "GPIO_LID_OPEN";
+			label = "LID_OPEN_EC";
+		};
+		ap_rst_l {
+			gpios = <&gpioc 1 GPIO_INPUT>;
+			enum-name = "GPIO_AP_RST_L";
+			label = "AP_RST_L";
+		};
+		ps_hold {
+			gpios = <&gpioa 4 (GPIO_INPUT | GPIO_PULL_DOWN)>;
+			enum-name = "GPIO_PS_HOLD";
+			label = "PS_HOLD";
+		};
+		ap_suspend {
+			gpios = <&gpio5 7 GPIO_INPUT>;
+			enum-name = "GPIO_AP_SUSPEND";
+			label = "AP_SUSPEND";
+		};
+		deprecated_ap_rst_req {
+			gpios = <&gpioc 2 (GPIO_INPUT | GPIO_PULL_DOWN)>;
+			enum-name = "GPIO_DEPRECATED_AP_RST_REQ";
+			label = "DEPRECATED_AP_RST_REQ";
+		};
+		power_good {
+			gpios = <&gpio5 4 (GPIO_INPUT | GPIO_PULL_DOWN)>;
+			enum-name = "GPIO_POWER_GOOD";
+			label = "POWER_GOOD";
+		};
+		warm_reset_l {
+			gpios = <&gpiof 4 GPIO_INPUT>;
+			enum-name = "GPIO_WARM_RESET_L";
+			label = "WARM_RESET_L";
+		};
+		ap_ec_spi_cs_l {
+			gpios = <&gpio5 3 (GPIO_INPUT | GPIO_PULL_DOWN)>;
+			label = "AP_EC_SPI_CS_L";
+		};
+		tablet_mode_l {
+			gpios = <&gpioc 6 GPIO_INPUT>;
+			enum-name = "GPIO_TABLET_MODE_L";
+			label = "TABLET_MODE_L";
+		};
+		gpio_accel_gyro_int_l: accel_gyro_int_l {
+			gpios = <&gpioa 0 GPIO_INPUT>;
+			enum-name = "GPIO_ACCEL_GYRO_INT_L";
+			label = "ACCEL_GYRO_INT_L";
+		};
+		gpio_ec_rst_odl: ec_rst_odl {
+			gpios = <&gpio0 2 GPIO_INPUT>;
+			enum-name = "GPIO_EC_RST_ODL";
+			label = "EC_RST_ODL";
+		};
+		ec_entering_rw {
+			gpios = <&gpioe 1 GPIO_OUT_LOW>;
+			enum-name = "GPIO_ENTERING_RW";
+			label = "EC_ENTERING_RW";
+		};
+		ccd_mode_odl {
+			gpios = <&gpioe 3 GPIO_INPUT>;
+			enum-name = "GPIO_CCD_MODE_ODL";
+			label = "CCD_MODE_ODL";
+		};
+		ec_batt_pres_odl {
+			gpios = <&gpioe 5 GPIO_INPUT>;
+			enum-name = "GPIO_BATT_PRES_ODL";
+			label = "EC_BATT_PRES_ODL";
+		};
+		pmic_resin_l {
+			gpios = <&gpio3 2 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_PMIC_RESIN_L";
+			label = "PMIC_RESIN_L";
+		};
+		pmic_kpd_pwr_odl {
+			gpios = <&gpiod 6 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_PMIC_KPD_PWR_ODL";
+			label = "PMIC_KPD_PWR_ODL";
+		};
+		ec_int_l {
+			gpios = <&gpioa 2 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_EC_INT_L";
+			label = "EC_INT_L";
+		};
+		hibernate_l {
+			gpios = <&gpio5 2 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_HIBERNATE_L";
+			label = "HIBERNATE_L";
+		};
+		switchcap_on {
+			gpios = <&gpiod 5 GPIO_OUT_LOW>;
+			enum-name = "GPIO_SWITCHCAP_ON";
+			label = "SWITCHCAP_ON";
+		};
+		en_pp3300_a {
+			gpios = <&gpioa 6 GPIO_OUT_LOW>;
+			enum-name = "GPIO_EN_PP3300_A";
+			label = "EN_PP3300_A";
+		};
+		en_pp5000_a {
+			gpios = <&gpio6 7 GPIO_OUT_LOW>;
+			enum-name = "GPIO_EN_PP5000";
+			label = "EN_PP5000_A";
+		};
+		ec_bl_disable_l {
+			gpios = <&gpiob 6 GPIO_OUT_LOW>;
+			enum-name = "GPIO_ENABLE_BACKLIGHT";
+			label = "EC_BL_DISABLE_L";
+		};
+		lid_accel_int_l {
+			gpios = <&gpio5 6 GPIO_INPUT>;
+			enum-name = "GPIO_LID_ACCEL_INT_L";
+			label = "LID_ACCEL_INT_L";
+		};
+		trackpad_int_gate {
+			gpios = <&gpio7 4 GPIO_OUT_LOW>;
+			enum-name = "GPIO_TRACKPAD_INT_GATE";
+			label = "TRACKPAD_INT_GATE";
+		};
+		usb_c0_pd_rst_l {
+			gpios = <&gpiof 1 GPIO_OUT_HIGH>;
+			enum-name = "GPIO_USB_C0_PD_RST_L";
+			label = "USB_C0_PD_RST_L";
+		};
+		usb_c1_pd_rst_l {
+			gpios = <&gpioe 4 GPIO_OUT_HIGH>;
+			enum-name = "GPIO_USB_C1_PD_RST_L";
+			label = "USB_C1_PD_RST_L";
+		};
+		dp_mux_oe_l {
+			gpios = <&gpio9 6 GPIO_ODR_HIGH>;
+			enum-name = "GPIO_DP_MUX_OE_L";
+			label = "DP_MUX_OE_L";
+		};
+		dp_mux_sel {
+			gpios = <&gpio4 5 GPIO_OUT_LOW>;
+			enum-name = "GPIO_DP_MUX_SEL";
+			label = "DP_MUX_SEL";
+		};
+		dp_hot_plug_det {
+			gpios = <&gpio9 5 GPIO_OUT_LOW>;
+			enum-name = "GPIO_DP_HOT_PLUG_DET";
+			label = "DP_HOT_PLUG_DET";
+		};
+		en_usb_a_5v {
+			gpios = <&gpio8 6 GPIO_OUT_LOW>;
+			enum-name = "GPIO_EN_USB_A_5V";
+			label = "EN_USB_A_5V";
+		};
+		usb_a_cdp_ilim_en_l {
+			gpios = <&gpio7 5 GPIO_OUT_HIGH>;
+			label = "USB_A_CDP_ILIM_EN_L";
+		};
+		ec_chg_led_y_c0 {
+			gpios = <&gpio6 0 GPIO_OUT_LOW>;
+			enum-name = "GPIO_EC_CHG_LED_Y_C0";
+			label = "EC_CHG_LED_Y_C0";
+		};
+		ec_chg_led_w_c0 {
+			gpios = <&gpioc 0 GPIO_OUT_LOW>;
+			enum-name = "GPIO_EC_CHG_LED_W_C0";
+			label = "EC_CHG_LED_W_C0";
+		};
+		ec_chg_led_y_c1 {
+			gpios = <&gpioc 3 GPIO_OUT_LOW>;
+			enum-name = "GPIO_EC_CHG_LED_Y_C1";
+			label = "EC_CHG_LED_Y_C1";
+		};
+		ec_chg_led_w_c1 {
+			gpios = <&gpioc 4 GPIO_OUT_LOW>;
+			enum-name = "GPIO_EC_CHG_LED_W_C1";
+			label = "EC_CHG_LED_W_C1";
+		};
+		ap_ec_spi_mosi {
+			gpios = <&gpio4 6 (GPIO_INPUT | GPIO_PULL_DOWN)>;
+			label = "AP_EC_SPI_MOSI";
+		};
+		ap_ec_spi_miso {
+			gpios = <&gpio4 7 (GPIO_INPUT | GPIO_PULL_DOWN)>;
+			label = "AP_EC_SPI_MISO";
+		};
+		ap_ec_spi_clk {
+			gpios = <&gpio5 5 (GPIO_INPUT | GPIO_PULL_DOWN)>;
+			label = "AP_EC_SPI_CLK";
+		};
+		kb_bl_pwm {
+			gpios = <&gpio8 0 GPIO_INPUT>;
+			label = "KB_BL_PWM";
+		};
+		edp_bkltctl {
+			gpios = <&gpiob 7 GPIO_INPUT>;
+			label = "EDP_BKLTCTL";
+		};
+		ppvar_boostin_sense {
+			gpios = <&gpio4 4 GPIO_INPUT>;
+			label = "PPVAR_BOOSTIN_SENSE";
+		};
+		charger_iadp {
+			gpios = <&gpio4 3 GPIO_INPUT>;
+			label = "CHARGER_IADP";
+		};
+		charger_pmon {
+			gpios = <&gpio4 2 GPIO_INPUT>;
+			label = "CHARGER_PMON";
+		};
+		brd_id0 {
+			gpios = <&gpioc 7 GPIO_INPUT>;
+			enum-name = "GPIO_BOARD_VERSION1";
+			label = "BRD_ID0";
+		};
+		brd_id1 {
+			gpios = <&gpio9 3 GPIO_INPUT>;
+			enum-name = "GPIO_BOARD_VERSION2";
+			label = "BRD_ID1";
+		};
+		brd_id2 {
+			gpios = <&gpio6 3 GPIO_INPUT>;
+			enum-name = "GPIO_BOARD_VERSION3";
+			label = "BRD_ID2";
+		};
+		sku_id0 {
+			gpios = <&gpiof 0 GPIO_INPUT>;
+			enum-name = "GPIO_SKU_ID0";
+			label = "SKU_ID0";
+		};
+		sku_id1 {
+			gpios = <&gpio4 1 GPIO_INPUT>;
+			enum-name = "GPIO_SKU_ID1";
+			label = "SKU_ID1";
+		};
+		sku_id2 {
+			gpios = <&gpiod 4 GPIO_INPUT>;
+			enum-name = "GPIO_SKU_ID2";
+			label = "SKU_ID2";
+		};
+		switchcap_gpio_1 {
+			gpios = <&gpioe 2 (GPIO_INPUT | GPIO_PULL_DOWN)>;
+			enum-name = "GPIO_SWITCHCAP_PG";
+			label = "SWITCHCAP_GPIO_1";
+		};
+		arm_x86 {
+			gpios = <&gpio6 6 GPIO_OUT_LOW>;
+			label = "ARM_X86";
+		};
+		ec_kso_02_inv {
+			gpios = <&gpio1 7 GPIO_OUT_LOW>;
+			enum-name = "GPIO_KBD_KSO2";
+			label = "EC_KSO_02_INV";
+		};
+	};
+
+	def-lvol-io-list {
+		compatible = "nuvoton,npcx-lvolctrl-def";
+		lvol-io-pads = <
+			&lvol_ioc1 /* AP_RST_L */
+			&lvol_ioc2 /* DEPRECATED_AP_RST_REQ */
+			&lvol_iof4 /* WARM_RESET_L */
+			&lvol_iob3 /* EC_I2C_SENSOR_SCL */
+			&lvol_iob2 /* EC_I2C_SENSOR_SDA */
+		>;
+	};
+
+	hibernate-wake-pins {
+		compatible = "cros-ec,hibernate-wake-pins";
+		wakeup-pins = <
+			&gpio_chg_acok_od
+			&gpio_ec_pwr_btn_odl
+			&gpio_lid_open_ec
+			&gpio_ec_rst_odl
+		>;
+	};
+};
diff --git a/zephyr/projects/herobrine/herobrine_npcx9/include/gpio_map.h b/zephyr/projects/herobrine/herobrine_npcx9/include/gpio_map.h
new file mode 100644
index 0000000000..df4dcb0e25
--- /dev/null
+++ b/zephyr/projects/herobrine/herobrine_npcx9/include/gpio_map.h
@@ -0,0 +1,63 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __ZEPHYR_GPIO_MAP_H
+#define __ZEPHYR_GPIO_MAP_H
+
+#include <devicetree.h>
+#include <gpio_signal.h>
+
+#ifdef CONFIG_PLATFORM_EC_GMR_TABLET_MODE
+#define GMR_TABLET_MODE_GPIO_L GPIO_TABLET_MODE_L
+#endif
+
+/*
+ * Set EC_CROS_GPIO_INTERRUPTS to a space-separated list of GPIO_INT items.
+ *
+ * Each GPIO_INT requires three parameters:
+ *   gpio_signal - The enum gpio_signal for the interrupt gpio
+ *   interrupt_flags - The interrupt-related flags (e.g. GPIO_INT_EDGE_BOTH)
+ *   handler - The platform/ec interrupt handler.
+ *
+ * Ensure that this files includes all necessary headers to declare all
+ * referenced handler functions.
+ *
+ * For example, one could use the follow definition:
+ * #define EC_CROS_GPIO_INTERRUPTS \
+ *   GPIO_INT(NAMED_GPIO(h1_ec_pwr_btn_odl), GPIO_INT_EDGE_BOTH, button_print)
+ */
+#define EC_CROS_GPIO_INTERRUPTS                                               \
+	GPIO_INT(GPIO_AC_PRESENT, GPIO_INT_EDGE_BOTH, extpower_interrupt)     \
+	GPIO_INT(GPIO_LID_OPEN, GPIO_INT_EDGE_BOTH, lid_interrupt)            \
+	GPIO_INT(GPIO_WP_L, GPIO_INT_EDGE_BOTH, switch_interrupt)             \
+	GPIO_INT(GPIO_POWER_BUTTON_L, GPIO_INT_EDGE_BOTH,                     \
+		 power_button_interrupt)                                      \
+	GPIO_INT(GPIO_VOLUME_DOWN_L, GPIO_INT_EDGE_BOTH, button_interrupt)    \
+	GPIO_INT(GPIO_VOLUME_UP_L, GPIO_INT_EDGE_BOTH, button_interrupt)      \
+	GPIO_INT(GPIO_AP_RST_L, GPIO_INT_EDGE_BOTH, chipset_ap_rst_interrupt) \
+	GPIO_INT(GPIO_AP_SUSPEND, GPIO_INT_EDGE_BOTH, power_signal_interrupt) \
+	GPIO_INT(GPIO_DEPRECATED_AP_RST_REQ, GPIO_INT_EDGE_BOTH,              \
+		 power_signal_interrupt)                                      \
+	GPIO_INT(GPIO_POWER_GOOD, GPIO_INT_EDGE_BOTH,                         \
+		 chipset_power_good_interrupt)                                \
+	GPIO_INT(GPIO_PS_HOLD, GPIO_INT_EDGE_BOTH, power_signal_interrupt)    \
+	GPIO_INT(GPIO_WARM_RESET_L, GPIO_INT_EDGE_BOTH,                       \
+		 chipset_warm_reset_interrupt)                                \
+	GPIO_INT(GPIO_USB_C0_PD_INT_ODL, GPIO_INT_EDGE_FALLING,               \
+		 tcpc_alert_event)                                            \
+	GPIO_INT(GPIO_USB_C1_PD_INT_ODL, GPIO_INT_EDGE_FALLING,               \
+		 tcpc_alert_event)                                            \
+	GPIO_INT(GPIO_USB_C0_SWCTL_INT_ODL, GPIO_INT_EDGE_FALLING,            \
+		 ppc_interrupt)                                               \
+	GPIO_INT(GPIO_USB_C1_SWCTL_INT_ODL, GPIO_INT_EDGE_FALLING,            \
+		 ppc_interrupt)                                               \
+	GPIO_INT(GPIO_USB_C0_BC12_INT_L, GPIO_INT_EDGE_FALLING, usb0_evt)     \
+	GPIO_INT(GPIO_USB_C1_BC12_INT_L, GPIO_INT_EDGE_FALLING, usb1_evt)     \
+	GPIO_INT(GPIO_USB_A0_OC_ODL, GPIO_INT_EDGE_BOTH, usba_oc_interrupt)   \
+	GPIO_INT(GPIO_ACCEL_GYRO_INT_L, GPIO_INT_EDGE_FALLING,                \
+		 bmi160_interrupt)                                            \
+	GPIO_INT(GPIO_TABLET_MODE_L, GPIO_INT_EDGE_BOTH, gmr_tablet_switch_isr)
+
+#endif /* __ZEPHYR_GPIO_MAP_H */
diff --git a/zephyr/projects/herobrine/herobrine_npcx9/include/pwm_map.h b/zephyr/projects/herobrine/herobrine_npcx9/include/pwm_map.h
new file mode 100644
index 0000000000..e704b6d6d3
--- /dev/null
+++ b/zephyr/projects/herobrine/herobrine_npcx9/include/pwm_map.h
@@ -0,0 +1,16 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __ZEPHYR_PWM_MAP_H
+#define __ZEPHYR_PWM_MAP_H
+
+#include <devicetree.h>
+
+#include "pwm/pwm.h"
+
+#define PWM_CH_KBLIGHT		NAMED_PWM(kblight)
+#define PWM_CH_DISPLIGHT	NAMED_PWM(displight)
+
+#endif /* __ZEPHYR_PWM_MAP_H */
diff --git a/zephyr/projects/herobrine/herobrine_npcx9/motionsense.dts b/zephyr/projects/herobrine/herobrine_npcx9/motionsense.dts
new file mode 100644
index 0000000000..1f222c8f18
--- /dev/null
+++ b/zephyr/projects/herobrine/herobrine_npcx9/motionsense.dts
@@ -0,0 +1,157 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <dt-bindings/motionsense/utils.h>
+
+
+/ {
+	aliases {
+		/*
+		 * motion sense's <>_INT_EVENT is handled
+		 * by alias. Using the alias, each driver creates
+		 * its own <>_INT_EVENT.
+		 */
+		bmi160-int = &base_accel;
+	};
+
+	/*
+	 * Declare mutexes used by sensor drivers.
+	 * A mutex node is used to create an instance of mutex_t.
+	 * A mutex node is referenced by a sensor node if the
+	 * corresponding sensor driver needs to use the
+	 * instance of the mutex.
+	 */
+	motionsense-mutex {
+		compatible = "cros-ec,motionsense-mutex";
+		lid_mutex: lid-mutex {
+			label = "LID_MUTEX";
+		};
+
+		mutex_bmi160: bmi160-mutex {
+			label = "BMI160_MUTEX";
+		};
+	};
+
+	/* Rotation matrix used by drivers. */
+	motionsense-rotation-ref {
+		compatible = "cros-ec,motionsense-rotation-ref";
+		lid_rot_ref: lid-rotation-ref {
+			mat33 = <0 1 0
+				 (-1) 0 0
+				 0 0 1>;
+		};
+
+		base_rot_ref: base-rotation-ref {
+			mat33 = <1 0 0
+				 0 (-1) 0
+				 0 0 (-1)>;
+		};
+	};
+
+	/*
+	 * Driver specific data. A driver-specific data can be shared with
+	 * different motion sensors while they are using the same driver.
+	 *
+	 * If a node's compatible starts with "cros-ec,accelgyro-", it is for
+	 * a common structure defined in accelgyro.h.
+	 * e.g) compatible = "cros-ec,accelgyro-als-drv-data" is for
+	 * "struct als_drv_data_t" in accelgyro.h
+	 */
+	motionsense-sensor-data {
+		bma255_data: bma255-drv-data {
+			compatible = "cros-ec,drvdata-bma255";
+			status = "okay";
+		};
+
+		bmi160_data: bmi160-drv-data {
+			compatible = "cros-ec,drvdata-bmi160";
+			status = "okay";
+		};
+	};
+
+	/*
+	 * List of motion sensors that creates motion_sensors array.
+	 * The label "lid_accel" and "base_accel" are used to indicate
+	 * motion sensor IDs for lid angle calculation.
+	 */
+	motionsense-sensor {
+		lid_accel: lid-accel {
+			compatible = "cros-ec,bma255";
+			status = "okay";
+
+			label = "Lid Accel";
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_LID";
+			mutex = <&lid_mutex>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&lid_rot_ref>;
+			default-range = <2>;
+			drv-data = <&bma255_data>;
+			i2c-spi-addr-flags = "BMA2x2_I2C_ADDR1_FLAGS";
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					label = "SENSOR_CONFIG_EC_S0";
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					label = "SENSOR_CONFIG_EC_S3";
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base_accel: base-accel {
+			compatible = "cros-ec,bmi160-accel";
+			status = "okay";
+
+			label = "Base Accel";
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&mutex_bmi160>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&bmi160_data>;
+			configs {
+				compatible =
+					"cros-ec,motionsense-sensor-config";
+				ec-s0 {
+					label = "SENSOR_CONFIG_EC_S0";
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+				ec-s3 {
+					label = "SENSOR_CONFIG_EC_S3";
+					odr = <(10000 | ROUND_UP_FLAG)>;
+				};
+			};
+		};
+
+		base-gyro {
+			compatible = "cros-ec,bmi160-gyro";
+			status = "okay";
+
+			label = "Base Gyro";
+			active-mask = "SENSOR_ACTIVE_S0_S3";
+			location = "MOTIONSENSE_LOC_BASE";
+			mutex = <&mutex_bmi160>;
+			port = <&i2c_sensor>;
+			rot-standard-ref = <&base_rot_ref>;
+			drv-data = <&bmi160_data>;
+		};
+	};
+
+	motionsense-sensor-info {
+		compatible = "cros-ec,motionsense-sensor-info";
+
+		/*
+		 * list of GPIO interrupts that have to
+		 * be enabled at initial stage
+		 */
+		sensor-irqs = <&gpio_accel_gyro_int_l>;
+		/* list of sensors in force mode */
+		accel-force-mode-sensors = <&lid_accel>;
+	};
+};
diff --git a/zephyr/projects/herobrine/herobrine_npcx9/prj.conf b/zephyr/projects/herobrine/herobrine_npcx9/prj.conf
new file mode 100644
index 0000000000..f846733869
--- /dev/null
+++ b/zephyr/projects/herobrine/herobrine_npcx9/prj.conf
@@ -0,0 +1,149 @@
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CONFIG_CROS_EC=y
+CONFIG_SHIMMED_TASKS=y
+CONFIG_PLATFORM_EC=y
+CONFIG_PLATFORM_EC_BRINGUP=y
+CONFIG_PLATFORM_EC_EXTPOWER_GPIO=y
+CONFIG_PLATFORM_EC_SWITCH=y
+CONFIG_PLATFORM_EC_LID_SWITCH=y
+CONFIG_PLATFORM_EC_BACKLIGHT_LID=y
+CONFIG_PLATFORM_EC_POWER_BUTTON=y
+CONFIG_I2C=y
+
+# LED
+CONFIG_PLATFORM_EC_LED_COMMON=y
+
+# PWM
+CONFIG_PWM=y
+CONFIG_PWM_SHELL=n
+CONFIG_PLATFORM_EC_PWM=y
+CONFIG_PLATFORM_EC_PWM_DISPLIGHT=y
+CONFIG_PLATFORM_EC_PWM_KBLIGHT=y
+
+# Application Processor is Qualcomm SC7280
+CONFIG_AP_ARM_QUALCOMM_SC7280=y
+
+# Board version is selected over GPIO board ID pins.
+CONFIG_PLATFORM_EC_BOARD_VERSION_GPIO=y
+
+# Power Sequencing
+CONFIG_PLATFORM_EC_POWERSEQ=y
+CONFIG_PLATFORM_EC_POWERSEQ_HOST_SLEEP=y
+CONFIG_PLATFORM_EC_POWER_SLEEP_FAILURE_DETECTION=y
+CONFIG_PLATFORM_EC_CHIPSET_RESET_HOOK=y
+CONFIG_PLATFORM_EC_CHIPSET_RESUME_INIT_HOOK=y
+
+# TODO(b:193719620): Enable EC EFS2 (toggled by PLATFORM_EC_VBOOT).
+CONFIG_PLATFORM_EC_VBOOT=n
+
+# MKBP event mask
+CONFIG_PLATFORM_EC_MKBP_EVENT_WAKEUP_MASK=y
+CONFIG_PLATFORM_EC_MKBP_HOST_EVENT_WAKEUP_MASK=y
+
+# MKBP event
+CONFIG_PLATFORM_EC_MKBP_EVENT=y
+CONFIG_PLATFORM_EC_MKBP_USE_GPIO=y
+
+# Keyboard
+CONFIG_PLATFORM_EC_KEYBOARD=y
+CONFIG_PLATFORM_EC_KEYBOARD_PROTOCOL_MKBP=y
+CONFIG_PLATFORM_EC_MKBP_INPUT_DEVICES=y
+CONFIG_PLATFORM_EC_KEYBOARD_COL2_INVERTED=y
+CONFIG_PLATFORM_EC_VOLUME_BUTTONS=y
+CONFIG_PLATFORM_EC_CMD_BUTTON=y
+CONFIG_CROS_KB_RAW_NPCX=y
+
+# ADC
+CONFIG_PLATFORM_EC_ADC=y
+CONFIG_ADC=y
+CONFIG_ADC_SHELL=n
+
+# Battery
+CONFIG_HAS_TASK_USB_CHG_P1=y
+CONFIG_PLATFORM_EC_BATTERY=y
+CONFIG_PLATFORM_EC_BATTERY_SMART=y
+CONFIG_PLATFORM_EC_I2C_VIRTUAL_BATTERY=y
+CONFIG_PLATFORM_EC_I2C_PASSTHRU_RESTRICTED=y
+CONFIG_PLATFORM_EC_BATTERY_FUEL_GAUGE=y
+CONFIG_PLATFORM_EC_BATTERY_CUT_OFF=y
+CONFIG_PLATFORM_EC_BATTERY_PRESENT_GPIO=y
+CONFIG_PLATFORM_EC_CHARGER_ISL9238=y
+CONFIG_PLATFORM_EC_CHARGE_RAMP_HW=y
+CONFIG_PLATFORM_EC_USE_BATTERY_DEVICE_CHEMISTRY=y
+CONFIG_PLATFORM_EC_BATTERY_DEVICE_CHEMISTRY="LION"
+CONFIG_PLATFORM_EC_BATTERY_REVIVE_DISCONNECT=y
+CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC=y
+CONFIG_PLATFORM_EC_CHARGER_DISCHARGE_ON_AC_CHARGER=y
+CONFIG_PLATFORM_EC_CHARGER_MIN_BAT_PCT_FOR_POWER_ON=2
+CONFIG_PLATFORM_EC_CHARGER_MIN_POWER_MW_FOR_POWER_ON=10000
+CONFIG_PLATFORM_EC_CHARGER_PROFILE_OVERRIDE=y
+CONFIG_PLATFORM_EC_CHARGER_PSYS=y
+CONFIG_PLATFORM_EC_CHARGER_PSYS_READ=y
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR=10
+CONFIG_PLATFORM_EC_CHARGER_SENSE_RESISTOR_AC=20
+CONFIG_PLATFORM_EC_CONSOLE_CMD_CHARGER_ADC_AMON_BMON=y
+
+# USB-A
+CONFIG_PLATFORM_EC_USB_A_PORT_COUNT=1
+
+# USB-C
+CONFIG_PLATFORM_EC_BC12_DETECT_PI3USB9201=y
+CONFIG_PLATFORM_EC_USB_PD_USB32_DRD=n
+CONFIG_PLATFORM_EC_USBC_PPC_SN5S330=y
+CONFIG_PLATFORM_EC_USBC_RETIMER_FW_UPDATE=n
+CONFIG_PLATFORM_EC_USBC_SS_MUX_DFP_ONLY=y
+CONFIG_PLATFORM_EC_USB_DRP_ACC_TRYSRC=y
+CONFIG_PLATFORM_EC_USB_PD_5V_EN_CUSTOM=y
+CONFIG_PLATFORM_EC_USB_PD_VBUS_DETECT_TCPC=y
+CONFIG_PLATFORM_EC_USB_PD_DISCHARGE_PPC=y
+CONFIG_PLATFORM_EC_USB_PD_PORT_MAX_COUNT=2
+CONFIG_PLATFORM_EC_USB_PD_REV30=n
+CONFIG_PLATFORM_EC_USB_PD_TCPC_LOW_POWER=y
+CONFIG_PLATFORM_EC_USB_PD_TCPM_PS8805=y
+CONFIG_PLATFORM_EC_USB_PD_TCPC_RUNTIME_CONFIG=n
+CONFIG_PLATFORM_EC_USB_PD_LOGGING=y
+CONFIG_PLATFORM_EC_USB_PORT_POWER_DUMB=y
+CONFIG_HAS_TASK_PD_C1=y
+CONFIG_HAS_TASK_PD_INT_C1=y
+
+# USB ID
+# This is allocated specifically for Herobrine
+# http://google3/hardware/standards/usb/
+# TODO(b/183608112): Move to device tree
+CONFIG_PLATFORM_EC_USB_PID=0x5055
+
+# RTC
+CONFIG_PLATFORM_EC_RTC=y
+CONFIG_PLATFORM_EC_HOSTCMD_RTC=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_RTC=y
+
+# EC software sync
+CONFIG_PLATFORM_EC_VBOOT_HASH=y
+
+# Serial Host Interface (SHI) device.
+CONFIG_CROS_SHI_NPCX=y
+
+# Sensors
+CONFIG_PLATFORM_EC_MOTIONSENSE=y
+CONFIG_PLATFORM_EC_ACCEL_FIFO=y
+CONFIG_PLATFORM_EC_ACCEL_INTERRUPTS=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCELS=y
+CONFIG_PLATFORM_EC_CONSOLE_CMD_ACCEL_INFO=y
+CONFIG_PLATFORM_EC_GMR_TABLET_MODE=y
+CONFIG_PLATFORM_EC_LID_ANGLE=y
+CONFIG_PLATFORM_EC_LID_ANGLE_UPDATE=y
+CONFIG_PLATFORM_EC_SENSOR_TIGHT_TIMESTAMPS=y
+CONFIG_PLATFORM_EC_TABLET_MODE=y
+CONFIG_PLATFORM_EC_TABLET_MODE_SWITCH=y
+
+# Sensor Drivers
+CONFIG_PLATFORM_EC_ACCEL_BMA255=y
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI160=y
+CONFIG_PLATFORM_EC_ACCELGYRO_BMI_COMM_I2C=y
+
+# Features should be enabled. But the code RAM is not enough, disable them.
+#CONFIG_PLATFORM_EC_ACCEL_SPOOF_MODE=y
+#CONFIG_PLATFORM_EC_EMULATED_SYSRQ=y
diff --git a/zephyr/projects/herobrine/herobrine_npcx9/src/i2c.c b/zephyr/projects/herobrine/herobrine_npcx9/src/i2c.c
new file mode 100644
index 0000000000..f78ea56513
--- /dev/null
+++ b/zephyr/projects/herobrine/herobrine_npcx9/src/i2c.c
@@ -0,0 +1,17 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "i2c/i2c.h"
+#include "i2c.h"
+
+/* Herobrine-NPCX9 board specific i2c implementation */
+
+#ifdef CONFIG_PLATFORM_EC_I2C_PASSTHRU_RESTRICTED
+int board_allow_i2c_passthru(int port)
+{
+	return (i2c_get_device_for_port(port) ==
+		i2c_get_device_for_port(I2C_PORT_VIRTUAL_BATTERY));
+}
+#endif
diff --git a/zephyr/projects/herobrine/herobrine_npcx9/src/sensors.c b/zephyr/projects/herobrine/herobrine_npcx9/src/sensors.c
new file mode 100644
index 0000000000..dd9ce10a16
--- /dev/null
+++ b/zephyr/projects/herobrine/herobrine_npcx9/src/sensors.c
@@ -0,0 +1,29 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "chipset.h"
+#include "common.h"
+#include "keyboard_scan.h"
+
+/* Herobrine-NPCX9 board specific sensor implementation */
+
+#ifdef CONFIG_LID_ANGLE_UPDATE
+void lid_angle_peripheral_enable(int enable)
+{
+	int chipset_in_s0 = chipset_in_state(CHIPSET_STATE_ON);
+
+	if (enable) {
+		keyboard_scan_enable(1, KB_SCAN_DISABLE_LID_ANGLE);
+	} else {
+		/*
+		 * Ensure that the chipset is off before disabling the keyboard.
+		 * When the chipset is on, the EC keeps the keyboard enabled and
+		 * the AP decides whether to ignore input devices or not.
+		 */
+		if (!chipset_in_s0)
+			keyboard_scan_enable(0, KB_SCAN_DISABLE_LID_ANGLE);
+	}
+}
+#endif
diff --git a/zephyr/projects/herobrine/herobrine_npcx9/zmake.yaml b/zephyr/projects/herobrine/herobrine_npcx9/zmake.yaml
new file mode 100644
index 0000000000..7620beedc4
--- /dev/null
+++ b/zephyr/projects/herobrine/herobrine_npcx9/zmake.yaml
@@ -0,0 +1,13 @@
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+board: herobrine_npcx9
+dts-overlays:
+  - gpio.dts
+  - battery.dts
+  - motionsense.dts
+supported-zephyr-versions:
+  - v2.6
+toolchain: coreboot-sdk
+output-type: npcx