servo_v4p1: Initial checkin of firmware

The flash is partitioned as follows:
  96K for RO
  40K for RW

  The bulk of the code is placed in RO and RW
  is used for software updates.

This initial checkin implements the following
functionality:
  1) Software updates over servo_updater

BRANCH=none
BUG=b:146793000
BUG=b:141180763
TEST=make -j buildall

Change-Id: I68f94c5110210c134e7ff7212d6ccc0854413457
Signed-off-by: Sam Hurst <shurst@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2107729
Reviewed-by: Wai-Hong Tam <waihong@google.com>

5 files changed, 586 insertions, 0 deletions

diff --git a/board/servo_v4p1/board.c b/board/servo_v4p1/board.c
new file mode 100644
index 0000000000..0ace86b3d3
--- /dev/null
+++ b/board/servo_v4p1/board.c
@@ -0,0 +1,252 @@
+/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/* Servo V4p1 configuration */
+
+#include "adc.h"
+#include "adc_chip.h"
+#include "common.h"
+#include "console.h"
+#include "ec_version.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "queue_policies.h"
+#include "registers.h"
+#include "spi.h"
+#include "system.h"
+#include "task.h"
+#include "timer.h"
+#include "update_fw.h"
+#include "usart-stm32f0.h"
+#include "usart_tx_dma.h"
+#include "usart_rx_dma.h"
+#include "usb_gpio.h"
+#include "usb_i2c.h"
+#include "usb_spi.h"
+#include "usb-stream.h"
+#include "util.h"
+
+#ifdef SECTION_IS_RO
+#define CROS_EC_SECTION "RO"
+#else
+#define CROS_EC_SECTION "RW"
+#endif
+
+/******************************************************************************
+ * GPIO interrupt handlers.
+ */
+#ifdef SECTION_IS_RO
+static void vbus0_evt(enum gpio_signal signal)
+{
+}
+
+static void vbus1_evt(enum gpio_signal signal)
+{
+}
+
+static void tca_evt(enum gpio_signal signal)
+{
+}
+
+static void dp_evt(enum gpio_signal signal)
+{
+}
+
+static void tcpc_evt(enum gpio_signal signal)
+{
+}
+
+static void hub_evt(enum gpio_signal signal)
+{
+}
+
+static void bc12_evt(enum gpio_signal signal)
+{
+}
+#endif /* SECTION_IS_RO */
+
+#include "gpio_list.h"
+
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+
+/******************************************************************************
+ * Board pre-init function.
+ */
+
+void board_config_pre_init(void)
+{
+	/* enable SYSCFG clock */
+	STM32_RCC_APB2ENR |= BIT(0);
+
+	/*
+	 * the DMA mapping is :
+	 *  Chan 2 : TIM1_CH1  (CHG RX) - Default mapping
+	 *  Chan 3 : SPI1_TX   (CHG TX) - Default mapping
+	 *  Chan 4 : USART1 TX - Remapped from default Chan 2
+	 *  Chan 5 : USART1 RX - Remapped from default Chan 3
+	 *  Chan 6 : TIM3_CH1  (DUT RX) - Remapped from default Chan 4
+	 *  Chan 7 : SPI2_TX   (DUT TX) - Remapped from default Chan 5
+	 *
+	 * As described in the comments above, both USART1 TX/RX and DUT Tx/RX
+	 * channels must be remapped from the defulat locations. Remapping is
+	 * acoomplished by setting the following bits in the STM32_SYSCFG_CFGR1
+	 * register. Information about this register and its settings can be
+	 * found in section 11.3.7 DMA Request Mapping of the STM RM0091
+	 * Reference Manual
+	 */
+	/* Remap USART1 Tx from DMA channel 2 to channel 4 */
+	STM32_SYSCFG_CFGR1 |= BIT(9);
+	/* Remap USART1 Rx from DMA channel 3 to channel 5 */
+	STM32_SYSCFG_CFGR1 |= BIT(10);
+	/* Remap TIM3_CH1 from DMA channel 4 to channel 6 */
+	STM32_SYSCFG_CFGR1 |= BIT(30);
+	/* Remap SPI2 Tx from DMA channel 5 to channel 7 */
+	STM32_SYSCFG_CFGR1 |= BIT(24);
+}
+
+/******************************************************************************
+ * Set up USB PD
+ */
+
+/* ADC channels */
+const struct adc_t adc_channels[] = {
+	/* USB PD CC lines sensing. Converted to mV (3300mV/4096). */
+	[ADC_CHG_CC1_PD] = {"CHG_CC1_PD", 3300, 4096, 0, STM32_AIN(2)},
+	[ADC_CHG_CC2_PD] = {"CHG_CC2_PD", 3300, 4096, 0, STM32_AIN(4)},
+	[ADC_DUT_CC1_PD] = {"DUT_CC1_PD", 3300, 4096, 0, STM32_AIN(0)},
+	[ADC_DUT_CC2_PD] = {"DUT_CC2_PD", 3300, 4096, 0, STM32_AIN(5)},
+	[ADC_SBU1_DET] = {"SBU1_DET", 3300, 4096, 0, STM32_AIN(3)},
+	[ADC_SBU2_DET] = {"SBU2_DET", 3300, 4096, 0, STM32_AIN(7)},
+	[ADC_SUB_C_REF] = {"SUB_C_REF", 3300, 4096, 0, STM32_AIN(1)},
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+
+/******************************************************************************
+ * Forward UARTs as a USB serial interface.
+ */
+
+#define USB_STREAM_RX_SIZE	16
+#define USB_STREAM_TX_SIZE	16
+
+/******************************************************************************
+ * Forward USART3 as a simple USB serial interface.
+ */
+
+static struct usart_config const usart3;
+struct usb_stream_config const usart3_usb;
+
+static struct queue const usart3_to_usb = QUEUE_DIRECT(64, uint8_t,
+	usart3.producer, usart3_usb.consumer);
+static struct queue const usb_to_usart3 = QUEUE_DIRECT(64, uint8_t,
+	usart3_usb.producer, usart3.consumer);
+
+static struct usart_config const usart3 =
+	USART_CONFIG(usart3_hw,
+		usart_rx_interrupt,
+		usart_tx_interrupt,
+		115200,
+		0,
+		usart3_to_usb,
+		usb_to_usart3);
+
+USB_STREAM_CONFIG(usart3_usb,
+	USB_IFACE_USART3_STREAM,
+	USB_STR_USART3_STREAM_NAME,
+	USB_EP_USART3_STREAM,
+	USB_STREAM_RX_SIZE,
+	USB_STREAM_TX_SIZE,
+	usb_to_usart3,
+	usart3_to_usb)
+
+
+/******************************************************************************
+ * Forward USART4 as a simple USB serial interface.
+ */
+
+static struct usart_config const usart4;
+struct usb_stream_config const usart4_usb;
+
+static struct queue const usart4_to_usb = QUEUE_DIRECT(64, uint8_t,
+	usart4.producer, usart4_usb.consumer);
+static struct queue const usb_to_usart4 = QUEUE_DIRECT(64, uint8_t,
+	usart4_usb.producer, usart4.consumer);
+
+static struct usart_config const usart4 =
+	USART_CONFIG(usart4_hw,
+		usart_rx_interrupt,
+		usart_tx_interrupt,
+		9600,
+		0,
+		usart4_to_usb,
+		usb_to_usart4);
+
+USB_STREAM_CONFIG(usart4_usb,
+	USB_IFACE_USART4_STREAM,
+	USB_STR_USART4_STREAM_NAME,
+	USB_EP_USART4_STREAM,
+	USB_STREAM_RX_SIZE,
+	USB_STREAM_TX_SIZE,
+	usb_to_usart4,
+	usart4_to_usb)
+
+
+/******************************************************************************
+ * Define the strings used in our USB descriptors.
+ */
+
+const void *const usb_strings[] = {
+	[USB_STR_DESC]         = usb_string_desc,
+	[USB_STR_VENDOR]       = USB_STRING_DESC("Google Inc."),
+	[USB_STR_PRODUCT]      = USB_STRING_DESC("Servo V4p1"),
+	[USB_STR_SERIALNO]     = USB_STRING_DESC("1234-a"),
+	[USB_STR_VERSION]      = USB_STRING_DESC(CROS_EC_VERSION32),
+	[USB_STR_I2C_NAME]     = USB_STRING_DESC("I2C"),
+	[USB_STR_CONSOLE_NAME] = USB_STRING_DESC("Servo EC Shell"),
+	[USB_STR_USART3_STREAM_NAME]  = USB_STRING_DESC("DUT UART"),
+	[USB_STR_USART4_STREAM_NAME]  = USB_STRING_DESC("Atmega UART"),
+	[USB_STR_UPDATE_NAME]  = USB_STRING_DESC("Firmware update"),
+};
+
+BUILD_ASSERT(ARRAY_SIZE(usb_strings) == USB_STR_COUNT);
+
+
+
+/******************************************************************************
+ * Support I2C bridging over USB.
+ */
+
+/* I2C ports */
+const struct i2c_port_t i2c_ports[] = {
+	{"master", I2C_PORT_MASTER, 100,
+		GPIO_MASTER_I2C_SCL, GPIO_MASTER_I2C_SDA},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+int usb_i2c_board_is_enabled(void) { return 1; }
+
+/******************************************************************************
+ * Initialize board.
+ */
+
+int board_get_version(void)
+{
+	return 0;
+}
+
+static void board_init(void)
+{
+	/* USB to serial queues */
+	queue_init(&usart3_to_usb);
+	queue_init(&usb_to_usart3);
+	queue_init(&usart4_to_usb);
+	queue_init(&usb_to_usart4);
+
+	/* UART init */
+	usart_init(&usart3);
+	usart_init(&usart4);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/board/servo_v4p1/board.h b/board/servo_v4p1/board.h
new file mode 100644
index 0000000000..17d8f6a7cd
--- /dev/null
+++ b/board/servo_v4p1/board.h
@@ -0,0 +1,224 @@
+/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Servo V4p1 configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/* Use Link-Time Optimizations to try to reduce the firmware code size */
+#define CONFIG_LTO
+
+#define CONFIG_BOARD_VERSION_CUSTOM
+
+/* 48 MHz SYSCLK clock frequency */
+#define CPU_CLOCK 48000000
+
+/*
+ * Flash layout: we redefine the sections offsets and sizes as we want to
+ * include a pstate region, and will use RO/RW regions of different sizes.
+ * RO has size 92K and usb_updater along with the majority of code is placed
+ *    here.
+ * RW has size 40K and usb_updater and other relevant code is placed here.
+ */
+#undef _IMAGE_SIZE
+#undef CONFIG_ROLLBACK_OFF
+#undef CONFIG_ROLLBACK_SIZE
+#undef CONFIG_FLASH_PSTATE
+#undef CONFIG_FW_PSTATE_SIZE
+#undef CONFIG_FW_PSTATE_OFF
+#undef CONFIG_SHAREDLIB_SIZE
+#undef CONFIG_RO_MEM_OFF
+#undef CONFIG_RO_STORAGE_OFF
+#undef CONFIG_RO_SIZE
+#undef CONFIG_RW_MEM_OFF
+#undef CONFIG_RW_STORAGE_OFF
+#undef CONFIG_RW_SIZE
+#undef CONFIG_EC_PROTECTED_STORAGE_OFF
+#undef CONFIG_EC_PROTECTED_STORAGE_SIZE
+#undef CONFIG_EC_WRITABLE_STORAGE_OFF
+#undef CONFIG_EC_WRITABLE_STORAGE_SIZE
+#undef CONFIG_WP_STORAGE_OFF
+#undef CONFIG_WP_STORAGE_SIZE
+
+#define CONFIG_RAM_BANK_SIZE CONFIG_RAM_SIZE
+
+
+#define CONFIG_FLASH_PSTATE
+#define CONFIG_FLASH_PSTATE_BANK
+
+#define CONFIG_SHAREDLIB_SIZE   0
+
+#define CONFIG_RO_MEM_OFF       0
+#define CONFIG_RO_STORAGE_OFF   0
+#define CONFIG_RO_SIZE          (92*1024)
+
+#define CONFIG_FW_PSTATE_OFF    (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
+#define CONFIG_FW_PSTATE_SIZE   CONFIG_FLASH_BANK_SIZE
+
+#define CONFIG_RW_MEM_OFF       (CONFIG_FW_PSTATE_OFF + CONFIG_FW_PSTATE_SIZE)
+#define CONFIG_RW_STORAGE_OFF   0
+#define CONFIG_RW_SIZE          (CONFIG_FLASH_SIZE - \
+				(CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF))
+
+#define CONFIG_EC_PROTECTED_STORAGE_OFF         CONFIG_RO_MEM_OFF
+#define CONFIG_EC_PROTECTED_STORAGE_SIZE        CONFIG_RO_SIZE
+#define CONFIG_EC_WRITABLE_STORAGE_OFF          CONFIG_RW_MEM_OFF
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE         CONFIG_RW_SIZE
+
+#define CONFIG_WP_STORAGE_OFF           CONFIG_EC_PROTECTED_STORAGE_OFF
+#define CONFIG_WP_STORAGE_SIZE          CONFIG_EC_PROTECTED_STORAGE_SIZE
+
+/* Enable USART1,3,4 and USB streams */
+#define CONFIG_STREAM_USART
+#define CONFIG_STREAM_USART3
+#define CONFIG_STREAM_USART4
+#define CONFIG_STREAM_USB
+#define CONFIG_CMD_USART_INFO
+
+/* Optional features */
+#define CONFIG_STM_HWTIMER32
+#define CONFIG_HW_CRC
+#define CONFIG_PVD
+/*
+ * See 'Programmable voltage detector characteristics' in the
+ * STM32F072x8 Datasheet. PVD Threshold 1 corresponds to a
+ * falling voltage threshold of min:2.09V, max:2.27V.
+ */
+#define PVD_THRESHOLD     (1)
+
+/* USB Configuration */
+#define CONFIG_USB
+#define CONFIG_USB_PID 0x520d
+#define CONFIG_USB_CONSOLE
+#define CONFIG_USB_UPDATE
+#define CONFIG_USB_BCD_DEV 0x0001 /* v 0.01 */
+
+#define CONFIG_USB_PD_IDENTITY_HW_VERS 1
+#define CONFIG_USB_PD_IDENTITY_SW_VERS 1
+#define CONFIG_USB_SELF_POWERED
+
+#define CONFIG_USB_SERIALNO
+#define DEFAULT_SERIALNO "Uninitialized"
+#define CONFIG_MAC_ADDR
+#define DEFAULT_MAC_ADDR "Uninitialized"
+
+/* USB interface indexes (use define rather than enum to expand them) */
+#define USB_IFACE_CONSOLE	0
+#define USB_IFACE_EMPTY		1
+#define USB_IFACE_I2C		2
+#define USB_IFACE_USART3_STREAM	3
+#define USB_IFACE_USART4_STREAM	4
+#define USB_IFACE_UPDATE	5
+#define USB_IFACE_COUNT		6
+
+/* USB endpoint indexes (use define rather than enum to expand them) */
+#define USB_EP_CONTROL		0
+#define USB_EP_CONSOLE		1
+#define USB_EP_EMPTY		2
+#define USB_EP_I2C		3
+#define USB_EP_USART3_STREAM	4
+#define USB_EP_USART4_STREAM	5
+#define USB_EP_UPDATE		6
+#define USB_EP_COUNT		7
+
+/* Enable console recasting of GPIO type. */
+#define CONFIG_CMD_GPIO_EXTENDED
+
+/* This is not actually an EC so disable some features. */
+#undef CONFIG_WATCHDOG_HELP
+#undef CONFIG_LID_SWITCH
+#undef CONFIG_HIBERNATE
+
+/* Remove console commands / features for flash / RAM savings */
+#undef CONFIG_USB_PD_HOST_CMD
+#undef CONFIG_CONSOLE_CMDHELP
+#undef CONFIG_CONSOLE_HISTORY
+#undef CONFIG_CMD_CRASH
+#undef CONFIG_CMD_ACCELSPOOF
+#undef CONFIG_CMD_FASTCHARGE
+#undef CONFIG_CMD_FLASHINFO
+#undef CONFIG_CMD_GETTIME
+#undef CONFIG_CMD_MEM
+#undef CONFIG_CMD_SHMEM
+#undef CONFIG_CMD_SYSLOCK
+#undef CONFIG_CMD_TIMERINFO
+#undef CONFIG_CMD_WAITMS
+
+/* Enable control of I2C over USB */
+#define CONFIG_USB_I2C
+#define CONFIG_I2C
+#define CONFIG_I2C_MASTER
+#define I2C_PORT_MASTER 1
+
+/* PD features */
+#define CONFIG_ADC
+#undef  CONFIG_ADC_WATCHDOG
+#define CONFIG_BOARD_PRE_INIT
+/*
+ * If task profiling is enabled then the rx falling edge detection interrupts
+ * can't be processed in time and can't support USB PD messaging.
+ */
+#undef CONFIG_TASK_PROFILING
+#undef CONFIG_USB_POWER_DELIVERY
+
+/*
+ * If task profiling is enabled then the rx falling edge detection interrupts
+ * can't be processed in time and can't support USB PD messaging.
+ */
+#undef CONFIG_TASK_PROFILING
+
+/*
+ * Allow dangerous commands all the time, since we don't have a write protect
+ * switch.
+ */
+#define CONFIG_SYSTEM_UNLOCKED
+
+#ifndef __ASSEMBLER__
+
+/* Timer selection */
+#define TIM_CLOCK32 2
+#define TIM_ADC     3
+
+
+#include "gpio_signal.h"
+
+/* USB string indexes */
+enum usb_strings {
+	USB_STR_DESC = 0,
+	USB_STR_VENDOR,
+	USB_STR_PRODUCT,
+	USB_STR_SERIALNO,
+	USB_STR_VERSION,
+	USB_STR_I2C_NAME,
+	USB_STR_CONSOLE_NAME,
+	USB_STR_USART3_STREAM_NAME,
+	USB_STR_USART4_STREAM_NAME,
+	USB_STR_UPDATE_NAME,
+	USB_STR_COUNT
+};
+
+
+/* ADC signal */
+enum adc_channel {
+	ADC_CHG_CC1_PD,
+	ADC_CHG_CC2_PD,
+	ADC_DUT_CC1_PD,
+	ADC_DUT_CC2_PD,
+	ADC_SBU1_DET,
+	ADC_SBU2_DET,
+	ADC_SUB_C_REF,
+	/* Number of ADC channels */
+	ADC_CH_COUNT
+};
+
+/**
+ * Get board HW ID version
+ *
+ * @return HW ID version
+ */
+int board_get_version(void);
+#endif /* !__ASSEMBLER__ */
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/servo_v4p1/build.mk b/board/servo_v4p1/build.mk
new file mode 100644
index 0000000000..a38a31279d
--- /dev/null
+++ b/board/servo_v4p1/build.mk
@@ -0,0 +1,19 @@
+# -*- makefile -*-
+# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+
+# the IC is STmicro STM32F072RBT6
+CHIP:=stm32
+CHIP_FAMILY:=stm32f0
+CHIP_VARIANT:=stm32f07x
+
+# Not enough SRAM: Disable all tests
+test-list-y=
+
+# These files are compiled into RO and RW
+board-y=board.o
+
+all_deps=$(patsubst ro,,$(def_all_deps))
diff --git a/board/servo_v4p1/ec.tasklist b/board/servo_v4p1/ec.tasklist
new file mode 100644
index 0000000000..411353df5d
--- /dev/null
+++ b/board/servo_v4p1/ec.tasklist
@@ -0,0 +1,11 @@
+/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS,   hook_task,    NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE)
diff --git a/board/servo_v4p1/gpio.inc b/board/servo_v4p1/gpio.inc
new file mode 100644
index 0000000000..b42bde495b
--- /dev/null
+++ b/board/servo_v4p1/gpio.inc
@@ -0,0 +1,80 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifdef SECTION_IS_RO
+GPIO_INT(USB_DET_PP_CHG,	PIN(C, 13), GPIO_INT_BOTH, vbus0_evt)
+GPIO_INT(USB_DET_PP_DUT,	PIN(C, 12), GPIO_INT_BOTH, vbus1_evt)
+GPIO_INT(STM_FAULT_IRQ_L,	PIN(A, 8),  GPIO_INT_FALLING, tca_evt)
+GPIO_INT(DP_HPD,		PIN(A, 15), GPIO_INT_BOTH, dp_evt)
+GPIO_INT(CHGSRV_TCPC_INT_ODL,	PIN(C, 0),  GPIO_INT_FALLING, tcpc_evt)
+GPIO_INT(USBH_I2C_BUSY_INT,	PIN(C, 9),  GPIO_INT_FALLING, hub_evt)
+GPIO_INT(BC12_INT_ODL,		PIN(F, 1),  GPIO_INT_FALLING, bc12_evt)
+#endif /* SECTION_IS_RO */
+
+/* Outputs */
+GPIO(HOST_USB_HUB_RESET_L,	PIN(D, 2),  GPIO_ODR_HIGH)
+GPIO(FASTBOOT_DUTHUB_MUX_SEL,	PIN(B, 5),  GPIO_OUT_HIGH)
+GPIO(SBU_MUX_EN,		PIN(B, 6),  GPIO_OUT_LOW)
+GPIO(FASTBOOT_DUTHUB_MUX_EN_L,	PIN(B, 7),  GPIO_OUT_LOW)
+/* Power on init has reset asserted, we will pull the hub out of reset
+ * in the board init to help avoid brownout.
+ */
+GPIO(DUT_HUB_USB_RESET_L,	PIN(B, 9), GPIO_ODR_HIGH)
+GPIO(ATMEL_HWB_L,		PIN(B, 12), GPIO_OUT_HIGH)
+GPIO(USB3_A1_MUX_EN_L,		PIN(F, 0),  GPIO_OUT_HIGH)
+
+/* Inputs */
+
+/* Type-C */
+/* PD RX/TX */
+GPIO(USB_C_REF,			PIN(A, 1),  GPIO_ANALOG)
+GPIO(USB_CHG_CC1_MCU,		PIN(A, 2),  GPIO_ANALOG)
+GPIO(USB_CHG_CC2_MCU,		PIN(A, 4),  GPIO_ANALOG)
+GPIO(USB_DUT_CC1_MCU,		PIN(A, 0),  GPIO_ANALOG)
+GPIO(USB_DUT_CC2_MCU,		PIN(A, 5),  GPIO_ANALOG)
+
+GPIO(USB_CHG_CC1_TX_DATA,	PIN(B, 4),  GPIO_INPUT)
+GPIO(USB_CHG_CC2_TX_DATA,	PIN(A, 6),  GPIO_INPUT)
+GPIO(USB_DUT_CC1_TX_DATA,	PIN(B, 14), GPIO_INPUT)
+GPIO(USB_DUT_CC2_TX_DATA,	PIN(C, 2),  GPIO_INPUT)
+
+GPIO(USB_DUT_CC1_RPUSB,		PIN(C, 3),  GPIO_INPUT)
+GPIO(USB_DUT_CC1_RD,		PIN(C, 6),  GPIO_INPUT)
+GPIO(USB_DUT_CC1_RA,		PIN(C, 7),  GPIO_INPUT)
+GPIO(USB_DUT_CC1_RP3A0,		PIN(C, 14), GPIO_INPUT)
+GPIO(USB_DUT_CC1_RP1A5,		PIN(C, 15), GPIO_INPUT)
+
+GPIO(USB_DUT_CC2_RPUSB,		PIN(B, 0),  GPIO_INPUT)
+GPIO(USB_DUT_CC2_RD,		PIN(B, 1),  GPIO_INPUT)
+GPIO(USB_DUT_CC2_RA,		PIN(B, 2),  GPIO_INPUT)
+GPIO(USB_DUT_CC2_RP1A5,		PIN(C, 1),  GPIO_INPUT)
+GPIO(USB_DUT_CC2_RP3A0,		PIN(C, 8),  GPIO_INPUT)
+
+/* Alternate PD functions */
+GPIO(USB_CHG_TX_CLKOUT,       PIN(B, 8),  GPIO_INPUT)
+GPIO(USB_CHG_TX_CLKIN,        PIN(B, 3),  GPIO_INPUT)
+GPIO(USB_DUT_TX_CLKOUT,       PIN(B, 15), GPIO_INPUT)
+GPIO(USB_DUT_TX_CLKIN,        PIN(B, 13), GPIO_INPUT)
+
+/* I2C pins should be configured as inputs until I2C module is    */
+/* initialized. This will avoid driving the lines unintentionally.*/
+GPIO(MASTER_I2C_SCL,		PIN(B, 10), GPIO_INPUT)
+GPIO(MASTER_I2C_SDA,		PIN(B, 11), GPIO_INPUT)
+
+/* Unimplemented signals since we are not an EC */
+UNIMPLEMENTED(ENTERING_RW)
+UNIMPLEMENTED(WP_L)
+
+ALTERNATE(PIN_MASK(A, 0x0600), 1, MODULE_USART, 0) /* USART1: PA9/PA10 - Servo DBG UART1 */
+ALTERNATE(PIN_MASK(C, 0x0030), 1, MODULE_USART, 0) /* USART3: PC4/PC5 - Servo DUT UART3 */
+ALTERNATE(PIN_MASK(C, 0x0C00), 0, MODULE_USART, 0) /* USART4: PC10/PC11 - Servo UART4 */
+ALTERNATE(PIN_MASK(B, 0x0C00), 1, MODULE_I2C, GPIO_ODR_HIGH) /* I2C MASTER:PB10/11 */
+ALTERNATE(PIN_MASK(B, 0x0008), 0, MODULE_USB_PD, 0) /* SPI1_SCK:  PB3   */
+ALTERNATE(PIN_MASK(B, 0x2000), 0, MODULE_USB_PD, 0) /* SPI2_SCK:  PB13  */
+ALTERNATE(PIN_MASK(B, 0x0100), 2, MODULE_USB_PD, 0) /* TIM16_CH1: PB8   */
+ALTERNATE(PIN_MASK(B, 0x8000), 1, MODULE_USB_PD, 0) /* TIM15_CH2: PB15  */
+