chip/mt8192_scp: add dummy chip implementations

BRANCH=none
BUG=b:146213943
TEST=make buildall

Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org>
Change-Id: Ib5da01056c5624eae1efc14e64638c052f74c50c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2198817
Reviewed-by: Eric Yilun Lin <yllin@chromium.org>

9 files changed, 293 insertions, 0 deletions

diff --git a/chip/mt8192_scp/build.mk b/chip/mt8192_scp/build.mk
new file mode 100644
index 0000000000..1ad9f2ee27
--- /dev/null
+++ b/chip/mt8192_scp/build.mk
@@ -0,0 +1,19 @@
+# -*- makefile -*-
+# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# SCP specific files build
+#
+
+CORE:=riscv-rv32i
+
+# Required chip modules
+chip-y+=clock.o
+chip-y+=gpio.o
+chip-y+=intc.o
+chip-y+=system.o
+chip-y+=uart.o
+
+# Optional chip modules
+chip-$(CONFIG_COMMON_TIMER)+=hrtimer.o
diff --git a/chip/mt8192_scp/clock.c b/chip/mt8192_scp/clock.c
new file mode 100644
index 0000000000..c707e1340e
--- /dev/null
+++ b/chip/mt8192_scp/clock.c
@@ -0,0 +1,12 @@
+/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Clocks, PLL and power settings */
+
+#include "clock.h"
+
+void clock_init(void)
+{
+}
diff --git a/chip/mt8192_scp/config_chip.h b/chip/mt8192_scp/config_chip.h
new file mode 100644
index 0000000000..9e87d2687f
--- /dev/null
+++ b/chip/mt8192_scp/config_chip.h
@@ -0,0 +1,55 @@
+/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_CONFIG_CHIP_H
+#define __CROS_EC_CONFIG_CHIP_H
+
+#include "core/riscv-rv32i/config_core.h"
+
+/* Interval between HOOK_TICK notifications */
+#define HOOK_TICK_INTERVAL_MS 500
+#define HOOK_TICK_INTERVAL    (HOOK_TICK_INTERVAL_MS * MSEC)
+
+/* RW only, no flash */
+#undef  CONFIG_FW_INCLUDE_RO
+#define CONFIG_RO_MEM_OFF 0
+#define CONFIG_RO_SIZE 0
+#define CONFIG_RW_MEM_OFF 0
+#define CONFIG_RW_SIZE 0x40000 /* 256KB */
+#define CONFIG_EC_WRITABLE_STORAGE_OFF 0
+#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
+#define CONFIG_RO_STORAGE_OFF 0
+#define CONFIG_RW_STORAGE_OFF 0
+#define CONFIG_PROGRAM_MEMORY_BASE 0
+#define CONFIG_MAPPED_STORAGE_BASE 0
+
+/* Unsupported features/commands */
+#undef CONFIG_CMD_FLASHINFO
+#undef CONFIG_CMD_POWER_AP
+#undef CONFIG_FLASH
+#undef CONFIG_FLASH_PHYSICAL
+#undef CONFIG_FMAP
+#undef CONFIG_HIBERNATE
+#undef CONFIG_LID_SWITCH
+
+/* Task stack size */
+#define CONFIG_STACK_SIZE 1024
+#define IDLE_TASK_STACK_SIZE 256
+#define SMALLER_TASK_STACK_SIZE 384
+#define TASK_STACK_SIZE 488
+#define LARGER_TASK_STACK_SIZE 640
+#define VENTI_TASK_STACK_SIZE 768
+
+/* TODO: need to confirm, placeholder */
+#define GPIO_PIN(num) ((num) / 32), ((num) % 32)
+#define GPIO_PIN_MASK(p, m) .port = (p), .mask = (m)
+#undef CONFIG_TASK_PROFILING
+/* TODO: not yet supported */
+#undef CONFIG_WATCHDOG
+#undef CONFIG_MPU
+/* TODO: core/riscv-rv32i pollution */
+#define __ram_code
+
+#endif /* __CROS_EC_CONFIG_CHIP_H */
diff --git a/chip/mt8192_scp/gpio.c b/chip/mt8192_scp/gpio.c
new file mode 100644
index 0000000000..0ca3e3ac25
--- /dev/null
+++ b/chip/mt8192_scp/gpio.c
@@ -0,0 +1,21 @@
+/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* GPIO module */
+
+#include "gpio.h"
+
+void gpio_pre_init(void)
+{
+}
+
+test_mockable int gpio_get_level(enum gpio_signal signal)
+{
+	return 0;
+}
+
+void gpio_set_level(enum gpio_signal signal, int value)
+{
+}
diff --git a/chip/mt8192_scp/hrtimer.c b/chip/mt8192_scp/hrtimer.c
new file mode 100644
index 0000000000..22c68177be
--- /dev/null
+++ b/chip/mt8192_scp/hrtimer.c
@@ -0,0 +1,39 @@
+/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * High-res hardware timer
+ *
+ * SCP hardware 32bit count down timer can be configured to source clock from
+ * 32KHz, 26MHz, BCLK or PCLK. This implementation selects BCLK (ULPOSC1/8) as a
+ * source, countdown mode and converts to micro second value matching common
+ * timer.
+ */
+
+#include "common.h"
+#include "hwtimer.h"
+
+int __hw_clock_source_init(uint32_t start_t)
+{
+	return 0;
+}
+
+uint32_t __hw_clock_source_read(void)
+{
+	return 0;
+}
+
+uint32_t __hw_clock_event_get(void)
+{
+	return 0;
+}
+
+void __hw_clock_event_clear(void)
+{
+}
+
+void __hw_clock_event_set(uint32_t deadline)
+{
+}
diff --git a/chip/mt8192_scp/intc.c b/chip/mt8192_scp/intc.c
new file mode 100644
index 0000000000..25dfb32735
--- /dev/null
+++ b/chip/mt8192_scp/intc.c
@@ -0,0 +1,40 @@
+/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* INTC control module */
+
+int chip_get_ec_int(void)
+{
+	return 0;
+}
+
+int chip_get_intc_group(int irq)
+{
+	return 0;
+}
+
+int chip_enable_irq(int irq)
+{
+	return 0;
+}
+
+int chip_disable_irq(int irq)
+{
+	return 0;
+}
+
+int chip_clear_pending_irq(int irq)
+{
+	return 0;
+}
+
+int chip_trigger_irq(int irq)
+{
+	return 0;
+}
+
+void chip_init_irqs(void)
+{
+}
diff --git a/chip/mt8192_scp/registers.h b/chip/mt8192_scp/registers.h
new file mode 100644
index 0000000000..9c27eb4f99
--- /dev/null
+++ b/chip/mt8192_scp/registers.h
@@ -0,0 +1,16 @@
+/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Register map */
+
+#ifndef __CROS_EC_REGISTERS_H
+#define __CROS_EC_REGISTERS_H
+
+#include "common.h"
+#include "compile_time_macros.h"
+
+#define DUMMY_GPIO_BANK 0
+
+#endif /* __CROS_EC_REGISTERS_H */
diff --git a/chip/mt8192_scp/system.c b/chip/mt8192_scp/system.c
new file mode 100644
index 0000000000..044e6bc4e2
--- /dev/null
+++ b/chip/mt8192_scp/system.c
@@ -0,0 +1,39 @@
+/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* System : hardware specific implementation */
+
+#include "system.h"
+
+void system_pre_init(void)
+{
+}
+
+void system_reset(int flags)
+{
+	while (1)
+		;
+}
+
+int system_get_bbram(enum system_bbram_idx idx, uint8_t *value)
+{
+	return EC_ERROR_INVAL;
+}
+
+const char *system_get_chip_vendor(void)
+{
+	return "mtk";
+}
+
+const char *system_get_chip_name(void)
+{
+	/* Support only SCP_A for now */
+	return "scp_a";
+}
+
+const char *system_get_chip_revision(void)
+{
+	return "";
+}
diff --git a/chip/mt8192_scp/uart.c b/chip/mt8192_scp/uart.c
new file mode 100644
index 0000000000..960e42944d
--- /dev/null
+++ b/chip/mt8192_scp/uart.c
@@ -0,0 +1,52 @@
+/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* SCP UART module */
+
+#include "uart.h"
+
+void uart_init(void)
+{
+}
+
+int uart_init_done(void)
+{
+	return 0;
+}
+
+void uart_tx_flush(void)
+{
+}
+
+int uart_tx_ready(void)
+{
+	return 0;
+}
+
+int uart_rx_available(void)
+{
+	return 0;
+}
+
+void uart_write_char(char c)
+{
+}
+
+int uart_read_char(void)
+{
+	return 0;
+}
+
+void uart_tx_start(void)
+{
+}
+
+void uart_tx_stop(void)
+{
+}
+
+void uart_process(void)
+{
+}