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| author | Tim Lin <tim2.lin@ite.corp-partner.google.com> | 2021-07-17 08:34:46 +0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-08-30 15:47:17 +0000 |
| commit | 1f8be41fecffa454885f2b06bd9daf312ed4e37b (patch) | |
| tree | 4fb3d6810e7b3ffc08a822159b9de5db0c2c67b2 | |
| parent | 01ca8a6f2ff363a8a370870c3c6e58d364212b20 (diff) | |
| download | chrome-ec-1f8be41fecffa454885f2b06bd9daf312ed4e37b.tar.gz | |
zephyr/drivers: it8xxx2: add hard reset in cros_system driver
This reset cause is power-on reset by enabling ETWD HW reset.
BUG=b:185202623
BRANCH=none
TEST=console command: reboot hard
21-08-20 10:53:02.198 --- UART initialized after reboot ---
21-08-20 10:53:02.198 [Image: RO, asurada_zephyr_v2.0.10073+ed882 2021-08-20 10:33:]
21-08-20 10:53:02.209 [Reset cause: power-on hard]
Change-Id: Iabe71305ef16ab04160a85e86398ef037ad1eba6
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3108847
Commit-Queue: Denis Brockus <dbrockus@chromium.org>
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
| -rw-r--r-- | zephyr/drivers/cros_system/cros_system_it8xxx2.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/zephyr/drivers/cros_system/cros_system_it8xxx2.c b/zephyr/drivers/cros_system/cros_system_it8xxx2.c index 922a88d826..e058fa6980 100644 --- a/zephyr/drivers/cros_system/cros_system_it8xxx2.c +++ b/zephyr/drivers/cros_system/cros_system_it8xxx2.c @@ -116,18 +116,26 @@ static int cros_system_it8xxx2_get_reset_cause(const struct device *dev) static int cros_system_it8xxx2_init(const struct device *dev) { - ARG_UNUSED(dev); + struct gctrl_it8xxx2_regs *const gctrl_base = GCTRL_IT8XXX2_REG_BASE; + + /* System triggers a soft reset by default (command: reboot). */ + gctrl_base->GCTRL_ETWDUARTCR &= ~IT8XXX2_GCTRL_ETWD_HW_RST_EN; return 0; } static int cros_system_it8xxx2_soc_reset(const struct device *dev) { + struct gctrl_it8xxx2_regs *const gctrl_base = GCTRL_IT8XXX2_REG_BASE; struct wdt_it8xxx2_regs *const wdt_base = WDT_IT8XXX2_REG_BASE; + uint32_t chip_reset_flags = chip_read_reset_flags(); /* Disable interrupts to avoid task swaps during reboot. */ interrupt_disable_all(); + if (chip_reset_flags & EC_RESET_FLAG_HARD) + gctrl_base->GCTRL_ETWDUARTCR |= IT8XXX2_GCTRL_ETWD_HW_RST_EN; + /* * Writing invalid key to watchdog module triggers a soft or hardware * reset. It depends on the setting of bit0 at ETWDUARTCR register. |