diff options
| author | Mary Ruthven <mruthven@chromium.org> | 2021-08-18 15:14:27 -0500 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-08-19 15:26:33 +0000 |
| commit | 5db45a1e5e122ab1098eeb8cd61176e0837809f6 (patch) | |
| tree | 972eab1dc7fd8673d0895ce602471d1ddeebd5df | |
| parent | 4de87085a2da49887ac90aae9df571afa84168f6 (diff) | |
| download | chrome-ec-5db45a1e5e122ab1098eeb8cd61176e0837809f6.tar.gz | |
tpm_mode: move s_tpm_mode to .bss.Tpm2_common
Move tpm_mode_s to .bss.Tpm2_common, so TPM_MODE_ENABLED is cleared
during tpm reset events.
Cr50 still clears TPM_MODE_DISABLED by doing a hard reset instead of
triggering a tpm reset event.
BUG=b:191180387,b:196820239
TEST=run firmawre_Cr50TpmMode
Change-Id: I5f5cedb7b5b6a03bf504583c378fae87896cef2b
Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3105485
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
| -rw-r--r-- | board/cr50/tpm2/tpm_mode.c | 18 |
1 files changed, 12 insertions, 6 deletions
diff --git a/board/cr50/tpm2/tpm_mode.c b/board/cr50/tpm2/tpm_mode.c index 3049ab840c..8b83081e88 100644 --- a/board/cr50/tpm2/tpm_mode.c +++ b/board/cr50/tpm2/tpm_mode.c @@ -32,17 +32,23 @@ static void disable_tpm(void) DECLARE_DEFERRED(disable_tpm); /* - * tpm_mode can be set only once after a hardware reset, to either - * TPM_MODE_ENABLED or TPM_MODE_DISABLED. + * Set TPM mode to TPM_MODE_ENABLED or TPM_MODE_DISABLED once per tpm reset. * - * This allows the AP to make sure that TPM can't be disabled by setting mode - * to TPM_MODE_ENABLED during start up. + * If mode is set to TPM_MODE_ENABLED, it can't be set to DISABLED until the + * AP resets. * * If mode is set to TPM_MODE_DISABLED, the AP loses the ability to * communicate with the TPM until next TPM reset (which will trigger the H1 - * hardware reset in that case). + * hardware reset in that case). Resetting the TPM will clear tpm_mode field and + * enable AP communication, but the TPM will not be fully operational until the + * crypto hardware is restarted. That's why a full Cr50 reboot is required to + * restore TPM operation. + * + * On TPM reset event, tpm_reset_now() in tpm_registers.c clears TPM2 BSS memory + * area. By placing s_tpm_mode in TPM2 BSS area, TPM mode value shall be + * "TPM_MODE_ENABLED_TENTATIVE" on every TPM reset events. */ -static enum tpm_modes s_tpm_mode; +static enum tpm_modes s_tpm_mode __attribute__((section(".bss.Tpm2_common"))); static enum vendor_cmd_rc process_tpm_mode(struct vendor_cmd_params *p) { |