zephyr: guybrush: Bringup power sequencing

Bringup power sequencing for AMD and enable for guybrush.

Note that at the moment we had to copy-paste the power signals and
related funcitons, the code was a bit too far from shimming without
extensive editing.  We can try and merge together later.

BUG=b:195137794
BRANCH=none
TEST=power sequence to S0, nothing useful on ap console (yet!)

Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I9a577e24d80fe0ff992af4b847e14695b82f871d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3169568
Reviewed-by: Diana Z <dzigterman@chromium.org>

8 files changed, 184 insertions, 7 deletions

diff --git a/zephyr/CMakeLists.txt b/zephyr/CMakeLists.txt
index 4e3294220e..cb85bf2154 100644
--- a/zephyr/CMakeLists.txt
+++ b/zephyr/CMakeLists.txt
@@ -115,6 +115,8 @@ zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC "${PLATFORM_EC}/common/base32.c"
 
 # Now include files that depend on or relate to other CONFIG options, sorted by
 # CONFIG
+zephyr_library_sources_ifdef(CONFIG_HAS_TASK_POWERBTN
+                                                "${PLATFORM_EC}/common/power_button_x86.c")
 zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_ACCEL_BMA255
                                                 "${PLATFORM_EC}/driver/accel_bma2x2.c"
                                                 "${PLATFORM_EC}/common/math_util.c")
@@ -253,12 +255,13 @@ zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_POWER_BUTTON
                                                 "${PLATFORM_EC}/common/power_button.c")
 zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_POWERSEQ
                                                 "${PLATFORM_EC}/power/common.c")
+zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_POWERSEQ_AMD
+                                                "${PLATFORM_EC}/power/amd_x86.c")
 zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_POWERSEQ_COMETLAKE
                                                 "${PLATFORM_EC}/power/cometlake.c")
 zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_POWERSEQ_ICELAKE
                                                 "${PLATFORM_EC}/power/icelake.c")
 zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_POWERSEQ_INTEL
-                                                "${PLATFORM_EC}/common/power_button_x86.c"
                                                 "${PLATFORM_EC}/power/intel_x86.c")
 zephyr_library_sources_ifdef(CONFIG_PLATFORM_EC_POWERSEQ_HOST_SLEEP
                                                 "${PLATFORM_EC}/power/host_sleep.c")
diff --git a/zephyr/Kconfig.powerseq b/zephyr/Kconfig.powerseq
index 89a2d5729e..0045a69ad8 100644
--- a/zephyr/Kconfig.powerseq
+++ b/zephyr/Kconfig.powerseq
@@ -44,11 +44,31 @@ config PLATFORM_EC_HOSTCMD_AP_RESET
 
 config PLATFORM_EC_POWERSEQ_PP5000_CONTROL
 	bool "Enable a task-safe way to control the PP5000 rail"
+	depends on !AP_X86_AMD
 	default y
 	help
 	  Guard access to the PP5000 GPIO using mutex locks, allowing
 	  the rail to be changed in a task-safe manner.
 
+menuconfig PLATFORM_EC_POWERSEQ_AMD
+	bool "AMD power sequencing"
+	depends on AP_X86_AMD
+	select HAS_TASK_POWERBTN
+	default y
+	help
+	  Enable AMD power sequencing code.
+
+if PLATFORM_EC_POWERSEQ_AMD
+
+config PLATFORM_EC_POWER_BUTTON_TO_PCH_CUSTOM
+	bool "Custom board_pwrbtn_to_pch"
+	help
+	  The board support code provides a custom function,
+	  board_pwrbtn_to_pch, that replaces the standard GPIO set
+	  level to the SoC.
+
+endif  # PLATFORM_EC_POWERSEQ_AMD
+
 menuconfig PLATFORM_EC_POWERSEQ_INTEL
 	bool "Enable shimming common Intel power sequencing code"
 	depends on AP_X86_INTEL
diff --git a/zephyr/dts/bindings/gpio/gpio-enum-name.yaml b/zephyr/dts/bindings/gpio/gpio-enum-name.yaml
index aa4a01dd3d..b7fc3809ac 100644
--- a/zephyr/dts/bindings/gpio/gpio-enum-name.yaml
+++ b/zephyr/dts/bindings/gpio/gpio-enum-name.yaml
@@ -56,9 +56,11 @@ properties:
       - GPIO_EC_INT_L
       - GPIO_EC_PCH_SYS_PWROK
       - GPIO_EC_PCH_WAKE_ODL
+      - GPIO_EC_PCORE_INT_ODL
       - GPIO_EC_PMIC_EN_ODL
       - GPIO_EC_PMIC_WATCHDOG_L
       - GPIO_EC_PROCHOT_IN_L
+      - GPIO_EC_PWR_BTN_ODL
       - GPIO_EC_RST_ODL
       - GPIO_EC_WP_L
       - GPIO_EC_X_GPIO1
@@ -75,6 +77,9 @@ properties:
       - GPIO_EN_PP5000_USB_A0_VBUS
       - GPIO_EN_PP5000_USBA
       - GPIO_EN_PPVAR_VCCIN
+      - GPIO_EN_PWR_A
+      - GPIO_EN_PWR_PCORE_S0_R
+      - GPIO_EN_PWR_S0_R
       - GPIO_EN_SLP_Z
       - GPIO_EN_USB_A_5V
       - GPIO_ENABLE_BACKLIGHT
@@ -100,11 +105,14 @@ properties:
       - GPIO_PCH_SLP_S0_L
       - GPIO_PCH_SLP_S3_L
       - GPIO_PCH_SLP_S4_L
+      - GPIO_PCH_SLP_S5_L
       - GPIO_PCH_SLP_SUS_L
       - GPIO_PCH_SYS_PWROK
       - GPIO_PG_EC_ALL_SYS_PWRGD
       - GPIO_PG_EC_DSW_PWROK
       - GPIO_PG_EC_RSMRST_ODL
+      - GPIO_PG_GROUPC_S0_OD
+      - GPIO_PG_LPDDR4X_S3_OD
       - GPIO_PG_MT6360_ODL
       - GPIO_PG_MT6315_GPU_ODL
       - GPIO_PG_MT6315_PROC_ODL
@@ -119,6 +127,8 @@ properties:
       - GPIO_PS_HOLD
       - GPIO_QSIP_ON
       - GPIO_RSMRST_L_PGOOD
+      - GPIO_S0_PGOOD
+      - GPIO_S5_PGOOD
       - GPIO_SET_VMC_VOLT_AT_1V8
       - GPIO_SKU_ID0
       - GPIO_SKU_ID1
diff --git a/zephyr/projects/guybrush/CMakeLists.txt b/zephyr/projects/guybrush/CMakeLists.txt
index 8bec336ebb..b565aad308 100644
--- a/zephyr/projects/guybrush/CMakeLists.txt
+++ b/zephyr/projects/guybrush/CMakeLists.txt
@@ -13,3 +13,5 @@ set(PLATFORM_EC_BASEBOARD "${PLATFORM_EC}/baseboard/guybrush" CACHE PATH
   "Path to the platform/ec baseboard directory")
 set(PLATFORM_EC_BOARD "${PLATFORM_EC}/board/guybrush" CACHE PATH
   "Path to the platform/ec board directory")
+
+zephyr_library_sources("power_signals.c")
diff --git a/zephyr/projects/guybrush/gpio.dts b/zephyr/projects/guybrush/gpio.dts
index 60f8be941e..430d4c3755 100644
--- a/zephyr/projects/guybrush/gpio.dts
+++ b/zephyr/projects/guybrush/gpio.dts
@@ -23,26 +23,32 @@
 		ec_pwr_btn_odl {
 			gpios = <&gpio0 1 GPIO_INPUT>;
 			label = "EC_PWR_BTN_ODL";
+			enum-name = "GPIO_EC_PWR_BTN_ODL";
 		};
 		slp_s3_l {
 			gpios = <&gpio6 1 GPIO_INPUT>;
 			label = "SLP_S3_L";
+			enum-name = "GPIO_PCH_SLP_S3_L";
 		};
 		slp_s5_l {
 			gpios = <&gpio7 2 GPIO_INPUT>;
 			label = "SLP_S5_L";
+			enum-name = "GPIO_PCH_SLP_S5_L";
 		};
 		slp_s3_s0i3_l {
 			gpios = <&gpio7 4 GPIO_INPUT>;
 			label = "SLP_S3_S0I3_L";
+			enum-name = "GPIO_PCH_SLP_S0_L";
 		};
 		pg_pwr_s5 {
 			gpios = <&gpioc 0 GPIO_INPUT>;
 			label = "PG_PWR_S5";
+			enum-name = "GPIO_S5_PGOOD";
 		};
 		pg_pcore_s0_r_od {
 			gpios = <&gpiob 6 GPIO_INPUT>;
 			label = "PG_PCORE_S0_R_OD";
+			enum-name = "GPIO_S0_PGOOD";
 		};
 		acok_od {
 			gpios = <&gpio0 0 GPIO_INPUT>;
@@ -52,26 +58,32 @@
 		ec_pcore_int_odl {
 			gpios = <&gpiof 0 (GPIO_INPUT | GPIO_PULL_UP)>;
 			label = "EC_PCORE_INT_ODL";
+			enum-name = "GPIO_EC_PCORE_INT_ODL";
 		};
 		pg_groupc_s0_od {
 			gpios = <&gpioa 3 GPIO_INPUT>;
 			label = "PG_GROUPC_S0_OD";
+			enum-name = "GPIO_PG_GROUPC_S0_OD";
 		};
 		pg_lpddr4x_s3_od {
 			gpios = <&gpio9 5 GPIO_INPUT>;
 			label = "PG_LPDDR4X_S3_OD";
+			enum-name = "GPIO_PG_LPDDR4X_S3_OD";
 		};
 		en_pwr_s5 {
 			gpios = <&gpiob 7 GPIO_OUT_LOW>;
 			label = "EN_PWR_S5";
+			enum-name = "GPIO_EN_PWR_A";
 		};
 		en_pwr_s0_r {
 			gpios = <&gpiof 1 GPIO_OUT_LOW>;
 			label = "EN_PWR_S0_R";
+			enum-name = "GPIO_EN_PWR_S0_R";
 		};
 		en_pwr_pcore_s0_r {
 			gpios = <&gpioe 1 GPIO_OUT_LOW>;
 			label = "EN_PWR_PCORE_S0_R";
+			enum-name = "GPIO_EN_PWR_PCORE_S0_R";
 		};
 		ec_entering_rw {
 			gpios = <&gpio6 6 GPIO_OUT_LOW>;
@@ -81,10 +93,12 @@
 		ec_sys_rst_l {
 			gpios = <&gpio7 6 GPIO_ODR_HIGH>;
 			label = "EC_SYS_RST_L";
+			enum-name = "GPIO_SYS_RESET_L";
 		};
 		ec_soc_rsmrst_l {
 			gpios = <&gpioc 5 GPIO_OUT_LOW>;
 			label = "EC_SOC_RSMRST_L";
+			enum-name = "GPIO_PCH_RSMRST_L";
 		};
 		ec_clr_cmos {
 			gpios = <&gpioa 1 GPIO_OUT_LOW>;
@@ -97,10 +111,12 @@
 		ec_soc_pwr_btn_l {
 			gpios = <&gpio6 3 GPIO_OUT_HIGH>;
 			label = "EC_SOC_PWR_BTN_L";
+			enum-name = "GPIO_PCH_PWRBTN_L";
 		};
 		ec_soc_pwr_good {
 			gpios = <&gpiod 3 GPIO_OUT_LOW>;
 			label = "EC_SOC_PWR_GOOD";
+			enum-name = "GPIO_PCH_SYS_PWROK";
 		};
 		ec_soc_wake_l {
 			gpios = <&gpio0 3 GPIO_OUT_HIGH>;
@@ -114,6 +130,7 @@
 		prochot_odl {
 			gpios = <&gpiod 5 GPIO_ODR_HIGH>;
 			label = "PROCHOT_ODL";
+			enum-name = "GPIO_CPU_PROCHOT";
 		};
 		soc_alert_ec_l {
 			gpios = <&gpioe 2 GPIO_INPUT>;
diff --git a/zephyr/projects/guybrush/include/gpio_map.h b/zephyr/projects/guybrush/include/gpio_map.h
index 668bb5a0ba..3f1a7dd94a 100644
--- a/zephyr/projects/guybrush/include/gpio_map.h
+++ b/zephyr/projects/guybrush/include/gpio_map.h
@@ -9,6 +9,19 @@
 #include <devicetree.h>
 #include <gpio_signal.h>
 
+/* Power input signals */
+enum power_signal {
+	X86_SLP_S0_N, /* SOC  -> SLP_S3_S0I3_L */
+	X86_SLP_S3_N, /* SOC  -> SLP_S3_L */
+	X86_SLP_S5_N, /* SOC  -> SLP_S5_L */
+
+	X86_S0_PGOOD, /* PMIC -> S0_PWROK_OD */
+	X86_S5_PGOOD, /* PMIC -> S5_PWROK */
+
+	/* Number of X86 signals */
+	POWER_SIGNAL_COUNT,
+};
+
 /*
  * Set EC_CROS_GPIO_INTERRUPTS to a space-separated list of GPIO_INT items.
  *
@@ -24,10 +37,25 @@
  * #define EC_CROS_GPIO_INTERRUPTS \
  *   GPIO_INT(NAMED_GPIO(h1_ec_pwr_btn_odl), GPIO_INT_EDGE_BOTH, button_print)
  */
-#define EC_CROS_GPIO_INTERRUPTS                                           \
-	GPIO_INT(GPIO_LID_OPEN, GPIO_INT_EDGE_BOTH, lid_interrupt)        \
-	GPIO_INT(GPIO_AC_PRESENT, GPIO_INT_EDGE_BOTH, extpower_interrupt) \
-	GPIO_INT(GPIO_POWER_BUTTON_L, GPIO_INT_EDGE_BOTH,                 \
-		 power_button_interrupt)
+#define EC_CROS_GPIO_INTERRUPTS                                              \
+	GPIO_INT(GPIO_LID_OPEN, GPIO_INT_EDGE_BOTH, lid_interrupt)           \
+	GPIO_INT(GPIO_AC_PRESENT, GPIO_INT_EDGE_BOTH, extpower_interrupt)    \
+	GPIO_INT(GPIO_POWER_BUTTON_L, GPIO_INT_EDGE_BOTH,                    \
+		 power_button_interrupt)                                     \
+	GPIO_INT(GPIO_EC_PWR_BTN_ODL, GPIO_INT_EDGE_BOTH,                    \
+		 power_button_interrupt)                                     \
+	GPIO_INT(GPIO_PCH_SLP_S3_L, GPIO_INT_EDGE_BOTH, baseboard_en_pwr_s0) \
+	GPIO_INT(GPIO_PCH_SLP_S5_L, GPIO_INT_EDGE_BOTH,                      \
+		 power_signal_interrupt)                                     \
+	GPIO_INT(GPIO_PCH_SLP_S0_L, GPIO_INT_EDGE_BOTH,                      \
+		 power_signal_interrupt)                                     \
+	GPIO_INT(GPIO_S5_PGOOD, GPIO_INT_EDGE_BOTH, extpower_interrupt)      \
+	GPIO_INT(GPIO_S0_PGOOD, GPIO_INT_EDGE_BOTH, power_signal_interrupt)  \
+	GPIO_INT(GPIO_EC_PCORE_INT_ODL, GPIO_INT_EDGE_BOTH,                  \
+		 power_signal_interrupt)                                     \
+	GPIO_INT(GPIO_PG_GROUPC_S0_OD, GPIO_INT_EDGE_BOTH,                   \
+		 baseboard_en_pwr_pcore_s0)                                  \
+	GPIO_INT(GPIO_PG_LPDDR4X_S3_OD, GPIO_INT_EDGE_BOTH,                  \
+		 baseboard_en_pwr_pcore_s0)
 
 #endif /* __ZEPHYR_GPIO_MAP_H */
diff --git a/zephyr/projects/guybrush/power_signals.c b/zephyr/projects/guybrush/power_signals.c
new file mode 100644
index 0000000000..7d5781d0cb
--- /dev/null
+++ b/zephyr/projects/guybrush/power_signals.c
@@ -0,0 +1,95 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "chipset.h"
+#include "config.h"
+#include "gpio.h"
+#include "power.h"
+#include "timer.h"
+
+/* Wake Sources */
+const enum gpio_signal hibernate_wake_pins[] = {
+	GPIO_LID_OPEN,
+	GPIO_AC_PRESENT,
+	GPIO_POWER_BUTTON_L,
+};
+const int hibernate_wake_pins_used =  ARRAY_SIZE(hibernate_wake_pins);
+
+/* Power Signal Input List */
+const struct power_signal_info power_signal_list[] = {
+	[X86_SLP_S0_N] = {
+		.gpio = GPIO_PCH_SLP_S0_L,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "SLP_S0_DEASSERTED",
+	},
+	[X86_SLP_S3_N] = {
+		.gpio = GPIO_PCH_SLP_S3_L,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "SLP_S3_DEASSERTED",
+	},
+	[X86_SLP_S5_N] = {
+		.gpio = GPIO_PCH_SLP_S5_L,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "SLP_S5_DEASSERTED",
+	},
+	[X86_S0_PGOOD] = {
+		.gpio = GPIO_S0_PGOOD,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "S0_PGOOD",
+	},
+	[X86_S5_PGOOD] = {
+		.gpio = GPIO_S5_PGOOD,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "S5_PGOOD",
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
+
+/**
+ * b/175324615: On G3->S5, wait for RSMRST_L to be deasserted before asserting
+ * PCH_PWRBTN_L.
+ */
+void board_pwrbtn_to_pch(int level)
+{
+	timestamp_t start;
+	const uint32_t timeout_rsmrst_rise_us = 30 * MSEC;
+
+	/* Add delay for G3 exit if asserting PWRBTN_L and RSMRST_L is low. */
+	if (!level && !gpio_get_level(GPIO_PCH_RSMRST_L)) {
+		start = get_time();
+		do {
+			usleep(200);
+			if (gpio_get_level(GPIO_PCH_RSMRST_L))
+				break;
+		} while (time_since32(start) < timeout_rsmrst_rise_us);
+
+		if (!gpio_get_level(GPIO_PCH_RSMRST_L))
+			ccprints("Error pwrbtn: RSMRST_L still low");
+
+		msleep(16);
+	}
+	gpio_set_level(GPIO_PCH_PWRBTN_L, level);
+}
+
+void baseboard_en_pwr_pcore_s0(enum gpio_signal signal)
+{
+
+	/* EC must AND signals PG_LPDDR4X_S3_OD and PG_GROUPC_S0_OD */
+	gpio_set_level(GPIO_EN_PWR_PCORE_S0_R,
+		       gpio_get_level(GPIO_PG_LPDDR4X_S3_OD) &&
+		       gpio_get_level(GPIO_PG_GROUPC_S0_OD));
+}
+
+void baseboard_en_pwr_s0(enum gpio_signal signal)
+{
+
+	/* EC must AND signals SLP_S3_L and PG_PWR_S5 */
+	gpio_set_level(GPIO_EN_PWR_S0_R,
+		       gpio_get_level(GPIO_PCH_SLP_S3_L) &&
+		       gpio_get_level(GPIO_S5_PGOOD));
+
+	/* Now chain off to the normal power signal interrupt handler. */
+	power_signal_interrupt(signal);
+}
diff --git a/zephyr/projects/guybrush/prj.conf b/zephyr/projects/guybrush/prj.conf
index 8dc54c4c86..73ce8ba715 100644
--- a/zephyr/projects/guybrush/prj.conf
+++ b/zephyr/projects/guybrush/prj.conf
@@ -18,10 +18,12 @@ CONFIG_PLATFORM_EC_VBOOT_EFS2=n
 # Power sequencing
 CONFIG_AP=y
 CONFIG_AP_X86_AMD=y
+CONFIG_PLATFORM_EC_POWERSEQ=y
+CONFIG_PLATFORM_EC_POWER_BUTTON_TO_PCH_CUSTOM=y
+CONFIG_PLATFORM_EC_PORT80=y
 
 # Power button
 CONFIG_PLATFORM_EC_POWER_BUTTON=y
-CONFIG_HAS_TASK_POWERBTN=n
 
 # External power
 CONFIG_PLATFORM_EC_HOSTCMD=y